MB90598GPF-G-152-JNE1

The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB90598G/F598G/V595G F2MC-16LX MB90595G Series CMOS 16-bit Proprietary Microcontroller The MB90595G series with FULL-CAN interface and FLASH ROM is especially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional instruction sets for highlevel languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90595G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)) and stepping motor controller. Features ■ ■ ■ Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions ■ Program patch function (for two address pointers) ■ Enhanced execution speed: 4-byte instruction queue ■ Enhanced interrupt function: 8 levels, 34 factors ■ Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 10 channels ■ Embedded ROM size and types Mask ROM: 128 Kbytes Flash ROM: 128 Kbytes Embedded RAM size: 4 Kbytes (MB90595G: 6 Kbytes) ■ Flash ROM Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector Erase can be performed on each block Block protection with external programming voltage ■ Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) Cypress Semiconductor Corporation Document Number: 002-07700 Rev. *B • CPU intermittent operation mode Hardware stand-by mode ■ Process: 0.5 m CMOS technology ■ I/O port General-purpose I/O ports: 78 ports Push-pull output and Schmitt trigger input. Programmable on each bit as I/O or signal for peripherals. ■ Timer Watchdog timer: 1 channel 8/16-bit PPG timer: 8/16-bit  6 channels 16-bit re-load timer: 2 channels ■ 16-bit I/O timer 16-bit Free-run timer: 1 channel Input capture: 4 channels Output compare: 4 channels ■ Extended I/O serial interface: 1 channel ■ UART0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. ■ UART1 (SCI) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial transmission (I/O extended transmission) can be selectively used. ■ Stepping motor controller (4 channels) ■ External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. ■ Delayed interrupt generation module: Generates an interrupt request for switching tasks. ■ 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. ■ FULL-CAN interface: 1 channel Conforming to Version 2.0 Part A and Part B Flexible message buffering (mailbox and FIFO buffering can be mixed) ■ 18-bit Time-base counter ■ External bus interface: Maximum address space 16 Mbytes 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 6, 2018 MB90595G Series Contents Product Lineup ................................................................. 3 Pin Assignment ................................................................ 5 Pin Description ................................................................. 6 I/O Circuit Type ................................................................. 8 Handling Devices ............................................................ 11 Block Diagram ............................................................... 14 Memory Space ................................................................ 15 I/O Map ............................................................................. 16 Can Controller ................................................................. 23 List of Control Registers ............................................ 23 List of Message Buffers (ID Registers) ...................... 24 List of Message Buffers (DLC Registers and Data Registers) ......................................................... 27 Interrupt Source, Interrupt Vector, and Interrupt Control Register ............................................................. 29 Document Number: 002-07700 Rev. *B Electrical Characteristics ............................................... 31 Absolute Maximum Ratings ....................................... 31 Recommended Conditions ........................................ 33 DC Characteristics .................................................... 33 AC Characteristics ..................................................... 35 A/D Converter ............................................................ 42 A/D Converter Glossary ............................................ 44 Notes on Using A/D Converter .................................. 45 Flash memory ............................................................ 46 Example Characteristics ................................................ 47 Ordering Information ...................................................... 49 Package Dimensions ...................................................... 50 Major Changes ................................................................ 51 Page 2 of 52 MB90595G Series 1. Product Lineup Features MB90598G MB90F598G MB90V595G Mask ROM product Flash ROM product Evaluation product ROM size 128 Kbytes 128 Kbytes Boot block Hard-wired reset vector None RAM size 4 Kbytes 4 Kbytes 6 Kbytes Classification  Emulator-specific power supply *1 None CPU functions The number of instructions: 351 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz) Interrupt processing time: 1.5 s (at machine clock frequency of 16 MHz, minimum value) UART0 Clock synchronized transmission (500 K/1 M/2 Mbps) Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500 /500000 bps at machine clock frequency of 16 MHz) Transmission can be performed by bi-directional serial transmission or by master/slave connection. UART1(SCI) Clock synchronized transmission (62.5 K/125 K/250 K/500 K/1 Mbps) Clock asynchronized transmission (1202/2404/4808/9615/31250 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. 8/10-bit A/D converter Conversion precision: 8/10-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel once only) Scan conversion mode (converts two or more successive channels and can program up to 8 channels) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit PPG timers (6 channels) Number of channels: 6 (8/16-bit  6 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: fsys, fsys/21, fsys/22, fsys/23, fsys/24 (fsys  system clock frequency) 128s (fosc = 4MHz: oscillation clock frequency) 16-bit Reload timer Number of channels: 2 Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function 16-bit 16-bit Output compares Number of channels: 4 Pin input factor: A match signal of compare register I/O timer Input captures Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges) Document Number: 002-07700 Rev. *B Page 3 of 52 MB90595G Series Features MB90598G MB90F598G MB90V595G CAN Interface Number of channels: 1 Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps CAN bit timing setting: MB90598G/F598G:TSEG2RSJW Stepping motor controller (4 channels) Four high current outputs for each channel Synchronized two 8-bit PWM’s for each channel External interrupt circuit Number of inputs: 8 Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. Serial IO Clock synchronized transmission (31.25 K/62.5 K/125 K/500 K/1 Mbps at system clock frequency of 16 MHz) LSB first/MSB first Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Flash Memory Low-power consumption (stand-by) mode Supports automatic programming, Embedded Algorithm and Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Writer from Minato Electronics, Inc. Sleep/stop/CPU intermittent operation/watch timer/hardware stand-by Process CMOS 5 V10 % Power supply voltage for operation*2 Package QFP-100 PGA-256 *1: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *2: Varies with conditions such as the operating frequency. (See “Electrical Characteristics.”) Document Number: 002-07700 Rev. *B Page 4 of 52 MB90595G Series 2. Pin Assignment X1 X0 Vss 83 82 81 P00/IN0 Vcc 85 84 P02/IN2 P01/IN1 86 87 88 89 90 P07/OUT3 P06/OUT2 P05/OUT1 P04/OUT0 P03/IN3 92 91 P11/PPG1 P10/PPG0 93 P12/PPG2 94 95 P14/PPG4 P13/PPG3 96 97 P16/TIN1 P15/PPG5 99 98 P17/TOT1 100 (Top view) P20 1 80 P95/INT3 P21 2 79 P94/INT2 P22 3 78 P93/INT1 P23 P24 4 77 5 76 RST P92/INT0 P25 6 75 P26 7 74 P91/RX P90/TX P27 P30 8 73 DVSS 9 72 P87/PWM2M3 P31 10 71 P86/PWM2P3 Vss 11 70 P85/PWM1M3 P32 P33 P34 12 69 P84/PWM1P3 13 68 DVCC 14 67 P83/PWM2M2 P35 15 66 P82/PWM2P2 P36 16 65 P81/PWM1M2 P80/PWM1P2 P37 48 49 50 MD0 MD1 MD2 P56/TIN0 51 P57/TOT0 30 47 HST P52/INT5 46 52 P67/AN7 DVSS 29 45 53 P66/AN6 28 44 P70/PWM1P0 P50/SIN2 P51/INT4 P65/AN5 54 43 27 P64/AN4 P71/PWM1M0 C 42 55 41 26 Vss P72/PWM2P0 P47/SCK2 P63/AN3 56 40 P73/PWM2M0 25 39 57 P62/AN2 DVCC 24 P61/AN1 23 P45/SOT1 P46/SOT2 38 P74/PWM1P1 58 P60/AN0 59 37 22 36 P75/PWM1M1 P44/SCK1 Vcc AVss 60 AVRL 21 35 P76/PWM2P1 P43/SIN1 34 61 AVcc P77/PWM2M1 20 AVRH 62 33 19 P55/ADTG DVSS P41/SCK0 P42/SIN0 32 63 31 18 P54/INT7 P40/SOT0 P53/INT6 17 64 (PQH100) Document Number: 002-07700 Rev. *B Page 5 of 52 MB90595G Series 3. Pin Description Pin no. Pin name 82 X0 83 X1 77 52 85 to 88 89 to 92 93 to 98 99 100 1 to 8 Circuit type Function A Oscillator pin RST B Reset input HST C Hardware standby input P00 to P03 IN0 to IN3 P04 to P07 OUT0 to OUT3 P10 to P15 PPG0 to PPG5 P16 TIN1 P17 TOT1 P20 to P27 G G D D D G General purpose IO Inputs for the Input Captures General purpose IO Outputs for the Output Compares. General purpose IO Outputs for the Programmable Pulse Generators General purpose IO TIN input for the 16-bit Reload Timer 1 General purpose IO TOT output for the 16-bit Reload Timer 1 General purpose IO 9 to 10 P30 to P31 G General purpose IO 12 to 16 P32 to P36 G General purpose IO 17 P37 D General purpose IO 18 19 20 21 22 24 25 26 P40 SOT0 P41 SCK0 P42 SIN0 P43 SIN1 P44 SCK1 P45 SOT1 P46 SOT2 P47 SCK2 Document Number: 002-07700 Rev. *B G G G G G G G G General purpose IO SOT output for UART 0 General purpose IO SCK input/output for UART 0 General purpose IO SIN input for UART 0 General purpose IO SIN input for UART 1 General purpose IO SCK input/output for UART 1 General purpose IO SOT output for UART 1 General purpose IO SOT output for the Serial IO General purpose IO SCK input/output for the Serial IO Page 6 of 52 MB90595G Series Pin no. 28 29 to 32 33 38 to 41 43 to 46 47 48 Pin name Circuit type P50 SIN2 P51 to P54 INT4 to INT7 P55 ADTG P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P56 TIN0 P57 TOT0 D D D E E D D P70 to P73 54 to 57 PWM1P0 PWM1M0 PWM2P0 PWM2M0 PWM1P1 PWM1M1 PWM2P1 PWM2M1 F PWM1P2 PWM1M2 PWM2P2 PWM2M2 F 74 75 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P90 TX P91 RX Document Number: 002-07700 Rev. *B General purpose IO External interrupt input for INT4 to INT7 General purpose IO Input for the external trigger of the A/D Converter General purpose IO Inputs for the A/D Converter General purpose IO Inputs for the A/D Converter General purpose IO TIN input for the 16-bit Reload Timer 0 General purpose IO TOT output for the 16-bit Reload Timer 0 Output for Stepper Motor Controller channel 0 Output for Stepper Motor Controller channel 1 General purpose IO F P84 to P87 69 to 72 SIN Input for the Serial IO General purpose IO P80 to P83 64 to 67 General purpose IO General purpose IO P74 to P77 59 to 62 Function Output for Stepper Motor Controller channel 2 General purpose IO F D D Output for Stepper Motor Controller channel 3 General purpose IO TX output for CAN Interface General purpose IO RX input for CAN Interface Page 7 of 52 MB90595G Series Pin no. Pin name Circuit type P92 76 78 to 80 General purpose IO D INT0 P93 to P95 External interrupt input for INT0 General purpose IO D INT1 to INT3 Function External interrupt input for INT1 to INT3 58, 68 DVCC  Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) 53, 63, 73 DVSS  Dedicated ground pins for the high current output buffers (Pin No. 54 to 72) 34 AVCC Power supply Dedicated power supply pin for the A/D Converter 37 AVSS Power supply Dedicated ground pin for the A/D Converter 35 AVRH Power supply Upper reference voltage input for the A/D Converter 36 AVRL Power supply Lower reference voltage input for the A/D Converter 49, 50 MD0 MD1 C Operating mode selection input pins. These pins should be connected to VCC or VSS. 51 MD2 H Operating mode selection input pin. This pin should be connected to VCC or VSS. 27 C  External capacitor pin. A capacitor of 0.1F should be connected to this pin and VSS. 23, 84 VCC Power supply Power supply pins (5.0 V). 11, 42, 81 VSS Power supply Ground pins (0.0 V). 4. I/O Circuit Type Circuit Type Circuit Remarks X1 ■ Oscillation feedback resistor: 1 M approx. ■ Hysteresis input with pull-up Resistor: 50 k approx. ■ Hysteresis input Clock input X0 A Hard, Soft Standby control B R C Document Number: 002-07700 Rev. *B R HYS R HYS Page 8 of 52 MB90595G Series Circuit Type Circuit Remarks VCC P-ch ■ CMOS output ■ CMOS Hysteresis input ■ CMOS output ■ CMOS Hysteresis input ■ Analog input N-ch D R HYS VCC P-ch N-ch E Analog input R HYS (Continued) Document Number: 002-07700 Rev. *B Page 9 of 52 MB90595G Series Circuit Type Circuit Remarks VCC ■ CMOS high current output ■ CMOS Hysteresis input ■ CMOS output ■ CMOS Hysteresis input ■ TTL input (MB90F598G, only in Flash mode) ■ Hysteresis input Pull-down Resistor: 50 k approx. (except MB90F598G) P-ch High current N-ch F R HYS VCC P-ch N-ch G R HYS R T R H TTL HYS R Document Number: 002-07700 Rev. *B Page 10 of 52 MB90595G Series 5. Handling Devices (1) Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up). In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC) and analog input voltages not exceed the digital voltage (VCC). (2) Treatment of Unused Pins Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. (3) Using external clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. Using external clock X0 MB90595G Series Open X1 (4) Power supply pins (Vcc/Vss) In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating (See the figure below.) Make sure to connect Vcc and Vss pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between Vcc and Vss pins near the device. Vcc Vss Vcc Vss Vss Vcc MB90595G Series Vcc Vss Vss Document Number: 002-07700 Rev. *B Vcc Page 11 of 52 MB90595G Series (5) Pull-up/down resistors The MB90595G Series does not support internal pull-up/down resistors. Use external components where needed. (6) Crystal Oscillator Circuit Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuit not cross the lines of other circuits. A printed circuit board artwork surrounding the X0 and X1 pins with ground area for stabilizing the operation is highly recommended. (7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). (8) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS. (9) N.C. Pin The N.C. (internally connected) pin must be opened for use. (10) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V). (11) Indeterminate outputs from ports 0 and 1 (MB90V595G only) During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. ■ If RST pin is “H”, the outputs become indeterminate. ■ If RST pin is “L”, the outputs become high-impedance. Pay attention to the port output timing shown as follows. Oscillation setting time RST pin is “H” Power-on reset Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminated *1:Power-on reset time: Period of “clock frequency  217” (Clock frequency of 16 MHz: 8.19 ms) *2:Oscillation setting time: Period of “clock frequency  218” (Clock frequency of 16 MHz: 16.38ms) Document Number: 002-07700 Rev. *B Page 12 of 52 MB90595G Series Oscillation setting time RST pin is “L” Power-on reset Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1:Power-on reset time: Period of “clock frequency  2 ” (Clock frequency of 16 MHz: 8.19 ms) 17 *2:Oscillation setting time: Period of “clock frequency  218” (Clock frequency of 16 MHz: 16.38ms) (12) Initialization The device contains internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions In the signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00H”. If the values of the corresponding bank register (DTB,ADB,USB,SSB) are set to other than “00H”, the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (15) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free-running frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed. Document Number: 002-07700 Rev. *B Page 13 of 52 MB90595G Series 6. Block Diagram X0,X1 RST HST Clock Controller F2MC-16LX CPU 16-bit Free-run Timer RAM 4 K ROM/Flash 128 K 16-bit Input Capture 4 ch IN0 to IN3 16-bit Output Compare 4 ch OUT0 to OUT3 8/16-bit PPG 6 ch PPG0 to PPG5 Prescaler SOT0 SCK0 SIN0 UART0 CAN Controller Prescaler UART1 (SCI) Timer 2 ch Prescaler SOT2 SCK2 SIN2 AVCC AVSS AN0 to AN7 AVRH AVRL ADTG 16-bit Reload Serial I/O F2MC-16 Bus SOT1 SCK1 SIN1 RX TX TIN0, TIN1 TOT0, TOT1 PWM1M0 to PWM1M3 PWM1P0 to PWM1P3 SMC 4ch PWM2M0 to PWM2M3 PWM2P0 to PWM2P3 DVCC DVSS 10-bit ADC 8 ch Document Number: 002-07700 Rev. *B External Interrupt 8 ch INT0 to INT7 Page 14 of 52 MB90595G Series 7. Memory Space The memory space of the MB90595G Series is shown below Figure 1. Memory space map MB90V595G FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H 00FFFFH 004000H 001FFFH 001900H 0018FFH ROM (FF bank) ROM (FE bank) MB90598G/F598G FFFFFFH FF0000H FEFFFFH FE0000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (Image of FF bank) 00FFFFH 004000H ROM (Image of FF bank) Peripheral 001FFFH 001900H Peripheral RAM 6 K 0010FFH RAM 4 K 000100H 0000BFH 000000H 000100H Peripheral 0000BFH 000000H Peripheral Note: : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. Document Number: 002-07700 Rev. *B Page 15 of 52 MB90595G Series 8. I/O Map Address Register Abbreviation Access Peripheral Initial value 00H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXXB 01H Port 1 Data Register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 Data Register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 Data Register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 Data Register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 Data Register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 Data Register PDR6 R/W Port 6 XXXXXXXXB 07H Port 7 Data Register PDR7 R/W Port 7 XXXXXXXXB 08H Port 8 Data Register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 Data Register PDR9 R/W Port 9 _ _ XXXXXXB 0AH to 0FH Reserved 10H Port 0 Direction Register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B 11H Port 1 Direction Register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B 12H Port 2 Direction Register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B 13H Port 3 Direction Register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B 14H Port 4 Direction Register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B 15H Port 5 Direction Register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B 16H Port 6 Direction Register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B 17H Port 7 Direction Register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B 18H Port 8 Direction Register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B 19H Port 9 Direction Register DDR9 R/W Port 9 _ _ 0 0 0 0 0 0B R/W Port 6, A/D 1 1 1 1 1 1 1 1B 1AH 1BH Reserved Analog Input Enable Register 1CH to 1FH ADER Reserved 20H Serial Mode Control Register 0 UMC0 R/W 0 0 0 0 0 1 0 0B 21H Serial status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B 22H Serial Input/Output Data Register 0 UIDR0/UODR0 R/W 23H Rate and Data Register 0 URD0 R/W 0 0 0 0 0 0 0 XB 24H Serial Mode Register 1 SMR1 R/W 0 0 0 0 0 0 0 0B 25H Serial Control Register 1 SCR1 R/W 0 0 0 0 0 1 0 0B 26H Serial Input/Output Data Register 1 SIDR1/SODR1 R/W 27H Serial Status Register 1 SSR1 R/W 0 0 0 0 1 _ 0 0B 28H UART1 Prescaler Control Register U1CDCR R/W 0 _ _ _ 1 1 1 1B UART0 UART1 XXXXXXXXB XXXXXXXXB (Continued) Document Number: 002-07700 Rev. *B Page 16 of 52 MB90595G Series Address Register 29H to 2AH Abbreviation Access Peripheral Initial value Reserved 2BH Serial IO Prescaler SCDCR R/W 0 _ _ _ 1 1 1 1B 2CH Serial Mode Control Register (low-order) SMCS R/W _ _ _ _ 0 0 0 0B 2DH Serial Mode Control Register (high-order) SMCS R/W 2EH Serial Data Register SDR R/W XXXXXXXXB Serial IO 0 0 0 0 0 0 1 0B 2FH Edge Selector SES R/W _ _ _ _ _ _ _ 0B 30H External Interrupt Enable Register ENIR R/W 0 0 0 0 0 0 0 0B 31H External Interrupt Request Register EIRR R/W 32H External Interrupt Level Register ELVR R/W 33H External Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B 34H A/D Control Status Register 0 ADCS0 R/W 0 0 0 0 0 0 0 0B 35H A/D Control Status Register 1 ADCS1 R/W 36H A/D Data Register 0 ADCR0 R External Interrupt A/D Converter XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 37H A/D Data Register 1 ADCR1 R/W 0 0 0 0 1 _ XXB 38H PPG0 Operation Mode Control Register PPGC0 R/W 0 _ 0 0 0 _ _ 1B 39H PPG1 Operation Mode Control Register PPGC1 R/W 3AH PPG0, 1 Output Pin Control Register PPG01 R/W 3BH 16-bit Programmable Pulse Generator 0/1 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B Reserved 3CH PPG2 Operation Mode Control Register PPGC2 R/W 3DH PPG3 Operation Mode Control Register PPGC3 R/W 3EH PPG2, 3 Output Pin Control Register PPG23 R/W 40H PPG4 Operation Mode Control Register PPGC4 R/W 41H PPG5 Operation Mode Control Register PPGC5 R/W 42H PPG4, 5 Output Pin Control Register PPG45 R/W 3FH 16-bit Programmable Pulse Generator 2/3 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B Reserved 43H 16-bit Programmable Pulse Generator 4/5 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B Reserved 44H PPG6 Operation Mode Control Register PPGC6 R/W 45H PPG7 Operation Mode Control Register PPGC7 R/W 46H PPG6, 7 Output Pin Control Register PPG67 R/W 48H PPG8 Operation Mode Control Register PPGC8 R/W 49H PPG9 Operation Mode Control Register PPGC9 R/W 4AH PPG8, 9 Output Pin Control Register PPG89 R/W 47H 16-bit Programmable Pulse Generator 6/7 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B Reserved 4BH 16-bit Programmable Pulse Generator 8/9 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B Reserved (Continued) Document Number: 002-07700 Rev. *B Page 17 of 52 MB90595G Series Address Register Abbreviation Access 4CH PPGA Operation Mode Control Register PPGCA R/W 4DH PPGB Operation Mode Control Register PPGCB R/W 4EH PPGA, B Output Pin Control Register PPGAB R/W 4FH Peripheral 16-bit Programmable Pulse Generator A/B Initial value 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B Reserved 50H Timer Control Status Register 0 51H 52H 0 0 0 0 0 0 0 0B TMCSR0 R/W Timer Control Status Register 0 TMCSR0 R/W Timer 0/Reload Register 0 TMR0/TMRLR0 R/W 53H Timer 0/Reload Register 0 TMR0/TMRLR0 R/W 54H Timer Control Status Register 1 TMCSR1 R/W 0 0 0 0 0 0 0 0B 55H Timer Control Status Register 1 TMCSR1 R/W _ _ _ _ 0 0 0 0B 56H Timer Register 1/Reload Register 1 TMR1/TMRLR1 R/W 57H Timer Register 1/Reload Register 1 TMR1/TMRLR1 R/W 58H Output Compare Control Status Register 0 OCS0 R/W 59H Output Compare Control Status Register 1 OCS1 R/W 5AH Output Compare Control Status Register 2 OCS2 R/W 5BH Output Compare Control Status Register 3 OCS3 5CH Input Capture Control Status Register 0/1 5DH Input Capture Control Status Register 2/3 5EH PWM Control Register 0 5FH 60H PWM Control Register 1 XXXXXXXXB XXXXXXXXB 16-bit Reload Timer 1 XXXXXXXXB XXXXXXXXB Output Compare 0/1 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B 0 0 0 0 _ _ 0 0B R/W Output Compare 2/3 _ _ _ 0 0 0 0 0B ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B R/W Stepping Motor Controller 0 0 0 0 0 0 _ _ 0B R/W Stepping Motor Controller 1 0 0 0 0 0 _ _ 0B R/W Stepping Motor Controller 2 0 0 0 0 0 _ _ 0B R/W Stepping Motor Controller 3 0 0 0 0 0 _ _ 0B PWC0 PWC1 Reserved PWM Control Register 2 63H 64H _ _ _ _ 0 0 0 0B Reserved 61H 62H 16-bit Reload Timer 0 PWC2 Reserved PWM Control Register 3 PWC3 66H Timer Data Register (low-order) TCDT R/W 67H Timer Data Register (high-order) TCDT R/W 68H Timer Control Status Register TCCS R/W 65H Reserved 69H to 6EH 0 0 0 0 0 0 0 0B 16-bit Free-run Timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Reserved (Continued) Document Number: 002-07700 Rev. *B Page 18 of 52 MB90595G Series Address Register Abbreviation Access Peripheral Initial value 6FH ROM Mirror Function Selection Register ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B 70H PWM1 Compare Register 0 PWC10 R/W 71H PWM2 Compare Register 0 PWC20 R/W 72H PWM1 Select Register 0 PWS10 R/W 73H PWM2 Select Register 0 PWS20 R/W _ 0 0 0 0 0 0 0B 74H PWM1 Compare Register 1 PWC11 R/W XXXXXXXXB 75H PWM2 Compare Register 1 PWC21 R/W 76H PWM1 Select Register 1 PWS11 R/W 77H PWM2 Select Register 1 PWS21 R/W _ 0 0 0 0 0 0 0B 78H PWM1 Compare Register 2 PWC12 R/W XXXXXXXXB 79H PWM2 Compare Register 2 PWC22 R/W 7AH PWM1 Select Register 2 PWS12 R/W 7BH PWM2 Select Register 2 PWS22 R/W _ 0 0 0 0 0 0 0B 7CH PWM1 Compare Register 3 PWC13 R/W XXXXXXXXB 7DH PWM2 Compare Register 3 PWC23 R/W 7EH PWM1 Select Register 3 PWS13 R/W 7FH PWM2 Select Register 3 PWS23 R/W XXXXXXXXB Stepping Motor Controller 0 Stepping Motor Controller 1 Stepping Motor Controller 2 Stepping Motor Controller 3 XXXXXXXXB _ _ 0 0 0 0 0 0B XXXXXXXXB _ _ 0 0 0 0 0 0B XXXXXXXXB _ _ 0 0 0 0 0 0B XXXXXXXXB _ _ 0 0 0 0 0 0B _ 0 0 0 0 0 0 0B 80H to 8FH CAN Controller. Refer to section about CAN Controller 90H to 9DH Reserved 9EH Program Address Detection Control Status Register PACSR R/W Address Match Detection Function 0 0 0 0 0 0 0 0B 9FH Delayed Interrupt/Request Register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B A0H Low-Power Mode Control Register LPMCR R/W Low Power Controller 0 0 0 1 1 0 0 0B A1H Clock Selection Register CKSCR R/W Low Power Controller 1 1 1 1 1 1 0 0B A8H Watchdog Timer Control Register WDTC R/W Watchdog Timer XXXXX 1 1 1B A9H Time Base Timer Control Register TBTC R/W Time Base Timer 1 _ _ 0 0 1 0 0B R/W Flash Memory 0 0 0 X 0 0 0 0B A2H to A7H Reserved AAH to ADH AEH Reserved Flash Memory Control Status Register (MB90F598G only. Otherwise reserved) AFH FMCS Reserved (Continued) Document Number: 002-07700 Rev. *B Page 19 of 52 MB90595G Series Address Register Abbreviation Access Peripheral Initial value B0H Interrupt Control Register 00 ICR00 R/W B1H Interrupt Control Register 01 ICR01 R/W B2H Interrupt Control Register 02 ICR02 R/W B3H Interrupt Control Register 03 ICR03 R/W 0 0 0 0 0 1 1 1B B4H Interrupt Control Register 04 ICR04 R/W 0 0 0 0 0 1 1 1B B5H Interrupt Control Register 05 ICR05 R/W 0 0 0 0 0 1 1 1B B6H Interrupt Control Register 06 ICR06 R/W 0 0 0 0 0 1 1 1B B7H Interrupt Control Register 07 ICR07 R/W 0 0 0 0 0 1 1 1B B8H Interrupt Control Register 08 ICR08 R/W 0 0 0 0 0 1 1 1B B9H Interrupt Control Register 09 ICR09 R/W BAH Interrupt Control Register 10 ICR10 R/W 0 0 0 0 0 1 1 1B Interrupt controller Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B BBH Interrupt Control Register 11 ICR11 R/W 0 0 0 0 0 1 1 1B BCH Interrupt Control Register 12 ICR12 R/W 0 0 0 0 0 1 1 1B BDH Interrupt Control Register 13 ICR13 R/W 0 0 0 0 0 1 1 1B BEH Interrupt Control Register 14 ICR14 R/W 0 0 0 0 0 1 1 1B BFH Interrupt Control Register 15 ICR15 R/W 0 0 0 0 0 1 1 1B C0H to FFH 1900H 1901H Reserved Reload Register L Reload Register H PRLL0 PRLH0 R/W 1902H Reload Register L PRLL1 R/W 1903H Reload Register H PRLH1 R/W 1904H Reload Register L PRLL2 R/W 1905H Reload Register H PRLH2 R/W 1906H Reload Register L PRLL3 R/W 1907H Reload Register H PRLH3 R/W 1908H Reload Register L PRLL4 R/W 1909H Reload Register H PRLH4 R/W 190AH Reload Register L PRLL5 R/W 190BH Reload Register H PRLH5 R/W 190CH Reload Register L PRLL6 R/W 190DH Reload Register H XXXXXXXXB R/W PRLH6 R/W 190EH Reload Register L PRLL7 R/W 190FH Reload Register H PRLH7 R/W 16-bit Programmable Pulse Generator 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) Document Number: 002-07700 Rev. *B Page 20 of 52 MB90595G Series Address Register Abbreviation Access 1910H Reload Register L PRLL8 R/W 1911H Reload Register H PRLH8 R/W 1912H Reload Register L PRLL9 R/W 1913H Reload Register H PRLH9 1914H Reload Register L PRLLA 1915H Reload Register H PRLHA R/W 1916H Reload Register L PRLLB R/W 1917H Reload Register H PRLHB 1918H to 191FH Peripheral Initial value XXXXXXXXB 16-bit Programmable Pulse Generator 8/9 XXXXXXXXB R/W XXXXXXXXB R/W 16-bit Programmable Pulse Generator A/B XXXXXXXXB 16-bit Programmable Pulse Generator A/B XXXXXXXXB R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved 1920H Input Capture Register 0 (low-order) IPCP0 R 1921H Input Capture Register 0 (high-order) IPCP0 R 1922H Input Capture Register 1 (low-order) IPCP1 R XXXXXXXXB 1923H Input Capture Register 1 (high-order) IPCP1 R XXXXXXXXB 1924H Input Capture Register 2 (low-order) IPCP2 R XXXXXXXXB 1925H Input Capture Register 2 (high-order) IPCP2 R 1926H Input Capture Register 3 (low-order) IPCP3 R XXXXXXXXB 1927H Input Capture Register 3 (high-order) IPCP3 R XXXXXXXXB 1928H Output Compare Register 0 (low-order) OCCP0 R/W XXXXXXXXB 1929H Output Compare Register 0 (high-order) OCCP0 R/W 192AH Output Compare Register 1 (low-order) OCCP1 R/W XXXXXXXXB 192BH Output Compare Register 1 (high-order) OCCP1 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Capture 0/1 XXXXXXXXB Input Capture 2/3 XXXXXXXXB Output Compare 0/1 (Continued) Document Number: 002-07700 Rev. *B Page 21 of 52 MB90595G Series (Continued) Address Register Abbreviation Access Peripheral 192CH Output Compare Register 2 (low-order) OCCP2 R/W 192DH Output Compare Register 2 (high-order) OCCP2 R/W 192EH Output Compare Register 3 (low-order) OCCP3 R/W XXXXXXXXB 192FH Output Compare Register 3 (high-order) OCCP3 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB Output Compare 2/3 1930H to 19FFH Reserved 1A00H to 1AFFH CAN Controller. Refer to section about CAN Controller 1B00H to 1BFFH CAN Controller. Refer to section about CAN Controller 1C00H to 1EFFH Reserved 1FF0H Program Address Detection Register 0 (low-order) 1FF1H Program Address Detection Register 0 (middle-order) 1FF2H Program Address Detection Register 0 (high-order) 1FF3H Program Address Detection Register 1 (low-order) 1FF4H Program Address Detection Register 1 (middle-order) 1FF5H Program Address Detection Register 1 (high-order) 1FF6H to 1FFFH ■ Description for Read/Write R/W : Readable/writable R : Read only W : Write only ■ Description of initial value 0 : the initial value of this bit is "0". 1 : the initial value of this bit is "1". X : the initial value of this bit is undefined. _ : this bit is unused. the initial value is undefined. Initial value XXXXXXXXB PADR0 XXXXXXXXB R/W Address Match Detection Function PADR1 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved Note: : Addresses in the range of 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results in reading “X”, and any write access should not be performed. Document Number: 002-07700 Rev. *B Page 22 of 52 MB90595G Series 9. Can Controller The CAN controller has the following features: ■ Conforms to CAN Specification Version 2.0 Part A and B ❐ - Supports transmission/reception in standard frame and extended frame formats ■ Supports transmission of data frames by receiving remote frames ■ 16 transmitting/receiving message buffers ❐ 29-bit ID and 8-byte data ❐ Multi-level message buffer configuration ■ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask ❐ Two acceptance mask registers in either standard frame format or extended frame format ■ Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz) 9.1 List of Control Registers Address 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 001B00H 001B01H 001B02H 001B03H 001B04H 001B05H 001B06H 001B07H Register Abbreviation Access Initial Value Message buffer valid register BVALR R/W 00000000 00000000B Transmit request register TREQR R/W 00000000 00000000B Transmit cancel register TCANR W 00000000 00000000B Transmit complete register TCR R/W 00000000 00000000B Receive complete register RCR R/W 00000000 00000000B Remote request receiving register RRTRR R/W 00000000 00000000B Receive overrun register ROVRR R/W 00000000 00000000B Receive interrupt enable register RIER R/W 00000000 00000000B Control status register CSR R/W, R 00---000 0----0-1B Last event indicator register LEIR R/W -------- 000-0000B Receive/transmit error counter RTEC R 00000000 00000000B BTR R/W -1111111 11111111B Bit timing register (Continued) Document Number: 002-07700 Rev. *B Page 23 of 52 MB90595G Series (Continued) Address 001B08H 001B09H 001B0AH 001B0BH 001B0CH 001B0DH 001B0EH 001B0FH Register Abbreviation Access Initial Value IDER R/W XXXXXXXX XXXXXXXXB Transmit RTR register TRTRR R/W 00000000 00000000B Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXXB Transmit interrupt enable register TIER R/W 00000000 00000000B Acceptance mask select register AMSR R/W IDE register 001B10H 001B11H 001B12H XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB 001B13H 001B14H 001B15H 001B16H XXXXXXXX XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB 001B17H 001B18H 001B19H 001B1AH XXXXXXXX XXXXXXXXB Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXXB 001B1BH 9.2 List of Message Buffers (ID Registers) Address 001A00H to 001A1FH Register General-purpose RAM Abbreviation Access Initial Value -- R/W XXXXXXXXB to XXXXXXXXB 001A20H 001A21H 001A22H XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXX--- XXXXXXXXB 001A23H 001A24H 001A25H 001A26H XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--- XXXXXXXXB 001A27H 001A28H 001A29H 001A2AH XXXXXXXX XXXXXXXXB ID register 2 001A2BH Document Number: 002-07700 Rev. *B IDR2 R/W XXXXX--- XXXXXXXXB Page 24 of 52 MB90595G Series Address Register Abbreviation Access 001A2CH 001A2DH 001A2EH XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--- XXXXXXXXB 001A2FH 001A30H 001A31H 001A32H XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--- XXXXXXXXB 001A33H 001A34H 001A35H 001A36H XXXXXXXX XXXXXXXXB ID register 5 IDR5 R/W XXXXX--- XXXXXXXXB 001A37H 001A38H 001A39H 001A3AH XXXXXXXX XXXXXXXXB ID register 6 IDR6 R/W XXXXX--- XXXXXXXXB 001A3BH 001A3CH 001A3DH 001A3EH Initial Value XXXXXXXX XXXXXXXXB ID register 7 001A3FH IDR7 R/W XXXXX--- XXXXXXXXB (Continued) Document Number: 002-07700 Rev. *B Page 25 of 52 MB90595G Series (Continued) Address Register Abbreviation Access IDR8 R/W 001A40H 001A41H 001A42H XXXXXXXX XXXXXXXXB ID register 8 XXXXX--- XXXXXXXXB 001A43H 001A44H 001A45H 001A46H XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB 001A47H 001A48H 001A49H 001A4AH XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB 001A4BH 001A4CH 001A4DH 001A4EH XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB 001A4FH 001A50H 001A51H 001A52H XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB 001A53H 001A54H 001A55H 001A56H XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB 001A57H 001A58H 001A59H 001A5AH XXXXXXXX XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB 001A5BH 001A5CH 001A5DH 001A5EH Initial Value XXXXXXXX XXXXXXXXB ID register 15 001A5FH Document Number: 002-07700 Rev. *B IDR15 R/W XXXXX--- XXXXXXXXB Page 26 of 52 MB90595G Series 9.3 List of Message Buffers (DLC Registers and Data Registers) Address 001A60H 001A61H 001A62H 001A63H 001A64H 001A65H 001A66H 001A67H 001A68H 001A69H 001A6AH 001A6BH 001A6CH 001A6DH 001A6EH 001A6FH 001A70H 001A71H 001A72H 001A73H 001A74H 001A75H 001A76H 001A77H 001A78H 001A79H 001A7AH 001A7BH 001A7CH 001A7DH 001A7EH 001A7FH 001A80H to 001A87H Register Abbreviation Access Initial Value DLC register 0 DLCR0 R/W ----XXXXB DLC register 1 DLCR1 R/W ----XXXXB DLC register 2 DLCR2 R/W ----XXXXB DLC register 3 DLCR3 R/W ----XXXXB DLC register 4 DLCR4 R/W ----XXXXB DLC register 5 DLCR5 R/W ----XXXXB DLC register 6 DLCR6 R/W ----XXXXB DLC register 7 DLCR7 R/W ----XXXXB DLC register 8 DLCR8 R/W ----XXXX DLC register 9 DLCR9 R/W ----XXXXB DLC register 10 DLCR10 R/W ----XXXXB DLC register 11 DLCR11 R/W ----XXXXB DLC register 12 DLCR12 R/W ----XXXXB DLC register 13 DLCR13 R/W ----XXXXB DLC register 14 DLCR14 R/W ----XXXXB DLC register 15 DLCR15 R/W ----XXXXB DTR0 R/W XXXXXXXXB to XXXXXXXXB Data register 0 (8 bytes) (Continued) Document Number: 002-07700 Rev. *B Page 27 of 52 MB90595G Series (Continued) Address Register Abbreviation Access Initial Value 001A88H to 001A8FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXXB to XXXXXXXXB 001A90H to 001A97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXXB to XXXXXXXXB 001A98H to 001A9FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXXB to XXXXXXXXB 001AA0H to 001AA7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXXB to XXXXXXXXB 001AA8H to 001AAFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXXB to XXXXXXXXB 001AB0H to 001AB7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXXB to XXXXXXXXB 001AB8H to 001ABFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXXB to XXXXXXXXB 001AC0H to 001AC7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXXB to XXXXXXXXB 001AC8H to 001ACFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXXB to XXXXXXXXB 001AD0H to 001AD7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXXB to XXXXXXXXB 001AD8H to 001ADFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXXB to XXXXXXXXB 001AE0H to 001AE7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXXB to XXXXXXXXB 001AE8H to 001AEFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXXB to XXXXXXXXB 001AF0H to 001AF7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXXB to XXXXXXXXB 001AF8H to 001AFFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXXB to XXXXXXXXB Document Number: 002-07700 Rev. *B Page 28 of 52 MB90595G Series 10. Interrupt Source, Interrupt Vector, and Interrupt Control Register Interrupt vector Interrupt control register EI2OS clear Number Address Number Address Reset N/A # 08 FFFFDCH —— —— INT9 instruction N/A # 09 FFFFD8H —— —— Exception N/A # 10 FFFFD4H —— —— CAN RX N/A # 11 FFFFD0H CAN TX/NS N/A # 12 FFFFCCH ICR00 0000B0H *1 # 13 FFFFC8H N/A # 14 FFFFC4H ICR01 0000B1H 16-bit Reload Timer 0 *1 # 15 FFFFC0H 8/10-bit A/D Converter *1 # 16 FFFFBCH ICR02 0000B2H 16-bit Free-run Timer ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Interrupt source External Interrupt (INT0/INT1) Time Base Timer N/A # 17 FFFFB8H External Interrupt (INT2/INT3) *1 # 18 FFFFB4H Serial I/O *1 # 19 FFFFB0H External Interrupt (INT4/INT5) *1 # 20 FFFFACH Input Capture 0 *1 # 21 FFFFA8H 8/16-bit PPG 0/1 N/A # 22 FFFFA4H Output Compare 0 *1 # 23 FFFFA0H N/A # 24 FFFF9CH External Interrupt (INT6/INT7) *1 # 25 FFFF98H Input Capture 1 *1 # 26 FFFF94H 8/16-bit PPG 4/5 N/A # 27 FFFF90H *1 # 28 FFFF8CH 8/16-bit PPG 6/7 N/A # 29 FFFF88H Input Capture 2 *1 # 30 FFFF84H 8/16-bit PPG 8/9 N/A # 31 FFFF80H *1 # 32 FFFF7CH 8/16-bit PPG 2/3 Output Compare 1 Output Compare 2 Input Capture 3 *1 # 33 FFFF78H N/A # 34 FFFF74H Output Compare 3 *1 # 35 FFFF70H 16-bit Reload Timer 1 *1 # 36 FFFF6CH UART 0 RX *2 # 37 FFFF68H UART 0 TX *1 # 38 FFFF64H 8/16-bit PPG A/B UART 1 RX *2 # 39 FFFF60H UART 1 TX *1 # 40 FFFF5CH Flash Memory N/A # 41 FFFF58H Delayed interrupt N/A # 42 FFFF54H *1: The interrupt request flag is cleared by the EI2OS interrupt clear signal. *2: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. N/A:The interrupt request flag is not cleared by the EI2OS interrupt clear signal. Document Number: 002-07700 Rev. *B Page 29 of 52 MB90595G Series Notes: ■ For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. ■ At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. ■ If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. Document Number: 002-07700 Rev. *B Page 30 of 52 MB90595G Series 11. Electrical Characteristics 11.1 Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage Min Rating Max VSS  0.3 AVCC VSS  0.3 AVRH AVRL VSS  0.3 DVCC Input voltage VI Output voltage VO VSS  6.0 VSS  6.0 Unit Remarks V V VCC  AVCC *1 VSS  6.0 V VSS  0.3 VSS  6.0 AVCC  AVRH/L, AVRH  AVRL *1 V VCC  DVCC VSS  0.3 VSS  6.0 VSS  0.3 VSS  6.0 V *2 V *2 ICLAMP 2.0  20 mA “L” level Max. output current IOL1 — 15 mA Normal output *3 “L” level Avg. output current IOLAV1 — 4 mA Normal output, average value *4 “L” level Max. output current IOL2 — 40 mA High current output *3 “L” level Avg. output current IOLAV2 — 30 mA High current output, average value *4 Maximum Clamp Current Maximum Total Clamp Current ICLAMP 2.0 mA *6 *6 “L” level Max. overall output current IOL1 — 100 mA Total normal output “L” level Max. overall output current IOL2 — 330 mA Total high current output “L” level Avg. overall output current IOLAV1 — 50 mA Total normal output, average value *5 “L” level Avg. overall output current IOLAV2 — 250 mA Total high current output, average value *5 “H” level Max. output current IOH1 — mA Normal output *3 “H” level Avg. output current IOHAV1 — mA Normal output, average value *4 “H” level Max. output current IOH2 — mA High current output *3 “H” level Avg. output current IOHAV2 — mA High current output, average value *4 “H” level Max. overall output current IOH1 — “H” level Max. overall output current IOH2 — “H” level Avg. overall output current IOHAV1 — “H” level Avg. overall output current IOHAV2 — 15 4 40 30 100 330 50 250 — — Power consumption PD Operating temperature TA Storage temperature TSTG 40 55 mA Total normal output mA Total high current output mA Total normal output, average value *5 mA Total high current output, average value *5 500 mW MB90F598G 400 mW MB90598G 85 150 C C *1: AVCC, AVRH, AVRL and DVCC shall not exceed VCC. AVRH and AVRL shall not exceed AVCC. Also, AVRL shall never exceed AVRH. *2: VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3: The maximum output current is a peak value for a corresponding pin. *4: Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: Total average current is an average current value observed for a 100 ms period for all corresponding pins. *6: ■ Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, P90 to P95 ■ Use within recommended operating conditions. ■ Use at DC voltage (current) . ■ The B signal should always be applied with a limiting resistance placed between the B signal and the microcontroller. Document Number: 002-07700 Rev. *B Page 31 of 52 MB90595G Series ■ ■ The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. ■ Note that if a B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. ■ Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. ■ Care must be taken not to leave the B input pin open. ■ Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept B signal input. ■ Sample recommended circuits : • Input/Output Equivalent circuits Protective diode VCC B input (0 V to 16 V) Limiting resistance P-ch N-ch R Note: : Average output current = operating current  operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-07700 Rev. *B Page 32 of 52 MB90595G Series 11.2 Recommended Conditions (VSS = AVSS = 0.0 V) Parameter Value Symbol Min Typ Max Unit Remarks VCC 4.5 5.0 5.5 V Under normal operation AVCC 3.0  5.5 V Maintains RAM data in stop mode Smooth capacitor CS 0.022 0.1 1.0 F * Operating temperature TA –40  +85 C Power supply voltage *: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. • C Pin Connection Diagram C CS 11.3 DC Characteristics Parameter Input H voltage Input L voltage Output H voltage Output L voltage Symbol Pin name (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Condition Unit Remarks Min Typ Max VIHS CMOS hysteresis input pin — 0.8 VCC  VCC +0.3 V VIHM MD input pin — VCC – 0.3  VCC +0.3 V VILS CMOS hysteresis input pin — VSS – 0.3  0.2 VCC V VILM MD input pin — VSS – 0.3  VSS +0.3 V VOH1 Output pins except P70 to P87 VCC = 4.5 V, IOH1 = –4.0 mA VCC – 0.5 — — V VOH2 P70 to P87 VCC = 4.5 V, IOH2 = –30.0 mA VCC – 0.5 — — V VOL1 Output pins except P70 to P87 VCC = 4.5 V, IOL1 = 4.0 mA — — 0.4 V VOL2 P70 to P87 VCC = 4.5 V, IOL2 = 30.0 mA — — 0.5 V Document Number: 002-07700 Rev. *B Page 33 of 52 MB90595G Series Parameter Input leak current Symbol Pin name Condition IIL VCC = 5.5 V, VSS < VI < VCC ICC VCC = 5.0 V10%, Internal frequency: 16 MHz, At normal operating Value Unit Remarks Min Typ Max –5 — 5 A — 35 60 mA MB90598G — 40 60 mA MB90F598G — 11 18 mA — 0.3 0.6 mA — — 20 A — — 20 A MB90598G — 50 100 A MB90F598G VCC = 5.0 V10%, Internal frequency: ICCS Power supply current * 16 MHz, At sleep VCC ICTS VCC = 5.0 V1%, Internal frequency: 2 MHz, At timer mode ICCH VCC = 5.0 V10%, At stop, TA = 25C ICCH2 VCC = 5.0 V10%, At Hardware standby mode, TA = 25C (Continued) Document Number: 002-07700 Rev. *B Page 34 of 52 MB90595G Series (Continued) Parameter (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Condition Unit Remarks Min Typ Max Symbol Pin name CIN Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, P70 to P87 — — 5 15 pF P70 to P87 — — 15 30 pF Input capacity Pull-up resistance RUP RST — 25 50 100 k Pull-down resistance RDOWN MD2 — 25 50 100 k * : The power supply current testing conditions are when using the external clock. 11.4 AC Characteristics 11.4.1 Clock Timing Parameter (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Unit Remarks Typ Max Symbol Pin name Oscillation frequency fC X0, X1 3 — 5 MHz When using oscillation circuit Oscillation cycle time tCYL X0, X1 200 — 333 ns When using oscillation circuit External clock frequency fC X0, X1 3 — 16 MHz When using external clock External clock cycle time tCYL X0, X1 62.5 — 333 ns When using external clock f — — — 5 % PWH, PWL X0 10 — — ns Duty ratio is about 30 to 70%. tCR, tCF X0 — — 5 ns When using external clock Machine clock frequency fCP — 1.5 — 16 MHz Machine clock cycle time tCP — 62.5 — 666 ns tCYL — — 2*tCP — ns Frequency deviation with PLL * Input clock pulse width Input clock rise and fall time Flash Read cycle time Min When Flash is accessed via CPU *: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock.   f = ------  100% fo Central frequency fO  • Clock Timing tCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF Document Number: 002-07700 Rev. *B tCR Page 35 of 52 MB90595G Series ■ Example of Oscillation circuit X0 X1 R C1 Document Number: 002-07700 Rev. *B C2 Page 36 of 52 MB90595G Series • Guaranteed operation range Guaranteed operation range 5.5 4.5 Power supply voltage VCC (V) Guaranteed PLL operation range 3.0 1.5 8 16 Machine clock fCP (MHz) • Oscillation frequency and machine clock frequency 4 16 3 1 2 12 Machine clock fCP (MHz) 9 8 1/2 (PLL off) 4 3 4 8 16 Oscillation frequency fC (MHz) AC characteristics are set to the measured reference voltage values below. • Input signal waveform Hysteresis Input Pin 0.8 VCC 0.2 VCC Document Number: 002-07700 Rev. *B • Output signal waveform Output Pin 2.4 V 0.8 V Page 37 of 52 MB90595G Series 11.4.2 Reset and Hardware Standby Input Parameter (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Unit Remarks Min Max Symbol Pin name Reset input time tRSTL Hardware standby input time tHSTL RST HST 16 tCP*1 — ns Under normal operation Oscillation time of oscillator*2  16 tCP*1 — ms In stop mode 16 tCP*1 — ns Under normal operation Oscillation time of oscillator*2  16 tCP*1 — ms In stop mode *1: “tcp” represents one cycle time of the machine clock. No reset can fully initialize the Flash Memory if it is performing the automatic algorithm. *2: Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. Under Normal Operation tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC In Stop Mode tRSTL, tHSTL RST HST 0.2VCC 0.2VCC 90 of amplitude X0 Internal operation clock 16 tCP Oscillation time of oscillator Oscillation setting time Instruction execution Internal reset Document Number: 002-07700 Rev. *B Page 38 of 52 MB90595G Series 11.4.3 Power On Reset Parameter Power on rise time Power off time Symbol Pin name tR VCC tOFF VCC (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Condition Unit Remarks Min Max — 0.05 30 ms * 50 — ms Due to repetitive operation *: VCC must be kept lower than 0.2 V before power-on. Notes: ■ The above values are used for creating a power-on reset. ■ Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn on the power supply using the above values. tR 2.7 V VCC 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or less per second, however, you can use the PLL clock. VCC 3V RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. VSS 11.4.4 UART0/1, Serial I/O Timing Parameter Serial clock cycle time SCK   SOT delay time Symbol Pin name tSCYC SCK0 to SCK2 tSLOV SCK0 to SCK2, SOT0 to SOT2 Valid SIN  SCK  tIVSH SCK0 to SCK2, SIN0 to SIN2 SCK   Valid SIN hold time tSHIX SCK0 to SCK2, SIN0 to SIN2 Document Number: 002-07700 Rev. *B (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Condition Unit Remarks Min Max Internal clock operation output pins are CL = 80 pF + 1 TTL. 8 tCP — ns –80 80 ns 100 — ns 60 — ns Page 39 of 52 MB90595G Series Parameter Symbol Pin name Serial clock “H” pulse width tSHSL Serial clock “L” pulse width Condition Value Unit Min Max SCK0 to SCK2 4 tCP — ns tSLSH SCK0 to SCK2 4 tCP — ns SCK   SOT delay time tSLOV SCK0 to SCK2, SOT0 to SOT2 — 150 ns Valid SIN  SCK  tIVSH SCK0 to SCK2, SIN0 to SIN2 60 — ns SCK   Valid SIN hold time tSHIX SCK0 to SCK2, SIN0 to SIN2 60 — ns External clock operation output pins are CL = 80 pF + 1 TTL. Remarks Notes: ■ AC characteristic in CLK synchronized mode. ■ CL is load capacity value of pins when testing. ■ tcp (external operation clock cycle time) : see Clock timing. • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN Document Number: 002-07700 Rev. *B 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC Page 40 of 52 MB90595G Series • External Shift Clock Mode tSLSH tSHSL 0.8 VCC 0.8 VCC SCK 0.2 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC 0.8 VCC SIN 0.2 VCC (5) Timer Input Timing Parameter Input pulse width Symbol Pin name tTIWH TIN0, TIN1 tTIWL IN0 to IN3 (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Condition Unit Remarks Min Max — 4 tCP — ns • Timer Input Timing 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTIWH tTIWL 11.4.5 Trigger Input Timing Parameter Input pulse width Symbol Pin name Condition tTRGH tTRGL INT0 to INT7, ADTG — Document Number: 002-07700 Rev. *B (VCC  5.0 V10%, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Unit Remarks Min Max 5 tCP — ns Under normal operation 1 — s In stop mode Page 41 of 52 MB90595G Series • Trigger Input Timing 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTRGH tTRGL 11.4.6 Slew Rate High Current Outputs (MB90598G, MB90F598G only) (VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Typ Max Output Rise/Fall time tR2 tF2 Port P70 to P77, Port P80 to P87 — 15 40 150 ns • Slew Rate Output Timing VH VH VL tR2 11.5 A/D Converter tF2 (VCC  AVCC  5.0 V10%, VSS  AVSS  0.0 V,3.0 V  AVRH  AVRL, TA  40 C to +85 C) Value Symbol Pin name Resolution — — — Parameter VH  VOL2  0.1  (VOH2  VOL2) VL  VOL2  0.9  (VOH2  VOL2) VL Min Typ Max 10 5.0 2.5 1.9 AVRL  Unit bit LSB Conversion error — — — — Nonlinearity error — — — — Differential linearity error — — — — Zero transition voltage VOT AN0 to AN7 AVRL  3.5 LSB AVRL + 0.5 LSB Full scale transition voltage VFST AN0 to AN7 AVRH  6.5 LSB AVRH  1.5 LSB AVRH  1.5 LSB V Conversion time — — — 352tCP — ns Sampling time — — — 64tCP — ns Analog port input current IAIN AN0 to AN7 10 — 10 A Analog input voltage range VAIN AN0 to AN7 AVRL — AVRH V Document Number: 002-07700 Rev. *B 4.5 LSB Remarks LSB LSB V Page 42 of 52 MB90595G Series Parameter Reference voltage range Power supply current Reference voltage current Offset between input channels Symbol Pin name — Value Unit Remarks Min Typ Max AVRH AVRL  3.0 — AVCC V — AVRL 0 — AVRH  3.0 V IA AVCC — 5 — mA IAH AVCC — — 5 A * IR AVRH — 400 600 A MB90V595G, MB90F598G — 140 600 A MB90598G * IRH AVRH — — 5 A — AN0 to AN7 — — 4 LSB * : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped. Document Number: 002-07700 Rev. *B Page 43 of 52 MB90595G Series 11.6 A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter Linearity error:The deviation of the straight line connecting the zero transition point (“00 0000 0000”  “00 0000 0001”) with the full-scale transition point (“11 1111 1110” “11 1111 1111”) from actual conversion characteristics Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error:The total error is defined as a difference between the actual value and the theoretical value, which includes zerotransition error/full-scale transition error and linearity error. Total error 3FF 3FE 0.5 LSB Actual conversion value Digital output 3FD {1 LSB  (N – 1) + 0.5 LSB} 004 VNT (measured value) 003 Actual conversion characteristics 002 Theoretical characteristics 001 0.5 LSB AVRL 1 LSB = (Theoretical value) AVRH – AVRL 1024 VOT (Theoretical value) = AVRL + 0.5 LSB[V] Analog input [V] AVRH Total error for digital output N = VNT – {1 LSB  (N – 1) + 0.5 LSB} 1 LSB [LSB] VNT: Voltage at a transition of digital output from (N – 1) to N VFST (Theoretical value) = AVRH – 1.5 LSB[V] (Continued) Document Number: 002-07700 Rev. *B Page 44 of 52 MB90595G Series (Continued) Linearity error Differential linearity error Theoretical characteristics 3FF Actual conversion value {1 LSB  (N – 1)+ VOT} 3FE N+1 Actual conversion value VFST (measured value) Digital output Digital output 3FD VNT 004 Actual conversion characteristics 003 N V(N + 1)T (measured value) N–1 VNT (measured value) 002 Theoretical characteristics 001 Actual conversion value N–2 VOT (measured value) AVRL Analog input AVRH AVRL Analog input AVRH Linearity error of VNT – {1 LSB  (N – 1) + VOT} [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = V(N + 1)T – VNT 1 LSB – 1 LSB [LSB] VFST – VOT [V] 1022 VOT: Voltage at transition of digital output from “000H” to “001H” VFST: Voltage at transition of digital output from “3FEH” to “3FFH” 11.7 Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions,: ■ Output impedance values of the external circuit of 15 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). ■ • Equipment of analog input circuit model Analog input Comparator 3.2 k Max 30 pF Max Error The smaller the | AVRH  AVRL |, the greater the error would become relatively. ■ Document Number: 002-07700 Rev. *B Page 45 of 52 MB90595G Series 11.8 Flash memory ■ Erase and programming performance Parameter Condition Sector erase time Chip erase time TA  25 C, VCC  5.0 V Word (16-bit) programming time Erase/Program cycle  Document Number: 002-07700 Rev. *B Value Unit Remarks Min Typ Max  1 15 s MB90F598G Excludes 00H programming prior erasure  5  s MB90F598G Excludes 00H programming prior  16 3600 s MB90F598G Excludes system-level overhead 10000   cycle Page 46 of 52 MB90595G Series 12. Example Characteristics ■ H” Level Output Voltage VOH1 – IOH1 4.5 4.5 4 4 3.5 3.5 3 2.5 3 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 (Vcc = 4.5 V, TA = +25˚C) 5 VOH2 [V] VOH1 [V] VOH2 – IOH2 (Vcc = 4.5 V, TA = +25˚C) 5 0 0.0 -2.0 -4.0 -6.0 -8.0 0 -10.0 -10 IOH1 [mA] ■ -30 -40 L” Level Input Voltage VOL2 – IOL2 VOL1 – IOL1 (Vcc = 4.5 V, TA = +25˚C) 600 500 VOL2 [mV] VOL1 [mV] 400 300 400 300 200 200 100 100 0 0.0 (Vcc = 4.5 V, TA = +25˚C) 600 500 2.0 4.0 8.0 6.0 0 10.0 IOL1 [mA] ■ -20 IOH2 [mA] 0 10 20 30 40 IOL2 [mA] H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN – VCC 5 (TA = +25˚C) 4 VIN [V] VIH 3 VIL 2 1 0 3 4 5 6 Vcc [V] Document Number: 002-07700 Rev. *B Page 47 of 52 MB90595G Series Supply Current ICCS – VCC ICC – VCC (TA = +25˚C) 45 fcp = 16 MHz 40 fcp = 16 MHz fcp = 12 MHz 30 25 fcp = 8 MHz ICCS [mA] 14 35 ICC [mA] (TA = +25˚C) 16 12 fcp = 12 MHz 10 8 fcp = 8 MHz 20 6 15 fcp = 4 MHz 4 fcp = 2 MHz 2 10 5 0 fcp = 4 MHz fcp = 2 MHz 0 2.0 3.0 4.0 5.0 6.0 2.0 7.0 4.0 5.0 6.0 VCC [V] ICTS – VCC ICCH – VCC (fcp = f2 MHz, TA = +25˚C) 600 3.0 VCC [V] 7.0 (TA = +25˚C) 20 18 500 400 ICCT [A] ICTS [A] 16 300 14 12 10 8 200 6 100 4 2 0 2.0 3.0 4.0 5.0 6.0 7.0 VCC [V] 0 2.0 3.0 4.0 5.0 6.0 7.0 VCC [V] ICCT2 – VCC (MB90F598G only, TA = 25˚C) 100 90 ICCT2 [A] 80 70 60 50 40 30 20 10 0 2.0 3.0 4.0 5.0 6.0 7.0 Vcc [V] Document Number: 002-07700 Rev. *B Page 48 of 52 MB90595G Series 13. Ordering Information Part number Package  MB90598GPF MB90F598GPF 100-pin Plastic QFP (PQH100) MB90V595GCR 256-pin Ceramic PGA Document Number: 002-07700 Rev. *B Remarks  For evaluation Page 49 of 52 MB90595G Series 14. Package Dimensions Package Type Package Code QFP 100 PQH100 D D1 4 5 7 80 51 51 81 50 80 50 81 31 100 E1 E 5 7 6 3 4 31 100 1 30 e 3 0.40 C A-B D 30 2 5 7 1 0.20 C A-B D b 0.13 C A-B D BOTTOM VIEW 8 TOP VIEW 2 θ 9 A A' SEATING PLANE L2 c 10 b 0.10 C SECTION A-A' DETAIL A SIDE VIEW SYMBOL DIMENSIONS MIN. NOM. MAX. A1 0.05 0.45 b 0.27 c 0.11 A 3.35 0.32 D 23.90 BSC D1 20.00 BSC e 0.65 BSC E 17.90 BSC E1 θ L 0.37 0.23 14.00 BSC 0° 0.73 8° 0.88 L1 1.95 REF L2 0.25 BSC 1.03 PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3.35 MM PQH100 REV** Document Number: 002-07700 Rev. *B 002-15156 ** Page 50 of 52 MB90595G Series 15. Major Changes Spansion Publication Number: DS07-13705-7E Section  Change Results Deleted the old products, MB90598, MB90F598, and MB90V595.  Changed the series name; MB90595/595G series MB90595G series  Changed the following erroneous name. I/O timer 16-bit Free-run Timer PRODUCT LINEUP One of Standby mode name is changed. Clock mode Watch mode I/O CIRCUIT TYPE Changed Pull-down resistor value of circuit type H. ELECTRICAL CHARACTERISTICS AC Characteristics Add the “External clock input” and “Flash Read cycle time” in (1) Clock Timing Figure in (2) Reset and Hardware Standby Input RST/HST input level of “In Stop Mode” is changed. 0.6 VCC0.2 VCC ELECTRICAL CHARACTERISTICS 5. A/D Converter Changed the items of “Zero transition voltage” and “Full scale transition voltage”. NOTE: Please see “Document History” about later revised information. Document History Document Title: MB90598G/F598G/V595G F2MC-16LX MB90595G Series CMOS 16-bit Proprietary Microcontroller Document Number: 002-07700 Orig. of Change Submission Date AKIH 09/26/2008 Migrated to Cypress and assigned document number 002-07700. No change to document contents or format. 5537128 AKIH 11/30/2016 Updated to Cypress template 6059031 TORS 02/06/2018 Adapted new Cypress logo Updated following package code FPT-100P-M06 → PQH100 Revision ECN **  *A *B Document Number: 002-07700 Rev. *B Description of Change Page 51 of 52 MB90595G Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2008-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-07700 Rev. *B Revised February 6, 2018 Page 52 of 52