MB90F548GPF-G-FLE1

MB90F543G(S)/546G(S)/548G(S)/549G(S)/549G(S)/ V540G/MB90543G(S)/547G(S)/548G(S)/F548GL(S) CMOS F2MC-16LX MB90540G/545G Series 16-bit Proprietary Microcontroller The MB90540G/545G series with FULL-CAN and Flash ROM is specially designed for automotive and industrial applications. Its main features are on-board CAN Interfaces (MB90540G series: 2 channels, MB90545G series: 1 channel) , which conform to CAN V2.0A and V2.0B specifications, supporting very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MCfamily with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing long word data.The MB90540G/545G series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) . Features  Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from : dividedby-2 of oscillation or one to four times the oscillation Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, PLL four times multiplied : machine clock 16 MHz and at operating VCC = 5.0 V)  Subsystem Clock : 32 kHz  Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator Erase can be performed on each block Block protection with external programming voltage  Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Watch mode Hardware stand-by mode  Process 0.5 m CMOS technology  I/O port General-purpose I/O ports : 81 ports  Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit  4 channels 16-bit reload timer : 2 channels  Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions  16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 8 channels Output compare : 4 channels  Program patch function (for two address pointers)  Extended I/O serial interface : 1 channel  Enhanced execution speed : 4-byte Instruction queue  UART0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.  Enhanced interrupt function : 8 levels, 34 factors  Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS)  Embedded ROM size and types MASK ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes Flash ROM : 128 Kbytes/256 Kbytes Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip)  Flash ROM Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Cypress Semiconductor Corporation Document Number: 002- 07696 Rev. *B •  UART 1 (SCI) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial (extended I/O serial) can be used.  External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input.  Delayed interrupt generation module Generates an interrupt request for switching tasks.  8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised 2018 February 5 MB90540G/545G Series Starting by an external trigger input. Conversion time : 26.3 s  FULL-CAN interfaces MB90540G series : 2 channels MB90545G series : 1 channel Conforming to Version 2.0 Part A and Part B Document Number: 002- 07696 Rev. *B Flexible message buffering (mailbox and FIFO buffering can be mixed)  External bus interface : Maximum address space 16 Mbytes  Package: QFP-100, LQFP-100 Page 2 of 70 MB90540G/545G Series Contents Features.............................................................................. 1 Product Lineup .................................................................. 4 Pin Assignment ................................................................. 7 Pin Description .................................................................. 9 I/O Circuit Type ................................................................ 14 Handling Devices............................................................. 17 Block Diagram ................................................................. 21 Memory Map..................................................................... 22 I/O Map.............................................................................. 23 CAN Controller................................................................. 29 Document Number: 002- 07696 Rev. *B Interrupt Map.................................................................... 35 Electrical Characteristics................................................ 37 Example Characteristics................................................. 61 Ordering Information....................................................... 66 Package Dimensions....................................................... 67 Major Changes................................................................. 69 Document History............................................................ 69 Sales, Solutions, and Legal Information ....................... 70 Page 3 of 70 MB90540G/545G Series 1. Product Lineup CPU System clock On-chip PLL clock multiplier (1, 2, 3, 4, 1/2 when PLL stop) Minimum instruction exection time : 62.5 ns (machine clock 16MHz, 4MHz osc. four times multiplied by PLL) MB90F543G(S)/F548G(S) / F548GL(S) : 128 Kbytes MB90F549G(S)/F546G(S) : 256 Kbytes MASK ROM : MB90547G(S): 64 Kbytes MB90543G(S)/548G(S): 128 Kbytes MB90F543G (S) /F549G(S) : 6 Kbytes MB90F546G(S) : 8 Kbytes MB90F543G/F548G/F549G/F546G/ F548GL : Clocks Two clocks system MB90F543GS/F548GS/F549GS/ F546GS/F548GLS : One clock system Operating voltage range External MB90549G(S): 256 Kbytes MB90F548G(S)/F548GL(S): 4 Kbytes RAM MB90V540G F2MC-16LX CPU Flash memory ROM MB90543G (S) MB90547G (S) MB90548G (S) MB90549G (S) MB90F543G (S) /F548G (S) MB90F549G (S) /F546G (S) MB90F548GL(S) Features MB90547G(S): 2 Kbytes MB90548G(S): 4 Kbytes MB90543G(S)/549G(S): 6 Kbytes 8 Kbytes MB90543G/547G/548G/549G : Two clocks system MB90543GS/547GS/548GS/ 549GS : Two clocks system*1 One clock system *3 Temperature range 40 C to 105 C Package QFP100, LQFP100 PGA-256 Emulator-specify power supply*2  None Full duplex double buffer UART0 Support asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock  16 MHz Full duplex double buffer UART1 Asynchronous (start-stop synchronized) and CLK-synchronous communication (SCI) Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous) 62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz Transfer can be started from MSB or LSB Serial I/O Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and nagative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock  16 MHz 10-bit or 8-bit resolution A/D Converter 8 input channels Conversion time : 26.3 s (per one channel) (Continued) Document Number: 002- 07696 Rev. *B Page 4 of 70 MB90540G/545G Series Features 16-bit Reload Timer (2 channels) 16-bit Free-run Timer 16-bit Output Compare (4 channels) 16-bit Input Capture (8 channels) MB90F543G (S) /F548G (S) MB90F549G (S) /F546G (S) MB90F548GL(S) MB90543G (S) MB90547G (S) MB90548G (S) MB90549G (S) MB90V540G Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys  System clock frequency) Supports External Event Count function Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys  System clock freq.) Signals an interrupt when a match with 16-bit Free-run Timer Four 16-bit compare registers A pair of compare registers can be used to generate an output signal Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters 8/16-bit Programmable Pulse Generator (4 channels) Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc  4 MHz (fsys  System clock frequency, fosc  Oscillation clock frequency) Conforms to CAN Specification Version 2.0 Part A and B CAN Interface Automatic re-transmission in case of error MB90540G series Automatic transmission responding to Remote Frame : 2 channels Prioritized 16 massage buffers for data and ID’s supports multipe massages MB90545G series Flexible configuration of acceptance filtering : : 1 channel Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps 32 kHz Sub-clock Sub-clock for low power operation External Interrupt (8 channels) Can be programmed edge sensitive or level sensitive External bus External access using the selectable 8-bit or 16-bit bus is enabled interface (external bus mode.) Virtually all external pins can be used as general purpose I/O I/O Ports All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Sub-clock for 32 kHz Sub clock low power operation Supports automatic programming, Embeded Algorithm Write/Erase/Erase-Suspend/Erase-Resume commands A flag indicating completion of the algorithm Flash Memory Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage *1 : If the one clock system is used, equip X0A and X1A with clocks from the tool side. Document Number: 002- 07696 Rev. *B Page 5 of 70 MB90540G/545G Series *2 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *3 : Operating Voltage Range Products Operation guarantee range MB90F543G(S)/F546G(S)/F548G(S)/ MB90549G(S)/F549G(S)/V540/V540G 4.5 V to 5.5 V MB90F548GL(S)/543G(S)/547G(S)/548G(S) 3.5 V to 5.5 V Document Number: 002- 07696 Rev. *B Page 6 of 70 MB90540G/545G Series 2. Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A PA0 RST P97/RX1 P96/TX1 P95/RX0 P94/TX0 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 HST MD2 P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C P50/SIN2 P51/INT4 P52/INT5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS (TOP VIEW) (PQH100) Document Number: 002- 07696 Rev. *B Page 7 of 70 MB90540G/545G Series 100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 X0A 77 X1A 76 PA0 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RST P97/RX1 P96/TX1 P95/RX0 P94/TX0 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 P50/SIN2 P51/INT4 P52/INT5 P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1 MD2 HST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C (LQI100) Document Number: 002- 07696 Rev. *B Page 8 of 70 MB90540G/545G Series 3. Pin Description Pin No. LQFP*2 Pin name QFP*1 80 81 82 83 X0 X1 78 80 X0A 77 79 X1A Circuit type A (Oscillation) A (Oscillation) Function High speed crystal oscillator input pins Low speed crystal oscillator input pins. For the one clock system parts, perfom external pull-down processing. Low speed crystal oscillator input pins. For the one clock system parts, leave it open. 75 77 RST B External reset request input pin 50 52 HST C Hardware standby input pin P00 to P07 83 to 90 91 to 98 99 to 6 7 8 10 85 to 92 I AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. P10 to P17 General I/O port with programmable pullup. This function is enabled in the single-chip mode. 93 to 100 I AD08 to AD15 I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled. P20 to P27 General I/O port with programmable pullup. In external bus mode, this function is valid when the corresponding bits in the external address output control resister (HACR) are set to “1”. 1 to 8 I A16 to A23 8-bit I/O pins for A16 to A23 at the external address/data bus. In external bus mode, this function is valid when the corresponding bits in the external address output control resister (HACR) are set to “0”. P30 General I/O port with programmable pullup. This function is enabled in the single-chip mode. 9 I ALE Address latch enable output pin. This function is enabled when the external bus is enabled. P31 General I/O port with programmable pullup. This function is enabled in the single-chip mode. 10 12 General I/O port with programmable pullup. This function is enabled in the single-chip mode. I RD Read strobe output pin for the data bus. This function is enabled when the external bus is enabled. P32 General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the WR/WRL pin output is disabled. WRL WR I Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is writestrobe output pin for the lower 8 bits of the data bus in 16-bit access. WR is write-strobe output pin for the 8 bits of the data bus in 8-bit access. (Continued) Document Number: 002- 07696 Rev. *B Page 9 of 70 MB90540G/545G Series Pin No. LQFP*2 QFP*1 Pin name Circuit type General I/O port with programmable pullup. This function is enabled in the single-chip mode, external bus 8-bit mode or when WRH pin output is disabled. P33 11 12 13 14 15 16 17 13 I WRH Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. P34 General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the hold function is disabled. 14 I HRQ Hold request input pin. This function is enabled when both the external bus and the hold functions are enabled. P35 General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the hold function is disabled. 15 I HAK Hold acknowledge output pin. This function is enabled when both the external bus and the hold functions are enabled. P36 General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the external ready function is disabled. 16 I RDY Ready input pin. This function is enabled when both the external bus and the external ready functions are enabled. P37 General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the CLK output is disabled. 17 H CLK CLK output pin. This function is enabled when both the external bus and CLK outputs are enabled. P40 General I/O port. This function is enabled when UART0 disables the serial data output. 18 G SOT0 Serial data output pin for UART0. This function is enabled when UART0 enables the serial data output. P41 General I/O port. This function is enabled when UART0 disables serial clock output. 19 G SCK0 P42 18 20 19 21 Function SIN0 General I/O port. This function is always enabled. G P43 SIN1 Serial clock I/O pin for UART0. This function is enabled when UART0 enables the serial clock output. Serial data input pin for UART0. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. G Serial data input pin for UART1. Set the corresponding Port Direction Register to input if this function is used. (Continued) Document Number: 002- 07696 Rev. *B Page 10 of 70 MB90540G/545G Series Pin No. LQFP*2 QFP*1 Pin name Circuit type P44 20 22 23 24 22 G Serial clock pulse I/O pin for UART1. This function is enabled when UART1 enables the serial clock output. P45 General I/O port. This function is enabled when UART1 disables the serial data output. G SOT1 Serial data output pin for UART1. This function is enabled when UART1 enables the serial data output. P46 General I/O port. This function is enabled when the Extended I/O serial interface disables the serial data output. 25 G SOT2 Serial data output pin for the Extended I/O serial interface. This function is enabled when the Extended I/O serial interface enables the serial data output. P47 General I/O port. This function is enabled when the Extended I/O serial interface disables the clock output. 26 G SCK2 P50 28 27 to 30 29 to 32 31 33 SIN2 INT4 to INT7 41 to 44 E General I/O port. This function is enabled when the analog input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. P64 to P67 General I/O port. The function is enabled when the analog input enable register specifies a port. 43 to 46 E P56 47 Trigger input pin for the A/D converter. Set the corresponding Port Direction Register to input if this function is used. AN0 to AN3 AN4 to AN7 45 External interrupt request input pins for INT4 to INT7. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. D P60 to P63 38 to 41 Serial data input pin for the Extended I/O serial interface . Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. D P55 ADTG Serial clock pulse I/O pin for the Extended I/O serial interface . This function is enabled when the Extended I/O serial interface enables the Serial clock output. General I/O port. This function is always enabled. D P51 to P54 36 to 39 General I/O port. This function is enabled when UART1 disables the clock output. SCK1 24 26 Function TIN0 Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O port. This function is always enabled. D Event input pin for the 16-bit reload timers 0. Set the corresponding Port Direction Register to input if this function is used. (Continued) Document Number: 002- 07696 Rev. *B Page 11 of 70 MB90540G/545G Series Pin No. LQFP*2 QFP*1 Pin name Circuit type P57 46 51 to 56 48 53 to 58 D 59 to 62 63 , 64 59 , 60 Output pin for the 16-bit reload timers 0. This function is enabled when the 16-bit reload timers 0 enables the output. P70 to P75 General I/O ports. This function is always enabled. IN0 to IN5 D OUT2 , OUT3 D Trigger input pins for input captures ICU6 and ICU7. Set the corresponding Port Direction Register to input and disable the OCU waveform output if this function is used. P80 to P83 General I/O ports. This function is enabled when 8/16-bit PPG disables the waveform output. D PPG0 to PPG3 Output pins for 8/16-bit PPGs. This function is enabled when 8/16-bit PPG enables the waveform output. P84 , P85 General I/O ports. This function is enabled when the OCU disables the waveform output. 65 , 66 D P86 TIN1 68 D TOT1 P90 to P93 67 to 70 69 to 72 71 73 INT0 to INT3 Input pin for the 16-bit reload timers 1. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when the 16-bit reload timers 1 disables the output. Output pin for the 16-bit reload timers 1.This function is enabled when the 16bit reload timers 1 enables the output. General I/O port. This function is always enabled. D P94 TX0 Waveform output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables the waveform output. General I/O port. This function is always enabled. D P87 66 Event output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables the waveform output. IN6 , IN7 61 to 64 67 Trigger input pins for input captures ICU0 to ICU5. Set the corresponding Port Direction Register to input if this function is used. General I/O ports. This function is enabled when the OCU disables the waveform output. OUT0 , OUT1 65 General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output. TOT0 P76 , P77 57 , 58 Function External interrupt request input pins for INT0 to INT3. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when CAN0 disables the output. D TX output pin for CAN0. This function is enabled when CAN0 enables the output. (Continued) Document Number: 002- 07696 Rev. *B Page 12 of 70 MB90540G/545G Series (Continued) Pin No. LQFP Pin name QFP*1 *2 Circuit type P95 72 74 73 75 74 76 76 78 RX0 General I/O port. This function is always enabled. D P96 TX1 Function RX input pin for CAN0 Interface. When the CAN function is used, output from the other functions must be stopped. General I/O port. This function is enabled when CAN1 disables the output. D P97 TX output pin for CAN1. This function is enabled when CAN1 enables the output (only MB90540G series) . General I/O port. This function is always enabled. D RX input pin for CAN1 Interface. When the CAN function is used, output from the other functions must be stopped (only MB90540G series) . PA0 D General I/O port. This function is always enabled. Power supply pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVCC is applied to VCC. RX1 32 34 AVCC Power supply 35 37 AVSS Power supply Power supply pin for the A/D Converter. 33 35 AVRH Power supply External reference voltage input pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. 34 36 AVRL Power supply External reference voltage input pin for the A/D Converter. 47, 48 49, 50 MD0, MD1 C Input pins for specifying the operating mode. The pins must be directly connected to VCC or VSS. 49 51 MD2 F Input pin for specifying the operating mode. The pin must be directly connected to VCC or VSS. 25 27 C  Power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. 21, 82 23, 84 VCC Power supply Input pin for power supply (5.0 V) . 9, 40, 79 11, 42, 81 VSS Power supply Input pin for power supply (0.0 V) . *1 : PQH100 *2 : LQI100 Document Number: 002- 07696 Rev. *B Page 13 of 70 MB90540G/545G Series 4. I/O Circuit Type Circuit type Diagram Remarks  High-speed oscillation feedback resistor : 1 M approx. X1, X1A  Low-speed oscillation feedback resistor: 10 M approx. X0, X0A A Standby control signal  CMOS Hysteresis input  Pull-up resistor : 50 k approx. B R (Pull-up) R CMOS Hysteresis input R CMOS Hysteresis input  CMOS Hysteresis input C  CMOS level output VCC  CMOS Hysteresis input P-ch D N-ch R CMOS Hysteresis input (Continued) Document Number: 002- 07696 Rev. *B Page 14 of 70 MB90540G/545G Series Circuit type Diagram Remarks  CMOS level output  CMOS Hysteresis input VCC P-ch  Analog input N-ch E P-ch Analog input N-ch CMOS Hysteresis input R  CMOS Hysteresis input CMOS Hysteresis input R  Pull-down Resistor : 50 k approx. (except Flash devices) F R (Pull-down)  CMOS level output  CMOS Hysteresis input VCC P-ch  TTL level input (Flash devices in Flash writer mode only) N-ch G CMOS Hysteresis input R R T TTL level input (Continued) Document Number: 002- 07696 Rev. *B Page 15 of 70 MB90540G/545G Series (Continued) Circuit type Diagram Remarks  CMOS level output  CMOS Hysteresis input VCC CNTL  Programmable pull-up resistor : 50 k approx. VCC P-ch P-ch H N-ch CMOS Hysteresis input R  CMOS level output  CMOS Hysteresis input VCC CNTL  TTL level input (Flash devices in Flash writer mode only) P-ch  Programmable pullup resistor : 50 k approx. VCC P-ch I N-ch CMOS Hysteresis input R R T Document Number: 002- 07696 Rev. *B TTL level input Page 16 of 70 MB90540G/545G Series 5. Handling Devices (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions :  A voltage higher than VCC or lower than VSS is applied to an input or output pin.  A voltage higher than the rated voltage is applied between VCC and VSS.  The AVcc power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, care must also be taken in not allowing the analog power-supply voltage (AVCC, AVRH) to exceed the digital power-supply voltage. (2) Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) Using external clock To use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock. MB90540G/545G Series X0 Open X1 (4) Use of the sub-clock Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins. (5) Power supply pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electromagnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device. VCC VSS VCC VSS VSS VCC MB90540G/545G Series VCC VSS VSS Document Number: 002- 07696 Rev. *B VCC Page 17 of 70 MB90540G/545G Series (6) Pull-up/down resistors The MB90540G/545G Series does not support internal pull-up/down resistors (except Port0 external components where needed.  Port3 : pull-up resistors) . Use (7) Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation. (8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . (9) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC  VCC, AVSS  AVRH  VSS. (10) N.C. Pin The N.C. (internally connected) pin must be opened for use. (11) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V) . Document Number: 002- 07696 Rev. *B Page 18 of 70 MB90540G/545G Series (12) Indeterminate outputs from ports 0 and 1 (MB90V540G only) During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state.  If RST pin is “H”, the outputs become indeterminate.  If RST pin is “L”, the outputs become high-impedance. Pay attention to the port output timing shown as follow.  RST pin is “H” Oscillation setting time*2 Power-on reset*1 VCC (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminated *1 : Power-on reset time : “Period of clock frequency”  217 (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : “Period of clock frequency”  218 (Clock frequency of 16 MHz : 16.38 ms) Document Number: 002- 07696 Rev. *B Page 19 of 70 MB90540G/545G Series  RST pin is “L” Oscillation setting time*2 Power-on reset*1 VCC (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1 : Power-on reset time : “Period of clock frequency”  217 (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : “Period of clock frequency”  218 (Clock frequency of 16 MHz : 16.38 ms) (13) Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (14) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00H”. If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (15) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (16) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. Document Number: 002- 07696 Rev. *B Page 20 of 70 MB90540G/545G Series 6. Block Diagram X0, X1 X0A, X1A RST Clock Controller F2MC 16LX CPU HST 16-bit Free-run Timer RAM 2 K/4 K/6 K/8 K 16-bit Input Capture 8 ch. ROM/Flash 128 K/256 K/ 64K(ROM only) 16-bit Output Compare 4 ch. IN0 to IN5 IN6/OUT2, IN7/OUT3 OUT0, OUT1 Prescaler 8/16-bit PPG 4 ch. SOT0 SCK0 UART0 PPG0 to PPG3 SIN0 SOT1 SCK1 UART1 (SCI) SIN1 FMC-16 Bus Prescaler CAN Controller RX0, RX1 * 16-bit Reload Timer 2 ch. TIN0, TIN1 TX0, TX1 * TOT0, TOT1 Prescaler AD00 to AD15 SOT2 SCK2 A16 to A23 Serial I/O ALE SIN2 RD External Bus Interface AVCC AVSS AN0 to AN7 AVRH AVRL WRL WRH HRQ 10-bit A/D Converter 8 ch. HAK RDY CLK ADTG External Interrupt 8 ch. INT0 to INT7 * : Only the MB90540G series has two channels Document Number: 002- 07696 Rev. *B Page 21 of 70 MB90540G/545G Series 7. Memory Map The memory space of the MB90540G/545G Series is shown below. MB90V540G/ F546G (S) FFFFFFH FFFFFFH ROM (FF bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) MB90548G(S) MB90F548GL(S) MB90F548G (S) MB90543G(S) F543G(S) FE0000H ROM (FF bank) FE0000H ROM (FD bank) External ROM (FC bank) ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) External FC0000H FE0000H FDFFFFH FD0000H FCFFFFH MB90547G (S) FFFFFFH FFFFFFH FF0000H FEFFFFH ROM (FE bank) MB90549G (S) / F549G (S) ROM (FF bank) FF0000H ROM (FE bank) ROM (FD bank) External ROM (FC bank) FC0000H External External 00FFFFH 00FFFFH 004000H ROM (Image of FF bank) 003FFFH 00FFFFH 004000H ROM (Image of FF bank) 003FFFH 002000H ROM (Image of FF bank) 003FFFH 003900H External 004000H Peripheral Peripheral 003900H 00FFFFH 004000H Peripheral 002000H ROM (Image of FF bank) 003FFFH 003900H External 00FFFFH Peripheral Peripheral 003900H External 004000H 003FFFH 002100H ROM (Image of FF bank) 003900H External External 002000H 0020FFH 001FF5H ROM correction 001FF0H 0018FFH 0018FFH RAM 6 K 0010FFH RAM 8 K 000100H 000100H 000000H Peripheral 000100H 0008FFH 0000BFH 000000H Peripheral 0000BFH 000000H RAM 2 K 000100H External External External 0000BFH RAM 6 K RAM 4 K Peripheral 000100H External 0000BFH 000000H External 0000BFH Peripheral Peripheral 000000H Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced without using the “far” specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF. Document Number: 002- 07696 Rev. *B Page 22 of 70 MB90540G/545G Series 8. I/O Map Address Register Abbreviation Access Resource name Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB 0AH Port A data register PDRA R/W Port A _ _ _ _ _ _ _XB 0BH to 0FH Reserved 10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B 11H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B 12H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B 13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B 14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B 15H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B 16H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B 17H Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B 18H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B 19H Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B 1AH Port A direction register DDRA R/W Port A _ _ _ _ _ _ _0B 1BH Analog Input Enable register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B 1CH Port 0 Pullup control register PUCR0 R/W Port 0 0 0 0 0 0 0 0 0B 1DH Port 1 Pullup control register PUCR1 R/W Port 1 0 0 0 0 0 0 0 0B 1EH Port 2 Pullup control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B 1FH Port 3 Pullup control register PUCR3 R/W Port 3 0 0 0 0 0 0 0 0B 20H Serial Mode Control Register 0 UMC0 R/W 21H Serial Status Register 0 USR0 R/W 22H Serial input data register 0/ Serial output data register 0 UIDR0/UODR0 R/W 23H Rate and data register 0 URD0 R/W 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B UART0 XXXXXXXXB 0 0 0 0 0 0 0XB (Continued) Document Number: 002- 07696 Rev. *B Page 23 of 70 MB90540G/545G Series Address Register Abbreviation Access Resource name Initial value 24H Serial mode register 1 SMR1 R/W 0 0 0 0 0 0 0 0B 25H Serial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0B 26H Serial input data register 1/ Serial output data register 1 SIDR1/SODR1 R/W 27H Serial status register 1 SSR1 R/W 0 0 0 0 1_0 0B 28H UART1 prescaler control register CDCR R/W 0_ _ _1 1 1 1B 29H Serial Edge select register SES1 R/W _ _ _ _ _ _ _0B 2AH Prohibited 2BH Serial I/O prescaler SCDCR R/W 0_ _ _1 1 1 1B 2CH Serial mode control register SMCS R/W 2DH Serial mode control register SMCS R/W 2EH Serial data register SDR R/W XXXXXXXXB 2FH Serial Edge select register SES2 R/W _ _ _ _ _ _ _0B 30H External interrupt enable register ENIR R/W 0 0 0 0 0 0 0 0B 31H External interrupt request register EIRR R/W 32H External interrupt level register ELVR R/W 33H External interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B 34H A/D control status register 0 ADCS0 R/W 0 0 0 0 0 0 0 0B 35H A/D control status register 1 ADCS1 R/W 36H A/D data register 0 ADCR0 R 37H A/D data register 1 ADCR1 R/W 38H PPG0 operation mode control register PPGC0 R/W 39H PPG1 operation mode control register PPGC1 R/W 3AH PPG0/1 clock selection register PPG01 R/W PPGC2 R/W 3BH Prohibited 3CH PPG2 operation mode control register 3DH PPG3 operation mode control register PPGC3 R/W 3EH PPG2/3 Clock Selection Register PPG23 R/W 3FH Prohibited 40H PPG4 operation mode control register PPGC4 R/W 41H PPG5 operation mode control register PPGC5 R/W 42H PPG4/5 clock selection register PPG45 R/W 43H Prohibited 44H PPG6 operation mode control register PPGC6 R/W 45H PPG7 operation mode control register PPGC7 R/W 46H PPG6/7 clock selection register PPG67 R/W UART1 XXXXXXXXB _ _ _ _0 0 0 0B Extended I/O Serial Interface External Interrupt A/D Converter 0 0 0 0 0 0 1 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 _ XXB 0 _ 0 0 0 _ _ 1B 16-bit Programmable 0 _ 0 0 0 0 0 1B Pulse Generator 0/1 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _1B 16-bit Programmable 0 _ 0 0 0 0 0 1B Pulse Generator 2/3 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 16-bit Programmable 0 _ 0 0 0 0 0 1B Pulse Generator 4/5 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 16-bit Programmable 0 _ 0 0 0 0 0 1B Pulse Generator 6/7 0 0 0 0 0 0 _ _B (Continued) Document Number: 002- 07696 Rev. *B Page 24 of 70 MB90540G/545G Series Address Register Abbreviation Access Resource name Initial value 47H to 4BH Prohibited 4CH Input capture control status register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B 4DH Input capture control status register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B 4EH Input capture control status register 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B 4FH Input capture control status register 6/7 ICS67 R/W Input Capture 6/7 0 0 0 0 0 0 0 0B 50H Timer control status register 0 TMCSR0 R/W 0 0 0 0 0 0 0 0B 51H Timer control status register 0 TMCSR0 R/W _ _ _ _ 0 0 0 0B 52H Timer register 0/reload register 0 TMR0/TMRLR0 R/W 53H Timer register 0/reload register 0 TMR0/TMRLR0 R/W XXXXXXXXB 54H Timer control status register 1 TMCSR1 R/W 0 0 0 0 0 0 0 0B 55H Timer control status register 1 TMCSR1 R/W 56H Timer register 1/reload register 1 TMR1/TMRLR1 R/W 57H Timer register 1/reload register 1 TMR1/TMRLR1 R/W 58H Output compare control status register 0 OCS0 R/W 59H Output compare control status register 1 OCS1 R/W 5AH Output compare control status register 2 OCS2 R/W 5BH Output compare control status register 3 OCS3 R/W 5CH to 6BH Prohibited 6CH Timer Data register TCDT R/W 6DH Timer Data register TCDT R/W 6EH Timer Control register TCCS R/W 6FH ROM mirror function selection register ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B 70H to 7FH Reserved for CAN 0 Interface. 80H to 8FH Reserved for CAN 1 Interface. 90H to 9DH Prohibited 9EH Program address detection control status register PACSR R/W Address Match Detection Function 0 0 0 0 0 0 0 0B 9FH Delayed interrupt/release register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B 16-bit Reload Timer 0 16-bit Reload Timer 1 XXXXXXXXB _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB Output Compare 0/1 Output Compare 2/3 0 0 0 0 _ _ 0 0B _ _ _0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B 0 0 0 0 0 0 0 0B I/O Timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B A0H Low-power mode control register LPMCR R/W Low Power Controller A1H Clock selection register CKSCR R/W Low Power Controller (Continued) Document Number: 002- 07696 Rev. *B Page 25 of 70 MB90540G/545G Series Address Register A2H to A4H Prohibited A5H Automatic ready function select register Abbreviation ARSR Access Resource name W Initial value 0 0 1 1 _ _ 0 0B External Memory Access A6H External address output control register HACR W A7H Bus control signal selection register ECSR W A8H Watchdog Timer control register WDTC R/W Watchdog Timer XXXXX 1 1 1B A9H Time Base Timer Control register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B AAH Watch timer control register WTC R/W Watch Timer 1 X 0 0 0 0 0 0B ABH to ADH Prohibited AEH Flash memory control status register (Flash only, otherwise reserved) FMCS R/W Flash Memory 0 0 0 X 0 0 0 0B AFH Prohibited B0H Interrupt control register 00 ICR00 R/W 0 0 0 0 0 1 1 1B B1H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B B2H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B B3H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B B4H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B B5H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B B6H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B BAH Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B BBH Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B BCH Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B BDH Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B BEH Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B BFH Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B C0H to FFH External Address Register Abbreviation Access 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 _B Interrupt controller Resource name 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Initial value 1FF0H Program address detection register 0 PADR0 R/W XXXXXXXXB 1FF1H Program address detection register 0 PADR0 R/W XXXXXXXXB 1FF2H Program address detection register 0 PADR0 R/W 1FF3H Program address detection register 1 PADR1 R/W 1FF4H Program address detection register 1 PADR1 R/W XXXXXXXXB 1FF5H Program address detection register 1 PADR1 R/W XXXXXXXXB Address Match Detection Function XXXXXXXXB XXXXXXXXB (Continued) Document Number: 002- 07696 Rev. *B Page 26 of 70 MB90540G/545G Series Address Register Abbreviation Access Resource name Initial value 3900H Reload L PRLL0 R/W 3901H Reload H PRLH0 R/W 3902H Reload L PRLL1 R/W 3903H Reload H PRLH1 R/W XXXXXXXXB 3904H Reload L PRLL2 R/W XXXXXXXXB 3905H Reload H PRLH2 R/W 3906H Reload L PRLL3 R/W 3907H Reload H PRLH3 R/W XXXXXXXXB 3908H Reload L PRLL4 R/W XXXXXXXXB 3909H Reload H PRLH4 R/W 390AH Reload L PRLL5 R/W 390BH Reload H PRLH5 R/W XXXXXXXXB 390CH Reload L PRLL6 R/W XXXXXXXXB 390DH Reload H PRLH6 R/W 390EH Reload L PRLL7 R/W 390FH Reload H PRLH7 R/W XXXXXXXXB 3910H to 3917H Reserved 3918H Input Capture Register 0 IPCP0 R XXXXXXXXB 3919H Input Capture Register 0 IPCP0 R 391AH Input Capture Register 1 IPCP1 R 391BH Input Capture Register 1 IPCP1 R XXXXXXXXB 391CH Input Capture Register 2 IPCP2 R XXXXXXXXB 391DH Input Capture Register 2 IPCP2 R 391EH Input Capture Register 3 IPCP3 R 391FH Input Capture Register 3 IPCP3 R XXXXXXXXB 3920H Input Capture Register 4 IPCP4 R XXXXXXXXB 3921H Input Capture Register 4 IPCP4 R 3922H Input Capture Register 5 IPCP5 R 3923H Input Capture Register 5 IPCP5 R XXXXXXXXB 3924H Input Capture Register 6 IPCP6 R XXXXXXXXB 3925H Input Capture Register 6 IPCP6 R 3926H Input Capture Register 7 IPCP7 R 3927H Input Capture Register 7 IPCP7 R XXXXXXXXB 16-bit Programmable Pulse Generator 0/1 16-bit Programmable Pulse Generator 2/3 16-bit Programmable Pulse Generator 4/5 16-bit Programmable Pulse Generator 6/7 Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 Input Capture 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) Document Number: 002- 07696 Rev. *B Page 27 of 70 MB90540G/545G Series (Continued) Address Register Abbreviation Access Resource name Initial value 3928H Output Compare Register 0 OCCP0 R/W 3929H Output Compare Register 0 OCCP0 R/W 392AH Output Compare Register 1 OCCP1 R/W 392BH Output Compare Register 1 OCCP1 R/W XXXXXXXXB 392CH Output Compare Register 2 OCCP2 R/W XXXXXXXXB 392DH Output Compare Register 2 OCCP2 R/W 392EH Output Compare Register 3 OCCP3 R/W 392FH Output Compare Register 3 OCCP3 R/W 3930H to 39FFH Reserved 3A00H to 3AFFH Reserved for CAN 0 Interface. 3B00H to 3BFFH Reserved for CAN 0 Interface. 3C00H to 3CFFH Reserved for CAN 1 Interface. 3D00H to 3DFFH Reserved for CAN 1 Interface. 3E00H to 3FFFH Reserved XXXXXXXXB Output Compare 0/1 Output Compare 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB  Read/write notation R/W : Reading and writing permitted R : Read-only W : Write-only  Initial value notation 0 : Initial value is “0”. 1 : Initial value is “1”. X : Initial value is undefined. _ : Initial value is unused. Note: Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading “X”. Document Number: 002- 07696 Rev. *B Page 28 of 70 MB90540G/545G Series 9. CAN Controller The MB90540G series contains two CAN controllers (CAN0 and CAN1) , the MB90545G series contains only one (CAN0) . The Evaluation Chip MB90V540G also has two CAN controllers. The CAN controller has the following features :  Conforms to CAN Specification Version 2.0 Part A and B ❐ Supports transmission/reception in standard frame and extended frame formats  Supports transmission of data frames by receiving remote frames  16 transmitting/receiving message buffers ❐ 29-bit ID and 8-byte data ❐ Multi-level message buffer configuration  Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask ❐ Two acceptance mask registers in either standard frame format or extended frame formats  Bit rate programmable from 10 Kbps to 1 Mbps (when input clock is at 16 MHz) List of Control Registers Address CAN0 Register CAN1 000070H 000080H 000071H 000081H 000072H 000082H 000073H 000083H 000074H 000084H 000075H 000085H 000076H 000086H 000077H 000087H 000078H 000088H 000079H 000089H 00007AH 00008AH 00007BH 00008BH 00007CH 00008CH 00007DH 00008DH 00007EH 00008EH 00007FH 00008FH Abbreviation Access Initial Value Message buffer valid register BVALR R/W 00000000 00000000B Transmit request register TREQR R/W 00000000 00000000B Transmit cancel register TCANR W 00000000 00000000B Transmit complete register TCR R/W 00000000 00000000B Receive complete register RCR R/W 00000000 00000000B Remote request receiving register RRTRR R/W 00000000 00000000B Receive overrun register ROVRR R/W 00000000 00000000B Receive interrupt enable register RIER R/W 00000000 00000000B (Continued) Document Number: 002- 07696 Rev. *B Page 29 of 70 MB90540G/545G Series (Continued) Address CAN0 Register CAN1 003B00H 003D00H 003B01H 003D01H 003B02H 003D02H 003B03H 003D03H 003B04H 003D04H 003B05H 003D05H 003B06H 003D06H 003B07H 003D07H 003B08H 003D08H 003B09H 003D09H 003B0AH 003D0AH 003B0BH 003D0BH 003B0CH 003D0CH 003B0DH 003D0DH 003B0EH 003D0EH 003B0FH 003D0FH 003B10H 003D10H 003B11H 003D11H 003B12H 003D12H 003B13H 003D13H 003B14H 003D14H 003B15H 003D15H 003B16H 003D16H 003B17H 003D17H 003B18H 003D18H 003B19H 003D19H 003B1AH 003D1AH 003B1BH 003D1BH Abbreviation Access Initial Value Control status register CSR R/W, R 00---000 0----0-1B Last event indicator register LEIR R/W -------- 000-0000B Receive/transmit error counter register RTEC R 00000000 00000000B Bit timing register BTR R/W -1111111 11111111B IDE register IDER R/W XXXXXXXX XXXXXXXXB Transmit RTR register TRTRR R/W 00000000 00000000B Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXXB Transmit request enable register TIER R/W 00000000 00000000B Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXXB List of Message Buffers (ID Registers) Address CAN0 Register CAN1 003A00H to 003A1FH 003C00H to 003C1FH 003A20H 003C20H 003A21H 003C21H 003A22H 003C22H 003A23H 003C23H Abbreviation Access General-purpose RAM  R/W ID register 0 IDR0 R/W Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXX XXXXXXXXB Document Number: 002- 07696 Rev. *B XXXXX--- XXXXXXXXB Page 30 of 70 MB90540G/545G Series Address CAN0 Register CAN1 003A24H 003C24H 003A25H 003C25H 003A26H 003C26H 003A27H 003C27H 003A28H 003C28H 003A29H 003C29H 003A2AH 003C2AH 003A2BH 003C2BH 003A2CH 003C2CH 003A2DH 003C2DH 003A2EH 003C2EH 003A2FH 003C2FH 003A30H 003C30H 003A31H 003C31H 003A32H 003C32H 003A33H 003C33H 003A34H 003C34H 003A35H 003C35H 003A36H 003C36H 003A37H 003C37H 003A38H 003C38H 003A39H 003C39H 003A3AH 003C3AH 003A3BH 003C3BH Abbreviation Access Initial Value XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 5 IDR5 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 6 IDR6 R/W XXXXX--- XXXXXXXXB (Continued) Document Number: 002- 07696 Rev. *B Page 31 of 70 MB90540G/545G Series (Continued) Address CAN0 Register CAN1 003A3CH 003C3CH 003A3DH 003C3DH 003A3EH 003C3EH 003A3FH 003C3FH 003A40H 003C40H 003A41H 003C41H 003A42H 003C42H 003A43H 003C43H 003A44H 003C44H 003A45H 003C45H 003A46H 003C46H 003A47H 003C47H 003A48H 003C48H 003A49H 003C49H 003A4AH 003C4AH 003A4BH 003C4BH 003A4CH 003C4CH 003A4DH 003C4DH 003A4EH 003C4EH 003A4FH 003C4FH 003A50H 003C50H 003A51H 003C51H 003A52H 003C52H 003A53H 003C53H 003A54H 003C54H 003A55H 003C55H 003A56H 003C56H 003A57H 003C57H 003A58H 003C58H 003A59H 003C59H 003A5AH 003C5AH 003A5BH 003C5BH 003A5CH 003C5CH 003A5DH 003C5DH 003A5EH 003C5EH 003A5FH 003C5FH Abbreviation Access Initial Value XXXXXXXX XXXXXXXXB ID register 7 IDR7 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 8 IDR8 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 15 Document Number: 002- 07696 Rev. *B IDR15 R/W XXXXX--- XXXXXXXXB Page 32 of 70 MB90540G/545G Series List of Message Buffers (DLC Registers and Data Registers) Address CAN0 Register CAN1 003A60H 003C60H 003A61H 003C61H 003A62H 003C62H 003A63H 003C63H 003A64H 003C64H 003A65H 003C65H 003A66H 003C66H 003A67H 003C67H 003A68H 003C68H 003A69H 003C69H 003A6AH 003C6AH 003A6BH 003C6BH 003A6CH 003C6CH 003A6DH 003C6DH 003A6EH 003C6EH 003A6FH 003C6FH 003A70H 003C70H 003A71H 003C71H 003A72H 003C72H 003A73H 003C73H 003A74H 003C74H 003A75H 003C75H 003A76H 003C76H 003A77H 003C77H 003A78H 003C78H 003A79H 003C79H 003A7AH 003C7AH 003A7BH 003C7BH 003A7CH 003C7CH 003A7DH 003C7DH 003A7EH 003C7EH 003A7FH 003C7FH 003A80H to 003A87H 003C80H to 003C87H Abbreviation Access Initial Value DLC register 0 DLCR0 R/W ----XXXXB DLC register 1 DLCR1 R/W ----XXXXB DLC register 2 DLCR2 R/W ----XXXXB DLC register 3 DLCR3 R/W ----XXXXB DLC register 4 DLCR4 R/W ----XXXXB DLC register 5 DLCR5 R/W ----XXXXB DLC register 6 DLCR6 R/W ----XXXXB DLC register 7 DLCR7 R/W ----XXXXB DLC register 8 DLCR8 R/W ----XXXX DLC register 9 DLCR9 R/W ----XXXXB DLC register 10 DLCR10 R/W ----XXXXB DLC register 11 DLCR11 R/W ----XXXXB DLC register 12 DLCR12 R/W ----XXXXB DLC register 13 DLCR13 R/W ----XXXXB DLC register 14 DLCR14 R/W ----XXXXB DLC register 15 DLCR15 R/W ----XXXXB Data register 0 (8 bytes) DTR0 R/W XXXXXXXXB to XXXXXXXXB (Continued) Document Number: 002- 07696 Rev. *B Page 33 of 70 MB90540G/545G Series (Continued) Address CAN0 Register CAN1 Abbreviation Access Initial Value 003A88H to 003A8FH 003C88H to 003C8FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXXB to XXXXXXXXB 003A90H to 003A97H 003C90H to 003C97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXXB to XXXXXXXXB 003A98H to 003A9FH 003C98H to 003C9FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXXB to XXXXXXXXB 003AA0H to 003AA7H 003CA0H to 003CA7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXXB to XXXXXXXXB 003AA8H to 003AAFH 003CA8H to 003CAFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXXB to XXXXXXXXB 003AB0H to 003AB7H 003CB0H to 003CB7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXXB to XXXXXXXXB 003AB8H to 003ABFH 003CB8H to 003CBFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXXB to XXXXXXXXB 003AC0H to 003AC7H 003CC0H to 003CC7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXXB to XXXXXXXXB 003AC8H to 003ACFH 003CC8H to 003CCFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXXB to XXXXXXXXB 003AD0H to 003AD7H 003CD0H to 003CD7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXXB to XXXXXXXXB 003AD8H to 003ADFH 003CD8H to 003CDFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXXB to XXXXXXXXB 003AE0H to 003AE7H 003CE0H to 003CE7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXXB to XXXXXXXXB 003AE8H to 003AEFH 003CE8H to 003CEFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXXB to XXXXXXXXB 003AF0H to 003AF7H 003CF0H to 003CF7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXXB to XXXXXXXXB 003AF8H to 003AFFH 003CF8H to 003CFFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXXB to XXXXXXXXB Document Number: 002- 07696 Rev. *B Page 34 of 70 MB90540G/545G Series 10. Interrupt Map Interrupt cause Reset EI2OS clear N/A Interrupt vector Number #08 Interrupt control register Address FFFFDCH INT9 instruction N/A #09 FFFFD8H Exception N/A #10 FFFFD4H CAN 0 RX N/A #11 FFFFD0H CAN 0 TX/NS N/A #12 FFFFCCH CAN 1 RX N/A #13 FFFFC8H CAN 1 TX/NS N/A #14 FFFFC4H External Interrupt INT0/INT1 *1 #15 FFFFC0H Time Base Timer N/A #16 FFFFBCH 16-bit Reload Timer 0 *1 #17 FFFFB8H 8/10-bit A/D Converter *1 #18 FFFFB4H 16-bit Free-run Timer N/A #19 FFFFB0H External Interrupt INT2/INT3 *1 #20 FFFFACH Serial I/O *1 #21 FFFFA8H 8/16-bit PPG 0/1 N/A #22 FFFFA4H Input Capture 0 *1 #23 FFFFA0H External Interrupt INT4/INT5 *1 #24 FFFF9CH Input Capture 1 *1 #25 FFFF98H 8/16-bit PPG 2/3 N/A #26 FFFF94H External Interrupt INT6/INT7 *1 #27 FFFF90H Watch Timer N/A #28 FFFF8CH 8/16-bit PPG 4/5 N/A #29 FFFF88H Input Capture 2/3 *1 #30 FFFF84H 8/16-bit PPG 6/7 N/A #31 FFFF80H Output Compare 0 *1 #32 FFFF7CH Output Compare 1 *1 #33 FFFF78H Input Capture 4/5 *1 #34 FFFF74H Output Compare 2/3 - Input Capture 6/7 *1 #35 FFFF70H 16-bit Reload Timer 1 *1 #36 FFFF6CH UART 0 RX *2 #37 FFFF68H UART 0 TX *1 #38 FFFF64H UART 1 RX *2 #39 FFFF60H UART 1 TX *1 #40 FFFF5CH Flash Memory N/A #41 FFFF58H Delayed interrupt N/A #42 FFFF54H Number Address       ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH (Continued) Document Number: 002- 07696 Rev. *B Page 35 of 70 MB90540G/545G Series (Continued) *1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. *2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. Notes :  N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.  For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal.  At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number.  If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. Document Number: 002- 07696 Rev. *B Page 36 of 70 MB90540G/545G Series 11. Electrical Characteristics 11.1 Absolute Maximum Ratings (VSS  AVSS  0.0 V) Parameter Symbol VCC Power supply voltage Value Min VSS  0.3 Max VSS  6.0 V Remarks AVCC VSS  0.3 AVRH, AVRL VSS  0.3 VSS  6.0 V VSS  0.3 VSS  6.0 AVCC  AVRH/AVRL, AVRH  AVRL *1 V *2 Input voltage VI Output voltage VO Maximum clamp current ICLAMP Total maximum clamp current | ICLAMP | “L” level max output current IOL “L” level avg. output current IOLAV “L” level max overall output current IOL “L” level avg. overall output current IOLAV “H” level max output current IOH “H” level avg. output current IOHAV “H” level max overall output current IOH “H” level avg. overall output current IOHAV Power consumption PD Operating temperature TA Storage temperature TSTG VSS  0.3  2.0            40 55 VSS  6.0 Units VSS  6.0 V VCC  AVCC *1  2.0 V *2 mA *6 20 mA *6 15 mA *3 4 mA *4 100 mA 50 15 4 100 50 mA *5 mA *3 mA *4 mA mA *5 500 mW Flash device 400 mW MASK ROM 105 150 C C *1 : AVCC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not exceed AVRH. *2 : VI and VO should not exceed VCC  0.3 V. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *6 : ❐ Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 Use within recommended operating conditions. Use at DC voltage (current) . ❐ The  B signal should always be applied with a limiting resistance placed between the  B signal and the microcontroller. ❐ The value of the limiting resistance should be set so that when the  B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ❐ Note that when the microcontroller drive current is low, such as in the power saving modes, the  B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. ❐ Note that if a  B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. ❐ Note that if the  B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. ❐ Care must be taken not to leave the  B input pin open. ❐ ❐ Document Number: 002- 07696 Rev. *B Page 37 of 70 MB90540G/545G Series ❐ Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept  B signal input. ❐ Sample recommended circuits :  Input/Output Equivalent circuits Protective diode VCC  B input (0 V to 16 V) Limiting resistance P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002- 07696 Rev. *B Page 38 of 70 MB90540G/545G Series 11.2 Recommended Conditions Parameter (VSS  AVSS  0.0 V) Value Symbol Min Typ Max Units Remarks Under normal operation : Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S) Power supply voltage 4.5 5.0 5.5 V 3.5 5.0 5.5 V Under normal operation when A/D conveter is not used : MB90F548GL(S)/543G(S)/547G(S)/548G(S) VCC, AVCC Smooth capacitor CS Operating temperature TA Under normal operation when A/D conveter is used : MB90F548GL(S)/543G(S)/547G(S)/548G(S) 3.0  5.5 V Maintain RAM data in stop mode 0.022 0.1 1.0 F * 40  105 C *: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The bypass capacitor should be greater than this capacitor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.  C Pin Connection Diagram C CS Document Number: 002- 07696 Rev. *B Page 39 of 70 MB90540G/545G Series 11.3 DC Characteristics (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA  40 C to 105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10%, VSS  AVSS  0.0 V, TA  40 C to 105 C) Parameter Symbol Pin name Condition Value Typ Min Max Units VIL VILM CMOS hysteresis input pin TTL input pin MD input pin CMOS hysteresis input pin TTL input pin MD input pin Output H voltage VOH All output pins Output L voltage VOL All output pins Input leak current IIL  Pull-up resistance RUP P00 to P07, P10 to P17, P20 to P27, P30 to P37, RST  25 50 100 k Pull-down resistance RDOWN MD2  25 50 100 k Input H voltage Input L voltage VIHS VIH VIHM VILS  0.8 VCC  VCC  0.3   2.0 VCC  0.3   VCC  0.3 V V  VCC  0.3  0.2 VCC V   VSS  0.3  0.8 VSS  0.3 V V VCC  0.5     V   0.4 V 5  5 A VCC  4.5 V, IOH  4.0 mA VCC  4.5 V, IOL  4.0 mA VCC  5.5 V, VSS  VI  VCC  Remarks V Except Flash devices (Continued) Document Number: 002- 07696 Rev. *B Page 40 of 70 MB90540G/545G Series (Continued) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA  40 C to 105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA  40 C to 105 C) Parameter Symbol Pin name Condition Internal frequency : 16 MHz, At normal operating Internal frequency : 16 MHz, At Flash programming/erasing Internal frequency : 16 MHz, At sleep mode ICC ICCS VCC  5.0 V  10, ICTS Power supply current* Internal frequency : 2 MHz, At pseudo timer mode VCC ICCL At sub operation, TA  25 C Internal frequency : 8 kHz, ICCLS At sub sleep, TA  25 C Internal frequency : 8 kHz, ICCT At timer mode, TA  25 C At stop, TA  25 C At hardware standby mode, TA  25 C ICCH1 ICCH2 Input capacity CIN Internal frequency : 8 kHz, Other than AVCC, AVSS, AVRH, AVRL, C, VCC, VSS  Value Typ Min Max Units  40 55 mA  50 70 mA 12 20 mA 300 600 600 1100 A A 200 400 A 400 50 150 750 100 300 A A A 15 40 A 7 25 A 5 20 A 50 100 A 5 15 pF             Remarks Flash device MB90F548GL (S) only MB90543G(S)/547G(S)/ 548(S) only MB90F548GL only MASK ROM Flash device * : The power supply current testing conditions are when using the external clock. Document Number: 002- 07696 Rev. *B Page 41 of 70 MB90540G/545G Series 11.4 AC Characteristics 11.4.1 Clock Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA  40 C to 105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA  40 C to 105 C) Parameter Oscillation frequency Symbol fC fCL Value Pin name Min Max Units Remarks 3  16 MHz No multiplier When using an oscillator circuit VCC  5.0 V  10% 8  16 MHz PLL multiplied by 1 When using an oscillator circuit VCC  5.0 V  10% 4  8 MHz PLL multiplied by 2 When using an oscillator circuit VCC  5.0 V  10% 3  5.33 MHz PLL multiplied by 3 When using an oscillator circuit VCC  5.0 V  10% 3  4 MHz PLL multiplied by 4 When using an oscillator circuit VCC  5.0 V  10% 3  5 MHz When using an oscillator circuit VCC < 4.5 V(MB90F548GL(S)/543G(S)/ 547G(S)/548G(S)) 3  16 MHz No multiplier When using an external clock 8  16 MHz PLL multiplied by 1 When using an external clock 4  8 MHz PLL multiplied by 2 When using an external clock 3  5.33 MHz PLL multiplied by 3 When using an external clock 3  4 MHz PLL multiplied by 4 When using an external clock  32.768  kHz X0, X1 X0A, X1A Typ (Continued) Document Number: 002- 07696 Rev. *B Page 42 of 70 MB90540G/545G Series (Continued) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA  40 C to 105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA  40 C to 105 C) Parameter Clock cycle time Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time Symbol tCYL Value Pin name Min Typ Max Units Remarks 62.5  333 ns No multiplier When using an oscillator circuit VCC  5.0 V  10% 62.5  125 ns PLL multiplied by 1 When using an oscillator circuit VCC  5.0 V  10% 125  250 ns PLL multiplied by 2 When using an oscillator circuit VCC  5.0 V  10% 187.5  333 ns PLL multiplied by 3 When using an oscillator circuit VCC  5.0 V  10% 250  333 ns PLL multiplied by 4 When using an oscillator circuit VCC  5.0 V  10% 200  333 ns When using an oscillator circuit VCC < 4.5 V(MB90F548GL(S)/543G(S)/ 547G(S)/548G(S)) 62.5  333 ns No multiplier When using an external clock 62.5  125 ns PLL multiplied by 1 When using an external clock 125  250 ns PLL multiplied by 2 When using an external clock 187.5  333 ns PLL multiplied by 3 When using an external clock 250  333 ns PLL multiplied by 4 When using an external clock 30.5 s 15.2    X0, X1 tLCYL X0A, X1A  PWH, PWL X0 10 PWLH, PWLL X0A  tCR, tCF X0   5 ns When using an external clock 1.5  16 MHz When using main clock  kHz When using sub-clock 666 ns When using main clock  s When using sub-clock fCP fLCP tCP tLCP     Document Number: 002- 07696 Rev. *B  62.5   8.192  122.1 ns s Duty ratio is about 30 to 70. Page 43 of 70 MB90540G/545G Series  Clock Timing tCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF tCR tLCYL 0.8 VCC X0A 0.2 VCC PWLH PWLL tCF tCR  Guaranteed PLL operation range Guaranteed operation range (Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S)) Guaranteed operation range (MB90F548GL(S)/543G(S)/547G(S)/548G(S)) 5.5 Guaranteed A/D Converter operation range Power supply voltage 4.5 VCC (V) 3.5 Guaranteed PLL operation range (MB90F548GL(S)/543G(S)/547G(S)/548G(S)) Guaranteed PLL operation range ( Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S)) 1.5 8 16 Machine clock fCP (MHz) Document Number: 002- 07696 Rev. *B Page 44 of 70 MB90540G/545G Series  External clock frequency and Machine clock frequency ×4 16 Machine clock fCP (MHz) ×3 ×2 ×1 12 9 8 ×1/2 (PLL off) 4 3 4 8 16 External clock fC (MHz) AC characteristics are set to the measured reference voltage values below.  Input signal waveform Hysteresis Input Pin  Output signal waveform Output Pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V TTL Input Pin 2.0 V 0.8 V Document Number: 002- 07696 Rev. *B Page 45 of 70 MB90540G/545G Series 11.4.2 Clock Output Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA  40 C to 105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA  40 C to 105 C) Parameter Symbol Cycle time tCYC CLK  CLK tCHCL Pin name Value Condition Min 62.5 VCC  5 V  10 CLK 20 Max   Units Remarks ns ns tCYC tCHCL 2.4 V CLK 2.4 V 0.8 V 11.4.3 Reset and Hardware Standby Input Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA  40 C to 105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA  40 C to 105 C) Parameter Symbol Value Pin name Min Under normal operation  ms In stop mode 100  s In pseudo timer mode (MB90543G (S) /547G (S) /548G (S) ) 4 tCP  ns In pseudo timer mode (Other than MB90543G (S) /547G (S) /548G (S) ) 2 tLCP  s In sub-clock mode, sub-sleep mode, timer mode 4 tCP  ns Under normal operation oscillator  4 tCP Hardware standby input time tHSTL RST HST Remarks ns Oscillation time of tRSTL Units  4 tCP Reset input time Max Note : “tcp” represents one cycle time of the machine clock. Oscillation time of oscillator is time that amplitude reached the 90. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between handreds of s to several ms. In the external clock, the oscillation time is 0 ns. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm. Document Number: 002- 07696 Rev. *B Page 46 of 70 MB90540G/545G Series  In under normal operation, pseudo timer mode, sub-clock mode, sub-sleep mode, timer mode tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC  In stop mode tRSTL RST 0.2 VCC X0 0.2 VCC 90% of amplitude Internal operation clock 4 tCP Oscillation time of oscillator Internal reset Document Number: 002- 07696 Rev. *B Oscillation setting time Instruction execution Page 47 of 70 MB90540G/545G Series 11.4.4 Power On Reset (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Symbol Pin name Power on rise time tR VCC Power off time tOFF VCC Value Condition  Min Max Units Remarks 0.05 30 ms * 50  ms Waiting time until power-on * : VCC must be kept lower than 0.2 V before power-on. Notes :  The above values are used for creating a power-on reset.  Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power supply using the above values. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC 3.0 V VSS Document Number: 002- 07696 Rev. *B RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. Page 48 of 70 MB90540G/545G Series 11.4.5 Bus Timing (Read) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Symbol Pin name Value Condition Min Max Units ALE pulse width tLHLL ALE tCP/2  20  ns Valid address  ALE time tAVLL ALE, A16 to A23, AD00 to AD15 tCP/2  20  ns ALE  Address valid time tLLAX ALE, AD00 to AD15 tCP/2  15  ns Valid address  RD time tAVRL A16 toA23, AD00 to AD15, RD tCP  15  ns Valid address  Valid data input tAVDV A16 to A23, AD00 to AD15  5 tCP/2  60 ns RD pulse width tRLRH RD 3 tCP/2  20  ns RD  Valid data input tRLDV RD, AD00 to AD15  3 tCP/2  60 ns RD  Data hold time tRHDX RD, AD00 to AD15 0  ns RD  ALE time tRHLH RD, ALE tCP/2  15 RD  Address valid time tRHAX RD, A16 to A23 tCP/2  10   tAVCH A16 to A23, AD00 to AD15, CLK tCP/2  20  RD  CLK time tRLCH RD, CLK tCP/2  20 ALE  RD time tLLRL ALE, RD   Valid address  CLK time Document Number: 002- 07696 Rev. *B  tCP/2  15 Remarks ns ns ns ns ns Page 49 of 70 MB90540G/545G Series  Bus Timing (Read) tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH 2.4 V 2.4 V 2.4 V ALE tLHLL 0.8 V tRLRH 2.4 V RD tAVLL tLLAX 0.8 V tLLRL tAVRL tRLDV tRHAX 2.4 V 2.4 V 0.8 V 0.8 V A16 to A23 tAVDV 2.4 V AD00 to AD15 0.8 V Document Number: 002- 07696 Rev. *B 2.4 V Address 0.8 V tRHDX 0.8 VCC 0.2 VCC 0.8 VCC Read data 0.2 VCC Page 50 of 70 MB90540G/545G Series 11.4.6 Bus Timing (Write) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Symbol Pin name Value Condition Min Max Units Valid address  WR time tAVWL A16 to A23 AD00 to AD15, WR tCP  15  ns WR pulse width tWLWH WR 3 tCP/2  20  ns Valid data output  WR time tDVWH AD00 to AD15, WR 3 tCP/2  20  ns WR  Data hold time tWHDX AD00 to AD15, WR 20  ns WR  Address valid time tWHAX A16 to A23, WR WR  ALE time tWHLH WR, ALE WR  CLK time tWLCH WR, CLK  tCP/2  10 tCP/2  15 tCP/2  20    Remarks ns ns ns  Bus Timing (Write) tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL tWLWH 2.4 V WR (WRL, WRH) 0.8 V tWHAX 2.4 V 2.4 V 0.8 V 0.8 V A16 to A23 tDVWH AD00 to AD15 2.4 V 2.4 V Address 0.8 V Document Number: 002- 07696 Rev. *B tWHDX 2.4 V Write data 0.8 V 0.8 V Page 51 of 70 MB90540G/545G Series 11.4.7 Ready Input Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Symbol Pin name RDY setup time tRYHS RDY RDY hold time tRYHH RDY Value Condition Min 45  0 Max   Units Remarks ns ns Note : If the RDY setup time is insufficient, use the auto-ready function.  Ready Input Timing 2.4 V CLK ALE RD/WR tRYHS RDY no WAIT is used. RDY When WAIT is used (1 cycle). Document Number: 002- 07696 Rev. *B 0.8 VCC tRYHH 0.8 VCC 0.2 VCC Page 52 of 70 MB90540G/545G Series 11.4.8 Hold Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Symbol Pin name Pin floating  HAK time tXHAL HAK HAK time  Pin valid time tHAHV HAK Value Condition  Min Units Max 30 tCP ns tCP 2 tCP ns Remarks Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.  Hold Timing HAK 2.4 V 0.8 V tXHAL 2.4 V Each pin tHAHV High impedance 2.4 V 0.8 V 0.8 V 11.4.9 UART0/1, Serial I/O Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Symbol Pin name Condition Value Min Max Units 8 tCP  ns  80 80 ns 100  ns SCK0 to SCK2, SIN0 to SIN2 60  ns tSHSL SCK0 to SCK2 4 tCP tSLSH SCK0 to SCK2 4 tCP   SCK  SOT delay time tSLOV SCK0 to SCK2, SOT0 to SOT2  150 ns Valid SIN  SCK tIVSH SCK0 to SCK2, SIN0 to SIN2 60  ns SCK  Valid SIN hold time tSHIX SCK0 to SCK2, SIN0 to SIN2 60  ns tSCYC SCK0 to SCK2 SCK  SOT delay time tSLOV SCK0 to SCK2, SOT0 to SOT2 Valid SIN  SCK tIVSH SCK0 to SCK2, SIN0 to SIN2 SCK Valid SIN hold time tSHIX Serial clock “H” pulse width Serial clock “L” pulse width Serial clock cycle time Internal clock operation output pins are CL  80 pF  1 TTL. External clock operation output pins are CL  80 pF  1 TTL. Remarks ns ns Notes : ■ ■ ■ AC characteristic in CLK synchronized mode. CL is load capacity value of pins when testing. For tCP (Machine clock cycle time) , refer to “ (1) Clock Timing”. Document Number: 002- 07696 Rev. *B Page 53 of 70 MB90540G/545G Series  Internal Shift Clock Mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC  External Shift Clock Mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN Document Number: 002- 07696 Rev. *B tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Page 54 of 70 MB90540G/545G Series 11.4.10 Timer Input Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Input pulse width Symbol Pin name tTIWH TIN0, TIN1 tTIWL IN0 to IN7 Value Condition  Min Units Max  4 tCP Remarks ns  Timer Input Timing 0.8 VCC 0.8 VCC 0.2 VCC tTIWH 0.2 VCC tTIWL 11.4.11 Timer Output Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter CLK  TOUT change time Symbol Pin name TOT0 , TOT1, PPG0 to PPG3 tTO Value Condition  Min 30 Max  Units Remarks ns  Timer Output Timing 2.4 V CLK 2.4 V 0.8 V TOUT tTO Document Number: 002- 07696 Rev. *B Page 55 of 70 MB90540G/545G Series 11.4.12 Trigger Input Timing (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  3.5 V to 5.5 V, VSS  AVSS  0.0 V, TA   40 C to  105 C) (Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC  5.0 V  10, VSS  AVSS  0.0 V, TA   40 C to  105 C) Parameter Input pulse width Symbol tTRGH tTRGL Pin name INT0 to INT7, ADTG Value Condition Min 5 tCP  1 Max   Units Remarks ns Under nomal operation s In stop mode  Trigger Input Timing 0.8 VCC 0.8 VCC 0.2 VCC tTRGH Document Number: 002- 07696 Rev. *B 0.2 VCC tTRGL Page 56 of 70 MB90540G/545G Series 11.5 A/D Converter 11.5.1 Electrical Characteristics (VCC  AVCC  5.0 V10, VSS  AVSS  0.0 V, 3.0 V  AVRH  AVRL, TA   40 C to  105 C) Parameter Symbol Value Pin name Min Typ Max Units Remarks             Differential nonlinearity error      1.9 LSB Zero transition voltage VOT AN0 to AN7 AVRL  3.5 LSB AVRL  0.5 LSB AVRL  4.5 LSB V Full scale transition voltage VFST AN0 to AN7 AVRH  6.5 LSB AVRH  1.5 LSB AVRH  1.5 LSB V Compare time   352 tCP   ns Internal frequency : 16 MHz Sampling time   64 tCP   ns Internal frequency : 16 MHz Analog port input current IAIN AN0 to AN7 1  1 A VCC  AVCC  5.0 V  1 Analog input voltage range VAIN AN0 to AN7 AVRL AVRH V Reference voltage range   AVRH AVRL  2.7 AVCC V AVRL 0 Resolution Conversion error Nonlinearity error Power supply current Reference voltage supply current Offset between input channels IR AVRH IRH AVRH       AN0 to AN7  IA AVCC IAH AVCC    5  10  5.0  2.5 AVRH  2.7 bit LSB LSB V  mA 5 A * 400 600 A Flash device 140 260 A MASK ROM  5 A *  4 LSB * : When not using an A/D converter, this is the current (VCC  AVCC  AVRH  5.0 V) when the CPU is stopped. Note: The functionality of the A/D converter is only guaranteed for VCC  5.0 V  10  (also for MB90543G(S)/547G(S)/548G(S)/ F548G(S)/F548GL(S)). Document Number: 002- 07696 Rev. *B Page 57 of 70 MB90540G/545G Series 11.5.2 A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000”  “00 0000 0001”) with the full-scale transition point (“11 1111 1110”  “11 1111 1111”) from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 0.5 LSB Actual conversion Value 3FE Digital output 3FD {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (measured value) 003 Actual conversion characteristics Theoretical characteristics 002 001 0.5 LSB AVRL AVRH Analog input 1 LSB  (Theoretical value) AVRH  AVRL [V] 1024 VOT (Theoretical value)  AVRL  0.5 LSB [V] VFST (Theoretical value)  AVRH  1.5 LSB [V] Total error for digital output N  VNT  {1 LSB  (N  1) 1 LSB  0.5 LSB} [LSB] VNT : Voltage at a transition of digital output from (N  1) to N (Continued) Document Number: 002- 07696 Rev. *B Page 58 of 70 MB90540G/545G Series (Continued) Linearity error 3FE 3FD Digital output Theorential characteristics Actual conversion value {1 LSB × (N − 1) + VOT } N+1 Actual conversion value VFST (measured value) VNT 004 Actual conversion characteristics 003 Digital output 3FF Differential linearity error N V (N + 1) T (measured value) N−1 VNT (measured value) 002 Theoretical characteristics 001 N−2 Acturel conversion value VOT (measured value) AVRL AVRH AVRL Analog input Linearity error of digital output N AVRH Analog input  VNT  {1 LSB  (N  1)  VOT} [LSB] 1 LSB Differential linearity error V (N  1) T  VNT  of digital N 1 LSB 1 LSB  VFST  VOT [V] 1022  1 LSB [LSB] VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH” 11.5.3 Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions, :  Output impedance values of the external circuit of 15 k or lower are recommended.  When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. Note : When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period  4.00 s @machine clock of 16 MHz) .  Equipment of analog input circuit model Comparator Analog input 3.2 kΩ Max 30 pF Max 11.5.4 Error The smaller the | AVRH  AVRL |, the greater the error would become relatively. Document Number: 002- 07696 Rev. *B Page 59 of 70 MB90540G/545G Series 11.6 Flash Memory Program/Erase Characteristics Parameter TA   25 C VCC  5.0 V Word (16 bit width) programming time Erase/Program cycle Min  Sector erase time Chip erase time Value Condition  Document Number: 002- 07696 Rev. *B Typ Max Units Remarks 1 15 s Excludes 00H programming prior erasure 5  s MB90F543G (S) /F548G (S) /F548GL (S) 7  s MB90F549G (S) /F546G (S)  16 3,600 s Excludes system-level overhead 10,000   cycle  Excludes 00H programming prior erasure Page 60 of 70 MB90540G/545G Series 12. Example Characteristics  “H” level output voltage “L” level output voltage  VOL – IOL VOH – IOH (VCC = 4.5 V,Ta = +25˚C) (VCC = 4.5 V, Ta = +25˚C) 5 0.9 4.5 0.8 4 0.7 3.5 VOL [V] VOH [V] 0.6 3 2.5 0.5 0.4 2 0.3 1.5 1 0.2 0.5 0.1 0 0 0 -2 -4 -6 -8 -10 0 2 4 6 8 10 IOL [mA] IOH [mA]  “H” level input voltage/ “L” level input voltage (Hysterisis inpiut) Vin – Vcc (Ta = +25˚C) 5 4 Vin [V] VIH 3 VIL 2 1 0 3 3.5 4 4.5 Document Number: 002- 07696 Rev. *B 5 5.5 6 6.5 Page 61 of 70 MB90540G/545G Series  Power supply current (MB90549G) Icc – Vcc Iccs – Vcc (Ta = +25˚C) (Ta = +25˚C) 12 40 fcp = 16 MHz fcp = 16 MHz 35 10 fcp = 12 MHz 30 fcp = 12 MHz 8 fcp = 8 MHz 20 Icc [mA] Icc [mA] fcp = 10 MHz fcp = 10 MHz 25 15 fcp = 8 MHz 6 4 fcp = 4 MHz fcp = 4 MHz 10 fcp = 2 MHz fcp = 2 MHz 2 5 0 0 2 3 4 5 6 7 2 3 4 5 6 7 Vcc [V] Vcc [V] ICTS – VCC ICCL – VCC (Ta = +25˚C) 600 (Ta = +25˚C) 100 90 500 80 fcp = 2 MHz 70 ICCL [μA] ICTS [μA] 400 300 60 50 40 200 30 fcp = 8 kHz 20 100 10 0 0 2 3 4 5 Vcc [V] Document Number: 002- 07696 Rev. *B 6 7 2 3 4 5 6 7 Vcc [V] Page 62 of 70 MB90540G/545G Series ICCLS – VCC ICCT – VCC (Ta = +25˚C) (Ta = +25˚C) 40 25 35 20 30 ICCT [μA] ICCLS [μA] 25 20 15 10 15 fcp = 8 kHz 10 fcp = 8 kHz 5 5 0 0 2 3 4 5 2 7 6 3 4 Vcc [V] 6 7 Vcc [V] ICCH2 – VCC ICCH1 – VCC (hardware standby, Ta = +25 ˚C) (STOP, Ta = +25 ˚C) 20 90 18 85 16 70 14 ICCH1 [μA] 100 ICCH2 [μA] 5 60 50 12 10 40 8 30 6 20 4 10 2 0 0 2 3 4 5 VCC [V] Document Number: 002- 07696 Rev. *B 6 7 2 3 4 5 6 7 VCC [V] Page 63 of 70 MB90540G/545G Series  Power supply current (MB90F549G) Iccs – Vcc Icc – Vcc (Ta = +25 ˚C) (Ta = +25 ˚C) 14 45 fcp = 16 MHz fcp = 16 MHz 40 12 35 fcp = 12 MHz fcp = 12 MHz 10 30 fcp = 10 MHz ICC [mA] ICC [mA] fcp = 10 MHz 25 fcp = 8 MHz 20 15 fcp = 4 MHz 8 fcp = 8 MHz 6 fcp = 4 MHz 4 10 fcp = 2 MHz fcp = 2 MHz 2 5 0 0 2 3 4 5 6 2 7 3 4 5 VCC [V] 6 7 VCC [V] ICTS – VCC ICCL – VCC (Ta = +25 ˚C) (Ta = +25 ˚C) 600 300 250 500 fcp = 2 MHz 200 400 ICCL [μA] ICTS [μA] fcp = 8 kHz 300 150 200 100 100 50 0 0 2 3 4 5 VCC [V] Document Number: 002- 07696 Rev. *B 6 7 2 3 4 5 6 7 VCC [V] Page 64 of 70 MB90540G/545G Series ICCLS – VCC ICCT – VCC (Ta = +25 ˚C) (Ta = +25 ˚C) 25 45 40 20 35 30 ICCT [μA] ICCLS [μA] 15 25 20 10 15 fcp = 8 MHz fcp = 8 MHz 10 5 5 0 0 2 3 4 5 6 2 7 3 4 90 18 85 16 70 14 ICCH1 [μA] 20 ICCH2 [μA] 100 60 50 12 10 40 8 30 6 20 4 10 2 0 0 4 5 VCC [V] Document Number: 002- 07696 Rev. *B 7 (STOP, Ta = +25 ˚C) (hardware standby, Ta = +25 ˚C) 3 6 ICCH1 – VCC ICCH2 – VCC 2 5 VCC [V] VCC [V] 6 7 2 3 4 5 6 7 VCC [V] Page 65 of 70 MB90540G/545G Series 13. Ordering Information Part number Package Remarks MB90F543GPF MB90F543GSPF MB90F546GPF MB90F546GSPF MB90F548GPF MB90F548GSPF MB90F548GLPF MB90F548GLSPF MB90F549GPF MB90F549GSPF  100-pin Plastic QFP (PQH100) MB90543GPF MB90543GSPF MB90547GPF MB90547GSPF MB90548GPF MB90548GSPF MB90549GPF MB90549GSPF MB90F543GPMC MB90F543GSPMC MB90F546GPMC MB90F546GSPMC MB90F548GPMC MB90F548GSPMC MB90F548GLPMC MB90F548GLSPMC MB90F549GPMC MB90F549GSPMC  100-pin Plastic LQFP (LQI100) MB90543GPMC MB90543GSPMC MB90547GPMC MB90547GSPMC MB90548GPMC MB90548GSPMC MB90549GPMC MB90549GSPMC Document Number: 002- 07696 Rev. *B Page 66 of 70 MB90540G/545G Series 14. Package Dimensions Package Type Package Code QFP 100 PQH100 D D1 4 5 7 80 51 51 81 50 80 50 81 31 100 E1 E 5 7 6 3 4 31 100 1 30 e 3 0.40 C A-B D 30 2 5 7 1 0.20 C A-B D b 0.13 C A-B D BOTTOM VIEW 8 TOP VIEW 2 θ 9 A A' SEATING PLANE L2 c 10 b 0.10 C SECTION A-A' DETAIL A SIDE VIEW SYMBOL DIMENSIONS MIN. NOM. MAX. A1 0.05 0.45 b 0.27 c 0.11 A 3.35 0.32 0.23 D 23.90 BSC D1 20.00 BSC e 0.65 BSC E 17.90 BSC E1 θ L 0.37 14.00 BSC 0° 0.73 8° 0.88 L1 1.95 REF L2 0.25 BSC 1.03 002-15156 ** PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3.35 MM PQH100 REV** Document Number: 002- 07696 Rev. *B Page 67 of 70 MB90540G/545G Series (Continued) Package Type Package Code LQFP 100 LQI100 D D1 75 4 D 5 7 D1 51 51 5 7 75 50 50 76 4 76 E1 E 5 4 7 E1 E 5 4 7 3 6 26 26 100 1 25 1 25 2 5 7 e 100 BOTTOM VIEW 0.1 0 C A-B D 3 0.2 0 C A-B D b TOP VIEW 8 0.0 8 C A-B D 2 A 9 A SEATING PLANE A' 0.25 L1 0.0 8 C c A1 b 10 SECTION A-A' L SIDE VIEW SYMBOL DETAIL A DIMENSIONS MIN. NOM. MAX. 1.70 A A1 0.05 b 0.15 0.15 0.27 c 0.09 0.20 D 16.00 BSC D1 14.00 BSC e 0.50 BSC E 16.00 BSC E1 14.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 NOTES : 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY. 3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H. 4. TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PRE SIDE. DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. 7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS. BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER SECTIONS OF THE MOLDER BODY. 8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT. 9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. 10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY. PACKAGE OUTLINE, 100 LEAD LQFP 14.0X14.0X1.7 MM LQI100 REV*A Document Number: 002- 07696 Rev. *B 002-11500 *A Page 68 of 70 MB90540G/545G Series 15. Major Changes Spansion Publication Number: DS07-13703-7E Section Change Results ■ PRODUCT LINEUP Changed the name in peripheral resource. 16-bit I/O Timer  16-bit Free-run Timer ■ I/O CIRCUIT TYPE Changed the name of input typ. Hysteresis  CMOS Hysteresis HYS  CMOS Hysteresis ■ BLOCK DIAGRAM Changed the arrow direction of SOT1 signal at UART1(SCI). “ ” (input/output)  “” (output) ■ I/O MAP Changed the text of “Note”. ■ INTERRUPT MAP Changed the name of peripheral resource of the pin number: #19. I/O Timer  16-bit Free-run Timer ■ ELECTRICAL CHARACTERISTICS 2. Recommended Conditions Changed the remarks of “parameter: Power supply voltage”. 3. DC Characteristics Changed the maximum value of symbol : VILM of parameter: Input voltage. VCC + 0.3  VSS + 0.3 Added the following remarks for parameter : Pull-down resistance. Except Flash device 4. AC Characteristics Added the value when using an external clock in Oscillation frequency and Clock cycle time on (1) Clock Timing for parameter. (1) Clock Timing Added the item of A/D converter operation range in figure of “ Guaranteed PLL operation range” (3) Reset and Hardware Standby Input Timing (4) Power On Reset Changed the following item. (3) Reset and Hardware Standby Input Timing Remarks: In sub-clock mode, sub-sleep mode, timer mode 2tCP  2tLCP Changed as follows; Due to repetitive operation  Waiting time until power-on 5. A/D Converter Changed the unit of Zero transition voltage and Full scale transition voltage. mV  V ■ ORDERING INFORMATION Added the MB90F548GLPMC in Part Numbers. NOTE: Please see “Document History” about later revised information. Document History Document Title: MB90F543G(S)/546G(S)/548G(S)/549G(S)/549G(S)/V540G/MB90543G(S)/547G(S)/548G(S)/F548GL(S) CMOS F2MC-16LX MB90540G/545G Series 16-bit Proprietary Microcontroller Document Number: 002-07696 Revision ECN Orig. of Change Submission Date **  AKIH 11/13/2008 Description of Change Migrated to Cypress and assigned document number 002-07696. No change to document contents or format. *A 5537115 AKIH 11/30/2016 Updated to Cypress template *B 6040590 YSAT 02/05/2018 Adapted new Cypress logo Updated following package code FPT-100P-M06 → PQH100 FPT-100P-M20 → LQI100 Document Number: 002- 07696 Rev. *B Page 69 of 70 MB90540G/545G Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Lighting & Power Control Memory cypress.com/iot cypress.com/powerpsoc Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/memory PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2002-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-07696 Rev. *B Revised February 5, 2018 Page 70 of 70