MB91F467SAPMC-GSK5E2

CY91460S Series FR60 32-bit Microcontroller CY91460S series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family of CPUs. This series contains the LIN-USART, CAN and APIX® controllers. Features ■ FR60 CPU core ■ 32-bit RISC, load/store architecture, five-stage pipeline ■ 16-bit fixed-length instructions (basic instructions) ■ Instruction execution speed: 1 instruction per cycle ■ ■ Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for embedded applications ■ ■ Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language ■ Register interlock function: Facilitating assembly-language coding ■ Built-in multiplier with instruction-level support ❐ Signed 32-bit multiplication: 5 cycles ❐ Signed 16-bit multiplication: 3 cycles ■ Interrupts (save PC/PS) : 6 cycles (16 priority levels) ■ Harvard architecture enabling program access and data access to be performed simultaneously ■ Instructions compatible with the FR family Internal peripheral resources ■ General-purpose ports : Maximum 133 ports ■ DMAC (DMA Controller) ❐ Maximum of 5 channels able to operate simultaneously. ❐ 2 transfer sources (internal peripheral/software) ❐ Activation source can be selected using software. ❐ Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) ❐ Transfer mode (demand transfer/burst transfer/step transfer/block transfer) ❐ Transfer data size selectable from 8/16/32-bit ❐ Multi-byte transfer enabled (by software) ❐ DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) ■ A/D converter (successive approximation type) ❐ 10-bit resolution: 16 channels ❐ Conversion time: minimum 1 μs ■ External interrupt inputs : 16 channels 2 ❐ Shares the CAN RX pin and I C SDA pin ■ Bit search module (for REALOS) ❐ Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word Cypress Semiconductor Corporation Document Number: 002-04623 Rev. *B • ■ LIN-USART (full duplex double buffer): 6 channels ❐ Clock synchronous/asynchronous selectable ❐ Sync-break detection ❐ Internal dedicated baud rate generator I2C bus interface (supports 400 kbps): 3 channels ❐ Master/slave transmission and reception ❐ Arbitration function, clock synchronization function CAN controller (C-CAN): 2 channels ❐ Maximum transfer speed: 1 Mbps ❐ 32 transmission/reception message buffers APIX® controller ® ❐ APIX link (105Mbit / 6Mbit): 1 channel ❐ Automotive Interconnect links (5Mbit / 6Mbit): 2 links ■ Sound generator : 1 channel ❐ Tone frequency : PWM frequency divide-by-two (reload value + 1) ■ Alarm comparator : 1 channel ❐ Monitor external voltage ❐ Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) ■ 16-bit PPG timer : 16 channels ■ 16-bit PFM timer : 1 channel ■ 16-bit reload timer: 8 channels ■ 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) ■ Input capture: 8 channels (operates in conjunction with the free-run timer) ■ Output compare: 4 channels (operates in conjunction with the free-run timer) ■ Up/Down counter: 4 channels (4×8-bit or 2×16 bit) ■ Watchdog timer ■ Real-time clock ■ Low-power consumption modes : Sleep/stop mode function ■ Low voltage detection circuit ■ Clock monitor ■ Clock supervisor ❐ Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 19, 2018 CY91460S Series ■ ■ ■ ■ Clock modulator * Package and technology Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator ■ Package : LQFP-176 ■ CMOS 0.18 μm technology Main oscillator stabilization timer ❐ Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter ■ Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) ■ Operating temperature range: between - 40°C and + 105°C Sub-oscillator stabilization timer ❐ Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter *: The clock modulator is currently being evaluated and should not be used for other purpose than testing. Note: APIX® is a registered mark of INOVA Semiconductors GmbH Document Number: 002-04623 Rev. *B Page 2 of 144 CY91460S Series Contents Product Lineup ................................................................. 4 Pin Assignment ................................................................ 6 CY91F467SA .............................................................. 6 Pin Description ................................................................. 7 CY91F467SA .............................................................. 7 I/O Circuit Types ............................................................. 15 Handling Devices ............................................................ 21 Preventing Latch-up .................................................. 21 Handling of unused input pins ................................... 21 Power supply pins ..................................................... 21 Crystal oscillator circuit .............................................. 21 Notes on using external clock ................................... 21 Mode pins (MD_x) ..................................................... 22 Notes on operating in PLL clock mode ...................... 22 Pull-up control ........................................................... 22 Notes on PS register ................................................. 22 Notes on Debugger ........................................................ 23 Execution of the RETI Command .............................. 23 Break function ........................................................... 23 Operand break .......................................................... 23 Block Diagram ................................................................ 24 CY91F467SA ............................................................ 24 CPU and Control Unit ..................................................... 25 Features .................................................................... 25 Internal architecture ................................................... 25 Programming model .................................................. 26 Registers ................................................................... 27 Document Number: 002-04623 Rev. *B Embedded Program/Data Memory (Flash) ................... 30 Flash features ............................................................ 30 Operation modes ....................................................... 30 Flash access in CPU mode ....................................... 31 Parallel Flash programming mode ............................ 33 Flash Security ............................................................ 35 APIX® Controller ............................................................ 38 Overview ................................................................... 38 Automotive Remote Handler ..................................... 39 APIX® PHY Configuration ......................................... 51 DMA transfer request ................................................ 53 Automotive Interconnect Pins .................................... 54 USECASES ............................................................... 55 Memory Space ................................................................ 58 Memory Maps .................................................................. 59 CY91F467SA ............................................................ 59 I/O Map ............................................................................. 60 CY91F467SA ............................................................ 60 Flash memory and external bus area ....................... 88 Interrupt Vector Table .................................................... 90 Recommended Settings ................................................. 95 PLL and Clockgear settings ...................................... 95 Clock Modulator settings ........................................... 96 Electrical Characteristics ............................................. 102 Absolute maximum ratings ...................................... 102 Recommended operating conditions ....................... 104 DC characteristics ................................................... 106 A/D converter characteristics .................................. 110 Alarm comparator characteristics ............................ 114 FLASH memory program/erase characteristics ...... 115 AC characteristics ................................................... 116 Ordering Information .................................................... 138 Package Dimension ...................................................... 139 Revision History ........................................................... 140 Major Changes .............................................................. 141 Document History ......................................................... 143 Page 3 of 144 CY91460S Series 1. Product Lineup Feature CY91V460B CY91F467SA Max. core frequency (CLKB) 80MHz 100MHz Max. resource frequency (CLKP) 40MHz 50MHz Max. external bus freq. (CLKT) 40MHz 50MHz Max. CAN frequency (CLKCAN) 20MHz 40MHz Max. FlexRay frequency (SCLK) - - 0.35μm 0.18μm Technology Watchdog yes yes yes (disengageable) yes Bit Search yes yes Reset input (INITX) yes yes Hardware Standby input (HSTX) yes no Clock Modulator yes yes Clock Monitor yes yes Low Power Mode yes yes DMA 5 ch 5 ch Watchdog (RC osc. based) MAC (μDSP) MMU/MPU Flash no MPU (16 ch) no 1) MPU (8 ch) 1) Emulation SRAM 32bit read data 1088 KByte Satellite Flash - no Flash Protection - yes D-RAM 64 KByte 32 KByte ID-RAM 64 KByte 32 KByte Flash-Cache (Instruction cache) 16 KByte 8 KByte 4 KByte fixed 4 KByte RTC 1 ch 1 ch Free Running Timer 8 ch 8 ch ICU 8 ch 8 ch OCU 8 ch 4 ch Reload Timer 8 ch 8 ch PPG 16-bit 16 ch 16 ch PFM 16-bit 1 ch 1 ch Boot-ROM / BI-ROM Sound Generator Up/Down Counter (8/16-bit) 1 ch 1 ch 4 ch (8-bit) / 2 ch (16-bit) 4 ch (8-bit) / 2 ch (16-bit) (Continued) Document Number: 002-04623 Rev. *B Page 4 of 144 CY91460S Series (Continued) Feature CY91V460B CY91F467SA 6 ch (128msg) 2 ch (32msg) 4 ch + 4 ch FIFO + 8 ch 2 ch + 4 ch FIFO 4 ch 3 ch - 2ch (1ch physical) yes (32bit addr, 32bit data) yes (24bit addr, 16bit data) External Interrupts 16 ch 16 ch NMI Interrupts 1 ch 1 ch SMC 6 ch - LCD controller (40x4) 1 ch - ADC (10 bit) 32 ch 16 ch Alarm Comparator 2 ch 1 ch Supply Supervisor yes yes Clock Supervisor yes yes Main clock oscillator 4MHz 4MHz Sub clock oscillator 32kHz 32kHz RC Oscillator C_CAN LIN-USART I2C (400k) ® APIX FR external bus 100kHz 100kHz / 2MHz PLL x 20 x 25 DSU4 yes EDSU Supply Voltage Regulator Power Consumption yes (32 BP) *1 yes (16 BP) *1 3V / 5V 3V / 5V yes yes n.a. =LEVEL) LVIEN LVIRQ *Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored OFLIEN OFLIRQ 0(def) Event Buffer Overflow Interrupt disabled 1 Event Buffer Overflow Interrupt enabled 0(def) Event Buffer Overflow Interrupt not active 1 Event Buffer Overflow Interrupt active *Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored EVIEN EVIRQ 0(def) Event Buffer Interrupt disabled 1 Event Buffer Interrupt enabled 0(def) Event Buffer Interrupt not active 1 Event Buffer Interrupt active *Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored Set by hardware, reset by software STATUS[7:0] 0-128 Current FIFO filling status read only LEVEL[7:0] 0-128 FIFO interrupt level (128 default) Document Number: 002-04623 Rev. *B Page 48 of 144 CY91460S Series Eventbuffer • EVBUF0: Address 072F8h • EVBUF1: Address 072FCh 31 EVBUF0 30 - 29 - R0 R0 R/(W) R/(W) R/(W) 15 14 - 13 - R0 7 R/W 31 R/W 30 R/W 29 R/(W) R/(W) 23 R/(W) 22 R/(W) 15 R/(W) R/(W) R/(W) 19 R/(W) 20 EVDATA1[7:0] R/(W) 11 R/(W) 12 EVDATA2[7:0] R/(W) 6 3 R/(W) 4 EVDATA3[7:0] R/(W) R/(W) 5 R/(W) EVCH Holds channel number from Remote Handler RX event EVIDX[7:0] 0-255 Holds index number from Remote Handler RX event Bit8 - R/W 26 R/(W) R/W 25 R/(W) 18 R/(W) R/(W) R/(W) R/(W) 24 17 10 16 R/(W) 9 R/(W) 2 R/(W) 0 - R/W R/(W) 13 R/(W) R/W 8 reserved R/W0 1 - 27 21 14 7 R/(W) R/(W) 2 - 28 EVDATA0[7:0] R/(W) EVBUF1 9 R/W 3 - 16 R/(W) - R0 4 - R/(W) - R0 5 - 17 10 - R0 6 - R/(W) 11 - R0 18 24 EVCH R/(W) R0 19 12 - R0 R0 R/(W) - R0 20 EVIDX[7:0] R/(W) 25 - R0 21 26 - R0 22 27 - R0 23 28 - 8 R/(W) 1 R/(W) 0 R/(W) reserved Bit Always write 0 to this bit. The read value is the value written. EVDATA0-3 4 bytes of payload data *Remark: It is recommended to read first EVBUF0 and after that EVBUF1 A read access to EVBUF0 triggers a retrieve of the current event message from the event buffer fifo and returns the channel number and event index. A read access to EVBUF1 returns the data part of the a event message Document Number: 002-04623 Rev. *B Page 49 of 144 CY91460S Series Apix® configuration • APCFG0x (Link 0) • APCFG1x (Link 1) 31 30 29 28 config_byte_1 APCFG00/APCFG10 0 0 R/W 0 R/W R/W 23 R/W R/W R/W 15 0 0 R/W 7 5 0 R/W R/W 1 R/W 31 30 29 1 1 R/W 1 R/W R/W 23 0 R/W 0 R/W R/W 15 13 0 R/W R/W R/W 7 1 0 R/W 0 R/W 31 30 29 0 0 R/W 0 R/W R/W 23 21 0 R/W R/W 15 14 0 R/W R/W 7 6 5 - R/W R/W 30 29 APCFG03/APCFG13 0 R/W 1 R/W R/W 23 22 1 0 R/W 1 R/W R/W 15 14 1 13 0 R/W 0 R/W R/W 7 6 0 R/W 21 5 0 R/W R/W 9 12 config_byte_shell_3 1 1 R/W R/W 11 4 config_byte_shell_4 R/W R/W 3 R/W 2 1 0 - - R/W R/W 26 25 1 24 1 R/W 0 R/W R/W 18 17 0/1 16 0 R/W 0 R/W R/W 10 9 0 8 1 R/W 0 R/W R/W 2 1 0 R/W 0 R/W R/W 19 8 0 - 20 config_byte_shell_2 0 0 R/W R/W R/W 10 R/W 27 0 R/W 0 28 config_byte_shell_1 0 0 R/W R/W 16 1 R/W R/W R/W 17 0 - 24 0 R/W 18 3 - R/W 31 4 - R/W 0 11 R/W 12 config_byte_11 0 0 R/W 0 R/W - R/W 13 1 25 1 R/W 19 0 R/W R/W R/W 26 0 20 config_byte_10 0 0 R/W 0 0 R/W 27 0 R/W 22 0 0 1 0 R/W 28 config_byte_9 APCFG02/APCFG12 R/W 2 0 R/W 8 0 R/W 3 1 R/W 9 0 R/W 4 config_byte_8 R/W 10 0 R/W 5 16 0 R/W 11 0 R/W 6 0 R/W 0 17 0 R/W 12 config_byte_7 0 R/W 18 0 R/W 24 0 R/W 19 0 R/W 14 0 0 25 0 R/W 20 config_byte_6 R/W 26 0 R/W 21 0 0 R/W 27 0 R/W 22 0 1 1 0 R/W 28 config_byte_5 APCFG01/APCFG11 R/W 2 0 R/W 8 0 R/W 3 0 R/W 9 0 R/W 4 config_byte_4 0 R/W 10 0 R/W 16 0 R/W 11 0 R/W 6 1 0 R/W 17 0 R/W 12 config_byte_3 R/W 18 0 R/W 13 24 0 R/W 19 0 R/W 14 0 R/W 1 25 0 R/W 20 config_byte_2 1 26 0 R/W 21 0 27 0 R/W 22 0 0 0 0 R/W 0 R/W AShell and PHY configuration. Document Number: 002-04623 Rev. *B Page 50 of 144 CY91460S Series Module ID • MODULEID: Address 07320h MODULEID[31:0]: Version of the APIX® controller 10.3 APIX® PHY Configuration 10.3.1 Powerdown Configuration Vector: Bit APCFG 00 Default Description 31 0 global power down (upstream, downstream and PLL) 1: power down 0: power up 29 0 power down serializer and output driver (diff amp) 1: power down 0: power up 28 0 power down upstream path 1: power down 0: power up 10.3.2 Nominal Current Configuration Vector: Bit Default 19 0 18 0 17 0 16 0 15 0 14 0 APCFG 01 Description nominal current setting (64 steps) 000000: min (0 mA - power down output driver) 111111: max 10.3.3 Pre-emphasis Configuration Vector: Bit Default 26 0 25 0 24 0 APCFG 00 Description pre-emphasis configuration: reduce output current (pre-emphasis) after N equal serial bits (N = 0..7) Document Number: 002-04623 Rev. *B Page 51 of 144 CY91460S Series Configuration Vector: Bit APCFG 01 Default 13 0 12 0 11 0 10 0 9 0 8 0 Description pre-emphasis current setting (64 steps) 000000: min (0 mA - power down output driver) 111111: max 10.3.4 Sampling Offset Configuration Vector: Bit Default 11 0 10 0 9 0 8 0 APCFG 00 Description upstream sampling point configuration 0000: optimum sampling point when operating in 62.50 Mbit/s mode 0010: optimum sampling point when operating in 41.67 Mbit/s or 31.25 Mbit/s mode 0100: optimum sampling point when operating in 20.83 Mbit/s mode 10.3.5 Charge Pump Control Configuration Vector: Bit Default 23 1 22 0 21 0 20 0 APCFG 01 Description charge pump current control Document Number: 002-04623 Rev. *B Page 52 of 144 CY91460S Series 10.4 DMA transfer request To request a DMA transfer by a Transaction Buffer, please configure the transfer request source in DMACAx as follows. IS EIS(DDNO) RN Function Transfer stop request 10000 1010 160 APIX® Transaction Buffer 0 available 10001 1010 161 APIX® Transaction Buffer 1 available 10010 1010 162 ® available ® APIX Transaction Buffer 2 10011 1010 163 APIX Transaction Buffer 3 available 10100 1010 164 APIX® Transaction Buffer 4 available 10101 10110 1010 1010 165 166 ® available ® available ® APIX Transaction Buffer 5 APIX Transaction Buffer 6 10111 1010 167 APIX Transaction Buffer 7 available 11000 1010 168 APIX® Transaction Buffer 8 available 11001 11010 1010 1010 169 170 ® available ® available ® APIX Transaction Buffer 9 APIX Transaction Buffer 10 11011 1010 171 APIX Transaction Buffer 11 available 11100 1010 172 APIX® Transaction Buffer 12 available 11101 11110 11111 1010 1010 1010 173 174 175 Document Number: 002-04623 Rev. *B ® available ® available ® available APIX Transaction Buffer 13 APIX Transaction Buffer 14 APIX Transaction Buffer 15 Page 53 of 144 CY91460S Series 10.5 Automotive Interconnect Pins The AIC Pins also serve as general ports. Pin name Pin function RCK0 AIC uplink clock of Apix® link0 I/O format Pull-up Pull-down Standby control Setting required to use Set port function mode PFR28: Bit0 = 1, EPFR28: Bit0 = 1 Set port function mode PFR28: Bit1 = 1, EPFR28: Bit1 = 1 RDA00 AIC uplink data of Apix® link0 RDA01 Set port function mode PFR28: Bit2 = 1, EPFR28: Bit2 = 1 TDA00 Set port function mode PFR28: Bit5 = 1, EPFR28: Bit5 = 1 AIC downlink data of Apix® link0 Set port function mode PFR28: Bit6 = 1, EPFR28: Bit6 = 1 TDA01 TCLI0 AIC downlink clock of Apix® link0 RCK1 AIC uplink clock of Apix® link1 RDA10 AIC uplink data of Apix® link1 CMOS output and CMOS hysteresis, CMOS Automotive hysteresis, TTL input Programmable Provided Set port function mode PFR28: Bit7 = 1, EPFR28: Bit7 = 1 Set port function mode PFR17: Bit0 = 1, EPFR17: Bit0 = 1 Set port function mode PFR17: Bit1 = 1, EPFR17: Bit1 = 1 RDA11 Set port function mode PFR17: Bit2 = 1, EPFR17: Bit2 = 1 TDA10 Set port function mode PFR17: Bit5 = 1, EPFR17: Bit5 = 1 AIC downlink data of Apix® link1 TDA11 TCLI1 AIC downlink clock of Apix® link1 Document Number: 002-04623 Rev. *B Set port function mode PFR17: Bit6 = 1, EPFR17: Bit6 = 1 Set port function mode PFR17: Bit7 = 1, EPFR17: Bit7 = 1 Page 54 of 144 CY91460S Series 10.6 USECASES 10.6.1 Communication over APIX® link APIX® RX CY91F467SA Downlink over Pixelchannel Downlink over Pixelchannel is provided by default configuration. Please configure the PHY according to Chapter 10.3“APIX® PHY Configuration” Downlink over Sidebandchannel Register Bit Default Value APCFG01 31 1 0 Description 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode 10.6.2 Communication over Automotive Interconnect to external AShell 1Bit Datawidth D C CY91F467SA APIX® RX embedded TX D C Register Bit Default Value APCFGn1 31 1 0 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode APCFGn1 29 1 0 1: enable core clock of APIX® PHY 0: disable APCFGn3 23 1 0 1: sbup_data[1:0] 0: sbup_data[0] APCFGn3 21 1 0 1: sbdown_data[1:0] 0: sbdown_data[0] 1 AShell: connect internal Ashell to external APIX® PHY through GPIO interface 1: enable 0: disable APCFGn3 18 0 Document Number: 002-04623 Rev. *B Description Page 55 of 144 CY91460S Series 2Bit Datawidth D[1:0] C CY91F467SA APIX® RX embedded TX D [1:0] C Register Bit Default Value APCFGn1 31 1 0 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode APCFGn1 29 1 0 1: enable core clock of APIX® PHY 0: disable 1 AShell: connect internal Ashell to external APIX® PHY through GPIO interface 1: enable 0: disable APCFGn3 18 0 Document Number: 002-04623 Rev. *B Description Page 56 of 144 CY91460S Series 10.6.3 Communication over Automotive Interconnect to external PHY DACL SBDOWN DATA[1] D SBDOWN DATA[0] INAP 125T24 / embedded TX CY91F467SA APIX® RX DACL SBUP_DATA[1] D SBUP_DATA[0] Register Bit Default Value APCFGn1 31 1 0 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode APCFGn1 29 1 0 1: enable core clock of APIX® PHY 0: disable APCFGn3 22 0 1 AShell: validate sbup_data with 1: sbup_data[1] 0: sbup_valid APCFGn3 20 0 1 APCFGn3 19 0 0 APCFGn3 APCFGn3 18 0 2 0 1 0 0 0 30 0 29 1 28 0 27 0 26 1 25 1 24 0 Description AShell: generate sbdown clock and transmit as sbdown_data[1] 11: disable 10: with use of internal counter (asynchronous to core_clk of APIX® PHY) 01: with use of sbdown_trigger (synchronous to core_clk of APIX® PHY) 00: disable 1 AShell: connect internal Ashell to external APIX® PHY through GPIO interface 1: enable 0: disable t.b.d. AShell: configures cycle time of sbdown clock (multiples of Ashell core clock) when sbdown_data are asynchronous (sbdown_data[1] is used as sbdown clock) or cfg_spi_over_sb is enabled 0x0B: recommended minimum (no low bandwidth mode, AShell and APIX® PHY operate at same core clock frequency) 0x14: recommended minimum (low bandwidth mode 2, AShell and APIX® PHY operate at 62.5 MHz) 0x26: recommended minimum (low bandwidth mode 1, AShell and APIX® PHY operate at 62.5 MHz) 10.6.4 Caution Up to now only the usecases “Downlink over Pixelchannel” and 10.6.3“Communication over Automotive Interconnect to external PHY” are guaranteed. Document Number: 002-04623 Rev. *B Page 57 of 144 CY91460S Series 11. Memory Space The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH Document Number: 002-04623 Rev. *B Page 58 of 144 CY91460S Series 12. Memory Maps 12.1 CY91F467SA CY91F467SA 00000000H 00000400H 00001000H I/O (direct addressing area) I/O DMA 00002000H 00004000H Flash-Cache (8 KBytes) 00006000H 00007000H Flash memory control 00008000H 0000B000H 0000C000H Boot ROM (4 Kbytes) CAN 0000D000H 00028000H 00030000H D-RAM (0 wait, 32 Kbytes) ID-RAM (32 Kbytes) 00038000H 00040000H Flash memory (1088 Kbytes) 00150000H 00180000H External bus area 00500000H External data bus FFFFFFFFH Note: Document Number: 002-04623 Rev. *B Access prohibited areas Page 59 of 144 CY91460S Series 13. I/O Map 13.1 CY91F467SA Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX Block T-unit port data register Read/write attribute Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 1...) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.) Note : Initial values of register bits are represented as follows: “ 1 ” : Initial value “ 1 ” “ 0 ” : Initial value “ 0 ” “ X ” : Initial value “ undefined ” “ - ” : No physical register at this location Access is barred with an undefined data access attribute. Document Number: 002-04623 Rev. *B Page 60 of 144 CY91460S Series Address Register +0 +1 +2 000000H PDR00 [R/W] XXXXXXXX PDR01 [R/W] XXXXXXXX 000004H Reserved PDR05 [R/W] XXXXXXXX PDR06 [R/W] XXXXXXXX PDR07 [R/W] XXXXXXXX 000008H PDR08 [R/W] X - - X - - XX PDR09 [R/W] - - - - XXXX PDR10 [R/W] - - - - X - XX Reserved PDR14 [R/W] XXXXXXXX PDR15 [R/W] - - - - XXXX Reserved 00000CH +3 Block Reserved 000010H PDR16 [R/W] XXXXXXXX PDR17 [R/W] XXXXXXXX PDR18 [R/W] - XXX - XXX PDR19 [R/W] - XXX - XXX 000014H PDR20 [R/W] - XXX - XXX Reserved PDR22 [R/W] XXXX - X - X PDR23 [R/W] - X - XXXXX 000018H PDR24 [R/W] XXXXXXXX 00001CH PDR28 [R/W] XXXXXXXX R-bus Port Data Register Reserved PDR29 [R/W] XXXXXXXX 000024H to 00002CH Reserved Reserved 000030H EIRR0 [R/W] XXXXXXXX ENIR0 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 External interrupt (INT 0 to INT 7) 000034H EIRR1 [R/W] XXXXXXXX ENIR1 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 External interrupt (INT 8 to INT 15) 000038H DICR [R/W] -------0 HRCL [R/W] 0 - - 11111 RBSYNC*1 Delay Interrupt 00003CH to 00004CH Reserved SCR02 [R/W, W] 00000000 SMR02 [R/W, W] 00000000 000054H ESCR02 [R/W] 00000X00 ECCR02 [R/W, R, W] -00000XX 000058H SCR03 [R/W, W] 00000000 SMR03 [R/W, W] 00000000 ESCR03 [R/W] 00000X00 ECCR03 [R/W, R, W] -00000XX 000050H 00005CH SSR02 [R/W, R] 00001000 RDR02/TDR02 [R/W] 00000000 LIN-USART 2 Reserved SSR03 [R/W, R] 00001000 RDR03/TDR03 [R/W] 00000000 LIN-USART 3 Reserved (Continued) Document Number: 002-04623 Rev. *B Page 61 of 144 CY91460S Series Address Register +0 +1 +2 +3 000060H SCR04 [R/W, W] 00000000 SMR04 [R/W, W] 00000000 SSR04 [R/W, R] 00001000 RDR04/TDR04 [R/W] 00000000 000064H ESCR04 [R/W] 00000X00 ECCR04 [R/W, R, W] -00000XX FSR04 [R] - - - 00000 FCR04 [R/W] 0001 - 000 000068H SCR05 [R/W, W] 00000000 SMR05 [R/W, W] 00000000 SSR05 [R/W, R] 00001000 RDR05/TDR05 [R/W] 00000000 00006CH ESCR05 [R/W] 00000X00 ECCR05 [R/W, R, W] -00000XX FSR05 [R] - - - 00000 FCR05 [R/W] 0001 - 000 000070H SCR06 [R/W, W] 00000000 SMR06 [R/W, W] 00000000 SSR06 [R/W, R] 00001000 RDR06/TDR06 [R/W] 00000000 000074H ESCR06 [R/W] 00000X00 ECCR06 [R/W, R, W] -00000XX FSR06 [R] - - - 00000 FCR06 [R/W] 0001 - 000 000078H SCR07 [R/W, W] 00000000 SMR07 [R/W, W] 00000000 SSR07 [R/W, R] 00001000 RDR07/TDR07 [R/W] 00000000 00007CH ESCR07 [R/W] 00000X00 ECCR07 [R/W, R, W] -00000XX FSR07 [R] - - - 00000 FCR07 [R/W] 0001 - 000 000084H BGR102 [R/W] 00000000 BGR002 [R/W] 00000000 BGR103 [R/W] 00000000 BGR003 [R/W] 00000000 000088H BGR104 [R/W] 00000000 BGR004 [R/W] 00000000 BGR105 [R/W] 00000000 BGR005 [R/W] 00000000 00008CH BGR106 [R/W] 00000000 BGR006 [R/W] 00000000 BGR107 [R/W] 00000000 BGR007 [R/W] 00000000 Block LIN-USART 4 with FIFO LIN-USART 5 with FIFO LIN-USART 6 with FIFO LIN-USART 7 with FIFO Reserved 000080H 000090H to 0000CCH Baud rate Generator LIN-USART 2 to 7 Reserved 0000D0H IBCR0 [R/W] 00000000 IBSR0 [R] 00000000 ITBAH0 [R/W] - - - - - - 00 ITBAL0 [R/W] 00000000 0000D4H ITMKH0 [R/W] 00 - - - - 11 ITMKL0 [R/W] 11111111 ISMK0 [R/W] 01111111 ISBA0 [R/W] - 0000000 0000D8H Reserved IDAR0 [R/W] 00000000 ICCR0 [R/W] - 0011111 Reserved I2C 0 (Continued) Document Number: 002-04623 Rev. *B Page 62 of 144 CY91460S Series Address Register +0 +1 +2 +3 0000DCH IBCR1 [R/W] 00000000 IBSR1 [R] 00000000 ITBAH1[R/W] - - - - - - 00 ITBAL1 [R/W] 00000000 0000E0H ITMKH1 [R/W] 00 - - - - 11 ITMKL1 [R/W] 11111111 ISMK1 [R/W] 01111111 ISBA1 [R/W] - 0000000 0000E4H Reserved IDAR1 [R/W] 00000000 ICCR1 [R/W] - 0011111 Reserved 0000E8H to 0000FCH Block I2C 1 Reserved 000100H GCN10 [R/W] 00110010 00010000 Reserved GCN20 [R/W] - - - - 0000 PPG Control 0 to 3 000104H GCN11 [R/W] 00110010 00010000 Reserved GCN21 [R/W] - - - - 0000 PPG Control 4 to 7 000108H GCN12 [R/W] 00110010 00010000 Reserved GCN22 [R/W] - - - - 0000 PPG Control 8 to 11 Reserved 00010CH 000110H PTMR00 [R] 11111111 11111111 000114H PDUT00 [W] XXXXXXXX XXXXXXXX 000118H PTMR01 [R] 11111111 11111111 00011CH PDUT01 [W] XXXXXXXX XXXXXXXX 000120H PTMR02 [R] 11111111 11111111 000124H PDUT02 [W] XXXXXXXX XXXXXXXX 000128H PTMR03 [R] 11111111 11111111 00012CH PDUT03 [W] XXXXXXXX XXXXXXXX 000130H PTMR04 [R] 11111111 11111111 000134H PDUT04 [W] XXXXXXXX XXXXXXXX 000138H PTMR05 [R] 11111111 11111111 00013CH PDUT05 [W] XXXXXXXX XXXXXXXX PCSR00 [W] XXXXXXXX XXXXXXXX PCNH00 [R/W] 0000000 - PCNL00 [R/W] 000000 - 0 PCSR01 [W] XXXXXXXX XXXXXXXX PCNH01 [R/W] 0000000 - PCNL01 [R/W] 000000 - 0 PCSR02 [W] XXXXXXXX XXXXXXXX PCNH02 [R/W] 0000000 - PCNL02 [R/W] 000000 - 0 PCSR03 [W] XXXXXXXX XXXXXXXX PCNH03 [R/W] 0000000 - PCNL03 [R/W] 000000 - 0 PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 - PCNL04 [R/W] 000000 - 0 PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 - PCNL05 [R/W] 000000 - 0 PPG 0 PPG 1 PPG2 PPG3 PPG 4 PPG 5 (Continued) Document Number: 002-04623 Rev. *B Page 63 of 144 CY91460S Series Address Register +0 +1 000140H PTMR06 [R] 11111111 11111111 000144H PDUT06 [W] XXXXXXXX XXXXXXXX 000148H PTMR07 [R] 11111111 11111111 00014CH PDUT07 [W] XXXXXXXX XXXXXXXX 000150H PTMR08 [R] 11111111 11111111 000154H PDUT08 [W] XXXXXXXX XXXXXXXX 000158H PTMR09 [R] 11111111 11111111 00015CH PDUT09 [W] XXXXXXXX XXXXXXXX 000160H PTMR10 [R] 11111111 11111111 000164H PDUT10 [W] XXXXXXXX XXXXXXXX 000168H PTMR11 [R] 11111111 11111111 00016CH PDUT11 [W] XXXXXXXX XXXXXXXX 000170H P0TMCSRH [R/W] - 0 - 000 - 0 +2 +3 PCSR06 [W] XXXXXXXX XXXXXXXX PCNH06 [R/W] 0000000 - PCNL06 [R/W] 000000 - 0 PCSR07 [W] XXXXXXXX XXXXXXXX PCNH07 [R/W] 0000000 - PCNL07 [R/W] 000000 - 0 PCSR08 [W] XXXXXXXX XXXXXXXX PCNH08 [R/W] 0000000 - PCNL08 [R/W] 000000 - 0 PCSR09 [W] XXXXXXXX XXXXXXXX PCNH09 [R/W] 0000000 - PCNL09 [R/W] 000000 - 0 PCSR10 [W] XXXXXXXX XXXXXXXX PCNH10 [R/W] 0000000 - PCNL10 [R/W] 000000 - 0 PCSR11 [W] XXXXXXXX XXXXXXXX P0TMCSRL [R/W] - - - 00000 PCNH11 [R/W] 0000000 - PCNL11 [R/W] 000000 - 0 P1TMCSRH [R/W] - 0 - 000 - 0 P1TMCSRL [R/W] - - - 00000 000174H P0TMRLR [W] XXXXXXXX XXXXXXXX P0TMR [R] XXXXXXXX XXXXXXXX 000178H P1TMRLR [W] XXXXXXXX XXXXXXXX P1TMR [R] XXXXXXXX XXXXXXXX PPG 6 PPG 7 PPG 8 PPG 9 PPG 10 PPG 11 Pulse Frequency Modulator Reserved 00017CH 000180H Block Reserved ICS01 [R/W] 00000000 Reserved ICS23 [R/W] 00000000 000184H IPCP0 [R] XXXXXXXX XXXXXXXX IPCP1 [R] XXXXXXXX XXXXXXXX 000188H IPCP2 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX Input Capture 0 to 3 (Continued) Document Number: 002-04623 Rev. *B Page 64 of 144 CY91460S Series Address Register +0 +1 +2 +3 00018CH OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCS23 [R/W] - - - 0 - - 00 0000 - - 00 000190H OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP1 [R/W] XXXXXXXX XXXXXXXX 000194H OCCP2 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX 000198H SGCRH [R/W] 0000 - - 00 00019CH SGAR [R/W] 00000000 0001A0H SGCRL [R/W] - - 0 - - 000 Reserved ADERH [R/W] 00000000 00000000 SGFR [R/W, R] XXXXXXXX XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX ADCS1 [R/W] 00000000 ADCS0 [R/W] 00000000 ADCR1 [R] 000000XX ADCR0 [R] XXXXXXXX 0001A8H ADCT1 [R/W] 00010000 ADCT0 [R/W] 00101100 ADSCH [R/W] - - - 00000 ADECH [R/W] - - - 00000 0001ACH Reserved ACSR0 [R/W] - 11XXX00 TMRLR0 [W] XXXXXXXX XXXXXXXX 0001B4H Reserved 0001B8H TMRLR1 [W] XXXXXXXX XXXXXXXX 0001BCH Reserved 0001C0H TMRLR2 [W] XXXXXXXX XXXXXXXX 0001C4H Reserved 0001C8H TMRLR3 [W] XXXXXXXX XXXXXXXX 0001CCH Reserved Output Compare 0 to 3 Sound Generator ADERL [R/W] 00000000 00000000 0001A4 0001B0H Block Reserved Alarm Comparator 0 TMR0 [R] XXXXXXXX XXXXXXXX TMCSRH0 [R/W] - - - 00000 TMCSRL0 [R/W] 0 - 000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSRH1 [R/W] - - - 00000 TMCSRL1 [R/W] 0 - 000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSRH2 [R/W] - - - 00000 TMCSRL2 [R/W] 0 - 000000 TMR3 [R] XXXXXXXX XXXXXXXX TMCSRH3 [R/W] - - - 00000 A/D Converter TMCSRL3 [R/W] 0 - 000000 Reload Timer 0 (PPG 0, PPG 1) Reload Timer 1 (PPG 2, PPG 3) Reload Timer 2 (PPG 4, PPG 5) Reload Timer 3 (PPG 6, PPG 7) (Continued) Document Number: 002-04623 Rev. *B Page 65 of 144 CY91460S Series Address 0001D0H Register +0 +1 TMRLR4 [W] XXXXXXXX XXXXXXXX 0001D4H Reserved 0001D8H TMRLR5 [W] XXXXXXXX XXXXXXXX 0001DCH Reserved 0001E0H TMRLR6 [W] XXXXXXXX XXXXXXXX +2 +3 TMR4 [R] XXXXXXXX XXXXXXXX TMCSRH4 [R/W] - - - 00000 TMCSRL4 [R/W] 0 - 000000 TMR5 [R] XXXXXXXX XXXXXXXX TMCSRH5 [R/W] - - - 00000 TMCSRL5 [R/W] 0 - 000000 TMR6 [R] XXXXXXXX XXXXXXXX TMCSRH6 [R/W] - - - 00000 TMCSRL6 [R/W] 0 - 000000 0001E4H Reserved 0001E8H TMRLR7 [W] XXXXXXXX XXXXXXXX 0001ECH Reserved TMCSRH7 [R/W] - - - 00000 TMCSRL7 [R/W] 0 - 000000 0001F0H TCDT0 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS0 [R/W] 00000000 TCDT1 [R/W] XXXXXXXX XXXXXXXX Reserved TCDT2 [R/W] XXXXXXXX XXXXXXXX Reserved TCDT3 [R/W] XXXXXXXX XXXXXXXX Reserved 0001F4H 0001F8H 0001FCH TMR7 [R] XXXXXXXX XXXXXXXX TCCS1 [R/W] 00000000 TCCS2 [R/W] 00000000 TCCS3 [R/W] 00000000 Block Reload Timer 4 (PPG 8, PPG 9) Reload Timer 5 (PPG 10, PPG 11) Reload Timer 6 (PPG 12, PPG 13) Reload Timer 7 (PPG 14, PPG 15) (A/D Converter) Free Running Timer 0 (ICU 0, ICU 1) Free Running Timer 1 (ICU 2, ICU 3) Free Running Timer 2 (OCU 0, OCU 1) Free Running Timer 3 (OCU 2, OCU 3) (Continued) Document Number: 002-04623 Rev. *B Page 66 of 144 CY91460S Series Address Register +0 +1 +2 000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000228H to 00023CH Reserved 000240H DMACR [R/W] 00 - - 0000 DMAC Reserved Reserved ICS045 [R/W] 00000000 Reserved ICS67 [R/W] 00000000 0002D4H IPCP4 [R] XXXXXXXX XXXXXXXX IPCP5 [R] XXXXXXXX XXXXXXXX 0002D8H IPCP6 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX 0002DCH to 0002ECH 0002F0H Block Reserved 000244H to 0002CCH 0002D0H +3 Input Capture 4 to 7 Reserved TCDT4 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS4 [R/W] 00000000 Free Running Timer 4 (ICU 4, ICU 5) (Continued) Document Number: 002-04623 Rev. *B Page 67 of 144 CY91460S Series Address Register +1 Block +2 +3 TCDT5 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS5 [R/W] 00000000 0002F8H TCDT6 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS6 [R/W] 00000000 Free Running Timer 6 0002FCH TCDT7 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS7 [R/W] 00000000 Free Running Timer 7 0002F4H +0 000300H UDRC1 [W] 00000000 UDRC0 [W] 00000000 UDCR1 [R] 00000000 UDCR0 [R] 00000000 000304H UDCCH0 [R/W] 00000000 UDCCL0 [R/W] 00000000 Reserved UDCS0 [R/W] 00000000 000308H UDCCH1 [R/W] 00000000 UDCCL1[R/W] 00000000 Reserved UDCS1 [R/W] 00000000 (ICU 6, ICU 7) Up/Down Counter 0/1 Reserved 00030CH 000310H UDRC3 [W] 00000000 UDRC2 [W] 00000000 UDCR3 [R] 00000000 UDCR2 [R] 00000000 000314H UDCCH2 [R/W] 00000000 UDCCL2 [R/W] 00000000 Reserved UDCS2 [R/W] 00000000 000318H UDCCH3 [R/W] 00000000 UDCCL3 [R/W] 00000000 Reserved UDCS3 [R/W] 00000000 Reserved GCN23 [R/W] - - - - 0000 Up/Down Counter 2/3 Reserved 00031CH 000320H Free Running Timer 5 GCN13 [R/W] 00110010 00010000 000324H to 00032CH PPG Control 12 to 15 Reserved 000330H PTMR12 [R] 11111111 11111111 000334H PDUT12 [W] XXXXXXXX XXXXXXXX 000338H PTMR13 [R] 11111111 11111111 00033CH PDUT13 [W] XXXXXXXX XXXXXXXX 000340H PTMR14 [R] 11111111 11111111 000344H PDUT14 [W] XXXXXXXX XXXXXXXX PCSR12 [W] XXXXXXXX XXXXXXXX PCNH12 [R/W] 0000000 - PCNL12 [R/W] 000000 - 0 PCSR13 [W] XXXXXXXX XXXXXXXX PCNH13 [R/W] 0000000 - PCNL13 [R/W] 000000 - 0 PCSR14 [W] XXXXXXXX XXXXXXXX PCNH14 [R/W] 0000000 - PCNL14 [R/W] 000000 - 0 PPG 12 PPG 13 PPG 14 (Continued) Document Number: 002-04623 Rev. *B Page 68 of 144 CY91460S Series Address Register +0 +1 000348H PTMR15 [R] 11111111 11111111 00034CH PDUT15 [W] XXXXXXXX XXXXXXXX 000350H to 000364H +2 +3 PCSR15 [W] XXXXXXXX XXXXXXXX PCNH15 [R/W] 0000000 - PCNL15 [R/W] 000000 - 0 PPG 15 Reserved 000368H IBCR2 [R/W] 00000000 IBSR2 [R] 00000000 ITBAH2 [R/W] - - - - - - 00 ITBAL2 [R/W] 00000000 00036CH ITMKH2 [R/W] 00 - - - - 11 ITMKL2 [R/W] 11111111 ISMK2 [R/W] 01111111 ISBA2 [R/W] - 0000000 000370H Reserved IDAR2 [R/W] 00000000 ICCR2 [R/W] - 0011111 Reserved 000374H to 00038CH 000390H Block I2C 2 Reserved ROMS [R] 11111111 00000000 Reserved 000394H to 0003ECH Reserved 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H to 00043CH Reserved ROM Select Register Bit Search Module (Continued) Document Number: 002-04623 Rev. *B Page 69 of 144 CY91460S Series Address Register +0 +1 +2 +3 000440H ICR00 [R/W] ---11111 ICR01 [R/W] ---11111 ICR02 [R/W] ---11111 ICR03 [R/W] ---11111 000444H ICR04 [R/W] ---11111 ICR05 [R/W] ---11111 ICR06 [R/W] ---11111 ICR07 [R/W] ---11111 000448H ICR08 [R/W] ---11111 ICR09 [R/W] ---11111 ICR10 [R/W] ---11111 ICR11 [R/W] ---11111 00044CH ICR12 [R/W] ---11111 ICR13 [R/W] ---11111 ICR14 [R/W] ---11111 ICR15 [R/W] ---11111 000450H ICR16 [R/W] ---11111 ICR17 [R/W] ---11111 ICR18 [R/W] ---11111 ICR19 [R/W] ---11111 000454H ICR20 [R/W] ---11111 ICR21 [R/W] ---11111 ICR22 [R/W] ---11111 ICR23 [R/W] ---11111 000458H ICR24 [R/W] ---11111 ICR25 [R/W] ---11111 ICR26 [R/W] ---11111 ICR27 [R/W] ---11111 00045CH ICR28 [R/W] ---11111 ICR29 [R/W] ---11111 ICR30 [R/W] ---11111 ICR31 [R/W] ---11111 000460H ICR32 [R/W] ---11111 ICR33 [R/W] ---11111 ICR34 [R/W] ---11111 ICR35 [R/W] ---11111 000464H ICR36 [R/W] ---11111 ICR37 [R/W] ---11111 ICR38 [R/W] ---11111 ICR39 [R/W] ---11111 000468H ICR40 [R/W] ---11111 ICR41 [R/W] ---11111 ICR42 [R/W] ---11111 ICR43 [R/W] ---11111 00046CH ICR44 [R/W] ---11111 ICR45 [R/W] ---11111 ICR46 [R/W] ---11111 ICR47 [R/W] ---11111 000470H ICR48 [R/W] ---11111 ICR49 [R/W] ---11111 ICR50 [R/W] ---11111 ICR51 [R/W] ---11111 000474H ICR52 [R/W] ---11111 ICR53 [R/W] ---11111 ICR54 [R/W] ---11111 ICR55 [R/W] ---11111 000478H ICR56 [R/W] ---11111 ICR57 [R/W] ---11111 ICR58 [R/W] ---11111 ICR59 [R/W] ---11111 00047CH ICR60 [R/W] ---11111 ICR61 [R/W] ---11111 ICR62 [R/W] ---11111 ICR63 [R/W] ---11111 000480H RSRR [R/W] 10000000 STCR [R/W] 00110011 TBCR [R/W] 00XXX - 00 CTBR [W] XXXXXXXX 000484H CLKR [R/W] ---- 0000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 00048CH PLLDIVM [R/W] - - - - 0000 PLLDIVN [R/W] - - 000000 000490H PLLCTRL [R/W] - - - - 0000 Block Interrupt Controller Clock Control Reserved 000488H PLLDIVG [R/W] - - - - 0000 PLLDIVG [W] 00000000 PLL Interface Reserved (Continued) Document Number: 002-04623 Rev. *B Page 70 of 144 CY91460S Series Address Register +0 +1 +2 +3 000494H OSCC1 [R/W] - - - - - 010 OSCS1 [R/W] 00001111 OSCC2 [R/W] - - - - - 010 OSCS2 [R/W] 00001111 000498H PORTEN [R/W] - - - - - - 00 Block Main/Sub Oscillator Control Port Input Enable Control Reserved Reserved 00049CH WTCER [R/W] - - - - - - 00 WTCR [R/W] 00000000 000 - 00 - 0 0004A0H Reserved 0004A4H Reserved 0004A8H WTHR [R/W] - - - 00000 WTMR [R/W] - - 000000 WTSR [R/W] - - 000000 Reserved 0004ACH CSVTR [R/W] - - - 00010 CSVCR [R/W] 00011100 CSCFG [R/W] 0X000000 CMCFG [R/W] 00000000 WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX 0004B0H CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTD [R/W] 10000000 00000000 0004B4H CUTR1 [R] - - - - - - - - 00000000 CUTR2 [R] 00000000 00000000 0004B8H CMPR [R/W] - - 000010 11111101 0004BCH CMT1 [R/W] 00000000 1 - - - 0000 CMCR [R/W] - 001 - - 00 Reserved CMT2 [R/W] - - 000000 - - 000000 Real Time Clock (Watch Timer) ClockSupervisor / Selector / Monitor Calibration of Sub Clock Clock Modulator 0004C0H CANPRE [R/W] - - 000000 CANCKD [R/W] - - - - - - 00*3 0004C4H LVSEL [R/W] 00000111 LVDET [R/W] 0000 0 - 00 HWWDE [R/W] - - - - - - 00 HWWD [R/W, W] 00011000 Low Voltage Detection/Hardware Watchdog 0004C8H OSCRH [R/W] 000 - - 001 OSCRL [R/W] - - - - - 000 WPCRH [R/W] 00 - - - 000 WPCRL [R/W] - - - - - - 00 Main-/Sub-Oscillation Stabilization Timer 0004CCH OSCCR [R/W] -------0 Reserved REGSEL [R/W] - - 000100 REGCTR [R/W] - - - 0 - - 00 Main- Oscillation Standby Control Main-/Subregulator Control 0004D0H to 00063CH Reserved CAN Clock Control Reserved (Continued) Document Number: 002-04623 Rev. *B Page 71 of 144 CY91460S Series Address Register +0 +1 +2 +3 000640H ASR0 [R/W] 00000000 00000000 ACR0 [R/W] 1111**00 00100000*4 000644H ASR1 [R/W] XXXXXXXX XXXXXXXX ACR1 [R/W] XXXXXXXX XXXXXXXX 000648H ASR2 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX 00064CH ASR3 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX 000650H ASR4 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX 000654H ASR5 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX 000658H ASR6 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX 00065CH ASR7 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX 000660H AWR0 [R/W] 01001111 11111011 AWR1 [R/W] XXXXXXXX XXXXXXXX 000664H AWR2 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX 000668H AWR4 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX 00066CH AWR6 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX 000670H MCRA [R/W] XXXXXXXX MCRB [R/W] XXXXXXXX IORW0 [R/W] XXXXXXXX IORW1 [R/W] XXXXXXXX Reserved IORW2 [R/W] XXXXXXXX Reserved Reserved 00067CH 000680H CSER [R/W] 00000001 CHER [R/W] 11111111 000684H RCRH [R/W] 00XXXXXX RCRL [R/W] XXXX0XXX 000688H to 0007F8H 0007FCH External Bus Reserved 000674H 000678H Block TCR [R/W] 0000**** *5 Reserved Reserved Reserved Reserved MODR [W] XXXXXXXX Reserved Mode Register (Continued) Document Number: 002-04623 Rev. *B Page 72 of 144 CY91460S Series Address Register +0 +1 000800H to 000CFCH +2 +3 Block Reserved 000D00H PDRD00 [R] XXXXXXXX PDRD01 [R] XXXXXXXX 000D04H Reserved PDRD05 [R] XXXXXXXX PDRD06 [R] XXXXXXXX PDRD07 [R] XXXXXXXX 000D08H PDRD08 [R] X - - X - - XX PDRD09 [R] - - - - XXXX PDRD10 [R] - - - - X - XX Reserved PDRD14 [R] XXXXXXXX PDRD15 [R] - - - - XXXX Reserved 000D0CH Reserved 000D10H PDRD16 [R] XXXXXXXX PDRD17 [R] XXXXXXXX PDRD18 [R] - XXX - XXX PDRD19 [R] - XXX - XXX 000D14H PDRD20 [R] - XXX - XXX Reserved PDRD22 [R] XXXX - X - X PDRD23 [R] -X - XXXXX 000D18H PDRD24 [R] XXXXXXXX Reserved Reserved 000D1CH PDRD28 [R] XXXXXXXX PDRD29 [R] XXXXXXXX Reserved 000D20H to 000D3CH R-bus Port Data Direct Read Register Reserved 000D40H DDR00 [R/W] 00000000 DDR01 [R/W] 00000000 000D44H Reserved DDR05 [R/W] 00000000 DDR06 [R/W] 00000000 DDR07 [R/W] 00000000 000D48H DDR08 [R/W] 0 - - 0 - -00 DDR09 [R/W] - - - - 0000 DDR10 [R/W] - - - - 0 - 00 Reserved 000D4CH Reserved Reserved DDR14 [R/W] 00000000 DDR15 [R/W] - - - - 0000 000D50H DDR16 [R/W] 00000000 DDR17 [R/W] 00000000 DDR18 [R/W] - 000 - 000 DDR19 [R/W] - 000 - 000 000D54H DDR20 [R/W] - 000 - 000 Reserved DDR22 [R/W] 0000 - 0 - 0 DDR23 [R/W] - 0 - 00000 000D58H DDR24 [R/W] 00000000 Reserved Reserved Reserved 000D5CH DDR28 [R/W] 00000000 DDR29 [R/W] 00000000 000D60H to 000D7CH Reserved R-bus Port Direction Register Reserved Reserved (Continued) Document Number: 002-04623 Rev. *B Page 73 of 144 CY91460S Series Address Register +0 +1 +2 000D80H PFR00 [R/W] 00000000 PFR01 [R/W] 00000000 000D84H Reserved PFR05 [R/W] 00000000 PFR06 [R/W] 00000000 PFR07 [R/W] 00000000 000D88H PFR08 [R/W] 0 - - 0 - - 00 PFR09 [R/W] - - - - 0000 PFR10 [R/W] - - - - 0 - 00 Reserved PFR14 [R/W] 00000000 PFR15 [R/W] - - - - 0000 Reserved 000D8CH +3 Reserved 000D90H PFR16 [R/W] 00000000 PFR17 [R/W] 00000000 PFR18 [R/W] - 000 - 000 PFR19 [R/W] - 000 - 000 000D94H PFR20 [R/W] - 000 - 000 Reserved PFR22 [R/W] 0000 - 0 - 0 PFR23 [R/W] - 0 - 00000 000D98H PFR24 [R/W] 00000000 000D9CH PFR28 [R/W] 00000000 R-bus Port Function Register Reserved PFR29 [R/W] 00000000 000DA0H to 000DBCH Reserved Reserved 000DC0H EPFR00 [R/W] -------- EPFR01 [R/W] -------- 000DC4H Reserved EPFR05 [R/W] -------- EPFR06 [R/W] -------- EPFR07 [R/W] -------- 000DC8H EPFR08 [R/W] -------- EPFR09 [R/W] -------- EPFR10 [R/W] -------0 Reserved EPFR14 [R/W] 00000000 EPFR15 [R/W] - - - - 0000 000DCCH Block Reserved Reserved 000DD0H EPFR16 [R/W] 0000 - - - - EPFR17 [R/W] - 000 - 000 EPFR18 [R/W] - 000 - 000 EPFR19 [R/W] - 0- - - 0- - 000DD4H EPFR20 [R/W] - 000 - 000 Reserved EPFR22 [R/W] -------- EPFR23 [R/W] -------- 000DD8H EPFR24 [R/W] -------- 000DDCH EPFR28 [R/W] - 000 - 000 000DE0H to 000DFCH R-bus Extra Port Function Register Reserved EPFR29 [R/W] -------- Reserved Reserved (Continued) Document Number: 002-04623 Rev. *B Page 74 of 144 CY91460S Series Address Register +0 +1 +2 000E00H PODR00 [R/W] 00000000 PODR01 [R/W] 00000000 000E04H Reserved PODR05 [R/W] 00000000 PODR06 [R/W] 00000000 PODR07 [R/W] 00000000 000E08H PODR08 [R/W] 0 - - 0 - - 00 PODR09 [R/W] - - - - 0000 PODR10 [R/W] - - - - 0 - 00 Reserved PODR14 [R/W] 00000000 PODR15 [R/W] - - - - 0000 Reserved 000E0CH +3 Reserved 000E10H PODR16 [R/W] 00000000 PODR17 [R/W] 0000 - - - - PODR18 [R/W] - 000 - 000 PODR19 [R/W] - 000 - 000 000E14H PODR20 [R/W] - 000 - 000 Reserved PODR22 [R/W] 0000 - 0 - 0 PODR23 [R/W] - 0 - 00000 000E18H PODR24 [R/W] 00000000 000E1CH PODR28 [R/W] 00000000 R-bus Port Output Drive Select Register Reserved PODR29 [R/W] 00000000 000E20H to 000E3CH Reserved Reserved 000E40H PILR00 [R/W] 00000000 PILR01 [R/W] 00000000 000E44H Reserved PILR05 [R/W] 00000000 PILR06 [R/W] 00000000 PILR07 [R/W] 00000000 000E48H PILR08 [R/W] 0 - - 0 - - 00 PILR09 [R/W] - - - - 0000 PILR10 [R/W] - - - - 0 - 00 Reserved PILR14 [R/W] 00000000 PILR15 [R/W] - - - - 0000 000E4CH Block Reserved Reserved 000E50H PILR16 [R/W] 00000000 PILR17 [R/W] 0000 - - - - PILR18 [R/W] - 000 - 000 PILR19 [R/W] - 000 - 000 000E54H PILR20 [R/W] - 000 - 000 Reserved PILR22 [R/W] 0000 - 0 - 0 PILR23 [R/W] - 0 - 00000 000E58H PILR24 [R/W] 00000000 000E5CH PILR28 [R/W] 00000000 000E60H to 000E7CH R-bus Port Input Level Select Register Reserved PILR29 [R/W] 00000000 Reserved Reserved (Continued) Document Number: 002-04623 Rev. *B Page 75 of 144 CY91460S Series Address Register +0 +1 +2 000E80H EPILR00 [R/W] 00000000 EPILR01 [R/W] 00000000 000E84H Reserved EPILR05 [R/W] 00000000 EPILR06 [R/W] 00000000 EPILR07 [R/W] 00000000 000E88H EPILR08 [R/W] 0 - - 0 - - 00 EPILR09 [R/W] - - - - 0000 EPILR10 [R/W] - - - - 0 - 00 Reserved EPILR14 [R/W] 00000000 EPILR15 [R/W] - - - - 0000 Reserved 000E8CH +3 Reserved 000E90H EPILR16 [R/W] 00000000 EPILR17 [R/W] 0000 - - - - EPILR18 [R/W] - 000 - 000 EPILR19 [R/W] - 000 - 000 000E94H EPILR20 [R/W] - 000 - 000 Reserved EPILR22 [R/W] 0000 - 0 - 0 EPILR23 [R/W] - 0 - 00000 000E98H EPILR24 [R/W] 00000000 000E9CH EPILR28 [R/W] 00000000 R-bus Extra Port Input Level Select Register Reserved EPILR29 [R/W] 00000000 000EA0H to 000EBCH Reserved Reserved 000EC0H PPER00 [R/W] 00000000 PPER01 [R/W] 00000000 000EC4H Reserved PPER05 [R/W] 00000000 PPER06 [R/W] 00000000 PPER07 [R/W] 00000000 000EC8H PPER08 [R/W] 0 - - 0 - - 00 PPER09 [R/W] - - - - 0000 PPER10 [R/W] - - - - 0 - 00 Reserved PPER14 [R/W] 00000000 PPER15 [R/W] - - - - 0000 000ECCH Block Reserved Reserved 000ED0H PPER16 [R/W] 00000000 PPER17 [R/W] 0000 - - - - PPER18 [R/W] - 000 - 000 PPER19 [R/W] - 000 - 000 000ED4H PPER20 [R/W] - 000 - 000 Reserved PPER22 [R/W] 0000 - 0 - 0 PPER23 [R/W] - 0 - 00000 000ED8H PPER24 [R/W] 00000000 000EDCH PPER28 [R/W] 00000000 000EE0H to 000EFCH R-bus Port Pull-Up/Down Enable Register Reserved PPER29 [R/W] 00000000 Reserved Reserved (Continued) Document Number: 002-04623 Rev. *B Page 76 of 144 CY91460S Series Address Register +0 +1 000F00H PPCR00 [R/W] 11111111 PPCR01 [R/W] 11111111 000F04H Reserved PPCR05 [R/W] 11111111 PPCR06 [R/W] 11111111 PPCR07 [R/W] 11111111 000F08H PPCR08 [R/W] 1 - - 1- - 11 PPCR09 [R/W] - - - - 1111 PPCR10 [R/W] - - - - 1 - 11 Reserved PPCR14 [R/W] 11111111 PPCR15 [R/W] - - - - 1111 000F0CH +2 Reserved +3 Block Reserved 000F10H PPCR16 [R/W] 11111111 PPCR17 [R/W] 11111111 PPCR18 [R/W] - 111 - 111 PPCR19 [R/W] - 111 - 111 000F14H PPCR20 [R/W] - 111 - 111 Reserved PPCR22 [R/W] 1111 - 1 - 1 PPCR23 [R/W] - 1 - 11111 000F18H PPCR24 [R/W] 11111111 000F1CH PPCR28 [R/W] 11111111 R-bus Port Pull-Up/Down Control Register Reserved PPCR29 [R/W] 11111111 Reserved 000F20H to 000F3CH Reserved 001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMAC (Continued) Document Number: 002-04623 Rev. *B Page 77 of 144 CY91460S Series Address Register +0 +1 001028H to 001FFCH 002000H to 006FFCH 007000H 007004H +2 +3 Block Reserved CY91F467SA Flash-cache size is 8 Kbytes : 004000H to 005FFCH FMCS [R/W] 01101000 FMCR [R] - - - 00000 FCHCR [R/W] - - - - - - 00 10000011 FMWT [R/W] 11111111 11111111 FMWT2 [R] - 001 - - - - 007008H FMAC [R] 00000000 00000000 00000000 00000000 00700CH FCHA0 [R/W] - - - - - - - - - - - 00000 00000000 00000000 007010H FCHA1 [R/W] - - - - - - - - - - - 00000 00000000 00000000 007014H to 0071FCH FMPS [R/W] - - - - - 000 Flash-cache / I-RAM area Flash Memory/ Flash-cache/ I-RAM Control Register Flash-cache Non-cacheable area setting Register Reserved 007200H RHCTRL[R/W] 00 - - 0000 - - - - - - - - 0000 - 000 - - - - - - - - 007204H Reserved 007208H CHCTRL0[R/W] - - - - 0 - - - 000 - - - 00 - 0000000 - - 00 - 111 00720CH CHSTAT0[R] 00000000 - - - - - - - - 00000000 00000000 007210H CHWDG0[R/W] 00 - - 0000 00000000 xxxxxxxx xxxxxxxx 007214H CHCTRL1[R/W] - - - - 0 - - - 000 - - - 00 - 0000000 - - 00 - 111 007218H CHSTAT1[R] 00000000 - - - - - - - - 00000000 00000000 00721CH CHWDG1[R/W] 00 - - 0000 00000000 xxxxxxxx xxxxxxxx Automotive Remote Handler Control APIX® Control/Status (Continued) Document Number: 002-04623 Rev. *B Page 78 of 144 CY91460S Series Address Register +0 +1 +2 +3 007220H TBCTRL00[R/W] - - - 00000 0000 - 000 TBCTRL01[R/W] - - - 00000 0000 - 000 007224H TBCTRL02[R/W] - - - 00000 0000 - 000 TBCTRL03[R/W] - - - 00000 0000 - 000 007228H TBCTRL04[R/W] - - - 00000 0000 - 000 TBCTRL05[R/W] - - - 00000 0000 - 000 00722CH TBCTRL06[R/W] - - - 00000 0000 - 000 TBCTRL07[R/W] - - - 00000 0000 - 000 007230H TBCTRL08[R/W] - - - 00000 0000 - 000 TBCTRL09[R/W] - - - 00000 0000 - 000 007234H TBCTRL10[R/W] - - - 00000 0000 - 000 TBCTRL11[R/W] - - - 00000 0000 - 000 007238H TBCTRL12[R/W] - - - 00000 0000 - 000 TBCTRL13[R/W] - - - 00000 0000 - 000 00723CH TBCTRL14[R/W] - - - 00000 0000 - 000 TBCTRL15[R/W] - - - 00000 0000 - 000 007240H TBIRQ[R] 00000000 00000000 Reserved 007244H to 00724CH Block Automotive Remote Handler Transaction Buffer Control Automotive Remote Handler Interrupt Reserved 007250H TFCRTL00[R/W] 00 - 00000 TFIDX00[R/W] 00000000 TFCRTL01[R/W] 00 - 00000 TFIDX01[R/W] 00000000 007254H TFCRTL02[R/W] 00 - 00000 TFIDX02[R/W] 00000000 TFCRTL03[R/W] 00 - 00000 TFIDX03[R/W] 00000000 007258H TFCRTL04[R/W] 00 - 00000 TFIDX04[R/W] 00000000 TFCRTL05[R/W] 00 - 00000 TFIDX05[R/W] 00000000 00725CH TFCRTL06[R/W] 00 - 00000 TFIDX06[R/W] 00000000 TFCRTL07[R/W] 00 - 00000 TFIDX07[R/W] 00000000 007260H TFCRTL08[R/W] 00 - 00000 TFIDX08[R/W] 00000000 TFCRTL09[R/W] 00 - 00000 TFIDX09[R/W] 00000000 007264H TFCRTL10[R/W] 00 - 00000 TFIDX10[R/W] 00000000 TFCRTL11[R/W] 00 - 00000 TFIDX11[R/W] 00000000 007268H TFCRTL12[R/W] 00 - 00000 TFIDX12[R/W] 00000000 TFCRTL13[R/W] 00 - 00000 TFIDX13[R/W] 00000000 00726CH TFCRTL14[R/W] 00 - 00000 TFIDX14[R/W] 00000000 TFCRTL15[R/W] 00 - 00000 TFIDX15[R/W] 00000000 007270H TFADDR00[R/W] - - - - - - - - - - - - 0000 00000000 00000000 007274H TFADDR01[R/W] - - - - - - - - - - - - 0000 00000000 00000000 Transaction Frame (Continued) Document Number: 002-04623 Rev. *B Page 79 of 144 CY91460S Series Address Register +0 +1 +2 007278H TFADDR02[R/W] - - - - - - - - - - - - 0000 00000000 00000000 00727CH TFADDR03[R/W] - - - - - - - - - - - - 0000 00000000 00000000 007280H TFADDR04[R/W] - - - - - - - - - - - - 0000 00000000 00000000 007284H TFADDR05[R/W] - - - - - - - - - - - - 0000 00000000 00000000 007288H TFADDR06[R/W] - - - - - - - - - - - - 0000 00000000 00000000 00728CH TFADDR07[R/W] - - - - - - - - - - - - 0000 00000000 00000000 007290H TFADDR08[R/W] - - - - - - - - - - - - 0000 00000000 00000000 007294H TFADDR09[R/W] - - - - - - - - - - - - 0000 00000000 00000000 007298H TFADDR10[R/W] - - - - - - - - - - - - 0000 00000000 00000000 00729CH TFADDR11[R/W] - - - - - - - - - - - - 0000 00000000 00000000 0072A0H TFADDR12[R/W] - - - - - - - - - - - - 0000 00000000 00000000 0072A4H TFADDR13[R/W] - - - - - - - - - - - - 0000 00000000 00000000 0072A8H TFADDR14[R/W] - - - - - - - - - - - - 0000 00000000 00000000 0072ACH TFADDR15[R/W] - - - - - - - - - - - - 0000 00000000 00000000 0072B0H TFDATA00[R/W] 00000000 00000000 00000000 00000000 0072B4H TFDATA01[R/W] 00000000 00000000 00000000 00000000 0072B8H TFDATA02[R/W] 00000000 00000000 00000000 00000000 0072BCH TFDATA03[R/W] 00000000 00000000 00000000 00000000 0072C0H TFDATA04[R/W] 00000000 00000000 00000000 00000000 0072C4H TFDATA05[R/W] 00000000 00000000 00000000 00000000 0072C8H TFDATA06[R/W] 00000000 00000000 00000000 00000000 +3 Block (Continued) Document Number: 002-04623 Rev. *B Page 80 of 144 CY91460S Series Address Register +0 +1 +2 0072CCH TFDATA07[R/W] 00000000 00000000 00000000 00000000 0072D0H TFDATA08[R/W] 00000000 00000000 00000000 00000000 0072D4H TFDATA09[R/W] 00000000 00000000 00000000 00000000 0072D8H TFDATA10[R/W] 00000000 00000000 00000000 00000000 0072DCH TFDATA11[R/W] 00000000 00000000 00000000 00000000 0072E0H TFDATA12[R/W] 00000000 00000000 00000000 00000000 0072E4H TFDATA13[R/W] 00000000 00000000 00000000 00000000 0072E8H TFDATA14[R/W] 00000000 00000000 00000000 00000000 0072ECH TFDATA15[R/W] 00000000 00000000 00000000 00000000 0072F0H EVCTRL[R/W] - - - - - - - 0 0 - 000000 00000000 00000000 0072F4H Reserved 0072F8H EVBUF0[R/W] - - - - - - - 0 00000000 - - - - - - - - - - - - - - - - 0072FCH EVBUF1[R/W] 00000000 00000000 00000000 00000000 007300H APCFG00[R/W] 00000000 00110000 00000000 10010000 007304H APCFG01[R/W] 11110000 10000000 00000000 01001000 007308H APCFG02[R/W] 00000010 00000010 01000000 - - - - - - - - 00730CH APCFG03[R/W] 00100110 10100000 10011010 00 - - - 000 007310H APCFG10[R/W] 00000000 00110000 00000000 10010000 007314H APCFG11[R/W] 11110000 00000000 00000000 01001000 007318H APCFG12[R/W] 00000010 00000010 01000000 - - - - - - - - 00731CH APCFG13[R/W] 00100110 10100100 10011010 00 - - - 000 +3 Block Automotive Remote Handler Eventcontrol Automotive Remote Handler Eventqueue APIX® Configuration (Continued) Document Number: 002-04623 Rev. *B Page 81 of 144 CY91460S Series Address Register +0 +1 +2 +3 007320H MODULEID[R] 0 - - - - - - - ******** ******** ******** *6 007324H to 007FFCH Reserved 008000H to 00BFFCH CY91F467SA Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH (instruction access is 1 wait cycle, data access is 1 wait cycle) 00C000H CTRLR0 [R/W] 00000000 00000001 STATR0 [R/W] 00000000 00000000 00C004H ERRCNT0 [R] 00000000 00000000 BTR0 [R/W] 00100011 00000001 00C008H INTR0 [R] 00000000 00000000 TESTR0 [R/W] 00000000 X0000000 00C00CH BRPE0 [R/W] 00000000 00000000 CBSYNC*2 00C010H IF1CREQ0 [R/W] 00000000 00000001 IF1CMSK0 [R/W] 00000000 00000000 00C014H IF1MSK20 [R/W] 11111111 11111111 IF1MSK10 [R/W] 11111111 11111111 00C018H IF1ARB20 [R/W] 00000000 00000000 IF1ARB10 [R/W] 00000000 00000000 00C01CH IF1MCTR0 [R/W] 00000000 00000000 Reserved 00C020H IF1DTA10 [R/W] 00000000 00000000 IF1DTA20 [R/W] 00000000 00000000 00C024H IF1DTB10 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 00C028H, 00C02CH Reserved 00C030H IF1DTA20 [R/W] 00000000 00000000 IF1DTA10 [R/W] 00000000 00000000 00C034H IF1DTB20 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 00C038H, 00C03CH Block Version of APIX® Controller Boot ROM area CAN 0 Control Register CAN 0 IF 1 Register CAN 0 IF 1 Register Reserved (Continued) Document Number: 002-04623 Rev. *B Page 82 of 144 CY91460S Series Address Register +0 +1 +2 +3 00C040H IF2CREQ0 [R/W] 00000000 00000001 IF2CMSK0 [R/W] 00000000 00000000 00C044H IF2MSK20 [R/W] 11111111 11111111 IF2MSK10 [R/W] 11111111 11111111 00C048H IF2ARB20 [R/W] 00000000 00000000 IF2ARB10 [R/W] 00000000 00000000 00C04CH IF2MCTR0 [R/W] 00000000 00000000 Reserved 00C050H IF2DTA10 [R/W] 00000000 00000000 IF2DTA20 [R/W] 00000000 00000000 00C054H IF2DTB10 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 00C058H, 00C05CH IF2DTA20 [R/W] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 00C064H IF2DTB20 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 00C068H to 00C07CH Reserved TREQR20 [R] 00000000 00000000 00C084H to 00C08CH 00C090H NEWDT20 [R] 00000000 00000000 NEWDT10 [R] 00000000 00000000 CAN 0 Status Flags Reserved INTPND20 [R] 00000000 00000000 00C0A4H to 00C0ACH 00C0B0H TREQR10 [R] 00000000 00000000 Reserved 00C094H to 00C09CH 00C0A0H CAN 0 IF 2 Register Reserved 00C060H 00C080H Block INTPND10 [R] 00000000 00000000 Reserved MSGVAL20 [R] 00000000 00000000 00C0B4H to 00C0FCH MSGVAL10 [R] 00000000 00000000 Reserved (Continued) Document Number: 002-04623 Rev. *B Page 83 of 144 CY91460S Series Address Register +0 +1 +2 +3 00C100H CTRLR1 [R/W] 00000000 00000001 STATR1 [R/W] 00000000 00000000 00C104H ERRCNT1 [R] 00000000 00000000 BTR1 [R/W] 00100011 00000001 00C108H INTR1 [R] 00000000 00000000 TESTR1 [R/W] 00000000 X0000000 00C10CH BRPE1 [R/W] 00000000 00000000 Reserved 00C110H IF1CREQ1 [R/W] 00000000 00000001 IF1CMSK1 [R/W] 00000000 00000000 00C114H IF1MSK21 [R/W] 11111111 11111111 IF1MSK11 [R/W] 11111111 11111111 00C118H IF1ARB21 [R/W] 00000000 00000000 IF1ARB11 [R/W] 00000000 00000000 00C11CH IF1MCTR1 [R/W] 00000000 00000000 Reserved 00C120H IF1DTA11 [R/W] 00000000 00000000 IF1DTA21 [R/W] 00000000 00000000 00C124H IF1DTB11 [R/W] 00000000 00000000 IF1DTB21 [R/W] 00000000 00000000 00C128H, 00C12CH Block CAN 1 Control Register CAN 1 IF 1 Register Reserved 00C130H IF1DTA21 [R/W] 00000000 00000000 IF1DTA11 [R/W] 00000000 00000000 00C134H IF1DTB21 [R/W] 00000000 00000000 IF1DTB11 [R/W] 00000000 00000000 00C138H, 00C13CH CAN 1 IF 1 Register Reserved (Continued) Document Number: 002-04623 Rev. *B Page 84 of 144 CY91460S Series Address Register +0 +1 +2 +3 00C140H IF2CREQ1 [R/W] 00000000 00000001 IF2CMSK1 [R/W] 00000000 00000000 00C144H IF2MSK21 [R/W] 11111111 11111111 IF2MSK11 [R/W] 11111111 11111111 00C148H IF2ARB21 [R/W] 00000000 00000000 IF2ARB11 [R/W] 00000000 00000000 00C14CH IF2MCTR1 [R/W] 00000000 00000000 Reserved 00C150H IF2DTA11 [R/W] 00000000 00000000 IF2DTA21 [R/W] 00000000 00000000 00C154H IF2DTB11 [R/W] 00000000 00000000 IF2DTB21 [R/W] 00000000 00000000 00C158H, 00C15CH IF2DTA21 [R/W] 00000000 00000000 IF2DTA11 [R/W] 00000000 00000000 00C164H IF2DTB21 [R/W] 00000000 00000000 IF2DTB11 [R/W] 00000000 00000000 00C168H to 00C17CH Reserved TREQR21 [R] 00000000 00000000 00C184H to 00C18CH 00C190H NEWDT21 [R] 00000000 00000000 NEWDT11 [R] 00000000 00000000 CAN 1 Status Flags Reserved INTPND21 [R] 00000000 00000000 00C1A4H to 00C1ACH 00C1B0H TREQR11 [R] 00000000 00000000 Reserved 00C194H to 00C19CH 00C1A0H CAN 1 IF 2 Register Reserved 00C160H 00C180H Block INTPND11 [R] 00000000 00000000 Reserved MSGVAL21 [R] 00000000 00000000 00C1B4H to 00C1FCH MSGVAL11 [R] 00000000 00000000 CAN 1 Status Flags Reserved (Continued) Document Number: 002-04623 Rev. *B Page 85 of 144 CY91460S Series Address Register +0 +1 +2 00C200H to 00EFFCH Reserved 00F000H BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 00F004H BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000 00F008H BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F00CH BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F010H BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000 00F014H to 00F01CH Reserved 00F020H BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 00F024H BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 00F028H BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 00F02CH BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 00F030H to 00F07CH Reserved 00F080H BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F084H BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F088H BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F08CH BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F090H BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F094H BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F098H BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX +3 Block EDSU / MPU EDSU / MPU (Continued) Document Number: 002-04623 Rev. *B Page 86 of 144 CY91460S Series (Continued) Address Register +0 +1 +2 +3 Block 00F09CH BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A0H BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A4H BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A8H BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0ACH BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B0H BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B4H BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B8H BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0BCH BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C0H to 01FFFCH Reserved 020000H to 02FFFCH CY91F467SA D-RAM size is 32 Kbytes : 028000H to 02FFFCH (data access is 0 wait cycles) D-RAM area 030000H to 037FFCH CY91F467SA ID-RAM size is 32 Kbytes : 030000H to 037FFCH (instruction access is 0 wait cycles, data access is 1 wait cycle) ID-RAM area 038000H to 03FFFCH Reserved EDSU / MPU *1 : Use a read access ( byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt acceptance of the CPU) to a preceding write access to the resources on R-bus (e.g. to an interrupt flag) on following address (0x0000-0x01FF, 0x0280-0x037F, 0x0400-0x063F and 0x0C00-0x0FFF). *2 : Use a read access ( byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt acceptance of the CPU) to a preceding write access to the CANS on D-bus (e.g. to an interrupt flag) on following address (0x0000-0xFFFF). *3 : depends on the number of available CAN channels *4 : ACR0 [11 : 10] depends on Mode vector fetch information on bus width *5 : TCR [3 : 0] INIT value = 0000, keeps value after RST *6 : Datecode of APIX® controller version Document Number: 002-04623 Rev. *B Page 87 of 144 CY91460S Series 13.2 Flash memory and external bus area 32bit write mode 16bit write mode Address dat[31:0] dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 +5 +6 +7 Block 040000H to 05FFF8H SA8 (64kB) SA9 (64kB) ROMS0 060000H to 07FFF8H SA10 (64kB) SA11 (64kB) ROMS1 080000H to 09FFF8H SA12 (64kB) SA13 (64kB) ROMS2 0A0000H to 0BFFF8H SA14 (64kB) SA15 (64kB) ROMS3 0C0000H to 0DFFF8H SA16 (64kB) SA17 (64kB) ROMS4 0E0000H to 0FFFF0H SA18 (64kB) SA19 (64kB) 0FFFF8H FMV [R] 06 00 00 00H FRV [R] 00 00 BF F8H 100000H to 11FFF8H SA20 (64kB) SA21 (64kB) 120000H to 13FFF8H SA22 (64kB) SA23 (64kB) 140000H to 143FF8H SA0 (8kB) SA1 (8kB) 144000H to 17FF8H SA2 (8kB) SA3 (8kB) 148000H to 14BFF8H SA4 (8kB) SA5 (8kB) 14C000H to 14FFF8H SA6 (8kB) SA7 (8kB) ROMS5 ROMS6 150000H to 17FFF8H ROMS7 Reserved (Continued) Document Number: 002-04623 Rev. *B Page 88 of 144 CY91460S Series (Continued) 32bit write mode 16bit write mode Address dat[31:0] dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 +5 +6 +7 Block 180000H to 1BFFF8H ROMS8 1C0000H to 1FFFF8H ROMS9 200000H to 27FFF8H ROMS10 280000H to 2FFFF8H ROMS11 300000H to 37FFF8H External Bus Area ROMS12 380000H to 3FFFF8H ROMS13 400000H to 47FFF8H ROMS14 480000H to 4FFFF8H ROMS15 Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read. Document Number: 002-04623 Rev. *B Page 89 of 144 CY91460S Series 14. Interrupt Vector Table Interrupt number Interrupt Interrupt level*1 Interrupt vector*2 DMA Decimal Hexadecimal Setting Register Register address Offset Default Vector address RN*5 Stop*6 Reset 0 00 — — 3FCH 000FFFFCH — — Mode vector 1 01 — — 3F8H 000FFFF8H — — System reserved 2 02 — — 3F4H 000FFFF4H — — System reserved 3 03 — — 3F0H 000FFFF0H — — System reserved 4 04 — — 3ECH 000FFFECH — — CPU supervisor mode (INT #5 instruction) *7 5 05 — — 3E8H 000FFFE8H — — Memory Protection exception *7 6 06 — — 3E4H 000FFFE4H — — System reserved 7 07 — — 3E0H 000FFFE0H — — System reserved 8 08 — — 3DCH 000FFFDCH — — System reserved 9 09 — — 3D8H 000FFFD8H — — System reserved 10 0A — — 3D4H 000FFFD4H — — System reserved 11 0B — — 3D0H 000FFFD0H — — System reserved 12 0C — — 3CCH 000FFFCCH — — System reserved 13 0D — — 3C8H 000FFFC8H — — Undefined instruction exception 14 0E — — 3C4H 000FFFC4H — — NMI request 15 0F 3C0H 000FFFC0H — — External Interrupt 0 16 10 3BCH 000FFFBCH 0, 16 — External Interrupt 1 17 11 3B8H 000FFFB8H 1, 17 — 3B4H 000FFFB4H 2, 18 — 3B0H 000FFFB0H 3, 19 — 3ACH 000FFFACH 20 — 3A8H 000FFFA8H 21 — 3A4H 000FFFA4H 22 — 3A0H 000FFFA0H 23 — 39CH 000FFF9CH — — 398H 000FFF98H — — 394H 000FFF94H — — 390H 000FFF90H — — 38CH 000FFF8CH — — 388H 000FFF88H — — External Interrupt 2 18 12 External Interrupt 3 19 13 External Interrupt 4 20 14 External Interrupt 5 21 15 External Interrupt 6 22 16 External Interrupt 7 23 17 External Interrupt 8 24 18 External Interrupt 9 25 19 External Interrupt 10 26 1A External Interrupt 11 27 1B External Interrupt 12 28 1C External Interrupt 13 29 1D FH fixed ICR00 440H ICR01 441H ICR02 442H ICR03 443H ICR04 444H ICR05 445H ICR06 446H (Continued) Document Number: 002-04623 Rev. *B Page 90 of 144 CY91460S Series Interrupt number Interrupt Decimal Hexadecimal External Interrupt 14 30 1E External Interrupt 15 31 1F Reload Timer 0 32 20 Reload Timer 1 33 21 Reload Timer 2 34 22 Reload Timer 3 35 23 Reload Timer 4 36 24 Reload Timer 5 37 25 Reload Timer 6 38 26 Reload Timer 7 39 27 Free Run Timer 0 40 28 Free Run Timer 1 41 29 Free Run Timer 2 42 2A Free Run Timer 3 43 2B Free Run Timer 4 44 2C Free Run Timer 5 45 2D Free Run Timer 6 46 2E Free Run Timer 7 47 2F CAN 0 48 30 CAN 1 49 31 System reserved 50 32 System reserved 51 33 System reserved 52 34 System reserved 53 35 System reserved 54 36 System reserved 55 37 System reserved 56 38 System reserved 57 39 LIN-USART 2 RX 58 3A LIN-USART 2 TX 59 3B LIN-USART 3 RX 60 3C LIN-USART 3 TX 61 3D Interrupt level*1 Setting Register Register address ICR07 447H ICR08 448H ICR09 449H ICR10 44AH ICR11 44BH ICR12 44CH ICR13 44DH ICR14 44EH ICR15 44FH ICR16 450H ICR17 451H ICR18 452H ICR19 453H ICR20 454H ICR21 455H ICR22 456H Interrupt vector*2 DMA Offset Default Vector address RN*5 Stop*6 384H 000FFF84H — — 380H 000FFF80H — — 37CH 000FFF7CH 4, 32 — 378H 000FFF78H 5, 33 — 374H 000FFF74H 34 — 370H 000FFF70H 35 — 36CH 000FFF6CH 36 — 368H 000FFF68H 37 — 364H 000FFF64H 38 — 360H 000FFF60H 39 — 35CH 000FFF5CH 40 — 358H 000FFF58H 41 — 354H 000FFF54H 42 — 350H 000FFF50H 43 — 34CH 000FFF4CH 44 — 348H 000FFF48H 45 — 344H 000FFF44H 46 — 340H 000FFF40H 47 — 33CH 000FFF3CH — — 338H 000FFF38H — — 334H 000FFF34H — — 330H 000FFF30H — — 32CH 000FFF2CH — — 328H 000FFF28H — — 324H 000FFF24H 6, 48 — 320H 000FFF20H 7, 49 — 31CH 000FFF1CH 8, 50 — 318H 000FFF18H 9, 51 — 314H 000FFF14H 52 — 310H 000FFF10H 53 — 30CH 000FFF0CH 54 — 308H 000FFF08H 55 — (Continued) Document Number: 002-04623 Rev. *B Page 91 of 144 CY91460S Series Interrupt number Interrupt System reserved Delayed Interrupt Decimal Hexadecimal 62 3E 63 3F 4 System reserved * 64 40 System reserved *4 65 41 LIN-USART (FIFO) 4 RX 66 42 LIN-USART (FIFO) 4 TX 67 43 LIN-USART (FIFO) 5 RX 68 44 LIN-USART (FIFO) 5 TX 69 45 LIN-USART (FIFO) 6 RX 70 46 LIN-USART (FIFO) 6 TX 71 47 LIN-USART (FIFO) 7 RX 72 48 LIN-USART (FIFO) 7 TX 73 49 74 4A 75 4B APIX Event/ Eventlevel/ Eventbufferoverflow/ Fatal Error/Watchdog 76 4C System reserved 77 4D System reserved 78 4E System reserved 79 4F 80 50 System reserved 81 51 System reserved 82 52 System reserved 83 53 System reserved 84 54 System reserved 85 55 System reserved 86 56 System reserved 87 57 System reserved 88 58 System reserved 89 59 2C 0/ 2C 1 I I I2C 2 Interrupt level*1 Setting Register Register address ICR23 *3 457H (ICR24) (458H) ICR25 459H ICR26 45AH ICR27 45BH ICR28 45CH ICR29 45DH ICR30 45EH Interrupt vector*2 DMA Offset Default Vector address RN*5 Stop*6 304H 000FFF04H — — 300H 000FFF00H — — 2FCH 000FFEFCH — — 2F8H 000FFEF8H — — 2F4H 000FFEF4H 10, 56 10, 56 2F0H 000FFEF0H 11, 57 — 2ECH 000FFEECH 12, 58 12, 58 2E8H 000FFEE8H 13, 59 — 2E4H 000FFEE4H 60 60 2E0H 000FFEE0H 61 — 2DCH 000FFEDCH 62 62 2D8H 000FFED8H 63 — 2D4H 000FFED4H 28, 30 28, 30 2D0H 000FFED0H 29 29 2CCH 000FFECCH — — 2C8H 000FFEC8H 65 — ® ® Transaction APIX Buffer System reserved 90 5A System reserved 91 5B ICR31 45FH ICR32 460H ICR33 461H ICR34 462H ICR35 463H ICR36 464H ICR37 465H 2C4H 000FFEC4H 66 — 2C0H 000FFEC0H 67 — 2BCH 000FFEBCH 160-175 160-175 2B8H 000FFEB8H 69 — 2B4H 000FFEB4H 70 — 2B0H 000FFEB0H 71 — 2ACH 000FFEACH 72 — 2A8H 000FFEA8H 73 — 2A4H 000FFEA4H 74 — 2A0H 000FFEA0H 75 — 29CH 000FFE9CH 76 — 298H 000FFE98H 77 — 294H 000FFE94H 78 — 290H 000FFE90H 79 — (Continued) Document Number: 002-04623 Rev. *B Page 92 of 144 CY91460S Series Interrupt number Interrupt Decimal Hexadecimal Input Capture 0 92 5C Input Capture 1 93 5D Input Capture 2 94 5E Input Capture 3 95 5F Input Capture 4 96 60 Input Capture 5 97 61 Input Capture 6 98 62 Input Capture 7 99 63 Output Compare 0 100 64 Output Compare 1 101 65 Output Compare 2 102 66 Output Compare 3 103 67 System reserved 104 68 System reserved 105 69 System reserved 106 6A System reserved 107 6B Sound Generator 108 6C Phase Frequency Modulator 109 6D System reserved 110 6E System reserved 111 6F PPG0 112 70 PPG1 113 71 PPG2 114 72 PPG3 115 73 PPG4 116 74 PPG5 117 75 PPG6 118 76 PPG7 119 77 PPG8 120 78 PPG9 121 79 PPG10 122 7A PPG11 123 7B Interrupt level*1 Setting Register Register address ICR38 466H ICR39 467H ICR40 468H ICR41 469H ICR42 46AH ICR43 46BH ICR44 46CH ICR45 46DH ICR46 46EH ICR47 *3 46FH ICR48 470H ICR49 471H ICR50 472H ICR51 473H ICR52 474H ICR53 475H Interrupt vector*2 DMA Offset Default Vector address RN*5 Stop*6 28CH 000FFE8CH 80 — 288H 000FFE88H 81 — 284H 000FFE84H 82 — 280H 000FFE80H 83 — 27CH 000FFE7CH 84 — 278H 000FFE78H 85 — 274H 000FFE74H 86 — 270H 000FFE70H 87 — 26CH 000FFE6CH 88 — 268H 000FFE68H 89 — 264H 000FFE64H 90 — 260H 000FFE60H 91 — 25CH 000FFE5CH 92 — 258H 000FFE58H 93 — 254H 000FFE54H 94 — 250H 000FFE50H 95 — 24CH 000FFE4CH — — 248H 000FFE48H — — 244H 000FFE44H — — 240H 000FFE40H — — 23CH 000FFE3CH 15, 96 — 238H 000FFE38H 97 — 234H 000FFE34H 98 — 230H 000FFE30H 99 — 22CH 000FFE2CH 100 — 228H 000FFE28H 101 — 224H 000FFE24H 102 — 220H 000FFE20H 103 — 21CH 000FFE1CH 104 — 218H 000FFE18H 105 — 214H 000FFE14H 106 — 210H 000FFE10H 107 — (Continued) Document Number: 002-04623 Rev. *B Page 93 of 144 CY91460S Series (Continued) Interrupt number Interrupt Interrupt level*1 Decimal Hexadecimal PPG12 124 7C PPG13 125 7D PPG14 126 7E PPG15 127 7F Up/Down Counter 0 128 80 Up/Down Counter 1 129 81 Up/Down Counter 2 130 82 Up/Down Counter 3 131 83 Real Time Clock 132 84 Calibration Unit 133 85 Setting Register Register address ICR54 476H ICR55 477H ICR56 478H ICR57 479H ICR58 47AH ICR59 47BH ICR60 47CH ICR61 47DH ICR62 47EH ICR63 47FH A/D Converter 0 134 86 System reserved 135 87 Alarm Comparator 0 136 88 System reserved 137 89 Low Voltage Detection 138 8A SMC Comparator 0 to 5 139 8B Timebase Overflow 140 8C PLL Clock Gear 141 8D DMA Controller 142 8E Main/Sub OSC stability wait 143 8F Security vector 144 90 — Used by the INT instruction. 145 to 255 91 to FF — Interrupt vector*2 DMA Offset Default Vector address RN*5 Stop*6 20CH 000FFE0CH 108 — 208H 000FFE08H 109 — 204H 000FFE04H 110 — 200H 000FFE00H 111 — 1FCH 000FFDFCH — — 1F8H 000FFDF8H — — 1F4H 000FFDF4H — — 1F0H 000FFDF0H — — 1ECH 000FFDECH — — 1E8H 000FFDE8H — — 1E4H 000FFDE4H 14, 112 — 1E0H 000FFDE0H — — 1DCH 000FFDDCH — — 1D8H 000FFDD8H — — 1D4H 000FFDD4H — — 1D0H 000FFDD0H — — 1CCH 000FFDCCH — — 1C8H 000FFDC8H — — 1C4H 000FFDC4H — — 1C0H 000FFDC0H — — — 1BCH 000FFDBCH — — — 1B8H to 000H 000FFDB8H to 000FFC00H — — *1 : The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. *3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]) *4 : Used by REALOS *5 : DMA RN is the resource number used for DMA operation. No number means that this resource interrupt cannot be used to trigger a DMA transfer. *6 : DMA Stop shows the DMA Transfer Stop Request feature. *7 : Memory Protection Unit (MPU) support Document Number: 002-04623 Rev. *B Page 94 of 144 CY91460S Series 15. Recommended Settings 15.1 PLL and Clockgear settings Please note that for CY91F467SA the core base clock frequencies are valid in both 1.8 V and 1.9 V nominal operation modes of the Main regulator and Flash. Recommended PLL divider and clockgear settings PLL Input (CLK) [MHz] Frequency Parameter Clockgear Parameter PLL Output (X) [MHz] Core Base Clock [MHz] DIVM DIVN DIVG MULG 4 2 25 16 24 200 100 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 4 4 9 16 24 144 36 4 4 8 16 24 128 32 4 4 7 16 24 112 28 4 6 6 16 24 144 24 4 8 5 16 28 160 20 4 10 4 16 32 160 16 4 12 3 16 32 144 12 Document Number: 002-04623 Rev. *B Remarks MULG Page 95 of 144 CY91460S Series 15.2 Clock Modulator settings The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz. The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according to base clock frequency. Clock Modulator settings, frequency range and supported supply voltage Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 1 3 026F 88 79.5 98.5 1 3 026F 84 76.1 93.8 1 3 026F 80 72.6 89.1 1 5 02AE 80 68.7 95.8 2 3 046E 80 68.7 95.8 1 3 026F 76 69.1 84.5 1 5 02AE 76 65.3 90.8 1 7 02ED 76 62 98.1 2 3 046E 76 65.3 90.8 3 3 066D 76 62 98.1 1 3 026F 72 65.5 79.9 1 5 02AE 72 62 85.8 1 7 02ED 72 58.8 92.7 2 3 046E 72 62 85.8 3 3 066D 72 58.8 92.7 1 3 026F 68 62 75.3 1 5 02AE 68 58.7 80.9 1 7 02ED 68 55.7 87.3 1 9 032C 68 53 95 2 3 046E 68 58.7 80.9 2 5 04AC 68 53 95 3 3 066D 68 55.7 87.3 4 3 086C 68 53 95 1 3 026F 64 58.5 70.7 1 5 02AE 64 55.3 75.9 1 7 02ED 64 52.5 82 1 9 032C 64 49.9 89.1 1 11 036B 64 47.6 97.6 2 3 046E 64 55.3 75.9 Remarks (Continued) Document Number: 002-04623 Rev. *B Page 96 of 144 CY91460S Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 2 5 04AC 64 49.9 89.1 3 3 066D 64 52.5 82 4 3 086C 64 49.9 89.1 5 3 0A6B 64 47.6 97.6 1 3 026F 60 54.9 66.1 1 5 02AE 60 51.9 71 1 7 02ED 60 49.3 76.7 1 9 032C 60 46.9 83.3 1 11 036B 60 44.7 91.3 2 3 046E 60 51.9 71 2 5 04AC 60 46.9 83.3 3 3 066D 60 49.3 76.7 4 3 086C 60 46.9 83.3 5 3 0A6B 60 44.7 91.3 1 3 026F 56 51.4 61.6 1 5 02AE 56 48.6 66.1 1 7 02ED 56 46.1 71.4 1 9 032C 56 43.8 77.6 1 11 036B 56 41.8 84.9 1 13 03AA 56 39.9 93.8 2 3 046E 56 48.6 66.1 2 5 04AC 56 43.8 77.6 2 7 04EA 56 39.9 93.8 3 3 066D 56 46.1 71.4 3 5 06AA 56 39.9 93.8 4 3 086C 56 43.8 77.6 5 3 0A6B 56 41.8 84.9 6 3 0C6A 56 39.9 93.8 1 3 026F 52 47.8 57 1 5 02AE 52 45.2 61.2 1 7 02ED 52 42.9 66.1 1 9 032C 52 40.8 71.8 1 11 036B 52 38.8 78.6 1 13 03AA 52 37.1 86.8 1 15 03E9 52 35.5 96.9 Remarks (Continued) Document Number: 002-04623 Rev. *B Page 97 of 144 CY91460S Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 2 3 046E 52 45.2 61.2 2 5 04AC 52 40.8 71.8 2 7 04EA 52 37.1 86.8 3 3 066D 52 42.9 66.1 3 5 06AA 52 37.1 86.8 4 3 086C 52 40.8 71.8 5 3 0A6B 52 38.8 78.6 6 3 0C6A 52 37.1 86.8 7 3 0E69 52 35.5 96.9 1 3 026F 48 44.2 52.5 1 5 02AE 48 41.8 56.4 1 7 02ED 48 39.6 60.9 1 9 032C 48 37.7 66.1 1 11 036B 48 35.9 72.3 1 13 03AA 48 34.3 79.9 1 15 03E9 48 32.8 89.1 2 3 046E 48 41.8 56.4 2 5 04AC 48 37.7 66.1 2 7 04EA 48 34.3 79.9 3 3 066D 48 39.6 60.9 3 5 06AA 48 34.3 79.9 4 3 086C 48 37.7 66.1 5 3 0A6B 48 35.9 72.3 6 3 0C6A 48 34.3 79.9 7 3 0E69 48 32.8 89.1 1 3 026F 44 40.6 48.1 1 5 02AE 44 38.4 51.6 1 7 02ED 44 36.4 55.7 1 9 032C 44 34.6 60.4 1 11 036B 44 33 66.1 1 13 03AA 44 31.5 73 1 15 03E9 44 30.1 81.4 2 3 046E 44 38.4 51.6 2 5 04AC 44 34.6 60.4 2 7 04EA 44 31.5 73 Remarks (Continued) Document Number: 002-04623 Rev. *B Page 98 of 144 CY91460S Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 2 9 0528 44 28.9 92.1 3 3 066D 44 36.4 55.7 3 5 06AA 44 31.5 73 4 3 086C 44 34.6 60.4 4 5 08A8 44 28.9 92.1 5 3 0A6B 44 33 66.1 6 3 0C6A 44 31.5 73 7 3 0E69 44 30.1 81.4 8 3 1068 44 28.9 92.1 1 3 026F 40 37 43.6 1 5 02AE 40 34.9 46.8 1 7 02ED 40 33.1 50.5 1 9 032C 40 31.5 54.8 1 11 036B 40 30 59.9 1 13 03AA 40 28.7 66.1 1 15 03E9 40 27.4 73.7 2 3 046E 40 34.9 46.8 2 5 04AC 40 31.5 54.8 2 7 04EA 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066D 40 33.1 50.5 3 5 06AA 40 28.7 66.1 3 7 06E7 40 25.3 95.8 4 3 086C 40 31.5 54.8 4 5 08A8 40 26.3 83.3 5 3 0A6B 40 30 59.9 6 3 0C6A 40 28.7 66.1 7 3 0E69 40 27.4 73.7 8 3 1068 40 26.3 83.3 9 3 1267 40 25.3 95.8 1 3 026F 36 33.3 39.2 1 5 02AE 36 31.5 42 1 7 02ED 36 29.9 45.3 1 9 032C 36 28.4 49.2 1 11 036B 36 27.1 53.8 Remarks (Continued) Document Number: 002-04623 Rev. *B Page 99 of 144 CY91460S Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 1 13 03AA 36 25.8 59.3 1 15 03E9 36 24.7 66.1 2 3 046E 36 31.5 42 2 5 04AC 36 28.4 49.2 2 7 04EA 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066D 36 29.9 45.3 3 5 06AA 36 25.8 59.3 3 7 06E7 36 22.8 85.8 4 3 086C 36 28.4 49.2 4 5 08A8 36 23.7 74.7 5 3 0A6B 36 27.1 53.8 6 3 0C6A 36 25.8 59.3 7 3 0E69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 1 3 026F 32 29.7 34.7 1 5 02AE 32 28 37.3 1 7 02ED 32 26.6 40.2 1 9 032C 32 25.3 43.6 1 11 036B 32 24.1 47.7 1 13 03AA 32 23 52.5 1 15 03E9 32 22 58.6 2 3 046E 32 28 37.3 2 5 04AC 32 25.3 43.6 2 7 04EA 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066D 32 26.6 40.2 3 5 06AA 32 23 52.5 3 7 06E7 32 20.3 75.9 4 3 086C 32 25.3 43.6 4 5 08A8 32 21.1 66.1 5 3 0A6B 32 24.1 47.7 5 5 0AA6 32 19.5 89.1 Remarks (Continued) Document Number: 002-04623 Rev. *B Page 100 of 144 CY91460S Series (Continued) Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 6 3 0C6A 32 23 52.5 7 3 0E69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 Document Number: 002-04623 Rev. *B Remarks Page 101 of 144 CY91460S Series 16. Electrical Characteristics 16.1 Absolute maximum ratings Parameter Symbol Power supply slew rate Power supply voltage 1* 1 Power supply voltage 2* 1 Rating Unit Min Max — — 50 V/ms VDD5R - 0.3 + 6.0 V Remarks VDD5 - 0.3 + 6.0 V Power supply voltage 3*1 VDD35 - 0.3 + 6.0 V 1 VDDA - 0.3 + 2.5 V VDD5 - 0.3 VDD5 + 0.3 V At least one pin of the Ports 28 to 29 (ANn) is used as digital input or output VSS5 - 0.3 VDD5 + 0.3 V All pins of the Ports 28 to 29 (ANn) follow the condition of VIA Power supply voltage 4* AVCC5 Relationship of the supply voltages Analog power supply voltage*1 AVCC5 - 0.3 + 6.0 V *2 Analog reference power supply voltage*1 AVRH5 - 0.3 + 6.0 V *2 Input voltage 1*1 VI1 Vss5 - 0.3 VDD5 + 0.3 V Input voltage 2*1 VI2 Vss5 - 0.3 VDD35 + 0.3 V VIA AVss - 0.3 AVcc5 + 0.3 V VO1 Vss5 - 0.3 VDD5 + 0.3 V VO2 Vss5 - 0.3 VDD35 + 0.3 V ICLAMP - 4.0 + 4.0 mA *3 Σ |ICLAMP| — 20 mA *3 IOL — 10 mA IOLAV Analog pin input voltage* 1 1 Output voltage 1* 1 Output voltage 2* Maximum clamp current Total maximum clamp current 4 “L” level maximum output current* “L” level average output current* 5 “L” level total maximum output current “L” level total average output current* 6 4 “H” level maximum output current* 5 “H” level average output current* “H” level total maximum output current “H” level total average output current*6 — 8 mA ΣIOL ΣIOLAV — 100 mA — 50 mA IOH — - 10 mA IOHAV — -4 mA — - 100 mA — - 25 mA ΣIOH ΣIOHAV External bus External bus (Continued) Document Number: 002-04623 Rev. *B Page 102 of 144 CY91460S Series (Continued) Parameter Rating Symbol Min Unit Max Power consumption PD — 1000 mW Operating temperature TA - 40 + 105 °C Tstg - 55 + 150 °C Storage temperature Remarks *1 : The parameter is based on VSS5 = AVSS5 = 0.0 V. *2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V. *3 : • Use within recommended operating conditions. • Use with DC voltage (current). • +B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. • The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time, either instantaneously or for an extended period, when the +B signal is input. • Note that when the microcontroller drive current is low, such as in the low power consumption modes, the +B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting other devices. • Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through the +B input pin; therefore, the microcontroller may partially operate. • Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. • Do not leave +B input pins open. • Example of recommended circuit : Input/output equivalent circuit Protective diode VCC Limiting resistor P-ch +B input (0 V to 16 V) N-ch R *4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *6 : Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04623 Rev. *B Page 103 of 144 CY91460S Series 16.2 Recommended operating conditions (VSS5 = AVSS5 = 0.0 V) Parameter Symbol Unit Typ Max 3.0 — 5.5 VDD5R 3.0 — 5.5 V Internal regulator VDD35 3.0 — 5.5 V External bus V VDDA 1.7 — 1.85 V APIX® Using APIX: Internal core supply voltage (default: 1.8 V nominal) must be changed to 1.9 V nominal. Can be done by register setting: • Register: REGSEL • Address: 0x04CE • Bit 4 = 1 and Bit 5 = 1 (sets Main Regulator 1.9 V nominal) VPPA — — 50 mV VDDA, VSSA peak-peak supply noise AVCC5 3.0 — 5.5 V A/D converter Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. Use a capacitor with a capacitance greater than Cs as the smoothing capacitor on the supply pin. Smoothing capacitor CS — 4.7 — μF Power supply slew rate — — — 50 V/ms Operating temperature TA - 40 — + 105 °C Main Oscillation stabilization time 10 — — ms Lock-up time PLL (4 MHz ->16 ...100MHz) — — 0.6 ms Vsurge 2 — — kV fRC100kHz fRC2MHz 50 1 100 2 200 4 ESD Protection (Human body model) RC Oscillator WARNING: Remarks Min VDD5 Power supply voltage Value Rdischarge = 1.5kΩ Cdischarge = 100pF kHz MHz VDDCORE ≥ 1.65V The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04623 Rev. *B Page 104 of 144 CY91460S Series VCC18C VSS5 AVSS5 CS Document Number: 002-04623 Rev. *B Page 105 of 144 CY91460S Series 16.3 DC characteristics Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or VDD5 for other pins. (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max 0.8 × VDD — VDD + 0.3 V CMOS hysteresis input 0.7 × VDD — VDD + 0.3 V 4.5 V ≤ VDD ≤ 5.5 V 0.74 × VDD — VDD + 0.3 — Port inputs if CMOS Hysteresis 0.8/0.2 input is selected — Port inputs if CMOS Hysteresis 0.7/0.3 input is selected — AUTOMOTIVE Hysteresis input is selected 0.8 × VDD — VDD + 0.3 V — Port inputs if TTL input is selected 2.0 — VDD + 0.3 V VIH Input “H” voltage Condition 3V ≤ VDD < 4.5 V VIHR INITX — 0.8 × VDD — VDD + 0.3 V INITX input pin (CMOS Hysteresis) VIHM MD2 to MD0 — VDD - 0.3 — VDD + 0.3 V MDx input pins VIHX0S X0, X0A — 2.5 — VDD + 0.3 V External clock in “Oscillation mode” VIHX0F X0 — 0.8 × VDD — VDD + 0.3 V External clock in “Fast Clock Input mode” — Port inputs if CMOS Hysteresis 0.8/0.2 input is selected VSS5 - 0.3 — 0.2 × VDD V — Port inputs if CMOS Hysteresis 0.7/0.3 input is selected VSS5 - 0.3 — 0.3 × VDD V VSS5 - 0.3 — 0.5 × VDD V 4.5 V ≤ VDD ≤ 5.5 V — Port inputs if AUTOMOTIVE Hysteresis input is selected VSS5 - 0.3 — 0.46 × VDD V 3V — Port inputs if TTL input is selected VSS5 - 0.3 — 0.8 V VIL Input “L” voltage ≤ VDD < 4.5 V VILR INITX — VSS5 - 0.3 — 0.2 × VDD V INITX input pin (CMOS Hysteresis) VILM MD2 to MD0 — VSS5 - 0.3 — VSS5 + 0.3 V MDx input pins VILXDS X0, X0A — VSS5 - 0.3 — 0.5 V External clock in “Oscillation mode” (Continued) Document Number: 002-04623 Rev. *B Page 106 of 144 CY91460S Series (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Parameter Input “L” voltage Output “H” voltage Symbol Pin name Condition VILXDF X0 — Value Unit Remarks Min Typ Max VSS5 - 0.3 — 0.2 × VDD V External clock in “Fast Clock Input mode” VOH2 4.5V ≤ VDD ≤ 5.5V, Normal IOH = - 2mA outputs 3.0V ≤ V < 4.5V, DD IOH = - 1.6mA VDD - 0.5 — — V Driving strength set to 2 mA VOH5 4.5V ≤ VDD ≤ 5.5V, Normal IOH = - 5mA outputs 3.0V ≤ V < 4.5V, DD IOH = - 3mA VDD - 0.5 — — V Driving strength set to 5 mA VOH3 3.0V ≤ VDD ≤ 5.5V, I2C outputs IOH = - 3mA VDD - 0.5 — — V VDD - 0.5 — — V Driving strength set to 30mA VOL2 4.5V ≤ VDD ≤ 5.5V, Normal IOL = + 2mA outputs 3.0V ≤ V < 4.5V, DD IOL = + 1.6mA — — 0.4 V Driving strength set to 2 mA VOL5 4.5V ≤ VDD ≤ 5.5V, Normal IOL = + 5mA outputs 3.0V ≤ V < 4.5V, DD IOL = + 3mA — — 0.4 V Driving strength set to 5 mA VOL3 3.0V ≤ VDD ≤ 5.5V, I2C outputs IOL = + 3mA — — 0.4 V — — 0.5 V 4.5V ≤ VDD ≤ 5.5V, TA = -40°C, IOH = -40mA VOH30 High current 4.5V ≤ VDD ≤ 5.5V, outputs IOH = -30mA 3.0V ≤ VDD < 4.5V, IOH = -20mA Output “L” voltage 4.5V ≤ VDD ≤ 5.5V, TA = -40°C, IOL = +40mA VOL30 High current 4.5V ≤ VDD ≤ 5.5V, IOL outputs = +30mA Driving strength set to 30mA 3.0V ≤ VDD < 4.5V, IOL = +20mA (Continued) Document Number: 002-04623 Rev. *B Page 107 of 144 CY91460S Series (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Parameter Input leakage current Symbol IIL Pin name Pnn_m *1 Analog input leakage current IAIN Sum input leakage Σ IL Pnn_m ALARM Pull-up resistance RUP Pnn_m*1, INITX Pull-down resistance RDOWN Pnn_m*1 RTERM SDINM SDINP SDOUTM SDOUTMP APIX® terminal resistance ADIN Condition Value Min Typ Max 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD TA = 25°C -1 — +1 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD TA = 105°C -3 — +3 3.0V ≤ VDD ≤ 5.5V AVSS5 ≤ VI ≤ AVCC5 TA = 25°C -1 — +1 3.0V ≤ VDD ≤ 5.5V AVSS5 ≤ VI ≤ AVCC5 TA = 105°C VDD5 ≥ VIN ≥ VSS5 AVCC5, AVRH5 ≥ VIN ≥ AVSS5 Σ (1 to n) [max (|ILHi|, |ILLi|)] (n = number of IO = 133 GPIO + 1 ALARM) Unit Remarks μA μA -3 — +3 — 13 130 3.0V ≤ VDD ≤ 3.6V 40 100 160 4.5V ≤ VDD ≤ 5.5V 25 50 100 3.0V ≤ VDD ≤ 3.6V 40 100 160 4.5V ≤ VDD ≤ 5.5V 25 50 100 — 35 — 65 μA kΩ kΩ Ω (Continued) Document Number: 002-04623 Rev. *B Page 108 of 144 CY91460S Series (Continued) Parameter (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name Condition Value Min Typ Max Unit Remarks (Conditions at CY91F467SA) ICC VDD5R — — 125 155 mA CLKB: 100 MHz CLKP: 50 MHz CLKT: 50 MHz CLKCAN: 40 MHz Code fetch from Flash VDDA Power supply current ICCH APIX® — 12 60 TA = + 25°C — 30 150 μA TA = + 105°C — 400 2000 μA At stop mode *2 TA = + 25°C — 100 500 μA TA = + 105°C — 500 2400 μA TA = + 25°C — 50 250 μA TA = + 105°C — 450 2200 μA RTC : 100 kHz mode *2 RTC : 4 MHz mode *2 VDDA — — 10 50 μA APIX® powerdown ILVE VDD5 — — 70 150 μA External low voltage detection ILVI VDD5R — — 50 100 μA Internal low voltage detection — — 250 500 μA Main clock (4 MHz) — — 20 40 μA Sub clock (32 kHz) All except VDD5, VDD5R, VSS5, AVCC5, f = 1 MHz AVSS, VDDA, VSSA, — 5 15 pF IOSC Input capacitance VDD5R — CIN VDD5 *1: Pnn_m includes all pins unless the pins, which include analog inputs. *2: Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled. Document Number: 002-04623 Rev. *B Page 109 of 144 CY91460S Series 16.4 A/D converter characteristics Parameter (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name Resolution — Total error Value Unit Min Typ Max — — — 10 bit — — -3 — +3 LSB Nonlinearity error — — - 2.5 — + 2.5 LSB Differential nonlinearity error — — - 1.9 — + 1.9 LSB AVRL + 0.5 LSB AVRL + 2.5 LSB V Zero reading voltage VOT ANn AVRL− 1.5 LSB Full scale reading voltage VFST ANn AVRH− 3.5 LSB AVRH− 1.5 LSB AVRH + 0.5 LSB V Compare time Tcomp — 1.0 — 16,500 μs 2.0 — — μs 0.4 — — μs 1.0 — — μs 1.4 — — μs Sampling time Conversion time Tsamp — Tconv — Input capacitance CIN ANn Input resistance RIN ANn Analog input leakage current IAIN ANn Analog input voltage range VAIN — Offset between input channels Remarks 4.5 V ≤ AVCC5 ≤ 5.5 V 3.0 V ≤ AVCC5 < 4.5 V 4.5 V ≤ AVCC5 ≤ 5.5 V, REXT < 2 kΩ 3.0 V ≤ AVCC5 < 4.5 V, REXT < 1 kΩ 4.5 V ≤ AVCC5 ≤ 5.5 V 3.0 V ≤ AVCC5 < 4.5 V 3.0 — — μs — — 11 pF — — 2.6 kΩ 4.5 V ≤ AVCC5 ≤ 5.5 V — — 12.1 kΩ 3.0 V ≤ AVCC5 < 4.5 V -1 — +1 μA TA = + 25°C -3 — +3 ANn AVRL — AVRH μA TA = + 105°C V ANn — — 4 LSB (Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller Document Number: 002-04623 Rev. *B Page 110 of 144 CY91460S Series (Continued) Parameter Reference voltage range Power supply current per ADC macro *3 Reference voltage current per ADC macro *3 Symbol Pin name AVRH Value Unit Remarks Min Typ Max AVRH5 0.75 × AVCC5 — AVCC5 V AVRL AVSS5 AVSS5 — AVCC5 × 0.25 V IA AVCC5 — 2.5 5 mA A/D Converter active IAH AVCC5 — — 5 μA A/D Converter not operated *1 IR AVRH5 — 0.7 1 mA A/D Converter active IRH AVRH5 — — 5 μA A/D Converter not operated *2 *1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the current values have to be multiplied by the number of macros. Sampling Time Calculation Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V ≤ AVCC5 < 4.5V Conversion Time Calculation Tconv = Tsamp + Tcomp Definition of A/D converter terms • Resolution Analog variation that is recognizable by the A/D converter. • Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B). • Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. • Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error. Document Number: 002-04623 Rev. *B Page 111 of 144 CY91460S Series Total error 3FFH 1.5 LSB’ 3FEH Actual conversion characteristics 3FDH Digital output {1 LSB’ (N - 1) + 0.5 LSB’} 004H VNT (measurement value) 003H Actual conversion characteristics Ideal characteristics 002H 001H 0.5 LSB' AVSS5 AVRH Analog input 1LSB' (ideal value) = AVRH - AVSS5 1024 Total error of digital output N = [V] VNT - {1 LSB' × (N - 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS5 + 0.5 LSB' [V] VFST' (ideal value) = AVRH - 1.5 LSB' [V] VNT : Voltage at which the digital output changes from (N + 1) H to NH (Continued) Document Number: 002-04623 Rev. *B Page 112 of 144 CY91460S Series (Continued) 3FFH Nonlinearity error Differential nonlinearity error Actual conversion characteristics Actual conversion characteristics (N+1)H {1 LSB (N - 1) + VOT} VFST (measurement value) Digital output 3FDH 004H VNT (measurement value) 003H 002H Digital output 3FEH Ideal characteristics NH (N-1)H VFST (measurement VNT value) (measurement value) Actual conversion characteristics Ideal characteristics (N-2)H 001H Actual conversion characteristics VTO (measurement value) AVSS5 AVSS5 AVRH AVRH Analog input Nonlinearity error of digital output N = Analog input VNT - {1LSB × (N - 1) + VOT} 1LSB Differential nonlinearity error of digital output N = 1LSB = VFST - VOT 1022 V (N + 1) T - VNT 1LSB [LSB] - 1 [LSB] [V] N : A/D converter digital output value VOT : Voltage at which the digital output changes from 000H to 001H. VFST : Voltage at which the digital output changes from 3FEH to 3FFH. Document Number: 002-04623 Rev. *B Page 113 of 144 CY91460S Series 16.5 Alarm comparator characteristics Parameter Symbol Pin name IA5ALMS Min — IA5ALMF Power supply current Value AVCC5 IA5ALMH Typ 25 Max 40 Unit Remarks μA Alarm comparator enabled in fast mode (one channel) — 7 10 μA Alarm comparator enabled in fast mode (one channel) — — 5 μA Alarm comparator disabled -1 — +1 -3 — +3 VALIN 0 — AVCC5 V Alarm upper limit voltage VIAH AVCC5 × 0.78 - 3% AVCC5 × 0.78 AVCC5 × 0.78 + 3% V Alarm lower limit voltage VIAL AVCC5 × 0.36 - 5% AVCC5 × 0.36 AVCC5 × 0.36 + 5% V Alarm hysteresis voltage VIAHYS 50 — 250 mV RIN 5 — — MΩ tCOMPF — 0.1 0.2 μs ACSR.MD=1 tCOMPS — 1 2 μs ACSR.MD=0 ALARM pin input current IALIN ALARM pin input voltage range Alarm input resistance Comparison time ALARM Document Number: 002-04623 Rev. *B μA TA = + 25°C TA = + 105°C Page 114 of 144 CY91460S Series 16.6 FLASH memory program/erase characteristics 16.6.1 CY91F467SA (TA = 25oC, Vcc = 5.0V) Value Parameter Unit Remarks 2.0 s Erasure programming time not included n*0.5 n*2.0 s n is the number of Flash sector of the device 6 100 μs System overhead time not included Min Typ Max Sector erase time - 0.5 Chip erase time - Word (16-bit width) programming time - Programme/Erase cycle 10 000 cycle Flash data retention time 20 year *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) Document Number: 002-04623 Rev. *B Page 115 of 144 CY91460S Series 16.7 AC characteristics 16.7.1 Clock timing Parameter (VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Clock frequency fC Pin name Value Unit Condition 16 MHz Opposite phase external supply or crystal 100 kHz Min Typ Max X0 X1 3.5 4 X0A X1A 32 32.768 Clock timing condition tC X0, X1, X0A, X1A 0.8 VCC 0.2 VCC PWH 16.7.2 Reset input ratings Parameter INITX input time (at power-on) INITX input time (other than the above) PWL (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name Condition tINTL INITX — Value Unit Min Max 8 — ms 20 — μs tINTL INITX Document Number: 002-04623 Rev. *B 0.2 VCC Page 116 of 144 CY91460S Series 16.7.3 LIN-USART Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = -40°C to +105°C - Cl = 50 pF (load capacity value of pins when testing) - VOL = 0.2 × VDD5, VOH = 0.8 × VDD5 - EPILR = 0, PILR = 1 (Automotive Level = worst case) (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Parameter Symbol Pin name Condition VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V Unit Min Max Min Max 4 tCLKP — 4 tCLKP — ns - 30 30 - 20 20 ns m× tCLKP - 30* — m× tCLKP - 20* — ns tCLKP + 55 — tCLKP + 45 — ns Serial clock cycle time tSCYCI SCKn SCK ↓ → SOT delay time tSLOVI SCKn SOTn SOT → SCK ↓ delay time tOVSHI SCKn SOTn Valid SIN → SCK ↑ setup time tIVSHI SCKn SINn SCK ↑ → valid SIN hold time tSHIXI SCKn SINn 0 — 0 — ns Serial clock “H” pulse width tSHSLE SCKn tCLKP + 10 — tCLKP + 10 — ns Serial clock “L” pulse width tSLSHE SCKn tCLKP + 10 — tCLKP + 10 — ns SCK ↓ → SOT delay time tSLOVE SCKn SOTn — 2 tCLKP + 55 — 2 tCLKP + 45 ns Valid SIN → SCK ↑ setup time tIVSHE SCKn SINn 10 — 10 — ns SCK ↑ → valid SIN hold time tSHIXE SCKn SINn tCLKP + 10 — tCLKP + 10 — ns SCK rising time tFE SCKn — 20 — 20 ns SCK falling time tRE SCKn — 20 — 20 ns Internal clock operation (master mode) External clock operation (slave mode) * : Parameter m depends on tSCYCI and can be calculated as : • if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2 • if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : • The above values are AC characteristics for CLK synchronous mode. • tCLKP is the cycle time of the peripheral clock. Document Number: 002-04623 Rev. *B Page 117 of 144 CY91460S Series Internal clock mode (master mode) tSCYCI SCKn for ESCR:SCES = 0 VOH VOL VOL VOH SCKn for ESCR:SCES = 1 VOH VOL tSLOVI tOVSHI VOH VOL SOTn tIVSHI tSHIXI VIH VIL SINn VIH VIL External clock mode (slave mode) tSLSHE SCKn for ESCR:SCES = 0 VOH SCKn for ESCR:SCES = 1 VOL tSHSLE VOH VOL VOL VOH VOH VOL VOH VOL tRE tFE tSLOVE SOTn VOH VOL tIVSHE SINn Document Number: 002-04623 Rev. *B VIH VIL tSHIXE VIH VIL Page 118 of 144 CY91460S Series 16.7.4 I2C AC Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40°C to + 105°C - Cl = 50 pF - VOL = 0.3 × VDD5, VOH = 0.7 × VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Parameter Symbol Pin name fSCL Value Unit Min Max SCLn 0 400 kHz tHD;STA SCLn, SDAn 0.6 — μs LOW period of the SCL clock tLOW SCLn 1.3 — μs HIGH period of the SCL clock tHIGH SCLn 0.6 — μs Setup time for a repeated START condition tSU;STA SCLn, SDAn 0.6 — μs Data hold time for I2C-bus devices tHD;DAT SCLn, SDAn 0 0.9 μs Data setup time tSU;DAT SCLn SDAn 100 — ns Rise time of both SDA and SCL signals tr SCLn, SDAn 20 + 0.1Cb 300 ns Fall time of both SDA and SCL signals tf SCLn, SDAn 20 + 0.1Cb 300 ns tSU;STO SCLn, SDAn 0.6 — μs tBUF SCLn, SDAn 1.3 — μs Capacitive load for each bus line Cb SCLn, SDAn — 400 pF Pulse width of spike suppressed by input filter tSP SCLn, SDAn 0 (1..1.5) × tCLKP ns SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated Setup time for STOP condition Bus free time between a STOP and START condition Remark *1 *1: The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock. Document Number: 002-04623 Rev. *B Page 119 of 144 Document Number: 002-04623 Rev. *B SCL SDA tHD;STA tf S tr tHD;DAT tLOW tHIGH tSU;DAT tSU;STA Sr tHD;STA tSP tr P tSU;ST0 tBUF S tf CY91460S Series Page 120 of 144 CY91460S Series 16.7.5 Free-run timer clock Parameter Input pulse width (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name Condition tTIWH tTIWL CKn — Value Min Max 4tCLKP — Unit ns Note : tCLKP is the cycle time of the peripheral clock. CKn VIH VIH tTIWH 16.7.6 Trigger input timing Parameter Input capture input trigger A/D converter trigger VIL VIL tTIWL (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name Condition tINP ICUn tATGX ATGX Value Unit Min Max — 5tCLKP — ns — 5tCLKP — ns Note : tCLKP is the cycle time of the peripheral clock. tATGX, tINP ICUn, ATGX Document Number: 002-04623 Rev. *B Page 121 of 144 CY91460S Series 16.7.7 External Bus AC Timings at VDD35 = 4.5 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 4.5 V to 5.5 V, Iload = 5 mA - VSS5 = 0 V - Ta = - 40°C to + 105°C - Cl = 50 pF - VOL = 0.2 × VDD35, VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) Basic Timing (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Parameter SYSCLK SYSCLK ↓ to CSXn delay time SYSCLK ↑ to CSXn delay time (Addr → CS delay) SYSCLK ↓ to ASX delay time SYSCLK ↓ to Address valid delay time Symbol tCLCH tCHCL Pin name SYSCLK tCLCSL tCLCSH SYSCLK CSXn tCHCSL tCLASL tCLASH tCLAV Value Unit Min Max 1/2 x tCLKT - 1 1/2 × tCLKT + 1 1/2 × tCLKT - 1 1/2 × tCLKT + 1 ns — 5 ns — 5 ns 3 7 ns ns SYSCLK ASX — 5 ns — 5 ns SYSCLK A23 to A0 — 7 ns Note : tCLKT is the cycle time of the external bus clock. Document Number: 002-04623 Rev. *B Page 122 of 144 CY91460S Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS Document Number: 002-04623 Rev. *B Page 123 of 144 CY91460S Series Synchronous/Asynchronous read access Parameter (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name TCHRL SYSCLK ↑ to RDX delay time SYSCLK RDX TCHRH Value Unit Min Max 2 5 ns 2 5 ns Data valid to RDX ↑ setup time TDSRH RDX D31 to D16 12 — ns RDX ↑ to Data valid hold time TRHDX RDX D31 to D16 0 — ns TCLWRL SYSCLK WRXn — 5 ns 2 — ns SYSCLK CSXn — 5 ns — 5 ns SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRH TCLCSL SYSCLK ↓ to CSXn delay time TCLCSH SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN Document Number: 002-04623 Rev. *B Page 124 of 144 CY91460S Series Synchronous write access - byte control type Parameter (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name TCLWL Value Unit Min Max — 5 ns TCLWH SYSCLK WEX 2 — ns Data valid to WEX ↓ setup time TDSWL WEX D31 to D16 -1 — ns WEX ↑ to Data valid hold time TWHDH WEX D31 to D16 tCLKT - 1 — ns SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRL SYSCLK WRXn — 5 ns TCLWRH 2 — ns SYSCLK CSXn — 5 ns — 5 ns SYSCLK ↓ to WEX delay time SYSCLK ↓ to CSXn delay time TCLCSL TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCLWH tCLWL WEX tDSWL tWHDH DATA OUT Document Number: 002-04623 Rev. *B Page 125 of 144 CY91460S Series Synchronous write access - no byte control type Parameter (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name TCLWRL Value Unit Min Max — 5 ns TCLWRH SYSCLK WRXn 2 — ns Data valid to WRXn ↓ setup time TDSWRL WRXn D31 to D16 -1 — ns WRXn ↑ to Data valid hold time TWRHDH WRXn D31 to D16 tCLKT - 1 — ns TCLCSL SYSCLK CSXn — 5 ns — 5 ns SYSCLK ↓ to WRXn delay time SYSCLK ↓ to CSXn delay time TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT Document Number: 002-04623 Rev. *B Page 126 of 144 CY91460S Series Asynchronous write access - byte control type (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Parameter Symbol Pin name WEX ↓ to WEX ↑ pulse width TWLWH Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Value Unit Min Max WEX tCLKT - 1 — ns TDSWL WEX D31 to D16 1/2 × tCLKT - 1 — ns TWHDH WEX D31 to D16 1/2 × tCLKT - 1 — ns TWRLWL WEX WRXn — 1/2 × tCLKT + 1 ns 1/2 × tCLKT - 1 — ns — 1/2 × tCLKT + 1 ns 1/2 × tCLKT - 1 — ns TWHWRH TCLWL WEX CSXn TWHCH CSXn tWHCH tCLWL WRXn (as byte enable) tWHWRH tWRLWL tWLWH WEX tDSWL tWHDH DATA OUT Document Number: 002-04623 Rev. *B Page 127 of 144 CY91460S Series Asynchronous write access - no byte control type Parameter (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name WRXn ↓ to WRXn ↑ pulse width TWRLWRH Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Value Unit Min Max WRXn tCLKT - 1 — ns TDSWRL WRXn D31 to D16 1/2 × tCLKT - 1 — ns TWRHDH WRXn D31 to D16 1/2 × tCLKT - 1 — ns TCLWRL WRXn CSXn — 1/2 × tCLKT + 1 ns 1/2 × tCLKT - 1 — ns TWRHCH CSXn TWRHCH TCLWRL TWRLWRH WRXn TDSWRL TWRHDH DATA OUT Document Number: 002-04623 Rev. *B Page 128 of 144 CY91460S Series RDY waitcycle insertion Parameter (VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name RDY setup time TRDYS RDY hold time TRDYH Value Unit Min Max SYSCLK RDY 8 — ns SYSCLK RDY 0 — ns SYSCLK tRDYS tRDYH RDY Document Number: 002-04623 Rev. *B Page 129 of 144 CY91460S Series 16.7.8 External Bus AC Timings at VDD35 = 3.0 to 4.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 3.0 V to 4.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40°C to + 105°C - Cl = 50 pF - VOL = 0.2 × VDD35, VOH = 0.8 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) Basic Timing (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Parameter SYSCLK SYSCLK ↓ to CSXn delay time SYSCLK ↑ to CSXn delay time (Addr → CS delay) SYSCLK ↓ to ASX delay time SYSCLK ↓ to Address valid delay time Document Number: 002-04623 Rev. *B Symbol Pin name Value Unit Min Max 1/2 × tCLKT 1/2 × tCLKT + 2 1/2 × tCLKT - 2 1/2 × tCLKT ns — 11 ns — 7 ns 2 6 ns — 6 ns TCLASH SYSCLK ASX — 7 ns TCLAV SYSCLK A23 to A0 — 13 ns TCLCH TCHCL SYSCLK TCLCSL TCLCSH SYSCLK CSXn TCHCSL TCLASL ns Page 130 of 144 CY91460S Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS Document Number: 002-04623 Rev. *B Page 131 of 144 CY91460S Series Synchronous/Asynchronous read access Parameter (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name TCHRL TCHRH SYSCLK RDX Data valid to RDX ↑ setup time TDSRH RDX ↑ to Data valid hold time SYSCLK ↑ to RDX delay time SYSCLK ↓ to WRXn (as byte enable) delay time Unit Max 1 4 ns 2 6 ns RDX D31 to D16 16 — ns TRHDX RDX D31 to D16 0 — ns TCLWRL SYSCLK WRXn — 6 ns 3 — ns SYSCLK CSXn — 11 ns — 7 ns TCLWRH TCLCSL SYSCLK ↓ to CSXn delay time Value Min TCLCSH SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN Document Number: 002-04623 Rev. *B Page 132 of 144 CY91460S Series Synchronous write access - byte control type Parameter (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name TCLWL Value Unit Min Max — 6 ns TCLWH SYSCLK WEX 3 — ns Data valid to WEX ↓ setup time TDSWL WEX D31 to D16 -7 — ns WEX ↑ to Data valid hold time TWHDH WEX D31 to D16 tCLKT - 3 — ns SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRL SYSCLK WRXn — 6 ns TCLWRH 3 — ns SYSCLK CSXn — 11 ns — 7 ns SYSCLK ↓ to WEX delay time SYSCLK ↓ to CSXn delay time TCLCSL TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn (as byte enable) tCLWH tCLWL WEX tDSWL tWHDH DATA OUT Document Number: 002-04623 Rev. *B Page 133 of 144 CY91460S Series Synchronous write access - no byte control type Parameter (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name TCLWRL Value Unit Min Max — 6 ns TCLWRH SYSCLK WRXn 3 — ns Data valid to WRXn ↓ setup time TDSWRL WRXn D31 to D16 -7 — ns WRXn ↑ to Data valid hold time TWRHDH WRXn D31 to D16 tCLKT - 3 — ns TCLCSL SYSCLK CSXn — 11 ns — 7 ns SYSCLK ↓ to WRXn delay time SYSCLK ↓ to CSXn delay time TCLCSH SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT Document Number: 002-04623 Rev. *B Page 134 of 144 CY91460S Series Asynchronous write access - byte control type Parameter (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name WEX ↓ to WEX ↑ pulse width TWLWH Data valid to WEX ↓ setup time WEX ↑ to Data valid hold time WEX to WRXn delay time WEX to CSXn delay time Value Unit Min Max WEX tCLKT — ns TDSWL WEX D31 to D16 1/2 × tCLKT - 7 — ns TWHDH WEX D31 to D16 1/2 × tCLKT - 3 — ns TWRLWL WEX WRXn — 1/2 × tCLKT + 1 ns 1/2 × tCLKT - 1 — ns — 1/2 × tCLKT - 1 ns 1/2 × tCLKT - 1 — ns TWHWRH TCLWL WEX CSXn TWHCH CSXn TCLWL TWHCH WRXn (as byte enable) TWHWRH TWRLWL TWLWH WEX TDSWL TWHDH DATA OUT Document Number: 002-04623 Rev. *B Page 135 of 144 CY91460S Series Asynchronous write access - no byte control type Parameter (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name WRXn ↓ to WRXn ↑ pulse width TWRLWRH Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Value Unit Min Max WRXn tCLKT — ns TDSWRL WRXn D31 to D16 1/2 × tCLKT - 7 — ns TWRHDH WRXn D31 to D16 1/2 × tCLKT - 3 — ns TCLWRL WRXn CSXn — 1/2 × tCLKT+1 ns 1/2 × tCLKT - 1 — ns TWRHCH CSXn TWRHCH TCLWRL TWRLWRH WRXn TDSWRL TWRHDH DATA OUT Document Number: 002-04623 Rev. *B Page 136 of 144 CY91460S Series RDY waitcycle insertion Parameter (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40°C to + 105°C) Symbol Pin name RDY setup time TRDYS RDY hold time TRDYH Value Unit Min Max SYSCLK RDY 12 — ns SYSCLK RDY 0 — ns SYSCLK tRDYS tRDYH RDY Document Number: 002-04623 Rev. *B Page 137 of 144 CY91460S Series 17. Ordering Information Part number CY91F467SAPMC-GS-UJE2 Document Number: 002-04623 Rev. *B Package 176-pin plastic LQFP (LQP176) Remarks Lead-free package Page 138 of 144 CY91460S Series 18. Package Dimension D D1 132 4 5 7 89 133 89 88 132 133 88 E1 E 5 7 4 3 6 176 45 1 176 45 44 3 0.20 C 1 44 2 5 7 e 0.10 C A-B D b 0.08 C A-B BOTTOM VIEW A-B D D 8 TOP VIEW 2 A A' 0.08 C SIDE VIEW SYMBOL NOM. L1 0.25 A1 10 L c b SECTION A-A' MAX. 1.70 0.05 0.15 b 0.17 c 0.09 0.22 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 0.27 0.20 D 24.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ SEA TING PLAN E DIMENSIONS MIN. A A1 9 θ A 0° 8° 002-15150 ** PACKAGE OUTLINE, 176 LEAD LQFP 24.0X24.0X1.7 MM LQP176 REV** Document Number: 002-04623 Rev. *B Page 139 of 144 CY91460S Series 19. Revision History Version Date Remark 0.10 2007-10-04 Initial draft 0.11 2007-10-10 corrected pindescription 0.12 2007-10-10 added scope 0.13 2007-11-07 updated pinning and featurelist 0.14 2007-11-19 updated the IO-map, Interrupt table and Flash access 0.15 2007-11-26 added APIX® register description, changed scope 0.16 2007-12-04 added trademark information, changed scope 0.17 2008-01-20 updated APIX® register description 0.18 2008-02-12 updated product lineup 0.19 2008-04-10 updated APIX® register description 0.20 2008-04-11 updated APIX® register description, Interruptvectortable 0.21 2008-07-31 added APIX® overview and DMA trigger settings 0.22 2008-08-01 updated APIX® PHY configuration 0.23 2008-08-27 updated APIX® controller description 0.24 2008-09-03 updated electrical characteristics and APIX® controller description 0.25 2009-02-02 updated APIX® RH description, operating conditions and AC characteristics, added clockmodulator limitation 0.26 2009-02-04 updated APIX® RH description and operating conditions 0.27 2009-02-10 added trademark information 0.28 2009-03-03 updated product lineup and electrical characteristics 0.29 2009-03-10 updated ADC electrical characteristics 0.30 2009-05-08 corrected default values for PFR00 to PFR10 and level for AC specification 1.00 2009-06-02 corrected AC specification 1.01 2009-06-05 updated DC characteristics 1.02 2009-06-17 updated ordering information Document Number: 002-04623 Rev. *B Page 140 of 144 CY91460S Series 20. Major Changes Spansion Publication Number: DS07-16617-3E Page 4, 5 Section Product Lineup 41 42 APIX® Controller 2. Automotive Remote Handler 2.1. Register Description 2.1.2. Channel Control and Status Change Results Corrected the part number; MB91V460A → MB91V460B Corrected the status in figure as follows. “PLLGOOD” → “reserved” Corrected the status for UPVALID. read only Read only status → Read only status Added the sentence as follows. “*Remark: Reading UPVALID returns the status and then clears the flag value to “0”.” 50 2.1.8. Eventbuffer Corrected the sentence as follows. “*Remark: It is recommended to read first EVBUF0 and” → “*Remark: It is recommended to read first EVBUF0 and after that EVBUF1.” 52 3. APIX® PHY Configuration Corrected the title. APIX1/4® PHY Configuration → APIX® PHY Configuration 79 I/O Map Address: 007208H Address: 007214H Corrected the Register as follows. “- - - - 0 - - - 000 - - - 00 00000000 - - 00 - - 000” → “ - - - 0 - - - 000 - - - 00 - 0000000 - - 00 - 111” 96 Recommended Settings 1. PLL and Clockgear settings Corrected the sentence as follows. “Please note that for MB91F467SA the core base clock frequencies are valid in the 1.8 V operation mode of the Main regulator and Flash.” → “Please note that for MB91F467SA the core base clock frequencies are valid in both 1.8 V and 1.9 V nominal operation modes of the Main regulator and Flash.” 97 2. Clock Modulator settings Deleted the sentence as follows. “The clock modulator is currently being evaluated and should not be used for other purpose than testing.” 104 Electrical Characteristics 1. Absolute maximum ratings Deleted the footnote *7. 2. Recommended operating conditions Corrected the symbol VDDA for Power supply voltage as follows. Maximum value: 1.0 → 1.85 Remarks: APIX® → APIX® Using APIX: Internal core supply voltage (default: 1.8 V nominal) must be changed to 1.9 V nominal. Can be done by register setting: Register: REGSEL Address: 0x04CE Bit 4 =1 and Bit 5 = 1 (sets Main Regulator 1.9V nominal) 105 NOTE: Please see “Document History” about later revised information. Document Number: 002-04623 Rev. *B Page 141 of 144 CY91460S Series Page Section Change Results Rev.*B 6, 138, 139 Marketing Part Numbers changed form an MB prefix to a CY prefix 2. Pin Assignments 17. Ordering information 18. Package Dimensions Package description modified to JEDEC description. FPT-176P-M07 → LQP176 Revised Marketing Part Numbers as follows: 138 17. Ordering information Before) MB91F467SAPMC-GSE2 After) CY91F467SAPMC-GS-UJE2 Document Number: 002-04623 Rev. *B Page 142 of 144 CY91460S Series Document History Document Title: CY91460S Series FR60 32-bit Microcontroller Document Number: 002-04623 Revision ECN Orig. of Change Submission Date ** — AKIH 07/22/2010 Migrated to Cypress and assigned document number 002-04623. No change to document contents or format. *A 5223810 AKIH 05/27/2016 Updated to Cypress format. *B 6074464 WAFA 02/19/2018 Revised the following items: Marketing Part Numbers changed from an MB prefix to a CY prefix. 2.Pin Assignments 17.Ordering Information 18.Package Dimension For details, please see 20. Major Changes. Document Number: 002-04623 Rev. *B Description of Change Page 143 of 144 CY91460S Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2009-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04623 Rev. *B Revised February 19, 2018 Page 144 of 144