The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
1. Go to www.cypress.com/pcn.
2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB91F469GA/F469GB
FR60 MB91460G Series,
32-bit Microcontroller Datasheet
MB91460G series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which
require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU,
which is compatible with the FR family of CPUs.
This series contains the LIN-USART and CAN controllers.
Features
FR60 CPU core
■
32-bit RISC, load/store architecture, five-stage pipeline
■
16-bit fixed-length instructions (basic instructions)
■
Instruction execution speed: 1 instruction per cycle
■
Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for
embedded applications
■
Function entry/exit instructions and register data multi-load
store instructions: Instructions supporting C language
■
Register interlock function: Facilitating assembly-language
coding
■
Built-in multiplier with instruction-level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
■
Interrupts (save PC/PS): 6 cycles (16 priority levels)
■
Harvard architecture enabling program access and data
access to be performed simultaneously
■
Instructions compatible with the FR family
Internal Peripheral Resources
■
General-purpose ports : Maximum 205 ports
■
I2C bus interface (supports 400 kbps): 4 channel
■
DMAC (DMA Controller)
■
Master/slave transmission and reception
■
Arbitration function, clock synchronization function
■
CAN controller (C-CAN): 6 channels
Activation source can be selected using software
■
Maximum transfer speed: 1 Mbps
Addressing mode specifies full 32-bit addresses
(increment/decrement/fixed)
■
128 transmission/reception message buffers
■
Sound generator: 1 channelTone frequency: PWM frequency
divide-by-two (reload value + 1)
■
Alarm comparator: 2 channelsMonitor external voltage
Generate an interrupt in case of voltage lower/higher than the
defined thresholds (reference voltage)
Multi-byte transfer enabled (by software)
■
16-bit PPG timer: 16 channels
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
■
16-bit PFM timer: 1 channel
■
16-bit reload timer: 8 channels
■
16-bit free-run timer: 8 channels (1 channel each for ICU and
OCU)
■
Input capture: 8 channels (operates in conjunction with the
free-run timer)
■
Output compare: 8 channels (operates in conjunction with the
free-run timer)
■
Up/Down counter: 4 channels (4*8-bit or 2*16-bit)
■
Watchdog timer
■
Real-time clock
■
Low-power consumption modes: Sleep/stop mode function
■
Low voltage detection circuit
Maximum of 5 channels able to operate simultaneously
(including 2 external channels)
3 transfer sources (external pin/internal peripheral/software)
Transfer mode (demand transfer/burst transfer/step
transfer/block transfer)
Fly-by transfer support (between external I/O and memory)
Transfer data size selectable from 8/16/32-bit
■
A/D converter (successive approximation type)
10-bit resolution: 32 channels
Conversion time: minimum 1 s
■
External interrupt inputs : 16 channels
12 channels shared with CAN RX, I2C SDA or I2C SCL pins
■
Bit search module (for REALOS)
Function to search from the MSB (most significant bit) for the
position of the first “0”, “1”, or changed bit in a word
■
LIN-USART (full duplex double buffer): 8 channels, 4 channels
with FIFO
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
Cypress Semiconductor Corporation
Document Number: 002-04606 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 20, 2016
MB91460G Series
■
Clock supervisor
Monitors the sub-clock (32 kHz) and the main clock (4 MHz) ,
and switches to a recovery clock (CR oscillator, etc.) when the
oscillations stop.
■
Main oscillator stabilization timer
Generates an interrupt in sub-clock mode after the stabilization
wait time has elapsed on the 23-bit stabilization wait time
counter
■
Clock modulator
■
■
Clock monitor
■
Sub-clock calibration
Corrects the real-time clock timer when operating with the 32
kHz or CR oscillator
Sub-oscillator stabilization timer
Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time
counter
■
Power supply range 3 V to 5 V (1.8 V internal logic provided by
a step-down voltage converter)
■
Operating temperature range: between 40°C and 125°C
Package and Technology
■
Package: 320-pin plastic BGA (BGA-320)
■
CMOS 0.18 m technology
Document Number: 002-04606 Rev. *A
Page 2 of 146
MB91460G Series
Contents
1.
Product Lineup............................................................. 4
2.
2.1
Pin Assignment............................................................ 6
MB91F469Gx................................................................. 6
3.
3.1
3.2
Pin Description............................................................. 7
MB91F469Gx................................................................. 7
Power Supply/Ground Pins.......................................... 21
4.
I/O Circuit Types......................................................... 22
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Handling Devices .......................................................
Preventing Latch-up.....................................................
Handling of Unused Input Pins ....................................
Power Supply Pins.......................................................
Crystal Oscillator Circuit...............................................
Notes on using External Clock.....................................
Mode pins (MD_x)........................................................
Notes on operating in PLL clock mode ........................
Pull-up control ..............................................................
Notes on PS register....................................................
29
29
29
29
29
29
30
30
30
30
6.
6.1
6.2
6.3
Notes on Debugger....................................................
Execution of the RETI Command ................................
Break function ..............................................................
Operand break .............................................................
31
31
31
31
7.
7.1
Block Diagram............................................................ 32
MB91F469Gx............................................................... 32
8.
8.1
8.2
8.3
8.4
CPU and Control Unit ................................................
Features.......................................................................
Internal Architecture.....................................................
Programming Model.....................................................
Registers......................................................................
33
33
33
34
35
9.
9.1
9.2
9.3
9.4
9.5
9.6
Embedded Program/Data Memory (Flash) ..............
Flash features ..............................................................
Operation modes .........................................................
Flash Access in CPU Mode .........................................
Parallel Flash Programming Mode...............................
Power on Sequence in Parallel Programming Mode ...
Flash Security ..............................................................
38
38
38
39
42
44
45
10.
Memory Space............................................................ 48
15.3
15.4
15.5
15.6
15.7
DC Characteristics ........................................................ 99
A/D Converter Characteristics .................................... 102
Alarm Comparator Characteristics.............................. 106
Flash Memory Program/Erase Characteristics ........... 107
AC Characteristics ...................................................... 107
16.
Ordering Information ................................................ 141
17.
Package Dimension .................................................. 142
18.
Revision History........................................................ 143
19. Main Changes in this Edition................................... 144
Document History .............................................................. 145
11. Memory Maps ............................................................. 49
11.1 MB91F469Gx............................................................... 49
12. I/O Map ........................................................................ 50
12.1 MB91F469Gx............................................................... 50
12.2 Flash Memory and External Bus Area ......................... 81
13.
Interrupt Vector Table ................................................ 83
14. Recommended Settings ............................................ 88
14.1 PLL and Clock Gear Settings....................................... 88
14.2 Clock Modulator Settings ............................................. 89
15. Electrical Characteristics .......................................... 95
15.1 Absolute maximum ratings........................................... 95
15.2 Recommended Operating Conditions.......................... 98
Document Number: 002-04606 Rev. *A
Page 3 of 146
MB91460G Series
1. Product Lineup
Feature
MB91V460A
(Evaluation device)
MB91F469Gx
Max. core frequency (CLKB)
80MHz
100MHz at 1.9V main regulator output voltage [1]
88MHz at 1.8V main regulator output voltage
Max. resource frequency (CLKP)
40MHz
50MHz
Max. external bus freq. (CLKT)
40MHz
50MHz
Max. CAN frequency (CLKCAN)
20MHz
50MHz
0.35m
0.18m
Emulation SRAM 32bit read data
2112 KByte
Satellite Flash memory
no
no
Flash Protection
no
yes
Flash CRC calculation
no
yes
64 KByte
64 KByte
Max. FlexRay frequency (SCLK)
Technology
Flash memory
D-RAM
ID-RAM
64 KByte
32 KByte
Flash-cache (F-cache)
16 KByte
16 KBytes
External bus cache (I-cache)
4 KBytes
4 KBytes
Boot-ROM / BI-ROM
MMU/MPU
DMA
4 KByte fixed
MPU (16 ch)
[1]
4 KByte
MPU (8 ch) [2]
5 ch
5 ch
MAC (DSP)
no
no
Watchdog timer
yes
yes
yes (disengageable)
yes
yes
yes
Watchdog timer (RC osc. based)
Bit Search
RTC
1 ch
1 ch
Free Running Timer
8 ch
8 ch
ICU
8 ch
8 ch
OCU
8 ch
8 ch
Reload Timer
8 ch
8 ch
PPG 16-bit
16 ch
16 ch
PFM 16-bit
1 ch
1 ch
Sound Generator
1 ch
1 ch
Up/Down Counter (8/16-bit)
4 ch (8-bit) / 2 ch (16-bit)
4 ch (8-bit) / 2 ch (16-bit)
SMC
6 ch
-
LCD controller (40x4)
1ch
-
Document Number: 002-04606 Rev. *A
Page 4 of 146
MB91460G Series
Feature
C_CAN
MB91V460A
(Evaluation device)
MB91F469Gx
6 ch (128msg)
6 ch (128msg)
4 ch + 4 ch FIFO + 8 ch
4 ch + 4 ch FIFO
4 ch
4 ch
yes (32bit addr, 32bit data, 8 chip selects)
yes (28bit addr, 32bit data, 8 chip selects)
External Interrupts
16 ch
16 ch
NMI Interrupts
1 ch
General IO ports
288
205
ADC (10 bit)
32 ch
32 ch
Alarm Comparator
2 ch
2 ch
Reset input (INITX)
yes
yes
Hardware Standby Input (HSTX)
yes
no
Clock Modulator
yes
yes
Low power mode
yes
yes
Supply Supervisor
(low voltage detection
yes
yes
Clock Supervisor
yes
yes
LIN-USART
I2C (400k)
FR external bus
Main clock oscillator
4MHz
4MHz
Sub clock oscillator
32kHz
32kHz
RC Oscillator
100kHz
100kHz / 2MHz
PLL
x 20
x 25
DSU4
yes
EDSU
JTAG Boundary Scan
yes (32 BP)
no
[2]
yes (16 BP) [2]
no
yes
3V / 5V
3V / 5V
Regulator
yes
yes
Power Consumption
n.a.
2
■ if tSCYCI (2*k 1)*tCLKP, then m k 1, where k is an integer > 1
Notes:
■
The above values are AC characteristics for CLK synchronous mode.
■ tCLKP
is the cycle time of the peripheral clock.
Document Number: 002-04606 Rev. *A
Page 109 of 146
MB91460G Series
Figure 4. Internal clock mode (master mode)
tSCYCI
SCKn
for ESCR:SCES = 0
VOH
VOL
VOL
VOH
SCKn
for ESCR:SCES = 1
VOH
VOL
tSLOVI
tOVSHI
VOH
VOL
SOTn
tIVSHI
tSHIXI
VIH
VIL
SINn
VIH
VIL
Figure 5. External clock mode (slave mode)
tSLSHE
SCKn
for ESCR:SCES = 0
VOH
SCKn
for ESCR:SCES = 1
VOL
tSHSLE
VOH
VOL
VOL
VOH
VOH
VOL
VOH
VOL
tRE
tFE
tSLOVE
SOTn
VOH
VOL
tIVSHE
SINn
Document Number: 002-04606 Rev. *A
VIH
VIL
tSHIXE
VIH
VIL
Page 110 of 146
MB91460G Series
15.7.4 I2C AC Timings at VDD5 = 3.0 to 5.5 V
■
Conditions during AC measurements
All AC tests were measured under the following conditions:
❐ -IOdrive 3 mA
❐ -VDD5 3.0 V to 5.5 V, Iload 3 mA
❐ -VSS5 0 V
❐ -Ta 40 C to 125 C
❐ -Cl 50 pF
❐ -VOL 0.3 VDD5
❐ -VOH 0.7 VDD5
❐ -EPILR 0, PILR 0 (CMOS Hysteresis 0.3 VDD5/0.7 VDD5)
15.7.4.1
Fast mode:
(VDD5 3.5 V to 5.5 V, VSS5 AVSS5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
fSCL
Value
Unit
Min
Max
SCLn
0
400
kHz
tHD;STA
SCLn, SDAn
0.6
s
LOW period of the SCL clock
tLOW
SCLn
1.3
s
HIGH period of the SCL clock
tHIGH
SCLn
0.6
s
tSU;STA
SCLn, SDAn
0.6
s
tHD;DAT
SCLn, SDAn
0
0.9
s
SCL clock frequency
Hold time (repeated) START
condition. After this period, the first clock
pulse is generated
Setup time for a repeated START condition
Data hold time for I
2C-bus
devices
tSU;DAT
SCLn SDAn
100
ns
Rise time of both SDA and SCL signals
tr
SCLn, SDAn
20 + 0.1Cb
300
ns
Fall time of both SDA and SCL signals
tf
SCLn, SDAn
20 + 0.1Cb
300
ns
tSU;STO
SCLn, SDAn
0.6
s
tBUF
SCLn, SDAn
1.3
s
Capacitive load for each bus line
Cb
SCLn, SDAn
400
pF
Pulse width of spike suppressed by input
filter
tSP
SCLn, SDAn
0
(1..1.5)
tCLKP
ns
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
Remark
[1]
1. The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase
relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
Document Number: 002-04606 Rev. *A
Page 111 of 146
Document Number: 002-04606 Rev. *A
SCL
SDA
tHD;STA
tf
S
tr
tHD;DAT
tLOW
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSP
tr
P
tSU;ST0
tBUF
S
tf
MB91460G Series
Page 112 of 146
MB91460G Series
15.7.5 Free-Run Timer Clock
(VDD5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40 C to 125 C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
CKn
Value
Min
Max
4tCLKP
Unit
ns
Note: tCLKP is the cycle time of the peripheral clock.
CKn
VIH
VIH
VIL
VIL
tTIWH
tTIWL
15.7.6 Trigger Input Timing
(VDD5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Condition
Value
Min
Max
Unit
tINP
ICUn
5tCLKP
ns
tATGX
ATGX
5tCLKP
ns
Input capture input trigger
A/D converter trigger
Pin name
Note: tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn,
ATGX
Document Number: 002-04606 Rev. *A
Page 113 of 146
MB91460G Series
15.7.7 External Bus AC Timings at VDD35 4.5 to 5.5 V
■
Conditions during AC measurements
All AC tests were measured under the following conditions:
❐ -IOdrive 5 mA
❐ -VDD35 4.5 V to 5.5 V, Iload 5 mA
❐ -VSS5 0 V
❐ -Ta 40 C to 125 C
❐ -Cl 50 pF
❐ -VOL 0.2 VDD35
❐ -VOH 0.8 VDD35
❐ -EPILR 0, PILR 1 (Automotive Level worst case)
15.7.7.1
Basic Timing
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK
SYSCLK ↓ to CSXn delay time
SYSCLK ↑ to CSXn delay time
(Addr → CS delay)
SYSCLK ↓ to ASX delay time
SYSCLK ↓ to BAAX delay time
SYSCLK ↓ to Address valid delay time
Symbol
tCLCH
tCHCL
Pin name
Max
1/2 tCLKT 4
1/2 tCLKT 5
ns
1/2 tCLKT 5
1/2 tCLKT + 4
ns
9
ns
8
ns
2
8
ns
SYSCLK
ASX
8
ns
7
ns
SYSCLK
BAAX
5
ns
2
ns
10
ns
SYSCLK
SYSCLK
CSXn
tCHCSL
tCLASL
tCLASH
tCLBAL
tCLBAH
tCLAV
Unit
Min
tCLCSL
tCLCSH
Value
SYSCLK
A27 to A0
Note: tCLKT is the cycle time of the external bus clock.
Document Number: 002-04606 Rev. *A
Page 114 of 146
MB91460G Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL
tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
tCLBAH
tCLBAL
BAAX
Document Number: 002-04606 Rev. *A
Page 115 of 146
MB91460G Series
15.7.7.2
Synchronous/Asynchronous Read Access with External MCLKI Input
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
tCHRL
Value
Unit
Min
Max
SYSCLK
RDX
2
7
ns
tCHRH
MCLKI
RDX
10
20
ns
Data valid to RDX ↑ setup time
tDSRH
RDX
D31 to D0
20
ns
RDX ↑ to Data valid hold time (external MCLKI
input)
tRHDX
RDX
D31 to D0
0
ns
Data valid to MCLKI ↑ setup time
tDSCH
MCLKI
D31 to D0
1
ns
MCLKI ↑ to Data valid hold time
tCHDX
MCLKI
D31 to D0
3
ns
SYSCLK ↓ to WRXn (as byte enable) delay
time
tCLWRL
9
ns
SYSCLK ↑ /MCLKI ↑ to RDX delay time
SYSCLK
WRXn
tCLWRH
tCLCSL
SYSCLK ↓ to CSXn delay time
SYSCLK
CSXn
tCLCSH
1
ns
9
ns
8
ns
SYSCLK
MCLKI
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tDSCH
tRHDX
tCHDX
DATA IN
Document Number: 002-04606 Rev. *A
Page 116 of 146
MB91460G Series
15.7.7.3
Synchronous/Asynchronous Read Access with Internal MCLKO --> MCLKI Feedback
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↑ to RDX delay time
Symbol
Pin name
tCHRL
SYSCLK
RDX
tCHRH
Value
Unit
Min
Max
2
7
ns
2
4
ns
Data valid to RDX setup time
tDSRH
RDX
D31 to D0
19
ns
RDX ↑ to Data valid hold time (internal
MCLKO → MCLKI / /MCLKI feedback)
tRHDX
RDX
D31 to D0
0
ns
9
ns
1
ns
9
ns
8
ns
tCLWRL
SYSCLK ↓ to WRXn (as byte enable) delay
time
SYSCLK
WRXn
tCLWRH
tCLCSL
SYSCLK ↓ to CSXn delay time
SYSCLK
CSXn
tCLCSH
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tRHDX
DATA IN
Document Number: 002-04606 Rev. *A
Page 117 of 146
MB91460G Series
15.7.7.4
Synchronous Write Access - Byte Control Type
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to WEX delay time
Symbol
Pin name
tCLWL
SYSCLK
WEX
tCLWH
Data valid to WEX ↓ setup time
tDSWL
WEX
D31 to D0
WEX ↑ to Data valid hold time
tWHDH
WEX
D31 to D0
SYSCLK ↓ to WRXn (as byte enable) delay time
SYSCLK ↓ to CSXn delay time
tCLWRL
Value
Max
8
ns
2
ns
5
ns
tCLKT 10
ns
9
ns
SYSCLK
WRXn
tCLWRH
tCLCSL
SYSCLK
CSXn
tCLCSH
Unit
Min
1
ns
9
ns
8
ns
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCLWH
tCLWL
WEX
tDSWL
tWHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 118 of 146
MB91460G Series
15.7.7.5
Synchronous Write Access - No Byte Control Type
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to WRXn delay time
Symbol
Pin name
tCLWRL
SYSCLK
WRXn
tCLWRH
Value
Unit
Min
Max
9
ns
1
ns
Data valid to WRXn ↓ setup time
tDSWRL
WRXn
D31 to D0
6
ns
WRXn ↑ to Data valid hold time
tWRHDH
WRXn
D31 to D0
tCLKT 10
ns
9
ns
8
ns
SYSCLK ↓ to CSXn delay time
tCLCSL
SYSCLK
CSXn
tCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 119 of 146
MB91460G Series
15.7.7.6
Asynchronous Write Access - Byte Control Type
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
tWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT 6
ns
tDSWL
WEX
D31 to D0
1/2 tCLKT 9
ns
tWHDH
WEX
D31 to D0
1/2 tCLKT 7
ns
tWRLWL
WEX
WRXn
tWHWRH
tCLWL
WEX
CSXn
tWHCH
1/2 tCLKT 2
ns
1/2 tCLKT 1
ns
1/2 tCLKT 1
ns
1/2 tCLKT + 1
ns
CSXn
tWHCH
tCLWL
WRXn
(as byte enable)
tWHWRH
tWRLWL
tWLWH
WEX
tDSWL
tWHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 120 of 146
MB91460G Series
15.7.7.7
Asynchronous Write Access - No Byte Control Type
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
tWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT 6
ns
tDSWRL
WRXn
D31 to D0
1/2 tCLKT 9
ns
tWRHDH
WRXn
D31 to D0
1/2 tCLKT 7
ns
1/2 tCLKT 1
ns
1/2 tCLKT + 1
ns
tCLWRL
WRXn
CSXn
tWRHCH
CSXn
tWRHCH
tCLWRL
tWRLWRH
WRXn
tDSWRL
tWRHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 121 of 146
MB91460G Series
15.7.7.8
RDY Waitcycle Insertion
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
RDY setup time
tRDYS
RDY hold time
tRDYH
Value
Unit
Min
Max
SYSCLK
RDY
19
ns
SYSCLK
RDY
0
ns
SYSCLK
tRDYS
tRDYH
RDY
15.7.7.9
Bus Hold Timing
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to BGRNTX delay time
Symbol
Pin name
tCLBGL
tCLBGH
Bus HIZ to BGRNTX ↓
tAXBGL
BGRNTX ↑ to Bus drive
tBGHAV
Value
Unit
Min
Max
SYSCLK
BGRNTX
5
ns
5
ns
BGRNTX
MCLK*
A0 to An
RDX, ASX
WRXn,WEX
CSXn,BAAX
tCLKT + 2
ns
tCLKT 1
ns
Note: BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as
long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.
SYSCLK
BRQ
tCLBGL
tCLBGH
BGRNTX
tAXBGL
tBGHAV
ADDR,RDX,WRX,
WEX,CSXn,ASX,
MCLKE,MCLKI,
MCLKO,BAAX
Document Number: 002-04606 Rev. *A
Page 122 of 146
MB91460G Series
15.7.7.10 Clock Relationships
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK to MCLKO
Symbol
Pin name
tCSHMH
tCSLML
MCLKO ↓ to MCLKE (in sleep mode)
tCLML
tCLMH
Value
Unit
Min
Max
SYSCLK
MCLKO
1
5
ns
0
2
ns
MCLKO
MCLKE
5
ns
3
ns
SYSCLK
tCSHMH
tCSLML
MCLKO
tCLML
tCLMH
MCLKE (sleep)
Document Number: 002-04606 Rev. *A
Page 123 of 146
MB91460G Series
15.7.7.11 DMA Transfer
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to DACKX delay time
SYSCLK ↓ to DEOP delay time
Symbol
Pin name
tCLDAL
tCLDAH
tCLDEL
Value
Unit
Min
Max
SYSCLK
DACKXn
8
ns
8
ns
SYSCLK
DEOPn
7
ns
9
ns
tCHDAL
SYSCLK
DACKXn
1
8
ns
SYSCLK ↑ to DEOP delay time
(ADDR → delayed CS)
tCHDEL
SYSCLK
DEOPn
1
8
ns
DREQ setup time
tDRQS
SYSCLK
DREQn
19
ns
DREQ hold time
tDRQH
SYSCLK
DREQn
0
ns
DEOTXn setup time
tDTXS
SYSCLK
DEOTXn
20
ns
DEOTXn hold time
tDTXH
SYSCLK
DEOTXn
0
ns
SYSCLK ↑ to DACKX delay time
(ADDR → delayed CS)
tCLDEH
Note: DREQ and DEOTX must be applied for at least 5 tCLKT to ensure that they are really sampled and evaluated.Under best
case conditions (DMA not busy) only setup and hold times are required.
Document Number: 002-04606 Rev. *A
Page 124 of 146
MB91460G Series
SYSCLK
tCLDAL
tCLDAH
tCLDEL
tCLDEH
DACKX
DEOP
tCHDAL
delayed DACKX
tCHDEL
delayed DEOP
tDRQS
tDRQH
tDTXS
tDTXH
DREQ
DEOTX
Document Number: 002-04606 Rev. *A
Page 125 of 146
MB91460G Series
15.7.7.12 DMA Flyby Transfer
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C
to 125 C)
Parameter
SYSCLK ↑ to IORDX delay time
Symbol
Pin name
tCHIRL
tCHIRH
tCHIWL
SYSCLK ↑ to IOWRX delay time
tCHIWH
Value
Unit
Min
Max
SYSCLK
IORDX
2
8
ns
0
4
ns
SYSCLK
IOWRX
2
8
ns
1
3
ns
SYSCLK
tCHIRH
tCHIRL
IORDX
tCHIWH
tCHIWL
IOWRX
Document Number: 002-04606 Rev. *A
Page 126 of 146
MB91460G Series
15.7.8 External Bus AC Timings at VDD35 3.0 to 4.5 V
■
Conditions during AC measurements
All AC tests were measured under the following conditions:
❐ -IOdrive 5 mA
❐ -VDD35 3.0 V to 4.5 V, Iload 3 mA
❐ -VSS5 0 V
❐ -Ta 40 C to 125 C
❐ -Cl 50 pF
❐ -VOL 0.2 VDD35
❐ -VOH 0.8 VDD35
❐ -EPILR 0, PILR 1 (Automotive Level worst case)
15.7.8.1
Basic Timing
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK
SYSCLK ↓ to CSXn delay time
SYSCLK ↑ to CSXn delay time
(Addr → CS delay)
SYSCLK ↓ to ASX delay time
SYSCLK ↓ to BAAX delay time
SYSCLK ↓ to Address valid delay time
Document Number: 002-04606 Rev. *A
Symbol
tCLCH
tCHCL
Pin name
SYSCLK
tCLASH
tCLBAL
tCLBAH
tCLAV
Max
1/2 tCLKT 1
1/2 tCLKT 3
ns
1/2 tCLKT 3
1/2 tCLKT 1
ns
9
ns
7
ns
1
4
ns
SYSCLK
ASX
5
ns
6
ns
SYSCLK
BAAX
6
ns
0
ns
13
ns
SYSCLK
CSXn
tCHCSL
tCLASL
Unit
Min
tCLCSL
tCLCSH
Value
SYSCLK
A27 to A0
Page 127 of 146
MB91460G Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL
tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
tCLBAH
tCLBAL
BAAX
Document Number: 002-04606 Rev. *A
Page 128 of 146
MB91460G Series
15.7.8.2
Synchronous/Asynchronous Read Access With External MCLKI Input
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
tCHRL
Value
Unit
Min
Max
SYSCLK
RDX
1
3
ns
tCHRH
MCLKI
RDX
11
25
ns
Data valid to RDX ↑ setup time
tDSRH
RDX
D31 to D0
25
ns
RDX ↑ to Data valid hold time (external MCLKI
input)
tRHDX
RDX
D31 to D0
0
ns
Data valid to MCLKI ↑ setup time
tDSCH
MCLKI
D31 to D0
1
ns
MCLKI ↑ to Data valid hold time
tCHDX
MCLKI
D31 to D0
3
ns
SYSCLK ↓ to WRXn (as byte enable) delay
time
tCLWRL
5
ns
1
ns
5
ns
6
ns
SYSCLK ↑/MCLKI ↑ to RDX delay time
SYSCLK
WRXn
tCLWRH
tCLCSL
SYSCLK ↓ to CSXn delay time
SYSCLK
CSXn
tCLCSH
SYSCLK
MCLKI
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tDSCH
tRHDX
tCHDX
DATA IN
Document Number: 002-04606 Rev. *A
Page 129 of 146
MB91460G Series
15.7.8.3
Synchronous/Asynchronous Read Access with Internal MCLKO --> MCLKI Feedback
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↑ to RDX delay time
Symbol
Pin name
tCHRL
SYSCLK
RDX
tCHRH
Value
Unit
Min
Max
1
3
ns
2
4
ns
Data valid to RDX ↑ setup time
tDSRH
RDX
D31 to D0
25
ns
RDX ↑ to Data valid hold time
(internal MCLKO → MCLKI /
/MCLKI feedback)
tRHDX
RDX
D31 to D0
0
ns
5
ns
tCLWRL
SYSCLK ↓ to WRXn
(as byte enable) delay time
tCLWRH
tCLCSL
SYSCLK ↓ to CSXn delay time
tCLCSH
SYSCLK
WRXn
SYSCLK
CSXn
1
ns
5
ns
6
ns
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tRHDX
DATA IN
Document Number: 002-04606 Rev. *A
Page 130 of 146
MB91460G Series
15.7.8.4
Synchronous Write Access - Byte Control Type
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to WEX delay time
Symbol
Pin name
tCLWL
SYSCLK
WEX
tCLWH
Value
Unit
Min
Max
5
ns
1
ns
Data valid to WEX ↓ setup time
tDSWL
WEX
D31 to D0
11
ns
WEX ↑ to Data valid hold time
tWHDH
WEX
D31 to D0
tCLKT 13
ns
SYSCLK ↓ to WRXn (as byte enable) delay
time
tCLWRL
5
ns
1
ns
5
ns
6
ns
SYSCLK ↓ to CSXn delay time
SYSCLK
WRXn
tCLWRH
tCLCSL
SYSCLK
CSXn
tCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCLWH
tCLWL
WEX
tDSWL
tWHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 131 of 146
MB91460G Series
15.7.8.5
Synchronous Write Access - No Byte Control Type
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to WRXn delay time
Symbol
Pin name
tCLWRL
SYSCLK
WRXn
tCLWRH
Value
Unit
Min
Max
5
ns
1
ns
Data valid to WRXn ↓ setup time
tDSWRL
WRXn
D31 to D0
11
ns
WRXn ↑ to Data valid hold time
tWRHDH
WRXn
D31 to D0
tCLKT 13
ns
5
ns
6
ns
SYSCLK ↓ to CSXn delay time
tCLCSL
SYSCLK
CSXn
tCLCSH
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 132 of 146
MB91460G Series
15.7.8.6
Asynchronous Write Access - Byte Control Type
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
tWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT 4
ns
tDSWL
WEX
D31 to D0
1/2 tCLKT 12
ns
tWHDH
WEX
D31 to D0
1/2 tCLKT 11
ns
tWRLWL
WEX
WRXn
tWHWRH
tCLWL
WEX
CSXn
tWHCH
1/2 tCLKT 1
ns
1/2 tCLKT 1
ns
1/2 tCLKT 1
ns
1/2 tCLKT + 1
ns
CSXn
tWHCH
tCLWL
WRXn
(as byte enable)
tWHWRH
tWRLWL
tWLWH
WEX
tDSWL
tWHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 133 of 146
MB91460G Series
15.7.8.7
Asynchronous Write Access - No Byte Control Type
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
tWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT 3
ns
tDSWRL
WRXn
D31 to D0
1/2 tCLKT 12
ns
tWRHDH
WRXn
D31 to D0
1/2 tCLKT 11
ns
1/2 tCLKT 1
ns
1/2 tCLKT + 1
ns
tCLWRL
WRXn
CSXn
tWRHCH
CSXn
tWRHCH
tCLWRL
tWRLWRH
WRXn
tDSWRL
tWRHDH
DATA OUT
Document Number: 002-04606 Rev. *A
Page 134 of 146
MB91460G Series
15.7.8.8
RDY Waitcycle Insertion
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
Symbol
Pin name
RDY setup time
tRDYS
RDY hold time
tRDYH
Value
Unit
Min
Max
SYSCLK
RDY
24
ns
SYSCLK
RDY
0
ns
SYSCLK
tRDYS
tRDYH
RDY
Document Number: 002-04606 Rev. *A
Page 135 of 146
MB91460G Series
15.7.8.9
Bus Hold Timing
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to BGRNTX delay time
Symbol
Pin name
tCLBGL
tCLBGH
Bus HIZ to BGRNTX ↓
tAXBGL
BGRNTX ↑ to Bus drive
tBGHAV
Value
Unit
Min
Max
SYSCLK
BGRNTX
5
ns
6
ns
BGRNTX
MCLK*
A0 to An
RDX, ASX
WRXn,WEX
CSXn,BAAX
tCLKT 2
ns
tCLKT 2
ns
Note: BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as
long as the bus shall be hold.After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.
SYSCLK
BRQ
tCLBGL
tCLBGH
BGRNTX
tAXBGL
tBGHAV
ADDR,RDX,WRX,
WEX,CSXn,ASX,
MCLKE,MCLKI,
MCLKO,BAAX
Document Number: 002-04606 Rev. *A
Page 136 of 146
MB91460G Series
15.7.8.10 Clock Relationships
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK to MCLKO
Symbol
Pin name
tCSHMH
tCSLML
MCLKO ↓ to MCLKE (in sleep mode)
tCLML
tCLMH
Value
Unit
Min
Max
SYSCLK
MCLKO
1
5
ns
0
2
ns
MCLKO
MCLKE
4
ns
3
ns
SYSCLK
tCSHMH
tCSLML
MCLKO
tCLML
tCLMH
MCLKE (sleep)
Document Number: 002-04606 Rev. *A
Page 137 of 146
MB91460G Series
15.7.8.11 DMA Transfer
(VDD35 3.0 V to 4.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↓ to DACKX delay time
SYSCLK ↓ to DEOP delay time
Symbol
Pin name
tCLDAL
SYSCLK
DACKXn
tCLDAH
tCLDEL
SYSCLK
DEOPn
Value
Unit
Min
Max
9
ns
7
ns
8
ns
7
ns
tCHDAL
SYSCLK
DACKXn
0
8
ns
SYSCLK ↑ to DEOP delay time
(ADDR → delayed CS)
tCHDEL
SYSCLK
DEOPn
1
8
ns
DREQ setup time
tDRQS
SYSCLK
DREQn
25
ns
DREQ hold time
tDRQH
SYSCLK
DREQn
0
ns
DEOTXn setup time
tDTXS
SYSCLK
DEOTXn
26
ns
DEOTXn hold time
tDTXH
SYSCLK
DEOTXn
0
ns
SYSCLK ↑ to DACKX delay time
(ADDR → delayed CS)
tCLDEH
Note: DREQ and DEOTX must be applied for at least 5 tCLKT to ensure that they are really sampled and evaluated.Under best case
conditions (DMA not busy) only setup and hold times are required.
Document Number: 002-04606 Rev. *A
Page 138 of 146
MB91460G Series
SYSCLK
tCLDAL
tCLDAH
tCLDEL
tCLDEH
DACKX
DEOP
tCHDAL
delayed DACKX
tCHDEL
delayed DEOP
tDRQS
tDRQH
tDTXS
tDTXH
DREQ
DEOTX
Document Number: 002-04606 Rev. *A
Page 139 of 146
MB91460G Series
15.7.8.12 DMA Flyby Transfer
(VDD35 4.5 V to 5.5 V, Vss5 AVss5 0 V, TA 40 C to 125 C)
Parameter
SYSCLK ↑ to IORDX delay time
Symbol
Pin name
tCHIRL
SYSCLK
IORDX
tCHIRH
tCHIWL
SYSCLK ↑ to IOWRX delay time
tCHIWH
SYSCLK
IOWRX
Value
Min
Max
1
6
Unit
ns
2
3
ns
0
5
ns
2
3
ns
SYSCLK
tCHIRH
tCHIRL
IORDX
tCHIWH
tCHIWL
IOWRX
Document Number: 002-04606 Rev. *A
Page 140 of 146
MB91460G Series
16. Ordering Information
Part number
Package
not recommended
MB91F469GAPB-GS
MB91F469GBPB-GS
Remarks
320-pin plastic BGA
(BGA-320P-M06)
not recommended
MB91F469GBPB-GSE1
Document Number: 002-04606 Rev. *A
Page 141 of 146
MB91460G Series
17. Package Dimension
320-pin plastic PBGA
Lead pitch
1.27 mm
Package width ×
package length
27.00 mm × 27.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
2.46 mm Max
Weight
2.90 g
(BGA-320P-M06)
320-pin plastic PBGA
(BGA-320P-M06)
B
27.00(1.063)
24.13(.950)
24.00±0.10(.945±.004)
1.44
(.057)
A
0.635
(.025)
1.27
(.050)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1.27
(.050)
27.00
(1.063)
24.13
(.950)
24.00±0.10
(.945±.004)
0.635
(.025)
INDEX
1.44
(.057)
0.20(.008) (4X)
YW V U T R P NM L K J H G F E D C B A
ø0.75±0.15(.030±.006)
ø0.30(.012) M C A B
ø0.15(.006) M C
C
0.15(.006) C
1.66±0.10
(.065±.004)
©2006-2008
FUJITSU MICROELECTRONICS LIMITED BGA320006S-c-2-2
C
2006 FUJITSU LIMITED BGA320006S-c-2-1
Document Number: 002-04606 Rev. *A
2.46(.097)
MAX.
0.35(.014)
MIN.
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 142 of 146
MB91460G Series
18. Revision History
Spansion Publication Number: DS07-16608-1E
Version
Date
2.0
2008-01-08
Initial version
2.1
2008-01-11
I/O circuit type J2: Feedback resistor = approx. 2 * 5 M.
2.2
2008-02-01
Pins 257 to 320 are GND.
2.3
2008-02-04
Various changes after proofread by FJ
2.4
2008-02-15
Corrected product lineup table: No NMI function,
updated disclaimer at the end
2.5
2008-02-22
Corrected naming and size of Flash-cache (F-cache)
2008-04-29
Flash Operation modes: Added note about the
"flash access mode switching" incl. address in Boot ROM
Flash parallel programming: wait times added
2008-08-18
Product Lineup: corrected typos
Pin Description: corrected CAN RX (is input only)
IO Circuit Type: corrected typos
Handling Devices: updated the "Notes on PS register"
Interrupt Vector Table: corrected the footnotes
Electrical Characteristics: removed the note that analog input/output
pins cannot accept +B signal input.
DC characteristics: updated PullUp/Down resistance values,
corrected the table footnotes,
splitted ILV into external and internal LV detection
ADC Characteristics: Corrected the items about nonlinearity error
FLASH memory parallel programming mode: added section "Poweron
Sequence in parallel programming mode"
FLASH memory program/erase characteristics: word programming time
is for 16- and 32-bit
Ordering information: updated the part numbers
All pages: Kilobytes are now written with “K”
2.7
2008-08-19
DC characteristics: updated the current consumption values ICC, ICCH
3.0
2009-01-09
DC characteristics: corrected the current consumption values ICC, ICCH
Added Ta=125C characteristics
2.6
Remark
Document Number: 002-04606 Rev. *A
Page 143 of 146
MB91460G Series
19. Main Changes in this Edition
Page
Section
Change Results
33
Block Diagram
Corrected alarm comparator input pin name.
ALARM1 ALARM_1
100
Electrical Characteristics
15.3. DC characteristics
Corrected output "L" voltage condition.
IOH IOL
103
15.4. A/D converter characteristics
Corrected the explanation for “Zero reading voltage” and “Full scale reading voltage” in the table.
Unit:
LSB V
Value:
AVRL - 1.5 AVRL - 1.5 LSB
AVRL + 0.5 AVRL + 0.5 LSB
AVRL + 2.5 AVRL + 2.5 LSB
AVRH - 3.5 AVRH - 3.5 LSB
AVRH - 1.5 AVRH - 1.5 LSB
AVRH + 0.5 AVRH + 0.5 LSB
109
15.7. AC characteristics
15.7.3 LIN-USART Timings at
VDD5 = 3.0 to 5.5 V
Corrected “ All AC tests were measured under the
following conditions:“.
Ta:
125 C 125 C
111
112
Corrected the figures in "Internal clock mode
(master mode)" and "External clock mode (slave mode)".
VOH VIH, VOL VIL
15.7.4 I2C AC Timings at
VDD5 = 3.0 to 5.5 V
Corrected the explanation for “Rise time of both SDA and SCL signals”
and “Fall time of both SDA and SCL signals” in the table.
0.1Cb 0.1Cb
NOTE: Please see “Document History” for later revised information.
Document Number: 002-04606 Rev. *A
Page 144 of 146
MB91460G Series
Document History
Document Title: MB91F469GA/F469GB, FR60 MB91460G Series, 32-bit Microcontroller Datasheet
Document Number: 002-04606
Revision
ECN
Orig. of
Change
Submission
Date
**
AKIH
05/25/2009
Migrated to Cypress and assigned document number 002-04606.
No change to document contents or format.
*A
5218210
AKIH
04/20/2016
Updated to Cypress template
Document Number: 002-04606 Rev. *A
Description of Change
Page 145 of 146
MB91460G Series
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Document Number: 002-04606 Rev. *A
Revised April 20, 2016
Page 146 of 146
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