MB95F354EWQN-G-SNE1

MB95F352E/F352L/F353E/F353L/F354E/F354L 2 CMOS F MC-8FX MB95350L Series 8-bit Microcontrollers MB95350L is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. Features F2MC-8FX CPU core LIN-UART Instruction set optimized for controllers ■ Full duplex double buffer ■ Capable of clock-synchronous serial data transfer and clock-asynchronous serial data transfer ■ Multiplication and division instructions ■ 16-bit arithmetic operations ■ Bit test branch instructions ■ Bit manipulation instructions, etc. External interrupt  6 channels Clock ■ Selectable main clock source Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) Main CR clock (1/8/10/12.5 MHz 2%, maximum machine clock frequency: 12.5 MHz) ■ Selectable subclock source Sub-OSC clock (32.768 kHz) External clock (32.768 kHz) Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz) 8/16-bit composite timer  2 channels ■ Time-base timer  1 channel ■ Watch prescaler  1 channel Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ■ Can be used to wake up the device from different low power consumption (standby) modes 8/10-bit A/D converter  6 channels ■ ■ Stop mode ■ Sleep mode ■ Watch mode ■ Time-base timer mode I/O port MB95F352L/F353L/F354L (maximum no. of I/O ports: 21) General-purpose I/O ports (N-ch open drain) ................ : 3 General-purpose I/O ports (CMOS I/O) ....................... : 18 ■ UART/SIO  1 channel (The channel can be used either as a UART/SIO channel or as an I2C channel.) ■ Alternative selection of UART/SIO ■ Full duplex double buffer ■ Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer 2 I C  2 channels (One of the two channels can be used either as an I2C channel or as a UART/SIO channel.) ■ Supports Standard-mode and Fast-mode (400 kHz) ■ Built-in wake-up function MB95F352E/F353E/F354E (maximum no. of I/O ports: 22) General-purpose I/O ports (N-ch open drain) ................ : 3 General-purpose I/O ports (CMOS I/O) ....................... : 18 General-purpose input port (CMOS input) ..................... : 1 On-chip debug ■ 1-wire serial control ■ Serial writing supported (asynchronous mode) Hardware/software watchdog timer ■ Built-in hardware watchdog timer ■ Built-in software watchdog timer Low-voltage detection reset and interrupt circuit ■ Built-in low-voltage detector Clock supervisor counter ■ Cypress Semiconductor Corporation Document Number: 002-07527 Rev. *A 8-bit and 10-bit resolution can be chosen. Low power consumption (standby) modes ■ Timer ■ ■ • 198 Champion Court Built-in clock supervisor counter function • San Jose, CA 95134-1709 • 408-943-2600 Revised March 31, 2016 MB95350L Series Programmable port input voltage level ■ CMOS input level / hysteresis input level Dual operation Flash memory ■ The erase/write operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. Flash memory security function ■ Document Number: 002-07527 Rev. *A Protects the content of the Flash memory Page 2 of 70 MB95350L Series Content Product Line-up ................................................................ 3 Packages and Corresponding Products ........................ 5 Differences Among Products and Notes On Product Selection ............................................................. 6 Pin Assignment ................................................................ 7 Pin Description (24-pin MCU) .......................................... 8 Pin Description (32-pin MCU) ........................................ 10 I/O Circuit Type ............................................................... 12 Notes On Device Handling ............................................. 15 Pin Connection ............................................................... 15 Block Diagram ................................................................ 16 CPU Core ......................................................................... 17 I/O Map ............................................................................. 18 Interrupt Source Table ................................................... 22 Electrical Characteristics ............................................... 23 Absolute Maximum Ratings ....................................... 23 Recommended Operating Conditions ....................... 25 DC Characteristics .................................................... 26 AC Characteristics ..................................................... 29 Document Number: 002-07527 Rev. *A Clock Timing .............................................................. 29 Source Clock/Machine Clock ................................... 31 External Reset ........................................................... 34 Power-on Reset ......................................................... 35 Peripheral Input Timing ............................................. 36 LIN-UART Timing ...................................................... 37 Low-voltage Detection ............................................... 43 I2C Timing ................................................................. 45 UART/SIO, Serial I/O Timing ..................................... 48 A/D Converter ............................................................ 50 A/D Converter Electrical Characteristics ................... 50 Notes on Using the A/D Converter ............................ 51 Definitions of A/D Converter Terms ........................... 52 Flash Memory Write/Erase Characteristics ............... 54 Sample Characteristics .................................................. 55 Mask Options .................................................................. 61 Ordering Information ...................................................... 62 Package Dimension ........................................................ 63 Major Changes ............................................................... 66 Page 3 of 70 MB95350L Series 1. Product Line-up Part number MB95F352E MB95F353E MB95F354E MB95F352L MB95F353L MB95F354L Parameter Type Clock supervisor counter Flash memory product It supervises the main clock oscillation. Program ROM capacity 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Low-voltage detection reset Yes Reset input No Selected through software Dedicated CPU functions Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time General-purpose I/O I/O ports (Max): 22 CMOS I/O: 18 N-ch open drain: 3 CMOS input: 1 Time-base timer Interrupt cycle: 0.256 ms to 8.3 s (when external clock = 4 MHz) Hardware/software watchdog timer Reset generation cycle - Main oscillation clock at 10 MHz: 105 ms (Min) The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. LIN-UART A wide range of communication speeds can be selected by a dedicated reload timer. Clock-synchronous serial data transfer and clock-asynchronous serial data transfer is enabled. The LIN function can be used as a LIN master or a LIN slave. 8/10-bit A/D converter : 136 : 8 bits : 1 to 3 bytes : 1, 8 and 16 bits : 61.5 ns (with machine clock = 16.25 MHz) : 0.6 µs (with machine clock = 16.25 MHz) I/O ports (Max): 21 CMOS I/O: 18 N-ch open drain: 3 6 channels 8-bit resolution and 10-bit resolution can be chosen. 2 channels 8/16-bit composite timer External interrupt On-chip debug The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel". It has built-in timer function, PWC function, PWM function and input capture function. Count clock: it can be selected from internal clocks (seven types) and external clocks. It can output square wave. 6 channels Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) It can be used to wake up the device from different standby modes. 1-wire serial control It supports serial writing. (asynchronous mode) (Continued) Document Number: 002-07527 Rev. *A Page 4 of 70 MB95350L Series (Continued) Part number MB95F352E MB95F353E MB95F354E MB95F352L MB95F353L MB95F354L Parameter 1 channel (The channel can be used either as a UART/SIO channel or as an I2C channel.) UART/SIO Data transfer with UART/SIO is enabled. It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error detection function. It uses the NRZ type transfer format. LSB-first data transfer and MSB-first data transfer are available to use. Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer is enabled. 2 channels (One of the two channels can be used either as an I2C channel or as a UART/SIO channel.) I2 C Master/slave transmission and receiving It has the following functions: • bus error function • arbitration function • transmission direction detection function • wake-up function • functions of generating and detecting repeated START conditions. Watch prescaler Eight different time intervals can be selected. Flash memory It supports automatic programming, Embedded Algorithm, write/erase/erase-suspend/erase-resume commands. It has a flag indicating the completion of the operation of Embedded Algorithm. Number of write/erase cycles: 100000 Data retention time: 20 years Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode Package Document Number: 002-07527 Rev. *A FPT-24P-M34 FPT-24P-M10 LCC-32P-M19 Page 5 of 70 MB95350L Series 2. Packages and Corresponding Products Part number MB95F352E MB95F353E MB95F354E MB95F352L MB95F353L MB95F354L FPT-24P-M34 O O O O O O FPT-24P-M10 O O O O O O LCC-32P-M19 O O O O O O Package O: Available Document Number: 002-07527 Rev. *A Page 6 of 70 MB95350L Series 3. Differences Among Products and Notes On Product Selection ■ Current consumption When using the on-chip debug function, take account of the current consumption of flash erase/write. For details of current consumption, see “Electrical Characteristics”. ■ Package For details of information on each package, see “Packages and Corresponding Products” and “Package Dimension”. ■ Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of the operating voltage, see “Electrical Characteristics” ■ On-chip debug function The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. Document Number: 002-07527 Rev. *A Page 7 of 70 MB95350L Series 4. Pin Assignment X0/PF0 X1/PF1 1 2 Vss X1A/PG2 3 4 X0A/PG1 Vcc 5 6 UCK/PG0 RST/PF2 UI/SCL1/P17 UO/SDA1/P16 TO10/P62 TO11/P63 7 24 23 (TOP VIEW) 22 21 SOP24 FPT-24P-M34 20 19 18 TSSOP24 FPT-24P-M10 8 17 16 9 10 11 12 15 14 32 31 30 29 28 27 26 25 X0/PF0 X1/PF1 NC NC NC NC P07/INT07 P12/EC0/DBG 13 P12/EC0/DBG P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01 P00/AN00 P64/EC1 P14/SDA0 P15/SCL0 Vss X1A/PG2 1 2 X0A/PG1 Vcc 3 4 UCK/PG0 5 6 Document Number: 002-07527 Rev. *A QFN32 LCC-32P-M19 9 10 11 12 13 14 15 16 NC NC SDA0/P14 SCL0/P15 7 8 TO11/P63 TO10/P62 NC NC RST/PF2 UI/SCL1/P17 UO/SDA1/P16 (TOP VIEW) 24 23 22 21 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT 20 19 18 17 P02/INT02/AN02/SCK P01/AN01 P00/AN00 P64/EC1 Page 8 of 70 MB95350L Series 5. Pin Description (24-pin MCU) Pin no. 1 2 3 4 5 6 7 Pin name I/O circuit type* PF0 X0 PF1 X1 VSS PG2 X1A PG1 X0A VCC PG0 UCK B B — C C — G PF2 8 RST 10 SCL1 J 14 15 16 Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin General-purpose I/O port UART/SIO clock pin Reset pin Dedicated reset pin on MB95F352L/F353L/F354L I2C ch. 1 clock I/O pin UI UART/SIO data input pin General-purpose I/O port SDA1 J P62 P63 P15 SCL0 P14 SDA0 P64 EC1 P00 AN00 I2C ch. 1 data I/O pin UART/SIO data output pin D General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin D TO11 13 General-purpose I/O port Main clock I/O oscillation pin P16 TO10 12 Main clock input oscillation pin General-purpose I/O port UO 11 General-purpose I/O port General-purpose input port A P17 9 Function General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin I I D E General-purpose I/O port I2C ch. 0 clock I/O pin General-purpose I/O port I2C ch. 0 data I/O pin General-purpose I/O port 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port A/D converter analog input pin (Continued) Document Number: 002-07527 Rev. *A Page 9 of 70 MB95350L Series (Continued) Pin no. 17 Pin name I/O circuit type* P01 AN01 E P02 18 19 20 21 INT02 AN02 E A/D converter analog input pin LIN-UART clock I/O pin P03 General-purpose I/O port INT03 AN03 E External interrupt input pin A/D converter analog input pin SOT LIN-UART data output pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 F A/D converter analog input pin SIN LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin INT05 E INT06 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin G TO01 P07 INT07 DBG External interrupt input pin 8/16-bit composite timer ch. 0 output pin G P12 EC0 External interrupt input pin A/D converter analog input pin P06 24 External interrupt input pin SCK TO00 23 General-purpose I/O port A/D converter analog input pin General-purpose I/O port AN05 22 Function General-purpose I/O port External interrupt input pin General-purpose I/O port H 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “I/O Circuit Type”. Document Number: 002-07527 Rev. *A Page 10 of 70 MB95350L Series 6. Pin Description (32-pin MCU) Pin no. Pin name I/O circuit type* 1 VSS — 2 3 4 5 PG2 X1A PG1 X0A VCC PG0 UCK C C — G PF2 6 RST 8 SCL1 J Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin General-purpose I/O port UART/SIO clock pin Reset pin Dedicated reset pin on MB95F352L/F353L/F354L I2C ch. 1 clock I/O pin UI UART/SIO data input pin P16 General-purpose I/O port SDA1 J P63 P62 I2C ch. 1 data I/O pin UART/SIO data output pin D TO11 10 General-purpose I/O port General-purpose I/O port UO 9 Power supply pin (GND) General-purpose input port A P17 7 Function General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin D TO10 General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin 11 NC — It is an internally connected pin. Always leave it unconnected. 12 NC — It is an internally connected pin. Always leave it unconnected. 13 NC — It is an internally connected pin. Always leave it unconnected. 14 NC — It is an internally connected pin. Always leave it unconnected. 15 16 17 18 P14 SDA0 P15 SCL0 P64 EC1 P00 AN00 I I D E General-purpose I/O port I2C ch. 0 data I/O pin General-purpose I/O port I2C ch. 0 clock I/O pin General-purpose I/O port 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port A/D converter analog input pin (Continued) Document Number: 002-07527 Rev. *A Page 11 of 70 MB95350L Series (Continued) Pin no. 19 Pin name I/O circuit type* P01 AN01 E P02 20 21 22 23 INT02 AN02 E A/D converter analog input pin LIN-UART clock I/O pin P03 General-purpose I/O port INT03 AN03 E External interrupt input pin A/D converter analog input pin SOT LIN-UART data output pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 F A/D converter analog input pin SIN LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin INT05 E INT06 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin G TO01 External interrupt input pin 8/16-bit composite timer ch. 0 output pin P12 EC0 External interrupt input pin A/D converter analog input pin P06 26 External interrupt input pin SCK TO00 25 General-purpose I/O port A/D converter analog input pin General-purpose I/O port AN05 24 Function General-purpose I/O port H 8/16-bit composite timer ch. 0 clock input pin DBG DBG input pin P07 General-purpose I/O port INT07 G External interrupt input pin 27 NC — It is an internally connected pin. Always leave it unconnected. 28 NC — It is an internally connected pin. Always leave it unconnected. 29 NC — It is an internally connected pin. Always leave it unconnected. 30 NC — It is an internally connected pin. Always leave it unconnected. 31 32 PF1 X1 PF0 X0 B B General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin *: For the I/O circuit types, see “I/O Circuit Type”. Document Number: 002-07527 Rev. *A Page 12 of 70 MB95350L Series 7. I/O Circuit Type Type Circuit Remarks A Reset input / Hysteresis input B P-ch Port select Digital output N-ch ■ Hysteresis input ■ Reset input ■ Oscillation circuit ■ High-speed side ■ Feedback resistance: approx. 1 M ■ CMOS output ■ Hysteresis input Digital output Standby control Hysteresis input Clock input X1 X0 Standby control / Port select P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input ■ Oscillation circuit Port select ■ Low-speed side Pull-up control ■ Feedback resistance: approx.10 M ■ CMOS output ■ Hysteresis input ■ Pull-up control available C R P-ch Digital output P-ch N-ch Digital output Standby control Hysteresis input Clock input X1A X0A Standby control / Port select Port select R Pull-up control Digital output Digital output P-ch N-ch Digital output Standby control Hysteresis input (Continued) Document Number: 002-07527 Rev. *A Page 13 of 70 MB95350L Series Type Circuit D Remarks P-ch Digital output ■ CMOS output ■ Hysteresis input ■ CMOS output ■ Hysteresis input ■ Pull-up control available ■ CMOS output ■ Hysteresis input ■ CMOS input ■ Pull-up control available ■ CMOS output ■ Hysteresis input ■ Pull-up control available ■ N-ch open drain output ■ Hysteresis input Digital output N-ch Standby control Hysteresis input E Pull-up control R P-ch Digital output P-ch Digital output N-ch Analog input A/D control Standby control Hysteresis input F Pull-up control R P-ch Digital output P-ch Digital output N-ch Analog input A/D control Standby control Hysteresis input CMOS input G Pull-up control R P-ch Digital output P-ch Digital output N-ch Standby control Hysteresis input H Standby control Hysteresis input Digital output N-ch (Continued) Document Number: 002-07527 Rev. *A Page 14 of 70 MB95350L Series (Continued) Type Circuit Remarks I N-ch Digital output ■ N-ch open drain output ■ Hysteresis input ■ CMOS input ■ CMOS output ■ Hysteresis input ■ CMOS input ■ N-ch open drain output in I2C mode CMOS input Hysteresis input Standby control J I2C mode control Digital output P-ch N-ch Digital output CMOS input Standby control Document Number: 002-07527 Rev. *A Hysteresis input Page 15 of 70 MB95350L Series 8. Notes On Device Handling ■ Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "14.1 Absolute Maximum Ratings" of “Electrical Characteristics” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. ■ Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. ■ Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. 9. Pin Connection ■ Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. ■ Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. ■ DBG pin Connect the DBG pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board. The DBG pin should not stay at “L” level after power-on until the reset is released. ■ RST pin Connect the RST pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input pin after power-on. The RSTEN bit in the SYSC register is used to switch the pin functions, the reset input function and the general-purpose I/O port function, of the PF2/RST pin. However, only on MB95F352E/F353E/F354E can the pin functions be changed. Document Number: 002-07527 Rev. *A Page 16 of 70 MB95350L Series 10. Block Diagram F2MC-8FX CPU PF2/RST*2 Reset with LVD Flash with security function PF1/X1*2 PF0/X0*2 Oscillator circuit PG2/X1A*2 CR oscillator RAM (496/240 bytes) PG1/X0A*2 Interrupt controller Clock control (P05*3/TO00) (P12*1/DBG) On-chip debug 8/16-bit composite timer ch. 0 (P06*3/TO01) P02/INT02 to P07/INT07 (P00/AN00 to External interrupt P05*3/AN05) Internal bus P12*1/EC0, (P04/EC0) Wild register P62*3/TO10 8/16-bit composite timer ch. 1 P63*3/TO11 P64/EC1 8/10-bit A/D converter I2C ch. 0 I2C ch. 1 (P02/SCK) P14*1/SDA0 P15*1/SCL0 (P16/SDA1) (P17/SCL1) PG0/UCK (P03/SOT) LIN-UART UART/SIO (P04/SIN) P16/UO P17/UI Port Vcc *1: P12, P14 and P15 are N-ch open drain pins. Vss *2: Software option Port *3: P05, P06, P62 and P63 are high-current pins. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. Document Number: 002-07527 Rev. *A Page 17 of 70 MB95350L Series 11. CPU Core ■ Memory Space The memory space of the MB95350L Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95350L Series are shown below. ■ Memory Maps MB95F352E/F352L MB95F353E/F353L 0000H 0000H I/O 0080H 0090H 0100H Access prohibited RAM 240 bytes I/O 0080H 0090H 0100H Register 0180H MB95F354E/F354L 0000H Access prohibited RAM 496 bytes I/O 0080H 0090H 0100H Register 0200H Access prohibited RAM 496 bytes Register 0200H 0280H 0280H Access prohibited Access prohibited 0F80H 0F80H Extended I/O 1000H B000H 1000H Flash 4 Kbyte Access prohibited F000H FFFFH 0F80H Extended I/O Access prohibited C000H Flash 4 Kbyte Document Number: 002-07527 Rev. *A Access prohibited Extended I/O 1000H Access prohibited B000H C000H Flash 4 Kbyte Access prohibited B000H Access prohibited Flash 20 Kbyte E000H Flash 8 Kbyte FFFFH FFFFH Page 18 of 70 MB95350L Series 12. I/O Map Address Register abbreviation 0000H PDR0 0001H 0002H 0003H R/W Initial value Port 0 data register R/W 00000000B DDR0 Port 0 direction register R/W 00000000B PDR1 Port 1 data register R/W 00000000B DDR1 Port 1 direction register R/W 00000000B 0004H — 0005H WATR 0006H — Register name (Disabled) Oscillation stabilization wait time setting register (Disabled) — — R/W 11111111B — — 0007H SYCC System clock control register R/W 0000X011B 0008H STBC Standby control register R/W 00000XXXB 0009H RSRR Reset source register R/W XXXXXXXXB 000AH TBTC Time-base timer control register R/W 00000000B 000BH WPCR Watch prescaler control register R/W 00000000B 000CH WDTC Watchdog timer control register R/W 00XX0000B 000DH SYCC2 System clock control register 2 R/W XX100011B 000EH to 0015H — — — (Disabled) 0016H PDR6 Port 6 data register R/W 00000000B 0017H DDR6 Port 6 direction register R/W 00000000B 0018H to 0027H — — — (Disabled) 0028H PDRF Port F data register R/W 00000000B 0029H DDRF Port F direction register R/W 00000000B 002AH PDRG Port G data register R/W 00000000B 002BH DDRG Port G direction register R/W 00000000B 002CH PUL0 Port 0 pull-up register R/W 00000000B 002DH to 0034H — — — 0035H PULG Port G pull-up register R/W 00000000B 0036H T01CR1 8/16-bit composite timer 01 status control register 1 ch. 0 R/W 00000000B 0037H T00CR1 8/16-bit composite timer 00 status control register 1 ch. 0 R/W 00000000B 0038H T11CR1 8/16-bit composite timer 11 status control register 1 ch. 1 R/W 00000000B 8/16-bit composite timer 10 status control register 1 ch. 1 R/W 00000000B — — (Disabled) 0039H T10CR1 003AH to 0048H — 0049H EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 00000000B 004AH EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 00000000B 004BH EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 00000000B (Disabled) (Continued) Document Number: 002-07527 Rev. *A Page 19 of 70 MB95350L Series Address Register abbreviation Register name R/W Initial value 004CH, 004DH — (Disabled) — — 004EH LVDR LVD reset voltage selection ID register R/W 00000000B 004FH LVDC LVD interrupt control register R/W X000000XB 0050H SCR LIN-UART serial control register R/W 00000000B 0051H SMR LIN-UART serial mode register R/W 00000000B 0052H SSR LIN-UART serial status register R/W 00001000B 0053H RDR/TDR LIN-UART receive/transmit data register R/W 00000000B 0054H ESCR LIN-UART extended status control register R/W 00000100B 0055H ECCR LIN-UART extended communication control register R/W 000000XXB 0056H SMC10 UART/SIO serial mode control register 1 ch. 0 R/W 00000000B 0057H SMC20 UART/SIO serial mode control register 2 ch. 0 R/W 00100000B 0058H SSR0 UART/SIO serial status and data register ch. 0 R/W 00000001B R/W 00000000B R 00000000B — — 0059H TDR0 UART/SIO serial output data register ch. 0 005AH RDR0 UART/SIO serial input data register ch. 0 005BH to 005FH — 0060H IBCR00 I2C bus control register 0 ch. 0 R/W 00000000B 0061H IBCR10 I2 C R/W 00000000B 0062H IBSR0 I2C bus status register ch. 0 R 00000000B IDDR0 I2 C data register ch. 0 R/W 00000000B IAAR0 I2 C address register ch. 0 R/W 00000000B 0065H ICCR0 I2 C clock control register ch. 0 R/W 00000000B 0066H IBCR01 I2C bus control register 0 ch. 1 R/W 00000000B IBCR11 I2 C bus control register 1 ch. 1 R/W 00000000B IBSR1 I2 C bus status register ch. 1 R 00000000B 0069H IDDR1 2 I C data register ch. 1 R/W 00000000B 006AH IAAR1 I2C address register ch. 1 R/W 00000000B 006BH ICCR1 I2 C R/W 00000000B 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000B 006EH ADDH 8/10-bit A/D converter data register (upper) R/W 00000000B 006FH ADDL 8/10-bit A/D converter data register (lower) R/W 00000000B 0070H — — — 0071H FSR2 Flash memory status register 2 R/W 00000000B 0072H FSR Flash memory status register R/W 000X0000B 0073H SWRE0 Flash memory sector write control register 0 R/W 00000000B 0074H FSR3 R 00000000B 0063H 0064H 0067H 0068H (Disabled) bus control register 1 ch. 0 clock control register ch. 1 (Disabled) Flash memory status register 3 (Continued) Document Number: 002-07527 Rev. *A Page 20 of 70 MB95350L Series Address Register abbreviation Register name R/W Initial value 0075H — (Disabled) — — 0076H WREN Wild register address compare enable register R/W 00000000B 0077H WROR Wild register data test setting register R/W 00000000B — — 0078H — Mirror of register bank pointer (RP) and mirror of direct bank pointer (DP) 0079H ILR0 Interrupt level setting register 0 R/W 11111111B 007AH ILR1 Interrupt level setting register 1 R/W 11111111B 007BH ILR2 Interrupt level setting register 2 R/W 11111111B 007CH ILR3 Interrupt level setting register 3 R/W 11111111B 007DH ILR4 Interrupt level setting register 4 R/W 11111111B 007EH ILR5 Interrupt level setting register 5 R/W 11111111B 007FH — — — 0F80H WRARH0 Wild register address setting register (upper) ch. 0 R/W 00000000B 0F81H WRARL0 Wild register address setting register (lower) ch. 0 R/W 00000000B 0F82H WRDR0 Wild register data setting register ch. 0 R/W 00000000B 0F83H WRARH1 Wild register address setting register (upper) ch. 1 R/W 00000000B 0F84H WRARL1 Wild register address setting register (lower) ch. 1 R/W 00000000B (Disabled) 0F85H WRDR1 Wild register data setting register ch. 1 R/W 00000000B 0F86H WRARH2 Wild register address setting register (upper) ch. 2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (lower) ch. 2 R/W 00000000B 0F88H WRDR2 Wild register data setting register ch. 2 R/W 00000000B 0F89H to 0F91H — — — 0F92H T01CR0 8/16-bit composite timer 01 status control register 0 ch. 0 R/W 00000000B 0F93H T00CR0 8/16-bit composite timer 00 status control register 0 ch. 0 R/W 00000000B 0F94H T01DR 8/16-bit composite timer 01 data register ch. 0 R/W 00000000B (Disabled) 0F95H T00DR 8/16-bit composite timer 00 data register ch. 0 R/W 00000000B 0F96H TMCR0 8/16-bit composite timer 00/01 timer mode control register ch. 0 R/W 00000000B 0F97H T11CR0 8/16-bit composite timer 11 status control register 0 ch. 1 R/W 00000000B 0F98H T10CR0 8/16-bit composite timer 10 status control register 0 ch. 1 R/W 00000000B 0F99H T11DR 8/16-bit composite timer 11 data register ch. 1 R/W 00000000B 0F9AH T10DR 8/16-bit composite timer 10 data register ch. 1 R/W 00000000B 0F9BH TMCR1 8/16-bit composite timer 10/11 timer mode control register ch. 1 R/W 00000000B 0F9CH to 0FBBH — — — (Disabled) (Continued) Document Number: 002-07527 Rev. *A Page 21 of 70 MB95350L Series (Continued) Address Register abbreviation 0FBCH BGR1 0FBDH BGR0 0FBEH 0FBFH 0FC0H to 0FC2H — 0FC3H AIDRL 0FC4H to 0FE3H — 0FE4H CRTH Register name R/W Initial value LIN-UART baud rate generator register 1 R/W 00000000B LIN-UART baud rate generator register 0 R/W 00000000B PSSR0 UART/SIO dedicated baud rate generator prescaler select register ch. 0 R/W 00000000B BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch. 0 R/W 00000000B — — R/W 00000000B — — Main CR clock trimming register (upper) R/W 0XXXXXXXB Main CR clock trimming register (lower) R/W 00XXXXXXB — — (Disabled) A/D input disable register (lower) (Disabled) 0FE5H CRTL 0FE6H, 0FE7H — 0FE8H SYSC System configuration register R/W 11000001B (Disabled) 0FE9H CMCR Clock monitoring control register R/W 00000000B 0FEAH CMDR Clock monitoring data register R 00000000B 0FEBH WDTH Watchdog timer selection ID register (upper) R XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (lower) R XXXXXXXXB 0FEDH — 0FEEH ILSR 0FEFH to 0FFFH — (Disabled) Input level select register (Disabled) — — R/W 00000000B — — R/W access symbols R/W : Readable / Writable R : Read only W : Write only Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is indeterminate. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. Document Number: 002-07527 Rev. *A Page 22 of 70 MB95350L Series 13. Interrupt Source Table Interrupt source Interrupt request number Vector table address Upper Lower Bit name of interrupt level setting register External interrupt ch. 4 IRQ00 FFFAH FFFBH L00 [1:0] External interrupt ch. 5 IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] IRQ04 FFF2H FFF3H L04 [1:0] External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 LVD interrupt UART/SIO ch. 0 8/16-bit composite timer ch. 0 (lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 FFEEH FFEFH L06 [1:0] LIN-UART (reception) IRQ07 FFECH FFEDH L07 [1:0] LIN-UART (transmission) IRQ08 FFEAH FFEBH L08 [1:0] IRQ09 FFE8H FFE9H L09 [1:0] IRQ10 FFE6H FFE7H L10 [1:0] — IRQ11 FFE4H FFE5H L11 [1:0] — IRQ12 FFE2H FFE3H L12 [1:0] — I2C ch. 1 — 8/16-bit composite timer ch. 1 (upper) — I 2C ch. 0 IRQ13 FFE0H FFE1H L13 [1:0] IRQ14 FFDEH FFDFH L14 [1:0] IRQ15 FFDCH FFDDH L15 [1:0] IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] Watch prescaler IRQ20 FFD2H FFD3H L20 [1:0] IRQ21 FFD0H FFD1H L21 [1:0] 8/16-bit composite timer ch. 1 (lower) IRQ22 FFCEH FFCFH L22 [1:0] Flash memory IRQ23 FFCCH FFCDH L23 [1:0] — Priority order of interrupt sources of the same level (occurring simultaneously) High Low Document Number: 002-07527 Rev. *A Page 23 of 70 MB95350L Series 14. Electrical Characteristics 14.1 Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current “L” level maximum output current Symbol Rating Unit Max VCC VSS  0.3 VSS  4.0 V VI1 VSS  0.3 VSS  4.0 V Other than P14 and P15*2 VI2 VSS  0.3 VSS  6.0 V P14 and P15*2 VO VSS  0.3 VSS  4.0 V ICLAMP 2 2 mA Applicable to specific pins*3 |ICLAMP| — 20 mA Applicable to specific pins*3 IOL1 IOL2 — IOLAV1 “L” level average current 15 15 mA 4 — IOLAV2 mA 12 “L” level total maximum output current IOL — 100 mA “L” level total average output current IOLAV — 50 mA “H” level maximum output current IOH1 IOH2 — “H” level average current 15 15 mA 4 IOHAV1 — mA 8 IOHAV2 “H” level total maximum output current IOH — 100 mA “H” level total average output current IOHAV — 50 mA Pd — 320 mW Operating temperature TA 40 85 C Storage temperature Tstg 55 150 C Power consumption Remarks Min *2 Other than P05, P06, P62 and P63 P05, P06, P62 and P63 Other than P05, P06, P62 and P63 Average output current = operating current  operating ratio (1 pin) P05, P06, P62 and P63 Average output current = operating current  operating ratio (1 pin) Total average output current = operating current  operating ratio (Total number of pins) Other than P05, P06, P62 and P63 P05, P06, P62 and P63 Other than P05, P06, P62 and P63 Average output current = operating current  operating ratio (1 pin) P05, P06, P62 and P63 Average output current = operating current  operating ratio (1 pin) Total average output current = operating current  operating ratio (Total number of pins) (Continued) Document Number: 002-07527 Rev. *A Page 24 of 70 MB95350L Series (Continued) *1: The parameter is based on VSS = 0.0 V. *2: VI1, VI2 and VO must not exceed VCC  0.3 V. VI1 and VI2 must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI1 and VI2 ratings. *3: Applicable to the following pins: P00 to P07, P15, P16, P62 to P64, PF0, PF1, PG0 to PG2 ■Use under recommended operating conditions. ■Use with DC voltage (current). ■The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. ■The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. ■When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. ■If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. ■If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ■Do not leave the HV (High Voltage) input pin unconnected. ■Example of a recommended circuit • Input/Output equivalent circuit Protective diode VCC HV(High Voltage) input (0 V to 16 V) P-ch Limiting resistor N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-07527 Rev. *A Page 25 of 70 MB95350L Series 14.2 Recommended Operating Conditions (VSS = 0.0 V) Parameter Power supply voltage Operating temperature Symbol VCC TA Value Unit Remarks Min Max 1.8*1*2*3 3.6 In normal operation, TA = 10C to 85C 2.0 3.6 In normal operation, TA = 40C to 85C 1.5 3.6 Hold condition in stop mode 2.7 3.6 In normal operation 1.5 3.6 Hold condition in stop mode 40 85 5 35 V C Other than on-chip debug mode On-chip debug mode Other than on-chip debug mode On-chip debug mode *1: This value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: This value is initially 2.03 V when the low-voltage detection reset is used. *3: The threshold voltage can be set to 2.03 V, 2.55 V or 3.10 V by using the software. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-07527 Rev. *A Page 26 of 70 MB95350L Series 14.3 DC Characteristics Parameter "H" level input voltage “L” level input voltage Open-drain output application voltage “H” level output voltage “L” level output voltage Input leak current (Hi-Z output leak current) Pull-up resistance Input capacitance Symbol (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Pin name Condition Value Min Typ Max Unit Remarks VIHI1 P04, P16, P17 *1 0.7 VCC — VCC  0.3 V When CMOS input level is selected VIHI2 P14, P15 *1 0.7 VCC — VSS  5.5 V When CMOS input level is selected VIHS1 P00 to P07, P12, P16, P17, P60 to P64, PF0, PF1, PG0 to PG2 *1 0.8 VCC — VCC  0.3 V Hysteresis input VIHS2 P14, P15 *1 0.8 VCC — VSS  5.5 V Hysteresis input VIHM PF2 — 0.7 VCC — VCC  0.3 V Hysteresis input VIL P04, P14 to P17 *1 VSS  0.3 — 0.3 VCC V When CMOS input level is selected VILS P00 to P07, P12, P14 to P17, P62 to P64, PF0, PF1, PG0 to PG2 *1 VSS  0.3 — 0.2 VCC V Hysteresis input VILM PF2 — VSS  0.3 — 0.3 VCC V Hysteresis input VD1 P12 — VSS  0.3 — VSS  5.5 V VD2 P14, P15 — VSS  0.3 — VSS  5.5 V VD3 P16, P17 — VSS  0.3 — VSS  3.6 V In I2C mode VOH1 Output pins other than P05, P06, P12, P62, P63 IOH = 4 mA VCC  0.5 — — V VOH2 P05, P06, P62 and IOH = 8 mA P63 VCC  0.5 — — V VOL1 Output pins other than P05, P06, P62, P63 — — 0.4 V VOL2 P05, P06, P62, P63 IOL = 12 mA — — 0.4 V All input pins 0.0 V < VI < VCC 5 — 5 µA When pull-up resistance is disabled P00 to P07, PG1, PG2 VI = 0 V 25 50 100 k When pull-up resistance is enabled — 5 15 pF ILI RPULL CIN IOL = 4 mA Other than VCC and f = 1 MHz VSS (Continued) Document Number: 002-07527 Rev. *A Page 27 of 70 MB95350L Series (VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Parameter Symbol Pin name Remarks 20 mA Flash memory product (except writing and erasing) 26.2 38 mA Flash memory product (at writing and erasing) — 13.3 23.4 mA At A/D conversion FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) — 5.2 9.6 mA FCL = 32 kHz FMPL = 16 kHz Subclock mode (divided by 2) TA = 25C — 15 35 µA ICCLS FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = 25C — 5 15 µA ICCT FCL = 32 kHz Watch mode Main stop mode TA = 25C — 1 10 µA FCRH = 12.5 MHz FMP = 12.5 MHz Main CR clock mode — 9 15 mA Sub-CR clock mode (divided by 2) TA = 25C — 77 160 µA FCH = 32 MHz Time-base timer mode — 1.1 3 mA Substop mode TA = 25C — 0.1 5 µA FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) ICC ICCS Power supply current*2 Value Unit ICCL VCC (External clock operation) ICCMCR VCC ICCSCR ICCTS ICCH Condition VCC (External clock operation) Min Typ*3 Max — 11.2 — (Continued) Document Number: 002-07527 Rev. *A Page 28 of 70 MB95350L Series (Continued) Parameter (VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Symbol Pin name ILVD Power supply current*2 ICRH VCC ICRL Condition Value Unit Min Typ*3 Max Current consumption for low-voltage detection circuit only — 6.4 32 µA Current consumption for the main CR oscillator — 0.25 0.6 mA Current consumption for the sub-CR oscillator oscillating at 100 kHz — 20 72 µA Remarks *1: The input levels of P04 and P14 to P17 can be switched between “CMOS input level” and “hysteresis input level”. The input level selection register (ILSR) is used to switch between the two input levels. *2: • The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. ■See "AC Characteristics: Clock Timing" for FCH and FCL. ■See "AC Characteristics: Source Clock/Machine Clock" for FMP and FMPL. *3: VCC = 3.0 V, TA = 25C Document Number: 002-07527 Rev. *A Page 29 of 70 MB95350L Series 14.4 AC Characteristics 14.4.1 Clock Timing Parameter (VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Symbol Pin name X0, X1 FCH X0 X0, X1 — Clock frequency FCL X0A, X1A FCRL — X0, X1 tHCYL Clock cycle time Input clock pulse width Input clock rise time and fall time CR oscillation start time Min Typ Max — 1 — 16.25 X1: open 1 — 12 * 1 — 32.5 MHz When the main external clock is MHz used 12.25 12.5 12.75 MHz X0 X0, X1 tLCYL X0A, X1A tWH1 tWL1 X0 tWH2 tWL2 tCR tCF X0, X1 X0A X0 X0, X1 Unit Remarks MHz When the main oscillation circuit is used 9.8 10 10.2 7.84 8 8.16 MHz When the main CR clock is used MHz TA   10 C to  85 C 0.98 1 1.02 MHz 12.1875 12.5 12.8125 MHz 9.75 10 10.25 7.8 8 8.2 0.975 1 1.025 MHz — — 32.768 — kHz When the sub-oscillation circuit or the sub-external clock is used — 50 100 200 kHz When the sub-CR clock is used — 61.5 — 1000 ns When the main oscillation circuit is used X1: open 83.4 — 1000 ns * 30.8 — 1000 ns — — 30.5 — µs X1: open 33.4 — — ns * 12.4 — — ns — — 15.2 — µs X1: open — — 5 ns * — — 5 ns — FCRH — Value Condition — MHz When the main CR clock is used MHz TA   40 C to  10 C When the main external clock is used When the sub-oscillation circuit or the sub-external clock is used When the external clock is used, the duty ratio should range between 40% and 60%. When the external clock is used tCRHWK — — — — 250 µs When the main CR clock is used tCRLWK — — — — 10 µs When the sub-CR clock is used *: The external clock signal is input to X0 and the inverted external clock signal to X1. Document Number: 002-07527 Rev. *A Page 30 of 70 MB95350L Series • Input waveform generated when an external clock (main clock) is used tHCYL tWH1 tWL1 tCR tCF 0.8 VCC 0.8 VCC X0, X1 0.2 VCC 0.2 VCC 0.2 VCC • Figure of main clock input port external connection When a crystal oscillator or a ceramic oscillator is used X0 When the external clock is used When the external clock (X1 is open) is used X0 X1 X1 X0 X1 Open FCH FCH FCH • Input waveform generated when an external clock (subclock) is used tLCYL tWH2 tCR tWL2 tCF 0.8 VCC 0.8 VCC X0A 0.1 VCC 0.1 VCC 0.1 VCC • Figure of subclock input port external connection When a crystal oscillator or a ceramic oscillator is used X0A X1A FCL When the external clock is used X0A X1A Open FCL Document Number: 002-07527 Rev. *A Page 31 of 70 MB95350L Series 14.4.2 Source Clock/Machine Clock Parameter Source clock cycle time*1 Symbol tSCLK Pin name — FSP Source clock frequency — FSPL Machine clock cycle time*2 (minimum instruction execution time) tMCLK Unit — FMPL Remarks Min Typ Max 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 80 — 1000 ns When the main CR clock is used Min: FCRH = 12.5 MHz Max: FCRH = 1 MHz — 61 — µs When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 — 20 — µs When the sub-CR clock is used FCRL = 100 kHz, divided by 2 0.5 — 16.25 MHz When the main oscillation clock is used 1 — 12.5 MHz When the main CR clock is used — 16.384 — kHz When the sub-oscillation clock is used — 50 — kHz When the sub-CR clock is used FCRL = 100 kHz, divided by 2 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 80 — 16000 ns When the main CR clock is used Min: FSP = 12.5 MHz Max: FSP = 1 MHz, divided by 16 61 — 976.5 µs When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 0.031 — 16.25 MHz When the main oscillation clock is used 0.0625 — 12.5 MHz When the main CR clock is used 1.024 — 16.384 kHz When the sub-oscillation clock is used 3.125 — 50 kHz When the sub-CR clock is used FCRL = 100 kHz — FMP Machine clock frequency Value *1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio selection bits (SYCC:DIV1, DIV0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio selection bits (SYCC:DIV1, DIV0]). In addition, a source clock can be selected from the following. • Main clock divided by 2 • Main CR clock • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 Document Number: 002-07527 Rev. *A Page 32 of 70 MB95350L Series • Schematic diagram of the clock generation block Divided by 2 FCH (Main oscillation) FCRH (Main CR clock) FCL (Sub-oscillation) FCRL (Sub-CR clock) FSP/FSPL Divided by 2 (Source clock) Divided by 2 Clock mode select bits (SYCC2: RCS1, RCS0) Division circuit × 1 × 1/4 × 1/8 ×1/16 FMP/FMPL (Machine clock) Machine clock divide ratio select bits (SYCC:DIV1, DIV0) • Operating voltage - Operating frequency (When TA = 40C to 85C) Without the on-chip debug function Operating voltage (V) 3.6 2.7 2.0 ~ 16 kHz 7.5 MHz 16.25 MHz Source clock frequency (FSP/FSPL) Document Number: 002-07527 Rev. *A Page 33 of 70 MB95350L Series • Operating voltage - Operating frequency (When TA = 10C to 85C) Without the on-chip debug function Operating voltage (V) 3.6 2.7 1.8 ~ 16 kHz 5 MHz 16.25 MHz Source clock frequency (FSP/FSPL) • Operating voltage - Operating frequency (When TA = 40C to 85C) With the on-chip debug function Operating voltage (V) 3.6 2.7 ~ 16 kHz 5 MHz 16.25 MHz Source clock frequency (FSP/FSPL) Document Number: 002-07527 Rev. *A Page 34 of 70 MB95350L Series 14.4.3 External Reset Parameter (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Value Symbol Min Max 2 tMCLK*1 RST “L” level pulse width tRSTL Unit Remarks — ns In normal operation Oscillation time of the oscillator*  100 — µs In stop mode, subclock mode, sub-sleep mode, watch mode, and power-on 100 — µs In time-base timer mode 2 *1: See “Source Clock/Machine Clock” for tMCLK. *2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and several ms. • In normal operation tRSTL RST 0.2 VCC 0.2 VCC • In stop mode, subclock mode, subsleep mode, watch mode and power-on tRSTL RST X0 0.2 VCC 0.2 VCC 90% of amplitude Internal operating clock Oscillation time of oscillator Internal reset Document Number: 002-07527 Rev. *A 100 μs Oscillation stabilization wait time Execute instruction Page 35 of 70 MB95350L Series 14.4.4 Power-on Reset Parameter (VSS = 0.0 V, TA = 40C to 85C) Symbol Condition Power supply rising time tR Power supply cutoff time tOFF Value Unit Min Max — — 50 ms — 1 — ms tR Remarks Wait time until power-on tOFF 1.5 V VCC 0.2 V 0.2 V 0.2 V Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 20 mV/ms as shown below. VCC 1.5 V Set the slope of rising to a value below 20 mV/ms. Hold condition in stop mode VSS Document Number: 002-07527 Rev. *A Page 36 of 70 MB95350L Series 14.4.5 Peripheral Input Timing Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Symbol tILIH tIHIL Value Pin name Min INT02 to INT07, EC0, EC1 Max Unit 2 tMCLK* — ns * — ns 2 tMCLK *: See “Source Clock/Machine Clock” for tMCLK. tILIH INT02 to INT07, EC0, EC1 0.8 VCC tIHIL 0.8 VCC 0.2 VCC Document Number: 002-07527 Rev. *A 0.2 VCC Page 37 of 70 MB95350L Series 14.4.6 LIN-UART Timing Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0) (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Parameter Serial clock cycle time Symbol tSCYC Pin name SCK SCK  SOT delay time tSLOVI SCK, SOT Valid SIN  SCK  tIVSHI SCK, SIN SCK  valid SIN hold time tSHIXI SCK, SIN Serial clock “L” pulse width tSLSH Max 5 tMCLK*3 — ns 95 95 ns tMCLK*3  190 — ns 0 — ns — ns *3 *3 tSHSL SCK tSLOVE SCK, SOT Valid SIN  SCK  tIVSHE SCK, SIN SCK, SIN tMCLK External clock operation output pin: CL = 80 pF  1 TTL Unit Min 3 tMCLK SCK  SOT delay time tSHIXE Internal clock operation output pin: CL = 80 pF  1 TTL Value SCK Serial clock “H” pulse width SCK  valid SIN hold time Condition  tR  95 — ns — 2 tMCLK*3  95 ns 190 — ns 3 tMCLK*  95 — ns SCK fall time tF SCK — 10 ns SCK rise time tR SCK — 10 ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “Source Clock/Machine Clock” for tMCLK. Document Number: 002-07527 Rev. *A Page 38 of 70 MB95350L Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOVI 2.4 V SOT 0.8 V tIVSHI tSHIXI 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.8 VCC SCK 0.2 VCC tF 0.2 VCC tR tSLOVE 2.4 V SOT 0.8 V tIVSHE tSHIXE 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC Document Number: 002-07527 Rev. *A Page 39 of 70 MB95350L Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0) (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK  SOT delay time tSHOVI SCK, SOT Valid SIN  SCK  Condition Internal clock operation output pin: CL = 80 pF  1 TTL Value Unit Min Max 5 tMCLK*3 — ns 95 95 ns *3 — ns SCK, SIN SCK  valid SIN hold time tSLIXI SCK, SIN 0 — ns Serial clock “H” pulse width tSHSL SCK 3 tMCLK*3  tR — ns SCK *3 — ns Serial clock “L” pulse width tSLSH SCK  SOT delay time tSHOVE SCK, SOT Valid SIN  SCK  tIVSLE SCK, SIN SCK  valid SIN hold time tSLIXE SCK, SIN tMCLK  190 tIVSLI tMCLK External clock operation output pin: CL = 80 pF  1 TTL  95 — 2 tMCLK *3  95 ns 190 — ns tMCLK*3  95 — ns SCK fall time tF SCK — 10 ns SCK rise time tR SCK — 10 ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “Source Clock/Machine Clock” for tMCLK. Document Number: 002-07527 Rev. *A Page 40 of 70 MB95350L Series • Internal shift clock mode tSCYC 2.4 V 2.4 V SCK 0.8 V tSHOVI 2.4 V SOT 0.8 V tIVSLI tSLIXI 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC • External shift clock mode tSHSL 0.8 VCC tSLSH 0.8 VCC SCK 0.2 VCC tR tF 0.2 VCC 0.2 VCC tSHOVE 2.4 V SOT 0.8 V tIVSLE tSLIXE 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC Document Number: 002-07527 Rev. *A Page 41 of 70 MB95350L Series Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1) (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK  SOT delay time tSHOVI SCK, SOT Valid SIN  SCK  tIVSLI SCK, SIN SCK  valid SIN hold time tSLIXI SCK, SIN SOT  SCK  delay time Value Condition Min Internal clock operation output pin: CL = 80 pF  1 TTL 5 tMCLK*3 — ns 95 95 ns tMCLK*3  190 — ns 0 — SCK, SOT tSOVLI Unit Max — 4 tMCLK* ns 3 ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “Source Clock/Machine Clock” for tMCLK. tSCYC 2.4 V SCK 0.8 V tSOVLI SOT 2.4 V 2.4 V 0.8 V 0.8 V tIVSLI SIN 0.8 V tSHOVI tSLIXI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Document Number: 002-07527 Rev. *A Page 42 of 70 MB95350L Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1) (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK  SOT delay time tSLOVI SCK, SOT Valid SIN  SCK  tIVSHI SCK, SIN SCK  valid SIN hold time tSHIXI SCK, SIN SOT  SCK  delay time tSOVHI SCK, SOT Value Condition Internal clock operation output pin: CL = 80 pF  1 TTL Unit Min Max 5 tMCLK*3 — ns 95 95 ns *3 — ns 0 — ns — 4 tMCLK*3 ns tMCLK  190 *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “Source Clock/Machine Clock” for tMCLK. tSCYC 2.4 V SCK 2.4 V 0.8 V tSOVHI SOT 2.4 V 0.8 V 0.8 V tIVSHI SIN tSLOVI 2.4 V tSHIXI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Document Number: 002-07527 Rev. *A Page 43 of 70 MB95350L Series 14.4.7 Low-voltage Detection Parameter (VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = 40C to 85C) Symbol Value Min Typ Max Unit Remarks Power release voltage 0 VPDL0+ 1.83 1.93 2.03 V At power supply rise Power detection voltage 0 VPDL0- 1.80 1.90 2.00 V At power supply fall Power release voltage 1 VPDL1+ 2.25 2.40 2.55 V At power supply rise Power detection voltage 1 VPDL1- 2.20 2.35 2.50 V At power supply fall Power release voltage 2 VPDL2+ 2.80 2.95 3.10 V At power supply rise Power detection voltage 2 VPDL2- 2.70 2.85 3.00 V At power supply fall Interrupt release voltage 0 VIDL0+ 2.03 2.18 2.33 V At power supply rise Interrupt detection voltage 0 VIDL0- 2.00 2.15 2.30 V At power supply fall Interrupt release voltage 1 VIDL1+ 2.25 2.40 2.55 V At power supply rise Interrupt detection voltage 1 VIDL1- 2.20 2.35 2.50 V At power supply fall Interrupt release voltage 2 VIDL2+ 2.46 2.61 2.76 V At power supply rise Interrupt detection voltage 2 VIDL2- 2.40 2.55 2.70 V At power supply fall Interrupt release voltage 3 VIDL3+ 2.67 2.82 2.97 V At power supply rise Interrupt detection voltage 3 VIDL3- 2.60 2.75 2.90 V At power supply fall Interrupt release voltage 4 VIDL4+ 2.90 3.10 3.30 V At power supply rise Interrupt detection voltage 4 At power supply fall VIDL4- 2.80 3.00 3.20 V Power supply start voltage Voff — — 1.8 V Power supply end voltage Von 3.3 — — V tr 3000 — — µs Power supply voltage change time (at power supply rise) Slope of power supply that the reset release signal generates within the rating (VPDL+/VIDL+) (Continued) Document Number: 002-07527 Rev. *A Page 44 of 70 MB95350L Series (Continued) (VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = 40C to 85C) Parameter Symbol Power supply voltage change time (at power supply fall) Value Unit Remarks — µs Slope of power supply that the reset detection signal generates within the rating (VPDL-/VIDL-) — 300 µs — — 150 µs tdi1 10 — 200 µs tdi2 — — 150 µs Min Typ Max tf 3000 — Power reset release delay time tdp1 10 Power reset detection delay time tdp2 Interrupt reset release delay time Interrupt reset detection delay time VCC Von Voff time VCC tf tr VPDL+/VIDL+ VPDL-/VIDL- Reset/Interrupt time tdp2/tdi2 Document Number: 002-07527 Rev. *A tdp1/tdi1 Page 45 of 70 MB95350L Series 14.4.8 I2C Timing (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Parameter Symbol SCL clock frequency Pin name Condition Value StanFast-mode dard-mode Min Max Min Max Unit fSCL SCL0, SCL1 0 100 0 400 kHz tHD;STA SCL0, SCL1, SDA0, SDA1 4.0 — 0.6 — µs SCL clock “L” width tLOW SCL0, SCL1 4.7 — 1.3 — µs SCL clock “H” width tHIGH SCL0, SCL1 4.0 — 0.6 — µs (Repeated) START condition hold time SCL  SDA  tSU;STA SCL0, SCL1, SDA0, SDA1 4.7 — 0.6 — µs Data hold time SCL  SDA  tHD;DAT SCL0, SCL1, SDA0, SDA1 0 3.45*2 0 0.9*3 µs Data setup time SDA  SCL  tSU;DAT SCL0, SCL1, SDA0, SDA1 0.25 — 0.1 — µs STOP condition setup time SCL   SDA  tSU;STO SCL0, SCL1, SDA0, SDA1 4 — 0.6 — µs tBUF SCL0, SCL1, SDA0, SDA1 4.7 — 1.3 — µs (Repeated) START condition hold time SDA  SCL  Bus free time between STOP condition and START condition R = 1.7 k, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL0/1 and SDA0/1 lines, and C the load capacitor of the SCL0/1 and SDA0/1 lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at “L” (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT  250 ns is fulfilled. tWAKEUP SDA0, SDA1 tLOW SCL0, SCL1 tHD;DAT tHD;STA tHIGH tSU;DAT fSCL tHD;STA tSU;STA tBUF tSU;STO (Continued) Document Number: 002-07527 Rev. *A Page 46 of 70 MB95350L Series (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Parameter Symbol Pin name Condition 2 Value* Min Max Unit Remarks SCL clock “L” width tLOW SCL0, SCL1 (2  nm/2)tMCLK  20 — ns Master mode SCL clock “H” width tHIGH SCL0, SCL1 (nm/2)tMCLK  20 (nm/2)tMCLK  20 ns Master mode START condition tHD;STA hold time SCL0, SCL1, SDA0, SDA1 (1  nm/2)tMCLK  20 (1  nm)tMCLK  20 ns Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. STOP condition setup time SCL0, SCL1, SDA0, SDA1 (1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode SCL0, SCL1, START condition tSU;STA SDA0, setup time SDA1 (1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode (2 nm  4)tMCLK  20 — ns 3 tMCLK  20 — ns Master mode ns Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. ns Minimum value is applied to interrupt at 9th SCL. Maximum value is applied to the interrupt at the 8th SCL. Bus free time between STOP condition and START condition Data hold time Data setup time Setup time between clearing interrupt and SCL rising tSU;STO tBUF SCL0, SCL1, SDA0, SDA1 tHD;DAT SCL0, SCL1, SDA0, SDA1 tSU;DAT tSU;INT R = 1.7 k, C = 50 pF*1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1 (2  nm/2)tMCLK  20 (nm/2)tMCLK  20 (1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 (Continued) Document Number: 002-07527 Rev. *A Page 47 of 70 MB95350L Series (Continued) Parameter (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Symbol Pin name Condition Value*2 Min Max Unit Remarks SCL clock “L” width tLOW SCL0, SCL1 4 tMCLK  20 — ns At reception SCL clock “H” width tHIGH SCL0, SCL1 4 tMCLK  20 — ns At reception START condition detection tHD;STA SCL0, SCL1, SDA0, SDA1 2 tMCLK  20 — ns Undetected when 1 tMCLK is used at reception STOP condition detection tSU;STO SCL0, SCL1, SDA0, SDA1 2 tMCLK  20 — ns Undetected when 1 tMCLK is used at reception RESTART condition detection condition tSU;STA SCL0, SCL1, SDA0, SDA1 2 tMCLK  20 — ns Undetected when 1 tMCLK is used at reception tBUF SCL0, SCL1, SDA0, SDA1 2 tMCLK  20 — ns At reception Data hold time tHD;DAT SCL0, SCL1, SDA0, SDA1 2 tMCLK  20 — ns At slave transmission mode Data setup time tSU;DAT SCL0, SCL1, SDA0, SDA1 tLOW  3 tMCLK  20 — ns At slave transmission mode Data hold time tHD;DAT SCL0, SCL1, SDA0, SDA1 0 — ns At reception Data setup time tSU;DAT SCL0, SCL1, SDA0, SDA1 tMCLK  20 — ns At reception SDA  SCL (at wakeup function) tWAKEUP SCL0, SCL1, SDA0, SDA1 Oscillation stabilization wait time 2 tMCLK  20 — ns Bus free time R = 1.7 k, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL0/1 and SDA0/1 lines, and C the load capacitor of the SCL0/1 and SDA0/1 lines. See “Source Clock/Machine Clock” for tMCLK. m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0). n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0). The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the CS4 to CS0 bits in the ICCR0 register. • Standard-mode: m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 10 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < tMCLK  1 MHz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK  2 MHz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK  4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK  10 MHz • Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 10 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < tMCLK  4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK  8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK  10 MHz *2: • • • • Document Number: 002-07527 Rev. *A Page 48 of 70 MB95350L Series 14.4.9 UART/SIO, Serial I/O Timing Parameter (VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = 40C to 85C) Symbol Pin name Serial clock cycle time tSCYC UCK UCK  UO time tSLOV UCK, UO Valid UI  UCK  tIVSH UCK, UI UCK  valid UI hold time tSHIX Serial clock “H” pulse width Serial clock “L” pulse width UCK  UO time tSLOV UCK, UO Valid UI  UCK  tIVSH UCK  valid UI hold time tSHIX Condition Value Min Max Unit 4 tMCLK* — ns 190 190 ns 2 tMCLK* — ns UCK, UI 2 tMCLK* — ns tSHSL UCK 4 tMCLK* — ns tSLSH UCK 4 tMCLK* — ns — 190 ns UCK, UI 2 tMCLK* — ns UCK, UI 2 tMCLK* — ns Internal clock operation External clock operation *: See “Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC 2.4 V UCK 0.8 V 0.8 V tSLOV 2.4 V UO 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC UI 0.2 VCC 0.2 VCC Document Number: 002-07527 Rev. *A Page 49 of 70 MB95350L Series • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC UCK 0.2 VCC 0.2 VCC tSLOV 2.4 V UO 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC UI 0.2 VCC 0.2 VCC Document Number: 002-07527 Rev. *A Page 50 of 70 MB95350L Series 14.5 A/D Converter 14.5.1 A/D Converter Electrical Characteristics Parameter Value Symbol Linearity error Max — — 10 bit 3 — 3 LSB 2.5 — 2.5 LSB 1.9 — 1.9 LSB VSS  1.5 LSB VSS  0.5 LSB VSS  2.5 LSB V 2.7 V VCC 3.6 V VSS  0.5 LSB VSS  1.5 LSB VSS  3.5 LSB V 1.8 V VCC