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MB95F478HPMC1-G-SNE2

MB95F478HPMC1-G-SNE2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    LQFP-64

  • 描述:

    IC MCU 8BIT 60KB FLASH 64LQFP

  • 数据手册
  • 价格&库存
MB95F478HPMC1-G-SNE2 数据手册
The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB95410H/470H Series New 8FX 8-bit Microcontrollers MB95410H/470H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. Features F2MC-8FX CPU core 8/10-bit A/D converter Instruction set optimized for controllers ■ ■ Multiplication and division instructions ■ 16-bit arithmetic operations ■ Bit test branch instructions ■ Bit manipulation instructions, etc. LCD controller (LCDC) Clock ■ Selectable main clock source Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) ❐ External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) ❐ Main CR clock (1/8/10/12.5 MHz 2%, maximum machine clock frequency: 12.5 MHz) ❐ Main PLL clock (up to 16.25 MHz, maximum machine clock frequency: 16.25 MHz) ❐ ■ Selectable subclock source ❐ Sub-OSC clock (32.768 kHz) ❐ External clock (32.768 kHz) ❐ Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz) Timer ■ 8/16-bit composite timer  2 channels ■ 8/16-bit PPG  2 channels ■ 16-bit reload timer  1 channel ■ Event counter  1 channel ■ Time-base timer  1 channel ■ Watch prescaler  1 channel 8-bit or 10-bit resolution can be selected ■ On MB95F414H/F414K/F416H/F416K/F418H/F418K, LCD output can be selected from 40 SEG  4 COM to 36 SEG  8 COM. ■ On MB95F474H/F474K/F476H/F476K/F478H/F478K, LCD output can be selected from 32 SEG  4 COM to 28 SEG  8 COM. ■ Internal divider resistor whose resistance value can be selected from 10 k or 100 k through software ■ Interrupt in sync with the LCD module frame frequency ■ Blinking function ■ Inverted display function Low power consumption (standby) modes ■ Stop mode ■ Sleep mode ■ Watch mode ■ Time-base timer mode I/O port ■ MB95F414H/F416H/F418H (maximum no. of I/O ports: 74) General-purpose I/O ports (N-ch open drain) :3 ❐ General-purpose I/O ports (CMOS I/O) : 71 ❐ ■ MB95F414K/F416K/F418K (maximum no. of I/O ports: 75) General-purpose I/O ports (N-ch open drain) :4 ❐ General-purpose I/O ports (CMOS I/O) : 71 ❐ UART-SIO ■ ■ Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer ■ Full duplex double buffer MB95F474H/F476H/F478H (maximum no. of I/O ports: 58) General-purpose I/O ports (N-ch open drain) :3 ❐ General-purpose I/O ports (CMOS I/O) : 55 ❐ ■ MB95F474K/F476K/F478K (maximum no. of I/O ports: 59) General-purpose I/O ports (N-ch open drain) :4 ❐ General-purpose I/O ports (CMOS I/O) : 55 ❐ I2C Built-in wake-up function On-chip debug External interrupt ■ 1-wire serial control ■ Serial writing supported (asynchronous mode) ■ Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ■ Can be used to wake up the device from different low power consumption (standby) modes Cypress Semiconductor Corporation Document Number: 002-07475 Rev. *B • Hardware/software watchdog timer ■ Built-in hardware watchdog timer ■ Built-in software watchdog timer 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 24, 2017 MB95410H/470H Series Low-voltage detection reset circuit Dual operation Flash memory Built-in low-voltage detector The program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. Clock supervisor counter Built-in clock supervisor counter function Programmable port input voltage level Flash memory security function Protects the content of the Flash memory CMOS input level / hysteresis input level Document Number: 002-07475 Rev. *B Page 2 of 85 MB95410H/470H Series Contents Product Line-up ................................................................ 4 Oscillation Stabilization Wait Time ................................. 8 Packages And Corresponding Products ........................ 8 Differences among Products and Notes on Product Selection ........................................................ 9 Pin Assignment .............................................................. 10 Pin Description (MB95410H Series) .............................. 12 Pin Description (MB95470H Series) .............................. 18 I/O Circuit Type ............................................................... 23 Notes on Device Handling ............................................. 28 Pin Connection ............................................................... 28 Block Diagram (MB95410H Series) ............................... 30 Block Diagram (MB95470H Series) ............................... 31 CPU Core ......................................................................... 32 I/O Map (MB95410H Series) ........................................... 33 Document Number: 002-07475 Rev. *B I/O Map (MB95470H Series) ........................................... 39 Interrupt Source Table ................................................... 45 Electrical Characteristics ............................................... 46 Absolute Maximum Ratings ....................................... 46 Recommended Operating Conditions ....................... 48 DC Characteristics .................................................... 49 AC Characteristics ..................................................... 53 A/D Converter ............................................................ 67 Flash Memory Program/Erase Characteristics .......... 71 Sample Characteristics .................................................. 72 Mask Options .................................................................. 78 Ordering Information ...................................................... 79 Package Dimension ........................................................ 80 Major Changes ................................................................ 83 Document History ........................................................... 84 Page 3 of 85 MB95410H/470H Series 1. Product Line-up MB95410H Series Part number MB95F414H Package Type Clock supervisor counter Program ROM capacity RAM capacity Low-voltage detection reset Reset input MB95F416H MB95F418H MB95F414K MB95F416K MB95F418K Flash memory product It supervises the main clock oscillation. 20 Kbyte 36 Kbyte 60 Kbyte 20 Kbyte 36 Kbyte 60 Kbyte 496 bytes 1008 bytes 2032 bytes 496 bytes 1008 bytes 2032 bytes No Yes Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 75 • I/O ports (Max) : 74 General-purpose • CMOS I/O : 71 • CMOS I/O : 71 I/O • N-ch open drain :4 • N-ch open drain : 3 Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/software Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. 1 channel • Master/Slave sending and receiving • Bus error function and arbitration function I2C • Detecting transmitting direction function • Start condition repeated generation and detection functions • Built-in wake-up function 3 channels • Data transfer with UART/SIO is enabled. • It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error UART/SIO detection function. • It uses the NRZ type transfer format. • LSB-first data transfer and MSB-first data transfer are available to use. • Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer is enabled. 8 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. (Continued) Document Number: 002-07475 Rev. *B Page 4 of 85 MB95410H/470H Series (Continued) Part number MB95F414H MB95F416H MB95F418H MB95F414K MB95F416K MB95F418K Package 2 channels 8/16-bit composite • Each timer can be configured as an "8-bit timer  2 channels" or a "16-bit timer  1 channel". • It has built-in timer function, PWC function, PWM function and input capture function. timer • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. • COM output: 4 or 8 (selectable) • SEG output: 36 or 40 (selectable) - If the number of COM outputs is 4, the maximum number of SEG outputs is 40, and the maximum number of pixels that can be displayed 160 (440). - If the number of COM outputs is 8, the maximum number of SEG outputs is 36, and the maximum number of pixels that can be displayed 288 (836). LCD controller • LCD drive power supply (bias) pins: 5 (Max) (LCDC) • Duty LCD mode • LCD standby mode • Blinking function • Internal divider resistor whose resistance value can be selected from 10 k or 100 k through software • Interrupt in sync with the LCD module frame frequency • Inverted display function 1 channel • Two clock modes and two counter operating modes can be selected 16-bit reload timer • Square waveform output • Count clock: it can be selected from internal clocks (seven types) and external clocks. • Counter operating mode: reload mode or one-shot mode can be selected By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter function can be Event counter implemented. When the event counter function is used, the 16-bit reload timer and the 8/16-bit composite timer ch. 1 are unavailable. 2 channels 8/16-bit PPG • Each channel of the PPG can be used as “8-bit PPG  2 channels” or “16-bit PPG  1 channel” • Counter operating clock: Eight selectable clock sources • Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when the clock source is 1 second and the counter value is to 60) 8 channels External interrupt • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) • It can be used to wake up the device from the standby mode. • 1-wire serial control On-chip debug • It supports serial writing. (asynchronous mode) Eight different time intervals can be selected. Watch prescaler (62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s) • It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Number of program/erase cycles: 100000 • Data retention time: 20 years • Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode Package FPT-80P-M37 Document Number: 002-07475 Rev. *B Page 5 of 85 MB95410H/470H Series MB95470H Series Part number MB95F474H Package Type Clock supervisor counter Program ROM capacity RAM capacity Low-voltage detection reset Reset input MB95F476H MB95F478H MB95F474K MB95F476K MB95F478K Flash memory product It supervises the main clock oscillation. 20 Kbyte 36 Kbyte 60 Kbyte 20 Kbyte 36 Kbyte 60 Kbyte 496 bytes 1008 bytes 2032 bytes 496 bytes 1008 bytes 2032 bytes No Yes Dedicated Selected through software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 59 • I/O ports (Max) : 58 General-purpose • CMOS I/O : 55 • CMOS I/O : 55 I/O • N-ch open drain : 4 • N-ch open drain :3 Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/software Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. 1 channel • Master/Slave sending and receiving • Bus error function and arbitration function I2C • Detecting transmitting direction function • Start condition repeated generation and detection functions • Built-in wake-up function 3 channels • Data transfer with UART/SIO is enabled. • It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error UART/SIO detection function. • It uses the NRZ type transfer format. • LSB-first data transfer and MSB-first data transfer are available to use. • Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer is enabled. 8 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 2 channels 8/16-bit composite • Each timer can be configured as an "8-bit timer  2 channels" or a "16-bit timer  1 channel". • It has built-in timer function, PWC function, PWM function and input capture function. timer • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. (Continued) Document Number: 002-07475 Rev. *B Page 6 of 85 MB95410H/470H Series (Continued) Part number MB95F474H MB95F476H MB95F478H MB95F474K MB95F476K MB95F478K Package • COM output: 4 or 8 (selectable) • SEG output: 28 or 32 (selectable) - If the number of COM outputs is 4, the maximum number of SEG outputs is 32, and the maximum number of pixels that can be displayed 128 (432). - If the number of COM outputs is 8, the maximum number of SEG outputs is 28, and the maximum number of pixels that can be displayed 224 (828). LCD controller • LCD drive power supply (bias) pins: 4 (Max) (LCDC) • Duty LCD mode • LCD standby mode • Blinking function • Internal divider resistor whose resistance value can be selected from 10 k or 100 k through software • Inverted display function 1 channel • Two clock modes and two counter operating modes can be selected 16-bit reload timer • Square waveform output • Count clock: it can be selected from internal clocks (seven types) and external clocks. • Counter operating mode: reload mode or one-shot mode can be selected By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter function can be Event counter implemented. When the event counter function is used, the 16-bit reload timer and the 8/16-bit composite timer ch. 1 are unavailable. 2 channels 8/16-bit PPG • Each channel of the PPG can be used as “8-bit PPG  2 channels” or “16-bit PPG  1 channel“ • Counter operating clock: Eight selectable clock sources • Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when the clock source is 1 second and the counter value is to 60) 8 channels External interrupt Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) It can be used to wake up the device from the standby mode. • 1-wire serial control On-chip debug • It supports serial writing. (asynchronous mode) Eight different time intervals can be selected. Watch prescaler (62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s) • It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Number of program/erase cycles: 100000 • Data retention time: 20 years • Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode FPT-64P-M38 Package FPT-64P-M39 Document Number: 002-07475 Rev. *B Page 7 of 85 MB95410H/470H Series 2. Oscillation Stabilization Wait Time The main CR clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum value. Oscillation stabilization wait time Remarks (210  2) / FCRH Approx. 128 µs (when the main CR clock is 8 MHz) The main PLL clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum value. Oscillation stabilization wait time Remarks (214  2) / FCH Approx. 14.1 ms (when the main PLL clock is 4 MHz) 3. Packages And Corresponding Products Part number MB95F414H MB95F416H MB95F418H Package FPT-80P-M37 MB95F414K MB95F416K MB95F418K MB95F474K MB95F476K MB95F478K O Part number MB95F474H Package FPT-64P-M38 FPT-64P-M39 MB95F476H MB95F478H O O O: Available Document Number: 002-07475 Rev. *B Page 8 of 85 MB95410H/470H Series 4. Differences among Products and Notes on Product Selection Current consumption When using the on-chip debug function, take account of the current consumption of flash erase/write. For details of current consumption, see “17. Electrical Characteristics”. Package For details of information on each package, see “3. Packages And Corresponding Products” and “21. Package Dimension”. Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of the operating voltage, see “17. Electrical Characteristics”. On-chip debug function The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For details of the connection method, refer to “Chapter 31 Example Of Serial Programming Connection” in the hardware manual of the MB95410H/470H Series. Document Number: 002-07475 Rev. *B Page 9 of 85 MB95410H/470H Series P61/SEG11 P62/SEG12 P63/SEG13 P64/SEG14 P65/SEG15 P66/SEG16 P67/SEG17 P43/SEG18 P42/SEG19 P41/SEG20 P40/SEG21 PE0/SEG22 PE1/SEG23 PE2/SEG24 PE3/SEG25 PE4/SEG26 PE5/SEG27/TO11 PE6/SEG28/TO10 PE7/SEG29/EC1 AVss 5. Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVcc 1 60 P60/SEG10 P07/INT07/AN07/SEG30 2 59 PC7/SEG09 P06/INT06/AN06/SEG31 3 58 PC6/SEG08 P05/INT05/AN05/SEG32/UCK1 4 57 PC5/SEG07 P04/INT04/AN04/SEG33/UI1 5 56 PC4/SEG06 P03/INT03/AN03/SEG34/UO1 6 55 PC3/SEG05 P02/INT02/AN02/SEG35/UCK2 7 54 PC2/SEG04 P01/INT01/AN01/SEG36/UI2 8 53 PC1/SEG03 P00/INT00/AN00/UO2 9 52 PC0/SEG02 P16/PPG10 10 51 PB1/SEG01 P15/PPG11 11 50 PB0/SEG00 P14/UCK0 12 49 P17/CMPO P13/ADTG 13 48 PF2/RST P12/DBG 14 47 Vcc P11/UO0 15 46 PG1/X0A P10/UI0 16 45 PG2/X1A P53/TO0 17 44 C P52/TI0/TO00 18 43 PF0/X0 P51/EC0 19 42 PF1/X1 P50/TO01 20 41 Vss (TOP VIEW) MB95410H Series (FPT-80P-M37) PA7/COM7 PA6/COM6 PA5/COM5 PA4/COM4 PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0 PB4/SEG39 PB3/SEG38 PB2/SEG37 P94/V0 P93/V1 P92/V2 P91/V3 P90/V4 P20/PPG00/CMPN P21/PPG01/CMPP P22/SCL P23/SDA 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (Continued) Document Number: 002-07475 Rev. *B Page 10 of 85 MB95410H/470H Series P61/SEG07 P62/SEG08 P63/SEG09 P64/SEG10 P65/SEG11 P66/SEG12 P67/SEG13 PE0/SEG14 PE1/SEG15 PE2/SEG16 PE3/SEG17 PE4/SEG18 PE5/SEG19/TO11 PE6/SEG20/TO10 PE7/SEG21/EC1 AVss (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVcc 1 48 P60/SEG06 P07/INT07/AN07/SEG22 2 47 PC3/SEG05 P06/INT06/AN06/SEG23 3 46 PC2/SEG04 P05/INT05/AN05/SEG24/UCK1 4 45 PC1/SEG03 P04/INT04/AN04/SEG25/UI1 5 44 PC0/SEG02 P03/INT03/AN03/SEG26/UO1 6 43 PB1/SEG01 42 PB0/SEG00 41 P17/CMPO 40 PF2/RST P02/INT02/AN02/SEG27/UCK2 7 P01/INT01/AN01/SEG28/TO00/UI2 8 P00/INT00/AN00/SEG29/UO2 9 (TOP VIEW) MB95470H Series (FPT-64P-M38) (FPT-64P-M39) P16/SEG30/PPG10 10 39 Vcc P15/SEG31/PPG11 11 38 PG1/X0A P14/UCK0/EC0/TI0 12 37 PG2/X1A P13/ADTG/TO01 13 36 C P12/DBG 14 35 PF0/X0 P11/UO0 15 34 PF1/X1 P10/UI0/TO0 16 33 Vss Document Number: 002-07475 Rev. *B PA7/COM7 PA6/COM6 PA5/COM5 PA4/COM4 PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0 P93/V1 P92/V2 P91/V3 P90/V4 P21/PPG01/CMPP P20/PPG00/CMPN P22/SCL P23/SDA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Page 11 of 85 MB95410H/470H Series 6. Pin Description (MB95410H Series) Pin no. Pin name I/O circuit type* 1 AVCC — P07 2 INT07 AN07 S AN06 5 S 8 A/D analog input pin P05 General-purpose I/O port INT05 External interrupt input pin AN05 S A/D analog input pin SEG32 LCDC SEG output pin UCK1 UART/SIO ch. 1 clock I/O pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 V A/D analog input pin LCDC SEG output pin UI1 UART/SIO ch. 1 data input pin P03 General-purpose I/O port INT03 External interrupt input pin AN03 S SEG34 7 External interrupt input pin LCDC SEG output pin SEG33 6 A/D analog input pin General-purpose I/O port SEG31 4 External interrupt input pin LCDC SEG output pin P06 INT06 A/D converter power supply pin General-purpose I/O port SEG30 3 Function A/D analog input pin LCDC SEG output pin UO1 UART/SIO ch. 1 data output pin P02 General-purpose I/O port INT02 External interrupt input pin AN02 S A/D analog input pin SEG35 LCDC SEG output pin UCK2 UART/SIO ch. 2 clock I/O pin P01 General-purpose I/O port INT01 External interrupt input pin AN01 V SEG36 UI2 A/D analog input pin LCDC SEG output pin UART/SIO ch. 2 data input pin (Continued) Document Number: 002-07475 Rev. *B Page 12 of 85 MB95410H/470H Series Pin no. Pin name I/O circuit type* P00 9 INT00 AN00 General-purpose I/O port W UO2 10 11 12 13 14 15 16 17 P16 PPG10 P15 PPG11 P14 UCK0 P13 ADTG P12 DBG P11 UO0 P10 UI0 P53 TO0 TI0 Y Y H H D H G H 20 21 22 P51 EC0 P50 TO01 P23 SDA P22 SCL H PPG01 H H I I T General-purpose I/O port 8/16-bit PPG ch. 1 output pin General-purpose I/O port UART/SIO ch. 0 clock I/O pin General-purpose I/O port A/D trigger input (ADTG) pin General-purpose I/O port DBG input pin General-purpose I/O port UART/SIO ch. 0 data output pin General-purpose I/O port UART/SIO ch. 0 data input pin General-purpose I/O port 16-bit reload timer output pin 16-bit reload timer input pin General-purpose I/O port 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port 8/16-bit composite timer ch. 0 output pin General-purpose I/O port I2C data I/O pin General-purpose I/O port I2C clock I/O pin 8/16-bit PPG ch. 0 output pin Voltage comparator input pin P20 PPG00 8/16-bit PPG ch. 1 output pin General-purpose I/O port CMPP 24 General-purpose I/O port 8/16-bit composite timer ch. 0 output pin P21 23 A/D analog input pin General-purpose I/O port TO00 19 External interrupt input pin UART/SIO ch. 2 data output pin P52 18 Function General-purpose I/O port T CMPN 8/16-bit PPG ch. 0 output pin Voltage comparator input pin (Continued) Document Number: 002-07475 Rev. *B Page 13 of 85 MB95410H/470H Series Pin no. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin name P90 V4 P91 V3 P92 V2 P93 V1 P94 V0 PB2 SEG37 PB3 SEG38 PB4 SEG39 PA0 COM0 PA1 COM1 PA2 COM2 PA3 COM3 PA4 COM4 PA5 COM5 PA6 COM6 PA7 COM7 VSS PF1 X1 PF0 X0 I/O circuit type* R R R R R M M M M M M M M M M M — B B Function General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin Power supply pin (GND) General-purpose I/O port Main clock oscillation pin General-purpose I/O port Main clock oscillation pin (Continued) Document Number: 002-07475 Rev. *B Page 14 of 85 MB95410H/470H Series Pin no. Pin name I/O circuit type* 44 C — 45 46 47 PG2 X1A PG1 X0A VCC C C — PF2 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 RST P17 CMPO PB0 SEG00 PB1 SEG01 PC0 SEG02 PC1 SEG03 PC2 SEG04 PC3 SEG05 PC4 SEG06 PC5 SEG07 PC6 SEG08 PC7 SEG09 P60 SEG10 P61 SEG11 P62 SEG12 Function Capacitor connection pin General-purpose I/O port Subclock oscillation pin (32 kHz) General-purpose I/O port Subclock oscillation pin (32 kHz) Power supply pin General-purpose I/O port A H M M M M M M M M M M M M M Reset pin Dedicate reset pin for MB95F414H/F416H/F418H General-purpose I/O port Voltage comparator output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin (Continued) Document Number: 002-07475 Rev. *B Page 15 of 85 MB95410H/470H Series Pin no. 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Pin name P63 SEG13 P64 SEG14 P65 SEG15 P66 SEG16 P67 SEG17 P43 SEG18 P42 SEG19 P41 SEG20 P40 SEG21 PE0 SEG22 PE1 SEG23 PE2 SEG24 PE3 SEG25 PE4 SEG26 I/O circuit type* M M M M M M M M M M M M M M PE5 77 78 SEG27 Function General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port M LCDC SEG output pin TO11 8/16-bit composite timer ch. 1 output pin PE6 General-purpose I/O port SEG28 M TO10 LCDC SEG output pin 8/16-bit composite timer ch. 1 output pin (Continued) Document Number: 002-07475 Rev. *B Page 16 of 85 MB95410H/470H Series (Continued) Pin no. Pin name I/O circuit type* PE7 79 SEG29 General-purpose I/O port M EC1 80 AVSS Function LCDC SEG output pin 8/16-bit composite timer ch. 1 clock input pin — A/D converter power supply pin (GND) *: For the I/O circuit types, see “8. I/O Circuit Type”. Document Number: 002-07475 Rev. *B Page 17 of 85 MB95410H/470H Series 7. Pin Description (MB95470H Series) Pin no. Pin name I/O circuit type* 1 AVCC — P07 2 INT07 AN07 S AN06 5 S 8 A/D analog input pin P05 General-purpose I/O port INT05 External interrupt input pin AN05 S A/D analog input pin SEG24 LCDC SEG output pin UCK1 UART/SIO ch. 1 clock I/O pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 V A/D analog input pin LCDC SEG output pin UI1 UART/SIO ch. 1 data input pin P03 General-purpose I/O port INT03 External interrupt input pin AN03 S SEG26 7 External interrupt input pin LCDC SEG output pin SEG25 6 A/D analog input pin General-purpose I/O port SEG23 4 External interrupt input pin LCDC SEG output pin P06 INT06 A/D converter power supply pin General-purpose I/O port SEG22 3 Function A/D analog input pin LCDC SEG output pin UO1 UART/SIO ch. 1 data output pin P02 General-purpose I/O port INT02 External interrupt input pin AN02 S A/D analog input pin SEG27 LCDC SEG output pin UCK2 UART/SIO ch. 2 clock I/O pin P01 General-purpose I/O port INT01 External interrupt input pin AN01 SEG28 V TO00 UI2 A/D analog input pin LCDC SEG output pin 8/16-bit composite timer ch. 0 output pin UART/SIO ch. 2 data input pin (Continued) Document Number: 002-07475 Rev. *B Page 18 of 85 MB95410H/470H Series Pin no. 9 Pin name I/O circuit type* P00 General-purpose I/O port INT00 External interrupt input pin AN00 S SEG29 10 UO2 UART/SIO ch. 2 data output pin P16 General-purpose I/O port SEG30 M SEG31 General-purpose I/O port M PPG11 13 EC0 General-purpose I/O port H 15 P13 General-purpose I/O port ADTG H P12 DBG P11 UO0 UI0 18 P23 SDA P22 SCL D H PPG01 G I I General-purpose I/O port UART/SIO ch. 0 data output pin UART/SIO ch. 0 data input pin General-purpose I/O port I2C data I/O pin General-purpose I/O port I2C clock I/O pin General-purpose I/O port T 8/16-bit PPG ch. 0 output pin Voltage comparator input pin P20 PPG00 DBG input pin 16-bit reload timer output pin CMPP 20 General-purpose I/O port General-purpose I/O port P21 19 A/D trigger input (ADTG) pin 8/16-bit composite timer ch. 0 output pin TO0 17 8/16-bit composite timer ch. 0 clock input pin 16-bit reload timer input pin P10 16 UART/SIO ch. 0 clock I/O pin TI0 TO01 14 LCDC SEG output pin 8/16-bit PPG ch. 1 output pin P14 UCK0 LCDC SEG output pin 8/16-bit PPG ch. 1 output pin P15 12 A/D analog input pin LCDC SEG output pin PPG10 11 Function General-purpose I/O port T CMPN 8/16-bit PPG ch. 0 output pin Voltage comparator input pin (Continued) Document Number: 002-07475 Rev. *B Page 19 of 85 MB95410H/470H Series Pin no. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin name P90 V4 P91 V3 P92 V2 P93 V1 PA0 COM0 PA1 COM1 PA2 COM2 PA3 COM3 PA4 COM4 PA5 COM5 PA6 COM6 PA7 COM7 VSS PF1 X1 PF0 X0 C PG2 X1A PG1 X0A VCC I/O circuit type* R R R R M M M M M M M M — B B — C C — PF2 40 RST Function General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC drive power supply pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin General-purpose I/O port LCDC COM output pin Power supply pin (GND) General-purpose I/O port Main clock oscillation pin General-purpose I/O port Main clock oscillation pin Capacitor connection pin General-purpose I/O port Subclock oscillation pin (32 kHz) General-purpose I/O port Subclock oscillation pin (32 kHz) Power supply pin General-purpose I/O port A Reset pin Dedicated reset pin for MB95F474H/F476H/F478H (Continued) Document Number: 002-07475 Rev. *B Page 20 of 85 MB95410H/470H Series Pin no. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Pin name P17 CMPO PB0 SEG00 PB1 SEG01 PC0 SEG02 PC1 SEG03 PC2 SEG04 PC3 SEG05 P60 SEG06 P61 SEG07 P62 SEG08 P63 SEG09 P64 SEG10 P65 SEG11 P66 SEG12 P67 SEG13 PE0 SEG14 PE1 SEG15 I/O circuit type* H M M M M M M M M M M M M M M M M Function General-purpose I/O port Voltage comparator output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin (Continued) Document Number: 002-07475 Rev. *B Page 21 of 85 MB95410H/470H Series (Continued) Pin no. 58 59 60 Pin name PE2 SEG16 PE3 SEG17 PE4 SEG18 I/O circuit type* M M M PE5 61 62 63 SEG19 General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port LCDC SEG output pin General-purpose I/O port M LCDC SEG output pin TO11 8/16-bit composite timer ch. 1 output pin PE6 General-purpose I/O port SEG20 M LCDC SEG output pin TO10 8/16-bit composite timer ch. 1 output pin PE7 General-purpose I/O port SEG21 M EC1 64 Function AVSS LCDC SEG output pin 8/16-bit composite timer ch. 1 clock input pin — A/D converter power supply pin (GND) *: For the I/O circuit types, see “8. I/O Circuit Type”. Document Number: 002-07475 Rev. *B Page 22 of 85 MB95410H/470H Series 8. I/O Circuit Type Type Circuit Remarks Reset input / Hysteresis input A Reset output / Digital output • N-ch open drain output • Hysteresis input • Reset output N-ch P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input Clock input X1 B X0 • CMOS output • Hysteresis input Standby control / Port select P-ch • Oscillation circuit • High-speed side Feedback resistance: approx. 1 MΩ Port select Digital output N-ch Digital output Standby control Hysteresis input Port select R Pull-up control P-ch Digital output P-ch N-ch Digital output Standby control Hysteresis input Clock input X1A • Oscillation circuit • Low-speed side Feedback resistance: approx. 10 MΩ C • CMOS output • Hysteresis input • Pull-up control available X0A Standby control / Port select Port select R Pull-up control Digital output Digital output P-ch N-ch Digital output Standby control Hysteresis input (Continued) Document Number: 002-07475 Rev. *B Page 23 of 85 MB95410H/470H Series Type Circuit Remarks Standby control Hysteresis input D • N-ch open drain output • Hysteresis input Digital output N-ch Pull-up control R P-ch Digital output P-ch G Digital output N-ch • • • • CMOS output Hysteresis input CMOS input Pull-up control available Standby control Hysteresis input CMOS input Pull-up control R P-ch H Digital output P-ch Digital output • CMOS output • Hysteresis input • Pull-up control available N-ch Standby control Hysteresis input Standby control CMOS input I Hysteresis input • N-ch open drain output • CMOS input • Hysteresis input Digital output N-ch Pull-up control R P-ch Digital output P-ch J Digital output N-ch • • • • CMOS output Hysteresis input Analog input Pull-up control available Analog input A/D control Standby control Hysteresis input (Continued) Document Number: 002-07475 Rev. *B Page 24 of 85 MB95410H/470H Series Type Circuit Remarks P-ch Digital output Digital output M N-ch LCD output • CMOS output • LCD output • Hysteresis input LCD control Standby control Hysteresis input P-ch Digital output Digital output N-ch N LCD output LCD control Standby control Hysteresis input • • • • CMOS output LCD output Hysteresis input CMOS input CMOS input P-ch Digital output Digital output N-ch Q LCD output • CMOS output • LCD output • Hysteresis input LCD control Standby control External interrupt control Hysteresis input P-ch Digital output Digital output R N-ch LCD internal divider resistor I/O • CMOS output • LCD power supply • Hysteresis input LCD control Standby control Hysteresis input (Continued) Document Number: 002-07475 Rev. *B Page 25 of 85 MB95410H/470H Series Type Circuit Remarks P-ch Digital output Digital output N-ch Analog input S • • • • CMOS output LCD output Hysteresis input Analog input • • • • CMOS output Hysteresis input Analog input Pull-up control available • • • • • CMOS output LCD output Hysteresis input Analog input CMOS input LCD output LCD control A/D control Standby control Hysteresis input Pull-up control R P-ch Digital output T Digital output N-ch Analog input Analog input control Standby control Hysteresis input P-ch Digital output Digital output N-ch Analog input V LCD output LCD control A/D control Standby control Hysteresis input CMOS input (Continued) Document Number: 002-07475 Rev. *B Page 26 of 85 MB95410H/470H Series (Continued) Type Circuit Remarks P-ch Digital output Digital output W N-ch Analog input • CMOS output • Hysteresis input • Analog input Analog input control Standby control Hysteresis input P-ch Digital output Y Digital output N-ch • CMOS output • Hysteresis input Standby control Hysteresis input Document Number: 002-07475 Rev. *B Page 27 of 85 MB95410H/470H Series 9. Notes on Device Handling Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "17.1 Absolute Maximum Ratings" of “17. Electrical Characteristics” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. 10. Pin Connection Treatment of unused input pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. DBG pin Connect the DBG pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board. The DBG pin should not stay at “L” level after power-on until the reset output is released. RST pin Connect the RST pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output function of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function or the general purpose I/O function can be selected by the RSTEN bit in the SYSC register. Analog power supply Always set the same potential to AVCC and VCC pins. When VCC is larger than AVCC, the current may flow through the AN00 to AN07 pins. Document Number: 002-07475 Rev. *B Page 28 of 85 MB95410H/470H Series Treatment of power supply pins on the A/D converter Ensure that AVCC is equal to VCC and AVSS equal to VSS even when the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. Therefore, connect a ceramic capacitor of 0.1 µF (approx.) as a bypass capacitor between the AVCC pin and the AVSS pin in the vicinity of this device. C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. DBG/RST/C pins connection diagram DBG C RST Cs Document Number: 002-07475 Rev. *B Page 29 of 85 MB95410H/470H Series 11. Block Diagram (MB95410H Series) F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Flash with security function (60/36/20 Kbyte) PF1/X1*2 PF0/X0*2 PG2/X1A*2 Oscillator circuit RAM (2032/1008/496 bytes) CR oscillator PG1/X0A*2 Interrupt controller P52/TO00 Clock control C P50/TO01 8/16-bit composite timer ch. 0 Watch counter P12*1/DBG P51/EC0 On-chip debug P00/AN00 to P07/AN07 8/10-bit A/D converter P13/ADTG Wild register 4 COM: External interrupt P14/UCK0 P11/UO0 UART/SIO ch. 0 P10/UI0 Internal bus P00/INT00 to P07/INT07 LCDC (4 COM or 8 COM) P05/UCK1 P03/UO1 UART/SIO ch. 1 8 COM: P90/V4 to P94/V0 P90/V4 to P94/V0 PA0/COM0 to PA3/COM3 PA0/COM0 to PA7/COM7 PB0/SEG00, PB1/SEG01 PB0/SEG00, PB1/SEG01 PC0/SEG02 to PC7/SEG09 PC0/SEG02 to PC7/SEG09 P60/SEG10 to P67/SEG17 P60/SEG10 to P67/SEG17 P43/SEG18 to P40/SEG21 P43/SEG18 to P40/SEG21 PE0/SEG22 to PE7/SEG29 PE0/SEG22 to PE7/SEG29 P07/SEG30 to P01/SEG36 P07/SEG30 to P02/SEG35 PB2/SEG37 to PB4/SEG39 P04/UI1 *3 P02/UCK2 P00/UO2 UART/SIO ch. 2 16-bit reload timer P01/UI2 P20/PPG00 P21/PPG01 8/16-bit PPG ch. 0 P52/TI0 P53/TO0 PE5/TO11 8/16-bit composite timer ch. 1 PE6/TO10 PE7/EC1 P16/PPG10 P15/PPG11 8/16-bit PPG ch. 1 P20/CMPN P22/SCL*1 I2C P23/SDA*1 Port Vcc *1: PF2, P12, P22 and P23 are N-ch open drain pins. Vss *2: Software option Voltage comparator P21/CMPP P17/CMPO Port *3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter when the event counter operating mode is enabled. Document Number: 002-07475 Rev. *B Page 30 of 85 MB95410H/470H Series 12. Block Diagram (MB95470H Series) F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Flash with security function (60/36/20 Kbyte) PF1/X1*2 PF0/X0*2 PG2/X1A*2 Oscillator circuit RAM (2032/1008/496 bytes) CR oscillator PG1/X0A*2 Interrupt controller P01/TO00 Clock control C P13/TO01 8/16-bit composite timer ch. 0 Watch counter P12*1/DBG P14/EC0 On-chip debug P00/AN00 to P07/AN07 8/10-bit A/D converter P13/ADTG Wild register 4 COM: External interrupt P14/UCK0 P11/UO0 UART/SIO ch. 0 P10/UI0 Internal bus P00/INT00 to P07/INT07 LCDC (4 COM or 8 COM) P05/UCK1 P03/UO1 UART/SIO ch. 1 8 COM: P90/V4 to P93/V1 P90/V4 to P93/V1 PA0/COM0 to PA3/COM3 PA0/COM0 to PA7/COM7 PB0/SEG00, PB1/SEG01 PB0/SEG00, PB1/SEG01 PC0/SEG02 to PC3/SEG05 PC0/SEG02 to PC3/SEG05 P60/SEG06 to P67/SEG13 P60/SEG06 to P67/SEG13 PE0/SEG14 to PE7/SEG21 PE0/SEG14 to PE7/SEG21 P07/SEG22 to P00/SEG29 P07/SEG22 to P02/SEG27 P16/SEG30, P15/SEG31 P04/UI1 *3 P02/UCK2 P00/UO2 UART/SIO ch. 2 16-bit reload timer P01/UI2 P20/PPG00 P21/PPG01 8/16-bit PPG ch. 0 P14/TI0 P10/TO0 PE5/TO11 8/16-bit composite timer ch. 1 PE6/TO10 PE7/EC1 P16/PPG10 P15/PPG11 8/16-bit PPG ch. 1 P20/CMPN P22*1/SCL I2C P23*1/SDA Port Vcc *1: PF2, P12, P22 and P23 are N-ch open drain pins. Vss *2: Software option Voltage comparator P21/CMPP P17/CMPO Port *3: 8/16-bit composite timer ch. 1 and 16-bit reload timer can be used as an event counter when the event counter operating mode is enabled. Document Number: 002-07475 Rev. *B Page 31 of 85 MB95410H/470H Series 13. CPU Core Memory Space The memory space of the MB95410H/470H Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95410H/470H Series are shown below. Memory Maps MB95F414H/F414K MB95F474H/F474K 0000H MB95F416H/F416K MB95F476H/F476K 0080H 0090H 0100H Access prohibited RAM 496 bytes 0080H 0090H 0100H Access prohibited RAM 1008 bytes 0F80H Access prohibited RAM 2032 bytes Registers 0200H 0480H Access prohibited 0F80H Extended I/O area Flash 4 Kbyte 0080H 0090H 0100H Registers 0200H Access prohibited I/O area I/O area Registers 0200H 0280H 1000H 2000H 0000H 0000H I/O area MB95F418H/F418K MB95F478H/F478K 0880H 0F80H 1000H 2000H Flash 4 Kbyte Access prohibited Extended I/O area Extended I/O area 1000H Vacant Vacant 7FFFH Flash 60 Kbyte Flash 32 Kbyte BFFFH Flash 16 Kbyte FFFFH Document Number: 002-07475 Rev. *B FFFFH FFFFH Page 32 of 85 MB95410H/470H Series 14. I/O Map (MB95410H Series) Address Register abbreviation 0000H PDR0 0001H DDR0 Port 0 direction register R/W 00000000B 0002H PDR1 Port 1 data register R/W 00000000B 0003H DDR1 Port 1 direction register R/W 00000000B 0004H — 0005H WATR Register name Port 0 data register (Disabled) R/W Initial value R/W 00000000B — — Oscillation stabilization wait time setting register R/W 11111111B 0006H PLLC PLL control register R/W 00000000B 0007H SYCC System clock control register R/W XXXXXX11B 0008H STBC Standby control register R/W 00000XXXB 0009H RSRR Reset source register R/W 000XXXXXB 000AH TBTC Time-base timer control register R/W 00000000B 000BH WPCR Watch prescaler control register R/W 00000000B 000CH WDTC Watchdog timer control register R/W 00000000B 000DH SYCC2 System clock control register 2 R/W XX100011B 000EH PDR2 Port 2 data register R/W 00000000B 000FH DDR2 Port 2 direction register R/W 00000000B 0010H, 0011H — — — 0012H PDR4 R/W 00000000B 0013H DDR4 Port 4 direction register R/W 00000000B 0014H PDR5 Port 5 data register R/W 00000000B 0015H DDR5 Port 5 direction register R/W 00000000B 0016H PDR6 Port 6 data register R/W 00000000B 0017H DDR6 Port 6 direction register R/W 00000000B 0018H to 001BH — — — 001CH PDR9 R/W 00000000B (Disabled) Port 4 data register (Disabled) Port 9 data register 001DH DDR9 Port 9 direction register R/W 00000000B 001EH PDRA Port A data register R/W 00000000B 001FH DDRA Port A direction register R/W 00000000B 0020H PDRB Port B data register R/W 00000000B 0021H DDRB Port B direction register R/W 00000000B 0022H PDRC Port C data register R/W 00000000B 0023H DDRC Port C direction register R/W 00000000B 0024H, 0025H — — — (Disabled) (Continued) Document Number: 002-07475 Rev. *B Page 33 of 85 MB95410H/470H Series Address Register abbreviation 0026H PDRE 0027H Register name R/W Initial value Port E data register R/W 00000000B DDRE Port E direction register R/W 00000000B 0028H PDRF Port F data register R/W 00000000B 0029H DDRF Port F direction register R/W 00000000B 002AH PDRG Port G data register R/W 00000000B 002BH DDRG Port G direction register R/W 00000000B 002CH — — — 002DH PUL1 Port 1 pull-up register R/W 00000000B 002EH PUL2 Port 2 pull-up register R/W 00000000B 002FH, 0030H — — — 0031H PUL5 R/W 00000000B 0032H to 0034H — — — 0035H PULG Port G pull-up register R/W 00000000B 0036H T01CR1 8/16-bit composite timer 01 status control register 1 R/W 00000000B 0037H T00CR1 8/16-bit composite timer 00 status control register 1 R/W 00000000B 0038H T11CR1 8/16-bit composite timer 11 status control register 1 R/W 00000000B 0039H T10CR1 8/16-bit composite timer 10 status control register 1 R/W 00000000B 003AH PC01 8/16-bit PPG01 control register R/W 00000000B 003BH PC00 8/16-bit PPG00 control register R/W 00000000B 003CH PC11 8/16-bit PPG11 control register R/W 00000000B 003DH PC10 8/16-bit PPG10 control register R/W 00000000B 003EH TMCSRH0 16-bit reload timer control status register upper R/W 00000000B 003FH TMCSRL0 16-bit reload timer control status register lower R/W 00000000B 0040H to 0047H — — — 0048H EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 00000000B 0049H EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 00000000B 004AH EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 00000000B 004BH EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 00000000B 004CH to 004EH — — — 004FH LCDCC2 LCDC control register 2 R/W 00010100B 0050H CMR0 Voltage comparator control register R/W 000X0001B 0051H to 0055H — — — (Disabled) (Disabled) Port 5 pull-up register (Disabled) (Disabled) (Disabled) (Disabled) (Continued) Document Number: 002-07475 Rev. *B Page 34 of 85 MB95410H/470H Series Address Register abbreviation 0056H SMC10 0057H SMC20 0058H Register name R/W Initial value UART/SIO serial mode control register 1 ch. 0 R/W 00000000B UART/SIO serial mode control register 2 ch. 0 R/W 00100000B SSR0 UART/SIO serial status register ch. 0 R/W 00000001B 0059H TDR0 UART/SIO serial output data register ch. 0 R/W 00000000B 005AH RDR0 UART/SIO serial input data register ch. 0 R 00000000B 005BH SMC11 UART/SIO serial mode control register 1 ch. 1 R/W 00000000B 005CH SMC21 UART/SIO serial mode control register 2 ch. 1 R/W 00100000B 005DH SSR1 UART/SIO serial status register ch. 1 R/W 00000001B 005EH TDR1 UART/SIO serial output data register ch. 1 R/W 00000000B 005FH RDR1 UART/SIO serial input data register ch. 1 R 00000000B IBCR00 I2C bus control register 0 R/W 00000001B IBCR10 I2C bus control register 1 R/W 00000000B IBCR0 I2C bus status register R 00000000B IDDR0 I2C data register R/W 00000000B IAAR0 I2C address register R/W 00000000B 0065H ICCR0 I2C clock control register R/W 00000000B 0066H SMC12 UART/SIO serial mode control register 1 ch. 2 R/W 00000000B 0067H SMC22 UART/SIO serial mode control register 2 ch. 2 R/W 00100000B 0068H SSR2 UART/SIO serial status register ch. 2 R/W 00000001B 0069H TDR2 UART/SIO serial output data register ch. 2 R/W 00000000B 006AH RDR2 UART/SIO serial input data register ch. 2 R 00000000B 006BH — — — 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000B 006EH ADDH 8/10-bit A/D converter data register upper R/W 00000000B 006FH ADDL 8/10-bit A/D converter data register lower R/W 00000000B 0070H WCSR Watch counter status register R/W 00000000B 0071H FSR2 Flash memory status register 2 R/W 00000000B 0072H FSR Flash memory status register R/W 000X0000B 0073H SWRE0 Flash memory sector write control register 0 R/W 00000000B 0074H FSR3 R 00000000B 0075H — — — 0076H WREN Wild register address compare enable register R/W 00000000B 0077H WROR Wild register data test setting register R/W 00000000B 0078H — — — 0060H 0061H 0062H 0063H 0064H (Disabled) Flash memory status register 3 (Disabled) Mirror of register bank pointer (RP) and direct bank pointer (DP) (Continued) Document Number: 002-07475 Rev. *B Page 35 of 85 MB95410H/470H Series Address Register abbreviation 0079H ILR0 007AH 007BH Register name R/W Initial value Interrupt level setting register 0 R/W 11111111B ILR1 Interrupt level setting register 1 R/W 11111111B ILR2 Interrupt level setting register 2 R/W 11111111B 007CH ILR3 Interrupt level setting register 3 R/W 11111111B 007DH ILR4 Interrupt level setting register 4 R/W 11111111B 007EH ILR5 Interrupt level setting register 5 R/W 11111111B 007FH — — — 0F80H WRARH0 Wild register address setting register (upper) ch. 0 R/W 00000000B 0F81H WRARL0 Wild register address setting register (lower) ch. 0 R/W 00000000B (Disabled) 0F82H WRDR0 Wild register data setting register ch. 0 R/W 00000000B 0F83H WRARH1 Wild register address setting register (upper) ch. 1 R/W 00000000B 0F84H WRARL1 Wild register address setting register (lower) ch. 1 R/W 00000000B 0F85H WRDR1 Wild register data setting register ch. 1 R/W 00000000B 0F86H WRARH2 Wild register address setting register (upper) ch. 2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (lower) ch. 2 R/W 00000000B 0F88H WRDR2 Wild register data setting register ch. 2 R/W 00000000B 0F89H to 0F91H — — — 0F92H T01CR0 8/16-bit composite timer 01 status control register 0 R/W 00000000B 0F93H T00CR0 8/16-bit composite timer 00 status control register 0 R/W 00000000B 0F94H T01DR 8/16-bit composite timer 01 data register R/W 00000000B 0F95H T00DR 8/16-bit composite timer 00 data register R/W 00000000B 0F96H TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 00000000B 0F97H T11CR0 8/16-bit composite timer 11 status control register 0 R/W 00000000B 0F98H T10CR0 8/16-bit composite timer 10 status control register 0 R/W 00000000B 0F99H T11DR 8/16-bit composite timer 11 data register R/W 00000000B 0F9AH T10DR 8/16-bit composite timer 10 data register R/W 00000000B 0F9BH TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 00000000B 0F9CH PPS01 8/16-bit PPG01 cycle setting buffer register R/W 11111111B 0F9DH PPS00 8/16-bit PPG00 cycle setting buffer register R/W 11111111B 0F9EH PDS01 8/16-bit PPG01 duty setting buffer register R/W 11111111B 0F9FH PDS00 8/16-bit PPG00 duty setting buffer register R/W 11111111B (Disabled) 0FA0H PPS11 8/16-bit PPG11 cycle setting buffer register R/W 11111111B 0FA1H PPS10 8/16-bit PPG10 cycle setting buffer register R/W 11111111B 0FA2H PDS11 8/16-bit PPG11 duty setting buffer register R/W 11111111B 0FA3H PDS10 8/16-bit PPG10 duty setting buffer register R/W 11111111B (Continued) Document Number: 002-07475 Rev. *B Page 36 of 85 MB95410H/470H Series Address Register abbreviation 0FA4H PPGS 0FA5H 0FA6H 0FA7H Register name R/W Initial value 8/16-bit PPG start register R/W 00000000B REVC 8/16-bit PPG output inversion register R/W 00000000B TMRH0 16-bit reload timer timer register upper R/W 00000000B TMRLRH0 16-bit reload timer reload register upper R/W 00000000B TMRL0 16-bit reload timer timer register lower R/W 00000000B TMRLRL0 16-bit reload timer reload register lower R/W 00000000B 0FA8H PSSR0 UART/SIO dedicated baud rate generator prescaler select register ch. 0 R/W 00000000B 0FA9H BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch. 0 R/W 00000000B 0FAAH PSSR1 UART/SIO dedicated baud rate generator prescaler select register ch. 1 R/W 00000000B 0FABH BRSR1 UART/SIO dedicated baud rate generator baud rate setting register ch. 1 R/W 00000000B 0FACH PSSR2 UART/SIO dedicated baud rate generator prescaler select register ch. 2 R/W 00000000B 0FADH BRSR2 UART/SIO dedicated baud rate generator baud rate setting register ch. 2 R/W 00000000B 0FAEH — (Disabled) — — 0FAFH AIDRL 0FB0H LCDCC1 A/D input disable register (lower) R/W 00000000B LCDC control register 1 R/W 00000000B 0FB1H — — — 0FB2H LCDCE1 LCDC enable register 1 R/W 00111110B 0FB3H 0FB4H LCDCE2 LCDC enable register 2 R/W 00000000B LCDCE3 LCDC enable register 3 R/W 00000000B 0FB5H LCDCE4 LCDC enable register 4 R/W 00000000B 0FB6H LCDCE5 LCDC enable register 5 R/W 00000000B 0FB7H LCDCE6 LCDC enable register 6 R/W 00000000B 0FB8H LCDCE7 LCDC enable register 7 R/W 00000000B 0FB9H LCDCB1 LCDC blinking setting register 1 R/W 00000000B 0FBAH LCDCB2 LCDC blinking setting register 2 R/W 00000000B 0FBBH, 0FBCH — — — 0FBDH to 0FE0H LCDRAM R/W 00000000B 0FE1H — — — 0FE2H EVCR Event counter control register R/W 00000000B 0FE3H WCDR Watch counter data register R/W 00111111B (Disabled) (Disabled) LCDC display RAM (36 bytes) (Disabled) (Continued) Document Number: 002-07475 Rev. *B Page 37 of 85 MB95410H/470H Series (Continued) Address Register abbreviation 0FE4H CRTH 0FE5H CRTL 0FE6H, 0FE7H — 0FE8H SYSC Register name R/W Initial value Main CR clock trimming register (upper) R/W 0XXXXXXXB Main CR clock trimming register (lower) R/W 00XXXXXXB — — System configuration register R/W 11000011B (Disabled) 0FE9H CMCR Clock monitoring control register R/W XX000000B 0FEAH CMDR Clock monitoring data register R 00000000B 0FEBH WDTH Watchdog timer selection ID register (upper) R XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (lower) R XXXXXXXXB 0FEDH — — — 0FEEH ILSR Input level select register (Disabled) R/W 00000000B 0FEFH WICR Interrupt pin control register R/W 01000000B 0FF0H to 0FFFH — — — (Disabled) R/W access symbols R/W : Readable / Writable R : Read only Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is indeterminate. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. Document Number: 002-07475 Rev. *B Page 38 of 85 MB95410H/470H Series 15. I/O Map (MB95470H Series) Address Register abbreviation 0000H PDR0 0001H 0002H 0003H Register name R/W Initial value Port 0 data register R/W 00000000B DDR0 Port 0 direction register R/W 00000000B PDR1 Port 1 data register R/W 00000000B DDR1 Port 1 direction register R/W 00000000B 0004H — — — 0005H WATR Oscillation stabilization wait time setting register (Disabled) R/W 11111111B 0006H PLLC PLL control register R/W 00000000B 0007H SYCC System clock control register R/W XXXXXX11B 0008H STBC Standby control register R/W 00000XXXB 0009H RSRR Reset source register R/W 000XXXXXB 000AH TBTC Time-base timer control register R/W 00000000B 000BH WPCR Watch prescaler control register R/W 00000000B 000CH WDTC Watchdog timer control register R/W 00000000B 000DH SYCC2 System clock control register 2 R/W XX100011B 000EH PDR2 Port 2 data register R/W 00000000B 000FH DDR2 Port 2 direction register R/W 00000000B 0010H to 0015H — — — 0016H PDR6 Port 6 data register R/W 00000000B 0017H DDR6 Port 6 direction register R/W 00000000B 0018H to 001BH — — — (Disabled) (Disabled) 001CH PDR9 Port 9 data register R/W 00000000B 001DH DDR9 Port 9 direction register R/W 00000000B 001EH PDRA Port A data register R/W 00000000B 001FH DDRA Port A direction register R/W 00000000B 0020H PDRB Port B data register R/W 00000000B 0021H DDRB Port B direction register R/W 00000000B 0022H PDRC Port C data register R/W 00000000B 0023H DDRC Port C direction register R/W 00000000B 0024H, 0025H — — — (Disabled) 0026H PDRE Port E data register R/W 00000000B 0027H DDRE Port E direction register R/W 00000000B 0028H PDRF Port F data register R/W 00000000B 0029H DDRF Port F direction register R/W 00000000B 002AH PDRG Port G data register R/W 00000000B 002BH DDRG Port G direction register R/W 00000000B 002CH — — — (Disabled) (Continued) Document Number: 002-07475 Rev. *B Page 39 of 85 MB95410H/470H Series Address Register abbreviation 002DH PUL1 002EH PUL2 002FH to 0034H — 0035H PULG 0036H Register name R/W Initial value Port 1 pull-up register R/W 00000000B Port 2 pull-up register R/W 00000000B — — Port G pull-up register R/W 00000000B T01CR1 8/16-bit composite timer 01 status control register 1 R/W 00000000B 0037H T00CR1 8/16-bit composite timer 00 status control register 1 R/W 00000000B 0038H T11CR1 8/16-bit composite timer 11 status control register 1 R/W 00000000B 0039H T10CR1 8/16-bit composite timer 10 status control register 1 R/W 00000000B 003AH PC01 8/16-bit PPG01 control register R/W 00000000B 003BH PC00 8/16-bit PPG00 control register R/W 00000000B 003CH PC11 8/16-bit PPG11 control register R/W 00000000B 003DH PC10 8/16-bit PPG10 control register R/W 00000000B 003EH TMCSRH0 16-bit reload timer control status register upper R/W 00000000B 003FH TMCSRL0 16-bit reload timer control status register lower R/W 00000000B 0040H to 0047H — — — 0048H EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 00000000B 0049H EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 00000000B 004AH EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 00000000B 004BH EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 00000000B 004CH to 004EH — — — 004FH LCDCC2 LCDC control register 2 R/W 00010100B 0050H CMR0 Voltage comparator control register R/W 000X0001B 0051H to 0055H — — — 0056H SMC10 UART/SIO serial mode control register 1 ch. 0 R/W 00000000B 0057H SMC20 UART/SIO serial mode control register 2 ch. 0 R/W 00100000B 0058H SSR0 UART/SIO serial status register ch. 0 R/W 00000001B 0059H TDR0 UART/SIO serial output data register ch. 0 R/W 00000000B 005AH RDR0 UART/SIO serial input data register ch. 0 R 00000000B 005BH SMC11 UART/SIO serial mode control register 1 ch. 1 R/W 00000000B 005CH SMC21 UART/SIO serial mode control register 2 ch. 1 R/W 00100000B 005DH SSR1 UART/SIO serial status register ch. 1 R/W 00000001B 005EH TDR1 UART/SIO serial output data register ch. 1 R/W 00000000B (Disabled) (Disabled) (Disabled) (Disabled) (Continued) Document Number: 002-07475 Rev. *B Page 40 of 85 MB95410H/470H Series Address Register abbreviation 005FH RDR1 0060H 0061H 0062H 0063H 0064H IBCR00 IBCR10 IBCR0 IDDR0 IAAR0 Register name UART/SIO serial input data register ch. 1 R/W Initial value R 00000000B 2 R/W 00000001B 2 R/W 00000000B 2 R 00000000B 2 R/W 00000000B 2 R/W 00000000B 2 I C bus control register 0 I C bus control register 1 I C bus status register I C data register I C address register 0065H ICCR0 I C clock control register R/W 00000000B 0066H SMC12 UART/SIO serial mode control register 1 ch. 2 R/W 00000000B 0067H SMC22 UART/SIO serial mode control register 2 ch. 2 R/W 00100000B 0068H SSR2 UART/SIO serial status register ch. 2 R/W 00000001B 0069H TDR2 UART/SIO serial output data register ch. 2 R/W 00000000B 006AH RDR2 UART/SIO serial input data register ch. 2 R 00000000B 006BH — — — 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000B 006EH ADDH 8/10-bit A/D converter data register upper R/W 00000000B 006FH ADDL 8/10-bit A/D converter data register lower R/W 00000000B 0070H WCSR Watch counter status register R/W 00000000B 0071H FSR2 Flash memory status register 2 R/W 00000000B 0072H FSR Flash memory status register R/W 000X0000B 0073H SWRE0 Flash memory sector write control register 0 R/W 00000000B 0074H FSR3 R 00000000B 0075H — — — 0076H WREN Wild register address compare enable register R/W 00000000B 0077H WROR Wild register data test setting register R/W 00000000B 0078H — — — 0079H ILR0 Interrupt level setting register 0 R/W 11111111B 007AH ILR1 Interrupt level setting register 1 R/W 11111111B 007BH ILR2 Interrupt level setting register 2 R/W 11111111B 007CH ILR3 Interrupt level setting register 3 R/W 11111111B 007DH ILR4 Interrupt level setting register 4 R/W 11111111B 007EH ILR5 Interrupt level setting register 5 R/W 11111111B 007FH — — — 0F80H WRARH0 Wild register address setting register (upper) ch. 0 R/W 00000000B 0F81H WRARL0 Wild register address setting register (lower) ch. 0 R/W 00000000B 0F82H WRDR0 Wild register data setting register ch. 0 R/W 00000000B (Disabled) Flash memory status register 3 (Disabled) Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) (Continued) Document Number: 002-07475 Rev. *B Page 41 of 85 MB95410H/470H Series Address Register abbreviation 0F83H WRARH1 0F84H 0F85H 0F86H R/W Initial value Wild register address setting register (upper) ch. 1 R/W 00000000B WRARL1 Wild register address setting register (lower) ch. 1 R/W 00000000B WRDR1 Wild register data setting register ch. 1 R/W 00000000B WRARH2 Wild register address setting register (upper) ch. 2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (lower) ch. 2 R/W 00000000B Wild register data setting register ch. 2 R/W 00000000B — — 0F88H WRDR2 0F89H to 0F91H — Register name (Disabled) 0F92H T01CR0 8/16-bit composite timer 01 status control register 0 R/W 00000000B 0F93H T00CR0 8/16-bit composite timer 00 status control register 0 R/W 00000000B 0F94H T01DR 8/16-bit composite timer 01 data register R/W 00000000B 0F95H T00DR 8/16-bit composite timer 00 data register R/W 00000000B 0F96H TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 00000000B 0F97H T11CR0 8/16-bit composite timer 11 status control register 0 R/W 00000000B 0F98H T10CR0 8/16-bit composite timer 10 status control register 0 R/W 00000000B 0F99H T11DR 8/16-bit composite timer 11 data register R/W 00000000B 0F9AH T10DR 8/16-bit composite timer 10 data register R/W 00000000B 0F9BH TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 00000000B 0F9CH PPS01 8/16-bit PPG01 cycle setting buffer register R/W 11111111B 0F9DH PPS00 8/16-bit PPG00 cycle setting buffer register R/W 11111111B 0F9EH PDS01 8/16-bit PPG01 duty setting buffer register R/W 11111111B 0F9FH PDS00 8/16-bit PPG00 duty setting buffer register R/W 11111111B 0FA0H PPS11 8/16-bit PPG11 cycle setting buffer register R/W 11111111B 0FA1H PPS10 8/16-bit PPG10 cycle setting buffer register R/W 11111111B 0FA2H PDS11 8/16-bit PPG11 duty setting buffer register R/W 11111111B 0FA3H PDS10 8/16-bit PPG10 duty setting buffer register R/W 11111111B 0FA4H PPGS 8/16-bit PPG start register R/W 00000000B 0FA5H REVC 8/16-bit PPG output inversion register R/W 00000000B 0FA6H 0FA7H TMRH0 16-bit reload timer timer register upper R/W 00000000B TMRLRH0 16-bit reload timer reload register upper R/W 00000000B TMRL0 16-bit reload timer timer register lower R/W 00000000B TMRLRL0 16-bit reload timer reload register lower R/W 00000000B 0FA8H PSSR0 UART/SIO dedicated baud rate generator prescaler select register ch. 0 R/W 00000000B 0FA9H BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch. 0 R/W 00000000B 0FAAH PSSR1 UART/SIO dedicated baud rate generator prescaler select register ch. 1 R/W 00000000B 0FABH BRSR1 UART/SIO dedicated baud rate generator baud rate setting register ch. 1 R/W 00000000B (Continued) Document Number: 002-07475 Rev. *B Page 42 of 85 MB95410H/470H Series Address Register abbreviation 0FACH PSSR2 0FADH 0FAEH 0FAFH AIDRL 0FB0H LCDCC1 Register name R/W Initial value UART/SIO dedicated baud rate generator prescaler select register ch. 2 R/W 00000000B BRSR2 UART/SIO dedicated baud rate generator baud rate setting register ch. 2 R/W 00000000B — (Disabled) — — A/D input disable register (lower) R/W 00000000B LCDC control register 1 R/W 00000000B 0FB1H — — — 0FB2H LCDCE1 LCDC enable register 1 (Disabled) R/W 00111100B 0FB3H LCDCE2 LCDC enable register 2 R/W 00000000B 0FB4H LCDCE3 LCDC enable register 3 R/W 00000000B 0FB5H LCDCE4 LCDC enable register 4 R/W 00000000B 0FB6H LCDCE5 LCDC enable register 5 R/W 00000000B 0FB7H LCDCE6 LCDC enable register 6 R/W 00000000B 0FB8H — — — (Disabled) 0FB9H LCDCB1 LCDC blinking setting register 1 R/W 00000000B 0FBAH LCDCB2 LCDC blinking setting register 2 R/W 00000000B 0FBBH, 0FBCH — — — 0FBDH to 0FD8H LCDRAM R/W 00000000B 0FD9H to 0FE1H — — — 0FE2H EVCR Event counter control register R/W 00000000B 0FE3H WCDR Watch counter data register R/W 00111111B 0FE4H CRTH Main CR clock trimming register (upper) R/W 0XXXXXXXB 0FE5H CRTL Main CR clock trimming register (lower) R/W 00XXXXXXB 0FE6H, 0FE7H — — — 0FE8H SYSC System configuration register R/W 11000011B 0FE9H CMCR Clock monitoring control register R/W XX000000B 0FEAH CMDR Clock monitoring data register R 00000000B 0FEBH WDTH Watchdog timer selection ID register (upper) R XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (lower) R XXXXXXXXB (Disabled) LCDC display RAM (28 bytes) (Disabled) (Disabled) (Continued) Document Number: 002-07475 Rev. *B Page 43 of 85 MB95410H/470H Series (Continued) Address Register abbreviation Register name R/W Initial value 0FEDH — (Disabled) — — 0FEEH ILSR Input level select register R/W 00000000B 0FEFH WICR Interrupt pin control register R/W 01000000B 0FF0H to 0FFFH — — — (Disabled) R/W access symbols R/W : Readable / Writable R : Read only Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is indeterminate. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. Document Number: 002-07475 Rev. *B Page 44 of 85 MB95410H/470H Series 16. Interrupt Source Table Vector table address Upper Lower Bit name of interrupt level setting register IRQ00 FFFAH FFFBH L00 [1:0] IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] UART/SIO ch. 0 IRQ04 FFF2H FFF3H L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 FFEEH FFEFH L06 [1:0] UART/SIO ch. 2 IRQ07 FFECH FFEDH L07 [1:0] LCD controller IRQ08 FFEAH FFEBH L08 [1:0] IRQ09 FFE8H FFE9H L09 [1:0] 8/16-bit PPG ch. 1 (upper) IRQ10 FFE6H FFE7H L10 [1:0] 16-bit reload timer ch. 0 IRQ11 FFE4H FFE5H L11 [1:0] 8/16-bit PPG ch. 0 (upper) IRQ12 FFE2H FFE3H L12 [1:0] 8/16-bit PPG ch. 0 (lower) IRQ13 FFE0H FFE1H L13 [1:0] 8/16-bit composite timer ch. 1 (upper) IRQ14 FFDEH FFDFH L14 [1:0] Voltage comparator IRQ15 FFDCH FFDDH L15 [1:0] I2C IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] IRQ20 FFD2H FFD3H L20 [1:0] — IRQ21 FFD0H FFD1H L21 [1:0] 8/16-bit composite timer ch. 1 (lower) IRQ22 FFCEH FFCFH L22 [1:0] Flash memory IRQ23 FFCCH FFCDH L23 [1:0] Interrupt source External interrupt ch. 0 External interrupt ch. 4 External interrupt ch. 1 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 8/16-bit PPG ch. 1 (lower) UART/SIO ch. 1 Watch prescaler Watch counter Interrupt request number Priority order of interrupt sources of the same level (occurring simultaneously) High Low Document Number: 002-07475 Rev. *B Page 45 of 85 MB95410H/470H Series 17. Electrical Characteristics 17.1 Absolute Maximum Ratings Parameter Power supply voltage*1 1 Symbol Rating Unit Min Max VCC VSS  0.3 VSS  6 V Remarks VI VSS  0.3 VSS  6 V *2 voltage*1 VO VSS  0.3 VSS  6 V *2 Maximum clamp current ICLAMP 2 2 mA Applicable to specific pins*3 |ICLAMP| — 20 mA Applicable to specific pins*3 “L” level maximum output current ICL — 15 mA “L” level average current ICLAV — 4 mA “L” level total maximum output current IOL — 100 mA IOLAV — 50 mA “H” level maximum output current ICH — 15 mA “H” level average current ICHAV — 4 mA “H” level total maximum output current IOH — 100 mA IOHAV — 50 mA Power consumption Pd — 320 mW Operating temperature TA 40 85 C Storage temperature Tstg 55 150 C Input voltage* Output Total maximum clamp current “L” level total average output current “H” level total average output current Average output current = operating current  operating ratio (1 pin) Total average output current = operating current  operating ratio (Total number of pins) Average output current = operating current  operating ratio (1 pin) Total average output current = operating current  operating ratio (Total number of pins) *1: These parameters are based on the condition that VSS = 0.0 V. *2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. (Continued) Document Number: 002-07475 Rev. *B Page 46 of 85 MB95410H/470H Series (Continued) *3: Applicable to the following pins: P00 to P07, P10, P11, P13 to P16, P20 to P22, P40 to P43, P50 to P53, P60 to P67, P90 to P94, PA0 to PA7, PB0 to PB4, PC0 to PC7, PE0 to PE7, PF0, PF1, PG1 and PG2 (P40 to P43, P50 to P53, P94, PB2 to PB4 and PC4 to PC7 are only available on the MB95410H Series.) • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistance should be set so that when the HV (High Voltage) signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, and thus affects other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit Input/Output equivalent circuit Protective diode VCC HV(High Voltage) input (0 V to 16 V) P-ch Limiting resistor N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-07475 Rev. *B Page 47 of 85 MB95410H/470H Series 17.2 Recommended Operating Conditions (VSS = 0.0 V) Parameter Power supply voltage Symbol VCC, AVCC Smoothing capacitor CS Operating temperature TA Value Min Max 2.4*1*2 5.5*1 2.3 5.5 2.9 5.5 2.3 5.5 0.022 1 40 85 +5 35 Unit Remarks In normal operation V Other than on-chip debug mode Hold condition in stop mode In normal operation On-chip debug mode Hold condition in stop mode µF C *3 Other than on-chip debug mode On-chip debug mode *1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: The value is initially 2.88 V when the low-voltage detection reset is used. *3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. DBG / RST / C pins connection diagram * DBG C RST Cs *: Since the DBG pin becomes a communication pin in on-chip debug mode, set a pull-up resistor value suiting the input/output specifications of P12/DBG. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-07475 Rev. *B Page 48 of 85 MB95410H/470H Series 17.3 DC Characteristics Parameter "H" level input voltage “L” level input voltage Open-drain output application voltage “H” level output voltage Symbol (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C) Pin name Condition Value Min Typ Max Unit Remarks VIHI P01, P04, P10, P22, P23 *1 0.7 VCC — VCC  0.3 V When CMOS input level (hysteresis input) is selected VIHS P00 to P07, P10 to P17, P20 to P23, P40 to P43*2, P50 to P53*2, P60 to P67, P90 to P93, P94*2, PA0 to PA7, PB0, PB1, PB2 to PB4*2, PC0 to PC3, PC4 to PC7*2, PE0 to PE7, PF0, PF1, PG1, PG2 *1 0.8 VCC — VCC  0.3 V Hysteresis input VIHM PF2 — 0.7 VCC — VCC  0.3 V Hysteresis input VIL P01, P04, P10, P22, P23 *1 VSS  0.3 — 0.3 VCC V When CMOS input level (hysteresis input) is selected VILS P00 to P07, P10 to P17, P20 to P23, P40 to P43*2, P50 to P53*2, P60 to P67, P90 to P93, P94*2, PA0 to PA7, PB0, PB1, PB2 to PB4*2, PC0 to PC3, PC4 to PC7*2, PE0 to PE7, PF0, PF1, PG1, PG2 *1 VSS  0.3 — 0.2 VCC V Hysteresis input VILM PF2 — VSS  0.3 — 0.3 VCC V Hysteresis input P12, P22, P23, PF2 — VSS  0.3 — VSS  5.5 V VCC  0.5 — — V VD VOH1 Output pins other than P12, P22, P23, PF2 IOH = 4 mA (Continued) Document Number: 002-07475 Rev. *B Page 49 of 85 MB95410H/470H Series (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C) Parameter “L” level output voltage Input leak current (Hi-Z output leak current) Symbol VOL1 ILI Pin name Value Min Typ*4 Max Unit Remarks All output pins IOL = 4 mA — — 0.4 V All input pins 0.0 V < VI < VCC 5 — 5 µA When pull-up resistance is disabled VI = 0 V 25 50 100 k When pull-up resistance is enabled f = 1 MHz — 5 15 pF Pull-up resistance RPULL P10, P11, P13, P14, P17, P20, P21, P50 to P53*2, PG1, PG2 Input capacitance CIN Other than VCC and VSS — 14.1 17 mA Except during Flash memory programming and erasing — 20 39.5 mA During Flash memory programming and erasing VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) — 6.6 9 mA VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Subclock mode (divided by 2) TA = 25C — 60 153 µA ICCLS VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = 25C — 9 84 µA ICCT VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = 25C — 4.3 30 µA VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) ICC ICCS Power supply current*3 Condition ICCL VCC (External clock operation) (Continued) Document Number: 002-07475 Rev. *B Page 50 of 85 MB95410H/470H Series (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol ICCMPLL Pin name VCC (External clock operation) ICCMCR VCC Power supply current*3 ICCSCR ICCTS VCC (External clock operation) ICCH IA IAH AVCC IV Condition Value Unit Min Typ*4 Max VCC = 5.5 V FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) TA = 25C — 9.7 12.5 mA VCC = 5.5 V FCH = 6.44 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) TA = 25C — 13.9 20 mA VCC = 5.5 V FCRH = 12.5 MHz FMP = 12.5 MHz Main CR clock mode — 11 13.2 mA VCC = 5.5 V Sub-CR clock mode (multiplied by 2.5) TA = 25C — 112 410 µA VCC = 5.5 V FCH = 32 MHz Time-base timer mode TA = 25C — 1 3 mA VCC = 5.5 V Substop mode TA = 25C — 3.1 22.5 µA Current consumption for A/D conversion at 16 MHz — 1.5 4.7 mA Current consumption for stopping A/D conversion at 16 MHz — 1 5 µA Current consumption of voltage comparator at 16 MHz — 113 350 µA Remarks Main stop mode with one clock selected (Continued) Document Number: 002-07475 Rev. *B Page 51 of 85 MB95410H/470H Series (Continued) (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol Pin name ICRH RLCD COM0 to COM7 output impedance RVCOM SEG00 to SEG39 output impedance RVSEG LCD leakage current ILCDL Unit Typ*4 Max Current consumption of the low-voltage detection circuit — 31 54 µA Current consumption of the main CR oscillator — 0.5 0.6 mA Current consumption of the sub-CR oscillator oscillating at 100 kHz — 20 72 µA — 400 — k — 40 — k — — 5 k SEG00 to SEG39 — — 7 k V0 to V4, COM0 to COM7, — SEG00 to SEG39 1 — 1 µA VCC ICRL LCD internal division resistance Value Min ILVD Power supply current*3 Condition — Between V4 and VSS COM0 to COM7 Remarks V1 to V4 = 4.1 V *1: The input levels of P01, P04, P10, P22 and P23 can be switched between “CMOS input level” and “hysteresis input level”. The input level selection register (ILSR) is used to switch between the two input levels. *2: P40 to P43, P50 to P53, P94, PB2 to PB4 and PC4 to PC7 are only available on the MB95410H Series. *3: • The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. • See “17.4. AC Characteristics: 17.4.1. Clock Timing” for FCH and FCL. • See “17.4. AC Characteristics: 17.4.2. Source Clock/Machine Clock” for FMP and FMPL. *4: VCC = 5.0 V, TA = +25°C Document Number: 002-07475 Rev. *B Page 52 of 85 MB95410H/470H Series 17.4 AC Characteristics 17.4.1 Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol Pin name X0, X1 — X0 X1: open * — — — FCH X0, X1 Clock frequency — — — — FCRH FCL X0A, X1A tHCYL tLCYL Input clock pulse width tWH1 tWL1 tWH2 tWL2 Input clock rise time and fall time tCR tCF CR oscillation start time tCRHWK tCRLWK Min Value Typ Max 1 — 1 1 3 3 3 12.25 9.8 7.84 0.98 12.1875 9.75 7.8 0.975 Unit Remarks 16.25 MHz When the main oscillation circuit is used — — — — — 12.5 10 8 1 12.5 10 8 1 12 32.5 8.13 6.5 4.06 12.75 10.2 8.16 1.02 12.8125 10.25 8.2 1.025 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz — 32.768 — kHz — 32.768 — kHz — — — 50 100 200 kHz X0, X1 — 61.5 — 1000 ns X1: open * — X1: open * 83.4 30.8 — 33.4 12.4 — — 30.5 — — 1000 1000 — — — ns ns µs ns ns — — 15.2 — µs X1: open — — 5 ns * — — 5 ns — — — — — — 80 10 µs µs FCRL Clock cycle time Condition X0 X0, X1 X0A, X1A X0 X0, X1 X0A X0 X0, X1 — — When the main external clock is used Main PLL multiplied by 2 Main PLL multiplied by 2.5 Main PLL multiplied by 4 Operating conditions: • The main CR clock is used. • TA = 10C to 85C Operating conditions: • The main CR clock is used. • TA = 40C to 1C When the sub-oscillation circuit is used When the sub-external clock is used When the sub-CR clock is used When the main oscillation circuit is used When the external clock is used When the subclock is used When the external clock is used, the duty ratio should range between 40% and 60%. When the external clock is used When the main CR clock is used When the sub-CR clock is used *: The external clock signal is input to X0 and the inverted external clock signal to X1. Document Number: 002-07475 Rev. *B Page 53 of 85 MB95410H/470H Series Input waveform generated when an external clock (main clock) is used tHCYL tWH1 tWL1 tCR tCF 0.8 VCC 0.8 VCC X0, X1 0.2 VCC 0.2 VCC 0.2 VCC Figure of main clock input port external connection When a crystal oscillator or a ceramic oscillator is used X0 When the external clock is used (X1 is open) X0 X1 When the external clock is used X1 X0 X1 Open FCH FCH FCH Input waveform generated when an external clock (subclock) is used tLCYL tWH2 tCR tWL2 tCF 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC Figure of subclock input port external connection When a crystal oscillator or a ceramic oscillator is used X0A X1A FCL When the external clock is used X0A X1A Open FCL Document Number: 002-07475 Rev. *B Page 54 of 85 MB95410H/470H Series 17.4.2 Source Clock/Machine Clock (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C) Parameter Source clock cycle time*1 Symbol tSCLK Pin name — FSPL Machine clock cycle time*2 (minimum instruction execution time) tMCLK Typ Max 61.5 — 2000 Unit — FMPL Remarks ns When the main oscillation clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 61.5 — 2000 ns When the main oscillation clock is used Min: FCH = 8.125 MHz, multiplied by the PLL multiplier of 2 Max: FCH = 1 MHz, divided by 2 80 — 1000 ns When the main CR clock is used Min: FCRH = 12.5 MHz Max: FCRH = 1 MHz — 61 — µs When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 — 20 — µs When the sub-CR clock is used FCRL = 100 kHz, divided by 2 0.50 — 16.25 MHz When the main oscillation clock is used 1 — 12.5 MHz When the main CR clock is used — 16.384 — kHz When the sub-oscillation clock is used — 50 — kHz When the sub-CR clock is used FCRL = 100 kHz, divided by 2 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 80 — 16000 ns When the main CR clock is used Min: FSP = 12.5 MHz Max: FSP = 1 MHz, divided by 16 61 — 976.5 µs When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 0.031 — 16.25 MHz When the main oscillation clock is used 0.0625 — 12.5 MHz When the main CR clock is used 1.024 — 16.384 kHz When the sub-oscillation clock is used 3.125 — 50 kHz When the sub-CR clock is used FCRL = 100 kHz — FMP Machine clock frequency Min — FSP Source clock frequency Value *1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the division ratio set by the machine clock divide ratio select bits (SYCC:DIV1, DIV0). In addition, a source clock can be selected from the following. • Main clock divided by 2 • PLL multiplication of main clock (select from 2, 2.5, 4 multiplication) • Main CR clock divided by 2 • Subclock divided by 2 • Sub-CR clock divided by 2 (Continued) Document Number: 002-07475 Rev. *B Page 55 of 85 MB95410H/470H Series (Continued) *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 Schematic diagram of the clock generation block Main PLL × 2 × 2.5 × 4 FCH (main oscillation) Divided by 2 FCRH (Main CR clock) FCL (sub-oscillation) FCRL (Sub-CR clock) Divided by 2 Divided by 2 Clock mode select bits (SYCC2: RCS1, RCS0) Document Number: 002-07475 Rev. *B SCLK (source clock) Division circuit × 1 × 1/4 × 1/8 ×1/16 MCLK (machine clock) Machine clock divide ratio select bits (SYCC: DIV1, DIV0) Page 56 of 85 MB95410H/470H Series Operating voltage - Operating frequency (When TA = 40C to 85C) Without the on-chip debug function 5.5 Operating voltage (V) 5.0 A/D converter operation range 4.0 3.5 3.0 2.4 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) Operating voltage - Operating frequency (When TA = 40C to 85C) With the on-chip debug function 5.5 Operating voltage (V) 5.0 A/D converter operation range 4.0 3.5 2.9 3.0 16 kHz 3 MHz 12.5 MHz 16.25 MHz Source clock frequency (FSP) Document Number: 002-07475 Rev. *B Page 57 of 85 MB95410H/470H Series 17.4.3 External Reset (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C) Parameter Value Symbol RST “L” level pulse width tRSTL Unit Remarks Min Max 2 tMCLK*1 — ns In normal operation Oscillation time of the oscillator*2  100 — µs In stop mode, subclock mode, subsleep mode, watch mode, and power-on 100 — µs In time-base timer mode *1: See “17.4.2. Source Clock/Machine Clock” for tMCLK. *2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and several ms. In normal operation tRSTL RST 0.2 VCC 0.2 VCC In stop mode, subclock mode, subsleep mode, watch mode and power-on tRSTL RST X0 0.2 VCC 0.2 VCC 90% of amplitude Internal operating clock 100 μs Oscillation time of oscillator Internal reset Document Number: 002-07475 Rev. *B Oscillation stabilization wait time Execute instruction Page 58 of 85 MB95410H/470H Series 17.4.4 Power-on Reset (VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol Condition Power supply rising time tR Power supply cutoff time tOFF Value Unit Min Max — — 50 ms — 1 — ms Remarks Wait time until power-on tOFF tR 2.5 V VCC 0.2 V 0.2 V 0.2 V Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below. VCC 2.3 V Set the slope of rising to a value below 30 mV/ms. Hold condition in stop mode VSS 17.4.5 Peripheral Input Timing (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol Peripheral input “H” pulse width tILIH Peripheral input “L” pulse width tIHIL Value Pin name INT00 to INT07, EC0, EC1, ADTG Unit Min Max 2 tMCLK* — ns 2 tMCLK* — ns *: See “17.4.2. Source Clock/Machine Clock” for tMCLK. tILIH INT00 to INT07, EC0, EC1, ADTG Document Number: 002-07475 Rev. *B 0.8 VCC tIHIL 0.8 VCC 0.2 VCC 0.2 VCC Page 59 of 85 MB95410H/470H Series 17.4.6 UART/SIO, Serial I/O Timing (VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC UCK  UO time tSLOVI Valid UI  UCK  tIVSHI UCK  valid UI hold time tSHIXI Serial clock “H” pulse width Serial clock “L” pulse width tSHSL tSLSH UCK  UO time tSLOVE Valid UI  UCK  tIVSHE UCK  valid UI hold time tSHIXE UCK0, UCK1, UCK2 UCK0, UCK1, UCK2, UO0, UO1, UO2 UCK0, UCK1, UCK2, UI0, UI1, UI2 UCK0, UCK1, UCK2, UI0, UI1, UI2 UCK0, UCK1, UCK2 UCK0, UCK1, UCK2 UCK0, UCK1, UCK2, UO0, UO1, UO2 UCK0, UCK1, UCK2, UI0, UI1, UI2 UCK0, UCK1, UCK2, UI0, UI1, UI2 Condition Internal clock operation output pin: CL = 80 pF  1 TTL External clock operation output pin: CL = 80 pF  1 TTL Value Min Max — 4 tMCLK* Unit ns 190 190 ns 2 tMCLK* — ns 2 tMCLK* — ns 4 tMCLK* 4 tMCLK* — — ns ns — 190 ns 2 tMCLK* — ns 2 tMCLK* — ns *: See “17.4.2. Source Clock/Machine Clock” for tMCLK. Document Number: 002-07475 Rev. *B Page 60 of 85 MB95410H/470H Series Internal shift clock mode UCK0, UCK1, UCK2 tSCYC 2.4 V 0.8 V 0.8 V tSLOVI UO0, UO1, UO2 2.4 V 0.8 V tIVSHI UI0, UI1, UI2 tSHIXI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External shift clock mode tSLSH UCK0, UCK1, UCK2 tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOVE UO0, UO1, UO2 2.4 V 0.8 V tIVSHE UI0, UI1, UI2 Document Number: 002-07475 Rev. *B tSHIXE 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Page 61 of 85 MB95410H/470H Series 17.4.7 Low-voltage Detection (VSS = 0.0 V, TA = -40°C to +85°C) Parameter Value Symbol Min Typ Max Unit Remarks Release voltage VDL+ 2.52 2.7 2.88 V At power supply rise Detection voltage VDL- 2.42 2.6 2.78 V At power supply fall Hysteresis width VHYS 70 100 — mV Power supply start voltage Voff — — 2.3 V Power supply end voltage Von 4.9 — — V Power supply voltage change time (at power supply rise) tr 3000 — — µs Slope of power supply that the reset release signal generates within the rating (VDL+) Power supply voltage change time (at power supply fall) tf 300 — — µs Slope of power supply that the reset detection signal generates within the rating (VDL-) Reset release delay time td1 — — 300 µs Reset detection delay time td2 — — 20 µs VCC Von Voff time tf tr VDL+ VHYS VDL- Internal reset signal time td2 Document Number: 002-07475 Rev. *B td1 Page 62 of 85 MB95410H/470H Series 17.4.8 I2C Timing (VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C) Value Parameter Symbol SCL clock frequency fSCL (Repeat) Start condition hold time SDA ↓ → SCL ↓ tHD;STA Pin name Conditions Standard-mode Fast-mode Unit Min Max Min Max 0 100 0 400 kHz SCL, SDA 4.0 — 0.6 — µs SCL SCL clock “L” width tLOW SCL 4.7 — 1.3 — µs SCL clock “H” width tHIGH SCL 4.0 — 0.6 — µs 4.7 — 0.6 — µs 0 3.45*2 0 0.9*3 µs (Repeat) Start condition setup time SCL ↑ → SDA ↓ tSU;STA SCL, SDA Data hold time SCL ↓ → SDA ↓ ↑ tHD;DAT SCL, SDA Data setup time SDA ↓ ↑ → SCL ↑ tSU;DAT SCL, SDA 0.25 — 0.1 — µs Stop condition setup time SCL ↑ → SDA ↑ tSU;STO SCL, SDA 4.0 — 0.6 — µs tBUF SCL, SDA 4.7 — 1.3 — µs Bus free time between stop condition and start condition R = 1.7 k, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at “L” (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT ≥ 250 ns is fulfilled. tWAKEUP SDA tLOW tHD;DAT tHIGH tHD;STA tBUF SCL tHD;STA tSU;DAT fSCL tSU;STA tSU;STO (Continued) Document Number: 002-07475 Rev. *B Page 63 of 85 MB95410H/470H Series (VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol Pin name Conditions Value*2 Min Max Unit Remarks SCL clock “L” width tLOW SCL (2  nm / 2)tMCLK  20 — ns Master mode SCL clock “H” width tHIGH SCL (nm / 2)tMCLK  20 (nm / 2)tMCLK  20 ns Master mode Start condition hold time tHD;STA SCL, SDA ( 1  nm / 2)tMCLK  20 ( 1  nm)tMCLK  20 ns Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Stop condition setup time tSU;STO SCL, SDA (1  nm / 2)tMCLK  20 (1  nm / 2)tMCLK  20 ns Master mode Start condition setup time tSU;STA SCL, SDA (1  nm / 2)tMCLK  20 (1  nm / 2)tMCLK  20 ns Master mode Bus free time between stop condition and start condition tBUF SCL, SDA (2 nm  4)tMCLK  20 — ns Data hold time tHD;DAT SCL, SDA 3 tMCLK 20 — ns Master mode ns Master mode When assuming that “L” of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Data setup time tSU;DAT R = 1.7 k, C = 50 pF*1 SCL, SDA ( 2  nm / 2)tMCLK  20 ( 1  nm / 2)tMCLK  20 Setup time between clearing interrupt and SCL rising tSU;INT SCL (nm / 2)tMCLK  20 (1  nm / 2)tMCLK  20 ns Minimum value is applied to interrupt at 9th SCL↓. Maximum value is applied to interrupt at 8th SCL↓. SCL clock “L” width tLOW SCL 4 tMCLK  20 — ns At reception SCL clock “H” width tHIGH SCL 4 tMCLK  20 — ns At reception (Continued) Document Number: 002-07475 Rev. *B Page 64 of 85 MB95410H/470H Series (Continued) (VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C) Parameter Symbol Pin name Conditions Value*2 Min Max Unit Remarks Start condition detection tHD;STA SCL, SDA 2 tMCLK  20 — ns Not detected when 1 tMCLK is used at reception Stop condition detection tSU;STO SCL, SDA 2 tMCLK  20 — ns Not detected when 1 tMCLK is used at reception Restart condition detection condition tSU;STA SCL, SDA 2 tMCLK  20 — ns Not detected when 1 tMCLK is used at reception Bus free time tBUF SCL, SDA 2 tMCLK  20 — ns At reception Data hold time tHD;DAT SCL, SDA 2 tMCLK  20 — ns At slave transmission mode Data setup time tSU;DAT SCL, SDA tLOW  3 tMCLK  20 — ns At slave transmission mode Data hold time tHD;DAT SCL, SDA 0 — ns At reception Data setup time tSU;DAT SCL, SDA tMCLK  20 — ns At reception SDA↓→SCL↑ (at wakeup function) SCL, tWAKEUP SDA Oscillation stabilization wait time  2 tMCLK  20 — ns R = 1.7 k, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. See “17.4.2. Source Clock/Machine Clock” for tMCLK. m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0). n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0). The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the CS4 to CS0 bits in the ICCR0 register. • Standard-mode: m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 MHz < tMCLK ≤ 10 MHz (m, n) = (8, 22) : 0.9 MHz < tMCLK ≤ 16.25 MHz • Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 MHz < tMCLK ≤ 10 MHz (m, n) = (5, 8) : 3.3 MHz < tMCLK ≤ 16.25 MHz *2: • • • • Document Number: 002-07475 Rev. *B Page 65 of 85 MB95410H/470H Series 17.4.9 Voltage Comparator Timing (AVCC = 4.0 V to 5.5 V, AVSS = 0.0 V, TA = -40°C to +85°C) Parameter Pin name Value Min Typ Max Unit Remarks Voltage range CMPP, CMPN 0 — AVCC  1.3 V Offset voltage CMPP, CMPN 10 — 10 mV Delay time CMPO — 650 1210 ns 5 mV overdrive — 140 420 ns 50 mV overdrive — — 1210 ns Power down recovery PD: 1  0 0 — — ns Power down effective PD: 0  1 Output: “H” level — — 1210 ns Output stabilization time at power up 1.17 1.22 1.27 V Power down delay CMPO Power up stabilization time CMPO Bandgap reference voltage — Document Number: 002-07475 Rev. *B Page 66 of 85 MB95410H/470H Series 17.5 A/D Converter 17.5.1 A/D Converter Electrical Characteristics (AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40°C to +85°C) Parameter Value Symbol Resolution Total error Linearity error — Differential linear error Unit Min Typ Max — — 10 bit 3 — 3 LSB 2.5 — 2.5 LSB 1.9 — 1.9 LSB Zero transition voltage VOT AVSS  1.5 LSB AVSS  0.5 LSB AVSS  2.5 LSB V Full-scale transition voltage VFST AVCC  4.5 LSB AVCC  2 LSB AVCC  0.5 LSB V Compare time Sampling time — 0.9 — 16500 µs 4.5 V  VCC 5.5 V 1.8 — 16500 µs 4.0 V  VCC
MB95F478HPMC1-G-SNE2 价格&库存

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