MB96F347RSAPQC-GS-JAERE2

CY96345/346 CY96F346/F347/F348 F2MC-16FX, CY96340 Series, 16-bit Proprietary Microcontroller Datasheet CY96340 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology ■ Can also be used to implement embedded debug support ■ 0.18μm CMOS DMA CPU ■ Automatic transfer function independent of CPU, can be assigned freely to resources ■ F2MC-16FX CPU ■ Up to 56 MHz internal, 17.8 ns instruction cycle time ■ Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) ■ 8-byte instruction execution queue ■ Signed multiply (16-bit available × 16-bit) and divide (32-bit/16-bit) instructions Interrupts ■ Fast Interrupt processing ■ 8 programmable priority levels ■ Non-Maskable Interrupt (NMI) Timers ■ Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) System clock ■ On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) ■ 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor). ■ Watchdog Timer CAN ■ Up to 56 MHz external clock for devices with fast clock input feature ■ Supports CAN protocol version 2.0 part A and B ■ 32-100 kHz subsystem quartz clock ■ ISO16845 certified ■ 100kHz/2MHz internal RC clock for quick and safe startup, oscillator ■ Bit rates up to 1 Mbit/s stop detection, watchdog ■ Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. ■ Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) ■ 32 message objects ■ Each message object has its own identifier mask ■ Programmable FIFO mode (concatenation of message objects) ■ Maskable interrupt ■ Disabled Automatic Retransmission mode for Time Triggered CAN ■ Clock modulator applications On-chip voltage regulator ■ Programmable loop-back mode for self-test operation ■ Internal voltage regulator supports reduced internal MCU voltage, USART offering low EMI and low power consumption figures Low voltage reset ■ Wide range of baud rate settings using a dedicated reload timer ■ Reset is generated when supply voltage is below minimum ■ Special synchronous options for adapting to different synchronous serial protocols Code Security ■ Protects ROM content from unintended read-out Memory Patch Function ■ LIN functionality working either as master or slave LIN device I2C ■ Up to 400 kbps ■ Replaces ROM content Cypress Semiconductor Corporation Document Number: 002-04579 Rev. *B ■ Full duplex USARTs (SCI/LIN) ■ Master and Slave functionality, 8-bit and 10-bit addressing • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 31, 2018 CY96340 Series A/D converter ■ Once enabled, can not be disabled other than by reset. ■ SAR-type ■ Level high or level low sensitive ■ 10-bit resolution ■ Pin shared with external interrupt 0. ■ Signals interrupt on conversion end, single conversion mode, External bus interface continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer A/D Converter Reference Voltage switch ■ 2 independent positive A/D converter reference voltages available ■ 8-bit or 16-bit bidirectional data ■ Up to 24-bit addresses ■ 6 chip select signals ■ Multiplexed address/data lines Reload Timers ■ Wait state request ■ 16-bit wide ■ External bus master possible ■ Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock ■ Timing programmable ■ Event count function Alarm comparator frequency Free Running Timers ■ Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency ■ Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds ■ Threshold voltages defined externally or generated internally ■ Status is readable, interrupts can be masked separately Input Capture Units I/O Ports ■ 16-bit wide ■ Virtually all external pins can be used as general purpose I/O ■ Signals an interrupt upon external event ■ All push-pull outputs (except when used as I2C SDA/SCL line) ■ Rising edge, falling edge or rising & falling edge sensitive ■ Bit-wise programmable as input/output or peripheral signal Output Compare Units ■ 16-bit wide ■ Bit-wise programmable input enable ■ Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL (TTL levels not supported by all devices) ■ Signals an interrupt when a match with 16-bit I/O Timer occurs ■ Bit-wise programmable pull-up resistor ■ A pair of compare registers can be used to generate an output signal. ■ Bit-wise programmable output driving strength for EMI optimization Programmable Pulse Generator Packages ■ 16-bit down counter, cycle and duty setting registers ■ 100-pin plastic QFP and LQFP ■ Interrupt at trigger, counter borrow and/or duty match ■ PWM operation and one-shot operation ■ Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow as clock input ■ Can be triggered by software or reload timer Real Time Clock ■ Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the RC oscillator ■ Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) ■ Read/write accessible second/minute/hour registers Flash Memory ■ Supports automatic programming, Embedded Algorithm ■ Write/Erase/Erase-Suspend/Resume commands ■ A flag indicating completion of the algorithm ■ Number of erase cycles: 10,000 times ■ Data retention time: 20 years ■ Erase can be performed on each sector individually ■ Sector protection ■ Flash Security feature to protect the content of the Flash ■ Low voltage detection during Flash erase ■ Can signal interrupts every half second/second/minute/hour/day ■ Internal clock divider and prescaler provide exact 1s clock External Interrupts ■ Edge sensitive or level sensitive ■ Interrupt mask and pending bit per channel ■ Each available CAN channel RX has an external interrupt for wake-up ■ Selected USART channels SIN have an external interrupt for wake-up Non Maskable Interrupt ■ Disabled after reset Document Number: 002-04579 Rev. *B Page 2 of 111 CY96340 Series Contents Product Lineup ................................................................... 4 Block Diagram .................................................................... 6 Pin Assignments ................................................................. 7 Pin Function Description ..................................................... 9 Pin Circuit Type .................................................................11 I/O Circuit Type ................................................................. 12 Memory Map ..................................................................... 15 User ROM Memory Map For Flash Devices .................. 17 User ROM Memory Map for Mask ROM Devices ............. 20 Serial Programming Communication Interface ................. 21 I/O Map ............................................................................. 22 Interrupt Vector Table ....................................................... 49 Handling Devices .............................................................. 53 Latch-up prevention .......................................................... 53 Unused pins handling ....................................................... 53 External clock usage ........................................................ 53 Unused sub clock signal ................................................... 54 Notes on PLL clock mode operation ................................. 54 Power supply pins (VCC/VSS) ......................................... 54 Crystal oscillator and ceramic resonator circuit ................ 55 Turn on sequence of power supply to A/D converter and analog inputs ................................................................................ 55 Pin handling when not using the A/D converter ................ 55 Notes on Power-on ........................................................... 55 Stabilization of power supply voltage ............................... 55 Serial communication ....................................................... 55 Handling of Data Flash ..................................................... 55 Electrical Characteristics .................................................. 56 Absolute Maximum Ratings .............................................. 56 Recommended Operating Conditions .............................. 58 DC characteristics ............................................................ 59 AC Characteristics ............................................................ 68 Analog Digital Converter ................................................... 86 Alarm Comparator ............................................................ 90 Low Voltage Detector Characteristics ............................... 92 Flash Memory Program/erase Characteristics ................. 94 Example Characteristics ................................................... 95 Package Dimension CY96(F)34x LQFP 100P .................. 99 Package Dimension CY96(F)34x QFP 100P .................. 100 Ordering Information ....................................................... 101 MCU with CAN Controller ............................................... 101 MCU without CAN Controller .......................................... 102 Major Changes ............................................................... 103 Revision History .............................................................. 108 Document Number: 002-04579 Rev. *B Page 3 of 111 CY96340 Series 1. Product Lineup Features CY96V300B CY96(F)34x Product type Evaluation sample Flash product: CY96F34x Mask ROM product: CY9634x Product options YS Low voltage reset persistently on / Single clock RS Low voltage reset can be disabled / Single clock YW Low voltage reset persistently on / Dual clock RW Low voltage reset can be disabled / Dual clock TS indep. 32KB Flash / Low voltage reset persistently on / Single clock HS indep. 32KB Flash / Low voltage reset can be disabled / Single clock TW indep. 32KB Flash / Low voltage reset persistently on / Dual clock HW indep. 32KB Flash / Low voltage reset can be disabled / Dual clock NA FS 64KB Data Flash / Low voltage reset persistently on / Single clock DS 64KB Data Flash / Low voltage reset can be disabled / Single clock FW 64KB Data Flash / Low voltage reset persistently on / Dual clock DW 64KB Data Flash / Low voltage reset can be disabled / Dual clock AS No CAN / Low voltage reset can be disabled / Single clock devices CS No CAN / indep. 32KB Flash / Low voltage reset can be disabled / Single clock AW No CAN / Low voltage reset can be disabled / Dual clock CW No CAN / indep. 32KB Flash / Low voltage reset can be disabled / Dual clock Flash/ROM RAM 160KB 8KB CY96345Y, CY96345R 224KB [Flash A: 160KB, Data Flash A: 64KB] 8KB CY96F345F, CY96F345D 288KB 16KB 416KB 16KB 544KB 24KB CY96F348Y, CY96F348R, CY96F348A 576KB [Flash A: 544KB, Flash B: 32KB] 24KB CY96F348T, CY96F348H, CY96F348C ROM/Flash memory emulation by external RAM, 92KB internal RAM CY96F346Y, CY96346Y, CY96F346R, CY96346R, CY96F346A CY96F347Y, CY96F347R, CY96F347A Package BGA416 LQI100 PQH100 DMA 16 channels 6 channels USART 10 channels 7 channels Document Number: 002-04579 Rev. *B Page 4 of 111 CY96340 Series Features CY96V300B CY96(F)34x I2 C 2 channels 2 channels A/D Converter 40 channels 24 channels A/D Converter Reference Voltage switch yes yes (except CY96F345Dyy or CY96F345Fyy) 16-bit Reload Timer 6 channels + 1 channel (for PPG) 4 channels + 1 channel (for PPG) 16-bit Free-Running Timer 4 channels 2 channels 16-bit Output Compare 12 channels 8 channels 16-bit Input Capture 12 channels 8 channels 16-bit Programmable Pulse Generator 20 channels 16 channels CAN Interface 5 channels CY96(F)34xAyy or CY96(F)34xCyy: no CY96F345Dyy or CY96F345Fyy: 1 channel others: 2 channels External Interrupts 16 channels Non-Maskable Interrupt 1 channel Real Time Clock 1 I/O Ports Alarm comparator External bus interface 136 80 for part number with suffix "W", 82 for part number with suffix "S" 2 channels CY96F345Dyy or CY96F345Fyy: no others: 2 channels Yes Yes (multiplexed address/data) Chip select 6 signals Clock output function 2 channels Low voltage reset Yes On-chip RC-oscillator Yes Document Number: 002-04579 Rev. *B Page 5 of 111 CY96340 Series 2. Block Diagram Figure 1. Block diagram of CY96(F)34x AD00 ... AD15 A16 ... A23 ALE RDX WR(L)X, WRHX HRQ HAKX NMI, NMI_R RDY ECLK LBX, UBX CS0 ... CS5 External Bus Interface 16FX CPU Interrupt Controller CKOT0, CKOT1 CKOTX0, CKOTX1 X0, X1 X0A, X1A [1] RSTX MD0...MD2 Flash Memory A Flash Memory B or Data Flash A [2] Memory Patch Unit Clock & Mode Controller 16FX Core Bus (CLKB) SCL0, SCL1 AVCC AVSS AVRH AVRL/AVRH2 [5] AN0 ... AN23 10-bit ADC 24 ch. TOT0 ... TOT3 16-bit Reload Timer 4 ch. FRCK0 IN0 ... IN3 OUT0 ... OUT3 I/O Timer 0 ICU 0/1/2/3 OCU 0/1/2/3 FRCK1 IN4 ... IN7 OUT4 ... OUT7 I/O Timer 1 ICU 4/5/6/7 OCU 4/5/6/7 INT0 ... INT15 INT0_R ... INT2_R INT4_R, INT5_R INT7_R ... INT15_R INT3_R1 Peripheral Bus Bridge I2C 2 ch. ADTG, ADTG_R TIN0 ... TIN3 Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) SDA0, SDA1 Watchdog Peripheral Bus 1 (CLKP1) DMA Controller USART 7 ch. Alarm Comparator 2 ch. *4 16-bit PPG 16 ch. RLT6 External Interrupt Real Time Clock RAM Boot ROM Voltage Regulator VCC VSS C CAN Interface 2 ch. TX0, TX1 [3] RX0, RX1 [3] SIN0...SIN3, SIN2_R, SIN7_R...SIN9_R SOT0...SOT3, SOT2_R, SOT7_R...SOT9_R SCK0...SCK3, SCK2_R, SCK7_R...SCK9_R ALARM0 [4] ALARM1 [4] TTG0 ... TTG15 PPG0 ... PPG15 WOT [1]: X0A, X1A only available on CY96(F)34xyWy [2]: Flash B only available on CY96F34xCyy, CY96F34xHyy or CY96F34xTyy Data Flash A only available on CY96F34xDyy or CY96F34xFyy [3]: CAN interfaces are not available on CY96(F)34xAyy or CY96(F)34xCyy CAN1 is not available on CY96F345Dyy or CY96F345Fyy [4]: Alarm comparator is not available on CY96F345Dyy or CY96F345Fyy [5]: A/D converter reference voltage switch is not available on CY96F345Dyy or CY96F345Fyy Document Number: 002-04579 Rev. *B Page 6 of 111 CY96340 Series 3. Pin Assignments MD2 MD1 MD0 RSTX P07_6/AN22/INT6/SOT9_R P07_7/AN23/INT7/SIN9_R P08_0/TIN0/CKOTX0/ADTG/INT12_R P08_1/TOT0/CKOT0/INT13_R P08_2/SIN0/TIN2/INT14_R P08_3/SOT0/TOT2 P08_4/SCK0/INT15_R P08_5/SIN1/INT1_R P08_6/SOT1 P08_7/SCK1 Vcc Vss P09_0/PPG8/UBX P09_1/PPG9/LBX P09_2/PPG10/CS5 P09_3/PPG11/CS4 P09_4/OUT0/CS3 P09_5/OUT1/CS2 P09_6/OUT2/CS1 P09_7/OUT3/CS0 P10_0/RX0/INT8_R [2] P10_1/TX0 [2] P00_0/AD00/INT8/SCK7_R P00_1/AD01/INT9/SOT7_R P00_2/AD02/INT10/SIN7_R P00_3/AD03/INT11/SCK8_R Figure 2. Pin assignment of CY96(F)34x (PQH100) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P00_4/AD04/INT12/SOT8_R 81 50 P07_5/AN21/INT5/SCK9_R P00_5/AD05/INT13/SIN8_R 82 49 P07_4/AN20/INT4 P00_6/AD06/INT14 83 48 P07_3/AN19/INT3 P00_7/AD07/INT15 84 47 P07_2/AN18/INT2 P01_0/AD08/CKOT1/TIN1 85 46 P07_1/AN17/INT1 P01_1/AD09/CKOTX1/TOT1 86 45 P07_0/AN16/INT0/NMI P01_2/AD10/INT11_R/SIN3 87 44 Vss P01_3/AD11/SOT3 88 43 P06_7/AN7/PPG7 P01_4/AD12/SCK3 89 42 P06_6/AN6/PPG6 Vcc 90 41 P06_5/AN5/PPG5 Vss 91 40 P06_4/AN4/PPG4 X1 92 39 P06_3/AN3/PPG3 X0 93 38 P06_2/AN2/PPG2 P01_5/AD13/INT7_R/SIN2_R 94 37 P06_1/AN1/PPG1 P01_6/AD14/SOT2_R 95 36 P06_0/AN0/PPG0 P01_7/AD15/SCK2_R 96 35 AVss P02_0/A16/PPG12 97 34 AVRL/AVRH2 [4] P02_1/A17/PPG13 98 33 AVRH P02_2/A18/PPG14 99 32 AVcc P02_3/A19/PPG15 100 31 P05_7/AN15/INT5_R QFP - 100 P05_6/AN14/INT4_R P05_5/AN13/INT0_R/NMI_R P05_4/AN12/TOT3/INT2_R P05_3/AN11/TIN3/WOT P05_2/AN10/SCK2 P05_1/AN9/ALARM1/SOT2 [3] P05_0/AN8/ALARM0/SIN2/INT3_R1 [3] P04_7/SCL1 P04_6/SDA1 P03_3/WRHX P04_5/SCL0/FRCK1 P03_2/WRLX/WRX/INT10_R P04_4/SDA0/FRCK0 P03_0/ALE/IN4/TTG4/TTG12 P03_1/RDX/IN5/TTG5/TTG13 P04_3/IN7/TX1/TTG7/TTG15[2] P02_7/A23/IN3/TTG3/TTG11 P04_2/IN6/RX1/INT9_R/TTG6/TTG14 [2] P02_6/A22/IN2/TTG2/TTG10 C P02_4/A20/TTG8/TTG0/IN0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vss 8 Vcc 7 X1A/P04_1[1] 6 X0A/P04_0 [1] 5 P03_7/ECLK/OUT7 4 P03_6/RDY/OUT6 3 P03_5/HAKX/OUT5 2 P03_4/HRQ/OUT4 1 P02_5/A21/TTG9/TTG1/IN1/ADTG_R Package code (mold) PQH100 [1]: CY96(F)34xyWy: X0A, X1A CY96(F)34xySy: P04_0, P04_1 [2]: TX0, RX0, TX1, RX1 are not available on CY96(F)34xAyy or CY96(F)34xCyy TX1, RX1 are not available on CY96F345Dyy or CY96F345Fyy [3]: ALARM0, ALARM1 are not available on CY96F345Dyy or CY96F345Fyy [4]: AVRH2 is not available on CY96F345Dyy or CY96F345Fyy ( PQH100) Remark: CY96(F)34x products are pin-compatible to F2MC-16LX family CY90340 series. Document Number: 002-04579 Rev. *B Page 7 of 111 CY96340 Series MD0 RSTX P07_6/AN22/INT6/SOT9_R P07_7/AN23/INT7/SIN9_R P08_0/TIN0/CKOTX0/ADTG/INT12_R P08_1/TOT0/CKOT0/INT13_R P08_2/SIN0/TIN2/INT14_R P08_3/SOT0/TOT2 P08_4/SCK0/INT15_R P08_5/SIN1/INT1_R P08_6/SOT1 P08_7/SCK1 Vcc Vss P09_0/PPG8/UBX P09_1/PPG9/LBX P09_2/PPG10/CS5 P09_3/PPG11/CS4 P09_4/OUT0/CS3 P09_5/OUT1/CS2 P09_6/OUT2/CS1 P09_7/OUT3/CS0 P10_0/RX0/INT8_R [2] P10_1/TX0 [2] P00_0/AD00/INT8/SCK7_R Figure 3. Pin assignment of CY96(F)34x (LQI100) P00_1AD01/INT9/SOT7_R 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 MD1 P00_2/AD02/INT10/SIN7_R 77 49 MD2 P00_3/AD03/INT11/SCK8_R 78 48 P07_5/AN21/INT5/SCK9_R P00_4/AD04/INT12/SOT8_R 79 47 P07_4/AN20/INT4 P00_5/AD05/INT13/SIN8_R 80 46 P07_3/AN19/INT3 P00_6/AD06/INT14 81 45 P07_2/AN18/INT2 P00_7/AD07/INT15 82 44 P07_1/AN17/INT1 P01_0/AD08/CKOT1/TIN1 83 43 P07_0/AN16/INT0/NMI P01_1/AD09/CKOTX1/TOT1 84 42 Vss P01_2/AD10/INT11_R/SIN3 85 41 P06_7/AN7/PPG7 P01_3/AD11/SOT3 86 40 P06_6/AN6/PPG6 P01_4/AD12/SCK3 87 39 P06_5/AN5/PPG5 Vcc 88 38 P06_4/AN4/PPG4 Vss 89 37 P06_3/AN3/PPG3 X1 90 36 P06_2/AN2/PPG2 X0 91 35 P06_1/AN1/PPG1 P01_5/AD13/INT7_R/SIN2_R 92 34 P06_0/AN0/PPG0 P01_6/AD14/SOT2_R 93 33 AVss P01_7/AD15/SCK2_R 94 32 AVRL/AVRH2 [4] P02_0/A16/PPG12 95 31 AVRH P02_1/A17/PPG13 96 30 AVcc P02_2/A18/PPG14 97 29 P05_7/AN15/INT5_R P02_3/A19/PPG15 98 28 P05_6/AN14/INT4_R P02_4/A20/TTG8/TTG0/IN0 99 27 P05_5/AN13/INT0_R/NMI_R Package code (mold) LQI100 P05_4/AN12/TOT3/INT2_R P05_3/AN11/TIN3/WOT P05_2/AN10/SCK2 P05_1/AN9/ALARM1/SOT2[3] P05_0/AN8/ALARM0/SIN2/INT3_R1 [3] P04_7/SCL1 P04_6/SDA1 P04_5/SCL0/FRCK1 P04_4/SDA0/FRCK0 P04_3/IN7/TX1/TTG7/TTG15[2] P04_2/IN6/RX1/INT9_R/TTG6/TTG14[2] C Vss Vcc X1A/P04_1 [1] X0A/P04_0 [1] 7 8 P03_7/ECLK/OUT7 6 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P03_6/RDY/OUT6 5 P03_5/HAKX/OUT5 4 P03_3/WRHX 2 P03_4/HRQ/OUT4 3 P03_2/WRLX/WRX/INT10_R P02_6/A22/IN2/TTG2/TTG10 1 P03_1/RDX/IN5/TTG5/TTG13 100 P02_7/A23/IN3/TTG3/TTG11 P03_0/ALE/IN4/TTG4/TTG12 P02_5/A21/TTG9/TTG1/IN1/ADTG_R LQFP - 100 [1]: CY96(F)34xyWy: X0A, X1A CY96(F)34xySy: P04_0, P04_1 [2]: TX0, RX0, TX1, RX1 are not available on CY96(F)34xAyy or CY96(F)34xCyy TX1, RX1 are not available on CY96F345Dyy or CY96F345Fyy [3]: ALARM0, ALARM1 are not available on CY96F345Dyy or CY96F345Fyy [4]: AVRH2 is not available on CY96F345Dyy orCY96F345Fyy (LQI100) Remark: CY96(F)34x products are pin-compatible to F2MC-16LX family CY90340 series. Document Number: 002-04579 Rev. *B Page 8 of 111 CY96340 Series 4. Pin Function Description Table 1: Pin Function description Pin name Feature Description ADn External bus External bus interface (multiplexed mode) address output and data input/output ADTG ADC A/D converter trigger input ADTG_R ADC Relocated A/D converter trigger input ALARMn Alarm comparator Alarm Comparator n input ALE External bus External bus Address Latch Enable output An External bus External bus address output ANn ADC A/D converter channel n input AVCC Supply Analog circuits power supply AVRH ADC A/D converter high reference voltage input AVRH2 ADC Alternative A/D converter high reference voltage input AVRL ADC A/D converter low reference voltage input AVSS Supply Analog circuits power supply C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock output function Clock Output function n output CKOTXn Clock output function Clock Output function n inverted output ECLK External bus External bus clock output CSn External bus External bus chip select n output FRCKn Free Running Timer Free Running Timer n input HAKX External bus External bus Hold Acknowledge HRQ External bus External bus Hold Request INn ICU Input Capture Unit n input INTn External Interrupt External Interrupt n input INTn_R External Interrupt Relocated External Interrupt n input LBX External bus External Bus Interface Lower Byte select strobe output MDn Core Input pins for specifying the operating mode. NMI External Interrupt Non-Maskable Interrupt input NMI_R External Interrupt Relocated Non-Maskable Interrupt input OUTn OCU Output Compare Unit n waveform output Pxx_n GPIO General purpose IO PPGn PPG Programmable Pulse Generator n output RDX External bus External bus interface read strobe output Document Number: 002-04579 Rev. *B Page 9 of 111 CY96340 Series Table 1: Pin Function description Pin name Feature Description RDY External bus External bus interface external wait state request input RSTX Core Reset input RXn CAN CAN interface n RX input SCKn USART USART n serial clock input/output SCKn_R USART Relocated USART n serial clock input/output SCLn I2C I2C interface n clock I/O input/output SDAn I2C I2C interface n serial data I/O input/output SINn USART USART n serial data input SINn_R USART Relocated USART n serial data input SOTn USART USART n serial data output SOTn_R USART Relocated USART n serial data output TINn Reload Timer Reload Timer n event input TOTn Reload Timer Reload Timer n output TTGn PPG Programmable Pulse Generator n trigger input TXn CAN CAN interface n TX output UBX External bus External Bus Interface Upper Byte select strobe output VCC Supply Power supply VSS Supply Power supply WOT RTC Real Timer clock output WRHX External bus External bus High byte write strobe output WRLX/WRX External bus External bus Low byte / Word write strobe output X0 Clock Oscillator input X0A Clock Subclock Oscillator input (only for devices with suffix "W") X1 Clock Oscillator output X1A Clock Subclock Oscillator output (only for devices with suffix "W") Document Number: 002-04579 Rev. *B Page 10 of 111 CY96340 Series 5. Pin Circuit Type Table 2: Pin circuit types LQI100 PQH100 Pin no. Circuit type [1] Pin no. Circuit type [1] 1-10 H 1-12 H 11,12 B [2] 13, 14 B [2] 11,12 H [3] 13, 14 H [3] 13,14 Supply 15,16 Supply 15 F 17 F 16,17 H 18,19 H 18-21 N 20-23 N 22-29 I 24-31 I 30 Supply 32 Supply 31-32 G 33-34 G 33 Supply 35 Supply 34 to 41 I 36 to 43 I 42 Supply 44 Supply 43 to 48 I 45 to 50 I 49 to 51 C 51 to 53 C 52 E 54 E 53 to 54 I 55 to 56 I 55 to 62 H 57 to 64 H 63, 64 Supply 65, 66 Supply 65 to 87 H 67 to 89 H 88,89 Supply 90, 91 Supply 90, 91 A 92, 93 A 92-100 H 94 to 100 H [1]: Please refer to “ I/O Circuit Type” for details on the I/O circuit types [2]: Devices with suffix ”W” [3]: Devices without suffix ”W” Document Number: 002-04579 Rev. *B Page 11 of 111 CY96340 Series 6. I/O Circuit Type Type Circuit Remarks A High-speed oscillation circuit: ■ Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) X1 R ■ Programmable feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode 0 MRFBE Xout 1 FCI R X0 FCI or osc disable B Low-speed oscillation circuit: Xout X1A ■ Programmable feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled R SRFBE R X0A osc disable C ■ Mask ROM and EVA device:CMOS Hysteresis input pin ■ Flash device:CMOS input pin R Hysteresis inputs ■ CMOS Hysteresis input pin E ■ Pull-up resistor value: approx. 50 kΩ Pull-up Resistor R Document Number: 002-04579 Rev. *B Hysteresis inputs Page 12 of 111 CY96340 Series Type Circuit Remarks F ■ Power supply input protection circuit G ■ A/D converter ref+ (AVRH/AVRH2) power supply input pin with protection circuit ANE ■ Flash devices do not have a protection circuit against VCC AVR ■ Devices without AVRH reference switch do not have an for pins AVRH/AVRH2 analog switch for the AVRL pin ANE H ■ CMOS level output (programmable IOL = 5mA, IOH = -5mA pull-up control and IOL = 2mA, IOH = -2mA) ■ 2 different CMOS hysteresis inputs with input shutdown function * Pout ■ Automotive input with input shutdown function ■ TTL input with input shutdown function * ■ Programmable pull-up resistor: 50kΩ approx. Nout *CY96F345Dyy or CY96F345Fyy: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported R Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Document Number: 002-04579 Rev. *B Page 13 of 111 CY96340 Series Type Circuit Remarks I ■ CMOS level output (programmable IOL = 5mA, IOH = -5mA Pull-up control and IOL = 2mA, IOH = -2mA) ■ 2 different CMOS hysteresis inputs with input shutdown function * Pout ■ Automotive input with input shutdown function ■ TTL input with input shutdown function * ■ Programmable pull-up resistor: 50kΩ approx. Nout ■ Analog input *CY96F345Dyy or CY96F345Fyy: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported R Hysteresis input Standby control for input shutdown Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Analog input ■ CMOS level output (IOL = 3mA, IOH = -3mA) N pull-up control ■ 2 different CMOS hysteresis inputs with input shutdown function * ■ Automotive input with input shutdown function Pout ■ TTL input with input shutdown function * ■ Programmable pull-up resistor: 50kΩ approx. *CY96F345Dyy or CY96F345Fyy: Only Automotive input Nout and CMOS hysteresis input (0.7/0.3) are supported R Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Document Number: 002-04579 Rev. *B Page 14 of 111 CY96340 Series 7. Memory Map CY96(F)34x CY96V300B FF:FFFFH USER ROM / Emulation ROM External Bus[4] DE:0000H External Bus External Bus Boot-ROM Boot-ROM 10:0000H 0F:E000H 0F:0000H Reserved Reserved DATA FLASH / 0E:0000H 0C:0000H Reserved[4] External RAM Reserved 02:0000H Internal RAM bank 1 RAMEND1[2] RAMSTART1[2] 01:0000H ROM/RAM MIRROR Reserved Internal RAM bank 1 Reserved RAM availability depending on the device ROM/RAM MIRROR 00:8000H Internal RAM Internal RAM RAMSTART0[2] bank 0 bank 0 Reserved External Bus end address[2] RAMSTART0 [3] 00:0C00H External Bus External Bus Peripherals Peripherals GPR[1] GPR[1] DMA DMA External Bus External Bus Peripheral Peripheral 00:0380H 00:0180H 00:0100H 00:00F0H 00:0000H [1]: Unused GPR banks can be used as RAM area [2]: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page. [3]: For EVA device, RAMSTART0 depends on the configuration of the emulated device. [4]: For details about USER ROM area or DATA FLASH area, see the User ROM Memory Map For Flash Devices and User ROM Memory Map for Mask ROM Devices on the following pages. The External Bus area and DMA area are only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. Document Number: 002-04579 Rev. *B Page 15 of 111 CY96340 Series ■ RAM Start/End and External Bus End Addresses Devices Bank 0 RAM size Bank 1 RAM size External Bus end address RAMSTART0 RAMSTART1 RAMEND1 CY96(F)345 8KByte - 00:21FFH 00:6240H - - CY96(F)346,CY96F347 16KByte - 00:21FFH 00:4240H - - CY96F348 24KByte - 00:21FFH 00:2240H - - Document Number: 002-04579 Rev. *B Page 16 of 111 CY96340 Series 8. User ROM Memory Map For Flash Devices CY96F345D CY96F345F Flash size 160kByte +64KByte Data Flash Alternative mode CPU address Flash memory mode address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH DE:0000H 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H 0E:FFFFH 0E:FF00H 0E:FEFFH 0E:0000H 0D:FFFFH 0D:C000H 0D:BFFFH 0D:8000H 0D:7FFFH 0D:4000H 0D:3FFFH 0D:0000H 0C:FFFFH 0C:0000H (0E:FFFFH) (0E:FF00H) SDA0-256 [2] Reserved (0F:FFFFH) (0F:C000H) (0F:BFFFH) (0F:8000H) (0F:7FFFH) (0F:4000H) (0F:3FFFH) (0F:0000H) SDA4-16K S39 - 64K S38 - 64K Flash A External bus Reserved 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H SA3 - 8K SA2 - 8K SA1 - 8K Flash A SA0 - 8K [1] Reserved SDA3-16K SDA2-16K Data Flash A Data Flash A SDA1-16K Reserved [1]: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH [2]: Sector SDA0 contains the ROM Configuration Block RCBDA at CPU address DE:FF00H - DE:FF2FH Document Number: 002-04579 Rev. *B Page 17 of 111 CY96340 Series Alternative mode CPU address Flash memory mode address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH DE:0000H 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H CY96F346Y CY96F346R CY96F346A CY96F347Y CY96F347R CY96F347A Flash size 288kByte Flash size 416kByte S39 - 64K S39 - 64K S38 - 64K S38 - 64K S37 - 64K S37 - 64K S36 - 64K S36 - 64K Flash A S35 - 64K S34 - 64K External bus External bus Reserved Reserved SA3 - 8K SA3 - 8K SA2 - 8K SA2 - 8K SA1 - 8K SA1 - 8K SA0 - 8K [1] Reserved SA0 - 8K [1] Reserved Flash A [1]: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH Document Number: 002-04579 Rev. *B Page 18 of 111 CY96340 Series Alternative mode CPU address Flash memory mode address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH DE:8000H DE:7FFFH DE:6000H DE:5FFFH DE:4000H DE:3FFFH DE:2000H DE:1FFFH DE:0000H 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H 1E:7FFFH 1E:6000H 1E:5FFFH 1E:4000H 1E:3FFFH 1E:2000H 1E:1FFFH 1E:0000H CY96F348Y CY96F348R CY96F348A CY96F348T CY96F348H CY96F348C Flash size 544kByte Flash size 576kByte S39 - 64K S39 - 64K S38 - 64K S38 - 64K S37 - 64K S37 - 64K S36 - 64K S36 - 64K S35 - 64K S35 - 64K S34 - 64K S34 - 64K S33 - 64K S33 - 64K S32 - 64K S32 - 64K External bus External bus Reserved Reserved SA3 - 8K SA3 - 8K SA2 - 8K SA2 - 8K SA1 - 8K SA1 - 8K SA0 - 8K [1] SA0 - 8K [1] Reserved Flash A Flash A SB3 - 8K Reserved SB2 - 8K SB1 - 8K Flash B SB0 - 8K [2] [1]: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH [2]: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000H - DE:002FH Document Number: 002-04579 Rev. *B Page 19 of 111 CY96340 Series 9. User ROM Memory Map for Mask ROM Devices CPU address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:0080H DF:007FH DF:0000H DE:FFFFH DE:0000H Document Number: 002-04579 Rev. *B CY96345 CY96346 ROM size 160kByte ROM size 288kByte 128K ROM 256K ROM Reserved External bus External bus Reserved Reserved 32K ROM 32K ROM ROM configuration block RCB ROM configuration block RCB Reserved Reserved Page 20 of 111 CY96340 Series 10. Serial Programming Communication Interface Table 3: USART pins for Flash serial programming (MD[2:0] = 010, Serial Communication mode) CY96F34x Pin number Pin number USART Number Normal function LQFP-100 QFP-100 57 59 58 60 59 61 SCK0 60 62 SIN1 61 63 62 64 SCK1 22 24 SIN2 23 25 24 26 SCK2 85 87 SIN3 86 88 87 89 SIN0 USART0 USART1 USART2 USART3 SOT0 SOT1 SOT2 SOT3 SCK3 Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor to support at least port P00_1 on pin 76/78.If handshaking is used by the tool but P00_1 is not available in customer’s application, Cypress suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. Document Number: 002-04579 Rev. *B Page 21 of 111 CY96340 Series 11. I/O Map Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000000H I/O Port P00 - Port Data Register PDR00 R/W 000001H I/O Port P01 - Port Data Register PDR01 R/W 000002H I/O Port P02 - Port Data Register PDR02 R/W 000003H I/O Port P03 - Port Data Register PDR03 R/W 000004H I/O Port P04 - Port Data Register PDR04 R/W 000005H I/O Port P05 - Port Data Register PDR05 R/W 000006H I/O Port P06 - Port Data Register PDR06 R/W 000007H I/O Port P07 - Port Data Register PDR07 R/W 000008H I/O Port P08 - Port Data Register PDR08 R/W 000009H I/O Port P09 - Port Data Register PDR09 R/W 00000AH I/O Port P10 - Port Data Register PDR10 R/W 00000BH-000017H Reserved - 000018H ADC0 - Control Status register Low ADCSL 000019H ADC0 - Control Status register High ADCSH 00001AH ADC0 - Data Register Low ADCRL 00001BH ADC0 - Data Register High ADCRH 00001CH ADC0 - Setting Register 00001DH ADC0 - Setting Register 00001EH ADC0 - Extended Configuration Register 00001FH Reserved 000020H FRT0 - Data register of free-running timer 000021H FRT0 - Data register of free-running timer 000022H FRT0 - Control status register of free-running timer Low TCCSL0 000023H FRT0 - Control status register of free-running timer High TCCSH0 000024H FRT1 - Data register of free-running timer 000025H FRT1 - Data register of free-running timer 000026H FRT1 - Control status register of free-running timer Low TCCSL1 000027H FRT1 - Control status register of free-running timer High TCCSH1 R/W 000028H OCU0 - Output Compare Control Status OCS0 R/W 000029H OCU1 - Output Compare Control Status OCS1 R/W 00002AH OCU0 - Compare Register Document Number: 002-04579 Rev. *B ADCS R/W R/W ADCR R R ADSR R/W R/W ADECR R/W TCDT0 R/W R/W TCCS0 R/W R/W TCDT1 R/W R/W TCCS1 OCCP0 R/W R/W Page 22 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 00002BH OCU0 - Compare Register 00002CH OCU1 - Compare Register 00002DH OCU1 - Compare Register 00002EH OCU2 - Output Compare Control Status OCS2 R/W 00002FH OCU3 - Output Compare Control Status OCS3 R/W 000030H OCU2 - Compare Register 000031H OCU2 - Compare Register 000032H OCU3 - Compare Register 000033H OCU3 - Compare Register 000034H OCU4 - Output Compare Control Status OCS4 R/W 000035H OCU5 - Output Compare Control Status OCS5 R/W 000036H OCU4 - Compare Register 000037H OCU4 - Compare Register 000038H OCU5 - Compare Register 000039H OCU5 - Compare Register 00003AH OCU6 - Output Compare Control Status OCS6 R/W 00003BH OCU7 - Output Compare Control Status OCS7 R/W 00003CH OCU6 - Compare Register 00003DH OCU6 - Compare Register 00003EH OCU7 - Compare Register 00003FH OCU7 - Compare Register 000040H ICU0/ICU1 - Control Status Register ICS01 R/W 000041H ICU0/ICU1 - Edge register ICE01 R/W 000042H ICU0 - Capture Register Low IPCPL0 000043H ICU0 - Capture Register High IPCPH0 000044H ICU1 - Capture Register Low IPCPL1 000045H ICU1 - Capture Register High IPCPH1 R 000046H ICU2/ICU3 - Control Status Register ICS23 R/W 000047H ICU2/ICU3 - Edge register ICE23 R/W 000048H ICU2 - Capture Register Low IPCPL2 000049H ICU2 - Capture Register High IPCPH2 00004AH ICU3 - Capture Register Low IPCPL3 00004BH ICU3 - Capture Register High IPCPH3 Document Number: 002-04579 Rev. *B R/W OCCP1 R/W R/W OCCP2 R/W R/W OCCP3 R/W R/W OCCP4 R/W R/W OCCP5 R/W R/W OCCP6 R/W R/W OCCP7 R/W R/W IPCP0 R R IPCP1 IPCP2 R R R IPCP3 R R Page 23 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Abbreviation 8-bit access Abbreviation 16-bit access Address Register 00004CH ICU4/ICU5 - Control Status Register ICS45 R/W 00004DH ICU4/ICU5 - Edge register ICE45 R/W 00004EH ICU4 - Capture Register Low IPCPL4 00004FH ICU4 - Capture Register High IPCPH4 000050H ICU5 - Capture Register Low IPCPL5 000051H ICU5 - Capture Register High IPCPH5 R 000052H ICU6/ICU7 - Control Status Register ICS67 R/W 000053H ICU6/ICU7 - Edge register ICE67 R/W 000054H ICU6 - Capture Register Low IPCPL6 000055H ICU6 - Capture Register High IPCPH6 000056H ICU7 - Capture Register Low IPCPL7 000057H ICU7 - Capture Register High IPCPH7 R 000058H EXTINT0 - External Interrupt Enable Register ENIR0 R/W 000059H EXTINT0 - External Interrupt Interrupt request Register EIRR0 R/W 00005AH EXTINT0 - External Interrupt Level Select Low ELVRL0 00005BH EXTINT0 - External Interrupt Level Select High ELVRH0 R/W 00005CH EXTINT1 - External Interrupt Enable Register ENIR1 R/W 00005DH EXTINT1 - External Interrupt Interrupt request Register EIRR1 R/W 00005EH EXTINT1 - External Interrupt Level Select Low ELVRL1 00005FH EXTINT1 - External Interrupt Level Select High ELVRH1 000060H RLT0 - Timer Control Status Register Low TMCSRL0 000061H RLT0 - Timer Control Status Register High TMCSRH0 000062H RLT0 - Reload Register - for writing TMRLR0 W 000062H RLT0 - Reload Register - for reading TMR0 R 000063H RLT0 - Reload Register - for writing W 000063H RLT0 - Reload Register - for reading R 000064H RLT1 - Timer Control Status Register Low TMCSRL1 000065H RLT1 - Timer Control Status Register High TMCSRH1 000066H RLT1 - Reload Register - for writing TMRLR1 W 000066H RLT1 - Reload Register - for reading TMR1 R 000067H RLT1 - Reload Register - for writing W 000067H RLT1 - Reload Register - for reading R Document Number: 002-04579 Rev. *B IPCP4 Access R R IPCP5 IPCP6 R R R IPCP7 ELVR0 ELVR1 R R/W R/W R/W TMCSR0 R/W R/W TMCSR1 R/W R/W Page 24 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access TMCSR2 R/W 000068H RLT2 - Timer Control Status Register Low TMCSRL2 000069H RLT2 - Timer Control Status Register High TMCSRH2 00006AH RLT2 - Reload Register - for writing TMRLR2 W 00006AH RLT2 - Reload Register - for reading TMR2 R 00006BH RLT2 - Reload Register - for writing W 00006BH RLT2 - Reload Register - for reading R 00006CH RLT3 - Timer Control Status Register Low TMCSRL3 00006DH RLT3 - Timer Control Status Register High TMCSRH3 00006EH RLT3 - Reload Register - for writing TMRLR3 W 00006EH RLT3 - Reload Register - for reading TMR3 R 00006FH RLT3 - Reload Register - for writing W 00006FH RLT3 - Reload Register - for reading R 000070H RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) TMCSRL6 000071H RLT6 - Timer Control Status Register High (dedic. RLT for PPG) TMCSRH6 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for writing TMRLR6 W 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for reading TMR6 R 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for writing W 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for reading R 000074H PPG3-PPG0 - General Control register 1 Low GCN1L0 000075H PPG3-PPG0 - General Control register 1 High GCN1H0 000076H PPG3-PPG0 - General Control register 2 Low GCN2L0 000077H PPG3-PPG0 - General Control register 2 High GCN2H0 000078H PPG0 - Timer register 000079H PPG0 - Timer register 00007AH PPG0 - Period setting register 00007BH PPG0 - Period setting register 00007CH PPG0 - Duty cycle register 00007DH PPG0 - Duty cycle register 00007EH PPG0 - Control status register Low PCNL0 00007FH PPG0 - Control status register High PCNH0 000080H PPG1 - Timer register 000081H PPG1 - Timer register Document Number: 002-04579 Rev. *B R/W TMCSR3 R/W R/W TMCSR6 R/W R/W GCN10 R/W R/W GCN20 R/W R/W PTMR0 R R PCSR0 W W PDUT0 W W PCN0 R/W R/W PTMR1 R R Page 25 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access 000082H PPG1 - Period setting register 000083H PPG1 - Period setting register 000084H PPG1 - Duty cycle register 000085H PPG1 - Duty cycle register 000086H PPG1 - Control status register Low PCNL1 000087H PPG1 - Control status register High PCNH1 000088H PPG2 - Timer register 000089H PPG2 - Timer register 00008AH PPG2 - Period setting register 00008BH PPG2 - Period setting register 00008CH PPG2 - Duty cycle register 00008DH PPG2 - Duty cycle register 00008EH PPG2 - Control status register Low PCNL2 00008FH PPG2 - Control status register High PCNH2 000090H PPG3 - Timer register 000091H PPG3 - Timer register 000092H PPG3 - Period setting register 000093H PPG3 - Period setting register 000094H PPG3 - Duty cycle register 000095H PPG3 - Duty cycle register 000096H PPG3 - Control status register Low PCNL3 000097H PPG3 - Control status register High PCNH3 000098H PPG7-PPG4 - General Control register 1 Low GCN1L1 000099H PPG7-PPG4 - General Control register 1 High GCN1H1 00009AH PPG7-PPG4 - General Control register 2 Low GCN2L1 00009BH PPG7-PPG4 - General Control register 2 High GCN2H1 00009CH PPG4 - Timer register 00009DH PPG4 - Timer register 00009EH PPG4 - Period setting register 00009FH PPG4 - Period setting register 0000A0H PPG4 - Duty cycle register 0000A1H PPG4 - Duty cycle register Document Number: 002-04579 Rev. *B Abbreviation 16-bit access Access PCSR1 W W PDUT1 W W PCN1 R/W R/W PTMR2 R R PCSR2 W W PDUT2 W W PCN2 R/W R/W PTMR3 R R PCSR3 W W PDUT3 W W PCN3 R/W R/W GCN11 R/W R/W GCN21 R/W R/W PTMR4 R R PCSR4 W W PDUT4 W W Page 26 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access PCN4 R/W 0000A2H PPG4 - Control status register Low PCNL4 0000A3H PPG4 - Control status register High PCNH4 0000A4H PPG5 - Timer register 0000A5H PPG5 - Timer register 0000A6H PPG5 - Period setting register 0000A7H PPG5 - Period setting register 0000A8H PPG5 - Duty cycle register 0000A9H PPG5 - Duty cycle register 0000AAH PPG5 - Control status register Low PCNL5 0000ABH PPG5 - Control status register High PCNH5 R/W 0000ACH I2C0 - Bus Status Register IBSR0 R 0000ADH I2C0 - Bus Control Register IBCR0 R/W 0000AEH I2C0 - Ten bit Slave address Register Low ITBAL0 0000AFH I2C0 - Ten bit Slave address Register High ITBAH0 0000B0H I2C0 - Ten bit Address mask Register Low ITMKL0 0000B1H I2C0 - Ten bit Address mask Register High ITMKH0 R/W 0000B2H I2C0 - Seven bit Slave address Register ISBA0 R/W 0000B3H I2C0 - Seven bit Address mask Register ISMK0 R/W 0000B4H I2C0 - Data Register IDAR0 R/W 0000B5H I2C0 - Clock Control Register ICCR0 R/W 0000B6H I2C1 - Bus Status Register IBSR1 R 0000B7H I2C1 - Bus Control Register IBCR1 R/W 0000B8H I2C1 - Ten bit Slave address Register Low ITBAL1 0000B9H I2C1 - Ten bit Slave address Register High ITBAH1 0000BAH I2C1 - Ten bit Address mask Register Low ITMKL1 0000BBH I2C1 - Ten bit Address mask Register High ITMKH1 R/W 0000BCH I2C1 - Seven bit Slave address Register ISBA1 R/W 0000BDH I2C1 - Seven bit Address mask Register ISMK1 R/W 0000BEH I2C1 - Data Register IDAR1 R/W 0000BFH I2C1 - Clock Control Register ICCR1 R/W 0000C0H USART0 - Serial Mode Register SMR0 R/W 0000C1H USART0 - Serial Control Register SCR0 R/W Document Number: 002-04579 Rev. *B R/W PTMR5 R R PCSR5 W W PDUT5 W W PCN5 ITBA0 R/W R/W R/W ITMK0 ITBA1 R/W R/W R/W ITMK1 R/W Page 27 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0000C2H USART0 - TX Register TDR0 W 0000C2H USART0 - RX Register RDR0 R 0000C3H USART0 - Serial Status SSR0 R/W 0000C4H USART0 - Control/Com. Register ECCR0 R/W 0000C5H USART0 - Ext. Status Register ESCR0 R/W 0000C6H USART0 - Baud Rate Generator Register Low BGRL0 0000C7H USART0 - Baud Rate Generator Register High BGRH0 R/W 0000C8H USART0 - Extended Serial Interrupt Register ESIR0 R/W 0000C9H Reserved 0000CAH USART1 - Serial Mode Register SMR1 R/W 0000CBH USART1 - Serial Control Register SCR1 R/W 0000CCH USART1 - TX Register TDR1 W 0000CCH USART1 - RX Register RDR1 R 0000CDH USART1 - Serial Status SSR1 R/W 0000CEH USART1 - Control/Com. Register ECCR1 R/W 0000CFH USART1 - Ext. Status Register ESCR1 R/W 0000D0H USART1 - Baud Rate Generator Register Low BGRL1 0000D1H USART1 - Baud Rate Generator Register High BGRH1 R/W 0000D2H USART1 - Extended Serial Interrupt Register ESIR1 R/W 0000D3H Reserved 0000D4H USART2 - Serial Mode Register SMR2 R/W 0000D5H USART2 - Serial Control Register SCR2 R/W 0000D6H USART2 - TX Register TDR2 W 0000D6H USART2 - RX Register RDR2 R 0000D7H USART2 - Serial Status SSR2 R/W 0000D8H USART2 - Control/Com. Register ECCR2 R/W 0000D9H USART2 - Ext. Status Register ESCR2 R/W 0000DAH USART2 - Baud Rate Generator Register Low BGRL2 0000DBH USART2 - Baud Rate Generator Register High BGRH2 R/W 0000DCH USART2 - Extended Serial Interrupt Register ESIR2 R/W 0000DDH Reserved 0000DEH USART3 - Serial Mode Register Document Number: 002-04579 Rev. *B BGR0 R/W - BGR1 R/W - BGR2 R/W SMR3 R/W Page 28 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0000DFH USART3 - Serial Control Register SCR3 R/W 0000E0H USART3 - TX Register TDR3 W 0000E0H USART3 - RX Register RDR3 R 0000E1H USART3 - Serial Status SSR3 R/W 0000E2H USART3 - Control/Com. Register ECCR3 R/W 0000E3H USART3 - Ext. Status Register ESCR3 R/W 0000E4H USART3 - Baud Rate Generator Register Low BGRL3 0000E5H USART3 - Baud Rate Generator Register High BGRH3 R/W 0000E6H USART3 - Extended Serial Interrupt Register ESIR3 R/W 0000E7H-0000EFH Reserved 0000F0H-0000FFH External Bus area BGR3 R/W EXTBUS0 R/W 000100H DMA0 - Buffer address pointer low byte BAPL0 R/W 000101H DMA0 - Buffer address pointer middle byte BAPM0 R/W 000102H DMA0 - Buffer address pointer high byte BAPH0 R/W 000103H DMA0 - DMA control register DMACS0 R/W 000104H DMA0 - I/O register address pointer low byte IOAL0 000105H DMA0 - I/O register address pointer high byte IOAH0 000106H DMA0 - Data counter low byte DCTL0 000107H DMA0 - Data counter high byte DCTH0 R/W 000108H DMA1 - Buffer address pointer low byte BAPL1 R/W 000109H DMA1 - Buffer address pointer middle byte BAPM1 R/W 00010AH DMA1 - Buffer address pointer high byte BAPH1 R/W 00010BH DMA1 - DMA control register DMACS1 R/W 00010CH DMA1 - I/O register address pointer low byte IOAL1 00010DH DMA1 - I/O register address pointer high byte IOAH1 00010EH DMA1 - Data counter low byte DCTL1 00010FH DMA1 - Data counter high byte DCTH1 R/W 000110H DMA2 - Buffer address pointer low byte BAPL2 R/W 000111H DMA2 - Buffer address pointer middle byte BAPM2 R/W 000112H DMA2 - Buffer address pointer high byte BAPH2 R/W 000113H DMA2 - DMA control register DMACS2 R/W 000114H DMA2 - I/O register address pointer low byte Document Number: 002-04579 Rev. *B IOAL2 IOA0 R/W R/W DCT0 IOA1 R/W R/W R/W DCT1 IOA2 R/W R/W Page 29 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000115H DMA2 - I/O register address pointer high byte IOAH2 000116H DMA2 - Data counter low byte DCTL2 000117H DMA2 - Data counter high byte DCTH2 R/W 000118H DMA3 - Buffer address pointer low byte BAPL3 R/W 000119H DMA3 - Buffer address pointer middle byte BAPM3 R/W 00011AH DMA3 - Buffer address pointer high byte BAPH3 R/W 00011BH DMA3 - DMA control register DMACS3 R/W 00011CH DMA3 - I/O register address pointer low byte IOAL3 00011DH DMA3 - I/O register address pointer high byte IOAH3 00011EH DMA3 - Data counter low byte DCTL3 00011FH DMA3 - Data counter high byte DCTH3 R/W 000120H DMA4 - Buffer address pointer low byte BAPL4 R/W 000121H DMA4 - Buffer address pointer middle byte BAPM4 R/W 000122H DMA4 - Buffer address pointer high byte BAPH4 R/W 000123H DMA4 - DMA control register DMACS4 R/W 000124H DMA4 - I/O register address pointer low byte IOAL4 000125H DMA4 - I/O register address pointer high byte IOAH4 000126H DMA4 - Data counter low byte DCTL4 000127H DMA4 - Data counter high byte DCTH4 R/W 000128H DMA5 - Buffer address pointer low byte BAPL5 R/W 000129H DMA5 - Buffer address pointer middle byte BAPM5 R/W 00012AH DMA5 - Buffer address pointer high byte BAPH5 R/W 00012BH DMA5 - DMA control register DMACS5 R/W 00012CH DMA5 - I/O register address pointer low byte IOAL5 00012DH DMA5 - I/O register address pointer high byte IOAH5 00012EH DMA5 - Data counter low byte DCTL5 00012FH DMA5 - Data counter high byte DCTH5 000130H-00017FH Reserved 000180H-00037FH CPU - General Purpose registers (RAM access) R/W DCT2 IOA3 R/W R/W R/W DCT3 IOA4 R/W R/W R/W DCT4 IOA5 R/W R/W R/W DCT5 R/W R/W - GPR_RAM R/W 000380H DMA0 - Interrupt select DISEL0 R/W 000381H DMA1 - Interrupt select DISEL1 R/W 000382H DMA2 - Interrupt select DISEL2 R/W Document Number: 002-04579 Rev. *B Page 30 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000383H DMA3 - Interrupt select DISEL3 R/W 000384H DMA4 - Interrupt select DISEL4 R/W 000385H DMA5 - Interrupt select DISEL5 R/W 000386H-00038FH Reserved - 000390H DMA - Status register low byte DSRL 000391H DMA - Status register high byte DSRH 000392H DMA - Stop status register low byte DSSRL 000393H DMA - Stop status register high byte DSSRH 000394H DMA - Enable register low byte DERL 000395H DMA - Enable register high byte DERH 000396H-00039FH DSR R/W R/W DSSR R/W R/W DER R/W R/W Reserved - 0003A0H Interrupt level register ILR 0003A1H Interrupt index register IDX 0003A2H Interrupt vector table base register Low TBRL 0003A3H Interrupt vector table base register High TBRH R/W 0003A4H Delayed Interrupt register DIRR R/W 0003A5H Non Maskable Interrupt register NMI R/W 0003A6H-0003ABH ICR R/W R/W TBR Reserved R/W - 0003ACH EDSU communication interrupt selection Low EDSU2L 0003ADH EDSU communication interrupt selection High EDSU2H R/W 0003AEH ROM mirror control register ROMM R/W 0003AFH EDSU configuration register EDSU R/W 0003B0H Memory patch control/status register ch 0/1 0003B1H Memory patch control/status register ch 0/1 0003B2H Memory patch control/status register ch 2/3 0003B3H Memory patch control/status register ch 2/3 0003B4H Memory patch control/status register ch 4/5 0003B5H Memory patch control/status register ch 4/5 0003B6H Memory patch control/status register ch 6/7 0003B7H Memory patch control/status register ch 6/7 0003B8H Memory Patch function - Patch address 0 low PFAL0 R/W 0003B9H Memory Patch function - Patch address 0 middle PFAM0 R/W Document Number: 002-04579 Rev. *B EDSU2 PFCS0 R/W R/W R/W PFCS1 R/W R/W PFCS2 R/W R/W PFCS3 R/W R/W Page 31 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0003BAH Memory Patch function - Patch address 0 high PFAH0 R/W 0003BBH Memory Patch function - Patch address 1 low PFAL1 R/W 0003BCH Memory Patch function - Patch address 1 middle PFAM1 R/W 0003BDH Memory Patch function - Patch address 1 high PFAH1 R/W 0003BEH Memory Patch function - Patch address 2 low PFAL2 R/W 0003BFH Memory Patch function - Patch address 2 middle PFAM2 R/W 0003C0H Memory Patch function - Patch address 2 high PFAH2 R/W 0003C1H Memory Patch function - Patch address 3 low PFAL3 R/W 0003C2H Memory Patch function - Patch address 3 middle PFAM3 R/W 0003C3H Memory Patch function - Patch address 3 high PFAH3 R/W 0003C4H Memory Patch function - Patch address 4 low PFAL4 R/W 0003C5H Memory Patch function - Patch address 4 middle PFAM4 R/W 0003C6H Memory Patch function - Patch address 4 high PFAH4 R/W 0003C7H Memory Patch function - Patch address 5 low PFAL5 R/W 0003C8H Memory Patch function - Patch address 5 middle PFAM5 R/W 0003C9H Memory Patch function - Patch address 5 high PFAH5 R/W 0003CAH Memory Patch function - Patch address 6 low PFAL6 R/W 0003CBH Memory Patch function - Patch address 6 middle PFAM6 R/W 0003CCH Memory Patch function - Patch address 6 high PFAH6 R/W 0003CDH Memory Patch function - Patch address 7 low PFAL7 R/W 0003CEH Memory Patch function - Patch address 7 middle PFAM7 R/W 0003CFH Memory Patch function - Patch address 7 high PFAH7 R/W 0003D0H Memory Patch function - Patch data 0 Low PFDL0 0003D1H Memory Patch function - Patch data 0 High PFDH0 0003D2H Memory Patch function - Patch data 1 Low PFDL1 0003D3H Memory Patch function - Patch data 1 High PFDH1 0003D4H Memory Patch function - Patch data 2 Low PFDL2 0003D5H Memory Patch function - Patch data 2 High PFDH2 0003D6H Memory Patch function - Patch data 3 Low PFDL3 0003D7H Memory Patch function - Patch data 3 High PFDH3 0003D8H Memory Patch function - Patch data 4 Low PFDL4 0003D9H Memory Patch function - Patch data 4 High PFDH4 Document Number: 002-04579 Rev. *B PFD0 R/W R/W PFD1 R/W R/W PFD2 R/W R/W PFD3 R/W R/W PFD4 R/W R/W Page 32 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access PFD5 R/W 0003DAH Memory Patch function - Patch data 5 Low PFDL5 0003DBH Memory Patch function - Patch data 5 High PFDH5 0003DCH Memory Patch function - Patch data 6 Low PFDL6 0003DDH Memory Patch function - Patch data 6 High PFDH6 0003DEH Memory Patch function - Patch data 7 Low PFDL7 0003DFH Memory Patch function - Patch data 7 High PFDH7 R/W 0003E0H Data Flash Control and Status register A DFCSA R/W 0003E1H Data Flash Write command sequencer Control register A DFWCA R/W 0003E2H Data Flash Write command sequencer Status register A DFWSA R/W 0003E3H-0003F0H R/W PFD6 R/W R/W PFD7 Reserved R/W - 0003F1H Memory Control Status Register A MCSRA 0003F2H Memory Timing Configuration Register A Low MTCRAL 0003F3H Memory Timing Configuration Register A High MTCRAH 0003F4H Reserved 0003F5H Memory Control Status Register B MCSRB 0003F6H Memory Timing Configuration Register B Low MTCRBL 0003F7H Memory Timing Configuration Register B High MTCRBH R/W 0003F8H Flash Memory Write Control register 0 FMWC0 R/W 0003F9H Flash Memory Write Control register 1 FMWC1 R/W 0003FAH Flash Memory Write Control register 2 FMWC2 R/W 0003FBH Flash Memory Write Control register 3 FMWC3 R/W 0003FCH Flash Memory Write Control register 4 FMWC4 R/W 0003FDH Flash Memory Write Control register 5 FMWC5 R/W 0003FEH-0003FFH R/W MTCRA R/W R/W R/W MTCRB Reserved R/W - 000400H Standby Mode control register SMCR R/W 000401H Clock select register CKSR R/W 000402H Clock Stabilization select register CKSSR R/W 000403H Clock monitor register CKMR R 000404H Clock Frequency control register Low CKFCRL 000405H Clock Frequency control register High CKFCRH 000406H PLL Control register Low PLLCRL 000407H PLL Control register High PLLCRH Document Number: 002-04579 Rev. *B CKFCR R/W R/W PLLCR R/W R/W Page 33 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000408H RC clock timer control register RCTCR R/W 000409H Main clock timer control register MCTCR R/W 00040AH Sub clock timer control register SCTCR R/W 00040BH Reset cause and clock status register with clear function RCCSRC R 00040CH Reset configuration register RCR R/W 00040DH Reset cause and clock status register RCCSR R 00040EH Watch dog timer configuration register WDTC R/W 00040FH Watch dog timer clear pattern register WDTCP W 000410H-000414H Reserved 000415H Clock output activation register 000416H COAR R/W Clock output configuration register 0 COCR0 R/W 000417H Clock output configuration register 1 COCR1 R/W 000418H Clock Modulator control register CMCR R/W 000419H Reserved 00041AH Clock Modulator Parameter register Low CMPRL 00041BH Clock Modulator Parameter register High CMPRH 00041CH-00042BH - Reserved CMPR R/W R/W - 00042CH Voltage Regulator Control register VRCR R/W 00042DH Clock Input and LVD Control Register CILCR R/W 00042EH-00042FH Reserved - 000430H I/O Port P00 - Data Direction Register DDR00 R/W 000431H I/O Port P01 - Data Direction Register DDR01 R/W 000432H I/O Port P02 - Data Direction Register DDR02 R/W 000433H I/O Port P03 - Data Direction Register DDR03 R/W 000434H I/O Port P04 - Data Direction Register DDR04 R/W 000435H I/O Port P05 - Data Direction Register DDR05 R/W 000436H I/O Port P06 - Data Direction Register DDR06 R/W 000437H I/O Port P07 - Data Direction Register DDR07 R/W 000438H I/O Port P08 - Data Direction Register DDR08 R/W 000439H I/O Port P09 - Data Direction Register DDR09 R/W 00043AH I/O Port P10 - Data Direction Register DDR10 R/W 00043BH-000443H Reserved Document Number: 002-04579 Rev. *B - Page 34 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000444H I/O Port P00 - Port Input Enable Register PIER00 R/W 000445H I/O Port P01 - Port Input Enable Register PIER01 R/W 000446H I/O Port P02 - Port Input Enable Register PIER02 R/W 000447H I/O Port P03 - Port Input Enable Register PIER03 R/W 000448H I/O Port P04 - Port Input Enable Register PIER04 R/W 000449H I/O Port P05 - Port Input Enable Register PIER05 R/W 00044AH I/O Port P06 - Port Input Enable Register PIER06 R/W 00044BH I/O Port P07 - Port Input Enable Register PIER07 R/W 00044CH I/O Port P08 - Port Input Enable Register PIER08 R/W 00044DH I/O Port P09 - Port Input Enable Register PIER09 R/W 00044EH I/O Port P10 - Port Input Enable Register PIER10 R/W 00044FH-000457H Reserved - 000458H I/O Port P00 - Port Input Level Register PILR00 R/W 000459H I/O Port P01 - Port Input Level Register PILR01 R/W 00045AH I/O Port P02 - Port Input Level Register PILR02 R/W 00045BH I/O Port P03 - Port Input Level Register PILR03 R/W 00045CH I/O Port P04 - Port Input Level Register PILR04 R/W 00045DH I/O Port P05 - Port Input Level Register PILR05 R/W 00045EH I/O Port P06 - Port Input Level Register PILR06 R/W 00045FH I/O Port P07 - Port Input Level Register PILR07 R/W 000460H I/O Port P08 - Port Input Level Register PILR08 R/W 000461H I/O Port P09 - Port Input Level Register PILR09 R/W 000462H I/O Port P10 - Port Input Level Register PILR10 R/W 000463H-00046BH Reserved - 00046CH I/O Port P00 - Extended Port Input Level Register EPILR00 R/W 00046DH I/O Port P01 - Extended Port Input Level Register EPILR01 R/W 00046EH I/O Port P02 - Extended Port Input Level Register EPILR02 R/W 00046FH I/O Port P03 - Extended Port Input Level Register EPILR03 R/W 000470H I/O Port P04 - Extended Port Input Level Register EPILR04 R/W 000471H I/O Port P05 - Extended Port Input Level Register EPILR05 R/W 000472H I/O Port P06 - Extended Port Input Level Register EPILR06 R/W 000473H I/O Port P07 - Extended Port Input Level Register EPILR07 R/W Document Number: 002-04579 Rev. *B Page 35 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000474H I/O Port P08 - Extended Port Input Level Register EPILR08 R/W 000475H I/O Port P09 - Extended Port Input Level Register EPILR09 R/W 000476H I/O Port P10 - Extended Port Input Level Register EPILR10 R/W 000477H-00047FH Reserved - 000480H I/O Port P00 - Port Output Drive Register PODR00 R/W 000481H I/O Port P01 - Port Output Drive Register PODR01 R/W 000482H I/O Port P02 - Port Output Drive Register PODR02 R/W 000483H I/O Port P03 - Port Output Drive Register PODR03 R/W 000484H I/O Port P04 - Port Output Drive Register PODR04 R/W 000485H I/O Port P05 - Port Output Drive Register PODR05 R/W 000486H I/O Port P06 - Port Output Drive Register PODR06 R/W 000487H I/O Port P07 - Port Output Drive Register PODR07 R/W 000488H I/O Port P08 - Port Output Drive Register PODR08 R/W 000489H I/O Port P09 - Port Output Drive Register PODR09 R/W 00048AH I/O Port P10 - Port Output Drive Register PODR10 R/W 00048BH-00049BH Reserved - 00049CH I/O Port P08 - Port High Drive Register PHDR08 R/W 00049DH I/O Port P09 - Port High Drive Register PHDR09 R/W 00049EH I/O Port P10 - Port High Drive Register PHDR10 R/W 00049FH-0004A7H Reserved - 0004A8H I/O Port P00 - Pull-Up resistor Control Register PUCR00 R/W 0004A9H I/O Port P01 - Pull-Up resistor Control Register PUCR01 R/W 0004AAH I/O Port P02 - Pull-Up resistor Control Register PUCR02 R/W 0004ABH I/O Port P03 - Pull-Up resistor Control Register PUCR03 R/W 0004ACH I/O Port P04 - Pull-Up resistor Control Register PUCR04 R/W 0004ADH I/O Port P05 - Pull-Up resistor Control Register PUCR05 R/W 0004AEH I/O Port P06 - Pull-Up resistor Control Register PUCR06 R/W 0004AFH I/O Port P07 - Pull-Up resistor Control Register PUCR07 R/W 0004B0H I/O Port P08 - Pull-Up resistor Control Register PUCR08 R/W 0004B1H I/O Port P09 - Pull-Up resistor Control Register PUCR09 R/W 0004B2H I/O Port P10 - Pull-Up resistor Control Register PUCR10 R/W 0004B3H-0004BBH Reserved Document Number: 002-04579 Rev. *B - Page 36 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0004BCH I/O Port P00 - External Pin State Register EPSR00 R 0004BDH I/O Port P01 - External Pin State Register EPSR01 R 0004BEH I/O Port P02 - External Pin State Register EPSR02 R 0004BFH I/O Port P03 - External Pin State Register EPSR03 R 0004C0H I/O Port P04 - External Pin State Register EPSR04 R 0004C1H I/O Port P05 - External Pin State Register EPSR05 R 0004C2H I/O Port P06 - External Pin State Register EPSR06 R 0004C3H I/O Port P07 - External Pin State Register EPSR07 R 0004C4H I/O Port P08 - External Pin State Register EPSR08 R 0004C5H I/O Port P09 - External Pin State Register EPSR09 R 0004C6H I/O Port P10 - External Pin State Register EPSR10 R 0004C7H-0004CFH Reserved - 0004D0H ADC analog input enable register 0 ADER0 R/W 0004D1H ADC analog input enable register 1 ADER1 R/W 0004D2H ADC analog input enable register 2 ADER2 R/W 0004D3H ADC analog input enable register 3 ADER3 R/W 0004D4H ADC analog input enable register 4 ADER4 R/W 0004D5H Reserved 0004D6H Peripheral Resource Relocation Register 0 PRRR0 R/W 0004D7H Peripheral Resource Relocation Register 1 PRRR1 R/W 0004D8H Peripheral Resource Relocation Register 2 PRRR2 R/W 0004D9H Peripheral Resource Relocation Register 3 PRRR3 R/W 0004DAH Peripheral Resource Relocation Register 4 PRRR4 R/W 0004DBH Peripheral Resource Relocation Register 5 PRRR5 R/W 0004DCH Peripheral Resource Relocation Register 6 PRRR6 R/W 0004DDH Peripheral Resource Relocation Register 7 PRRR7 R/W 0004DEH Peripheral Resource Relocation Register 8 PRRR8 R/W 0004DFH Peripheral Resource Relocation Register 9 PRRR9 R/W 0004E0H RTC - Sub Second Register L WTBRL0 0004E1H RTC - Sub Second Register M WTBRH0 R/W 0004E2H RTC - Sub-Second Register H WTBR1 R/W 0004E3H RTC - Second Register WTSR R/W Document Number: 002-04579 Rev. *B - WTBR0 R/W Page 37 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0004E4H RTC - Minutes WTMR R/W 0004E5H RTC - Hour WTHR R/W 0004E6H RTC - Timer Control Extended Register WTCER R/W 0004E7H RTC - Clock select register WTCKSR R/W 0004E8H RTC - Timer Control Register Low WTCRL 0004E9H RTC - Timer Control Register High WTCRH R/W 0004EAH CAL - Calibration unit Control register CUCR R/W 0004EBH Reserved 0004ECH CAL - Duration Timer Data Register Low CUTDL 0004EDH CAL - Duration Timer Data Register High CUTDH 0004EEH CAL - Calibration Timer Register 2 Low CUTR2L 0004EFH CAL - Calibration Timer Register 2 High CUTR2H 0004F0H CAL - Calibration Timer Register 1 Low CUTR1L 0004F1H CAL - Calibration Timer Register 1 High CUTR1H 0004F2H-0004F9H 0004FAH 0004FBH-00053DH WTCR CUTD R/W R/W CUTR2 R R CUTR1 R R Reserved RLT - Timer input select (for Cascading) R/W TMISR R/W Reserved - 00053EH USART7 - Serial Mode Register SMR7 R/W 00053FH USART7 - Serial Control Register SCR7 R/W 000540H USART7 - Serial TX Register TDR7 W 000540H USART7 - Serial RX Register RDR7 R 000541H USART7 - Serial Status Register SSR7 R/W 000542H USART7 - Ext. Control/Com. Register ECCR7 R/W 000543H USART7 - Ext. Status Com. Register ESCR7 R/W 000544H USART7 - Baud Rate Generator Register Low BGRL7 000545H USART7 - Baud Rate Generator Register High BGRH7 R/W 000546H USART7 - Extended Serial Interrupt Register ESIR7 R/W 000547H Reserved 000548H USART8 - Serial Mode Register SMR8 R/W 000549H USART8 - Serial Control Register SCR8 R/W 00054AH USART8 - Serial TX Register TDR8 W 00054AH USART8 - Serial RX Register RDR8 R Document Number: 002-04579 Rev. *B BGR7 R/W - Page 38 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register 00054BH USART8 - Serial Status Register 00054CH Abbreviation 8-bit access Abbreviation 16-bit access Access SSR8 R/W USART8 - Ext. Control/Com. Register ECCR8 R/W 00054DH USART8 - Ext. Status Com. Register ESCR8 R/W 00054EH USART8 - Baud Rate Generator Register Low BGRL8 00054FH USART8 - Baud Rate Generator Register High BGRH8 R/W 000550H USART8 - Extended Serial Interrupt Register ESIR8 R/W 000551H Reserved 000552H USART9 - Serial Mode Register SMR9 R/W 000553H USART9 - Serial Control Register SCR9 R/W 000554H USART9 - Serial TX Register TDR9 W 000554H USART9 - Serial RX Register RDR9 R 000555H USART9 - Serial Status Register SSR9 R/W 000556H USART9 - Ext. Control/Com. Register ECCR9 R/W 000557H USART9 - Ext. Status Com. Register ESCR9 R/W 000558H USART9 - Baud Rate Generator Register Low BGRL9 000559H USART9 - Baud Rate Generator Register High BGRH9 R/W 00055AH USART9 - Extended Serial Interrupt Register ESIR9 R/W 00055BH-00055FH BGR8 - BGR9 Reserved R/W - 000560H ALARM0 - Control Status Register 000561H ALARM0 - Extended Control Status Register 000562H ALARM1 - Control Status Register 000563H ALARM1 - Extended Control Status Register 000564H PPG6 - Timer register 000565H PPG6 - Timer register 000566H PPG6 - Period setting register 000567H PPG6 - Period setting register 000568H PPG6 - Duty cycle register 000569H PPG6 - Duty cycle register 00056AH PPG6 - Control status register Low PCNL6 00056BH PPG6 - Control status register High PCNH6 00056CH PPG7 - Timer register 00056DH PPG7 - Timer register Document Number: 002-04579 Rev. *B R/W ACSR0 R/W AECSR0 R/W ACSR1 R/W AECSR1 R/W PTMR6 R R PCSR6 W W PDUT6 W W PCN6 R/W R/W PTMR7 R R Page 39 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access 00056EH PPG7 - Period setting register 00056FH PPG7 - Period setting register 000570H PPG7 - Duty cycle register 000571H PPG7 - Duty cycle register 000572H PPG7 - Control status register Low PCNL7 000573H PPG7 - Control status register High PCNH7 000574H PPG11-PPG8 - General Control register 1 Low GCN1L2 000575H PPG11-PPG8 - General Control register 1 High GCN1H2 000576H PPG11-PPG8 - General Control register 2 Low GCN2L2 000577H PPG11-PPG8 - General Control register 2 High GCN2H2 000578H PPG8 - Timer register 000579H PPG8 - Timer register 00057AH PPG8 - Period setting register 00057BH PPG8 - Period setting register 00057CH PPG8 - Duty cycle register 00057DH PPG8 - Duty cycle register 00057EH PPG8 - Control status register Low PCNL8 00057FH PPG8 - Control status register High PCNH8 000580H PPG9 - Timer register 000581H PPG9 - Timer register 000582H PPG9 - Period setting register 000583H PPG9 - Period setting register 000584H PPG9 - Duty cycle register 000585H PPG9 - Duty cycle register 000586H PPG9 - Control status register Low PCNL9 000587H PPG9 - Control status register High PCNH9 000588H PPG10 - Timer register 000589H PPG10 - Timer register 00058AH PPG10 - Period setting register 00058BH PPG10 - Period setting register 00058CH PPG10 - Duty cycle register 00058DH PPG10 - Duty cycle register Document Number: 002-04579 Rev. *B Abbreviation 16-bit access Access PCSR7 W W PDUT7 W W PCN7 R/W R/W GCN12 R/W R/W GCN22 R/W R/W PTMR8 R R PCSR8 W W PDUT8 W W PCN8 R/W R/W PTMR9 R R PCSR9 W W PDUT9 W W PCN9 R/W R/W PTMR10 R R PCSR10 W W PDUT10 W W Page 40 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Abbreviation 8-bit access Abbreviation 16-bit access Access PPG10 - Control status register Low PCNL10 PCN10 R/W 00058FH PPG10 - Control status register High PCNH10 000590H PPG11 - Timer register 000591H PPG11 - Timer register 000592H PPG11 - Period setting register 000593H PPG11 - Period setting register 000594H PPG11 - Duty cycle register 000595H PPG11 - Duty cycle register 000596H PPG11 - Control status register Low PCNL11 000597H PPG11 - Control status register High PCNH11 000598H PPG15-PPG12 - General Control register 1 Low GCN1L3 000599H PPG15-PPG12 - General Control register 1 High GCN1H3 00059AH PPG15-PPG12 - General Control register 2 Low GCN2L3 00059BH PPG15-PPG12 - General Control register 2 High GCN2H3 00059CH PPG12 - Timer register 00059DH PPG12 - Timer register 00059EH PPG12 - Period setting register 00059FH PPG12 - Period setting register 0005A0H PPG12 - Duty cycle register 0005A1H PPG12 - Duty cycle register 0005A2H PPG12 - Control status register Low PCNL12 0005A3H PPG12 - Control status register High PCNH12 0005A4H PPG13 - Timer register 0005A5H PPG13 - Timer register 0005A6H PPG13 - Period setting register 0005A7H PPG13 - Period setting register 0005A8H PPG13 - Duty cycle register 0005A9H PPG13 - Duty cycle register 0005AAH PPG13 - Control status register Low PCNL13 0005ABH PPG13 - Control status register High PCNH13 0005ACH PPG14 - Timer register 0005ADH PPG14 - Timer register Address Register 00058EH Document Number: 002-04579 Rev. *B R/W PTMR11 R R PCSR11 W W PDUT11 W W PCN11 R/W R/W GCN13 R/W R/W GCN23 R/W R/W PTMR12 R R PCSR12 W W PDUT12 W W PCN12 R/W R/W PTMR13 R R PCSR13 W W PDUT13 W W PCN13 R/W R/W PTMR14 R R Page 41 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access 0005AEH PPG14 - Period setting register 0005AFH PPG14 - Period setting register 0005B0H PPG14 - Duty cycle register 0005B1H PPG14 - Duty cycle register 0005B2H PPG14 - Control status register Low PCNL14 0005B3H PPG14 - Control status register High PCNH14 0005B4H PPG15 - Timer register 0005B5H PPG15 - Timer register 0005B6H PPG15 - Period setting register 0005B7H PPG15 - Period setting register 0005B8H PPG15 - Duty cycle register 0005B9H PPG15 - Duty cycle register 0005BAH PPG15 - Control status register Low PCNL15 0005BBH PPG15 - Control status register High PCNH15 0005BCH-00065FH Abbreviation 16-bit access Access PCSR14 W W PDUT14 W W PCN14 R/W R/W PTMR15 R R PCSR15 W W PDUT15 W W PCN15 R/W R/W Reserved - 000660H Peripheral Resource Relocation Register 10 PRRR10 R/W 000661H Peripheral Resource Relocation Register 11 PRRR11 R/W 000662H Peripheral Resource Relocation Register 12 PRRR12 R/W 000663H Peripheral Resource Relocation Register 13 PRRR13 W 000664H-0006DFH Reserved - 0006E0H External Bus - Area configuration register 0 Low EACL0 0006E1H External Bus - Area configuration register 0 High EACH0 0006E2H External Bus - Area configuration register 1 Low EACL1 0006E3H External Bus - Area configuration register 1 High EACH1 0006E4H External Bus - Area configuration register 2 Low EACL2 0006E5H External Bus - Area configuration register 2 High EACH2 0006E6H External Bus - Area configuration register 3 Low EACL3 0006E7H External Bus - Area configuration register 3 High EACH3 0006E8H External Bus - Area configuration register 4 Low EACL4 0006E9H External Bus - Area configuration register 4 High EACH4 0006EAH External Bus - Area configuration register 5 Low EACL5 0006EBH External Bus - Area configuration register 5 High EACH5 Document Number: 002-04579 Rev. *B EAC0 R/W R/W EAC1 R/W R/W EAC2 R/W R/W EAC3 R/W R/W EAC4 R/W R/W EAC5 R/W R/W Page 42 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Abbreviation 8-bit access Abbreviation 16-bit access Address Register 0006ECH External Bus - Area select register 2 EAS2 R/W 0006EDH External Bus - Area select register 3 EAS3 R/W 0006EEH External Bus - Area select register 4 EAS4 R/W 0006EFH External Bus - Area select register 5 EAS5 R/W 0006F0H External Bus - Mode register EBM R/W 0006F1H External Bus - Clock and Function register EBCF R/W 0006F2H External Bus - Address output enable register 0 EBAE0 R/W 0006F3H External Bus - Address output enable register 1 EBAE1 R/W 0006F4H External Bus - Address output enable register 2 EBAE2 R/W 0006F5H External Bus - Control signal register EBCS R/W 0006F6H-0006FFH Reserved - 000700H CAN0 - Control register Low CTRLRL0 000701H CAN0 - Control register High (reserved) CTRLRH0 000702H CAN0 - Status register Low STATRL0 000703H CAN0 - Status register High (reserved) STATRH0 000704H CAN0 - Error Counter Low (Transmit) ERRCNTL0 000705H CAN0 - Error Counter High (Receive) ERRCNTH0 000706H CAN0 - Bit Timing Register Low BTRL0 000707H CAN0 - Bit Timing Register High BTRH0 000708H CAN0 - Interrupt Register Low INTRL0 000709H CAN0 - Interrupt Register High INTRH0 00070AH CAN0 - Test Register Low TESTRL0 00070BH CAN0 - Test Register High (reserved) TESTRH0 00070CH CAN0 - BRP Extension register Low BRPERL0 00070DH CAN0 - BRP Extension register High (reserved) BRPERH0 00070EH-00070FH CTRLR0 R/W R STATR0 R/W R ERRCNT0 R R BTR0 R/W R/W INTR0 R R TESTR0 R/W R BRPER0 R/W R Reserved - 000710H CAN0 - IF1 Command request register Low IF1CREQL0 000711H CAN0 - IF1 Command request register High IF1CREQH0 000712H CAN0 - IF1 Command Mask register Low IF1CMSKL0 000713H CAN0 - IF1 Command Mask register High (reserved) IF1CMSKH0 000714H CAN0 - IF1 Mask 1 Register Low IF1MSK1L0 000715H CAN0 - IF1 Mask 1 Register High IF1MSK1H0 Document Number: 002-04579 Rev. *B Access IF1CREQ0 R/W R/W IF1CMSK0 R/W R IF1MSK10 R/W R/W Page 43 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access IF1MSK20 R/W 000716H CAN0 - IF1 Mask 2 Register Low IF1MSK2L0 000717H CAN0 - IF1 Mask 2 Register High IF1MSK2H0 000718H CAN0 - IF1 Arbitration 1 Register Low IF1ARB1L0 000719H CAN0 - IF1 Arbitration 1 Register High IF1ARB1H0 00071AH CAN0 - IF1 Arbitration 2 Register Low IF1ARB2L0 00071BH CAN0 - IF1 Arbitration 2 Register High IF1ARB2H0 00071CH CAN0 - IF1 Message Control Register Low IF1MCTRL0 00071DH CAN0 - IF1 Message Control Register High IF1MCTRH0 00071EH CAN0 - IF1 Data A1 Low IF1DTA1L0 00071FH CAN0 - IF1 Data A1 High IF1DTA1H0 000720H CAN0 - IF1 Data A2 Low IF1DTA2L0 000721H CAN0 - IF1 Data A2 High IF1DTA2H0 000722H CAN0 - IF1 Data B1 Low IF1DTB1L0 000723H CAN0 - IF1 Data B1 High IF1DTB1H0 000724H CAN0 - IF1 Data B2 Low IF1DTB2L0 000725H CAN0 - IF1 Data B2 High IF1DTB2H0 000726H-00073FH R/W IF1ARB10 R/W IF1ARB20 R/W R/W IF1MCTR0 R/W R/W IF1DTA10 R/W R/W IF1DTA20 R/W R/W IF1DTB10 R/W R/W IF1DTB20 R/W R/W Reserved - 000740H CAN0 - IF2 Command request register Low IF2CREQL0 000741H CAN0 - IF2 Command request register High IF2CREQH0 000742H CAN0 - IF2 Command Mask register Low IF2CMSKL0 000743H CAN0 - IF2 Command Mask register High (reserved) IF2CMSKH0 000744H CAN0 - IF2 Mask 1 Register Low IF2MSK1L0 000745H CAN0 - IF2 Mask 1 Register High IF2MSK1H0 000746H CAN0 - IF2 Mask 2 Register Low IF2MSK2L0 000747H CAN0 - IF2 Mask 2 Register High IF2MSK2H0 000748H CAN0 - IF2 Arbitration 1 Register Low IF2ARB1L0 000749H CAN0 - IF2 Arbitration 1 Register High IF2ARB1H0 00074AH CAN0 - IF2 Arbitration 2 Register Low IF2ARB2L0 00074BH CAN0 - IF2 Arbitration 2 Register High IF2ARB2H0 00074CH CAN0 - IF2 Message Control Register Low IF2MCTRL0 00074DH CAN0 - IF2 Message Control Register High IF2MCTRH0 00074EH CAN0 - IF2 Data A1 Low IF2DTA1L0 Document Number: 002-04579 Rev. *B R/W IF2CREQ0 R/W R/W IF2CMSK0 R/W R IF2MSK10 R/W R/W IF2MSK20 R/W R/W IF2ARB10 R/W R/W IF2ARB20 R/W R/W IF2MCTR0 R/W R/W IF2DTA10 R/W Page 44 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access 00074FH CAN0 - IF2 Data A1 High IF2DTA1H0 000750H CAN0 - IF2 Data A2 Low IF2DTA2L0 000751H CAN0 - IF2 Data A2 High IF2DTA2H0 000752H CAN0 - IF2 Data B1 Low IF2DTB1L0 000753H CAN0 - IF2 Data B1 High IF2DTB1H0 000754H CAN0 - IF2 Data B2 Low IF2DTB2L0 000755H CAN0 - IF2 Data B2 High IF2DTB2H0 000756H-00077FH TREQR1L0 000781H CAN0 - Transmission Request 1 Register High TREQR1H0 000782H CAN0 - Transmission Request 2 Register Low TREQR2L0 000783H CAN0 - Transmission Request 2 Register High TREQR2H0 NEWDT1L0 000791H CAN0 - New Data 1 Register High NEWDT1H0 000792H CAN0 - New Data 2 Register Low NEWDT2L0 000793H CAN0 - New Data 2 Register High NEWDT2H0 INTPND1L0 0007A1H CAN0 - Interrupt Pending 1 Register High INTPND1H0 0007A2H CAN0 - Interrupt Pending 2 Register Low INTPND2L0 0007A3H CAN0 - Interrupt Pending 2 Register High INTPND2H0 TREQR10 R R TREQR20 R R NEWDT10 R R NEWDT20 R R INTPND10 R R INTPND20 R R - CAN0 - Message Valid 1 Register Low MSGVAL1L0 0007B1H CAN0 - Message Valid 1 Register High MSGVAL1H0 0007B2H CAN0 - Message Valid 2 Register Low MSGVAL2L0 0007B3H CAN0 - Message Valid 2 Register High MSGVAL2H0 MSGVAL10 R R MSGVAL20 R R Reserved COER0 R/W Reserved - 000800H CAN1 - Control register Low CTRLRL1 000801H CAN1 - Control register High (reserved) CTRLRH1 Document Number: 002-04579 Rev. *B R/W R/W Reserved 0007B0H 0007CFH-0007FFH IF2DTB20 - CAN0 - Interrupt Pending 1 Register Low CAN0 - Output enable register R/W R/W Reserved 0007A0H 0007CEH IF2DTB10 - CAN0 - New Data 1 Register Low 0007B4H-0007CDH R/W R/W Reserved 000790H 0007A4H-0007AFH IF2DTA20 - CAN0 - Transmission Request 1 Register Low 000794H-00079FH Access R/W Reserved 000780H 000784H-00078FH Abbreviation 16-bit access CTRLR1 R/W R Page 45 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access STATR1 R/W 000802H CAN1 - Status register Low STATRL1 000803H CAN1 - Status register High (reserved) STATRH1 000804H CAN1 - Error Counter Low (Transmit) ERRCNTL1 000805H CAN1 - Error Counter High (Receive) ERRCNTH1 000806H CAN1 - Bit Timing Register Low BTRL1 000807H CAN1 - Bit Timing Register High BTRH1 000808H CAN1 - Interrupt Register Low INTRL1 000809H CAN1 - Interrupt Register High INTRH1 00080AH CAN1 - Test Register Low TESTRL1 00080BH CAN1 - Test Register High (reserved) TESTRH1 00080CH CAN1 - BRP Extension register Low BRPERL1 00080DH CAN1 - BRP Extension register High (reserved) BRPERH1 00080EH-00080FH R ERRCNT1 R BTR1 R/W R/W INTR1 R R TESTR1 R/W R BRPER1 R/W R Reserved - 000810H CAN1 - IF1 Command request register Low IF1CREQL1 000811H CAN1 - IF1 Command request register High IF1CREQH1 000812H CAN1 - IF1 Command Mask register Low IF1CMSKL1 000813H CAN1 - IF1 Command Mask register High (reserved) IF1CMSKH1 000814H CAN1 - IF1 Mask 1 Register Low IF1MSK1L1 000815H CAN1 - IF1 Mask 1 Register High IF1MSK1H1 000816H CAN1 - IF1 Mask 2 Register Low IF1MSK2L1 000817H CAN1 - IF1 Mask 2 Register High IF1MSK2H1 000818H CAN1 - IF1 Arbitration 1 Register Low IF1ARB1L1 000819H CAN1 - IF1 Arbitration 1 Register High IF1ARB1H1 00081AH CAN1 - IF1 Arbitration 2 Register Low IF1ARB2L1 00081BH CAN1 - IF1 Arbitration 2 Register High IF1ARB2H1 00081CH CAN1 - IF1 Message Control Register Low IF1MCTRL1 00081DH CAN1 - IF1 Message Control Register High IF1MCTRH1 00081EH CAN1 - IF1 Data A1 Low IF1DTA1L1 00081FH CAN1 - IF1 Data A1 High IF1DTA1H1 000820H CAN1 - IF1 Data A2 Low IF1DTA2L1 000821H CAN1 - IF1 Data A2 High IF1DTA2H1 000822H CAN1 - IF1 Data B1 Low IF1DTB1L1 Document Number: 002-04579 Rev. *B R IF1CREQ1 R/W R/W IF1CMSK1 R/W R IF1MSK11 R/W R/W IF1MSK21 R/W R/W IF1ARB11 R/W R/W IF1ARB21 R/W R/W IF1MCTR1 R/W R/W IF1DTA11 R/W R/W IF1DTA21 R/W R/W IF1DTB11 R/W Page 46 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access 000823H CAN1 - IF1 Data B1 High IF1DTB1H1 000824H CAN1 - IF1 Data B2 Low IF1DTB2L1 000825H CAN1 - IF1 Data B2 High IF1DTB2H1 000826H-00083FH IF1DTB21 IF2CREQL1 000841H CAN1 - IF2 Command request register High IF2CREQH1 000842H CAN1 - IF2 Command Mask register Low IF2CMSKL1 000843H CAN1 - IF2 Command Mask register High (reserved) IF2CMSKH1 000844H CAN1 - IF2 Mask 1 Register Low IF2MSK1L1 000845H CAN1 - IF2 Mask 1 Register High IF2MSK1H1 000846H CAN1 - IF2 Mask 2 Register Low IF2MSK2L1 000847H CAN1 - IF2 Mask 2 Register High IF2MSK2H1 000848H CAN1 - IF2 Arbitration 1 Register Low IF2ARB1L1 000849H CAN1 - IF2 Arbitration 1 Register High IF2ARB1H1 00084AH CAN1 - IF2 Arbitration 2 Register Low IF2ARB2L1 00084BH CAN1 - IF2 Arbitration 2 Register High IF2ARB2H1 00084CH CAN1 - IF2 Message Control Register Low IF2MCTRL1 00084DH CAN1 - IF2 Message Control Register High IF2MCTRH1 00084EH CAN1 - IF2 Data A1 Low IF2DTA1L1 00084FH CAN1 - IF2 Data A1 High IF2DTA1H1 000850H CAN1 - IF2 Data A2 Low IF2DTA2L1 000851H CAN1 - IF2 Data A2 High IF2DTA2H1 000852H CAN1 - IF2 Data B1 Low IF2DTB1L1 000853H CAN1 - IF2 Data B1 High IF2DTB1H1 000854H CAN1 - IF2 Data B2 Low IF2DTB2L1 000855H CAN1 - IF2 Data B2 High IF2DTB2H1 R/W IF2CREQ1 IF2CMSK1 R/W R IF2MSK11 R/W R/W IF2MSK21 R/W R/W IF2ARB11 R/W R/W IF2ARB21 R/W R/W IF2MCTR1 R/W R/W IF2DTA11 R/W R/W IF2DTA21 R/W R/W IF2DTB11 R/W R/W IF2DTB21 R/W R/W - 000880H CAN1 - Transmission Request 1 Register Low TREQR1L1 000881H CAN1 - Transmission Request 1 Register High TREQR1H1 000882H CAN1 - Transmission Request 2 Register Low TREQR2L1 000883H CAN1 - Transmission Request 2 Register High TREQR2H1 Document Number: 002-04579 Rev. *B R/W R/W Reserved Reserved R/W - CAN1 - IF2 Command request register Low 000884H-00088FH Access R/W Reserved 000840H 000856H-00087FH Abbreviation 16-bit access TREQR11 R R TREQR21 R R - Page 47 of 111 CY96340 Series Table 4: I/O map CY96(F)34x Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access NEWDT11 R 000890H CAN1 - New Data 1 Register Low NEWDT1L1 000891H CAN1 - New Data 1 Register High NEWDT1H1 000892H CAN1 - New Data 2 Register Low NEWDT2L1 000893H CAN1 - New Data 2 Register High NEWDT2H1 000894H-00089FH INTPND1L1 0008A1H CAN1 - Interrupt Pending 1 Register High INTPND1H1 0008A2H CAN1 - Interrupt Pending 2 Register Low INTPND2L1 0008A3H CAN1 - Interrupt Pending 2 Register High INTPND2H1 INTPND11 MSGVAL1L1 0008B1H CAN1 - Message Valid 1 Register High MSGVAL1H1 0008B2H CAN1 - Message Valid 2 Register Low MSGVAL2L1 0008B3H CAN1 - Message Valid 2 Register High MSGVAL2H1 Reserved CAN1 - Output enable register R R INTPND21 R R - CAN1 - Message Valid 1 Register Low 0008CFH-0009FFH R Reserved 0008B0H 0008CEH R - CAN1 - Interrupt Pending 1 Register Low 0008B4H-0008CDH NEWDT21 Reserved 0008A0H 0008A4H-0008AFH R MSGVAL11 R R MSGVAL21 R R - COER1 Reserved R/W - 000A00H DMA - IO address block register 0 IOABK0 R/W 000A01H DMA - IO address block register 1 IOABK1 R/W 000A02H DMA - IO address block register 2 IOABK2 R/W 000A03H DMA - IO address block register 3 IOABK3 R/W 000A04H DMA - IO address block register 4 IOABK4 R/W 000A05H DMA - IO address block register 5 IOABK5 R/W 000A06H-000BFFH Reserved - Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading ‘X’.Registers of resources which are described in this table, but which are not supported by the device, should also be handled as “Reserved”. Document Number: 002-04579 Rev. *B Page 48 of 111 CY96340 Series 12. Interrupt Vector Table Table 5: Interrupt vector table CY96(F)34x Vector number Offset in vector table Vector name Cleared by DMA Index in ICR to program 0 3FCH CALLV0 No - 1 3F8H CALLV1 No - 2 3F4H CALLV2 No - 3 3F0H CALLV3 No - 4 3ECH CALLV4 No - 5 3E8H CALLV5 No - 6 3E4H CALLV6 No - 7 3E0H CALLV7 No - 8 3DCH RESET No - 9 3D8H INT9 No - 10 3D4H EXCEPTION No - 11 3D0H NMI No - 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH RESERVED No 16 Reserved 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H EXTINT1 Yes 18 External Interrupt 1 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H EXTINT5 Yes 22 External Interrupt 5 23 3A0H EXTINT6 Yes 23 External Interrupt 6 24 39CH EXTINT7 Yes 24 External Interrupt 7 25 398H EXTINT8 Yes 25 External Interrupt 8 26 394H EXTINT9 Yes 26 External Interrupt 9 27 390H EXTINT10 Yes 27 External Interrupt 10 28 38CH EXTINT11 Yes 28 External Interrupt 11 29 388H EXTINT12 Yes 29 External Interrupt 12 Document Number: 002-04579 Rev. *B Description Non-Maskable Interrupt Page 49 of 111 CY96340 Series Table 5: Interrupt vector table CY96(F)34x Vector number Offset in vector table Vector name Cleared by DMA Index in ICR to program 30 384H EXTINT13 Yes 30 External Interrupt 13 31 380H EXTINT14 Yes 31 External Interrupt 14 32 37CH EXTINT15 Yes 32 External Interrupt 15 33 378H CAN0 No 33 CAN Controller 0 (except CY96(F)34xAyy or CY96(F)34xCyy) 34 374H CAN1 No 34 CAN Controller 1 (except CY96(F)34xAyy, CY96(F)34xCyy, CY96F345Dyy or CY96F345Fyy) 35 370H PPG0 Yes 35 Programmable Pulse Generator 0 36 36CH PPG1 Yes 36 Programmable Pulse Generator 1 37 368H PPG2 Yes 37 Programmable Pulse Generator 2 38 364H PPG3 Yes 38 Programmable Pulse Generator 3 39 360H PPG4 Yes 39 Programmable Pulse Generator 4 40 35CH PPG5 Yes 40 Programmable Pulse Generator 5 41 358H PPG6 Yes 41 Programmable Pulse Generator 6 42 354H PPG7 Yes 42 Programmable Pulse Generator 7 43 350H PPG8 Yes 43 Programmable Pulse Generator 8 44 34CH PPG9 Yes 44 Programmable Pulse Generator 9 45 348H PPG10 Yes 45 Programmable Pulse Generator 10 46 344H PPG11 Yes 46 Programmable Pulse Generator 11 47 340H PPG12 Yes 47 Programmable Pulse Generator 12 48 33CH PPG13 Yes 48 Programmable Pulse Generator 13 49 338H PPG14 Yes 49 Programmable Pulse Generator 14 50 334H PPG15 Yes 50 Programmable Pulse Generator 15 51 330H RLT0 Yes 51 Reload Timer 0 52 32CH RLT1 Yes 52 Reload Timer 1 53 328H RLT2 Yes 53 Reload Timer 2 54 324H RLT3 Yes 54 Reload Timer 3 55 320H PPGRLT Yes 55 Reload Timer 6 - dedicated for PPG 56 31CH ICU0 Yes 56 Input Capture Unit 0 57 318H ICU1 Yes 57 Input Capture Unit 1 58 314H ICU2 Yes 58 Input Capture Unit 2 59 310H ICU3 Yes 59 Input Capture Unit 3 Document Number: 002-04579 Rev. *B Description Page 50 of 111 CY96340 Series Table 5: Interrupt vector table CY96(F)34x Vector number Offset in vector table Vector name Cleared by DMA Index in ICR to program 60 30CH ICU4 Yes 60 Input Capture Unit 4 61 308H ICU5 Yes 61 Input Capture Unit 5 62 304H ICU6 Yes 62 Input Capture Unit 6 63 300H ICU7 Yes 63 Input Capture Unit 7 64 2FCH OCU0 Yes 64 Output Compare Unit 0 65 2F8H OCU1 Yes 65 Output Compare Unit 1 66 2F4H OCU2 Yes 66 Output Compare Unit 2 67 2F0H OCU3 Yes 67 Output Compare Unit 3 68 2ECH OCU4 Yes 68 Output Compare Unit 4 69 2E8H OCU5 Yes 69 Output Compare Unit 5 70 2E4H OCU6 Yes 70 Output Compare Unit 6 71 2E0H OCU7 Yes 71 Output Compare Unit 7 72 2DCH FRT0 Yes 72 Free Running Timer 0 73 2D8H FRT1 Yes 73 Free Running Timer 1 74 2D4H IIC0 Yes 74 I2C interface 75 2D0H IIC1 Yes 75 I2C interface 76 2CCH ADC0 Yes 76 A/D Converter 77 2C8H ALARM0 No 77 Alarm Comparator 0 (except CY96F345Dyy or CY96F345Fyy) 78 2C4H ALARM1 No 78 Alarm Comparator 1 (except CY96F345Dyy or CY96F345Fyy) 79 2C0H LINR0 Yes 79 LIN USART 0 RX 80 2BCH LINT0 Yes 80 LIN USART 0 TX 81 2B8H LINR1 Yes 81 LIN USART 1 RX 82 2B4H LINT1 Yes 82 LIN USART 1 TX 83 2B0H LINR2 Yes 83 LIN USART 2 RX 84 2ACH LINT2 Yes 84 LIN USART 2 TX 85 2A8H LINR3 Yes 85 LIN USART 3 RX 86 2A4H LINT3 Yes 86 LIN USART 3 TX 87 2A0H FLASH_A No 87 Flash memory A (only Flash devices) 88 29CH FLASH_B No 88 Flash memory B (only CY96F348T/H/C) 89 298H LINR7 Yes 89 LIN USART 7 RX Document Number: 002-04579 Rev. *B Description Page 51 of 111 CY96340 Series Table 5: Interrupt vector table CY96(F)34x Vector number Offset in vector table Vector name Cleared by DMA Index in ICR to program 90 294H LINT7 Yes 90 LIN USART 7 TX 91 290H LINR8 Yes 91 LIN USART 8 RX 92 28CH LINT8 Yes 92 LIN USART 8 TX 93 288H LINR9 Yes 93 LIN USART 9 RX 94 284H LINT9 Yes 94 LIN USART 9 TX 95 280H RTC0 No 95 Real Timer Clock 96 27CH CAL0 No 96 Clock Calibration Unit 97 278H DFLASH_A Yes 97 Data Flash A (only CY96F345Dyy, CY96F345Fyy) Document Number: 002-04579 Rev. *B Description Page 52 of 111 CY96340 Series 13. Handling Devices Special care is required for the following when handling the device: ■ Latch-up prevention ■ Unused pins handling ■ External clock usage ■ Unused sub clock signal ■ Notes on PLL clock mode operation ■ Power supply pins (VCC/VSS) ■ Crystal oscillator circuit ■ Turn on sequence of power supply to A/D converter and analog inputs ■ Pin handling when not using the A/D converter ■ Notes on energization ■ Stabilization of power supply voltage ■ Serial communication ■ Handling of Data Flash 13.1 Latch-up prevention CMOS IC chips may suffer latch-up under the following conditions: ■ A voltage higher than VCC or lower than VSS is applied to an input or output pin. ■ A voltage higher than the rated voltage is applied between VCC pins and VSS pins. ■ The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 13.2 Unused pins handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 kΩ. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 13.3 External clock usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: Document Number: 002-04579 Rev. *B Page 53 of 111 CY96340 Series 13.3.1 Single phase external clock ■ When using a single phase external clock, X0 pin must be driven and X1 pin left open. X0 X1 13.3.2 Opposite phase external clock ■ When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. X0 X1 13.4 Unused sub clock signal If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. 13.5 Notes on PLL clock mode operation If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 13.6 Power supply pins (VCC/VSS) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. VCC and VSS must be connected to the device from the power supply with lowest possible impedance. As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 μF between VCC and VSS as close as possible to VCC and VSS pins. Document Number: 002-04579 Rev. *B Page 54 of 111 CY96340 Series 13.7 Crystal oscillator and ceramic resonator circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 13.8 Turn on sequence of power supply to A/D converter and analog inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 13.9 Pin handling when not using the A/D converter It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 13.10 Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50μs from 0.2 V to 2.7 V. 13.11 Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/μs or less in instantaneous fluctuation for power supply switching. 13.12 Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication.Therefore, design a printed circuit board so as to avoid noise.Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. 13.13 Handling of Data Flash The Data Flash requires different and additional control signals for parallel programming. Please check with your programming equipment maker for support of this interface. Document Number: 002-04579 Rev. *B Page 55 of 111 CY96340 Series 14. Electrical Characteristics 14.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC [1] AVRH, AVRL VSS - 0.3 VSS + 6.0 V AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS Input voltage VI VSS - 0.3 VSS + 6.0 V VI ≤ VCC + 0.3V [2] Output voltage VO VSS - 0.3 VSS + 6.0 V VO ≤ VCC + 0.3V [2] ICLAMP -4.0 +4.0 mA Applicable to general purposeI/O pins [3] Σ|ICLAMP| - 40 mA Applicable to general purposeI/O pins [3] IOL1 - 15 mA Normal outputs with driving strength set to 5mA “L” level average output current IOLAV1 - 5 mA Normal outputs with driving strength set to 5mA “L” level maximum overall output current ΣIOL1 - 100 mA Normal outputs ΣIOLAV1 - 50 mA Normal outputs IOH1 - -15 ”H” level average output current IOHAV1 - -5 mA Normal outputs with driving strength set to 5mA ”H” level maximum overall output current ΣIOH1 - -100 mA Normal outputs ΣIOHAV1 - -50 mA Normal outputs - 430[5] mW TA=105oC - 750[5] mW TA=90oC - 540[5] mW TA=125oC, no Flash program/erase [6] - 375[5] mW TA=105oC - 750[5] mW TA=85oC - 470[5] mW TA=125oC, no Flash program/erase [6] - 560[5] mW TA=120oC, no Flash program/erase [6] - 335[5] mW TA=105oC - 670[5] mW TA=85oC - 840[5] mW TA=75oC - 420[5] mW TA=125oC, no Flash program/erase [6] - 590[5] mW TA=115oC, no Flash program/erase [6] Power supply voltage AD Converter voltage references Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average overall output current ”H” level maximum output current ”H” level average overall output current Permitted Power dissipation (Flash devices in QFP package) [4] Permitted Power dissipation (CY96F346/F347/F348 in LQFP package) [4] Permitted Power dissipation (CY96F345 in LQFP package) [4] Document Number: 002-04579 Rev. *B PD PD PD mA Normal outputs with driving strength set to 5mA Page 56 of 111 CY96340 Series Parameter Symbol Permitted Power dissipation (Mask ROM devices) [4] PD Operating ambient temperature TA TSTG Storage temperature Rating Unit Remarks Min Max - 350 mW TA=105oC - 360 mW TA=125oC [6] 0 +70 -40 +105 -40 +125 -55 +150 CY96V300B o C [6] o C [1]: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on. [2]: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of standard ports depend on VCC. [3]: ■ Applicable to all general purpose I/O pins (Pnn_m) ■ Use within recommended operating conditions. ■ Use at DC voltage (current) ■ The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. ■ The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ■ Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. ■ Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. ■ Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). Sample recommended circuits: Protective Diode VCC Limiting resistance P-ch +B input (0V to 16V) N-ch R Document Number: 002-04579 Rev. *B Page 57 of 111 CY96340 Series [4]: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB.The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO =  (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator.IA is the analog current consumption into AVCC. [5]: Worst case value for a package mounted on single layer PCB at specified TA without air flow. [6]: Please contact Cypress for reliability limitations when using under these conditions. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed any of these ratings. 14.2 Recommended Operating Conditions Parameter Symbol Value Min Typ Max Unit Power supply voltage VCC 3.0 - 5.5 V Smoothing capacitor at C pin CS 3.5 4.7 - 10 15 μF Remarks Use a low inductance capacitor (for example X7R ceramic capacitor) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04579 Rev. *B Page 58 of 111 CY96340 Series 14.3 DC characteristics (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Input H voltage Condition CMOS Hysteresis 0.8/0.2 input selected VIH Port inputs CMOS Hysteresis 0.7/0.3 input selected Pnn_m AUTOMOTIVE Hysteresis input selected TTL input selected Value Unit Typ Max 0.8 VCC - VCC + 0.3 V 0.7 VCC - VCC + 0.3 V VCC ≥ 4.5V 0.74 VCC - VCC + 0.3 V VCC < 4.5V 0.8 VCC - VCC + 0.3 V 2.0 - VCC + 0.3 V VIHX0F X0 External clock in “Fast Clock Input mode” 0.8 VCC - VCC + 0.3 V VIHX0S X0,X1, X0A,X1A External clock in “oscillation mode” 2.5 - VCC + 0.3 V VIHR RSTX - 0.8 VCC - VCC + 0.3 V VIHM MD2-MD0 - VCC - 0.3 - VCC + 0.3 V CMOS Hysteresis 0.8/0.2 input selected VSS - 0.3 - 0.2 VCC V CMOS Hysteresis 0.7/0.3 input selected VSS - 0.3 - 0.3 VCC V VSS - 0.3 - 0.5 VCC V VSS - 0.3 - 0.46 VCC TTL input selected VSS - 0.3 - 0.8 V External clock in “Fast Clock Input mode” VSS - 0.3 - 0.2 VCC V External clock in “oscillation mode” VSS - 0.3 - 0.4 V Input L voltage VIL Port inputs Pnn_m AUTOMOTIVE Hysteresis input selected Remarks Min Not available in CY96F34xY/R/AxA CMOS Hysteresis input VCC ≥ 4.5V VCC < 4.5V Not available in CY96F34xY/R/AxA VILX0F X0 VILX0S X0,X1, X0A,X1A VILR RSTX - VSS - 0.3 - 0.2 VCC V VILM MD2-MD0 - VSS - 0.3 - VSS + 0.3 V VCC - 0.5 - - V Driving strength set to 2mA VCC - 0.5 - - V Driving strength set to 5mA VCC - 0.5 - - V CMOS Hysteresis input 4.5V ≤ VCC ≤ 5.5V Output H voltage VOH2 Normal IOH = -2mA outputs 3.0V ≤ VCC < 4.5V IOH = -1.6mA 4.5V ≤ VCC ≤ 5.5V VOH5 Normal IOH = -5mA outputs 3.0V ≤ VCC < 4.5V IOH = -3mA 4.5V ≤ VCC ≤ 5.5V VOH3 3mA outputs IOH = -3mA 3.0V ≤ VCC < 4.5V IOH = -2mA Document Number: 002-04579 Rev. *B Page 59 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Condition Value Unit Remarks 0.4 V Driving strength set to 2mA - 0.4 V Driving strength set to 5mA - - 0.4 V AVSS, AVRL < VI < AVCC, AVRH -1 - +1 μA VCC = 3.3V ± 10% 40 100 160 kΩ VCC = 5.0V ± 10% 25 50 100 kΩ Min Typ Max - - - 4.5V ≤ VCC ≤ 5.5V Output L voltage VOL2 Normal IOL = +2mA outputs 3.0V ≤ VCC < 4.5V IOL = +1.6mA 4.5V ≤ VCC ≤ 5.5V VOL5 Normal IOL = +5mA outputs 3.0V ≤ VCC < 4.5V IOL = +3mA VOL3 3mA outputs Input leak current IIL Pnn_m Pull-up resistance RUP Pnn_m, RSTX 3.0V ≤ VCC ≤ 5.5V IOL = +3mA VSS < VI < VCC Document Number: 002-04579 Rev. *B Single port pin Page 60 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Value Condition (at TA) Symbol +25°C ICCPLL Power supply current in Run modes[1] ICCMAIN Typ Max 35 44 PLL Run mode with CLKS1/2 = 48MHz, CLKB = CLKP1/2 = 24MHz +125°C 36 47 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25°C 17 23 +125°C 18 25 +25°C 44 57 PLL Run mode with CLKS1/2 = CLKB = CLKP1= 56MHz,CLKP2 = 28MHz +125°C 45 60 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25°C 25 35 +125°C 26 37 PLL Run mode with CLKS1/2 = 72MHz, CLKB = CLKP1 = 36MHz, CLKP2 = 18MHz +25°C 38 50 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125°C 39 53 PLL Run mode with CLKS1/2 = 80MHz, CLKB = CLKP1 = 40MHz, CLKP2 = 20MHz +25°C 38 51 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125°C 40 54 +25°C 49 62 PLL Run mode with CLKS1/2 = 96MHz, CLKB = CLKP1= 48MHz, CLKP2 = 24MHz +125°C 50 65 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25°C 26 36 +125°C 27 38 +25°C 4.5 5.5 Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz +125°C 5.1 8.5 (CLKPLL, CLKSC and CLKRC stopped) +25°C 2.5 3.5 +125°C Document Number: 002-04579 Rev. *B 3.1 5.5 Unit Remarks mA Flash devices at 0 Flash wait states mA CY96345/346 at 0 ROM wait states mA CY96F346/F347/F348 at 2 Flash wait states mA CY96345/346 at 2 ROM wait states mA CY96F346/F347/F348Y/R/Ayy at 1 Flash wait state mA CY96F345 at 1 Flash wait state mA CY96F348T/H/CyB/C at 1 Flash wait state mA CY96345/346 at 1 ROM wait state mA Flash devices at 1 Flash wait state mA CY96345/346 at 1 ROM wait state Page 61 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Value Condition (at TA) Symbol +25°C ICCRCH Power supply current in Run modes[1] Typ Max 2.9 4 RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 2MHz +125°C 3.5 6.5 (CLKMC, CLKPLL and CLKSC stopped) +25°C 1.7 2.7 +125°C 2.3 4.7 +25°C 0.4 0.6 +125°C 0.9 3.5 RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 0 +25°C 0.18 0.3 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) +125°C 0.68 3.3 +25°C 0.4 0.6 ICCRCL ICCSUB +125°C 0.9 2.4 +25°C 0.15 0.25 RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 1 +125°C 0.65 3.2 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode, no Flash programming/erasing allowed) +25°C 0.15 0.25 +125°C 0.65 2.1 +25°C 0.1 0.2 Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz +125°C 0.6 3 (CLKMC, CLKPLL and CLKRC stopped, no Flash programming/erasing allowed) +25°C 0.1 0.2 +125°C 0.6 2 Document Number: 002-04579 Rev. *B Unit Remarks mA Flash devices at 1 Flash wait state mA CY96345/346 at 1 ROM wait state mA CY96F346/F347/F348 at 1 Flash wait state mA CY96F345 at 1 Flash wait state mA CY96345/346 at 1 ROM wait state mA Flash devices at 1 Flash wait state mA CY96345/346 at 1 ROM wait state mA Flash devices at 1 Flash wait state mA CY96345/346 at 1 ROM wait state Page 62 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter ICCSPLL Power supply current in Sleep modes[1] ICCSMAIN Value Condition (at TA) Symbol Typ Max +25°C 9 10.5 PLL Sleep mode with CLKS1/2 = 48MHz, CLKP1/2 = 24MHz +125°C 9.7 13 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25°C 8 9.5 +125°C 8.7 11.5 +25°C 14 15.5 PLL Sleep mode with CLKS1/2 = CLKP1= 56MHz, CLKP2 = 28MHz +125°C 14.8 18 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25°C 13.5 15 +125°C 14.3 17 PLL Sleep mode with CLKS1/2 = 72MHz, CLKP1 = 36MHz, CLKP2 = 18MHz +25°C 10.5 12 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125°C 11.3 14.5 PLL Sleep mode with CLKS1/2 = 80MHz, CLKP1 = 40MHz, CLKP2 = 20MHz +25°C 11 13.5 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125°C 11.7 16 +25°C 15 16.5 PLL Sleep mode with CLKS1/2 = 96MHz, CLKP1= 48MHz, CLKP2 = 24MHz +125°C 15.8 19 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25°C 14 15.5 +125°C 14.8 17.5 +25°C 1.5 1.8 Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz +125°C 2 4.5 (CLKPLL, CLKSC and CLKRC stopped) +25°C 1.5 1.8 +125°C 2 3.8 Document Number: 002-04579 Rev. *B Unit Remarks mA Flash devices mA CY96345/346 mA CY96F346/F347/F348 mA CY96345/346 mA CY96F346/F347/F348Y/R/Ayy mA CY96F345 mA CY96F348T/H/CyB/C mA CY96345/346 mA Flash devices mA CY96345/346 Page 63 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter ICCSRCH Typ Max +25°C 0.9 1.4 RC Sleep mode with CLKS1/2 = CLKP1/2 = 2MHz +125°C 1.5 4.1 (CLKMC, CLKPLL and CLKSC stopped) +25°C 0.9 1.4 +125°C 1.5 3.1 +25°C 0.3 0.5 +125°C 0.8 3.4 RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 0 +25°C 0.09 0.2 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) +125°C 0.59 3.1 +25°C 0.3 0.5 +125°C 0.8 2.3 +25°C 0.06 0.15 RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 1 +125°C 0.56 3 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) +25°C 0.06 0.15 +125°C 0.56 1.9 +25°C 0.04 0.12 Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz +125°C 0.54 2.9 (CLKMC, CLKPLL and CLKRC stopped) +25°C 0.04 0.12 +125°C 0.54 1.85 Power supply current in Sleep modes[1] Value Condition (at TA) Symbol ICCSRCL ICCSSUB Document Number: 002-04579 Rev. *B Unit Remarks mA Flash devices mA CY96345/346 mA CY96F346/F347/F348 mA CY96F345 mA CY96345/346 mA Flash devices mA CY96345/346 mA Flash devices mA CY96345/346 Page 64 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter ICCTPLL Value Condition (at TA) Symbol Typ Max +25°C 1.6 2 PLL Timer mode with CLKMC = 4MHz, CLKPLL = 48MHz +125°C 2.1 5 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25°C 1.6 2 +125°C 2.1 4 +25°C 0.35 0.5 +125°C 0.85 3.3 Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 +25°C 0.13 0.2 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in high power mode) +125°C 0.63 3 +25°C 0.35 0.5 +125°C 0.85 2.3 +25°C 0.1 0.15 Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 1 +125°C 0.6 2.9 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode) +25°C 0.1 0.15 +125°C 0.6 1.9 +25°C 0.35 0.5 +125°C 0.85 3.3 RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 +25°C 0.13 0.2 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) +125°C 0.63 3 +25°C 0.35 0.5 +125°C 0.85 2.3 +25°C 0.1 0.15 RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 1 +125°C 0.6 2.9 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) +25°C 0.1 0.15 +125°C 0.6 1.9 ICCTMAIN Power supply current in Timer modes[1] Remarks mA Flash devices mA CY96345/346 mA CY96F346/F347/F348 mA CY96F345 mA CY96345/346 mA Flash devices CY96345/346 ICCTRCH Document Number: 002-04579 Rev. *B Unit mA CY96F346/F347/F348 mA CY96F345 mA CY96345/346 mA Flash devices mA CY96345/346 Page 65 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Value Condition (at TA) Symbol Typ Max +25°C 0.3 0.45 +125°C 0.8 3.2 RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 0 +25°C 0.08 0.15 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) +125°C 0.58 2.95 +25°C 0.3 0.45 +125°C 0.8 2.2 +25°C 0.05 0.1 RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 1 +125°C 0.55 2.85 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) +25°C 0.05 0.1 +125°C 0.55 1.85 +25°C 0.03 0.1 +125°C 0.53 2.85 +25°C 0.03 0.1 +125°C 0.53 1.85 +25°C 0.02 0.08 +125°C 0.52 2.8 +25°C 0.02 0.08 +125°C 0.52 1.8 +25°C 0.015 0.06 +125°C 0.4 2.3 +25°C 0.015 0.06 +125°C 0.4 1.4 - 5 10 +25°C 90 140 ICCTRCL Power supply current in Timer modes[1] ICCTSUB Sub Timer mode with CLKSC = 32kHz (CLKMC, CLKPLL and CLKRC stopped) VRCR:LPMB[2:0] = 110B (Core voltage at 1.8V) Power supply current in Stop Mode Unit Remarks mA CY96F346/F347/F348 mA CY96F345 mA CY96345/346 mA Flash devices mA CY96345/346 mA Flash devices mA CY96345/346 mA Flash devices mA CY96345/346 mA Flash devices mA CY96345/346 ICCH VRCR:LPMB[2:0] = 000B (Core voltage at 1.2V) CY96F345 Power supply current for active Low Voltage ICCLVD Low voltage detector enabled (RCR:LVDE = 1) detector 100 150 Must be added to all current above Other devices μA +125°C Document Number: 002-04579 Rev. *B μA Must be added to all current above Page 66 of 111 CY96340 Series (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Power supply current for active Clock modulator ICCCLOMO Flash Write/Erase current Input capacitance Value Condition (at TA) Clock modulator enabled (CMCR:PDX = 1) ICCFLASH Current for one Flash module ICCDFLASH Current for one Data Flash module CIN - Remarks Typ Max Unit - 3 4.5 mA Must be added to all current above - 15 40 mA Must be added to all current above 10 20 mA Must be added to all current above 5 15 pF Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS - [1]: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Document Number: 002-04579 Rev. *B Page 67 of 111 CY96340 Series 14.4 AC Characteristics 14.4.1 Source Clock timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Clock frequency Clock frequency Clock frequency Symbol Pin fC X0, X1 fFCI Value Min Typ Max 3 - 16 Unit MHz When using a crystal oscillator, PLL off 0 - 16 MHz When using an opposite phase external clock, PLL off 3.5 - 16 MHz When using a crystal oscillator or opposite phase external clock, PLL on 0 - 56 MHz When using a single phase external clock in “Fast Clock Input mode” (not available in CY96F34xY/R/AxA), PLL off 3.5 - 56 MHz When using a single phase external clock in “Fast Clock Input mode” (not available in CY96F34xY/R/AxA), PLL on 32 32.768 100 kHz When using an oscillation circuit 0 - 100 kHz When using an opposite phase external clock 0 - 50 kHz When using a single phase external clock 50 100 200 kHz When using slow frequency of RC oscillator 1 2 4 MHz When using fast frequency of RC oscillator Permitted VCO output frequency of PLL (CLKVCO) X0 X0A, X1A fCL X0A Remarks fCR - PLL Clock frequency fCLKVCO - 64 - 200 MHz PLL Phase Jitter TPSKEW - - - ±5 ns For CLKMC (PLL input clock) ≥ 4MHz Input clock pulse width PWH, PWL X0,X1 8 - - ns Duty ratio is about 30% to 70% Input clock pulse width PWHL, PWLL X0A,X1A 5 - - μs Clock frequency tCYL VIH X0 VIL PWH PWL tCYLL VIH X0A VIL PWH Document Number: 002-04579 Rev. *B PWLL Page 68 of 111 CY96340 Series 14.4.2 Internal Clock timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Core Voltage Settings Parameter Internal System clock frequency (CLKS1 and CLKS2) Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) Symbol 1.8V Remarks Max 0 92 0 96 MHz Others than below 0 86 0 96 MHz CY96F348T/H/CxB/C 0 72 0 80 MHz CY96F345 0 68 0 74 MHz CY96F34xY/R/Axx fCLKB, fCLKP1 fCLKP2 Min Unit Min fCLKS1, fCLKS2 Internal peripheral clock frequency (CLKP2) 1.9V Max 0 52 0 56 MHz Others than below 0 36 0 40 MHz CY96F345 0 28 0 32 MHz Others than below 0 26 0 28 MHz CY96F34xY/R/Axx 14.4.3 External Reset timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Reset input time Symbol Pin tRSTL RSTX Value Min Typ Max 500 - - Unit Remarks ns tRSTL RSTX 0.2 VCC Document Number: 002-04579 Rev. *B 0.2 VCC Page 69 of 111 CY96340 Series 14.4.4 Power On Reset timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Power on rise time Power off time Symbol Pin tR tOFF Value Unit Min Typ Max Vcc 0.05 - 30 ms Vcc 1 - - ms Remarks tR 2.7V VCC 0.2 V 0.2 V 0.2 V tOFF If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. VCC 3V Document Number: 002-04579 Rev. *B Rising edge of 50 mV/ms maximum is allowed Page 70 of 111 CY96340 Series 14.4.5 External Input timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Condition INTn(_R) NMI(_R) Value Min Max 200 - Unit Used Pin input function ns tINH tINL NMI General Purpose IO Pnn_m Input pulse width External Interrupt TINn(_R) Reload Timer - TTGn(_R) 2*tCLKP1 + 200 (tCLKP1=1/fCLKP1) ADTG(_R) PPG Trigger input - ns AD Converter Trigger FRCKn(_R) Free Running Timer external clock INn(_R) Input Capture Note : Relocated Resource Inputs have same characteristics External Pin input VIH VIH VIL VIL tINH tINL 14.4.6 External Bus timing Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. Document Number: 002-04579 Rev. *B Page 71 of 111 CY96340 Series 14.4.7 Basic Timing (TA = −40°C to +125°C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition ECLK - tCYC ECLK ECLK → UBX/ LBX / CSn time ECLK → ALE time Max 25 tCYC/2+5 tCLCH tCYC/2-5 tCYC/2+5 tCHCBH -20 20 -20 20 -20 20 tCLCBL -20 20 tCHLH -10 10 -10 10 -10 10 -10 10 -15 15 -15 15 -15 15 -15 15 -10 10 -10 10 -10 10 -10 10 tCHCBL tCLCBH tCHLL tCLLH tCHAV tCLAV tCLADV tCHADV CSn, UBX, LBX, ECLK ALE, ECLK - - A[23:16], ECLK - AD[15:0], ECLK - tCHRWH ECLK → RDX /WRX time Min tCYC/2-5 tCHCL tCLLL ECLK → address valid time Value tCHRWL tCLRWH tCLRWL Document Number: 002-04579 Rev. *B RDX, WRX, WRLX,WRHX, ECLK - Unit Remarks ns ns ns ns ns ns Page 72 of 111 CY96340 Series (TA = −40°C to +125°C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition Min Max 30 - tCYC/2-8 tCYC/2+8 tCLCH tCYC/2-8 tCYC/2+8 tCHCBH -25 25 -25 25 -25 25 tCYC ECLK ECLK → UBX/ LBX / CSn time ECLK → ALE time ECLK → address valid time tCHCL tCHCBL tCLCBH ECLK CSn, UBX, LBX, ECLK - - tCLCBL -25 25 tCHLH -15 15 -15 15 -15 15 tCHLL tCLLH ALE, ECLK - tCLLL -15 15 tCHAV -20 20 -20 20 -20 20 -20 20 -15 15 -15 15 -15 15 -15 15 tCLAV tCLADV tCHADV A[23:16], ECLK - AD[15:0], ECLK - tCHRWH ECLK → RDX /WRX time Value tCHRWL tCLRWH tCLRWL Document Number: 002-04579 Rev. *B RDX, WRX, WRLX, WRHX, ECLK - Unit Remarks ns ns ns ns ns ns Page 73 of 111 CY96340 Series tCYC tCHCL ECLK tCLCH 0.8*Vcc 0.2*Vcc tCLAV tCHAV A[23:16] tCH- tCLCBH tCLCBL tCH- tCHRW tCL- tCLRWL tCHRW CSn LBX UBX RDX WRX (WRLX, WRHX) tCLLH tCHLL tCHLH tCLLL ALE tCHA tCLAD AD[15:0] Address Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04579 Rev. *B Page 74 of 111 CY96340 Series 14.4.8 Bus Timing (Read) (TA = −40°C to +125°C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions EACL:STS=0 and EACL:ACE=0 ALE pulse width tLHLL tAVLL ALE ALE, A[23:16], Valid address  ALE ↓ time tADVLL ALE ↓  Address valid time tLLAX ALE,AD[15:0] ALE, AD[15:0] RDX, A[23:16] Valid address  RDX ↓ time RDX, AD[15:0] tAVDV Valid address  Valid data input 3tCYC/2 − 5 - EACL:STS=0 and EACL:ACE=0 tCYC − 15 - EACL:STS=1 and EACL:ACE=0 3tCYC/2 − 15 - EACL:STS=0 and EACL:ACE=1 2tCYC − 15 - EACL:STS=1 and EACL:ACE=1 5tCYC/2 − 15 - EACL:STS=0 and EACL:ACE=0 tCYC/2 − 15 - EACL:STS=1 and EACL:ACE=0 tCYC − 15 - EACL:STS=0 and EACL:ACE=1 3tCYC/2 − 15 - EACL:STS=1 and EACL:ACE=1 2tCYC − 15 - EACL:STS=0 tCYC/2 − 15 - EACL:STS=1 -15 - 3tCYC/2 − 15 - 5tCYC/2 − 15 - tCYC − 15 - 2tCYC − 15 - - 3tCYC − 55 EACL:ACE=1 EACL:ACE=1 EACL:ACE=1 EACL:ACE=0 tADVDV AD[15:0] - EACL:ACE=0 A[23:16], AD[15:0] tCYC/2 − 5 tCYC − 5 EACL:ACE=0 tADVRL Max EACL:STS=0 and EACL:ACE=1 EACL:STS=1 EACL:ACE=0 tAVRL Value Min EACL:ACE=1 Unit Remarks ns ns ns ns ns ns - 4tCYC − 55 - 5tCYC/2 − 55 - 7tCYC/2 − 55 ns w/o cycle extension ns w/o cycle extension RDX pulse width tRLRH RDX - 3 tCYC/2 − 5 - ns w/o cycle extension RDX ↓  Valid data input tRLDV RDX, AD[15:0] - - 3 tCYC/2 − 50 ns w/o cycle extension RDX ↑  Data hold time tRHDX RDX, AD[15:0] - 0 - ns Address valid  Data hold time tAXDX A[23:16], AD[15:0] - 0 - ns Document Number: 002-04579 Rev. *B Page 75 of 111 CY96340 Series (TA = −40°C to +125°C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter RDX ↑  ALE ↑ time Valid address  ECLK ↑ time Symbol tRHLH Pin RDX, ALE tAVCH A[23:16], ECLK tADVCH AD[15:0], ECLK RDX ↓  ECLK ↑ time tRLCH RDX, ECLK ALE ↓  RDX ↓ time tLLRL ALE, RDX ECLK↑  Valid data input tCHDV AD[15:0], ECLK Value Conditions Min Max EACL:STS=1 and EACL:ACE=1 3tCYC/2 − 10 - other ECL:STS, EACL:ACE setting tCYC/2 − 10 - tCYC − 15 - tCYC/2 − 15 - tCYC/2 − 10 - - Unit Remarks ns ns ns EACL:STS=0 tCYC/2 − 10 - EACL:STS=1 − 10 - - tCYC − 50 - ns ns (TA = −40°C to +125°C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions Min Max tCYC/2 − 8 - tCYC − 8 - EACL:STS=0 and EACL:ACE=1 3tCYC/2 − 8 - EACL:STS=0 and EACL:ACE=0 tCYC − 20 - EACL:STS=1 and EACL:ACE=0 3tCYC/2 − 20 - EACL:STS=0 and EACL:ACE=1 2tCYC − 20 - EACL:STS=1 and EACL:ACE=1 5tCYC/2 − 20 - EACL:STS=0 and EACL:ACE=0 tCYC/2 − 20 - EACL:STS=1 and EACL:ACE=0 tCYC − 20 - EACL:STS=0 and EACL:ACE=1 3tCYC/2 − 20 - EACL:STS=1 and EACL:ACE=1 2tCYC − 20 - EACL:STS=0 tCYC/2 − 20 - EACL:STS=1 -20 - 3tCYC/2 − 20 - 5tCYC/2 − 20 - tCYC − 20 - 2tCYC − 20 - EACL:STS=0 and EACL:ACE=0 ALE pulse width tLHLL tAVLL ALE ALE, A[23:16], Valid address  ALE ↓ time tADVLL ALE ↓  Address valid time tLLAX ALE, AD[15:0] ALE, AD[15:0] EACL:STS=1 EACL:ACE=0 tAVRL RDX, A[23:16] EACL:ACE=1 Valid address  RDX ↓ time EACL:ACE=0 tADVRL Document Number: 002-04579 Rev. *B RDX, AD[15:0] Value EACL:ACE=1 Unit Remarks ns ns ns ns ns ns Page 76 of 111 CY96340 Series (TA = −40°C to +125°C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions EACL:ACE=0 tAVDV Valid address  Valid data input A[23:16], AD[15:0] EACL:ACE=1 EACL:ACE=0 tADVDV AD[15:0] EACL:ACE=1 Value Min Max - 3tCYC − 60 - 4tCYC − 60 - 5tCYC/2 − 60 - 7tCYC/2 − 60 Unit Remarks ns w/o cycle extension ns w/o cycle extension RDX pulse width tRLRH RDX - 3tCYC/2 − 8 - ns w/o cycle extension RDX ↓  Valid data input tRLDV RDX, AD[15:0] - - 3tCYC/2 − 55 ns w/o cycle extension RDX ↑  Data hold time tRHDX RDX, AD[15:0] - 0 - ns Address valid  Data hold time tAXDX A[23:16] - 0 - ns EACL:STS=1 and EACL:ACE=1 3tCYC/2 − 15 - other ECL:STS, EACL:ACE setting tCYC/2 − 15 - RDX ↑  ALE ↑ time Valid address  ECLK ↑ time RDX ↓  ECLK ↑ time tRHLH RDX, ALE tAVCH A[23:16], ECLK tADVCH AD[15:0], ECLK tRLCH RDX, ECLK ALE ↓  RDX ↓ time tLLRL ALE, RDX ECLK↑  Valid data input tCHDV AD[15:0], ECLK Document Number: 002-04579 Rev. *B - ns tCYC − 20 - tCYC/2 − 20 - tCYC/2 − 15 - EACL:STS=0 tCYC/2 − 15 - EACL:STS=1 − 15 - - tCYC − 55 - - ns ns ns ns Page 77 of 111 CY96340 Series tAVCH tRLC tADECLK tCHD 0.8*Vcc tAVLL tLLAX tADALE tRHL 0.2*VC tLHLL tAVRL tAD- tRLR RDX tLLRL A[23:16] tRLDV tAVDV tAXD tRHD tADAD[15:0] Address VIH VIL Read data VIH VIL Refer to the Hardware Manual for detailed Timing Charts . Document Number: 002-04579 Rev. *B Page 78 of 111 CY96340 Series 14.4.9 Bus Timing (Write) (TA = −40°C to +125°C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition EACL:ACE=0 tAVWL WRX, WRLX, WRHX, A[23:16] EACL:ACE=0 tADVWL Min Max 3tCYC/2 − 15 - 5tCYC/2 − 15 - tCYC − 15 - 2tCYC − 15 - Unit Remarks ns EACL:ACE=1 Valid address  WRX ↓ time WRX, WRLX, WRHX, AD[15:0] Value ns EACL:ACE=1 WRX pulse width tWLWH WRX, WRXL, WRHX - tCYC − 5 - ns w/o cycle extension Valid data output  WRX ↑ time tDVWH WRX, WRLX, WRHX, AD[15:0] - tCYC − 20 - ns w/o cycle extension WRX ↑  Data hold time tWHDX WRX, WRLX, WRHX, AD[15:0] - tCYC/2 − 15 - ns WRX ↑  Address valid time tWHAX WRX, WRLX, WRHX, A[23:16] - tCYC/2 − 15 - ns EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting 2tCYC − 10 - tWHLH WRX, WRLX, WRHX, ALE tCYC − 10 - tWLCH WRX, WRLX, WRHX, ECLK - tCYC/2 − 10 - - 3tCYC/2 − 15 - 5tCYC/2 − 15 tCYC/2 − 15 - WRX ↑  ALE ↑ time WRX ↓  ECLK ↑ time EACL:ACE=0 CSn  WRX time WRX  CSn time tCSLWL tWHCSH WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn ns ns EACL:ACE=1 - ns ns (TA = −40°C to +125°C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition EACL:ACE=0 tAVWL WRX, WRLX, WRHX, A[23:16] EACL:ACE=0 tADVWL Document Number: 002-04579 Rev. *B Min Max 3tCYC/2 − 20 - Unit Remarks ns EACL:ACE=1 Valid address  WRX ↓ time WRX, WRLX, WRHX, AD[15:0] Value 5tCYC/2 − 20 - tCYC − 20 ns EACL:ACE=1 2tCYC − 20 - Page 79 of 111 CY96340 Series (TA = −40°C to +125°C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition Value Min Max Unit Remarks WRX pulse width tWLWH WRX, WRXL, WRHX - tCYC − 8 - ns w/o cycle extension Valid data output  WRX ↑ time tDVWH WRX, WRLX, WRHX, AD[15:0] - tCYC − 25 - ns w/o cycle extension WRX ↑  Data hold time tWHDX WRX, WRLX, WRHX, AD[15:0] - tCYC/2 − 20 - ns tWHAX WRX, WRLX, WRHX, A[23:16] - tCYC/2 − 20 - ns EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting 2tCYC − 15 - tWHLH WRX, WRLX, WRHX, ALE tCYC − 15 - tWLCH WRX, WRLX, WRHX, ECLK - tCYC/2 − 15 - - 3tCYC/2 − 20 tCSLWL WRX, WRLX, WRHX, CSn - 5tCYC/2 − 20 tCYC/2 − 20 - WRX ↑  Address valid time WRX ↑  ALE ↑ time WRX ↓  ECLK ↑ time EACL:ACE=0 CSn  WRX time WRX  CSn time tWHCSH WRX, WRLX, WRHX, CSn Document Number: 002-04579 Rev. *B EACL:ACE=1 - ns ns ns ns Page 80 of 111 CY96340 Series tWLC 0.8*VC ECLK tWHL ALE tAVW tWLW tADVWL WRX (WRLX, WRHX) 0.2*VCC tCSLWL tWHCS CSn tWHA A[23:16] tDVW AD[15:0] Address tWHD Write data Refer to the Hardware Manual for detailed Timing Charts . 14.4.10 Ready Input Timing (TA = −40°C to +125°C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin RDY setup time tRYHS RDY RDY hold time tRYHH RDY Test Condition - Rated Value Min Max Units 35 - ns 0 - ns Remarks (TA = −40°C to +125°C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin RDY setup time tRYHS RDY RDY hold time tRYHH RDY Test Condition - Rated Value Units Min Max 45 - ns 0 - ns Remarks Note: If the RDY setup time is insufficient, use the auto-ready function. Document Number: 002-04579 Rev. *B Page 81 of 111 CY96340 Series 0.8*VC ECLK RDY When WAIT is not used. RDY When WAIT is used. tRYH tRYH VIH VIH VIL Refer to the Hardware Manual for detailed Timing Charts 14.4.11 Hold Timing (TA = −40°C to +125°C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Pin floating  HAKX ↓ time tXHAL HAKX HAKX ↑ time  Pin valid time tHAHV HAKX Value Condition - Units Min Max tCYC − 20 tCYC + 20 ns tCYC − 20 tCYC + 20 ns Remarks (TA = −40°C to +125°C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Pin floating  HAKX ↓ time tXHAL HAKX HAKX ↑ time  Pin valid time tHAHV HAKX Value Condition - Max tCYC − 25 tCYC + 25 ns tCYC − 25 tCYC + 25 ns Remarks 0.8*VCC HAKX 0.2*VCC tHAH tXHAL Each pin Units Min 0.8*VCC High-Z 0.2*VCC Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04579 Rev. *B Page 82 of 111 CY96340 Series 14.4.12 USART timing WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. (TA = -40°C to 125°C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Serial clock cycle time Pin Condition VCC = AVCC= 4.5V to 5.5V VCC = AVCC= 3.0V to 4.5V Min Max Min Max Unit tSCYCI SCKn 4 tCLKP1 - 4 tCLKP1 - ns SCK ↓→ SOT delay time tSLOVI SCKn, SOTn -20 +20 -30 +30 ns SOT → SCK ↑ delay time tOVSHI SCKn, SOTn N*tCLKP1 - 20 [1] - N*tCLKP1 - 30 [1] - ns Valid SIN → SCK ↑ tIVSHI SCKn, SINn tCLKP1 + 45 - tCLKP1 + 55 - ns SCK ↑→ Valid SIN hold time tSHIXI SCKn, SINn 0 - 0 - ns Serial clock “L” pulse width tSLSHE SCKn tCLKP1 + 10 - tCLKP1 + 10 - ns Serial clock “H” pulse width tSHSLE SCKn tCLKP1 + 10 - tCLKP1 + 10 - ns SCK ↓→ SOT delay time tSLOVE SCKn, SOTn - 2 tCLKP1 + 45 - 2 tCLKP1 + 55 ns Valid SIN → SCK ↑ tIVSHE SCKn, SINn tCLKP1/2 + 10 - tCLKP1/2 + 10 - ns SCK ↑→ Valid SIN hold time tSHIXE SCKn, SINn tCLKP1 + 10 - tCLKP1 + 10 - ns SCK fall time tFE SCKn - 20 - 20 ns SCK rise time tRE SCKn - 20 - 20 ns Internal Shift Clock Mode External Shift Clock Mode Notes: ■ AC characteristic in CLK synchronized mode. ■ CL is the load capacity value of pins when testing. ■ Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “CY96300 Super series HARDWARE MANUAL”. ■ tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns [1]: Parameter N depends on tSCYCI and can be calculated as follows: ■ if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 ■ if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI N 4*tCLKP1 2 5*tCLKP1, 3 7*tCLKP1, 4 ... ... Document Number: 002-04579 Rev. *B Page 83 of 111 CY96340 Series tSCY SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC SCK for ESCR:SCES = 1 0.8*VCC 0.8*VCC 0.2*VCC tSLOV tOVS 0.8*VCC SOT 0.2*VCC tSHIXI tIVSHI SIN VIH VIH VIL VIL Internal Shift Clock Mode tSLSH SCK for ESCR:SCES = 0 VIH SCK for ESCR:SCES = 1 VIL VIL VIH VIH VIL tFE SOT tSHSL tSLOVE VIH VIL VIL tRE 0.8*VCC 0.2*VCC tIVSH SIN VIH tSHIX VIH VIH VIL VIL External Shift Clock Mode Document Number: 002-04579 Rev. *B Page 84 of 111 CY96340 Series 14.4.13 I2C Timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V) Parameter Symbol SCL clock frequency Condition Standard-mode Fast-mode[4] Unit Min Max Min Max fSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs “L” width of the SCL clock tLOW 4.7 - 1.3 - μs “H” width of the SCL clock tHIGH 4.0 - 0.6 - μs 4.7 - 0.6 - μs Hold time (repeated) START condition SDA↓→SCL¬ R = 1.7 kΩ, C = 50 pF[1] Set-up time for a repeated START condition SCL↓→SDA↑ tSUSTA Data hold timeSCL↑→SDA↑↓ tHDDAT 0 3.45[2] 0 0.9[3] μs Data set-up timeSDA↑↓→SCL↑ tSUDAT 250 - 100 - ns Set-up time for STOP conditionSCL↑→SDA↑ tSUSTO 4.0 - 0.6 - μs tBUS 4.7 - 1.3 - μs Bus free time between a STOP and START condition [1] : R,C: Pull-up resistor and load capacitor of the SCL and SDA lines. [2]: The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. [3] : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT≥ 250 ns must then be met. [4] : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. SDA tSUDAT tLOW tBUS tHDSTA SCL tHDSTA tHDDAT Document Number: 002-04579 Rev. *B tHIGH tSUSTA tSUSTO Page 85 of 111 CY96340 Series 14.5 Analog Digital Converter (TA = -40 °C to +125 °C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Resolution - Total error Nonlinearity error Differential nonlinearity error Value Unit Min Typ Max - - - 10 bit - - -3 - +3 LSB - - -2.5 - +2.5 LSB - - -1.9 - +1.9 LSB Zero reading voltage VOT ANn AVRL - 1.5 LSB AVRL+ 0.5 LSB AVRL + 2.5 LSB V Full scale reading voltage VFST ANn AVRH - 3.5 LSB AVRH - 1.5 LSB AVRH + 0.5 LSB V Compare time - - Sampling time - - IAIN ANn Analog port input curren Analog port input curren Analog input voltage range Reference voltage range Power supply current IAIN 1.0 - 16,500 μs 4.5V ≤ ΑVCC ≤ 5.5V 2.0 - - μs 3.0V ≤ ΑVCC < 4.5V 0.5 - - μs 4.5V ≤ ΑVCC ≤ 5.5V 1.2 - - μs 3.0V ≤ ΑVCC < 4.5V -3 - +3 μA AVSS, AVRL < VI < AVCC, AVRH -1 - +1 μA TA = 25 °C, AVSS, AVRL < VI < AVCC, AVRH -3 - +3 μA TA = 125 °C,AVSS, AVRL < VI < AVCC, AVRH ANn VAIN ANn AVRL - AVRH V AVRH AVRH/ AVRH 2 0.75 AVcc - AVcc V AVRL AVRL AVSS - 0.25 AVCC V IA AVcc - 2.5 5 mA A/D Converter active IAH AVcc - - 5 μA A/D Converter not operated IR AVRH/ AVRL - 0.7 1 mA A/D Converter active IRH AVRH/ AVRL - - 5 μA A/D Converter not operated - ANn - - 4 LSB Reference voltage current Offset between input channels Remarks Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller. Document Number: 002-04579 Rev. *B Page 86 of 111 CY96340 Series 14.5.1 Definition of A/D Converter Terms ■ Resolution: Analog variation that is recognized by an A/D converter. ■ Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. ■ Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics. ■ Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. ■ Zero reading voltage: Input voltage which results in the minimum conversion value. ■ Full scale reading voltage: Input voltage which results in the maximum conversion value. Total error 3FF 3FE 1.5 LSB Actual conversion characteristics Digital output 3FD {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (Actually-measured value) 003 Actual conversion characteristics Ideal characteristics 002 001 0.5 LSB AVRL AVRH Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB Total error of digital output “N” = 1 LSB = (Ideal value) AVRH − AVRL 1024 [LSB] [V] N: A/D converter digital output value VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N − 1) to N. Document Number: 002-04579 Rev. *B Page 87 of 111 CY96340 Series Nonlinearity error Differential nonlinearity error Ideal characteristics 3FF Actual conversion characteristics {1 LSB × (N − 1) + VOT } Digital output 3FD N+1 VFST (actual measurement value) VNT (actual measurement value) 004 Actual conversion characteristics 003 Digital output 3FE Actual conversion characteristics N V (N + 1) T (actual measurement value) VNT (actual measurement value) N−1 002 Ideal characteristics Actual conversion characteristics N−2 001 VOT (actual measurement value) AVRL AVRH AVRL Analog input AVRH Analog input Nonlinearity error of digital output N = Differential nonlinearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 [LSB] − 1LSB [LSB] [V] N: A/D converter digital output value VOT: Voltage at which digital output transits from “000H” to “001H.” VFST: Voltage at which digital output transits from “3FEH” to “#FFH.” Document Number: 002-04579 Rev. *B Page 88 of 111 CY96340 Series 14.5.2 ■ Notes on A/D Converter Section About the external impedance of the analog input and the sampling time of the A/D converter (with sample and hold circuit): If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Analog input circuit model: R Comparator Analog input C Sampling switch Reference value: C = 8.5 pF (Max) To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum sampling time must be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be decreased so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7τ, where τ = RC. If the external input resistance (Rext) connected to the analog input is included, the sampling time is expressed as follows: Tsamp [min] = 7 ∞ (Rext + 2.6kΩ) × C for 4.5 ≤ AVcc ≤ 5.5 Tsamp [min] = 7 ∞ (Rext + 12.1kΩ) × C for 3.0 ≤ AVcc ≤ 4.5 If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin. ■ About the error The accuracy gets worse as |AVRH - AVRL| becomes smaller. Document Number: 002-04579 Rev. *B Page 89 of 111 CY96340 Series 14.6 Alarm Comparator (TA = -40 °C to +125 °C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Value Unit Remarks 45 μA enabled in fast mode (one channel) 7 13 μA enabled in slow mode (one channel) - - 5 μA Alarm comparator disabled -1 - +1 μA TA = 25 °C -3 - +3 μA TA = 125 °C Min Typ Max - 25 - Alarm comparator IA5ALMF Power supply current AVCC IA5ALMS IA5ALMH Alarm comparator ALARM pin input current IALIN ALARM pin input voltage range VALIN 0 - AVCC V External low threshold high->low transition VEVTL(H->L) 0.36 * AVCC -0.25 0.36 * AVCC -0.1 - V External low threshold low->high transition VEVTL(L->H) - External high threshold high->low transition VEVTH(H->L) 0.78 * AVCC -0.25 External high threshold low->high transition VEVTH(L->H) Internal low threshold high->low transition VIVTL(H->L) Internal low threshold low->high transition VIVTL(L->H) Internal high threshold high->low transition Internal high threshold low->high transition 0.36 * AVCC +0.1 0.36 * AVCC +0.25 V 0.78 * AVCC -0.1 V INTREF = 0 - 0.78 * AVCC +0.1 0.78 * AVCC +0.25 V 0.9 1.1 - V - 1.3 1.55 V VIVTH(H->L) 2.2 2.4 - V VIVTH(L->H) - 2.6 2.85 V VHYS 50 - 300 mV tCOMPF - 0.1 1 μs CMD = 1 (fast) tCOMPS - 1 10 μs CMD = 0 (slow) Power-up stabilization time after enabling alarm comparator tPD - 1 5 ms Slow/Fast mode transition time tCMD - 100 500 μs Threshold levels specified above are not guaranteed within this time Switching hysteresis Comparison time ALARM0, ALARM1 INTREF = 1 Document Number: 002-04579 Rev. *B Page 90 of 111 CY96340 Series Comparator Output H L VxVTx(H->L) VHY VALI VxVTx(L->H) Document Number: 002-04579 Rev. *B Page 91 of 111 CY96340 Series 14.7 Low Voltage Detector Characteristics (TA = -40 °C to +125 °C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V) Parameter Value [1] Symbol Value [2] Unit Remarks 110 μs After power-up or change of detection level 2.65 2.95 V CILCR:LVL[3:0]=”0000” 3.1 2.85 3.2 V CILCR:LVL[3:0]=”0001” 3.1 3.3 3.05 3.4 V CILCR:LVL[3:0]=”0010” VDL3 3.5 3.75 3.45 3.85 V CILCR:LVL[3:0]=”0011” Level 4 VDL4 3.6 3.85 3.55 3.95 V CILCR:LVL[3:0]=”0100” Level 5 VDL5 3.7 3.95 3.65 4.1 V CILCR:LVL[3:0]=”0101” Level 6 VDL6 3.8 4.05 3.75 4.2 V CILCR:LVL[3:0]=”0110” Level 7 VDL7 3.9 4.15 3.85 4.3 V CILCR:LVL[3:0]=”0111” Level 8 VDL8 4.0 4.25 3.95 4.4 V CILCR:LVL[3:0]=”1000” Level 9 VDL9 4.1 4.35 4.05 4.5 V CILCR:LVL[3:0]=”1001” Level 10 VDL10 not used not used Level 11 VDL11 not used not used Level 12 VDL12 not used not used Level 13 VDL13 not used not used Level 14 VDL14 not used not used Level 15 VDL15 not used not used Min Max Min Max TLVDSTAB - 75 - Level 0 VDL0 2.7 2.9 Level 1 VDL1 2.9 Level 2 VDL2 Level 3 Stabilization time [1]: valid for all devices except devices listed under “[2]” [2]: valid for: CY96F345 CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register. Levels 10 to 15 are not used in this device. V For correct detection, the slope of the voltage level must satisfy dV ≤ 0.004 ------ . μs dt Faster variations are regarded as noise and may not be detected. The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7V. The electrical characteristics however are only valid in the specified range (usually down to 3.0V). Document Number: 002-04579 Rev. *B Page 92 of 111 CY96340 Series 14.7.1 Low Voltage Detector Operation In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. Voltage [V] VCC VDLx, Max VDLx, Min dV dt Time [s] Normal Operation Document Number: 002-04579 Rev. *B Low Voltage Reset Assertion Power Reset Extension Time Page 93 of 111 CY96340 Series 14.8 Flash Memory Program/erase Characteristics (TA = -40°C to 105°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Sector erase time Program/Data Flash (Main Flash) Sector erase time Data Flash Chip erase time Program/Data Flash (Main Flash) Chip erase timeData Flash Word (16-bit width) programming time Program/Data Flash (Main Flash) Byte (8-bit width) programming time Data Flash Program/Erase cycle Flash data retention time Value Unit Remarks 3.6 s Without erasure pre-programming time 0.5 2 s Without erasure pre-programming time - 0.8 3.6 s Including erasure pre-programming time - n*0.9 n*3.6 s Without erasure pre-programming time (n is the number of Flash sector of the device) - 2.5 10 s Without erasure pre-programming time - 3.7 16.4 s Including erasure pre-programming time - 23 370 us Without overhead time for submitting write command - 15 100 us Without overhead time for submitting write command 10000 - - cycle 100 000 Program/Erase cycles are under evaluation by Cypress 20 - - year [1] Min Typ Max - 0.9 - [1]: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) Document Number: 002-04579 Rev. *B Page 94 of 111 CY96340 Series 15. Example Characteristics The diagrams below show the characteristics of one measured sample with typical process parameters. Run Mode 100.00 PLL clock (56 MHz) 10.00 Icc [mA] Main osc. (4 MHz) RC clock (2 MHz) 1.00 RC clock (100 kHz) 0.10 Sub osc.(32 kHz) 0.01 -50.00 0.00 50.00 100.00 150.00 100.00 150.00 Ta [ºC] Sleep mode 100.00 PLL clock (56 MHz) Icc [mA] 10.00 Main osc. (4 MHz) 1.00 RC clock (2 MHz) RC clock (100 kHz) 0.10 Sub osc.(32 kHz) 0.01 -50.00 0.00 50.00 Ta [ºC] Document Number: 002-04579 Rev. *B Page 95 of 111 CY96340 Series Timer mode 10.00 PLL clock (56 MHz) Icc [mA] 1.00 Main osc. (4 MHz) RC clock (2 MHz) RC clock (100 kHz) 0.10 Sub osc. (32 kHz) 0.01 -50.00 0.00 50.00 100.00 150.00 100.00 150.00 Ta [ºC] Stop mode 1.00 Icc [mA] 0.10 0.01 0.00 -50.00 0.00 50.00 Ta [ºC] Document Number: 002-04579 Rev. *B Page 96 of 111 CY96340 Series Table 6: Used settings Mode Run mode Sleep mode Selected Source Clock Clock/Regulator Settings PLL CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz CLKP2 = 28 MHz Regulator in High Power Mode Core Voltage = 1.9 V Main osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz Regulator in High Power Mode Core Voltage = 1.8 V RC clock fast CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz Regulator in High Power Mode Core Voltage = 1.8 V RC clock slow CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz Regulator in High Power Mode Core Voltage = 1.8 V Sub osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz Regulator in Low Power Mode A Core Voltage = 1.8 V PLL CLKS1 = CLKS2 = CLKP1 = 56 MHz CLKP2 = 28 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.9 V Main osc. CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V RC clock fast CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V RC clock slow CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V Sub osc. CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz (CLKB is stopped in this mode) Regulator in Low Power Mode A Core Voltage = 1.8 V Document Number: 002-04579 Rev. *B Page 97 of 111 CY96340 Series Table 6: Used settings Mode Timer mode Stop mode Selected Source Clock Clock/Regulator Settings PLL CLKMC = 4 MHz, CLKPLL = 56 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.9 V Main osc. CLKMC = 4 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock fast CLKRC = 2 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock slow CLKRC = 100 kHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V Sub osc. CLKSC = 100 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode A, Core Voltage = 1.8 V stopped (All clocks are stopped in this mode) Regulator in Low Power Mode B, Core Voltage = 1.8 V Document Number: 002-04579 Rev. *B Page 98 of 111 CY96340 Series 16. Package Dimension CY96(F)34x LQFP 100P 002-11500 *A Document Number: 002-04579 Rev. *B Page 99 of 111 CY96340 Series 17. Package Dimension CY96(F)34x QFP 100P % $ 31 100 $ 0.73 8° L ' $ ( /  ( + 7  )  23 7 , 1  2' , 7$ &( / ( 6( + 7 $7 / )0 2 ( 5 +) 7 P 2 7P   < /  3 3' $1 $ 6  1P 2P ,  6 1   ( 01 , '( ( ( : 67 (( +% 7       2 7  ( 1 $ / 3  * 1 , 7 $ ( 6 < ( +' 72 % 0  2( 5* )$ . ( & &$ 13 $ 7( 6+ , 7 '  ) ( 2 + 77 1 6 , $2 3 '  (7 16 , ( ) (: '2  / 6 , (   + $7        Page 100 of 111 Document Number: 002-04579 Rev. *B 5 $E1 % 2 0'  (' $( '& (  7 ( ; $ +( & 7 2 2  / 17 ( 2+ , % 7 6  7 8' ,2 5: 7 1 2' 1 5$$ ( & 3/   5 5 (($ %+ 7 7%2 0 0 $($2 '6')  8 ' ( '$P$ & ( 8P/  /7   &2 ( 11 +   , / 7 1  7 /$  5 2$+ 2 1+7  6( 6 6 8 (5, 262' ' 0$  5 E  1 < 2 5 1 ,%(  26 0 , : 8 6 82 150/ (7,  ; ( 02$ , 5 + '3 07         1.95 REF 0.25 BSC ᤡ ᤢ L1 L2 1.03 0° 0.88 ș  $ 17.90 BSC <  '76 6 2(5 %*55 8( 5 5 $%: (/  (2 : 7/ 2( +$ /7 * '  1 ' 7' 1$ $ 1 $ 5 $ ' ( 5 ((+3 1 6 3 3, 30$8 /  85) ( (' + ( +7/7  7(21 '0 ) ( (  2 ( ) 52 : ( $7 = ( ,  6 (9(< % , ' 6 ( ' 91 8+2 , /&% 7 $  $&75 $  ; /' 0( (6 ( ' , 56 < /  (1'02 0 +22< 7, 6%1( 1   ) $ ( + 7 2(+* 071 , 6  ) , 6' ) 2 ' 28 (  /6 /6 '1( 1 525&2 , $,817 & *77, & 7 $ (( (8( 56 )%6          0.65 BSC E  / 20.00 BSC ' ( 7 $ & 2 /  ( %  7 6 8 0  7 8 %  / $ 1 2 , 7 3 2  ( 5 $ ' 5 ( (7 , ) $ , 7 & , 1' (1 ', ,   (  1 1 2 ,= 3  ( ) 2+ 7 6  1 /, , $ + 77 (, ':       e c 9 / D1 ' ( 1 , 0 5 ( 7 (  ' 1  2 ( , 5 6 $ 8  5 ' 7 1 2 $  5 + 3 &  7 ' / ($ 2'0 ,6 06 ,  0 ( ( '5' 83/ /2 &P0 1P , (  7'  2 8 / 16  ,& 2 1 1, '2  ,   ( (6  8' ' + 151 7 $( $2  1   '5'$ / 3 3 6 6 ( 1 1/ 20 2%, , $68 6 7 1:1$ (2(' /07 0/ , , '$'$           23.90 BSC  &  ( 1 $ / 3  * 1 , 7 $ ( 6  7 $  ' ( 1 , 0 5 ( 7 ( '  ( %  2 7    D  +  ( 1 $ / 3  0 8 7 $ '  7 $  ' ( 1 , 0 5 ( 7 ( '  ( %  2 7  '  ' 1 $  %  $  6 0 8 7 $ '    0.11 0.23 0.27 c * 1 , 7 5 $ 3  ' /< 2' 02 %  ( ( ++ 77  ) 6 27 , 0 ; 2( 7'  7$ 2( %/   (( ++ 77  7 ( $5 ( ' (+ 7: $ &+ 27 /, : 6  , 7  +1 ( ( ' 1, $& /1 3, 2 0 & 8 ( 71 $, '/       3.35 A  6 5 ( 7 ( 0 , / / , 0  1 ,  ( 5 $  6 1 2 , 6 1 ( 0 , '  / / $    14.00 BSC E1 0.37 b 0.32 0.05 0.45 A1 DETAIL A SIDE VIEW b 0.10 C 10 L2 A' SEATING PLANE A ș & 6 ( 7 2 1 DIMENSIONS ;  $  / , $ 7 ( '  ( ( 6 MIN. NOM. MAX. SYMBOL ' ;  + 2 8 D C A-B 0.13 b 0.40 C A-B D 1 30 2 5 7 30 BOTTOM VIEW 0.20 C A-B D 3 100 3 e 1 4 31 6 5 7 81 E1 E 50 50 81 80 51 51 80 5 7 D1 4 D TOP VIEW SECTION A-A' 002-15156 ** PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3.35 MM PQH100 REV** CY96340 Series 18. Ordering Information 18.1 MCU with CAN Controller Flash/ROM Subclock Persistent Low Voltage Reset Package CY96345RSAPMC-GSE1 ROM (160KB) No No 100 pin Plastic LQFP (LQI100) CY96346RSAPMC-GSE2 ROM (288KB) No No 100 pin Plastic LQFP (LQI100) Flash A (160KB) Data Flash A (64KB) No No 100 pin Plastic LQFP (LQI100) No 100 pin Plastic LQFP (LQI100) No 100 pin Plastic QFP (PQH100) No 100 pin Plastic LQFP (LQI100) No 100 pin Plastic QFP (PQH100) Part number CY96F345DSBPMC-GS-UJE1 CY96F346RSAPMCR-GS-UJE2 No CY96F346RWAPMCR-GS-UJE2 Yes CY96F346RSAPQCR-GS-UJE2 No CY96F346RWAPQCR-GS-UJE2 Yes CY96F346RSBPMC-GS-UJE2 Flash A (288KB) No CY96F346RWBPMC-GS-UJE2 Yes CY96F346RSBPQC-GS-UJE2 No CY96F346RWBPQC-GS-UJE2 Yes CY96F346RSCPMC-GS-UJE1 No No 100 pin Plastic LQFP (LQI100) CY96F347RSAPQCR-GS-UJE2 No No 100 pin Plastic QFP (PQH100) No No 100 pin Plastic LQFP (LQI100) Flash A (416KB) CY96F347RSBPMC-GS-UJE2 CY96F348RSAPMCR-GS-UJE2 No No CY96F348RSAPQCR-GS-UJE2 CY96F348RSBPMC-GS-UJE2 100 pin Plastic LQFP (LQI100) 100 pin Plastic QFP (PQH100) 100 pin Plastic LQFP (LQI100) Flash A (544KB) No No CY96F348RWCPMC-G-UJE2 Yes No 100 pin Plastic LQFP (LQI100) CY96F348HSBPMCR-GSE2 No No 100 pin Plastic LQFP (LQI100) CY96F348HSBPQCR-GSE2 No No 100 pin Plastic QFP (PQH100) No No 100 pin Plastic LQFP (LQI100) CY96F348HSCPMC-GSE1 No No 100 pin Plastic LQFP (LQI100) CY96F348HSCPQC-GSE2 No No 100 pin Plastic QFP (PQH100) CY96F348RSBPQC-GS-UJE2 CY96F348RSBPQCR-GS-UJE2 CY96F348HSCPMC-GSE2 Document Number: 002-04579 Rev. *B Flash A (544KB) Flash B (32KB) 100 pin Plastic QFP (PQH100) Page 101 of 111 CY96340 Series 18.2 MCU without CAN Controller Part number Flash/ROM Subclock 100 pin Plastic LQFP (LQI100) CY96F346ASBPMCR-GS-UJE2 Flash A (288KB) CY96F346ASBPQC-G-UJE2 No CY96F347ASBPMC-GS-UJE2 Flash A (416KB) CY96F348ASBPMC-GS-UJE2 Flash A (544KB) Package 100 pin Plastic QFP (PQH100) 100 pin Plastic LQFP (LQI100) This datasheet is also valid for the following outdated devices: CY96F346YSA, CY96F346YWA, CY96F347YSA, CY96F347YWA, CY96F347RWA, CY96F348YSA, CY96F348YWA, CY96F348RWA, CY96F348TSB, CY96F348TWB, CY96F348HWB, CY96F346ASA, CY96F346AWA, CY96F347ASA, CY96F347AWA, CY96F348ASA, CY96F348AWA, CY96F348CSB, CY96F348CWB Document Number: 002-04579 Rev. *B Page 102 of 111 CY96340 Series 19. Major Changes Page Section Change Results Rev *A 89 Electrical Characteristics 14.5. Analog Digital Converter Corrected "Value" and "Unit" of Zero reading voltage. (AVRL - 1.5 → AVRL - 1.5 LSB AVRL + 0.5 → AVRL + 0.5 LSB AVRL + 2.5 → AVRL + 2.5 LSB LSB → V) Corrected "Value" and "Unit" of Full scale reading voltage. (AVRH - 3.5 → AVRH - 3.5 LSB AVRH - 1.5 → AVRH - 1.5 LSB AVRH + 0.5 → AVRH + 0.5 LSB LSB → V) Rev *B - Marketing Part Numbers changed from an MB prefix to a CY prefix. 1 - Deleted the following comment. MB96F345: These devices are under development and specification is preliminary. These products under development may change its specification without notice. 7 1. Product Lineup Deleted the following comment. [1]: These devices are under development and specification is preliminary. These products under development may change its specification without notice. 63 14. Electrical Characteristics 14.3 DC characteristics Updated below ICCPLL value for MB96F345 at 1 Flash wait state. “PLL Run mode with CLKS1/2 = 80MHz, CLKB = CLKP1 = 40MHz, CLKP2 = 20MHz (CLKRC and CLKSC stopped. Core voltage at 1.9V)” “TA = +25 °C” (before) Typ: TBD Max: TBD (after) Typ: 38 Max: 51 “TA = +125 °C” (before) Typ: TBD Max: TBD (after) Typ: 40 Max: 54 Document Number: 002-04579 Rev. *B Page 103 of 111 CY96340 Series Page 65 Section 14. Electrical Characteristics 14.3 DC characteristics Change Results Updated below ICCSPLL value for MB96F345. "PLL Sleep mode with CLKS1/2 = 80MHz, CLKP1 = 40MHz, CLKP2 = 20MHz (CLKRC and CLKSC stopped. Core voltage at 1.9V)" "TA = +25 °C" (before) Typ: TBD Max: TBD (after) Typ: 11 Max: 13.5 "TA = +125 °C" (before) Typ: TBD Max: TBD (after) Typ: 11.7 Max: 16 10 3. Pin Assignment 16. Package Dimension CY96(F)34x LQFP 100P 103, 104 18. Ordering Information 101 Package description modified to JEDEC description. (before) FPT-100P-M20 (after) LQI100 9 3. Pin Assignment Package description modified to JEDEC description. 17. Package Dimension CY96(F)34x QFP (before) FPT-100P-M22 100P (after) PQH100 103, 104 18. Ordering Information 102 Document Number: 002-04579 Rev. *B Page 104 of 111 CY96340 Series Page Section 103, 104 18. Ordering Information Change Results Deleted the following comment. [1]: These devices are under development and specification is preliminary. These products under development may change its specification without notice. Deleted the following part number. - MB96345YSA PQC-GSE2 - MB96345RSA PQC-GSE2 - MB96345YWA PQC-GSE2 - MB96345RWA PQC-GSE2 - MB96345YSA PMC-GSE2 - MB96345RSA PMC-GSE2 - MB96345YWA PMC-GSE2 - MB96345RWA PMC-GSE2 - MB96346YSA PQC-GSE2 - MB96346RSA PQC-GSE2 - MB96346YWA PQC-GSE2 - MB96346RWA PQC-GSE2 - MB96346YSA PMC-GSE2 - MB96346YWA PMC-GSE2 - MB96346RWA PMC-GSE2 - MB96F345FSA PQC-GSE2 - MB96F345DSA PQC-GSE2 - MB96F345FWA PQC-GSE2 - MB96F345DWA PQC-GSE2 - MB96F345FSA PMC-GSE2 - MB96F345DSA PMC-GSE2 - MB96F345FWA PMC-GSE2 - MB96F345DWA PMC-GSE2 - MB96F346YSB PQC-GSE2 - MB96F346YWB PQC-GSE2 - MB96F346YSB PMC-GSE2 - MB96F346YWB PMC-GSE2 - MB96F347YSB PQC-GSE2 - MB96F347RSB PQC-GSE2 - MB96F347YWB PQC-GSE2 - MB96F347RWB PQC-GSE2 - MB96F347YSB PMC-GSE2 - MB96F347YWB PMC-GSE2 - MB96F347RWB PMC-GSE2 - MB96F348YSB PQC-GSE2 - MB96F348YWB PQC-GSE2 - MB96F348RWB PQC-GSE2 - MB96F348YSB PMC-GSE2 - MB96F348YWB PMC-GSE2 - MB96F348RWB PMC-GSE2 - MB96F348TSC PQC-GSE2 - MB96F348TWC PQC-GSE2 - MB96F348HWC PQC-GSE2 - MB96F348TSC PMC-GSE2 - MB96F348TWC PMC-GSE2 - MB96F348HWC PMC-GSE2 - MB96V300BRB-ES(for evaluation) Document Number: 002-04579 Rev. *B Page 105 of 111 CY96340 Series Page Section 103, 104 18. Ordering Information Change Results Deleted the following part number. (Continue) - MB96F346ASB PQC-GSE2 - MB96F346AWB PQC-GSE2 - MB96F346ASB PMC-GSE2 - MB96F346AWB PMC-GSE2 - MB96F347ASB PQC-GSE2 - MB96F347AWB PQC-GSE2 - MB96F347AWB PMC-GSE2 - MB96F348ASB PQC-GSE2 - MB96F348AWB PQC-GSE2 - MB96F348AWB PMC-GSE2 - MB96F348CSC PQC-GSE2 - MB96F348CWC PQC-GSE2 - MB96F348CSC PMC-GSE2 - MB96F348CWC PMC-GSE2 Revised the following parts number. (before) - MB96346RSA PMC-GSE2 - MB96F346RSB PQC-GSE2 - MB96F346RWB PQC-GSE2 - MB96F346RSB PMC-GSE2 - MB96F346RWB PMC-GSE2 - MB96F347RSB PMC-GSE2 - MB96F348RSB PQC-GSE2 - MB96F348RSB PMC-GSE2 - MB96F348HSC PQC-GSE2 - MB96F348HSC PMC-GSE2 - MB96F347ASB PMC-GSE2 - MB96F348ASB PMC-GSE2 (after) - CY96346RSAPMC-GSE2 - CY96F346RSBPQC-GS-UJE2 - CY96F346RWBPQC-GS-UJE2 - CY96F346RSBPMC-GS-UJE2 - CY96F346RWBPMC-GS-UJE2 - CY96F347RSBPMC-GS-UJE2 - CY96F348RSBPQC-GS-UJE2 - CY96F348RSBPMC-GS-UJE2 - CY96F348HSCPQC-GS-UJE2 - CY96F348HSCPMC-GS-UJE2 - CY96F347ASBPMC-GS-UJE2 - CY96F348ASBPMC-GS-UJE2 Added the following parts number. - CY96345RSAPMC-GSE1 - CY96F345DSBPMC-GS-UJE1 - CY96F346RSAPMCR-GS-UJE2 - CY96F346RWAPMCR-GS-UJE2 - CY96F346RSAPQCR-GS-UJE2 - CY96F346RWAPQCR-GS-UJE2 - CY96F346RSCPMC-GS-UJE1 - CY96F347RSAPQCR-GS-UJE2 - CY96F348RSAPMCR-GS-UJE2 - CY96F348RSAPQCR-GS-UJE2 - CY96F348RSBPQCR-GS-UJE2 - CY96F348RWCPMC-G-UJE2 - CY96F348HSBPMCR-GSE2 - CY96F348HSBPQCR-GSE2 - CY96F348HSCPMC-GSE1 - CY96F346ASBPMCR-GS-UJE2 - CY96F346ASBPQC-G-UJE2 Document Number: 002-04579 Rev. *B Page 106 of 111 CY96340 Series Page Section 103, 104 18. Ordering Information Change Results Changed and deleted the parts number in Note. (before) MB96F346YSA, MB96F346RSA, MB96F346YWA, MB96F346RWA, MB96F347YSA, MB96F347RSA, MB96F347YWA, MB96F347RWA, MB96F348YSA, MB96F348RSA, MB96F348YWA, MB96F348RWA, MB96F348TSB, MB96F348HSB, MB96F348TWB, MB96F348HWB, MB96F346ASA, MB96F346AWA, MB96F347ASA, MB96F347AWA, MB96F348ASA, MB96F348AWA, MB96F348CSB, MB96F348CWB (after) CY96F346YSA, CY96F346YWA, CY96F347YSA, CY96F347YWA, CY96F347RWA, CY96F348YSA, CY96F348YWA, CY96F348RWA, CY96F348TSB, CY96F348TWB, CY96F348HWB, CY96F346ASA, CY96F346AWA, CY96F347ASA, CY96F347AWA, CY96F348ASA, CY96F348AWA, CY96F348CSB, CY96F348CWB 105 19. Major Changes Changed section title and section number. (before) 20. Main Changes in this Edition (after) 19. Major Changes 110 20. Revision History Changed section number. (before) 19. Revision History (after) 20. Revision History Document Number: 002-04579 Rev. *B Page 107 of 111 CY96340 Series 20. Revision History Revision Date Modification Prelim 1 2007-05-07 Creation Prelim 2 2007-05-10 External bus hold timing update Prelim 3 2007-05-23 Electrical characteristics updates Prelim 4 2007-08-02 Electrical characteristics updates, Product lineup, changes and ordering information Prelim 5 2007-09-12 Addition of the electrical characteristic examples and the LVD characteristics specifications, updates of the DC characteristics. Pin circuit type drawing modifications. Prelim 6 2007-11-21 LVD typo correction. Update of the DC characteristics. Typos corrections. Prelim 7 2007-12-04 Absolute maximum rating asterisks numbering corrected. Typos page 59: Hardware -> Hardware. IO map table regenerated. Typos corrections. IO circuit drawings modified. Renaming of the Main/Satellite Flash into Flash memory A/B. Memory map reworked. Prelim 8 2008-02-04 ■ Satellite Flash -> 32kB Data Flash ■ MB96345 added (under development) ■ MB96F348 TSA/HSA/TWA/HWA removed (outdated devices) ■ Block diagram and pin assignment corrected (existing resource pins) ■ Pin function table corrected ■ I/O circuit type diagrams corrected ■ Memory map cleaned up ■ "Flash sector configuration" replaced by corrected "User ROM Memory map for Flash devices", “ROM configuration” replaced by “User ROM Memory map for Mask ROM devices” ■ Parallel Flash programming pinning removed ■ IO map table regenerated: ❐ Port register: Naming style corrected ❐ Memory control registers renamed (Main/Sat -> A/B) ❐ addresses after 000BFFh removed ■ Absolute maximum ratings: Pd and Ta specified more precisely ■ oscillator input levels in oscillation mode with external clock added ■ Run and Sleep mode currents: 96/48MHz and 72/36MHz settings added ■ Run mode current spec in 48/24MHz mode corrected ■ Maximum CLKS1/2 frequency for all devices correctly specified ■ Maximum CLKP2 for MB96F34xY/R/Axx corrected ■ External bus timings: missing conditions added and readability improved ■ Alarm comparator spec updated (transition voltages defined) ■ MB96V300A removed ■ Ordering information updated ■ Typos and formatting corrected Document Number: 002-04579 Rev. *B Page 108 of 111 CY96340 Series Revision 9 Date 2009-01-09 Modification ■ Format adjusted to official Cypress datasheet standard (mainly style changes and official notes and disclaimer added) ■ Numbering of Electrical Characteristics subchapters automated ■ Note about devices under development modified ■ I/O map: Note added about reserved addresses ■ ICCSPLL for CLKS1=96MHz mode: increased by 1mA ■ Serial programming interface: Note about handshaking pins improved ■ specified AD converter channel offset to 4LSB ■ package code of MB96V300 corrected in ordering information ■ Added voltage condition to pull-up resistance spec ■ Lineup: Term “Data Flash” replaced by “independent 32KB Flash” ■ Ordering information: column “Independent 32KB Data Flash” replaced by new column “Flash/ROM”, column “Remarks” removed ■ Official package dimension drawing with additional notes added ■ Empty pages removed ■ Alarm comparator: Power supply current max values increased, comparison time reduced, mode transition time and power-up stabilization time newly added ■ Handling devices: Notes added about Serial communication and about using ceramic resonators. ■ Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For resonators, maximum frequency depends on Q-factor ■ AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz ■ VOL3 spec improved: spec valid for 3mA load for full Vcc range ■ MB96F345 added ■ Preliminary DC spec of MB96345/346 added ■ Permitted power dissipation of Flash devices in QFP package improved ■ C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted ■ “Preliminary” watermark removed 10 To be released ■ I/O map: IOABK0-5 added at address 000A00H-000A05H ■ Ordering Information: Suffix “A” added to all MB96F345 device versions ■ AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg NOTE: Please see “Document History” for later revised information. Document Number: 002-04579 Rev. *B Page 109 of 111 CY96340 Series Document History Spansion Publication Number: DS07-13802-3E Document Title: CY96345/346, CY96F346/F347/F348, F2MC-16FX, CY96340 Series, 16-bit Proprietary Microcontroller Datasheet Document Number: 002-04579 Revision ECN Orig. of Change Submission Date ** − AKIH 06/17/2009 Migrated to Cypress and assigned document number 002-04579. No change to document contents or format. *A 5198948 AKIH 04/01/2016 Updated to Cypress template *B 6184340 GSHI 05/31/2018 Revised the following items: Marketing Part Numbers changed from an MB prefix to a CY prefix. 3.Pin Assignments 16.Package Dimension 17.Package Dimension 18.Ordering Information Added 19. Major Changes For details, please see 19.Major Changes Document Number: 002-04579 Rev. *B Description of Change Page 110 of 111 CY96340 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2009-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. 111 TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04579 Rev. *B Revised May 31, 2018 Page 111 of 111