MB96F356RWBPMC1-GSE2

FUJITSU MICROELECTRONICS DATA SHEET FME-MB96350 rev 6 16-bit Proprietary Microcontroller CMOS F2MC-16FX MB96350 Series MB96F353/F355 *1 MB96F356 ■ DESCRIPTION MB96350 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller For the information for microcontroller support, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright©2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.1 MB96350 Series ■ FEATURES Feature Technology Description • 0.18µm CMOS • F2MC-16FX CPU • Up to 56 MHz internal, 17.8 ns instruction cycle time CPU • Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) • 8-byte instruction execution queue • Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available • On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) • 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor). • Up to 56 MHz external clock • 32-100 kHz subsystem quartz clock System clock • 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog • Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. • Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) • Clock modulator On-chip voltage regula- • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI tor and low power consumption figures Low voltage reset Code Security Memory Patch Function DMA • Reset is generated when supply voltage is below minimum. • Protects ROM content from unintended read-out • Replaces ROM content • Can also be used to implement embedded debug support • Automatic transfer function independent of CPU, can be assigned freely to resources • Fast Interrupt processing Interrupts • 8 programmable priority levels • Non-Maskable Interrupt (NMI) Timers • Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) • Watchdog Timer 2 FME-MB96350 rev 6 MB96350 Series Feature Description • Supports CAN protocol version 2.0 part A and B • ISO16845 certified • Bit rates up to 1 Mbit/s • 32 message objects CAN • Each message object has its own identifier mask • Programmable FIFO mode (concatenation of message objects) • Maskable interrupt • Disabled Automatic Retransmission mode for Time Triggered CAN applications • Programmable loop-back mode for self-test operation • Full duplex USARTs (SCI/LIN) USART • Wide range of baud rate settings using a dedicated reload timer • Special synchronous options for adapting to different synchronous serial protocols • LIN functionality working either as master or slave LIN device I2C • Up to 400 kbps • Master and Slave functionality, 8-bit and 10-bit addressing • SAR-type A/D converter • 10-bit resolution • Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer • 16-bit wide Reload Timers • Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency • Event count function Free Running Timers • Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency • 16-bit wide Input Capture Units • Signals an interrupt upon external event • Rising edge, falling edge or rising & falling edge sensitive • 16-bit wide Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs • A pair of compare registers can be used to generate an output signal. • 16-bit down counter, cycle and duty setting registers • Interrupt at trigger, counter borrow and/or duty match Programmable Pulse Generator • PWM operation and one-shot operation • Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow as clock input • Can be triggered by software or reload timer FME-MB96350 rev 6 3 MB96350 Series Feature Description • Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the RC oscillator Real Time Clock • Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) • Read/write accessible second/minute/hour registers • Can signal interrupts every half second/second/minute/hour/day • Internal clock divider and prescaler provide exact 1s clock • Edge sensitive or level sensitive External Interrupts • Interrupt mask and pending bit per channel • Each available CAN channel RX has an external interrupt for wake-up • Selected USART channels SIN have an external interrupt for wake-up • Disabled after reset Non Maskable Interrupt • Once enabled, can not be disabled other than by reset. • Level high or level low sensitive • Pin shared with external interrupt 0. • 8-bit or 16-bit bidirectional data • Up to 24-bit addresses • 6 chip select signals External bus interface • Multiplexed address/data lines • Wait state request • External bus master possible • Timing programmable • Virtually all external pins can be used as general purpose I/O • All push-pull outputs (except when used as I2C SDA/SCL line) • Bit-wise programmable as input/output or peripheral signal I/O Ports • Bit-wise programmable input enable • Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL • Bit-wise programmable pull-up resistor • Bit-wise programmable output driving strength for EMI optimization Packages 4 • 64-pin plastic LQFP M23/M24 FME-MB96350 rev 6 MB96350 Series Feature Description • Supports automatic programming, Embedded Algorithm • Write/Erase/Erase-Suspend/Resume commands • A flag indicating completion of the algorithm • Number of erase cycles: 10,000 times Flash Memory • Data retention time: 20 years • Erase can be performed on each sector individually • Sector protection • Flash Security feature to protect the content of the Flash • Low voltage detection during Flash erase FME-MB96350 rev 6 5 MB96350 Series ■ PRODUCT LINEUP Features MB96V300B MB96(F)35x Product type Evaluation sample Flash product: MB96F35x Mask ROM product: MB9635x Product options YS Low voltage reset persistently on / Single clock devices RS Low voltage reset can be disabled / Single clock devices YW Low voltage reset persistently on / Dual clock devices NA RW Low voltage reset can be disabled / Dual clock devices AS No CAN / Low voltage reset can be disabled / Single clock devices AW No CAN / Low voltage reset can be disabled / Dual clock devices Flash/ ROM RAM 96KB 8KB 160KB 8KB 288KB 12KB MB96F353R, MB96F353A *1 MB96F355R, MB96F355A *1 MB96F356Y, MB96F356R, MB96F356A Package BGA416 FPT-64P-M23/24 DMA 16 channels 4 channels USART 10 channels 4 channels I2C 2 channels 1 channel A/D Converter 40 channels 15 channels A/D Converter Reference Voltage switch yes No 16-bit Reload Timer 6 channels + 1 channel (for PPG) 4 channels + 1 channel (for PPG) 16-bit Free-Running Timer 4 channels 4 channels (2 channels with external clock input pin) 16-bit Output Compare 12 channels 4 channels 16-bit Input Capture 12 channels 6 channels (plus 2 channels for LIN USART) 16-bit Programmable Pulse Generator 20 channels 20 channels CAN Interface 5 channels MB96F35xA: no MB96F353R/F355R: 1 channel MB96F356Y/R: 2 channels External Interrupts 16 channels 13 channels Non-Maskable Interrupt 6 ROM/Flash memory emulation by external RAM, 92KB internal RAM 1 channel FME-MB96350 rev 6 MB96350 Series Features MB96V300B Real Time Clock I/O Ports MB96(F)35x 1 136 49 for part number with suffix "W", 51 for part number with suffix "S" External bus interface Yes Chip select 6 signals Clock output function 2 channels Low voltage reset Yes On-chip RC-oscillator Yes *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. FME-MB96350 rev 6 7 MB96350 Series ■ BLOCK DIAGRAM Block diagram of MB96(F)35x AD00 ... AD15 A16 ... A21 ALE RDX WR(L)X, WRHX HRQ HAKX RDY ECLK CS0_R ... CS5_R External Bus Interface CKOT0_R, CKOT1, CKOT1_R CKOTX1 X0, X1 X0A, X1A *1 RSTX MD0...MD2 NMI_R Interrupt Controller 16FX CPU Flash Memory A Clock & Mode Controller Memory Patch Unit 16FX Core Bus (CLKB) AVCC AVSS AVRH AN0 ... AN14 ADTG_R TIN0_R, TIN2_R TIN1, TIN3 TOT0_R, TOT2_R TOT1, TOT3 FRCK0 IN0 ... IN1 Peripheral Bus Bridge Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) SDA0 SCL0 Watchdog I2C 1 ch. 10-bit ADC 15 ch. 16-bit Reload Timer 4 ch. I/O Timer 0 ICU 0/1 Peripheral Bus 1 (CLKP1) DMA Controller USART 4 ch. 16-bit PPG 20 ch. RLT6 FRCK1 IN4 ... IN7 OUT4 ... OUT7 I/O Timer 1 ICU 4/5/6/7 OCU 4/5/6/7 Real Time Clock I/O Timer 2 ICU 9 I/O Timer 3 ICU 10 External Interrupt RAM Voltage Regulator Boot ROM VCC VSS C CAN Interface 2 ch. TX1 *2, TX2 *3 RX1*2 , RX2 *3 SIN2, SIN2_R, SIN3, SIN7_R, SIN8_R SOT2, SOT2_R, SOT3, SOT7_R, SOT8_R SCK2, SCK2_R, SCK3, SCK7_R, SCK8_R TTG0, TTG1, TTG4 ... TTG9, TTG12 ... TTG15 TTG8_R ... TTG11_R, TTG16_R ... TTG19_R PPG0 ... PPG7, PPG12 ... PPG15 PPG8_R ... PPG11_R, PPG16_R ... PPG19_R WOT INT8 ... INT15 INT0_R, INT2_R, INT4_R INT7_R, INT9_R ... INT11_R INT3_R1 *1: X0A, X1A only available on devices with suffix “W” *2: TX1, RX1 only available on MB96F356Y/R *3: TX2, RX2 only available on MB96F356Y/R and MB96F353R/F355R 8 FME-MB96350 rev 6 MB96350 Series ■ PIN ASSIGNMENTS P01_1/AD09/CKOTX1/TOT1/TTG17_R P01_2/AD10/INT11_R/SIN3/TTG18_R P01_3/AD11/SOT3/TTG19_R P01_4/AD12/SCK3/PPG16_R P01_5/AD13/SIN2_R/INT7_R/PPG17_R P01_6/AD14/SOT2_R/PPG18_R P01_7/AD15/SCK2_R/PPG19_R P02_0/A16/PPG12/CKOT1_R P02_1/A17/PPG13 P02_2/A18/PPG14/CKOT0_R P02_3/A19/PPG15 P02_4/A20/TTG8/TTG0/IN0 RSTX X1 X0 Vss Pin assignment of MB96(F)35x 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 P01_0/AD08/CKOT1/TIN1/TTG16_R C 50 31 P00_7/AD07/INT15/PPG11_R P02_5/A21/TTG9/TTG1/IN1/ADTG_R 51 30 P00_6/AD06/INT14/PPG10_R P04_4/SDA0/FRCK0/TIN0_R 52 29 P00_5/AD05/INT13/SIN8_R/PPG9_R P04_5/SCL0/FRCK1/TIN2_R 53 28 P00_4/AD04/INT12/SOT8_R/PPG8_R P03_0/ALE/IN4/TTG4/TTG12/TOT0_R 54 27 P00_3/AD03/INT11/SCK8_R/TTG11_R P03_1/RDX/IN5/TTG5/TTG13/TOT2_R 55 26 P00_2/AD02/INT10/SIN7_R/TTG10_R P03_2/WR(L)X/RX2/INT10_R *3 56 25 P00_1/AD01/INT9/SOT7_R/TTG9_R P03_3/TX2/WRHX *3 57 24 P00_0/AD00/INT8/SCK7_R/TTG8_R P03_4/HRQ/OUT4 58 23 MD0 P03_5/HAKX/OUT5 59 22 MD1 P03_6/RDY/OUT6 60 21 MD2 P03_7/ECLK/OUT7 61 20 X1A/P04_1 *1 P06_0/AN0/PPG0/CS0_R 62 19 X0A/P04_0 P06_1/AN1/PPG1/CS1_R 63 18 Vss AVcc 64 LQFP - 64 *2: TX1, RX1 only available on MB96F356Y/R *3: TX2, RX2 only available on MB96F356Y/R and MB96F353R/F355R *1 *2 *2 P04_3/IN7/TX1/TTG7/TTG15 P04_2/IN6/RX1/INT9_R/TTG6/TTG14 *1: Devices with suffix W: X0A, X1A Devices with suffix S: P04_0, P04_1 P05_6/AN14/INT4_R P05_5/AN13/INT0_R/NMI_R P05_4/AN12/TOT3/INT2_R 17 9 10 11 12 13 14 15 16 P05_3/AN11/TIN3/WOT 8 P05_2/AN10/SCK2 7 P05_1/AN9/SOT2 P06_3/AN3/PPG3/CS3_R 6 P05_0/AN8/SIN2/INT3_R1 P06_2/AN2/PPG2/CS2_R 5 P06_7/AN7/PPG7 4 P06_6/AN6/PPG6 3 P06_5/AN5/PPG5/CS5_R 2 P06_4/AN4/PPG4/CS4_R 1 AVss Package code (mold) FPT-64P-M23/M24 AVRH Vcc (FPT-64P-M23/M24) Remark: MB96(F)35x products are pin-compatible to F2MC-16LX family MB90350 series. FME-MB96350 rev 6 9 MB96350 Series ■ PIN FUNCTION DESCRIPTION Pin Function description (1 of 2) 10 Pin name Feature Description ADn External bus External bus interface (multiplexed mode) address output and data input/output ADTG_R ADC Relocated A/D converter trigger input ALE External bus External bus Address Latch Enable output An External bus External bus address output ANn ADC A/D converter channel n input AVCC Supply Analog circuits power supply AVRH ADC A/D converter high reference voltage input AVSS Supply Analog circuits power supply C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock output function Clock Output function n output CKOTn_R Clock output function Relocated Clock Output function n output CKOTXn Clock output function Clock Output function n inverted output ECLK External bus External bus clock output CSn_R External bus Relocated External bus chip select n output FRCKn Free Running Timer Free Running Timer n input HAKX External bus External bus Hold Acknowledge HRQ External bus External bus Hold Request INn ICU Input Capture Unit n input INTn External Interrupt External Interrupt n input INTn_R External Interrupt Relocated External Interrupt n input MDn Core Input pins for specifying the operating mode. NMI_R External Interrupt Relocated Non-Maskable Interrupt input OUTn OCU Output Compare Unit n waveform output Pxx_n GPIO General purpose IO PPGn PPG Programmable Pulse Generator n output PPGn_R PPG Relocated Programmable Pulse Generator n output RDX External bus External bus interface read strobe output RDY External bus External bus interface external wait state request input FME-MB96350 rev 6 MB96350 Series Pin Function description (2 of 2) Pin name Feature Description RSTX Core Reset input RXn CAN CAN interface n RX input SCKn USART USART n serial clock input/output SCKn_R USART Relocated USART n serial clock input/output SCLn I2C I2C interface n clock I/O input/output SDAn I2C I2C interface n serial data I/O input/output SINn USART USART n serial data input SINn_R USART Relocated USART n serial data input SOTn USART USART n serial data output SOTn_R USART Relocated USART n serial data output TINn Reload Timer Reload Timer n event input TINn_R Reload Timer Relocated Reload Timer n event input TOTn Reload Timer Reload Timer n output TOTn_R Reload Timer Relocated Reload Timer n output TTGn PPG Programmable Pulse Generator n trigger input TTGn_R PPG Relocated Programmable Pulse Generator n trigger input TXn CAN CAN interface n TX output VCC Supply Power supply VSS Supply Power supply WOT RTC Real Timer clock output WRHX External bus External bus High byte write strobe output WRLX/WRX External bus External bus Low byte / Word write strobe output X0 Clock Oscillator input X0A Clock Subclock Oscillator input (only for devices with suffix "W") X1 Clock Oscillator output X1A Clock Subclock Oscillator output (only for devices with suffix "W") FME-MB96350 rev 6 11 MB96350 Series ■ PIN CIRCUIT TYPE Pin circuit types FPT-64P-M23/24 Pin no. Circuit type *1 1 Supply 2 G 3 to 15 I 16,17 H 18 Supply 19,20 B *2 19,20 H *3 21 to 23 C 24 to 44 H 45 E 46,47 A 48,49 Supply 50 F 51 H 52,53 N 54 to 61 H 62,63 I 64 Supply *1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types *2: Devices with suffix ”W” *3: Devices without suffix ”W” 12 FME-MB96350 rev 6 MB96350 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A X1 R 0 Xout MRFBE 1 High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Programmable feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode FCI R X0 FCI or osc disable B Xout X1A Low-speed oscillation circuit: • Programmable feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled R SRFBE R X0A osc disable C R Hysteresis inputs E • Mask ROM and EVA device: CMOS Hysteresis input pin • Flash device: CMOS input pin • CMOS Hysteresis input pin • Pull-up resistor value: approx. 50 kΩ Pull-up Resistor R FME-MB96350 rev 6 Hysteresis inputs 13 MB96350 Series Type Circuit Remarks F • Power supply input protection circuit G • A/D converter ref+ (AVRH) power supply input pin with protection circuit • Flash devices do not have a protection circuit against VCC for pin AVRH ANE AVR ANE H pull-up control Pout Nout R Standby control for input shutdown 14 Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. * MB96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported FME-MB96350 rev 6 MB96350 Series Type Circuit Remarks I Pull-up control Pout Nout • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function. • Programmable pull-up resistor: 50kΩ approx. • Analog input R Hysteresis input Standby control for input shutdown Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input * MB96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported Analog input N pull-up control Pout • CMOS level output (IOL = 3mA, IOH = -3mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. Nout R Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input FME-MB96350 rev 6 * MB96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported 15 MB96350 Series ■ MEMORY MAP MB96V300B MB96(F)35x Emulation ROM USER ROM / External Bus*4 External Bus External Bus Boot-ROM Boot-ROM FF:FFFFH DE:0000H 10:0000H 0F:E000H Reserved 0E:0000H Reserved External RAM 02:0000H Internal RAM bank 1 RAMEND1*2 RAMSTART12 01:0000H ROM/RAM MIRROR Reserved Internal RAM bank 1 Reserved RAM availability depending on the device ROM/RAM MIRROR 00:8000H Internal RAM bank 0 RAMSTART0 Internal RAM bank 0 Reserved External Bus end address*2 External Bus RAMSTART0*3 00:0C00H *2 External Bus Peripherals Peripherals GPR*1 GPR*1 DMA DMA External Bus External Bus Peripheral Peripheral 00:0380H 00:0180H 00:0100H 00:00F0H 00:0000H *1: Unused GPR banks can be used as RAM area *2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page. *3: For EVA device, RAMSTART0 depends on the configuration of the emulated device. *4: For details about USER ROM area, see the ■ USER ROM MEMORY MAP FOR FLASH DEVICES on the following pages. The External Bus area and DMA area are only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. 16 FME-MB96350 rev 6 MB96350 Series ■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES Devices Bank 0 Bank 1 External Bus RAM size RAM size end address RAMSTART0 RAMSTART1 RAMEND1 MB96F353/F355 8KByte - 00:51FFH 00:6240H - - MB96F356 12KByte - 00:51FFH 00:5240H - - FME-MB96350 rev 6 17 MB96350 Series ■ USER ROM MEMORY MAP FOR FLASH DEVICES Alternative mode CPU address Flash memory mode address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H MB96F353 MB96F355 MB96F356 Flash size 96kByte Flash size 160kByte Flash size 288kByte S39 - 64K S39 - 64K S38 - 64K S39 - 64K S38 - 64K S37 - 64K S36 - 64K External bus Flash A External bus External bus Reserved Reserved Reserved SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 Reserved Reserved Reserved Flash A DE:0000H *1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH 18 FME-MB96350 rev 6 MB96350 Series ■ SERIAL PROGRAMMING COMMUNICATION INTERFACE USART pins for Flash serial programming (MD[2:0] = 010) MB96F35x Pin number USART Number Normal function LQFP-64 9 10 SIN2 USART2 SOT2 11 SCK2 34 SIN3 35 USART3 SOT3 36 SCK3 26 SIN7_R 25 USART7 SOT7_R 24 SCK7_R 29 SIN8_R 28 27 USART8 SOT8_R SCK8_R Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor to support at least port P00_1 on pin 25. If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. FME-MB96350 rev 6 19 MB96350 Series ■ I/O MAP I/O map MB96(F)35x (1 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000000H I/O Port P00 - Port Data Register PDR00 R/W 000001H I/O Port P01 - Port Data Register PDR01 R/W 000002H I/O Port P02 - Port Data Register PDR02 R/W 000003H I/O Port P03 - Port Data Register PDR03 R/W 000004H I/O Port P04 - Port Data Register PDR04 R/W 000005H I/O Port P05 - Port Data Register PDR05 R/W 000006H I/O Port P06 - Port Data Register PDR06 R/W 000007H000017H Reserved 000018H ADC0 - Control Status register Low ADCSL 000019H ADC0 - Control Status register High ADCSH 00001AH ADC0 - Data Register Low ADCRL 00001BH ADC0 - Data Register High ADCRH 00001CH ADC0 - Setting Register 00001DH ADC0 - Setting Register 00001EH ADC0 - Extended Configuration Register 00001FH Reserved 000020H FRT0 - Data register of free-running timer 000021H FRT0 - Data register of free-running timer 000022H FRT0 - Control status register of free-running timer Low TCCSL0 000023H FRT0 - Control status register of free-running timer High TCCSH0 000024H FRT1 - Data register of free-running timer 000025H FRT1 - Data register of free-running timer 000026H FRT1 - Control status register of free-running timer Low TCCSL1 000027H FRT1 - Control status register of free-running timer High TCCSH1 000028H000033H Reserved 20 ADCS R/W R/W ADCR R R ADSR R/W R/W ADECR R/W TCDT0 R/W R/W TCCS0 R/W R/W TCDT1 R/W R/W TCCS1 R/W R/W - FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (2 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000034H OCU4 - Output Compare Control Status OCS4 R/W 000035H OCU5 - Output Compare Control Status OCS5 R/W 000036H OCU4 - Compare Register 000037H OCU4 - Compare Register 000038H OCU5 - Compare Register 000039H OCU5 - Compare Register 00003AH OCU6 - Output Compare Control Status OCS6 R/W 00003BH OCU7 - Output Compare Control Status OCS7 R/W 00003CH OCU6 - Compare Register 00003DH OCU6 - Compare Register 00003EH OCU7 - Compare Register 00003FH OCU7 - Compare Register 000040H ICU0/ICU1 - Control Status Register ICS01 R/W 000041H ICU0/ICU1 - Edge register ICE01 R/W 000042H ICU0 - Capture Register Low IPCPL0 000043H ICU0 - Capture Register High IPCPH0 000044H ICU1 - Capture Register Low IPCPL1 000045H ICU1 - Capture Register High IPCPH1 R OCCP4 R/W R/W OCCP5 R/W R/W OCCP6 R/W R/W OCCP7 R/W R/W IPCP0 R R IPCP1 R 000046H 00004BH Reserved 00004CH ICU4/ICU5 - Control Status Register ICS45 R/W 00004DH ICU4/ICU5 - Edge register ICE45 R/W 00004EH ICU4 - Capture Register Low IPCPL4 00004FH ICU4 - Capture Register High IPCPH4 000050H ICU5 - Capture Register Low IPCPL5 000051H ICU5 - Capture Register High IPCPH5 R 000052H ICU6/ICU7 - Control Status Register ICS67 R/W 000053H ICU6/ICU7 - Edge register ICE67 R/W 000054H ICU6 - Capture Register Low IPCPL6 000055H ICU6 - Capture Register High IPCPH6 FME-MB96350 rev 6 IPCP4 R R IPCP5 IPCP6 R R R 21 MB96350 Series I/O map MB96(F)35x (3 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access IPCP7 R 000056H ICU7 - Capture Register Low IPCPL7 000057H ICU7 - Capture Register High IPCPH7 R 000058H EXTINT0 - External Interrupt Enable Register ENIR0 R/W 000059H EXTINT0 - External Interrupt Interrupt request Register EIRR0 R/W 00005AH EXTINT0 - External Interrupt Level Select Low ELVRL0 00005BH EXTINT0 - External Interrupt Level Select High ELVRH0 R/W 00005CH EXTINT1 - External Interrupt Enable Register ENIR1 R/W 00005DH EXTINT1 - External Interrupt Interrupt request Register EIRR1 R/W 00005EH EXTINT1 - External Interrupt Level Select Low ELVRL1 00005FH EXTINT1 - External Interrupt Level Select High ELVRH1 000060H RLT0 - Timer Control Status Register Low TMCSRL0 000061H RLT0 - Timer Control Status Register High TMCSRH0 000062H RLT0 - Reload Register - for writing TMRLR0 W 000062H RLT0 - Reload Register - for reading TMR0 R 000063H RLT0 - Reload Register - for writing W 000063H RLT0 - Reload Register - for reading R 000064H RLT1 - Timer Control Status Register Low TMCSRL1 000065H RLT1 - Timer Control Status Register High TMCSRH1 000066H RLT1 - Reload Register - for writing TMRLR1 W 000066H RLT1 - Reload Register - for reading TMR1 R 000067H RLT1 - Reload Register - for writing W 000067H RLT1 - Reload Register - for reading R 000068H RLT2 - Timer Control Status Register Low TMCSRL2 000069H RLT2 - Timer Control Status Register High TMCSRH2 00006AH RLT2 - Reload Register - for writing TMRLR2 W 00006AH RLT2 - Reload Register - for reading TMR2 R 00006BH RLT2 - Reload Register - for writing W 00006BH RLT2 - Reload Register - for reading R 00006CH RLT3 - Timer Control Status Register Low 22 TMCSRL3 ELVR0 ELVR1 R/W R/W R/W TMCSR0 R/W R/W TMCSR1 R/W R/W TMCSR2 R/W R/W TMCSR3 R/W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (4 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access 00006DH RLT3 - Timer Control Status Register High 00006EH RLT3 - Reload Register - for writing TMRLR3 W 00006EH RLT3 - Reload Register - for reading TMR3 R 00006FH RLT3 - Reload Register - for writing W 00006FH RLT3 - Reload Register - for reading R 000070H RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) TMCSRL6 000071H RLT6 - Timer Control Status Register High (dedic. RLT for PPG) TMCSRH6 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for writing TMRLR6 W 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for reading TMR6 R 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for writing W 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for reading R 000074H PPG3-PPG0 - General Control register 1 Low GCN1L0 000075H PPG3-PPG0 - General Control register 1 High GCN1H0 000076H PPG3-PPG0 - General Control register 2 Low GCN2L0 000077H PPG3-PPG0 - General Control register 2 High GCN2H0 000078H PPG0 - Timer register 000079H PPG0 - Timer register 00007AH PPG0 - Period setting register 00007BH PPG0 - Period setting register 00007CH PPG0 - Duty cycle register 00007DH PPG0 - Duty cycle register 00007EH PPG0 - Control status register Low PCNL0 00007FH PPG0 - Control status register High PCNH0 000080H PPG1 - Timer register 000081H PPG1 - Timer register 000082H PPG1 - Period setting register FME-MB96350 rev 6 TMCSRH3 Access R/W TMCSR6 R/W R/W GCN10 R/W R/W GCN20 R/W R/W PTMR0 R R PCSR0 W W PDUT0 W W PCN0 R/W R/W PTMR1 R R PCSR1 W 23 MB96350 Series I/O map MB96(F)35x (5 of 28) Abbreviation 8-bit access Address Register 000083H PPG1 - Period setting register 000084H PPG1 - Duty cycle register 000085H PPG1 - Duty cycle register 000086H PPG1 - Control status register Low PCNL1 000087H PPG1 - Control status register High PCNH1 000088H PPG2 - Timer register 000089H PPG2 - Timer register 00008AH PPG2 - Period setting register 00008BH PPG2 - Period setting register 00008CH PPG2 - Duty cycle register 00008DH PPG2 - Duty cycle register 00008EH PPG2 - Control status register Low PCNL2 00008FH PPG2 - Control status register High PCNH2 000090H PPG3 - Timer register 000091H PPG3 - Timer register 000092H PPG3 - Period setting register 000093H PPG3 - Period setting register 000094H PPG3 - Duty cycle register 000095H PPG3 - Duty cycle register 000096H PPG3 - Control status register Low PCNL3 000097H PPG3 - Control status register High PCNH3 000098H PPG7-PPG4 - General Control register 1 Low GCN1L1 000099H PPG7-PPG4 - General Control register 1 High GCN1H1 00009AH PPG7-PPG4 - General Control register 2 Low GCN2L1 00009BH PPG7-PPG4 - General Control register 2 High GCN2H1 00009CH PPG4 - Timer register 00009DH PPG4 - Timer register 00009EH PPG4 - Period setting register 00009FH PPG4 - Period setting register 0000A0H PPG4 - Duty cycle register 24 Abbreviation 16-bit access Access W PDUT1 W W PCN1 R/W R/W PTMR2 R R PCSR2 W W PDUT2 W W PCN2 R/W R/W PTMR3 R R PCSR3 W W PDUT3 W W PCN3 R/W R/W GCN11 R/W R/W GCN21 R/W R/W PTMR4 R R PCSR4 W W PDUT4 W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (6 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0000A1H PPG4 - Duty cycle register 0000A2H PPG4 - Control status register Low PCNL4 0000A3H PPG4 - Control status register High PCNH4 0000A4H PPG5 - Timer register 0000A5H PPG5 - Timer register 0000A6H PPG5 - Period setting register 0000A7H PPG5 - Period setting register 0000A8H PPG5 - Duty cycle register 0000A9H PPG5 - Duty cycle register 0000AAH PPG5 - Control status register Low PCNL5 0000ABH PPG5 - Control status register High PCNH5 R/W 0000ACH I2C0 - Bus Status Register IBSR0 R 0000ADH I2C0 - Bus Control Register IBCR0 R/W 0000AEH I2C0 - Ten bit Slave address Register Low ITBAL0 0000AFH I2C0 - Ten bit Slave address Register High ITBAH0 0000B0H I2C0 - Ten bit Address mask Register Low ITMKL0 0000B1H I2C0 - Ten bit Address mask Register High ITMKH0 R/W 0000B2H I2C0 - Seven bit Slave address Register ISBA0 R/W 0000B3H I2C0 - Seven bit Address mask Register ISMK0 R/W 0000B4H I2C0 - Data Register IDAR0 R/W 0000B5H I2C0 - Clock Control Register ICCR0 R/W 0000B6H0000D3H Reserved 0000D4H USART2 - Serial Mode Register SMR2 R/W 0000D5H USART2 - Serial Control Register SCR2 R/W 0000D6H USART2 - TX Register TDR2 W 0000D6H USART2 - RX Register RDR2 R 0000D7H USART2 - Serial Status SSR2 R/W 0000D8H USART2 - Control/Com. Register ECCR2 R/W 0000D9H USART2 - Ext. Status Register ESCR2 R/W FME-MB96350 rev 6 W PCN4 R/W R/W PTMR5 R R PCSR5 W W PDUT5 W W PCN5 ITBA0 R/W R/W R/W ITMK0 R/W - 25 MB96350 Series I/O map MB96(F)35x (7 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access BGR2 R/W 0000DAH USART2 - Baud Rate Generator Register Low BGRL2 0000DBH USART2 - Baud Rate Generator Register High BGRH2 R/W 0000DCH USART2 - Extended Serial Interrupt Register ESIR2 R/W 0000DDH Reserved 0000DEH USART3 - Serial Mode Register SMR3 R/W 0000DFH USART3 - Serial Control Register SCR3 R/W 0000E0H USART3 - TX Register TDR3 W 0000E0H USART3 - RX Register RDR3 R 0000E1H USART3 - Serial Status SSR3 R/W 0000E2H USART3 - Control/Com. Register ECCR3 R/W 0000E3H USART3 - Ext. Status Register ESCR3 R/W 0000E4H USART3 - Baud Rate Generator Register Low BGRL3 0000E5H USART3 - Baud Rate Generator Register High BGRH3 R/W 0000E6H USART3 - Extended Serial Interrupt Register ESIR3 R/W 0000E7H0000EFH Reserved 0000F0H0000FFH External Bus area 000100H - BGR3 R/W EXTBUS0 R/W DMA0 - Buffer address pointer low byte BAPL0 R/W 000101H DMA0 - Buffer address pointer middle byte BAPM0 R/W 000102H DMA0 - Buffer address pointer high byte BAPH0 R/W 000103H DMA0 - DMA control register DMACS0 R/W 000104H DMA0 - I/O register address pointer low byte IOAL0 000105H DMA0 - I/O register address pointer high byte IOAH0 000106H DMA0 - Data counter low byte DCTL0 000107H DMA0 - Data counter high byte DCTH0 R/W 000108H DMA1 - Buffer address pointer low byte BAPL1 R/W 000109H DMA1 - Buffer address pointer middle byte BAPM1 R/W 00010AH DMA1 - Buffer address pointer high byte BAPH1 R/W 00010BH DMA1 - DMA control register DMACS1 R/W 00010CH DMA1 - I/O register address pointer low byte 26 IOAL1 IOA0 R/W R/W DCT0 IOA1 R/W R/W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (8 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 00010DH DMA1 - I/O register address pointer high byte IOAH1 R/W 00010EH DMA1 - Data counter low byte DCTL1 00010FH DMA1 - Data counter high byte DCTH1 R/W 000110H DMA2 - Buffer address pointer low byte BAPL2 R/W 000111H DMA2 - Buffer address pointer middle byte BAPM2 R/W 000112H DMA2 - Buffer address pointer high byte BAPH2 R/W 000113H DMA2 - DMA control register DMACS2 R/W 000114H DMA2 - I/O register address pointer low byte IOAL2 000115H DMA2 - I/O register address pointer high byte IOAH2 000116H DMA2 - Data counter low byte DCTL2 000117H DMA2 - Data counter high byte DCTH2 R/W 000118H DMA3 - Buffer address pointer low byte BAPL3 R/W 000119H DMA3 - Buffer address pointer middle byte BAPM3 R/W 00011AH DMA3 - Buffer address pointer high byte BAPH3 R/W 00011BH DMA3 - DMA control register DMACS3 R/W 00011CH DMA3 - I/O register address pointer low byte IOAL3 00011DH DMA3 - I/O register address pointer high byte IOAH3 00011EH DMA3 - Data counter low byte DCTL3 00011FH DMA3 - Data counter high byte DCTH3 000120H00017FH Reserved 000180H00037FH CPU - General Purpose registers (RAM access) 000380H DCT1 IOA2 R/W R/W R/W DCT2 IOA3 R/W R/W R/W DCT3 R/W R/W - GPR_RAM R/W DMA0 - Interrupt select DISEL0 R/W 000381H DMA1 - Interrupt select DISEL1 R/W 000382H DMA2 - Interrupt select DISEL2 R/W 000383H DMA3 - Interrupt select DISEL3 R/W 000384H00038FH Reserved 000390H DMA - Status register low byte DSRL 000391H DMA - Status register high byte DSRH FME-MB96350 rev 6 DSR R/W R/W 27 MB96350 Series I/O map MB96(F)35x (9 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access DSSR R/W 000392H DMA - Stop status register low byte DSSRL 000393H DMA - Stop status register high byte DSSRH 000394H DMA - Enable register low byte DERL 000395H DMA - Enable register high byte DERH 000396H00039FH Reserved 0003A0H Interrupt level register ILR 0003A1H Interrupt index register IDX 0003A2H Interrupt vector table base register Low TBRL 0003A3H Interrupt vector table base register High TBRH R/W 0003A4H Delayed Interrupt register DIRR R/W 0003A5H Non Maskable Interrupt register NMI R/W 0003A6H0003ABH Reserved 0003ACH EDSU communication interrupt selection Low EDSU2L 0003ADH EDSU communication interrupt selection High EDSU2H R/W 0003AEH ROM mirror control register ROMM R/W 0003AFH EDSU configuration register EDSU R/W 0003B0H Memory patch control/status register ch 0/1 0003B1H Memory patch control/status register ch 0/1 0003B2H Memory patch control/status register ch 2/3 0003B3H Memory patch control/status register ch 2/3 0003B4H Memory patch control/status register ch 4/5 0003B5H Memory patch control/status register ch 4/5 0003B6H Memory patch control/status register ch 6/7 0003B7H Memory patch control/status register ch 6/7 0003B8H Memory Patch function - Patch address 0 low PFAL0 R/W 0003B9H Memory Patch function - Patch address 0 middle PFAM0 R/W 0003BAH Memory Patch function - Patch address 0 high PFAH0 R/W 0003BBH Memory Patch function - Patch address 1 low PFAL1 R/W 0003BCH Memory Patch function - Patch address 1 middle PFAM1 R/W 28 R/W DER R/W R/W - ICR R/W R/W TBR R/W EDSU2 PFCS0 R/W R/W R/W PFCS1 R/W R/W PFCS2 R/W R/W PFCS3 R/W R/W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (10 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0003BDH Memory Patch function - Patch address 1 high PFAH1 R/W 0003BEH Memory Patch function - Patch address 2 low PFAL2 R/W 0003BFH Memory Patch function - Patch address 2 middle PFAM2 R/W 0003C0H Memory Patch function - Patch address 2 high PFAH2 R/W 0003C1H Memory Patch function - Patch address 3 low PFAL3 R/W 0003C2H Memory Patch function - Patch address 3 middle PFAM3 R/W 0003C3H Memory Patch function - Patch address 3 high PFAH3 R/W 0003C4H Memory Patch function - Patch address 4 low PFAL4 R/W 0003C5H Memory Patch function - Patch address 4 middle PFAM4 R/W 0003C6H Memory Patch function - Patch address 4 high PFAH4 R/W 0003C7H Memory Patch function - Patch address 5 low PFAL5 R/W 0003C8H Memory Patch function - Patch address 5 middle PFAM5 R/W 0003C9H Memory Patch function - Patch address 5 high PFAH5 R/W 0003CAH Memory Patch function - Patch address 6 low PFAL6 R/W 0003CBH Memory Patch function - Patch address 6 middle PFAM6 R/W 0003CCH Memory Patch function - Patch address 6 high PFAH6 R/W 0003CDH Memory Patch function - Patch address 7 low PFAL7 R/W 0003CEH Memory Patch function - Patch address 7 middle PFAM7 R/W 0003CFH Memory Patch function - Patch address 7 high PFAH7 R/W 0003D0H Memory Patch function - Patch data 0 Low PFDL0 0003D1H Memory Patch function - Patch data 0 High PFDH0 0003D2H Memory Patch function - Patch data 1 Low PFDL1 0003D3H Memory Patch function - Patch data 1 High PFDH1 0003D4H Memory Patch function - Patch data 2 Low PFDL2 0003D5H Memory Patch function - Patch data 2 High PFDH2 0003D6H Memory Patch function - Patch data 3 Low PFDL3 0003D7H Memory Patch function - Patch data 3 High PFDH3 0003D8H Memory Patch function - Patch data 4 Low PFDL4 0003D9H Memory Patch function - Patch data 4 High PFDH4 0003DAH Memory Patch function - Patch data 5 Low PFDL5 FME-MB96350 rev 6 PFD0 R/W R/W PFD1 R/W R/W PFD2 R/W R/W PFD3 R/W R/W PFD4 R/W R/W PFD5 R/W 29 MB96350 Series I/O map MB96(F)35x (11 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0003DBH Memory Patch function - Patch data 5 High PFDH5 0003DCH Memory Patch function - Patch data 6 Low PFDL6 0003DDH Memory Patch function - Patch data 6 High PFDH6 0003DEH Memory Patch function - Patch data 7 Low PFDL7 0003DFH Memory Patch function - Patch data 7 High PFDH7 0003E0H0003F0H Reserved 0003F1H Memory Control Status Register A MCSRA 0003F2H Memory Timing Configuration Register A Low MTCRAL 0003F3H Memory Timing Configuration Register A High MTCRAH 0003F4H0003F8H Reserved 0003F9H Flash Memory Write Control register 1 FMWC1 R/W 0003FAH Flash Memory Write Control register 2 FMWC2 R/W 0003FBH Flash Memory Write Control register 3 FMWC3 R/W 0003FCH Flash Memory Write Control register 4 FMWC4 R/W 0003FDH Flash Memory Write Control register 5 FMWC5 R/W 0003FEH0003FFH Reserved 000400H Standby Mode control register SMCR R/W 000401H Clock select register CKSR R/W 000402H Clock Stabilisation select register CKSSR R/W 000403H Clock monitor register CKMR R 000404H Clock Frequency control register Low CKFCRL 000405H Clock Frequency control register High CKFCRH 000406H PLL Control register Low PLLCRL 000407H PLL Control register High PLLCRH R/W 000408H RC clock timer control register RCTCR R/W 000409H Main clock timer control register MCTCR R/W 00040AH Sub clock timer control register SCTCR R/W 30 R/W PFD6 R/W R/W PFD7 R/W R/W R/W MTCRA R/W R/W - - CKFCR R/W R/W PLLCR R/W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (12 of 28) Address Register 00040BH Reset cause and clock status register with clear function 00040CH Reset configuration register 00040DH Abbreviation 8-bit access Abbreviation 16-bit access Access RCCSRC R RCR R/W Reset cause and clock status register RCCSR R 00040EH Watch dog timer configuration register WDTC R/W 00040FH Watch dog timer clear pattern register WDTCP W 000410H000414H Reserved 000415H Clock output activation register 000416H COAR R/W Clock output configuration register 0 COCR0 R/W 000417H Clock output configuration register 1 COCR1 R/W 000418H Clock Modulator control register CMCR R/W 000419H Reserved 00041AH Clock Modulator Parameter register Low CMPRL 00041BH Clock Modulator Parameter register High CMPRH 00041CH00042BH Reserved 00042CH Voltage Regulator Control register VRCR R/W 00042DH Clock Input and LVD Control Register CILCR R/W 00042EH00042FH Reserved 000430H I/O Port P00 - Data Direction Register DDR00 R/W 000431H I/O Port P01 - Data Direction Register DDR01 R/W 000432H I/O Port P02 - Data Direction Register DDR02 R/W 000433H I/O Port P03 - Data Direction Register DDR03 R/W 000434H I/O Port P04 - Data Direction Register DDR04 R/W 000435H I/O Port P05 - Data Direction Register DDR05 R/W 000436H I/O Port P06 - Data Direction Register DDR06 R/W 000437H000443H Reserved 000444H I/O Port P00 - Port Input Enable Register PIER00 R/W 000445H I/O Port P01 - Port Input Enable Register PIER01 R/W FME-MB96350 rev 6 CMPR R/W R/W - - - 31 MB96350 Series I/O map MB96(F)35x (13 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000446H I/O Port P02 - Port Input Enable Register PIER02 R/W 000447H I/O Port P03 - Port Input Enable Register PIER03 R/W 000448H I/O Port P04 - Port Input Enable Register PIER04 R/W 000449H I/O Port P05 - Port Input Enable Register PIER05 R/W 00044AH I/O Port P06 - Port Input Enable Register PIER06 R/W 00044BH000457H Reserved 000458H I/O Port P00 - Port Input Level Register PILR00 R/W 000459H I/O Port P01 - Port Input Level Register PILR01 R/W 00045AH I/O Port P02 - Port Input Level Register PILR02 R/W 00045BH I/O Port P03 - Port Input Level Register PILR03 R/W 00045CH I/O Port P04 - Port Input Level Register PILR04 R/W 00045DH I/O Port P05 - Port Input Level Register PILR05 R/W 00045EH I/O Port P06 - Port Input Level Register PILR06 R/W 00045FH00046BH Reserved 00046CH I/O Port P00 - Extended Port Input Level Register EPILR00 R/W 00046DH I/O Port P01 - Extended Port Input Level Register EPILR01 R/W 00046EH I/O Port P02 - Extended Port Input Level Register EPILR02 R/W 00046FH I/O Port P03 - Extended Port Input Level Register EPILR03 R/W 000470H I/O Port P04 - Extended Port Input Level Register EPILR04 R/W 000471H I/O Port P05 - Extended Port Input Level Register EPILR05 R/W 000472H I/O Port P06 - Extended Port Input Level Register EPILR06 R/W 000473H00047FH Reserved 000480H I/O Port P00 - Port Output Drive Register PODR00 R/W 000481H I/O Port P01 - Port Output Drive Register PODR01 R/W 000482H I/O Port P02 - Port Output Drive Register PODR02 R/W 000483H I/O Port P03 - Port Output Drive Register PODR03 R/W 000484H I/O Port P04 - Port Output Drive Register PODR04 R/W 000485H I/O Port P05 - Port Output Drive Register PODR05 R/W 32 - - - FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (14 of 28) Address Register Abbreviation 8-bit access Access 000486H I/O Port P06 - Port Output Drive Register 000487H0004A7H Reserved 0004A8H I/O Port P00 - Pull-Up resistor Control Register PUCR00 R/W 0004A9H I/O Port P01 - Pull-Up resistor Control Register PUCR01 R/W 0004AAH I/O Port P02 - Pull-Up resistor Control Register PUCR02 R/W 0004ABH I/O Port P03 - Pull-Up resistor Control Register PUCR03 R/W 0004ACH I/O Port P04 - Pull-Up resistor Control Register PUCR04 R/W 0004ADH I/O Port P05 - Pull-Up resistor Control Register PUCR05 R/W 0004AEH I/O Port P06 - Pull-Up resistor Control Register PUCR06 R/W 0004AFH0004BBH Reserved 0004BCH I/O Port P00 - External Pin State Register EPSR00 R 0004BDH I/O Port P01 - External Pin State Register EPSR01 R 0004BEH I/O Port P02 - External Pin State Register EPSR02 R 0004BFH I/O Port P03 - External Pin State Register EPSR03 R 0004C0H I/O Port P04 - External Pin State Register EPSR04 R 0004C1H I/O Port P05 - External Pin State Register EPSR05 R 0004C2H I/O Port P06 - External Pin State Register EPSR06 R 0004C3H0004CFH Reserved 0004D0H ADC analog input enable register 0 ADER0 R/W 0004D1H ADC analog input enable register 1 ADER1 R/W 0004D2H ADC analog input enable register 2 ADER2 R/W 0004D3H ADC analog input enable register 3 ADER3 R/W 0004D4H ADC analog input enable register 4 ADER4 R/W 0004D5H Reserved 0004D6H Peripheral Resource Relocation Register 0 PRRR0 R/W 0004D7H Peripheral Resource Relocation Register 1 PRRR1 R/W 0004D8H Peripheral Resource Relocation Register 2 PRRR2 R/W 0004D9H Peripheral Resource Relocation Register 3 PRRR3 R/W FME-MB96350 rev 6 PODR06 Abbreviation 16-bit access R/W - - - - 33 MB96350 Series I/O map MB96(F)35x (15 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0004DAH Peripheral Resource Relocation Register 4 PRRR4 R/W 0004DBH Peripheral Resource Relocation Register 5 PRRR5 R/W 0004DCH Peripheral Resource Relocation Register 6 PRRR6 R/W 0004DDH Peripheral Resource Relocation Register 7 PRRR7 R/W 0004DEH Peripheral Resource Relocation Register 8 PRRR8 R/W 0004DFH Peripheral Resource Relocation Register 9 PRRR9 R/W 0004E0H RTC - Sub Second Register L WTBRL0 0004E1H RTC - Sub Second Register M WTBRH0 R/W 0004E2H RTC - Sub-Second Register H WTBR1 R/W 0004E3H RTC - Second Register WTSR R/W 0004E4H RTC - Minutes WTMR R/W 0004E5H RTC - Hour WTHR R/W 0004E6H RTC - Timer Control Extended Register WTCER R/W 0004E7H RTC - Clock select register WTCKSR R/W 0004E8H RTC - Timer Control Register Low WTCRL 0004E9H RTC - Timer Control Register High WTCRH R/W 0004EAH CAL - Calibration unit Control register CUCR R/W 0004EBH Reserved 0004ECH CAL - Duration Timer Data Register Low CUTDL 0004EDH CAL - Duration Timer Data Register High CUTDH 0004EEH CAL - Calibration Timer Register 2 Low CUTR2L 0004EFH CAL - Calibration Timer Register 2 High CUTR2H 0004F0H CAL - Calibration Timer Register 1 Low CUTR1L 0004F1H CAL - Calibration Timer Register 1 High CUTR1H 0004F2H0004F9H Reserved 0004FAH RLT - Timer input select (for Cascading) 0004FBH0004FFH Reserved 000500H FRT2 - Data register of free-running timer 000501H FRT2 - Data register of free-running timer 34 WTBR0 WTCR R/W R/W CUTD R/W R/W CUTR2 R R CUTR1 R R - TMISR R/W TCDT2 R/W R/W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (16 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000502H FRT2 - Control status register of free-running timer Low TCCSL2 TCCS2 R/W 000503H FRT2 - Control status register of free-running timer High TCCSH2 000504H FRT3 - Data register of free-running timer 000505H FRT3 - Data register of free-running timer 000506H FRT3 - Control status register of free-running timer Low TCCSL3 000507H FRT3 - Control status register of free-running timer High TCCSH3 000508H000513H Reserved 000514H ICU8/ICU9 - Control Status Register ICS89 R/W 000515H ICU8/ICU9 - Edge Register ICE89 R/W 000516H ICU8 - Capture Register Low IPCPL8 000517H ICU8 - Capture Register High IPCPH8 000518H ICU9 - Capture Register Low IPCPL9 000519H ICU9 - Capture Register High IPCPH9 R 00051AH ICU10/ICU11 - Control Status Register ICS1011 R/W 00051BH ICU10/ICU11 - Edge Register ICE1011 R/W 00051CH ICU10 - Capture Register Low IPCPL10 00051DH ICU10 - Capture Register High IPCPH10 00051EH ICU11 - Capture Register Low IPCPL11 00051FH ICU11 - Capture Register High IPCPH11 000520H00053DH Reserved 00053EH USART7 - Serial Mode Register SMR7 R/W 00053FH USART7 - Serial Control Register SCR7 R/W 000540H USART7 - Serial TX Register TDR7 W 000540H USART7 - Serial RX Register RDR7 R 000541H USART7 - Serial Status Register SSR7 R/W 000542H USART7 - Ext. Control/Com. Register ECCR7 R/W FME-MB96350 rev 6 R/W TCDT3 R/W R/W TCCS3 R/W R/W - IPCP8 R R IPCP9 IPCP10 R R R IPCP11 R R - 35 MB96350 Series I/O map MB96(F)35x (17 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 000543H USART7 - Ext. Status Com. Register ESCR7 000544H USART7 - Baud Rate Generator Register Low BGRL7 000545H USART7 - Baud Rate Generator Register High BGRH7 R/W 000546H USART7 - Extended Serial Interrupt Register ESIR7 R/W 000547H Reserved 000548H USART8 - Serial Mode Register SMR8 R/W 000549H USART8 - Serial Control Register SCR8 R/W 00054AH USART8 - Serial TX Register TDR8 W 00054AH USART8 - Serial RX Register RDR8 R 00054BH USART8 - Serial Status Register SSR8 R/W 00054CH USART8 - Ext. Control/Com. Register ECCR8 R/W 00054DH USART8 - Ext. Status Com. Register ESCR8 R/W 00054EH USART8 - Baud Rate Generator Register Low BGRL8 00054FH USART8 - Baud Rate Generator Register High BGRH8 R/W 000550H USART8 - Extended Serial Interrupt Register ESIR8 R/W 000551H000563H Reserved 000564H PPG6 - Timer register 000565H PPG6 - Timer register 000566H PPG6 - Period setting register 000567H PPG6 - Period setting register 000568H PPG6 - Duty cycle register 000569H PPG6 - Duty cycle register 00056AH PPG6 - Control status register Low PCNL6 00056BH PPG6 - Control status register High PCNH6 00056CH PPG7 - Timer register 00056DH PPG7 - Timer register 00056EH PPG7 - Period setting register 00056FH PPG7 - Period setting register 000570H PPG7 - Duty cycle register 36 R/W BGR7 R/W - BGR8 R/W PTMR6 R R PCSR6 W W PDUT6 W W PCN6 R/W R/W PTMR7 R R PCSR7 W W PDUT7 W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (18 of 28) Address Register Abbreviation 8-bit access 000571H PPG7 - Duty cycle register 000572H PPG7 - Control status register Low PCNL7 000573H PPG7 - Control status register High PCNH7 000574H PPG11-PPG8 - General Control register 1 Low GCN1L2 000575H PPG11-PPG8 - General Control register 1 High GCN1H2 000576H PPG11-PPG8 - General Control register 2 Low GCN2L2 000577H PPG11-PPG8 - General Control register 2 High GCN2H2 000578H PPG8 - Timer register 000579H PPG8 - Timer register 00057AH PPG8 - Period setting register 00057BH PPG8 - Period setting register 00057CH PPG8 - Duty cycle register 00057DH PPG8 - Duty cycle register 00057EH PPG8 - Control status register Low PCNL8 00057FH PPG8 - Control status register High PCNH8 000580H PPG9 - Timer register 000581H PPG9 - Timer register 000582H PPG9 - Period setting register 000583H PPG9 - Period setting register 000584H PPG9 - Duty cycle register 000585H PPG9 - Duty cycle register 000586H PPG9 - Control status register Low PCNL9 000587H PPG9 - Control status register High PCNH9 000588H PPG10 - Timer register 000589H PPG10 - Timer register 00058AH PPG10 - Period setting register 00058BH PPG10 - Period setting register 00058CH PPG10 - Duty cycle register 00058DH PPG10 - Duty cycle register 00058EH PPG10 - Control status register Low FME-MB96350 rev 6 Abbreviation 16-bit access Access W PCN7 R/W R/W GCN12 R/W R/W GCN22 R/W R/W PTMR8 R R PCSR8 W W PDUT8 W W PCN8 R/W R/W PTMR9 R R PCSR9 W W PDUT9 W W PCN9 R/W R/W PTMR10 R R PCSR10 W W PDUT10 W W PCNL10 PCN10 R/W 37 MB96350 Series I/O map MB96(F)35x (19 of 28) Address Register Abbreviation 8-bit access 00058FH PPG10 - Control status register High 000590H PPG11 - Timer register 000591H PPG11 - Timer register 000592H PPG11 - Period setting register 000593H PPG11 - Period setting register 000594H PPG11 - Duty cycle register 000595H PPG11 - Duty cycle register 000596H PPG11 - Control status register Low PCNL11 000597H PPG11 - Control status register High PCNH11 000598H PPG15-PPG12 - General Control register 1 Low GCN1L3 000599H PPG15-PPG12 - General Control register 1 High GCN1H3 00059AH PPG15-PPG12 - General Control register 2 Low GCN2L3 00059BH PPG15-PPG12 - General Control register 2 High GCN2H3 00059CH PPG12 - Timer register 00059DH PPG12 - Timer register 00059EH PPG12 - Period setting register 00059FH PPG12 - Period setting register 0005A0H PPG12 - Duty cycle register 0005A1H PPG12 - Duty cycle register 0005A2H PPG12 - Control status register Low PCNL12 0005A3H PPG12 - Control status register High PCNH12 0005A4H PPG13 - Timer register 0005A5H PPG13 - Timer register 0005A6H PPG13 - Period setting register 0005A7H PPG13 - Period setting register 0005A8H PPG13 - Duty cycle register 0005A9H PPG13 - Duty cycle register 0005AAH PPG13 - Control status register Low PCNL13 0005ABH PPG13 - Control status register High PCNH13 0005ACH PPG14 - Timer register 38 Abbreviation 16-bit access PCNH10 Access R/W PTMR11 R R PCSR11 W W PDUT11 W W PCN11 R/W R/W GCN13 R/W R/W GCN23 R/W R/W PTMR12 R R PCSR12 W W PDUT12 W W PCN12 R/W R/W PTMR13 R R PCSR13 W W PDUT13 W W PCN13 R/W R/W PTMR14 R FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (20 of 28) Address Register Abbreviation 8-bit access 0005ADH PPG14 - Timer register 0005AEH PPG14 - Period setting register 0005AFH PPG14 - Period setting register 0005B0H PPG14 - Duty cycle register 0005B1H PPG14 - Duty cycle register 0005B2H PPG14 - Control status register Low PCNL14 0005B3H PPG14 - Control status register High PCNH14 0005B4H PPG15 - Timer register 0005B5H PPG15 - Timer register 0005B6H PPG15 - Period setting register 0005B7H PPG15 - Period setting register 0005B8H PPG15 - Duty cycle register 0005B9H PPG15 - Duty cycle register 0005BAH PPG15 - Control status register Low PCNL15 0005BBH PPG15 - Control status register High PCNH15 0005BCH PPG19-PPG16 - General Control register 1 Low GCN1L4 0005BDH PPG19-PPG16 - General Control register 1 High GCN1H4 0005BEH PPG19-PPG16 - General Control register 2 Low GCN2L4 0005BFH PPG19-PPG16 - General Control register 2 High GCN2H4 0005C0H PPG16 - Timer register 0005C1H PPG16 - Timer register 0005C2H PPG16 - Period setting register 0005C3H PPG16 - Period setting register 0005C4H PPG16 - Duty cycle register 0005C5H PPG16 - Duty cycle register 0005C6H PPG16 - Control status register Low PCNL16 0005C7H PPG16 - Control status register High PCNH16 0005C8H PPG17 - Timer register 0005C9H PPG17 - Timer register 0005CAH PPG17 - Period setting register FME-MB96350 rev 6 Abbreviation 16-bit access Access R PCSR14 W W PDUT14 W W PCN14 R/W R/W PTMR15 R R PCSR15 W W PDUT15 W W PCN15 R/W R/W GCN14 R/W R/W GCN24 R/W R/W PTMR16 R R PCSR16 W W PDUT16 W W PCN16 R/W R/W PTMR17 R R PCSR17 W 39 MB96350 Series I/O map MB96(F)35x (21 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access 0005CBH PPG17 - Period setting register 0005CCH PPG17 - Duty cycle register 0005CDH PPG17 - Duty cycle register 0005CEH PPG17 - Control status register Low PCNL17 0005CFH PPG17 - Control status register High PCNH17 0005D0H PPG18 - Timer register 0005D1H PPG18 - Timer register 0005D2H PPG18 - Period setting register 0005D3H PPG18 - Period setting register 0005D4H PPG18 - Duty cycle register 0005D5H PPG18 - Duty cycle register 0005D6H PPG18 - Control status register Low PCNL18 0005D7H PPG18 - Control status register High PCNH18 0005D8H PPG19 - Timer register 0005D9H PPG19 - Timer register 0005DAH PPG19 - Period setting register 0005DBH PPG19 - Period setting register 0005DCH PPG19 - Duty cycle register 0005DDH PPG19 - Duty cycle register 0005DEH PPG19 - Control status register Low PCNL19 0005DFH PPG19 - Control status register High PCNH19 0005E0H00065FH Reserved 000660H Peripheral Resource Relocation Register 10 PRRR10 R/W 000661H Peripheral Resource Relocation Register 11 PRRR11 R/W 000662H Peripheral Resource Relocation Register 12 PRRR12 R/W 000663H Peripheral Resource Relocation Register 13 PRRR13 W 000664H0006DFH Reserved 0006E0H External Bus - Area configuration register 0 Low EACL0 0006E1H External Bus - Area configuration register 0 High EACH0 40 W PDUT17 W W PCN17 R/W R/W PTMR18 R R PCSR18 W W PDUT18 W W PCN18 R/W R/W PTMR19 R R PCSR19 W W PDUT19 W W PCN19 R/W R/W - EAC0 R/W R/W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (22 of 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access EAC1 R/W 0006E2H External Bus - Area configuration register 1 Low EACL1 0006E3H External Bus - Area configuration register 1 High EACH1 0006E4H External Bus - Area configuration register 2 Low EACL2 0006E5H External Bus - Area configuration register 2 High EACH2 0006E6H External Bus - Area configuration register 3 Low EACL3 0006E7H External Bus - Area configuration register 3 High EACH3 0006E8H External Bus - Area configuration register 4 Low EACL4 0006E9H External Bus - Area configuration register 4 High EACH4 0006EAH External Bus - Area configuration register 5 Low EACL5 0006EBH External Bus - Area configuration register 5 High EACH5 R/W 0006ECH External Bus - Area select register 2 EAS2 R/W 0006EDH External Bus - Area select register 3 EAS3 R/W 0006EEH External Bus - Area select register 4 EAS4 R/W 0006EFH External Bus - Area select register 5 EAS5 R/W 0006F0H External Bus - Mode register EBM R/W 0006F1H External Bus - Clock and Function register EBCF R/W 0006F2H External Bus - Address output enable register 0 EBAE0 R/W 0006F3H External Bus - Address output enable register 1 EBAE1 R/W 0006F4H External Bus - Address output enable register 2 EBAE2 R/W 0006F5H External Bus - Control signal register EBCS R/W 0006F6H0007FFH Reserved 000800H CAN1 - Control register Low CTRLRL1 000801H CAN1 - Control register High (reserved) CTRLRH1 000802H CAN1 - Status register Low STATRL1 000803H CAN1 - Status register High (reserved) STATRH1 000804H CAN1 - Error Counter Low (Transmit) ERRCNTL1 000805H CAN1 - Error Counter High (Receive) ERRCNTH1 000806H CAN1 - Bit Timing Register Low BTRL1 000807H CAN1 - Bit Timing Register High BTRH1 FME-MB96350 rev 6 R/W EAC2 R/W R/W EAC3 R/W R/W EAC4 R/W R/W EAC5 R/W CTRLR1 R/W R STATR1 R/W R ERRCNT1 R R BTR1 R/W R/W 41 MB96350 Series I/O map MB96(F)35x (23 of 28) Abbreviation 8-bit access Abbreviation 16-bit access Access CAN1 - Interrupt Register Low INTRL1 INTR1 R 000809H CAN1 - Interrupt Register High INTRH1 00080AH CAN1 - Test Register Low TESTRL1 00080BH CAN1 - Test Register High (reserved) TESTRH1 00080CH CAN1 - BRP Extension register Low BRPERL1 00080DH CAN1 - BRP Extension register High (reserved) BRPERH1 00080EH00080FH Reserved 000810H CAN1 - IF1 Command request register Low IF1CREQL1 000811H CAN1 - IF1 Command request register High IF1CREQH1 000812H CAN1 - IF1 Command Mask register Low IF1CMSKL1 000813H CAN1 - IF1 Command Mask register High (reserved) IF1CMSKH1 000814H CAN1 - IF1 Mask 1 Register Low IF1MSK1L1 000815H CAN1 - IF1 Mask 1 Register High IF1MSK1H1 000816H CAN1 - IF1 Mask 2 Register Low IF1MSK2L1 000817H CAN1 - IF1 Mask 2 Register High IF1MSK2H1 000818H CAN1 - IF1 Arbitration 1 Register Low IF1ARB1L1 000819H CAN1 - IF1 Arbitration 1 Register High IF1ARB1H1 00081AH CAN1 - IF1 Arbitration 2 Register Low IF1ARB2L1 00081BH CAN1 - IF1 Arbitration 2 Register High IF1ARB2H1 00081CH CAN1 - IF1 Message Control Register Low IF1MCTRL1 00081DH CAN1 - IF1 Message Control Register High IF1MCTRH1 00081EH CAN1 - IF1 Data A1 Low IF1DTA1L1 00081FH CAN1 - IF1 Data A1 High IF1DTA1H1 000820H CAN1 - IF1 Data A2 Low IF1DTA2L1 000821H CAN1 - IF1 Data A2 High IF1DTA2H1 000822H CAN1 - IF1 Data B1 Low IF1DTB1L1 000823H CAN1 - IF1 Data B1 High IF1DTB1H1 000824H CAN1 - IF1 Data B2 Low IF1DTB2L1 000825H CAN1 - IF1 Data B2 High IF1DTB2H1 Address Register 000808H 42 R TESTR1 R/W R BRPER1 R/W R - IF1CREQ1 R/W R/W IF1CMSK1 R/W R IF1MSK11 R/W R/W IF1MSK21 R/W R/W IF1ARB11 R/W R/W IF1ARB21 R/W R/W IF1MCTR1 R/W R/W IF1DTA11 R/W R/W IF1DTA21 R/W R/W IF1DTB11 R/W R/W IF1DTB21 R/W R/W FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (24 of 28) Address Register Abbreviation 8-bit access 000826H00083FH Reserved 000840H CAN1 - IF2 Command request register Low IF2CREQL1 000841H CAN1 - IF2 Command request register High IF2CREQH1 000842H CAN1 - IF2 Command Mask register Low IF2CMSKL1 000843H CAN1 - IF2 Command Mask register High (reserved) IF2CMSKH1 000844H CAN1 - IF2 Mask 1 Register Low IF2MSK1L1 000845H CAN1 - IF2 Mask 1 Register High IF2MSK1H1 000846H CAN1 - IF2 Mask 2 Register Low IF2MSK2L1 000847H CAN1 - IF2 Mask 2 Register High IF2MSK2H1 000848H CAN1 - IF2 Arbitration 1 Register Low IF2ARB1L1 000849H CAN1 - IF2 Arbitration 1 Register High IF2ARB1H1 00084AH CAN1 - IF2 Arbitration 2 Register Low IF2ARB2L1 00084BH CAN1 - IF2 Arbitration 2 Register High IF2ARB2H1 00084CH CAN1 - IF2 Message Control Register Low IF2MCTRL1 00084DH CAN1 - IF2 Message Control Register High IF2MCTRH1 00084EH CAN1 - IF2 Data A1 Low IF2DTA1L1 00084FH CAN1 - IF2 Data A1 High IF2DTA1H1 000850H CAN1 - IF2 Data A2 Low IF2DTA2L1 000851H CAN1 - IF2 Data A2 High IF2DTA2H1 000852H CAN1 - IF2 Data B1 Low IF2DTB1L1 000853H CAN1 - IF2 Data B1 High IF2DTB1H1 000854H CAN1 - IF2 Data B2 Low IF2DTB2L1 000855H CAN1 - IF2 Data B2 High IF2DTB2H1 000856H00087FH Reserved 000880H CAN1 - Transmission Request 1 Register Low TREQR1L1 000881H CAN1 - Transmission Request 1 Register High TREQR1H1 000882H CAN1 - Transmission Request 2 Register Low TREQR2L1 000883H CAN1 - Transmission Request 2 Register High TREQR2H1 FME-MB96350 rev 6 Abbreviation 16-bit access Access - IF2CREQ1 R/W R/W IF2CMSK1 R/W R IF2MSK11 R/W R/W IF2MSK21 R/W R/W IF2ARB11 R/W R/W IF2ARB21 R/W R/W IF2MCTR1 R/W R/W IF2DTA11 R/W R/W IF2DTA21 R/W R/W IF2DTB11 R/W R/W IF2DTB21 R/W R/W - TREQR11 R R TREQR21 R R 43 MB96350 Series I/O map MB96(F)35x (25 of 28) Address Register Abbreviation 8-bit access 000884H00088FH Reserved 000890H CAN1 - New Data 1 Register Low NEWDT1L1 000891H CAN1 - New Data 1 Register High NEWDT1H1 000892H CAN1 - New Data 2 Register Low NEWDT2L1 000893H CAN1 - New Data 2 Register High NEWDT2H1 000894H00089FH Reserved 0008A0H CAN1 - Interrupt Pending 1 Register Low INTPND1L1 0008A1H CAN1 - Interrupt Pending 1 Register High INTPND1H1 0008A2H CAN1 - Interrupt Pending 2 Register Low INTPND2L1 0008A3H CAN1 - Interrupt Pending 2 Register High INTPND2H1 0008A4H0008AFH Reserved 0008B0H CAN1 - Message Valid 1 Register Low MSGVAL1L1 0008B1H CAN1 - Message Valid 1 Register High MSGVAL1H1 0008B2H CAN1 - Message Valid 2 Register Low MSGVAL2L1 0008B3H CAN1 - Message Valid 2 Register High MSGVAL2H1 0008B4H0008CDH Reserved 0008CEH CAN1 - Output enable register 0008CFH0008FFH Reserved 000900H CAN2 - Control register Low CTRLRL2 000901H CAN2 - Control register High (reserved) CTRLRH2 000902H CAN2 - Status register Low STATRL2 000903H CAN2 - Status register High (reserved) STATRH2 000904H CAN2 - Error Counter Low (Transmit) ERRCNTL2 000905H CAN2 - Error Counter High (Receive) ERRCNTH2 000906H CAN2 - Bit Timing Register Low BTRL2 000907H CAN2 - Bit Timing Register High BTRH2 000908H CAN2 - Interrupt Register Low INTRL2 44 Abbreviation 16-bit access Access - NEWDT11 R R NEWDT21 R R - INTPND11 R R INTPND21 R R - MSGVAL11 R R MSGVAL21 R R - COER1 R/W CTRLR2 R/W R STATR2 R/W R ERRCNT2 R R BTR2 R/W R/W INTR2 R FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (26 of 28) Address Register Abbreviation 8-bit access 000909H CAN2 - Interrupt Register High 00090AH CAN2 - Test Register Low TESTRL2 00090BH CAN2 - Test Register High (reserved) TESTRH2 00090CH CAN2 - BRP Extension register Low BRPERL2 00090DH CAN2 - BRP Extension register High (reserved) BRPERH2 00090EH00090FH Reserved 000910H CAN2 - IF1 Command request register Low IF1CREQL2 000911H CAN2 - IF1 Command request register High IF1CREQH2 000912H CAN2 - IF1 Command Mask register Low IF1CMSKL2 000913H CAN2 - IF1 Command Mask register High (reserved) IF1CMSKH2 000914H CAN2 - IF1 Mask 1 Register Low IF1MSK1L2 000915H CAN2 - IF1 Mask 1 Register High IF1MSK1H2 000916H CAN2 - IF1 Mask 2 Register Low IF1MSK2L2 000917H CAN2 - IF1 Mask 2 Register High IF1MSK2H2 000918H CAN2 - IF1 Arbitration 1 Register Low IF1ARB1L2 000919H CAN2 - IF1 Arbitration 1 Register High IF1ARB1H2 00091AH CAN2 - IF1 Arbitration 2 Register Low IF1ARB2L2 00091BH CAN2 - IF1 Arbitration 2 Register High IF1ARB2H2 00091CH CAN2 - IF1 Message Control Register Low IF1MCTRL2 00091DH CAN2 - IF1 Message Control Register High IF1MCTRH2 00091EH CAN2 - IF1 Data A1 Low IF1DTA1L2 00091FH CAN2 - IF1 Data A1 High IF1DTA1H2 000920H CAN2 - IF1 Data A2 Low IF1DTA2L2 000921H CAN2 - IF1 Data A2 High IF1DTA2H2 000922H CAN2 - IF1 Data B1 Low IF1DTB1L2 000923H CAN2 - IF1 Data B1 High IF1DTB1H2 000924H CAN2 - IF1 Data B2 Low IF1DTB2L2 000925H CAN2 - IF1 Data B2 High IF1DTB2H2 FME-MB96350 rev 6 Abbreviation 16-bit access INTRH2 Access R TESTR2 R/W R BRPER2 R/W R - IF1CREQ2 R/W R/W IF1CMSK2 R/W R IF1MSK12 R/W R/W IF1MSK22 R/W R/W IF1ARB12 R/W R/W IF1ARB22 R/W R/W IF1MCTR2 R/W R/W IF1DTA12 R/W R/W IF1DTA22 R/W R/W IF1DTB12 R/W R/W IF1DTB22 R/W R/W 45 MB96350 Series I/O map MB96(F)35x (27 of 28) Address Register Abbreviation 8-bit access 000926H00093FH Reserved 000940H CAN2 - IF2 Command request register Low IF2CREQL2 000941H CAN2 - IF2 Command request register High IF2CREQH2 000942H CAN2 - IF2 Command Mask register Low IF2CMSKL2 000943H CAN2 - IF2 Command Mask register High (reserved) IF2CMSKH2 000944H CAN2 - IF2 Mask 1 Register Low IF2MSK1L2 000945H CAN2 - IF2 Mask 1 Register High IF2MSK1H2 000946H CAN2 - IF2 Mask 2 Register Low IF2MSK2L2 000947H CAN2 - IF2 Mask 2 Register High IF2MSK2H2 000948H CAN2 - IF2 Arbitration 1 Register Low IF2ARB1L2 000949H CAN2 - IF2 Arbitration 1 Register High IF2ARB1H2 00094AH CAN2 - IF2 Arbitration 2 Register Low IF2ARB2L2 00094BH CAN2 - IF2 Arbitration 2 Register High IF2ARB2H2 00094CH CAN2 - IF2 Message Control Register Low IF2MCTRL2 00094DH CAN2 - IF2 Message Control Register High IF2MCTRH2 00094EH CAN2 - IF2 Data A1 Low IF2DTA1L2 00094FH CAN2 - IF2 Data A1 High IF2DTA1H2 000950H CAN2 - IF2 Data A2 Low IF2DTA2L2 000951H CAN2 - IF2 Data A2 High IF2DTA2H2 000952H CAN2 - IF2 Data B1 Low IF2DTB1L2 000953H CAN2 - IF2 Data B1 High IF2DTB1H2 000954H CAN2 - IF2 Data B2 Low IF2DTB2L2 000955H CAN2 - IF2 Data B2 High IF2DTB2H2 000956H00097FH Reserved 000980H CAN2 - Transmission Request 1 Register Low TREQR1L2 000981H CAN2 - Transmission Request 1 Register High TREQR1H2 000982H CAN2 - Transmission Request 2 Register Low TREQR2L2 000983H CAN2 - Transmission Request 2 Register High TREQR2H2 46 Abbreviation 16-bit access Access - IF2CREQ2 R/W R/W IF2CMSK2 R/W R IF2MSK12 R/W R/W IF2MSK22 R/W R/W IF2ARB12 R/W R/W IF2ARB22 R/W R/W IF2MCTR2 R/W R/W IF2DTA12 R/W R/W IF2DTA22 R/W R/W IF2DTB12 R/W R/W IF2DTB22 R/W R/W - TREQR12 R R TREQR22 R R FME-MB96350 rev 6 MB96350 Series I/O map MB96(F)35x (28 of 28) Address Register Abbreviation 8-bit access 000984H00098FH Reserved 000990H CAN2 - New Data 1 Register Low NEWDT1L2 000991H CAN2 - New Data 1 Register High NEWDT1H2 000992H CAN2 - New Data 2 Register Low NEWDT2L2 000993H CAN2 - New Data 2 Register High NEWDT2H2 000994H00099FH Reserved 0009A0H CAN2 - Interrupt Pending 1 Register Low INTPND1L2 0009A1H CAN2 - Interrupt Pending 1 Register High INTPND1H2 0009A2H CAN2 - Interrupt Pending 2 Register Low INTPND2L2 0009A3H CAN2 - Interrupt Pending 2 Register High INTPND2H2 0009A4H0009AFH Reserved 0009B0H CAN2 - Message Valid 1 Register Low MSGVAL1L2 0009B1H CAN2 - Message Valid 1 Register High MSGVAL1H2 0009B2H CAN2 - Message Valid 2 Register Low MSGVAL2L2 0009B3H CAN2 - Message Valid 2 Register High MSGVAL2H2 0009B4H0009CDH Reserved 0009CEH CAN2 - Output enable register 0009CFH000BFFH Reserved Abbreviation 16-bit access Access - NEWDT12 R R NEWDT22 R R - INTPND12 R R INTPND22 R R - MSGVAL12 R R MSGVAL22 R R - COER2 R/W - Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading ‘X’. Registers of resources which are described in this table, but which are not supported by the device, should also be handled as “Reserved”. FME-MB96350 rev 6 47 MB96350 Series ■ INTERRUPT VECTOR TABLE Interrupt vector table MB96(F)35x (1 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 48 Description 0 3FCH CALLV0 No - 1 3F8H CALLV1 No - 2 3F4H CALLV2 No - 3 3F0H CALLV3 No - 4 3ECH CALLV4 No - 5 3E8H CALLV5 No - 6 3E4H CALLV6 No - 7 3E0H CALLV7 No - 8 3DCH RESET No - 9 3D8H INT9 No - 10 3D4H EXCEPTION No - 11 3D0H NMI No - 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH PLL_UNLOCK No 16 Reserved 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H 23 3A0H EXTINT7 Yes 23 External Interrupt 7 24 39CH EXTINT8 Yes 24 External Interrupt 8 25 398H EXTINT9 Yes 25 External Interrupt 9 26 394H EXTINT10 Yes 26 External Interrupt 10 27 390H EXTINT11 Yes 27 External Interrupt 11 28 38CH EXTINT12 Yes 28 External Interrupt 12 29 388H EXTINT13 Yes 29 External Interrupt 13 30 384H EXTINT14 Yes 30 External Interrupt 14 31 380H EXTINT15 Yes 31 External Interrupt 15 32 37CH CAN1 No 32 CAN Controller 1 (only MB96F356Y/R) Non-Maskable Interrupt Reserved Reserved FME-MB96350 rev 6 MB96350 Series Interrupt vector table MB96(F)35x (2 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram Description 33 378H CAN2 No 33 CAN Controller 2 (only MB96F356Y/R and MB96F353R/F355R) 34 374H PPG0 Yes 34 Programmable Pulse Generator 0 35 370H PPG1 Yes 35 Programmable Pulse Generator 1 36 36CH PPG2 Yes 36 Programmable Pulse Generator 2 37 368H PPG3 Yes 37 Programmable Pulse Generator 3 38 364H PPG4 Yes 38 Programmable Pulse Generator 4 39 360 PPG5 Yes 39 Programmable Pulse Generator 5 40 35CH PPG6 Yes 40 Programmable Pulse Generator 6 41 358H PPG7 Yes 41 Programmable Pulse Generator 7 42 354H PPG8 Yes 42 Programmable Pulse Generator 8 43 350H PPG9 Yes 43 Programmable Pulse Generator 9 44 34CH PPG10 Yes 44 Programmable Pulse Generator 10 45 348H PPG11 Yes 45 Programmable Pulse Generator 11 46 344H PPG12 Yes 46 Programmable Pulse Generator 12 47 340H PPG13 Yes 47 Programmable Pulse Generator 13 48 33CH PPG14 Yes 48 Programmable Pulse Generator 14 49 338H PPG15 Yes 49 Programmable Pulse Generator 15 50 334H PPG16 Yes 50 Programmable Pulse Generator 16 51 330H PPG17 Yes 51 Programmable Pulse Generator 17 52 32CH PPG18 Yes 52 Programmable Pulse Generator 18 53 328H PPG19 Yes 53 Programmable Pulse Generator 19 54 324H RLT0 Yes 54 Reload Timer 0 55 320H RLT1 Yes 55 Reload Timer 1 56 31CH RLT2 Yes 56 Reload Timer 2 57 318H RLT3 Yes 57 Reload Timer 3 58 314H PPGRLT Yes 58 Reload Timer 6 - dedicated for PPG 59 310H ICU0 Yes 59 Input Capture Unit 0 60 30CH ICU1 Yes 60 Input Capture Unit 1 61 308H Reserved 62 304H Reserved 63 300H ICU4 Yes 63 Input Capture Unit 4 64 2FCH ICU5 Yes 64 Input Capture Unit 5 65 2F8H ICU6 Yes 65 Input Capture Unit 6 66 2F4H ICU7 Yes 66 Input Capture Unit 7 FME-MB96350 rev 6 49 MB96350 Series Interrupt vector table MB96(F)35x (3 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 50 Description 67 2F0H Reserved 68 2ECH ICU9 Yes 68 Input Capture Unit 9 69 2E8H ICU10 Yes 69 Input Capture Unit 10 70 2E4H 71 2E0H OCU4 Yes 71 Output Compare Unit 4 72 2DCH OCU5 Yes 72 Output Compare Unit 5 73 2D8H OCU6 Yes 73 Output Compare Unit 6 74 2D4H OCU7 Yes 74 Output Compare Unit 7 75 2D0H Reserved 76 2CCH Reserved 77 2C8H FRT0 Yes 77 Free Running Timer 0 78 2C4H FRT1 Yes 78 Free Running Timer 1 79 2C0H FRT2 Yes 79 Free Running Timer 2 80 2BCH FRT3 Yes 80 Free Running Timer 3 81 2B8H RTC0 No 81 Real Timer Clock 82 2B4H CAL0 No 82 Clock Calibration Unit 83 2B0H IIC0 Yes 83 I2C interface 84 2ACH ADC0 Yes 84 A/D Converter 85 2A8H LINR2 Yes 85 LIN USART 2 RX 86 2A4H LINT2 Yes 86 LIN USART 2 TX 87 2A0H LINR3 Yes 87 LIN USART 3 RX 88 29CH LINT3 Yes 88 LIN USART 3 TX 89 298H LINR7 Yes 89 LIN USART 7 RX 90 294H LINT7 Yes 90 LIN USART 7 TX 91 290H LINR8 Yes 91 LIN USART 8 RX 92 28CH LINT8 Yes 92 LIN USART 8 TX 93 288H FLASH_A No 93 Flash memory A (only Flash devices) Reserved FME-MB96350 rev 6 MB96350 Series ■ HANDLING DEVICES Special care is required for the following when handling the device: • • • • • • • • • • • • Latch-up prevention Unused pins handling External clock usage Unused sub clock signal Notes on PLL clock mode operation Power supply pins (VCC/VSS) Crystal oscillator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on energization Stabilization of power supply voltage Serial communication 1. Latch-up prevention CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC pins and VSS pins. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. 2. Unused pins handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 kΩ. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. External clock usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 1. Single phase external clock • When using a single phase external clock, X0 pin must be driven and X1 pin left open. X0 X1 FME-MB96350 rev 6 51 MB96350 Series 2. Opposite phase external clock • When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. X0 X1 4. Unused sub clock signal If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. 5. Notes on PLL clock mode operation If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 6. Power supply pins (VCC/VSS) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. VCC and VSS must be connected to the device from the power supply with lowest possible impedance. As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between VCC and VSS as close as possible to VCC and VSS pins. 7. Crystal oscillator and ceramic resonator circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 8. Turn on sequence of power supply to A/D converter and analog inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. Pin handling when not using the A/D converter It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50µs from 0.2 V to 2.7 V. 52 FME-MB96350 rev 6 MB96350 Series 11. Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching. 12. Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. FME-MB96350 rev 6 53 MB96350 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Min Max Unit Remarks VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC *1 AVRH, AVRL VSS - 0.3 VSS + 6.0 V AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS Input voltage VI VSS - 0.3 VSS + 6.0 V VI ≤ VCC + 0.3V Output voltage VO VSS - 0.3 VSS + 6.0 V VO ≤ VCC + 0.3V *2 Power supply voltage AD Converter voltage references *2 ICLAMP -4.0 +4.0 mA Applicable to general purpose I/O pins *3 Σ|ICLAMP| - 40 mA Applicable to general purpose I/O pins *3 IOL1 - 15 mA Normal outputs with driving strength set to 5mA “L” level average output current IOLAV1 - 5 mA Normal outputs with driving strength set to 5mA “L” level maximum overall output current ΣIOL1 - 100 mA Normal outputs ΣIOLAV1 - 50 mA Normal outputs IOH1 - -15 mA ”H” level average output current IOHAV1 - -5 mA Normal outputs with driving strength set to 5mA ”H” level maximum overall output current ΣIOH1 - -100 mA Normal outputs ”H” level average overall output current ΣIOHAV1 - -50 mA Normal outputs - 320*5 mW TA=105oC - 640*5 mW TA=85oC - 800*5 mW TA=75oC - 400*5 mW TA=125oC, no Flash program/ erase *6 - 560*5 mW TA=115oC, no Flash program/ erase *6 0 +70 -40 +105 -40 +125 -55 +150 Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average overall output current ”H” level maximum output current Permitted Power dissipation (Flash devices) *4 Operating ambient temperature Storage temperature PD TA TSTG Normal outputs with driving strength set to 5mA MB96V300B o C *6 o C *1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on. 54 FME-MB96350 rev 6 MB96350 Series *2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of standard ports depend on VCC. *3: • Applicable to all general purpose I/O pins (Pnn_m) • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). • Sample recommended circuits: Protective Diode VCC Limiting resistance P-ch +B input (0V to 16V) N-ch R *4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator. IA is the analog current consumption into AVCC. *5: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *6: Please contact Fujitsu for reliability limitations when using under these conditions. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. FME-MB96350 rev 6 55 MB96350 Series 2. Recommended Operating Conditions Parameter Symbol Value Min Typ Max Unit Power supply voltage VCC 3.0 - 5.5 V Smoothing capacitor at C pin CS 3.5 4.7 - 10 15 µF Remarks Use a low inductance capacitor (for example X7R ceramic capacitor) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 56 FME-MB96350 rev 6 MB96350 Series 3. DC characteristics (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Input H voltage Value Unit Typ Max 0.8 VCC - VCC + 0.3 V 0.7 VCC - VCC + 0.3 V VCC ≥ 4.5V 0.74 VCC - VCC + 0.3 V VCC < 4.5V 0.8 VCC - VCC + 0.3 V TTL input selected 2.0 - VCC + 0.3 V CMOS Hysteresis Port inputs 0.7/0.3 input selected Pnn_m AUTOMOTIVE Hysteresis input selected VIHX0F X0 External clock in “Fast Clock Input mode” 0.8 VCC - VCC + 0.3 V VIHX0S X0,X1, X0A,X1A External clock in “oscillation mode” 2.5 - VCC + 0.3 V VIHR RSTX - 0.8 VCC - VCC + 0.3 V VIHM MD2-MD0 - VCC 0.3 - VCC + 0.3 V CMOS Hysteresis 0.8/0.2 input selected VSS 0.3 - 0.2 VCC V CMOS Hysteresis 0.7/0.3 input sePort inputs lected VSS 0.3 - 0.3 VCC V VSS 0.3 - 0.5 VCC V VSS 0.3 - 0.46 VCC TTL input selected VSS 0.3 - 0.8 V Input L voltage VIL Pnn_m Remarks Min CMOS Hysteresis 0.8/0.2 input selected VIH FME-MB96350 rev 6 Condition AUTOMOTIVE Hysteresis input selected CMOS Hysteresis input VCC ≥ 4.5V VCC < 4.5V VILX0F X0 External clock in “Fast Clock Input mode” VSS 0.3 - 0.2 VCC V VILX0S X0,X1, X0A,X1A External clock in “oscillation mode” VSS 0.3 - 0.4 V VILR RSTX - VSS 0.3 - 0.2 VCC V VILM MD2-MD0 - VSS 0.3 - VSS + 0.3 V CMOS Hysteresis input 57 MB96350 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Condition Value Unit Remarks Min Typ Max VCC 0.5 - - V Driving strength set to 2mA VCC 0.5 - - V Driving strength set to 5mA VCC 0.5 - - V - - 0.4 V Driving strength set to 2mA - - 0.4 V Driving strength set to 5mA - - 0.4 V AVSS, AVRL < VI < AVCC, AVRH -1 - +1 µA Single port pin VCC = 3.3V ± 10% 40 100 160 kΩ VCC = 5.0V ± 10% 25 50 100 kΩ 4.5V ≤ VCC ≤ 5.5V Output H voltage VOH2 Normal outputs IOH = -2mA 3.0V ≤ VCC < 4.5V IOH = -1.6mA 4.5V ≤ VCC ≤ 5.5V VOH5 Normal outputs IOH = -5mA 3.0V ≤ VCC < 4.5V IOH = -3mA 4.5V ≤ VCC ≤ 5.5V VOH3 3mA outputs IOH = -3mA 3.0V ≤ VCC < 4.5V IOH = -2mA 4.5V ≤ VCC ≤ 5.5V Output L voltage VOL2 Normal outputs IOL = +2mA 3.0V ≤ VCC < 4.5V IOL = +1.6mA 4.5V ≤ VCC ≤ 5.5V VOL5 Normal outputs IOL = +5mA 3.0V ≤ VCC < 4.5V IOL = +3mA VOL3 3mA outputs Input leak current IIL Pnn_m Pull-up resistance RUP Pnn_m, RSTX 3.0V ≤ VCC ≤ 5.5V IOL = +3mA VSS < VI < VCC 58 FME-MB96350 rev 6 MB96350 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol ICCPLL Power supply current in Run modes* ICCMAIN ICCRCH FME-MB96350 rev 6 Value Condition (at TA) Typ Max PLL Run mode with CLKS1/2 = 48MHz, CLKB = CLKP1/2 = 24MHz +25˚C 35 44 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125˚C 36 47 PLL Run mode with CLKS1/2 = CLKB = CLKP1= 56MHz, CLKP2 = 28MHz +25˚C 44 57 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125˚C 45 60 PLL Run mode with CLKS1/2 = 96MHz, CLKB = CLKP1= 48MHz, CLKP2 = 24MHz +25˚C 49 62 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125˚C 50 65 Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz +25˚C 4.5 5.5 (CLKPLL, CLKSC and CLKRC stopped) +125˚C 5.1 8.5 RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 2MHz +25˚C 2.9 4 (CLKMC, CLKPLL and CLKSC stopped) +125˚C 3.5 6.5 Unit Remarks mA 0 Flash wait states mA 2 Flash wait states mA 1 Flash wait state mA 1 Flash wait state mA 1 Flash wait state 59 MB96350 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) ICCRCL Power supply current in Run modes* RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 1 ICCSUB 60 +25˚C ICCSPLL Typ Max 0.4 0.6 +125˚C 0.9 3.5 +25˚C 0.18 0.3 +125˚C 0.68 3.3 +25˚C 0.15 0.25 0.65 3.2 0.1 0.2 0.6 3 (CLKMC, CLKPLL and CLKSC stopped. Voltage +125˚C regulator in low power mode, no Flash programming/erasing allowed) Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz Power supply current in Sleep modes* Value Condition (at TA) +25˚C (CLKMC, CLKPLL and CLKRC stopped, no Flash +125˚C programming/erasing allowed) Unit Remarks mA MB96F356 at 1 Flash wait state mA MB96F353/F355 at 1 Flash wait state mA 1 Flash wait state mA 1 Flash wait state PLL Sleep mode with CLKS1/2 = 48MHz, CLKP1/2 = 24MHz +25˚C 9 10.5 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125˚C 9.7 13 PLL Sleep mode with CLKS1/2 = CLKP1= 56MHz, CLKP2 = 28MHz +25˚C 14 15.5 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125˚C 14.8 18 PLL Sleep mode with CLKS1/2 = 96MHz, CLKP1= 48MHz, CLKP2 = 24MHz +25˚C 15 16.5 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125˚C 15.8 19 mA mA mA FME-MB96350 rev 6 MB96350 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol ICCSMAIN ICCSRCH Power supply current in Sleep modes* ICCSRCL ICCSSUB Power supply current in Timer modes* FME-MB96350 rev 6 ICCTPLL Value Condition (at TA) Typ Max Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz +25˚C 1.5 1.8 (CLKPLL, CLKSC and CLKRC stopped) +125˚C 2 4.5 RC Sleep mode with CLKS1/2 = CLKP1/2 = 2MHz +25˚C 0.8 1.3 (CLKMC, CLKPLL and CLKSC stopped) +125˚C 1.4 4 RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 0 +25˚C 0.3 0.5 +125˚C 0.8 3.4 +25˚C 0.09 0.2 +125˚C 0.59 3.1 RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 1 +25˚C 0.06 0.15 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) +125˚C 0.56 3 Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz +25˚C 0.04 0.12 (CLKMC, CLKPLL and CLKRC stopped) +125˚C 0.54 2.9 PLL Timer mode with CLKMC = 4MHz, CLKPLL = 48MHz +25˚C 1.6 2 (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125˚C 2.1 4.8 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) Unit Remarks mA mA mA MB96F356 mA MB96F353/F355 mA mA mA 61 MB96350 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Typ Max +25˚C 0.35 0.5 +125˚C 0.85 3.3 +25˚C 0.13 0.2 +125˚C 0.63 3 +25˚C 0.1 0.15 +125˚C 0.6 2.9 +25˚C 0.35 0.5 +125˚C 0.85 3.3 +25˚C 0.13 0.2 +125˚C 0.63 3 +25˚C 0.1 0.15 +125˚C 0.6 2.9 +25˚C 0.3 0.45 +125˚C 0.8 3.2 +25˚C 0.08 0.15 +125˚C 0.58 2.95 +25˚C 0.05 0.1 +125˚C 0.55 2.85 Sub Timer mode with CLKSC = 32kHz +25˚C 0.03 0.1 (CLKMC, CLKPLL and CLKRC stopped) +125˚C 0.53 2.85 Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 ICCTMAIN (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in high power mode) Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 1 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 ICCTRCH Power supply current in Timer modes* (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 0 ICCTRCL (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) ICCTSUB 62 Value Condition (at TA) Unit Remarks mA MB96F356 mA MB96F353/F355 mA mA MB96F356 mA MB96F353/F355 mA mA MB96F356 mA MB96F353/F355 mA mA FME-MB96350 rev 6 MB96350 Series (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Power supply current in Stop Mode Symbol Value Condition (at TA) Typ Max VRCR:LPMB[2:0] = 110B +25˚C 0.02 0.08 (Core voltage at 1.8V) +125˚C 0.52 2.8 VRCR:LPMB[2:0] = 000B +25˚C 0.015 0.06 (Core voltage at 1.2V) +125˚C 0.4 2.3 - 5 10 +25˚C 90 140 +125˚C 100 150 Unit Remarks mA ICCH mA MB96F353/F355 Power supply current for active Low Voltage detector ICCLVD Low voltage detector enabled (RCR:LVDE = 1) µA Must be added to all current above MB96F356 µA Must be added to all current above Power supply current for active Clock modulator ICCCLOMO Clock modulator enabled (CMCR:PDX = 1) - 3 4.5 mA Must be added to all current above Flash Write/Erase current ICCFLASH Current for one Flash module - 15 40 mA Must be added to all current above Input capacitance CIN - - 5 15 pF Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS * The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. FME-MB96350 rev 6 63 MB96350 Series 4. AC Characteristics Source Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Clock frequency Clock frequency Symbol fC fFCI Pin X0, X1 fCL X0A Clock frequency fCR Unit Remarks Min Typ Max 3 - 16 MHz When using a crystal oscillator, PLL off 0 - 16 MHz When using an opposite phase external clock, PLL off 3.5 - 16 MHz When using a crystal oscillator or opposite phase external clock, PLL on 0 - 56 MHz When using a single phase external clock in “Fast Clock Input mode” , PLL off 3.5 - 56 MHz When using a single phase external clock in “Fast Clock Input mode” , PLL on 32 32.768 100 kHz When using an oscillation circuit 0 - 100 kHz When using an opposite phase external clock 0 - 50 kHz When using a single phase external clock 50 100 200 kHz When using slow frequency of RC oscillator 1 2 4 MHz When using fast frequency of RC oscillator X0 X0A, X1A Clock frequency Value - PLL Clock frequency fCLKVCO - 64 - 200 MHz Permitted VCO output frequency of PLL (CLKVCO) PLL Phase Jitter TPSKEW - - - ± 5 ns For CLKMC (PLL input clock) ≥ 4MHz Input clock pulse width PWH, PWL X0,X1 8 - - ns Duty ratio is about 30% to 70% 5 - - µs Input clock pulse width 64 PWHL, PWLL X0A,X1A FME-MB96350 rev 6 MB96350 Series tCYL VIH X0 VIL PWH PWL tCYLL VIH X0A VIL PWHL FME-MB96350 rev 6 PWLL 65 MB96350 Series Internal Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Core Voltage Settings Parameter Internal System clock frequency (CLKS1 and CLKS2) Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) Internal peripheral clock frequency (CLKP2) 66 Symbol 1.8V 1.9V Unit Remarks Min Max Min Max 0 92 0 96 MHz Others than below 0 88 0 96 MHz MB96F356 fCLKB, fCLKP1 0 52 0 56 MHz fCLKP2 0 28 0 32 MHz fCLKS1, fCLKS2 FME-MB96350 rev 6 MB96350 Series External Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Reset input time Symbol Pin tRSTL RSTX Value Min Typ Max 500 - - Unit Remarks ns tRSTL RSTX 0.2 VCC FME-MB96350 rev 6 0.2 VCC 67 MB96350 Series Power On Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Power on rise time Power off time Symbol Pin tR tOFF Value Unit Min Typ Max Vcc 0.05 - 30 ms Vcc 1 - - ms Remarks tR 2.7V VCC 0.2 V 0.2 V 0.2 V tOFF If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. VCC 3V 68 Rising edge of 50 mV/ms maximum is allowed FME-MB96350 rev 6 MB96350 Series External Input timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Value Condition INTn(_R) NMI(_R) Input pulse width tINH tINL Min Max 200 ⎯ Unit Used Pin input function External Interrupt ns NMI Pnn_m General Purpose IO TINn(_R) Reload Timer TTGn(_R) ⎯ 2*tCLKP1 + 200 (tCLKP1=1/ fCLKP1) ADTG(_R) PPG Trigger input ⎯ ns AD Converter Trigger FRCKn(_R) Free Running Timer external clock INn(_R) Input Capture Note : Relocated Resource Inputs have same characteristics External Pin input VIH VIH tINH FME-MB96350 rev 6 VIL VIL tINL 69 MB96350 Series External Bus timing Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. Basic Timing Parameter (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin Condition ECLK → UBX/ LBX / CSn time ECLK → ALE time Max 25 ⎯ tCYC/2-5 tCYC/2+5 tCLCH tCYC/2-5 tCYC/2+5 tCHCBH -20 20 -20 20 -20 20 tCLCBL -20 20 tCHLH -10 10 -10 10 -10 10 -10 10 -15 15 -15 15 -15 15 -15 15 -10 10 -10 10 -10 10 -10 10 tCHCL tCHCBL tCLCBH tCHLL tCLLH ECLK CSn, UBX, LBX, ECLK ALE, ECLK ⎯ ⎯ ⎯ tCLLL tCHAV ECLK → address valid time tCLAV tCLADV tCHADV A[23:16], ECLK ⎯ AD[15:0], ECLK ⎯ tCHRWH ECLK → RDX /WRX time tCHRWL tCLRWH tCLRWL 70 Unit Min tCYC ECLK Value RDX, WRX, WRLX,WRHX, ECLK ⎯ Remarks ns ns ns ns ns ns FME-MB96350 rev 6 MB96350 Series (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition Min Max 30 ⎯ tCYC/2-8 tCYC/2+8 tCLCH tCYC/2-8 tCYC/2+8 tCHCBH -25 25 -25 25 -25 25 tCLCBL -25 25 tCHLH -15 15 -15 15 -15 15 -15 15 -20 20 -20 20 -20 20 -20 20 -15 15 -15 15 -15 15 -15 15 tCYC ECLK ECLK → UBX/ LBX / CSn time ECLK → ALE time tCHCL tCHCBL tCLCBH tCHLL tCLLH ECLK CSn, UBX, LBX, ECLK ALE, ECLK ⎯ ⎯ ⎯ tCLLL tCHAV ECLK → address valid time tCLAV tCLADV tCHADV A[23:16], ECLK ⎯ AD[15:0], ECLK ⎯ tCHRWH ECLK → RDX /WRX time tCHRWL tCLRWH tCLRWL FME-MB96350 rev 6 Value RDX, WRX, WRLX, WRHX, ECLK ⎯ Unit Remarks ns ns ns ns ns ns 71 MB96350 Series tCYC tCHCL ECLK tCLCH 0.8*Vcc 0.2*Vcc tCLAV tCHAV A[23:16] tCHCBL tCLCBH tCLCBL tCHCBH tCHRWL tCLRWH tCLRWL tCHRWH CSn LBX UBX RDX WRX (WRLX, WRHX) tCLLH tCHLL tCHLH tCLLL ALE tCHADV tCLADV AD[15:0] Address Refer to the Hardware Manual for detailed Timing Charts 72 FME-MB96350 rev 6 MB96350 Series Bus Timing (Read) Parameter (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin Conditions Min Max tCYC/2 − 5 ⎯ tCYC − 5 ⎯ EACL:STS=0 and EACL:ACE=1 3tCYC/2 − 5 ⎯ EACL:STS=0 and EACL:ACE=0 tCYC − 15 ⎯ EACL:STS=0 and EACL:ACE=0 ALE pulse width tLHLL ALE tAVLL ALE, A[23:16], Valid address ⇒ ALE ↓ time tADVLL ALE,AD[15:0] ALE ↓ ⇒ Address valid time tLLAX ALE, AD[15:0] tAVRL RDX, A[23:16] Valid address ⇒ RDX ↓ time tADVRL RDX, AD[15:0] tAVDV Valid address ⇒ Valid data input A[23:16], AD[15:0] tADVDV AD[15:0] Value EACL:STS=1 EACL:STS=1 and 3tCYC/2 − 15 EACL:ACE=0 ⎯ EACL:STS=0 and EACL:ACE=1 ⎯ 2tCYC − 15 ⎯ EACL:STS=0 and EACL:ACE=0 tCYC/2 − 15 ⎯ EACL:STS=1 and EACL:ACE=0 tCYC − 15 ⎯ ns ns EACL:STS=0 and 3tCYC/2 − 15 EACL:ACE=1 ⎯ EACL:STS=1 and EACL:ACE=1 2tCYC − 15 ⎯ EACL:STS=0 tCYC/2 − 15 ⎯ EACL:STS=1 -15 ⎯ EACL:ACE=0 3tCYC/2 − 15 ⎯ ns ns EACL:ACE=1 5tCYC/2 − 15 ⎯ EACL:ACE=0 tCYC − 15 ⎯ ns EACL:ACE=1 2tCYC − 15 ⎯ EACL:ACE=0 ⎯ 3tCYC − 55 ns w/o cycle extension ns w/o cycle extension ns w/o cycle extension 3 tCYC/2 − 50 ns w/o cycle extension EACL:ACE=1 ⎯ 4tCYC − 55 EACL:ACE=0 ⎯ 5tCYC/2 − 55 ⎯ 7tCYC/2 − 55 ⎯ RDX pulse width tRLRH RDX ⎯ 3 tCYC/2 − 5 RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0] ⎯ ⎯ RDX ↑ ⇒ Data hold time tRHDX RDX, AD[15:0] ⎯ 0 FME-MB96350 rev 6 Remarks ns EACL:STS=1 and 5tCYC/2 − 15 EACL:ACE=1 EACL:ACE=1 Unit ⎯ ns 73 MB96350 Series (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Address valid ⇒ Data hold time tAXDX Pin A[23:16], AD[15:0] RDX ↑ ⇒ ALE ↑ time tRHLH RDX, ALE Valid address ⇒ ECLK ↑ time tAVCH A[23:16], ECLK tADVCH AD[15:0], ECLK RDX ↓ ⇒ ECLK ↑ time tRLCH RDX, ECLK ALE ↓ ⇒ RDX ↓ time tLLRL ALE, RDX ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK Conditions ⎯ Value Min Max 0 ⎯ EACL:STS=1 and 3tCYC/2 − 10 EACL:ACE=1 ⎯ other ECL:STS, tCYC/2 − 10 EACL:ACE setting ⎯ Unit ns ns tCYC − 15 ⎯ tCYC/2 − 15 ⎯ tCYC/2 − 10 ⎯ EACL:STS=0 tCYC/2 − 10 ⎯ EACL:STS=1 − 10 ⎯ ⎯ tCYC − 50 ⎯ ⎯ ⎯ Remarks ns ns ns ns (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions Min Max tCYC/2 − 8 ⎯ tCYC − 8 ⎯ EACL:STS=0 and EACL:ACE=1 3tCYC/2 − 8 ⎯ EACL:STS=0 and EACL:ACE=0 tCYC − 20 ⎯ EACL:STS=0 and EACL:ACE=0 ALE pulse width tLHLL ALE tAVLL ALE, A[23:16], Valid address ⇒ ALE ↓ time tADVLL ALE, AD[15:0] ALE ↓ ⇒ Address valid time 74 tLLAX ALE, AD[15:0] Value EACL:STS=1 EACL:STS=1 and 3tCYC/2 − 20 EACL:ACE=0 ⎯ EACL:STS=0 and EACL:ACE=1 ⎯ 2tCYC − 20 Unit Remarks ns ns EACL:STS=1 and 5tCYC/2 − 20 EACL:ACE=1 ⎯ EACL:STS=0 and EACL:ACE=0 tCYC/2 − 20 ⎯ EACL:STS=1 and EACL:ACE=0 tCYC − 20 ⎯ ns EACL:STS=0 and 3tCYC/2 − 20 EACL:ACE=1 ⎯ EACL:STS=1 and EACL:ACE=1 2tCYC − 20 ⎯ EACL:STS=0 tCYC/2 − 20 ⎯ EACL:STS=1 -20 ⎯ ns FME-MB96350 rev 6 MB96350 Series (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol tAVRL Pin RDX, A[23:16] Valid address ⇒ RDX ↓ time tADVRL RDX, AD[15:0] tAVDV Valid address ⇒ Valid data input A[23:16], AD[15:0] tADVDV AD[15:0] Conditions Value Min Max EACL:ACE=0 3tCYC/2 − 20 ⎯ EACL:ACE=1 5tCYC/2 − 20 ⎯ EACL:ACE=0 tCYC − 20 ⎯ EACL:ACE=1 2tCYC − 20 ⎯ EACL:ACE=0 ⎯ 3tCYC − 60 ns ns w/o cycle extension ns w/o cycle extension ns w/o cycle extension 3tCYC/2 − 55 ns w/o cycle extension ⎯ 4tCYC − 60 EACL:ACE=0 ⎯ 5tCYC/2 − 60 ⎯ 7tCYC/2 − 60 ⎯ RDX pulse width tRLRH RDX ⎯ 3tCYC/2 − 8 RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0] ⎯ ⎯ RDX ↑ ⇒ Data hold time tRHDX RDX, AD[15:0] ⎯ 0 ⎯ ns Address valid ⇒ Data hold time tAXDX A[23:16] ⎯ 0 ⎯ ns RDX ↑ ⇒ ALE ↑ time tRHLH RDX, ALE Valid address ⇒ ECLK ↑ time tAVCH A[23:16], ECLK tADVCH AD[15:0], ECLK RDX ↓ ⇒ ECLK ↑ time tRLCH RDX, ECLK ALE ↓ ⇒ RDX ↓ time tLLRL ALE, RDX ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK FME-MB96350 rev 6 EACL:STS=1 and 3tCYC/2 − 15 EACL:ACE=1 ⎯ other ECL:STS, tCYC/2 − 15 EACL:ACE setting ⎯ ns tCYC − 20 ⎯ tCYC/2 − 20 ⎯ tCYC/2 − 15 ⎯ EACL:STS=0 tCYC/2 − 15 ⎯ EACL:STS=1 − 15 ⎯ ⎯ tCYC − 55 ⎯ ⎯ ⎯ Remarks ns EACL:ACE=1 EACL:ACE=1 Unit ns ns ns ns 75 MB96350 Series tAVCH tRLCH tADVCH tCHDV 0.8*Vcc ECLK tAVLL tLLAX tADVLL ALE tRHLH 0.2*VCC tLHLL tAVRL tADVRL tRLRH RDX tLLRL A[23:16] tRLDV tAXDX tAVDV tRHDX tADVDV AD[15:0] VIH VIH Address Read data VIL VIL Refer to the Hardware Manual for detailed Timing Charts . Bus Timing (Write) Parameter (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol tAVWL Valid address ⇒ WRX ↓ time tADVWL Pin WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] Condition Value Min Max EACL:ACE=0 3tCYC/2 − 15 ⎯ EACL:ACE=1 5tCYC/2 − 15 ⎯ EACL:ACE=0 tCYC − 15 ⎯ EACL:ACE=1 Unit Remarks ns ns 2tCYC − 15 ⎯ WRX pulse width tWLWH WRX, WRXL, WRHX ⎯ tCYC − 5 ⎯ ns w/o cycle extension Valid data output ⇒ WRX ↑ time tDVWH WRX, WRLX, WRHX, AD[15:0] ⎯ tCYC − 20 ⎯ ns w/o cycle extension 76 FME-MB96350 rev 6 MB96350 Series (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter WRX ↑ ⇒ Data hold time WRX ↑ ⇒ Address valid time WRX ↑ ⇒ ALE ↑ time WRX ↓ ⇒ ECLK ↑ time Symbol Pin Condition WRX ⇒ CSn time Unit Min Max tCYC/2 − 15 ⎯ ns tCYC/2 − 15 ⎯ ns 2tCYC − 10 ⎯ tWHLH WRX, WRLX, WRHX, ALE EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting tCYC − 10 ⎯ tWLCH WRX, WRLX, WRHX, ECLK ⎯ tCYC/2 − 10 ⎯ ⎯ 3tCYC/2 − 15 ⎯ 5tCYC/2 − 15 tCYC/2 − 15 ⎯ tWHDX WRX, WRLX, WRHX, AD[15:0] tWHAX WRX, WRLX, WRHX, A[23:16] ⎯ ⎯ EACL:ACE=0 CSn ⇒ WRX time Value tCSLWL tWHCSH WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn EACL:ACE=1 ⎯ Remarks ns ns ns ns (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol tAVWL Valid address ⇒ WRX ↓ time tADVWL Pin WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] Condition Value Min Max EACL:ACE=0 3tCYC/2 − 20 ⎯ EACL:ACE=1 5tCYC/2 − 20 ⎯ EACL:ACE=0 tCYC − 20 ⎯ EACL:ACE=1 Unit Remarks ns ns 2tCYC − 20 ⎯ WRX pulse width tWLWH WRX, WRXL, WRHX ⎯ tCYC − 8 ⎯ ns w/o cycle extension Valid data output ⇒ WRX ↑ time tDVWH WRX, WRLX, WRHX, AD[15:0] ⎯ tCYC − 25 ⎯ ns w/o cycle extension WRX ↑ ⇒ Data hold time tWHDX WRX, WRLX, WRHX, AD[15:0] ⎯ tCYC/2 − 20 ⎯ ns tWHAX WRX, WRLX, WRHX, A[23:16] tCYC/2 − 20 ⎯ ns WRX ↑ ⇒ Address valid time FME-MB96350 rev 6 ⎯ 77 MB96350 Series (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter WRX ↑ ⇒ ALE ↑ time WRX ↓ ⇒ ECLK ↑ time CSn ⇒ WRX time WRX ⇒ CSn time Symbol Pin Condition Value Min Max 2tCYC − 15 ⎯ tWHLH WRX, WRLX, WRHX, ALE EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting tCYC − 15 ⎯ tWLCH WRX, WRLX, WRHX, ECLK ⎯ tCYC/2 − 15 ⎯ EACL:ACE=0 ⎯ 3tCYC/2 − 20 EACL:ACE=1 ⎯ 5tCYC/2 − 20 tCYC/2 − 20 ⎯ tCSLWL tWHCSH WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn ⎯ Unit Remarks ns ns ns ns tWLCH 0.8*VCC ECLK tWHLH ALE . tAVWL tADVWL WRX (WRLX, WRHX) tWLWH 0.2*VCC tCSLWL tWHCSH CSn tWHAX A[23:16] tDVWH AD[15:0] Address tWHDX Write data Refer to the Hardware Manual for detailed Timing Charts 78 FME-MB96350 rev 6 MB96350 Series Ready Input Timing Parameter (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin RDY setup time tRYHS RDY RDY hold time tRYHH RDY Rated Value Test Condition ⎯ Units Min Max 35 ⎯ ns 0 ⎯ ns Remarks (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin RDY setup time tRYHS RDY RDY hold time tRYHH RDY Rated Value Test Condition ⎯ Units Min Max 45 ⎯ ns 0 ⎯ ns Remarks Note : If the RDY setup time is insufficient, use the auto-ready function. 0.8*VCC ECLK RDY When WAIT is not used. RDY When WAIT is used. tRYHS tRYHH VIH VIH VIL Refer to the Hardware Manual for detailed Timing Charts Hold Timing Parameter (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin Pin floating ⇒ HAKX ↓ time tXHAL HAKX HAKX ↑ time ⇒ Pin valid time tHAHV HAKX Condition ⎯ Value Min Max Units tCYC − 20 tCYC + 20 ns tCYC − 20 tCYC + 20 ns Remarks (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Pin floating ⇒ HAKX ↓ time tXHAL HAKX HAKX ↑ time ⇒ Pin valid time tHAHV HAKX FME-MB96350 rev 6 Condition ⎯ Value Min Max Units tCYC − 25 tCYC + 25 ns tCYC − 25 tCYC + 25 ns Remarks 79 MB96350 Series 0.8*VCC HAKX 0.2*VCC tHAHV tXHAL Each pin 0.8*VCC High-Z 0.2*VCC Refer to the Hardware Manual for detailed Timing Charts 80 FME-MB96350 rev 6 MB96350 Series USART timing WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. (TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) Parameter Condition VCC = AVCC= 4.5V VCC = AVCC= 3.0V to 5.5V to 4.5V Unit Min Max Min Max Symbol Pin Serial clock cycle time tSCYCI SCKn 4 tCLKP1 ⎯ 4 tCLKP1 ⎯ ns SCK ↓ → SOT delay time tSLOVI SCKn, SOTn -20 +20 -30 +30 ns SOT → SCK ↑ delay time tOVSHI SCKn, SOTn N*tCLKP1 - 20 *1 ⎯ N*tCLKP1 30 *1 ⎯ ns Valid SIN → SCK ↑ tIVSHI SCKn, SINn tCLKP1 + 45 ⎯ tCLKP1 + 55 ⎯ ns SCK ↑ → Valid SIN hold time tSHIXI SCKn, SINn 0 ⎯ 0 ⎯ ns Serial clock “L” pulse width tSLSHE SCKn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns Serial clock “H” pulse width tSHSLE SCKn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns SCK ↓ → SOT delay time tSLOVE SCKn, SOTn ⎯ 2 tCLKP1 + 45 ⎯ 2 tCLKP1 + 55 ns Valid SIN → SCK ↑ tIVSHE SCKn, SINn tCLKP1/2 + 10 ⎯ tCLKP1/2 + 10 ⎯ ns SCK ↑ → Valid SIN hold time tSHIXE SCKn, SINn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns SCK fall time tFE SCKn ⎯ 20 ⎯ 20 ns SCK rise time tRE SCKn ⎯ 20 ⎯ 20 ns Internal Shift Clock Mode External Shift Clock Mode Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL” • tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns *1: Parameter N depends on tSCYCI and can be calculated as follows: • if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 • if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI N FME-MB96350 rev 6 4*tCLKP1 2 5*tCLKP1, 6*tCLKP1 3 7*tCLKP1, 8*tCLKP1 4 ... ... 81 MB96350 Series tSCYCI SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC SCK for ESCR:SCES = 1 0.8*VCC 0.8*VCC 0.2*VCC tSLOVI tOVSHI 0.8*VCC SOT 0.2*VCC tSHIXI tIVSHI SIN VIH VIH VIL VIL Internal Shift Clock Mode tSLSHE SCK for ESCR:SCES = 0 tSHSLE VIH VIH VIL VIL VIH VIL tFE VIH VIL VIL SCK for ESCR:SCES = 1 VIH tSLOVE tRE SOT 0.8*VCC 0.2*VCC tIVSHE SIN tSHIXE VIH VIH VIL VIL External Shift Clock Mode 82 FME-MB96350 rev 6 MB96350 Series I2C Timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V) Parameter Symbol Condition Standard-mode Fast-mode*4 Unit Min Max Min Max fSCL 0 100 0 400 kHz tHDSTA 4.0 ⎯ 0.6 ⎯ µs “L” width of the SCL clock tLOW 4.7 ⎯ 1.3 ⎯ µs “H” width of the SCL clock tHIGH 4.0 ⎯ 0.6 ⎯ µs Set-up time for a repeated START condition SCL↑→SDA↓ tSUSTA 4.7 ⎯ 0.6 ⎯ µs Data hold time SCL↓→SDA↓↑ tHDDAT 0 3.45*2 0 0.9*3 µs Data set-up time SDA↓↑→SCL↑ tSUDAT 250 ⎯ 100 ⎯ ns Set-up time for STOP condition SCL↑→SDA↑ tSUSTO 4.0 ⎯ 0.6 ⎯ µs tBUS 4.7 ⎯ 1.3 ⎯ µs SCL clock frequency Hold time (repeated) START condition SDA↓→SCL↓ Bus free time between a STOP and START condition R = 1.7 kΩ, C = 50 pF*1 *1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. *4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. SDA tSUDAT tLOW tBUS tHDSTA SCL tHDSTA FME-MB96350 rev 6 tHDDAT tHIGH tSUSTA tSUSTO 83 MB96350 Series 5. Analog Digital Converter (TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Resolution - Total error Value Unit Min Typ Max - - - 10 bit - - -3 - +3 LSB Nonlinearity error - - -2.5 - +2.5 LSB Differential nonlinearity error - - -1.9 - +1.9 LSB VOT ANn AVRL 1.5 AVRL+ 0.5 VFST ANn AVRH 3.5 AVRH - AVRH + LSB 1.5 0.5 Compare time - - Sampling time - - IAIN ANn Zero reading voltage Full scale reading voltage Analog port input current Analog port input current Analog input voltage range Reference voltage range IAIN AVRL + LSB 2.5 1.0 - 16,500 µs 4.5V ≤ ΑVCC ≤ 5.5V 2.0 - - µs 3.0V ≤ ΑVCC < 4.5V 0.5 - - µs 4.5V ≤ ΑVCC ≤ 5.5V 1.2 - - µs 3.0V ≤ ΑVCC < 4.5V -3 - +3 µA AVSS, AVRL < VI < AVCC, AVRH -1 - +1 TA = 25 ˚C, µA AVSS, AVRL < VI < AVCC, AVRH -3 - +3 TA = 125 ˚C, µA AVSS, AVRL < VI < AVCC, AVRH ANn VAIN ANn AVRL - AVRH V AVRH AVRH 0.75 AVcc - AVcc V AVRL AVRL AVSS - 0.25 AVCC V IA AVcc - 2.5 5 mA A/D Converter active IAH AVcc - - 5 µA A/D Converter not operated IR AVRH/ AVRL - 0.7 1 mA A/D Converter active IRH AVRH/ AVRL - - 5 µA A/D Converter not operated - ANn - - 4 LSB Power supply current Reference voltage current Offset between input channels Remarks Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller. 84 FME-MB96350 rev 6 MB96350 Series Definition of A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics. Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Total error 3FF 3FE Actual conversion characteristics 1.5 LSB Digital output 3FD {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (Actually-measured value) 003 Actual conversion characteristics Ideal characteristics 002 001 0.5 LSB AVRL AVRH Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL 1 LSB = (Ideal value) [V] 1024 Total error of digital output “N” = [LSB] N: A/D converter digital output value VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N − 1) to N. FME-MB96350 rev 6 85 MB96350 Series Nonlinearity error Differential nonlinearity error Ideal characteristics 3FF Digital output 3FD Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) 004 003 Actual conversion characteristics Digital output 3FE Actual conversion characteristics N V (N + 1) T (actual measurement value) VNT (actual measurement value) N−1 002 Ideal characteristics Actual conversion characteristics N−2 001 VOT (actual measurement value) AVRL AVRH AVRL AVRH Analog input Analog input Nonlinearity error of digital output N = Differential nonlinearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 [LSB] −1 LSB [LSB] [V] N : A/D converter digital output value VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” Notes on A/D Converter Section • About the external impedance of the analog input and the sampling time of the A/D converter (with sample and hold circuit): If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • analog input circuit model: R Comparator Analog input C Sampling switch Reference value: • C = 8.5 pF (Max) 86 FME-MB96350 rev 6 MB96350 Series To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum sampling time must be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be decreased so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7τ, where τ = RC. If the external input resistance (Rext) connected to the analog input is included, the sampling time is expressed as follows: Tsamp [min] = 7 × (Rext + 2.6kΩ) × C for 4.5 ≤ AVcc ≤ 5.5 Tsamp [min] = 7 × (Rext + 12.1kΩ) × C for 3.0 ≤ AVcc ≤ 4.5 If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About the error The accuracy gets worse as |AVRH - AVRL| becomes smaller. FME-MB96350 rev 6 87 MB96350 Series 6. Low Voltage Detector characteristics (TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V) Parameter Symbol Stabilization time Value *1 Value *2 Unit Remarks 110 µs After power-up or change of detection level 2.65 2.95 V CILCR:LVL[3:0]=”0000” 3.1 2.85 3.2 V CILCR:LVL[3:0]=”0001” 3.1 3.3 3.05 3.4 V CILCR:LVL[3:0]=”0010” VDL3 3.5 3.75 3.45 3.85 V CILCR:LVL[3:0]=”0011” Level 4 VDL4 3.6 3.85 3.55 3.95 V CILCR:LVL[3:0]=”0100” Level 5 VDL5 3.7 3.95 3.65 4.1 V CILCR:LVL[3:0]=”0101” Level 6 VDL6 3.8 4.05 3.75 4.2 V CILCR:LVL[3:0]=”0110” Level 7 VDL7 3.9 4.15 3.85 4.3 V CILCR:LVL[3:0]=”0111” Level 8 VDL8 4.0 4.25 3.95 4.4 V CILCR:LVL[3:0]=”1000” Level 9 VDL9 4.1 4.35 4.05 4.5 V CILCR:LVL[3:0]=”1001” Level 10 VDL10 not used not used Level 11 VDL11 not used not used Level 12 VDL12 not used not used Level 13 VDL13 not used not used Level 14 VDL14 not used not used Level 15 VDL15 not used not used Min Max Min Max TLVDSTAB - 75 - Level 0 VDL0 2.7 2.9 Level 1 VDL1 2.9 Level 2 VDL2 Level 3 *1: valid for all devices except devices listed under “*2” *2: valid for: MB96F353/F355 CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register. Levels 10 to 15 are not used in this device. V For correct detection, the slope of the voltage level must satisfy dV ≤ 0.004 ----- . dt µs Faster variations are regarded as noise and may not be detected. The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7V. The electrical characteristics however are only valid in the specified range (usually down to 3.0V). 88 FME-MB96350 rev 6 MB96350 Series Low Voltage Detector Operation In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. Voltage [V] VCC VDLx, Max VDLx, Min dV dt Time [s] Normal Operation FME-MB96350 rev 6 Low Voltage Reset Assertion Power Reset Extension Time 89 MB96350 Series 7. FLASH memory program/erase characteristics (TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Value Unit Remarks 3.6 s Without erasure pre-programming time n*0.9 n*3.6 s Without erasure pre-programming time (n is the number of Flash sector of the device) - 23 370 us Without overhead time for submitting write command 10 000 - - cycle 20 - - year Min Typ Max Sector erase time - 0.9 Chip erase time - Word (16-bit width) programming time Program/Erase cycle Flash data retention time *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) 90 FME-MB96350 rev 6 MB96350 Series ■ EXAMPLE CHARACTERISTICS The diagrams below show the characteristics of one measured sample with typical process parameters. Run Mode 100.00 PLL clock (56 MHz) 10.00 Icc [mA] Main osc. (4 MHz) RC clock (2 MHz) 1.00 RC clock (100 kHz) 0.10 Sub osc.(32 kHz) 0.01 -50.00 0.00 50.00 100.00 150.00 100.00 150.00 Ta [ºC] Sleep mode 100.00 PLL clock (56 MHz) Icc [mA] 10.00 Main osc. (4 MHz) 1.00 RC clock (2 MHz) RC clock (100 kHz) 0.10 Sub osc.(32 kHz) 0.01 -50.00 0.00 50.00 Ta [ºC] FME-MB96350 rev 6 91 MB96350 Series Timer mode 10.00 PLL clock (56 MHz) Icc [mA] 1.00 Main osc. (4 MHz) RC clock (2 MHz) RC clock (100 kHz) 0.10 Sub osc. (32 kHz) 0.01 -50.00 0.00 50.00 100.00 150.00 100.00 150.00 Ta [ºC] Stop mode 1.00 Icc [mA] 0.10 0.01 0.00 -50.00 0.00 50.00 Ta [ºC] 92 FME-MB96350 rev 6 MB96350 Series Used settings Mode Run mode Sleep mode Selected Source Clock Clock/Regulator Settings PLL CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz CLKP2 = 28 MHz Regulator in High Power Mode Core Voltage = 1.9 V Main osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz Regulator in High Power Mode Core Voltage = 1.8 V RC clock fast CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz Regulator in High Power Mode Core Voltage = 1.8 V RC clock slow CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz Regulator in High Power Mode Core Voltage = 1.8 V Sub osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz Regulator in Low Power Mode A Core Voltage = 1.8 V PLL CLKS1 = CLKS2 = CLKP1 = 56 MHz CLKP2 = 28 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.9 V Main osc. CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V RC clock fast CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V RC clock slow CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz (CLKB is stopped in this mode) Regulator in High Power Mode Core Voltage = 1.8 V Sub osc. CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz (CLKB is stopped in this mode) Regulator in Low Power Mode A Core Voltage = 1.8 V FME-MB96350 rev 6 93 MB96350 Series Used settings Mode Timer mode Stop mode 94 Selected Source Clock Clock/Regulator Settings PLL CLKMC = 4 MHz, CLKPLL = 56 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.9 V Main osc. CLKMC = 4 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock fast CLKRC = 2 MHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V RC clock slow CLKRC = 100 kHz (System clocks are stopped in this mode) Regulator in High Power Mode, Core Voltage = 1.8 V Sub osc. CLKSC = 100 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode A, Core Voltage = 1.8 V stopped (All clocks are stopped in this mode) Regulator in Low Power Mode B, Core Voltage = 1.8 V FME-MB96350 rev 6 MB96350 Series ■ PACKAGE DIMENSION MB96(F)35x LQFP 64 - M23 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.0 × 12.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LFQFP64-12×12-0.65 (FPT-64P-M23) 64-pin plastic LQFP (FPT-64P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ *12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.0057±.0022) 33 32 49 0.10(.004) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 0.25(.010) INDEX 0~8˚ 17 64 1 "A" 16 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) ©2003-2008 FUJITSU LIMITED F64034S-c-1-2 C 2003 FUJITSU LIMITEDMICROELECTRONICS F64034S-c-1-1 FME-MB96350 rev 6 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) M Dimensions in mm (inches). Note: The values in parentheses are reference values 95 MB96350 Series ■ PACKAGE DIMENSION MB96(F)35x LQFP 64 - M24 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.0 × 10.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g Code (Reference) P-LFQFP64-10×10-0.50 (FPT-64P-M24) 64-pin plastic LQFP (FPT-64P-M24) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ * 10.00±0.10(.394±.004)SQ 48 0.145±0.055 (.006±.002) 33 49 32 Details of "A" part 0.08(.003) +0.20 1.50 –0.10 +.008 .059 –.004 INDEX 64 0˚~8˚ 17 (Mounting height) 0.10±0.10 (.004±.004) (Stand off) "A" LEAD No. 1 16 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M ©2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2 C 2005 FUJITSU LIMITED F64036S-c-1-1 96 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values FME-MB96350 rev 6 MB96350 Series ■ ORDERING INFORMATION MCU with CAN controller Part number Flash/ROM MB96F353RSA PMC-GSE2 *1 MB96F353RWA PMC-GSE2 *1 MB96F353RWA PMC1-GSE2 Flash A (96KB) *1 *1 MB96F355RSA PMC1-GSE2 *1 MB96F355RWA PMC1-GSE2 Flash A (160KB) *1 MB96F356YWB PMC-GSE2 64 pins Plastic LQFP (FPT-64P-M23) No Yes Flash A (288KB) No MB96F356RSB PMC1-GSE2 MB96F356YWB PMC1-GSE2 Yes MB96F356RWB PMC1-GSE2 MB96V300BRB-ES (for evaluation) No Yes No MB96F356RSB PMC-GSE2 MB96F356YSB PMC1-GSE2 64 pins Plastic LQFP (FPT-64P-M24) 64 pins Plastic LQFP (FPT-64P-M24) Yes MB96F356YSB PMC-GSE2 MB96F356RWB PMC-GSE2 No No Emulated by ext. RAM Yes Package 64 pins Plastic LQFP (FPT-64P-M23) Yes Yes MB96F355RSA PMC-GSE2 *1 MB96F355RWA PMC-GSE2 Persistent Low Voltage Reset No *1 MB96F353RSA PMC1-GSE2 Subclock Yes No Yes 64 pins Plastic LQFP (FPT-64P-M23) No Yes No Yes 64 pins Plastic LQFP (FPT-64P-M24) No No 416 pin Plastic BGA (BGA-416P-M02) *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. FME-MB96350 rev 6 97 MB96350 Series MCU without CAN controller Part number Flash/ROM MB96F353ASA PMC-GSE2 *1 MB96F353AWA PMC-GSE2 MB96F353ASA PMC1-GSE2 Flash A (96KB) No Yes MB96F355ASA PMC-GSE2 *1 No *1 MB96F355ASA PMC1-GSE2 *1 Flash A (160KB) Yes No MB96F355AWA PMC1-GSE2 *1 Yes MB96F356ASB PMC-GSE2 No MB96F356AWB PMC-GSE2 MB96F356ASB PMC1-GSE2 MB96F356AWB PMC1-GSE2 Flash A (288KB) Package 64 pins Plastic LQFP (FPT-64P-M23) Yes MB96F353AWA PMC1-GSE2 *1 MB96F355AWA PMC-GSE2 Persistent Low Voltage Reset No *1 *1 Subclock 64 pins Plastic LQFP (FPT-64P-M24) 64 pins Plastic LQFP (FPT-64P-M23) No Yes No Yes 64 pins Plastic LQFP (FPT-64P-M24) 64 pins Plastic LQFP (FPT-64P-M23) 64 pins Plastic LQFP (FPT-64P-M24) *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. This datasheet is also valid for the following outdated devices: MB96F356YSA, MB96F356RSA, MB96F356YWA, MB96F356RWA, MB96F356ASA, MB96F356AWA 98 FME-MB96350 rev 6 MB96350 Series ■ REVISION HISTORY Revision Date Modification Prelim 1 2007-05-03 Creation Prelim 2 2007-05-25 Electrical characteristics update Prelim 3 2007-11-27 Package description is removed from cover page. Typos corrections in product lineup. Product option details added Electrical characteristics update Update of the block diagram Update of the IO map Pin circuit type, LVD characteristics and example characteristics chapters added Prelim 4 2007-12-20 Update of the block diagram: external bus address lines, clock output function pins, AVRL removed from ADC block, relayout. RAMSTART value is corrected IO map regenerated Memory map and Flash configuration reworked Few typos corrected accross the document. Flash bank renaming. Ordering information: package type corrected. IO circuit drawings modified. Prelim 5 2008-02-04 • • • • • • • • • • • • • • • • FME-MB96350 rev 6 Reload Timer RLT 6 for PPGs added Block diagram corrected: ICU2 deleted, TTG2,3 deleted, TTG8,9 added Pin function description corrected with all existing pin types I/O circuit type diagrams corrected Memory map cleaned up "Flash sector configuration" replaced by corrected "User ROM Memory map for Flash devices" Parallel Flash programming spec removed IO map table regenerated: - Port register: Naming style corrected - Memory control registers renamed (Main -> A) - addresses after 000BFFh removed Handling devices: AD converter items added Absolute maximum ratings: Pd and Ta specified more precisely Run and Sleep mode currents: more conditions added (1WS settings) Run mode current spec in 48/24MHz mode corrected Maximum CLKS1 frequency corrected at 1.8V External bus timings: missing conditions added and readability improved Ordering information updated Typos and formatting corrected 99 MB96350 Series Revision Date Modification 6 2009-01-09 • Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly style changes and official notes and disclaimer added) • Numbering of Electrical Characteristics subchapters automated • CANless devices added (MB96F356A) • I/O map: Added node about reserved registers • Serial programming interface: Note about handshaking pins improved • specified AD converter channel offset to 4LSB • package code of MB96V300 corrected in ordering information • Added voltage condition to pull-up resistance spec • Ordering information: column “Flash/ROM” added, column “Remarks” removed • Official package dimension drawing with additional notes added • Empty pages removed • Handling devices: Notes added about Serial communication and about using ceramic resonators. • Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For resonators, maximum frequency depends on Q-factor • AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz • VOL3 spec improved: spec valid for 3mA load for full Vcc range • MB96F353/F355 added (under development) • Free running timer (I/O Timer) 2 and 3 added (without clock input pin) • Input capture ICU9 and ICU10 added (without input pin, only for LIN USART) • C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted • “Preliminary” watermark removed 100 FME-MB96350 rev 6 MB96350 Series FME-MB96350 rev 6 101 MB96350 Series FME-MB96350 rev 6 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Yan An Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. 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