MB96F395RWAPMC-GSE2

FUJITSU SEMICONDUCTOR DATA SHEET FME-MB96390 rev 1 16-bit Proprietary Microcontroller CMOS F2MC-16FX MB96390 Series Y MB96F395*1 AR ■ DESCRIPTION MB96390 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. IM IN For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 40MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 25ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. PR EL *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. 2008-4-18 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 2 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ FEATURES Feature Description Technology • 0.18µm CMOS • F2MC-16FX CPU • Up to 40 MHz internal, 25 ns instruction cycle time • 8-byte instruction execution queue Y • Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) CPU AR • Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available • On-chip PLL clock multiplier (x1..25, x1 when PLL stop) • 3-16 MHz external quartz clock • Up to 40 MHz external clock • 32-100 kHz subsystem quartz clock • 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog IN System clock • Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. IM • Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) • Clock modulator On-chip voltage regula- • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI tor and low power consumption figures Code Security Memory Patch Function • Reset is generated when supply voltage is below minimum. EL Low voltage reset • Protects ROM content from unintended read-out • Replaces ROM content • Can also be used to implement embedded debug support • Fast Interrupt processing • 8 programmable priority levels PR Interrupts • Non-Maskable Interrupt (NMI) Timers • Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) • Watchdog Timer 2008-4-18 3 MB96390 Series FME-MB96390 rev 1 Feature Description • Supports CAN protocol version 2.0 part A and B • ISO16845 certified • Bit rates up to 1 Mbit/s • 32 message objects CAN • Each message object has its own identifier mask Y • Programmable FIFO mode (concatenation of message objects) • Maskable interrupt • Disabled Automatic Retransmission mode for Time Triggered CAN applications • Full duplex USARTs (SCI/LIN) USART AR • Programmable loop-back mode for self-test operation • Wide range of baud rate settings using a dedicated reload timer • Special synchronous options for adapting to different synchronous serial protocols • LIN functionality working either as master or slave LIN device • Up to 400 kbit/s IN I2C • Master and Slave functionality, 8-bit and 10-bit addressing • SAR-type A/D converter • 10-bit resolution • 16-bit wide Reload Timers IM • Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer • Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency Free Running Timers EL • Event count function • Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency • 16-bit wide • Signals an interrupt upon external event PR Input Capture Units • Rising edge, falling edge or rising & falling edge sensitive • 16-bit wide Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs • A pair of compare registers can be used to generate an output signal. • 16-bit down counter, cycle and duty setting registers • Interrupt at trigger, counter borrow and/or duty match Programmable Pulse Generator • PWM operation and one-shot operation • Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow as clock input • Can be triggered by software or reload timer 4 2008-4-18 MB96390 Series FME-MB96390 rev 1 Feature Description • Stepper Motor Controller with integrated high current output drivers • Four high current outputs for each channel Stepper Motor Control- • Two synchronized 8/10-bit PWMs per channel ler • Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock • Separate power supply for high current output drivers • Internal or external voltage generation Y • LCD controller with up to 4 COM × SEG • Fixed 1/3 bias • Programmable frame period AR • Duty cycle: Selectable from options: 1/2, 1/3 and 1/4 • Clock source selectable from three options (peripheral clock, subclock or RC oscillator clock) LCD Controller • On-chip drivers for internal divider resistors or external divider resistors IN • On-chip data memory for display • LCD display can be operated in Timer Mode • Blank display: selectable IM • All SEG, COM and V pins can be switched between general and specialized purposes • External divided resistors can be also used to shut off the current when LCD is deactivated • 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter • PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock EL Sound Generator • Tone frequency: PWM frequency / 2 / (reload value + 1) • Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the RC oscillator PR Real Time Clock • Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) • Read/write accessible second/minute/hour registers • Can signal interrupts every half second/second/minute/hour/day • Internal clock divider and prescaler provide exact 1s clock • Edge sensitive or level sensitive External Interrupts • Interrupt mask and pending bit per channel • Each available CAN channel RX has an external interrupt for wake-up • Selected USART channels SIN have an external interrupt for wake-up 2008-4-18 5 MB96390 Series FME-MB96390 rev 1 Feature Description • Disabled after reset Non Maskable Interrupt • Once enabled, can not be disabled other than by reset. • Level high or level low sensitive • Pin shared with external interrupt 0. • Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds • Threshold voltages defined externally or generated internally Y Alarm comparator • Status is readable, interrupts can be masked separately AR • Virtually all external pins can be used as general purpose I/O • All push-pull outputs (except when used as I2C SDA/SCL line) • Bit-wise programmable as input/output or peripheral signal I/O Ports • Bit-wise programmable input enable • Bit-wise programmable input levels (Automotive / CMOS-Schmitt trigger / TTL) IN • Bit-wise programmable pull-up resistor • Bit-wise programmable output driving strength for EMI optimization Packages • 100-pin plastic LQFP • Supports automatic programming, Embedded AlgorithmTM*1 IM • Write/Erase/Erase-Suspend/Resume commands • A flag indicating completion of the algorithm • Number of erase cycles: 10,000 times Flash Memory • Data retention time: 20 years EL • Erase can be performed on each sector individually • Sector protection • Flash Security feature to protect the content of the Flash • Low voltage detection during Flash erase 6 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. PR *1 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ PRODUCT LINEUP Features MB96V300B MB9639x Product type Evaluation sample Flash product: MB96F39x Mask ROM product: MB9639x Y Product options YS LVD persistently on / Single clock devices RS LVD can be disabled / Single clock devices AR NA YW LVD persistently on / Dual clock devices RW LVD can be disabled / Dual clock devices RAM 160kB 5kB ROM/Flash memory emulation by external RAM, 92kB internal RAM IN Flash/ROM MB96F395Y*1, MB96F395R*1, Package BGA416 DMA 16 channels USART 10 channels 3 channels I2C 2 channels 1 channel A/D Converter 40 channels 11 channels 0 channels IM EL A/D Converter Reference Voltage switch FPT-100P-M20 yes No 6 channels + 1 channel (for PPG) 4 channels + 1 channel (for PPG) 4 channels 2 channels 12 channels 4 channels 16-bit Input Capture 12 channels 4 channels 16-bit Programmable Pulse Generator 20 channels 4 channels CAN Interface 5 channels 1 channels Stepping Motor Controller 6 channels 4 channels External Interrupts 16 channels 8 channels 16-bit Reload Timer 16-bit Free-Running Timer PR 16-bit Output Compare Non-Maskable Interrupt 1 channel Sound generator 2 channels 1 channels LCD Controller 4 COM x 72 SEG 4 COM x 49 SEG 2008-4-18 7 MB96390 Series Features FME-MB96390 rev 1 MB96V300B MB9639x Real Time Clock 1 I/O Ports 136 74 for part number with suffix "W", 76 for part number with suffix "S" Alarm comparator 2 channels 1 channels External bus interface Yes No 2 channels Low voltage reset Yes On-chip RC-oscillator Yes AR Y Clock output function PR EL IM IN *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. 8 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ BLOCK DIAGRAMS Block diagram of MB96F39x CKOT0_R, CKOT1, CKOT1_R CKOTX0, CKOTX1, CKOTX1_R X0, X1 X0A, X1A RSTX MD0...MD2 Memory Patch Unit Flash Memory A AR Interrupt Controller 16FX CPU Y NMI Clock & Mode Controller 16FX Core Bus (CLKB) Peripheral Bus Bridge FRCK0 FRCK0_R IN0 IN0_R,IN1_R OUT0 ... OUT3 OUT0_R,OUT2_R FRCK1 IN6,IN7 IN7_R INT0 ... INT7 INT1_R ... INT7_R V0 ... V3 COM0 ... COM3 SEG0 ... SEG64 (Except 5,6,8,9,10, 29,31,32,34,35,48 49,50,54,58,62) 2008-4-18 16-bit Reload Timer 4 ch. I/O Timer 0 ICU 0/1 OCU 0/1/2/3 I/O Timer 1 ICU 6/7 External Interrupt LCD controller/ driver RAM IN IM TIN0, TIN1 TIN2, TIN3 TOT0, TOT1 TOT2, TOT3 10-bit ADC 11 ch. EL AVCC AVSS AVRH AVRL/AVRH2 AN2,3,4,6,7,8,10 AN11,12,14,15 ADTG I2C 1 ch. Peripheral Bus 1 (CLKP1) SCL0 PR SDA0 Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) Watchdog USART 3 ch. Alarm Comparator 1 ch. 16-bit PPG 4 ch. RLT6 Stepper Motor Controller 4 ch. Real Time Clock Boot ROM Voltage Regulator VCC VSS C CAN Interface 1 ch. Sound Generator 1 ch. TX0 RX0 SGO0 SGA0 SIN0...SIN2 SOT0...SOT2 SCK0...SCK2 ALARM0 TTG0,TTG2,TTG3 PPG0,PPG1,PPG3 PPG0_R ... PPG3_R PWM1M0 ... PWM1M2,PWM1M4 PWM1P0 ... PWM1P2,PWM1P4 PWM2M0 ... PWM2M2,PWM2M4 PWM2P0 ... PWM2P2,PWM2P4 DVCC DVSS WOT 9 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 10 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ PIN ASSIGNMENTS 84 P01_7/CKOTX1_R/SEG27 P02_0/CKOT1_R/SEG28 P02_2/CKOT0_R/IN7_R/SEG30 P02_5/OUT0_R/SEG33 89 P03_0/V0/SEG36 P03_1/V1/SEG37 P03_2/V2/SEG38 P03_3/V3/SEG39 P03_4/INT4/RX0 P03_5/TX0 P03_6/NMI/INT0 Vcc 93 Y P09_3/PWM2M2 42 P09_2/PWM2P2 P09_1/PWM1M2 47 46 81 45 IN 82 83 LQFP - 100 85 86 87 41 40 39 Package code (mold) FPT-100P-M20 88 38 37 36 IM 90 91 92 94 95 96 97 EL 98 100 43 48 80 99 44 Vcc P10_3/PWM2M4 P10_2/PWM2P4/SCK2 P10_1/PWM1M4/SOT2/TOT3 P10_0/PWM1P4/SIN2/TIN3 DVss DVcc 50 49 2 3 4 5 6 7 8 PR 34 33 32 31 30 29 P08_5/PWM1M1 DVss DVcc P08_4/PWM1P1 P08_3/PWM2M0 P08_2/PWM2P0 P08_1/PWM1M0 P08_0/PWM1P0 P05_7/AN15/TOT2/SEG64 27 P05_6/AN14/TIN2/SEG63 P05_4/AN12/INT2_R/SEG61 26 Vss 28 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Vss C P03_7/INT1/SIN1/SEG40 P13_0/INT2/SOT1/SEG41 P13_1/INT3/SCK1/SEG42 P13_2/PPG0/TIN0/FRCK1/SEG43 P13_3/PPG1/TOT0/WOT/SEG44 P13_4/SIN0/INT6/SEG45 P13_5/SOT0/ADTG/INT7/SEG46 P13_6/SCK0/CKOTX0/SEG47 P04_4/PPG3/SDA0 P04_5/SCL0 P06_2/AN2/INT5/SEG51 P06_3/AN3/FRCK0/SEG52 1 35 P09_0/PWM1P2 P08_7/PWM2M1 P08_6/PWM2P1 P05_3/AN11/OUT3/SEG60 Vcc P01_2/OUT1/CKOTX1/SEG22 P01_3/SEG23 P01_4/SEG24 P01_5/SEG25 P01_6/SEG26 78 P05_2/AN10/OUT2/SEG59 79 AR P00_5/TTG2/IN6/SEG17 P00_6/TTG3/IN7/SEG18 P00_7/SGO0/SEG19 P01_0/SGA0/SEG20 P01_1/OUT0/CKOT1/SEG21 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 77 AVRL/AVRH2 AVss P05_0/AN8/ALARM0/SEG57 76 P06_4/AN4/IN0/TTG0/SEG53 P06_6/AN6/TIN1/SEG55 P06_7/AN7/TOT1/SEG56 AVcc AVRH Vss P00_3/INT6_R/SEG15 P00_4/INT7_R/SEG16 P00_1/INT4_R/SEG13 P00_0/INT3_R/SEG12 P12_7/INT1_R/SEG11 P12_3/OUT2_R/SEG7 P12_0/IN1_R/SEG4 P11_7/IN0_R/SEG3 P11_6/FRCK0_R/SEG2 P11_5/SEG1 P11_4/PPG3_R/SEG0 P11_3/PPG2_R/COM3 P11_2/PPG1_R/COM2 P11_1/PPG0_R/COM1 P11_0/COM0 RSTX X1A/P04_1 1) X0A/P04_0 1) Vss X1 X0 MD2 MD1 MD0 Vss Vcc P00_2/INT5_R/SEG14 Pin assignment of MB96F39x 1) Devices with suffix W: X0A/X1A Devices with suffix S: P04_0, P04_1 (FPT-100P-M20) 2008-4-18 11 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 12 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ PIN FUNCTION DESCRIPTION Pin Function description (1 / 2) Feature Description ADTG ADC A/D converter trigger input ALARMn Alarm comparator Alarm Comparator n input ANn ADC A/D converter channel n input AVCC Supply Analog circuits power supply AVRH ADC A/D converter high reference voltage input AVSS Supply C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock output function Clock Output function n output CKOTn_R Clock output function CKOTXn Clock output function CKOTXn_R Clock output function COMn LCD DVCC Supply FRCKn Free Running Timer Free Running Timer n input FRCKn_R Free Running Timer Relocated Free Running Timer n input INn ICU Input Capture Unit n input INn_R ICU Relocated Input Capture Unit n input INTn External Interrupt External Interrupt n input INTn_R External Interrupt Relocated External Interrupt n input MDn Core Input pins for specifying the operating mode. AR Analog circuits power supply Relocated Clock Output function n output IN Clock Output function n inverted output Relocated Clock Output function n inverted output IM EL PR NMI Y Pin name LCD COM pins SMC pins power supply External Interrupt Non-Maskable Interrupt input OCU Output Compare Unit n waveform output OCU Relocated Output Compare Unit n waveform output GPIO General purpose IO PPG Programmable Pulse Generator n output PPGn_R PPG Relocated Programmable Pulse Generator n output PWMn SMC SMC PWM high current RSTX Core Reset input RXn CAN CAN interface n RX input OUTn OUTn_R Pxx_n PPGn 2008-4-18 13 MB96390 Series FME-MB96390 rev 1 Pin Function description (2 / 2) Feature Description SCKn USART USART n serial clock input/output SCLn I2C I2C interface n clock I/O input/output SDAn I2C I2C interface n serial data I/O input/output SEGn LCD LCD segment n SGA Sound Generator SG amplitude output SGO Sound Generator SG sound/tone output SINn USART SOTn USART TINn Reload Timer TOTn Reload Timer TTGn PPG TXn CAN Vn LCD VCC Supply VSS Supply WOT RTC X0 Clock X0A Clock X1 Clock X1A Clock AR Y Pin name USART n serial data input USART n serial data output Reload Timer n event input Reload Timer n output IN Programmable Pulse Generator n trigger input CAN interface n TX output EL IM LCD voltage references Power supply Power supply Real Timer clock output Oscillator input Subclock Oscillator input (only for devices with suffix "W") Oscillator output PR Subclock Oscillator output (only for devices with suffix "W") 14 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ PIN CIRCUIT TYPE F 3 to 10 J 11,12 N 13 to 17 K 18 Supply 19 to 20 G 21 Supply 22 to 24 K 25,26 Supply 27 to 29 K 30 to 34 M 35,36 Supply 37 to 43 M 44,45 Supply 46 to 49 M 50, 51 Supply 52 to 54 C 55, 56 A 57 Supply 58,59 B1) 58,59 H2) 60 E 61 to 74 J 75 to 76 Supply 1) 2) AR 2 IN Supply IM 1 EL Circuit type PR Pin no. Y FPT-100P-M20 Devices with suffix ”W” Devices without suffix ”W” 2008-4-18 15 MB96390 Series FME-MB96390 rev 1 Pin no. Circuit type 77 to 92 J 93 to 96 L 97 to 99 H 100 Supply Devices with suffix ”W” Devices without suffix ”W” PR EL IM IN 2) AR 1) Y FPT-100P-M20 16 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ I/O CIRCUIT TYPE Circuit Remarks A X1 R 0 1 FCI R X0 IN FCI or osc disable AR Xout MRFBE High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Programmable feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode Y Type B Xout X1A IM R Low-speed oscillation circuit: • Programmable feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled EL SRFBE R X0A osc disable PR C R E Hysteresis inputs • Mask ROM and EVA device: CMOS Hysteresis input pin • Flash device: CMOS input pin • CMOS Hysteresis input pin • Pull-up resistor value: approx. 50 kΩ Pull-up Resistor R 2008-4-18 Hysteresis inputs 17 MB96390 Series Type FME-MB96390 rev 1 Circuit Remarks • Power supply input protection circuit G • A/D converter ref+ (AVRH/AVRH2) power supply input pin with protection circuit • Flash devices do not have a protection circuit against VCC for pins AVRH/AVRH2 • Devices without AVRH reference switch do not have an analog switch for the AVRL pin Y F AR ANE AVR ANE pull-up control IM Pout Nout R Hysteresis input Standby control for input shutdown Hysteresis input Automotive input TTL input PR Standby control for input shutdown EL Standby control for input shutdown Standby control for input shutdown • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. IN H 18 2008-4-18 MB96390 Series Circuit Remarks J • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. • SEG or COM output pull-up control Pout Nout Y Type FME-MB96390 rev 1 R Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input IN AR Standby control for input shutdown SEG, COM output IM K pull-up control EL Pout Nout R PR Standby control for input shutdown • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function. • Programmable pull-up resistor: 50kΩ approx. • Analog input • SEG output Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Analog input SEG output 2008-4-18 19 MB96390 Series Type FME-MB96390 rev 1 Circuit Remarks L • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. • Analog input • Vx input • SEG output pull-up control Pout Y Nout Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input IN Standby control for input shutdown AR R Analog input SEG output IM Vx input M EL pull-up control Pout Nout R PR Standby control for input shutdown 20 • CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL = 30mA, IOH = -30mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input 2008-4-18 MB96390 Series Circuit Remarks N • CMOS level output (IOL = 3mA, IOH = -3mA) • 2 different CMOS hysteresis inputs with input shutdown function • Automotive input with input shutdown function • TTL input with input shutdown function • Programmable pull-up resistor: 50kΩ approx. pull-up control Pout Nout R Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input PR EL IM IN AR Standby control for input shutdown Y Type FME-MB96390 rev 1 2008-4-18 21 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 22 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ MEMORY MAP MB96V300B MB96F90x Emulation ROM USER ROM / Reserved*4 External Bus Reserved FF:FFFFH AR Y DE:0000H 10:0000H 0F:E000H Boot-ROM Boot-ROM Reserved 0E:0000H IN External RAM 02:0000H 01:0000H IM Internal RAM bank 1 ROM/RAM MIRROR 00:8000H RAMSTART0*3 00:0C00H RAMSTART0 EL Internal RAM bank 0 PR 00:0180H 00:0100H 00:00F0H 00:0000H ROM/RAM MIRROR *2 Internal RAM bank 0 Reserved External Bus Peripherals 00:0380H Reserved Peripherals GPR*1 GPR*1 DMA Reserved External Bus Reserved Peripheral Peripheral *1: Unused GPR banks can be used as RAM area *2: For RAMSTART0 addresses, please refer to the table on the next page. *3: For EVA device, RAMSTART0 depends on the configuration of the emulated device. *4: For details about USER ROM area, see the USER ROM MEMORY MAP on the following pages. The DMA area is only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. 2008-4-18 23 MB96390 Series FME-MB96390 rev 1 ■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES Bank 0 RAM size RAMSTART0 MB96F395 5kB 00:6E40H PR EL IM IN AR Y Devices 24 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ USER ROM MEMORY MAP FOR FLASH DEVICES MB96F395R MB96F395Y E0:0000H DF:FFFFH DE:0000H 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H Reserved SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 EL DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH S39 - 64K S38 - 64K Y 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H AR FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH Flash size 160kByte IN Flash memory mode address IM Alternative mode CPU address Reserved PR *1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH 2008-4-18 25 MB96390 Series FME-MB96390 rev 1 ■ SERIAL PROGRAMMING COMMUNICATION INTERFACE USART pins for Flash serial programming (MD[2:0] = 010, Serial Communication mode) MB96F39x Pin number USART Number Normal function LQFP-100 SOT0 10 SCK0 3 SIN1 4 USART1 SOT1 5 SCK1 46 SIN2 47 48 USART2 Y USART0 AR 9 SIN0 SOT2 SCK2 IN 8 PR EL IM Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor to support at least port P00_1 on pin 88. If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. 26 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ I/O MAP I/O map MB96F39x (1 / 28) Address Abbreviation 8-bit access Register Abbreviation 16-bit access Access I/O Port P00 - Port Data Register PDR00 RW 000001H I/O Port P01 - Port Data Register PDR01 RW 000002H I/O Port P02 - Port Data Register PDR02 RW 000003H I/O Port P03 - Port Data Register PDR03 RW 000004H I/O Port P04 - Port Data Register PDR04 RW 000005H I/O Port P05 - Port Data Register PDR05 RW 000006H I/O Port P06 - Port Data Register PDR06 RW 000007H Reserved 000008H I/O Port P08 - Port Data Register 000009H I/O Port P09 - Port Data Register 00000AH I/O Port P10 - Port Data Register 00000BH I/O Port P11 - Port Data Register 00000CH AR Y 000000H RW PDR09 RW PDR10 RW PDR11 RW I/O Port P12 - Port Data Register PDR12 RW 00000DH I/O Port P13 - Port Data Register PDR13 RW 00000EH000017H Reserved 000018H ADC0 - Control Status register Low ADCSL 000019H ADC0 - Control Status register High ADCSH 00001AH ADC0 - Data Register Low ADCRL 00001BH ADC0 - Data Register High ADCRH 00001CH ADC0 - Setting Register 00001DH ADC0 - Setting Register 00001EH ADC0 - Extended Configuration Register 00001FH Reserved 000020H FRT0 - Data register of free-running timer 000021H FRT0 - Data register of free-running timer 000022H FRT0 - Control status register of free-running timer Low TCCSL0 000023H FRT0 - Control status register of free-running timer High TCCSH0 2008-4-18 PR EL IM IN PDR08 ADCS RW RW ADCR R R ADSR RW RW ADECR RW TCDT0 RW RW TCCS0 RW RW 27 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (2 / 28) Address 28 Abbreviation 8-bit access Register Abbreviation 16-bit access Access TCDT1 RW 000024H FRT1 - Data register of free-running timer 000025H FRT1 - Data register of free-running timer 000026H FRT1 - Control status register of free-running timer Low TCCSL1 000027H FRT1 - Control status register of free-running timer High TCCSH1 RW 000028H OCU0 - Output Compare Control Status OCS0 RW 000029H OCU1 - Output Compare Control Status OCS1 RW 00002AH OCU0 - Compare Register 00002BH OCU0 - Compare Register 00002CH OCU1 - Compare Register 00002DH OCU1 - Compare Register 00002EH OCU2 - Output Compare Control Status 00002FH OCU3 - Output Compare Control Status 000030H OCU2 - Compare Register 000031H OCU2 - Compare Register 000032H OCU3 - Compare Register 000033H OCU3 - Compare Register 000034H00003FH Reserved 000040H ICU0/ICU1 - Control Status Register ICS01 RW 000041H ICU0/ICU1 - Edge register ICE01 RW 000042H ICU0 - Capture Register Low IPCPL0 000043H ICU0 - Capture Register High IPCPH0 000044H ICU1 - Capture Register Low IPCPL1 000045H ICU1 - Capture Register High IPCPH1 R 000046H ICU2/ICU3 - Control Status Register ICS23 RW 000047H ICU2/ICU3 - Edge register ICE23 RW 000048H ICU2 - Capture Register Low IPCPL2 000049H ICU2 - Capture Register High IPCPH2 00004AH ICU3 - Capture Register Low IPCPL3 OCCP0 RW RW RW OCCP1 IN AR Y TCCS1 RW RW OCS2 RW OCS3 RW IM EL PR RW OCCP2 RW RW OCCP3 RW RW - IPCP0 R R IPCP1 IPCP2 R R R IPCP3 R 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (3 / 28) Address Register 00004BH ICU3 - Capture Register High 00004CH Abbreviation 8-bit access Abbreviation 16-bit access Access IPCPH3 R ICU4/ICU5 - Control Status Register ICS45 RW 00004DH ICU4/ICU5 - Edge register ICE45 RW 00004EH ICU4 - Capture Register Low 00004FH ICU4 - Capture Register High 000050H ICU5 - Capture Register Low 000051H ICU5 - Capture Register High 000052H ICU6/ICU7 - Control Status Register 000053H ICU6/ICU7 - Edge register 000054H ICU6 - Capture Register Low 000055H ICU6 - Capture Register High 000056H ICU7 - Capture Register Low 000057H ICU7 - Capture Register High 000058H Y IPCPL4 IPCP4 IPCPH4 AR IPCPL5 R IPCP5 R IPCPH5 R ICS67 RW ICE67 RW IPCPL6 IN R IPCP6 IPCPH6 IPCPL7 R R IPCP7 R R EXTINT0 - External Interrupt Enable Register ENIR0 RW 000059H EXTINT0 - External Interrupt Interrupt request Register EIRR0 RW 00005AH EXTINT0 - External Interrupt Level Select Low ELVRL0 00005BH EXTINT0 - External Interrupt Level Select High ELVRH0 00005CH00005FH Reserved 000060H RLT0 - Timer Control Status Register Low TMCSRL0 000061H RLT0 - Timer Control Status Register High TMCSRH0 000062H RLT0 - Reload Register - for writing TMRLR0 W 000062H RLT0 - Reload Register - for reading TMR0 R 000063H RLT0 - Reload Register - for writing W 000063H RLT0 - Reload Register - for reading R 000064H RLT1 - Timer Control Status Register Low TMCSRL1 000065H RLT1 - Timer Control Status Register High TMCSRH1 000066H RLT1 - Reload Register - for writing TMRLR1 W 000066H RLT1 - Reload Register - for reading TMR1 R 000067H RLT1 - Reload Register - for writing 2008-4-18 PR EL IM IPCPH7 ELVR0 RW RW - TMCSR0 RW RW TMCSR1 RW RW W 29 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (4 / 28) Address 30 Abbreviation 8-bit access Register Abbreviation 16-bit access Access 000067H RLT1 - Reload Register - for reading R 000068H RLT2 - Timer Control Status Register Low TMCSRL2 000069H RLT2 - Timer Control Status Register High TMCSRH2 00006AH RLT2 - Reload Register - for writing 00006AH RLT2 - Reload Register - for reading 00006BH RLT2 - Reload Register - for writing 00006BH RLT2 - Reload Register - for reading 00006CH RLT3 - Timer Control Status Register Low 00006DH RLT3 - Timer Control Status Register High 00006EH RLT3 - Reload Register - for writing 00006EH RLT3 - Reload Register - for reading 00006FH RLT3 - Reload Register - for writing 00006FH RLT3 - Reload Register - for reading 000070H RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) TMCSRL6 000071H RLT6 - Timer Control Status Register High (dedic. RLT for PPG) TMCSRH6 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for writing TMRLR6 W 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for reading TMR6 R 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for writing 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for reading 000074H PPG3-PPG0 - General Control register 1 Low GCN1L0 000075H PPG3-PPG0 - General Control register 1 High GCN1H0 000076H PPG3-PPG0 - General Control register 2 Low GCN2L0 000077H PPG3-PPG0 - General Control register 2 High GCN2H0 000078H PPG0 - Timer register 000079H PPG0 - Timer register 00007AH PPG0 - Period setting register TMCSR2 RW TMRLR2 W TMR2 R Y AR TMCSRL3 IN IM W R TMCSR3 TMCSRH3 EL PR RW RW RW TMRLR3 W TMR3 R W R TMCSR6 RW RW W R GCN10 RW RW GCN20 RW RW PTMR0 R R PCSR0 W 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (5 / 28) Abbreviation 8-bit access Address Register 00007BH PPG0 - Period setting register 00007CH PPG0 - Duty cycle register 00007DH PPG0 - Duty cycle register 00007EH PPG0 - Control status register Low 00007FH PPG0 - Control status register High 000080H PPG1 - Timer register 000081H PPG1 - Timer register 000082H PPG1 - Period setting register 000083H PPG1 - Period setting register 000084H PPG1 - Duty cycle register 000085H PPG1 - Duty cycle register 000086H PPG1 - Control status register Low PCNL1 000087H PPG1 - Control status register High PCNH1 000088H PPG2 - Timer register 000089H PPG2 - Timer register 00008AH PPG2 - Period setting register 00008BH PPG2 - Period setting register 00008CH PPG2 - Duty cycle register 00008DH PPG2 - Duty cycle register 00008EH PPG2 - Control status register Low PCNL2 00008FH PPG2 - Control status register High PCNH2 000090H PPG3 - Timer register 000091H PPG3 - Timer register 000092H PPG3 - Period setting register 000093H PPG3 - Period setting register 000094H PPG3 - Duty cycle register 000095H PPG3 - Duty cycle register 000096H PPG3 - Control status register Low PCNL3 000097H PPG3 - Control status register High PCNH3 000098H PPG7-PPG4 - General Control register 1 Low GCN1L1 2008-4-18 Abbreviation 16-bit access Access W PDUT0 W W Y PCNL0 PCN0 PTMR1 R R PCSR1 W W PDUT1 W W PCN1 RW RW R R PCSR2 W W PDUT2 W W PR EL RW PTMR2 IM IN AR PCNH0 RW PCN2 RW RW PTMR3 R R PCSR3 W W PDUT3 W W PCN3 RW RW GCN11 RW 31 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (6 / 28) Address 32 Abbreviation 8-bit access Register Abbreviation 16-bit access Access 000099H PPG7-PPG4 - General Control register 1 High GCN1H1 RW 00009AH PPG7-PPG4 - General Control register 2 Low GCN2L1 00009BH PPG7-PPG4 - General Control register 2 High GCN2H1 00009CH PPG4 - Timer register 00009DH PPG4 - Timer register 00009EH PPG4 - Period setting register 00009FH PPG4 - Period setting register 0000A0H PPG4 - Duty cycle register 0000A1H PPG4 - Duty cycle register 0000A2H PPG4 - Control status register Low 0000A3H PPG4 - Control status register High 0000A4H PPG5 - Timer register 0000A5H PPG5 - Timer register 0000A6H PPG5 - Period setting register 0000A7H PPG5 - Period setting register 0000A8H PPG5 - Duty cycle register 0000A9H PPG5 - Duty cycle register 0000AAH PPG5 - Control status register Low PCNL5 0000ABH PPG5 - Control status register High PCNH5 RW 0000ACH I2C0 - Bus Status Register IBSR0 R 0000ADH I2C0 - Bus Control Register IBCR0 RW 0000AEH I2C0 - Ten bit Slave address Register Low ITBAL0 0000AFH I2C0 - Ten bit Slave address Register High ITBAH0 0000B0H I2C0 - Ten bit Address mask Register Low ITMKL0 0000B1H I2C0 - Ten bit Address mask Register High ITMKH0 RW 0000B2H I2C0 - Seven bit Slave address Register ISBA0 RW 0000B3H I2C0 - Seven bit Address mask Register ISMK0 RW 0000B4H I2C0 - Data Register IDAR0 RW 0000B5H I2C0 - Clock Control Register ICCR0 RW GCN21 RW Y PTMR4 AR PCSR4 IN PCNL4 R R W W PDUT4 W W PCN4 PCNH4 IM EL PR RW RW RW PTMR5 R R PCSR5 W W PDUT5 W W PCN5 ITBA0 RW RW RW ITMK0 RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (7 / 28) Address Abbreviation 8-bit access Register Abbreviation 16-bit access Access 0000B6H0000BFH Reserved 0000C0H USART0 - Serial Mode Register SMR0 RW 0000C1H USART0 - Serial Control Register SCR0 RW 0000C2H USART0 - TX Register 0000C2H USART0 - RX Register 0000C3H USART0 - Serial Status 0000C4H USART0 - Control/Com. Register 0000C5H USART0 - Ext. Status Register 0000C6H USART0 - Baud Rate Generator Register Low BGRL0 0000C7H USART0 - Baud Rate Generator Register High BGRH0 RW 0000C8H USART0 - Extended Serial Interrupt Register ESIR0 RW 0000C9H Reserved 0000CAH USART1 - Serial Mode Register 0000CBH Y - W RDR0 R IN AR TDR0 SSR0 RW ECCR0 RW ESCR0 RW BGR0 RW RW USART1 - Serial Control Register SCR1 RW 0000CCH USART1 - TX Register TDR1 W 0000CCH USART1 - RX Register RDR1 R 0000CDH USART1 - Serial Status SSR1 RW 0000CEH USART1 - Control/Com. Register ECCR1 RW 0000CFH USART1 - Ext. Status Register ESCR1 RW 0000D0H USART1 - Baud Rate Generator Register Low BGRL1 0000D1H USART1 - Baud Rate Generator Register High BGRH1 RW 0000D2H USART1 - Extended Serial Interrupt Register ESIR1 RW 0000D3H Reserved 0000D4H USART2 - Serial Mode Register SMR2 RW 0000D5H USART2 - Serial Control Register SCR2 RW 0000D6H USART2 - TX Register TDR2 W 0000D6H USART2 - RX Register RDR2 R 0000D7H USART2 - Serial Status SSR2 RW 0000D8H USART2 - Control/Com. Register ECCR2 RW 2008-4-18 PR EL IM SMR1 BGR1 RW - 33 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (8 / 28) Address 34 Abbreviation 8-bit access Register Abbreviation 16-bit access Access 0000D9H USART2 - Ext. Status Register ESCR2 RW 0000DAH USART2 - Baud Rate Generator Register Low BGRL2 0000DBH USART2 - Baud Rate Generator Register High BGRH2 RW 0000DCH USART2 - Extended Serial Interrupt Register ESIR2 RW 0000DDH0000EFH Reserved 0000F0H0000FFH External Bus area 000100H DMA0 - Buffer address pointer low byte 000101H DMA0 - Buffer address pointer middle byte 000102H DMA0 - Buffer address pointer high byte 000103H DMA0 - DMA control register 000104H DMA0 - I/O register address pointer low byte IOAL0 000105H DMA0 - I/O register address pointer high byte IOAH0 000106H DMA0 - Data counter low byte 000107H DMA0 - Data counter high byte 000108H AR Y BGR2 RW BAPL0 RW BAPM0 RW BAPH0 RW IN EXTBUS0 DMACS0 DCTL0 RW IOA0 RW RW DCT0 RW RW DMA1 - Buffer address pointer low byte BAPL1 RW 000109H DMA1 - Buffer address pointer middle byte BAPM1 RW 00010AH DMA1 - Buffer address pointer high byte BAPH1 RW 00010BH DMA1 - DMA control register DMACS1 RW 00010CH DMA1 - I/O register address pointer low byte IOAL1 00010DH DMA1 - I/O register address pointer high byte IOAH1 00010EH DMA1 - Data counter low byte DCTL1 00010FH DMA1 - Data counter high byte DCTH1 RW 000110H DMA2 - Buffer address pointer low byte BAPL2 RW 000111H DMA2 - Buffer address pointer middle byte BAPM2 RW 000112H DMA2 - Buffer address pointer high byte BAPH2 RW 000113H DMA2 - DMA control register DMACS2 RW 000114H DMA2 - I/O register address pointer low byte IOAL2 000115H DMA2 - I/O register address pointer high byte IOAH2 000116H DMA2 - Data counter low byte DCTL2 EL DCTH0 PR IM RW IOA1 RW RW DCT1 IOA2 RW RW RW DCT2 RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (9 / 28) Address Abbreviation 8-bit access Register Abbreviation 16-bit access Access DMA2 - Data counter high byte DCTH2 RW 000118H DMA3 - Buffer address pointer low byte BAPL3 RW 000119H DMA3 - Buffer address pointer middle byte BAPM3 RW 00011AH DMA3 - Buffer address pointer high byte BAPH3 RW 00011BH DMA3 - DMA control register 00011CH DMA3 - I/O register address pointer low byte 00011DH DMA3 - I/O register address pointer high byte IOAH3 00011EH DMA3 - Data counter low byte DCTL3 00011FH DMA3 - Data counter high byte 000120H DMA4 - Buffer address pointer low byte 000121H Y 000117H DMACS3 AR IOAL3 RW IOA3 RW RW DCT3 RW RW BAPL4 RW DMA4 - Buffer address pointer middle byte BAPM4 RW 000122H DMA4 - Buffer address pointer high byte BAPH4 RW 000123H DMA4 - DMA control register DMACS4 RW 000124H DMA4 - I/O register address pointer low byte IOAL4 000125H DMA4 - I/O register address pointer high byte IOAH4 000126H DMA4 - Data counter low byte DCTL4 000127H DMA4 - Data counter high byte DCTH4 RW 000128H DMA5 - Buffer address pointer low byte BAPL5 RW 000129H DMA5 - Buffer address pointer middle byte BAPM5 RW 00012AH DMA5 - Buffer address pointer high byte BAPH5 RW 00012BH DMA5 - DMA control register DMACS5 RW 00012CH DMA5 - I/O register address pointer low byte IOAL5 00012DH DMA5 - I/O register address pointer high byte IOAH5 00012EH DMA5 - Data counter low byte DCTL5 00012FH DMA5 - Data counter high byte DCTH5 RW 000130H DMA6 - Buffer address pointer low byte BAPL6 RW 000131H DMA6 - Buffer address pointer middle byte BAPM6 RW 000132H DMA6 - Buffer address pointer high byte BAPH6 RW 000133H DMA6 - DMA control register DMACS6 RW 000134H DMA6 - I/O register address pointer low byte 2008-4-18 PR EL IM IN DCTH3 IOAL6 IOA4 RW RW DCT4 IOA5 RW RW RW DCT5 IOA6 RW RW 35 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (10 / 28) 36 Abbreviation 8-bit access Register Abbreviation 16-bit access Access 000135H DMA6 - I/O register address pointer high byte IOAH6 000136H DMA6 - Data counter low byte DCTL6 000137H DMA6 - Data counter high byte DCTH6 000138H00017FH Reserved 000180H00037FH CPU - General Purpose registers (RAM access) 000380H DMA0 - Interrupt select 000381H DMA1 - Interrupt select 000382H DMA2 - Interrupt select 000383H DMA3 - Interrupt select 000384H DMA4 - Interrupt select 000385H DMA5 - Interrupt select 000386H DMA6 - Interrupt select 000387H00038FH Reserved 000390H DMA - Status register low byte 000391H DMA - Status register high byte 000392H DMA - Stop status register low byte DSSRL 000393H DMA - Stop status register high byte DSSRH 000394H DMA - Enable register low byte DERL 000395H DMA - Enable register high byte DERH 000396H00039FH Reserved 0003A0H Interrupt level register ILR 0003A1H Interrupt index register IDX 0003A2H PR Address RW Interrupt vector table base register Low TBRL 0003A3H Interrupt vector table base register High TBRH RW 0003A4H Delayed Interrupt register DIRR RW 0003A5H Non Maskable Interrupt register NMI RW 0003A6H0003ABH Reserved DCT6 Y RW AR GPR_RAM RW DISEL0 RW DISEL1 RW DISEL2 RW DISEL3 RW IN IM EL RW DISEL4 RW DISEL5 RW DISEL6 RW - DSRL DSR DSRH RW RW DSSR RW RW DER RW RW - ICR RW RW TBR RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (11 / 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access EDSU2 RW EDSU communication interrupt selection Low EDSU2L 0003ADH EDSU communication interrupt selection High EDSU2H RW 0003AEH ROM mirror control register ROMM RW 0003AFH EDSU configuration register EDSU RW 0003B0H Memory patch control/status register ch 0/1 0003B1H Memory patch control/status register ch 0/1 0003B2H Memory patch control/status register ch 2/3 0003B3H Memory patch control/status register ch 2/3 0003B4H Memory patch control/status register ch 4/5 0003B5H Memory patch control/status register ch 4/5 0003B6H Memory patch control/status register ch 6/7 0003B7H Memory patch control/status register ch 6/7 0003B8H Memory Patch function - Patch address 0 low PFAL0 RW 0003B9H Memory Patch function - Patch address 0 middle PFAM0 RW 0003BAH Memory Patch function - Patch address 0 high PFAH0 RW 0003BBH Memory Patch function - Patch address 1 low PFAL1 RW 0003BCH Memory Patch function - Patch address 1 middle PFAM1 RW 0003BDH Memory Patch function - Patch address 1 high PFAH1 RW 0003BEH Memory Patch function - Patch address 2 low PFAL2 RW 0003BFH Memory Patch function - Patch address 2 middle PFAM2 RW 0003C0H Memory Patch function - Patch address 2 high PFAH2 RW 0003C1H Memory Patch function - Patch address 3 low PFAL3 RW 0003C2H Memory Patch function - Patch address 3 middle PFAM3 RW 0003C3H Memory Patch function - Patch address 3 high PFAH3 RW 0003C4H Memory Patch function - Patch address 4 low PFAL4 RW 0003C5H Memory Patch function - Patch address 4 middle PFAM4 RW 0003C6H Memory Patch function - Patch address 4 high PFAH4 RW 0003C7H Memory Patch function - Patch address 5 low PFAL5 RW 0003C8H Memory Patch function - Patch address 5 middle PFAM5 RW 0003C9H Memory Patch function - Patch address 5 high PFAH5 RW 2008-4-18 PR EL IM IN AR Y 0003ACH PFCS0 RW RW PFCS1 RW RW PFCS2 RW RW PFCS3 RW RW 37 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (12 / 28) Address 38 Abbreviation 8-bit access Register Abbreviation 16-bit access Access Memory Patch function - Patch address 6 low PFAL6 RW 0003CBH Memory Patch function - Patch address 6 middle PFAM6 RW 0003CCH Memory Patch function - Patch address 6 high PFAH6 RW 0003CDH Memory Patch function - Patch address 7 low PFAL7 RW 0003CEH Memory Patch function - Patch address 7 middle PFAM7 RW 0003CFH Memory Patch function - Patch address 7 high PFAH7 RW 0003D0H Memory Patch function - Patch data 0 Low 0003D1H Memory Patch function - Patch data 0 High 0003D2H Memory Patch function - Patch data 1 Low 0003D3H Memory Patch function - Patch data 1 High 0003D4H Memory Patch function - Patch data 2 Low PFDL2 0003D5H Memory Patch function - Patch data 2 High PFDH2 0003D6H Memory Patch function - Patch data 3 Low PFDL3 0003D7H Memory Patch function - Patch data 3 High PFDH3 0003D8H Memory Patch function - Patch data 4 Low PFDL4 0003D9H Memory Patch function - Patch data 4 High PFDH4 0003DAH Memory Patch function - Patch data 5 Low PFDL5 0003DBH Memory Patch function - Patch data 5 High PFDH5 0003DCH Memory Patch function - Patch data 6 Low PFDL6 0003DDH Memory Patch function - Patch data 6 High PFDH6 0003DEH Memory Patch function - Patch data 7 Low PFDL7 0003DFH Memory Patch function - Patch data 7 High 0003E0H0003F0H Reserved 0003F1H Memory Control Status Register A MCSRA 0003F2H Memory Timing Configuration Register A Low MTCRAL 0003F3H Memory Timing Configuration Register A High MTCRAH 0003F4H Reserved 0003F5H Memory Control Status Register B MCSRB 0003F6H Memory Timing Configuration Register B Low MTCRBL AR Y 0003CAH PFDL0 PFDH0 PFDL1 RW RW PFD1 PFDH1 IN IM EL PR PFD0 RW RW PFD2 RW RW PFD3 RW RW PFD4 RW RW PFD5 RW RW PFD6 RW RW PFD7 PFDH7 RW RW RW MTCRA RW RW RW MTCRB RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (13 / 28) Address Abbreviation 8-bit access Register Memory Timing Configuration Register B High 0003F8H Access MTCRBH RW Flash Memory Write Control register 0 FMWC0 RW 0003F9H Flash Memory Write Control register 1 FMWC1 RW 0003FAH Flash Memory Write Control register 2 FMWC2 RW 0003FBH Flash Memory Write Control register 3 0003FCH Flash Memory Write Control register 4 0003FDH Flash Memory Write Control register 5 0003FEH0003FFH Reserved 000400H Standby Mode control register 000401H Clock select register 000402H Clock Stabilisation select register 000403H Clock monitor register 000404H Clock Frequency control register Low 000405H Clock Frequency control register High CKFCRH 000406H PLL Control register Low PLLCRL 000407H PLL Control register High PLLCRH RW 000408H RC clock timer control register RCTCR RW 000409H Main clock timer control register MCTCR RW 00040AH Sub clock timer control register SCTCR RW 00040BH Reset cause and clock status register with clear function RCCSRC R 00040CH Reset configuration register RCR RW 00040DH Reset cause and clock status register RCCSR R 00040EH Watch dog timer configuration register WDTC RW 00040FH Watch dog timer clear pattern register WDTCP W 000410H000414H Reserved 000415H Clock output activation register 000416H 000417H 2008-4-18 Y 0003F7H Abbreviation 16-bit access FMWC4 RW RW CKSR RW CKSSR RW CKMR R IN AR RW SMCR IM EL PR FMWC3 FMWC5 CKFCRL RW - CKFCR RW RW PLLCR RW COAR RW Clock output configuration register 0 COCR0 RW Clock output configuration register 1 COCR1 RW 39 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (14 / 28) Address 40 Abbreviation 8-bit access Register 000418H Clock Modulator control register 000419H Reserved 00041AH Clock Modulator Parameter register Low CMPRL 00041BH Clock Modulator Parameter register High CMPRH 00041CH00042BH Reserved 00042CH Voltage Regulator Control register 00042DH Clock Input and LVD Control Register 00042EH00042FH Reserved 000430H I/O Port P00 - Data Direction Register 000431H I/O Port P01 - Data Direction Register 000432H I/O Port P02 - Data Direction Register 000433H I/O Port P03 - Data Direction Register 000434H Abbreviation 16-bit access CMCR Access RW - AR Y CMPR RW RW - VRCR RW CILCR RW IN DDR00 RW RW DDR02 RW DDR03 RW I/O Port P04 - Data Direction Register DDR04 RW 000435H I/O Port P05 - Data Direction Register DDR05 RW 000436H I/O Port P06 - Data Direction Register DDR06 RW 000437H Reserved 000438H I/O Port P08 - Data Direction Register DDR08 RW 000439H I/O Port P09 - Data Direction Register DDR09 RW 00043AH I/O Port P10 - Data Direction Register DDR10 RW 00043BH I/O Port P11 - Data Direction Register DDR11 RW 00043CH I/O Port P12 - Data Direction Register DDR12 RW 00043DH I/O Port P13 - Data Direction Register DDR13 RW 00043EH000443H Reserved 000444H I/O Port P00 - Port Input Enable Register PIER00 RW 000445H I/O Port P01 - Port Input Enable Register PIER01 RW 000446H I/O Port P02 - Port Input Enable Register PIER02 RW 000447H I/O Port P03 - Port Input Enable Register PIER03 RW 000448H I/O Port P04 - Port Input Enable Register PIER04 RW PR EL IM DDR01 - - 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (15 / 28) Address Abbreviation 8-bit access Register Abbreviation 16-bit access Access 000449H I/O Port P05 - Port Input Enable Register PIER05 RW 00044AH I/O Port P06 - Port Input Enable Register PIER06 RW 00044BH Reserved 00044CH I/O Port P08 - Port Input Enable Register 00044DH I/O Port P09 - Port Input Enable Register 00044EH I/O Port P10 - Port Input Enable Register 00044FH I/O Port P11 - Port Input Enable Register 000450H I/O Port P12 - Port Input Enable Register 000451H I/O Port P13 - Port Input Enable Register 000452H000457H Reserved 000458H I/O Port P00 - Port Input Level Register PILR00 RW 000459H I/O Port P01 - Port Input Level Register PILR01 RW 00045AH I/O Port P02 - Port Input Level Register PILR02 RW 00045BH I/O Port P03 - Port Input Level Register PILR03 RW 00045CH I/O Port P04 - Port Input Level Register PILR04 RW 00045DH I/O Port P05 - Port Input Level Register PILR05 RW 00045EH I/O Port P06 - Port Input Level Register PILR06 RW 00045FH Reserved 000460H I/O Port P08 - Port Input Level Register PILR08 RW 000461H I/O Port P09 - Port Input Level Register PILR09 RW 000462H I/O Port P10 - Port Input Level Register PILR10 RW 000463H I/O Port P11 - Port Input Level Register PILR11 RW 000464H I/O Port P12 - Port Input Level Register PILR12 RW 000465H I/O Port P13 - Port Input Level Register PILR13 RW 000466H00046BH Reserved 00046CH I/O Port P00 - Extended Port Input Level Register EPILR00 RW 00046DH I/O Port P01 - Extended Port Input Level Register EPILR01 RW 00046EH I/O Port P02 - Extended Port Input Level Register EPILR02 RW 00046FH I/O Port P03 - Extended Port Input Level Register EPILR03 RW 2008-4-18 - Y PIER08 PIER09 RW PIER10 RW AR IN IM EL PR RW PIER11 RW PIER12 RW PIER13 RW - - - 41 MB96390 Series FME-MB96390 rev 1 42 Register Abbreviation 8-bit access 000470H I/O Port P04 - Extended Port Input Level Register EPILR04 RW 000471H I/O Port P05 - Extended Port Input Level Register EPILR05 RW 000472H I/O Port P06 - Extended Port Input Level Register EPILR06 RW 000473H Reserved 000474H I/O Port P08 - Extended Port Input Level Register EPILR08 RW 000475H I/O Port P09 - Extended Port Input Level Register EPILR09 RW 000476H I/O Port P10 - Extended Port Input Level Register EPILR10 RW 000477H I/O Port P11 - Extended Port Input Level Register EPILR11 RW 000478H I/O Port P12 - Extended Port Input Level Register EPILR12 RW 000479H I/O Port P13 - Extended Port Input Level Register EPILR13 RW 00047AH00047FH Reserved 000480H I/O Port P00 - Port Output Drive Register PODR00 RW 000481H I/O Port P01 - Port Output Drive Register PODR01 RW 000482H I/O Port P02 - Port Output Drive Register PODR02 RW 000483H I/O Port P03 - Port Output Drive Register PODR03 RW 000484H I/O Port P04 - Port Output Drive Register PODR04 RW 000485H I/O Port P05 - Port Output Drive Register PODR05 RW 000486H I/O Port P06 - Port Output Drive Register PODR06 RW 000487H Reserved 000488H I/O Port P08 - Port Output Drive Register PODR08 RW 000489H I/O Port P09 - Port Output Drive Register PODR09 RW 00048AH I/O Port P10 - Port Output Drive Register PODR10 RW 00048BH I/O Port P11 - Port Output Drive Register PODR11 RW 00048CH I/O Port P12 - Port Output Drive Register PODR12 RW 00048DH I/O Port P13 - Port Output Drive Register PODR13 RW 00048EH00049BH Reserved 00049CH I/O Port P08 - Port High Drive Register PHDR08 RW 00049DH I/O Port P09 - Port High Drive Register PHDR09 RW 00049EH I/O Port P10 - Port High Drive Register PHDR10 RW AR IN IM EL Abbreviation 16-bit access Y Address PR I/O map MB96F39x (16 / 28) Access - - - - 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (17 / 28) Address Abbreviation 8-bit access Register Abbreviation 16-bit access Access 00049FH0004A7H Reserved 0004A8H I/O Port P00 - Pull-Up resistor Control Register PUCR00 RW 0004A9H I/O Port P01 - Pull-Up resistor Control Register PUCR01 RW 0004AAH I/O Port P02 - Pull-Up resistor Control Register 0004ABH I/O Port P03 - Pull-Up resistor Control Register 0004ACH I/O Port P04 - Pull-Up resistor Control Register PUCR04 RW 0004ADH I/O Port P05 - Pull-Up resistor Control Register PUCR05 RW 0004AEH I/O Port P06 - Pull-Up resistor Control Register PUCR06 RW 0004AFH Reserved 0004B0H I/O Port P08 - Pull-Up resistor Control Register 0004B1H Y - RW PUCR03 RW AR PUCR02 RW I/O Port P09 - Pull-Up resistor Control Register PUCR09 RW 0004B2H I/O Port P10 - Pull-Up resistor Control Register PUCR10 RW 0004B3H I/O Port P11 - Pull-Up resistor Control Register PUCR11 RW 0004B4H I/O Port P12 - Pull-Up resistor Control Register PUCR12 RW 0004B5H I/O Port P13 - Pull-Up resistor Control Register PUCR13 RW 0004B6H0004BBH Reserved 0004BCH I/O Port P00 - External Pin State Register EPSR00 R 0004BDH I/O Port P01 - External Pin State Register EPSR01 R 0004BEH I/O Port P02 - External Pin State Register EPSR02 R 0004BFH I/O Port P03 - External Pin State Register EPSR03 R 0004C0H I/O Port P04 - External Pin State Register EPSR04 R 0004C1H I/O Port P05 - External Pin State Register EPSR05 R 0004C2H I/O Port P06 - External Pin State Register EPSR06 R 0004C3H Reserved 0004C4H I/O Port P08 - External Pin State Register EPSR08 R 0004C5H I/O Port P09 - External Pin State Register EPSR09 R 0004C6H I/O Port P10 - External Pin State Register EPSR10 R 0004C7H I/O Port P11 - External Pin State Register EPSR11 R 0004C8H I/O Port P12 - External Pin State Register EPSR12 R 2008-4-18 PR EL IM IN PUCR08 - - 43 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (18 / 28) Address 44 Abbreviation 8-bit access Register Abbreviation 16-bit access EPSR13 Access 0004C9H I/O Port P13 - External Pin State Register R 0004CAH0004CFH Reserved 0004D0H ADC analog input enable register 0 ADER0 0004D1H ADC analog input enable register 1 ADER1 RW 0004D2H ADC analog input enable register 2 ADER2 RW 0004D3H ADC analog input enable register 3 0004D4H ADC analog input enable register 4 0004D5H Reserved 0004D6H Peripheral Resource Relocation Register 0 0004D7H Peripheral Resource Relocation Register 1 0004D8H - AR Y RW ADER3 RW ADER4 RW RW PRRR1 RW Peripheral Resource Relocation Register 2 PRRR2 RW 0004D9H Peripheral Resource Relocation Register 3 PRRR3 RW 0004DAH Peripheral Resource Relocation Register 4 PRRR4 RW 0004DBH Peripheral Resource Relocation Register 5 PRRR5 RW 0004DCH Peripheral Resource Relocation Register 6 PRRR6 RW 0004DDH Peripheral Resource Relocation Register 7 PRRR7 RW 0004DEH Peripheral Resource Relocation Register 8 PRRR8 RW 0004DFH Peripheral Resource Relocation Register 9 PRRR9 RW 0004E0H RTC - Sub Second Register L WTBRL0 0004E1H RTC - Sub Second Register M WTBRH0 RW 0004E2H RTC - Sub-Second Register H WTBR1 RW 0004E3H RTC - Second Register WTSR RW 0004E4H RTC - Minutes WTMR RW 0004E5H RTC - Hour WTHR RW 0004E6H RTC - Timer Control Extended Register WTCER RW 0004E7H RTC - Clock select register WTCKSR RW 0004E8H RTC - Timer Control Register Low WTCRL 0004E9H RTC - Timer Control Register High WTCRH RW 0004EAH CAL - Calibration unit Control register CUCR RW PR EL IM IN PRRR0 WTBR0 WTCR RW RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (19 / 28) Address Abbreviation 8-bit access Register Reserved 0004ECH CAL - Duration Timer Data Register Low CUTDL 0004EDH CAL - Duration Timer Data Register High CUTDH 0004EEH CAL - Calibration Timer Register 2 Low CUTR2L 0004EFH CAL - Calibration Timer Register 2 High 0004F0H CAL - Calibration Timer Register 1 Low 0004F1H CAL - Calibration Timer Register 1 High 0004F2H0004F9H Reserved 0004FAH RLT - Timer input select (for Cascading) 0004FBH00051FH Reserved 000520H USART4 - Serial Mode Register 000521H USART4 - Serial Control Register 000522H USART4 - TX Register 000522H USART4 - RX Register 000523H USART4 - Serial Status 000524H Access - Y 0004EBH Abbreviation 16-bit access CUTD RW CUTR2 CUTR2H IN R R CUTR1 AR CUTR1L RW CUTR1H R R - TMISR RW RW SCR4 RW TDR4 W RDR4 R SSR4 RW USART4 - Control/Com. Register (internal) ECCR4 RW 000525H USART4 - Ext. Status Register ESCR4 RW 000526H USART4 - Baud Rate Generator Register Low BGRL4 000527H USART4 - Baud Rate Generator Register High BGRH4 RW 000528H USART4 - Extended Serial Interrupt Register ESIR4 RW 000529H Reserved 00052AH USART5 - Serial Mode Register SMR5 RW 00052BH USART5 - Serial Control Register SCR5 RW 00052CH USART5 - RX Register TDR5 W 00052CH USART5 - TX Register RDR5 R 00052DH USART5 - Serial Status SSR5 RW 00052EH USART5 - Control/Com. Register ECCR5 RW 00052FH USART5 - Ext. Status Register ESCR5 RW 000530H USART5 - Baud Rate Generator Register Low BGRL5 2008-4-18 PR EL IM SMR4 BGR4 RW - BGR5 RW 45 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (20 / 28) Address 46 Abbreviation 8-bit access Register Abbreviation 16-bit access Access 000531H USART5 - Baud Rate Generator Register High BGRH5 RW 000532H USART5 - Extended Serial Interrupt Register ESIR5 RW 000533H00055FH Reserved 000560H ALARM0 - Control Status Register 000561H ALARM0 - Extended Control Status Register 000562H000563H Reserved 000564H PPG6 - Timer register 000565H PPG6 - Timer register 000566H PPG6 - Period setting register 000567H PPG6 - Period setting register 000568H PPG6 - Duty cycle register 000569H PPG6 - Duty cycle register 00056AH PPG6 - Control status register Low PCNL6 00056BH PPG6 - Control status register High PCNH6 00056CH PPG7 - Timer register 00056DH PPG7 - Timer register 00056EH PPG7 - Period setting register 00056FH PPG7 - Period setting register 000570H PPG7 - Duty cycle register 000571H PPG7 - Duty cycle register 000572H PPG7 - Control status register Low PCNL7 000573H PPG7 - Control status register High PCNH7 000574H0005DFH Reserved 0005E0H SMC0 - PWM control register 0005E1H SMC0 - Extended control register (Output enable) 0005E2H SMC0 - PWM compare register PWM 1 0005E3H SMC0 - PWM compare register PWM 1 0005E4H SMC0 - PWM compare register PWM 2 Y RW AECSR0 RW PR PTMR6 R R PCSR6 W W PDUT6 W W PCN6 RW RW PTMR7 R R EL IM IN AR ACSR0 PCSR7 W W PDUT7 W W PCN7 RW RW - PWC0 RW PWEC0 RW PWC10 RW RW PWC20 RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (21 / 28) Address Abbreviation 8-bit access Register Abbreviation 16-bit access Access 0005E5H SMC0 - PWM compare register PWM 2 0005E6H SMC0 - PWM Select register PWS10 RW 0005E7H SMC0 - PWM Select register PWS20 RW 0005E8H0005E9H Reserved 0005EAH SMC1 - PWM control register 0005EBH SMC1 - Extended control register (Output enable) 0005ECH SMC1 - PWM compare register PWM 1 0005EDH SMC1 - PWM compare register PWM 1 0005EEH SMC1 - PWM compare register PWM 2 0005EFH SMC1 - PWM compare register PWM 2 0005F0H SMC1 - PWM Select register 0005F1H SMC1 - PWM Select register 0005F2H0005F3H Reserved 0005F4H SMC2 - PWM control register 0005F5H SMC2 - Extended control register (Output enable) 0005F6H SMC2 - PWM compare register PWM 1 0005F7H SMC2 - PWM compare register PWM 1 0005F8H SMC2 - PWM compare register PWM 2 0005F9H SMC2 - PWM compare register PWM 2 0005FAH SMC2 - PWM Select register PWS12 RW 0005FBH SMC2 - PWM Select register PWS22 RW 0005FCH0005FDH Reserved 0005FEH SMC3 - PWM control register 0005FFH SMC3 - Extended control register (Output enable) 000600H SMC3 - PWM compare register PWM 1 000601H SMC3 - PWM compare register PWM 1 000602H SMC3 - PWM compare register PWM 2 000603H SMC3 - PWM compare register PWM 2 2008-4-18 RW RW RW PR EL IM IN PWC1 AR Y - PWEC1 PWC11 RW RW PWC21 RW RW PWS11 RW PWS21 RW - PWC2 RW PWEC2 RW PWC12 RW RW PWC22 RW RW PWC3 RW PWEC3 RW PWC13 RW RW PWC23 RW RW 47 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (22 / 28) Address 48 Abbreviation 8-bit access Register Abbreviation 16-bit access Access 000604H SMC3 - PWM Select register PWS13 RW 000605H SMC3 - PWM Select register PWS23 RW 000606H000607H Reserved 000608H SMC4 - PWM control register 000609H SMC4 - Extended control register (Output enable) 00060AH SMC4 - PWM compare register PWM 1 00060BH SMC4 - PWM compare register PWM 1 00060CH SMC4 - PWM compare register PWM 2 00060DH SMC4 - PWM compare register PWM 2 00060EH SMC4 - PWM Select register 00060FH SMC4 - PWM Select register 000610H00061BH Reserved 00061CH LCD - Output Enable Register 0 (Seg 7-0) LCDER0 RW 00061DH LCD - Output Enable Register 1 (Seg 15-8) LCDER1 RW 00061EH LCD - Output Enable Register 2 (Seg 23-16) LCDER2 RW 00061FH LCD - Output Enable Register 3 (Seg 31-24) LCDER3 RW 000620H LCD - Output Enable Register 4 (Seg 39-32) LCDER4 RW 000621H LCD - Output Enable Register 5 (Seg 47-40) LCDER5 RW 000622H LCD - Output Enable Register 6 (Seg 55-48) LCDER6 RW 000623H LCD - Output Enable Register 7 (Seg 63-56) LCDER7 RW 000624H LCD - Output Enable Register 8 (Seg 71-64) LCDER8 RW 000625H Reserved 000626H LCD - Output Enable Register V (Vx) 000627H LCD - Extended Control Register 000628H LCD - Common pin switching register 000629H LCD - Control Register 00062AH Y RW PWEC4 RW AR PWC4 RW RW PWC24 RW RW PWS14 RW PWS24 RW IN IM EL PR PWC14 - LCDVER RW LECR RW LCDCMR RW LCR RW LCD - Data register for Segment 1-0 VRAM0 RW 00062BH LCD - Data register for Segment 3-2 VRAM1 RW 00062CH LCD - Data register for Segment 5-4 VRAM2 RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (23 / 28) Address Abbreviation 8-bit access Register Abbreviation 16-bit access Access LCD - Data register for Segment 7-6 VRAM3 RW 00062EH LCD - Data register for Segment 9-8 VRAM4 RW 00062FH LCD - Data register for Segment 11-10 VRAM5 RW 000630H LCD - Data register for Segment 13-12 VRAM6 RW 000631H LCD - Data register for Segment 15-14 000632H LCD - Data register for Segment 17-16 000633H LCD - Data register for Segment 19-18 000634H LCD - Data register for Segment 21-20 000635H LCD - Data register for Segment 23-22 000636H LCD - Data register for Segment 25-24 000637H LCD - Data register for Segment 27-26 000638H Y 00062DH RW VRAM8 RW AR VRAM7 RW VRAM10 RW VRAM11 RW VRAM12 RW VRAM13 RW LCD - Data register for Segment 29-28 VRAM14 RW 000639H LCD - Data register for Segment 31-30 VRAM15 RW 00063AH LCD - Data register for Segment 33-32 VRAM16 RW 00063BH LCD - Data register for Segment 35-34 VRAM17 RW 00063CH LCD - Data register for Segment 37-36 VRAM18 RW 00063DH LCD - Data register for Segment 39-38 VRAM19 RW 00063EH LCD - Data register for Segment 41-40 VRAM20 RW 00063FH LCD - Data register for Segment 43-42 VRAM21 RW 000640H LCD - Data register for Segment 45-44 VRAM22 RW 000641H LCD - Data register for Segment 47-46 VRAM23 RW 000642H LCD - Data register for Segment 49-48 VRAM24 RW 000643H LCD - Data register for Segment 51-50 VRAM25 RW 000644H LCD - Data register for Segment 53-52 VRAM26 RW 000645H LCD - Data register for Segment 55-54 VRAM27 RW 000646H LCD - Data register for Segment 57-56 VRAM28 RW 000647H LCD - Data register for Segment 59-58 VRAM29 RW 000648H LCD - Data register for Segment 61-60 VRAM30 RW 000649H LCD - Data register for Segment 63-62 VRAM31 RW 00064AH LCD - Data register for Segment 65-64 VRAM32 RW 2008-4-18 PR EL IM IN VRAM9 49 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (24 / 28) 50 Abbreviation 8-bit access Register Abbreviation 16-bit access Access 00064BH00065FH Reserved 000660H Peripheral Resource Relocation Register 10 PRRR10 RW 000661H Peripheral Resource Relocation Register 11 PRRR11 RW 000662H Peripheral Resource Relocation Register 12 PRRR12 RW 000663H Peripheral Resource Relocation Register 13 PRRR13 W 000664H0006DFH Reserved 0006E0H External Bus - Area configuration register 0 Low 0006E1H External Bus - Area configuration register 0 High 0006E2H External Bus - Area configuration register 1 Low 0006E3H External Bus - Area configuration register 1 High EACH1 0006E4H External Bus - Area configuration register 2 Low EACL2 0006E5H External Bus - Area configuration register 2 High EACH2 0006E6H External Bus - Area configuration register 3 Low EACL3 0006E7H External Bus - Area configuration register 3 High EACH3 0006E8H External Bus - Area configuration register 4 Low EACL4 0006E9H IM Address External Bus - Area configuration register 4 High EACH4 0006EAH External Bus - Area configuration register 5 Low EACL5 0006EBH External Bus - Area configuration register 5 High EACH5 RW 0006ECH External Bus - Area select register 2 EAS2 RW 0006EDH External Bus - Area select register 3 EAS3 RW 0006EEH External Bus - Area select register 4 EAS4 RW 0006EFH External Bus - Area select register 5 EAS5 RW 0006F0H External Bus - Mode register EBM RW 0006F1H External Bus - Clock and Function register EBCF RW 0006F2H External Bus - Address output enable register 0 EBAE0 RW 0006F3H External Bus - Address output enable register 1 EBAE1 RW 0006F4H External Bus - Address output enable register 2 EBAE2 RW 0006F5H External Bus - Control signal register EBCS RW AR Y - EACL0 EAC0 EACH0 EACL1 IN EL PR RW RW EAC1 RW RW EAC2 RW RW EAC3 RW RW EAC4 RW RW EAC5 RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (25 / 28) Address Abbreviation 8-bit access Register 0006F6H0006FFH Reserved 000700H CAN0 - Control register Low CTRLRL0 000701H CAN0 - Control register High (reserved) CTRLRH0 000702H CAN0 - Status register Low 000703H CAN0 - Status register High (reserved) 000704H CAN0 - Error Counter Low (Transmit) 000705H CAN0 - Error Counter High (Receive) 000706H CAN0 - Bit Timing Register Low 000707H CAN0 - Bit Timing Register High 000708H CAN0 - Interrupt Register Low 000709H CAN0 - Interrupt Register High 00070AH CAN0 - Test Register Low 00070BH CAN0 - Test Register High (reserved) 00070CH CAN0 - BRP Extension register Low BRPERL0 00070DH CAN0 - BRP Extension register High (reserved) BRPERH0 00070EH00070FH Reserved 000710H CAN0 - IF1 Command request register Low IF1CREQL0 000711H CAN0 - IF1 Command request register High IF1CREQH0 000712H CAN0 - IF1 Command Mask register Low IF1CMSKL0 000713H CAN0 - IF1 Command Mask register High (reserved) IF1CMSKH0 000714H CAN0 - IF1 Mask 1 Register Low IF1MSK1L0 000715H CAN0 - IF1 Mask 1 Register High IF1MSK1H0 000716H CAN0 - IF1 Mask 2 Register Low IF1MSK2L0 000717H CAN0 - IF1 Mask 2 Register High IF1MSK2H0 000718H CAN0 - IF1 Arbitration 1 Register Low IF1ARB1L0 000719H CAN0 - IF1 Arbitration 1 Register High IF1ARB1H0 00071AH CAN0 - IF1 Arbitration 2 Register Low IF1ARB2L0 00071BH CAN0 - IF1 Arbitration 2 Register High IF1ARB2H0 2008-4-18 Abbreviation 16-bit access Access Y - STATRL0 CTRLR0 R STATR0 AR STATRH0 ERRCNTL0 ERRCNT0 BTR0 IN IM EL PR RW RW INTR0 INTRH0 TESTRL0 R R BTRH0 INTRL0 RW R ERRCNTH0 BTRL0 RW R R TESTR0 TESTRH0 RW R BRPER0 RW R - IF1CREQ0 RW RW IF1CMSK0 RW R IF1MSK10 RW RW IF1MSK20 RW RW IF1ARB10 RW RW IF1ARB20 RW RW 51 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (26 / 28) Address 52 Register Abbreviation 8-bit access Abbreviation 16-bit access Access IF1MCTR0 RW CAN0 - IF1 Message Control Register Low IF1MCTRL0 00071DH CAN0 - IF1 Message Control Register High IF1MCTRH0 00071EH CAN0 - IF1 Data A1 Low IF1DTA1L0 00071FH CAN0 - IF1 Data A1 High IF1DTA1H0 000720H CAN0 - IF1 Data A2 Low IF1DTA2L0 000721H CAN0 - IF1 Data A2 High IF1DTA2H0 000722H CAN0 - IF1 Data B1 Low 000723H CAN0 - IF1 Data B1 High 000724H CAN0 - IF1 Data B2 Low 000725H CAN0 - IF1 Data B2 High 000726H00073FH Reserved 000740H CAN0 - IF2 Command request register Low IF2CREQL0 000741H CAN0 - IF2 Command request register High IF2CREQH0 000742H CAN0 - IF2 Command Mask register Low IF2CMSKL0 000743H CAN0 - IF2 Command Mask register High (reserved) IF2CMSKH0 000744H CAN0 - IF2 Mask 1 Register Low IF2MSK1L0 000745H CAN0 - IF2 Mask 1 Register High IF2MSK1H0 000746H CAN0 - IF2 Mask 2 Register Low IF2MSK2L0 000747H CAN0 - IF2 Mask 2 Register High IF2MSK2H0 000748H CAN0 - IF2 Arbitration 1 Register Low IF2ARB1L0 000749H CAN0 - IF2 Arbitration 1 Register High IF2ARB1H0 00074AH CAN0 - IF2 Arbitration 2 Register Low IF2ARB2L0 00074BH CAN0 - IF2 Arbitration 2 Register High IF2ARB2H0 00074CH CAN0 - IF2 Message Control Register Low IF2MCTRL0 00074DH CAN0 - IF2 Message Control Register High IF2MCTRH0 00074EH CAN0 - IF2 Data A1 Low IF2DTA1L0 00074FH CAN0 - IF2 Data A1 High IF2DTA1H0 000750H CAN0 - IF2 Data A2 Low IF2DTA2L0 000751H CAN0 - IF2 Data A2 High IF2DTA2H0 RW IF1DTA10 AR Y 00071CH IF1DTB1L0 IF1DTA20 IF1DTB10 IF1DTB1H0 IF1DTB2L0 IN IM EL RW RW RW RW RW IF1DTB20 IF1DTB2H0 PR RW RW RW - IF2CREQ0 RW RW IF2CMSK0 RW R IF2MSK10 RW RW IF2MSK20 RW RW IF2ARB10 RW RW IF2ARB20 RW RW IF2MCTR0 RW RW IF2DTA10 RW RW IF2DTA20 RW RW 2008-4-18 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (27 / 28) Register Abbreviation 8-bit access Abbreviation 16-bit access Access IF2DTB10 RW CAN0 - IF2 Data B1 Low IF2DTB1L0 000753H CAN0 - IF2 Data B1 High IF2DTB1H0 000754H CAN0 - IF2 Data B2 Low IF2DTB2L0 000755H CAN0 - IF2 Data B2 High IF2DTB2H0 000756H00077FH Reserved 000780H CAN0 - Transmission Request 1 Register Low TREQR1L0 000781H CAN0 - Transmission Request 1 Register High TREQR1H0 000782H CAN0 - Transmission Request 2 Register Low TREQR2L0 000783H CAN0 - Transmission Request 2 Register High TREQR2H0 000784H00078FH Reserved 000790H CAN0 - New Data 1 Register Low 000791H CAN0 - New Data 1 Register High 000792H CAN0 - New Data 2 Register Low NEWDT2L0 000793H CAN0 - New Data 2 Register High NEWDT2H0 000794H00079FH Reserved 0007A0H CAN0 - Interrupt Pending 1 Register Low INTPND1L0 0007A1H CAN0 - Interrupt Pending 1 Register High INTPND1H0 0007A2H CAN0 - Interrupt Pending 2 Register Low INTPND2L0 0007A3H CAN0 - Interrupt Pending 2 Register High INTPND2H0 0007A4H0007AFH Reserved 0007B0H CAN0 - Message Valid 1 Register Low MSGVAL1L0 0007B1H CAN0 - Message Valid 1 Register High MSGVAL1H0 0007B2H CAN0 - Message Valid 2 Register Low MSGVAL2L0 0007B3H CAN0 - Message Valid 2 Register High MSGVAL2H0 0007B4H0007CDH Reserved 0007CEH CAN0 - Output enable register 0007CFH Reserved 2008-4-18 PR EL IM IN AR 000752H Y Address NEWDT1L0 RW IF2DTB20 RW RW - TREQR10 R R TREQR20 R R - NEWDT10 NEWDT1H0 R R NEWDT20 R R - INTPND10 R R INTPND20 R R - MSGVAL10 R R MSGVAL20 R R - COER0 RW 53 MB96390 Series FME-MB96390 rev 1 I/O map MB96F39x (28 / 28) Address Register Abbreviation 8-bit access Abbreviation 16-bit access Access SGCR0 RW SG0 - Sound Generator Control Register Low SGCRL0 0007D1H SG0 - Sound Generator Control Register High SGCRH0 RW 0007D2H SG0 - Sound Generator Frequency Register SGFR0 RW 0007D3H SG0 - Sound Generator Amplitude Register SGAR0 RW 0007D4H SG0 - Sound Generator Decrement Register SGDR0 RW 0007D5H SG0 - Sound Generator Tone Register SGTR0 RW 0007D6H SG1 - Sound Generator Control Register Low 0007D7H SG1 - Sound Generator Control Register High 0007D8H SG1 - Sound Generator Frequency Register 0007D9H SG1 - Sound Generator Amplitude Register 0007DAH SG1 - Sound Generator Decrement Register SGDR1 RW 0007DBH SG1 - Sound Generator Tone Register SGTR1 RW 0007DCH000BFFH Reserved AR Y 0007D0H SGCRL1 SGCR1 RW RW SGFR1 RW SGAR1 RW - IM IN SGCRH1 PR EL Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading ‘X’. Registers of resources which are described in this table, but which are not supported by the device, should also be handled as “Reserved”. 54 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ INTERRUPT VECTOR TABLE Interrupt vector table MB96(F)39x (1 / 3) Offset in Vector vector taVector name number ble Index in ICR to program Description 3FC CALLV0 - 1 3F8 CALLV1 - 2 3F4 CALLV2 - 3 3F0 CALLV3 - 4 3EC CALLV4 - 5 3E8 CALLV5 - 6 3E4 CALLV6 - 7 3E0 CALLV7 - 8 3DC RESET - 9 3D8 INT9 - 10 3D4 EXCEPTION - 11 3D0 NMI 12 3CC DLY 13 3C8 RC_TIMER 14 3C4 MC_TIMER 14 Main Clock Timer 15 3C0 SC_TIMER 15 Sub Clock Timer 16 3BC 17 3B8 EXTINT0 18 3B4 19 3B0 20 3AC 21 3A8 22 3A4 23 IN AR Y 0 - Non-Maskable Interrupt Delayed Interrupt 13 RC Timer IM 12 External Interrupt 0 EXTINT1 18 External Interrupt 1 EXTINT2 19 External Interrupt 2 EXTINT3 20 External Interrupt 3 EXTINT4 21 External Interrupt 4 EXTINT5 22 External Interrupt 5 3A0 EXTINT6 23 External Interrupt 6 24 39C EXTINT7 24 External Interrupt 7 25 398 CAN0 25 CAN Controller 0 26 394 27 390 PPG0 27 Programmable Pulse Generator 0 28 38C PPG1 28 Programmable Pulse Generator 1 29 388 PPG2 29 Programmable Pulse Generator 2 30 384 PPG3 30 Programmable Pulse Generator 3 31 380 Reserved 32 37C Reserved 2008-4-18 PR EL 17 Reserved Reserved 55 MB96390 Series FME-MB96390 rev 1 Interrupt vector table MB96(F)39x (2 / 3) Offset in Vector vector taVector name number ble 56 Index in ICR to program Description 378 Reserved 34 374 Reserved 35 370 RLT0 35 Reload Timer 0 36 36C RLT1 36 Reload Timer 1 37 368 RLT2 37 Reload Timer 2 38 364 RLT3 38 Reload Timer 3 39 360 PPGRLT 39 Reload Timer 6 - dedicated for PPG 40 35C ICU0 40 Input Capture Unit 0 41 358 ICU1 41 Input Capture Unit 1 42 354 Reserved 43 350 Reserved 44 34C Reserved 45 348 46 344 ICU6 46 47 340 ICU7 47 48 33C OCU0 48 49 338 OCU1 50 334 OCU2 51 330 OCU3 52 32C FRT0 53 328 54 IN AR Y 33 Reserved Input Capture Unit 6 Input Capture Unit 7 IM Output Compare Unit 0 Output Compare Unit 1 50 Output Compare Unit 2 51 Output Compare Unit 3 52 Free Running Timer 0 FRT1 53 Free Running Timer 1 324 RTC0 54 Real Timer Clock 55 320 CAL0 55 Clock Calibration Unit 56 31C SG0 56 Sound Generator 0 57 318 58 314 59 310 60 30C 61 308 62 304 63 PR EL 49 Reserved IIC0 58 I2C interface ADC0 59 A/D Converter ALARM0 60 Alarm Comparator 0 Reserved LINR0 62 LIN USART 0 RX 300 LINT0 63 LIN USART 0 TX 64 2FC LINR1 64 LIN USART 1 RX 65 2F8 LINT1 65 LIN USART 1 TX 66 2F4 LINR2 66 LIN USART 2 RX 67 2F0 LINT2 67 LIN USART 2 TX 2008-4-18 MB96390 Series FME-MB96390 rev 1 Index in ICR to program Description 68 2EC Reserved 69 2E8 Reserved 70 2E4 Reserved 71 2E0 Reserved 72 2DC 73 2D8 FLASH_A 72 Flash memory A (only Flash devices) PR EL IM IN AR Reserved Y Interrupt vector table MB96(F)39x (3 / 3) Offset in Vector vector taVector name number ble 2008-4-18 57 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 58 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ HANDLING DEVICES Special care is required for the following when handling the device: Y Latch-up prevention Unused pins handling External clock usage Unused sub clock signal Notes on PLL clock mode operation Power supply pins (VCC/VSS) Crystal oscillator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on energization Stabilization of power supply voltage SMC power supply pins AR • • • • • • • • • • • • 1. Latch-up prevention • CMOS IC chips may suffer latch-up under the following conditions: IN • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. • Latch-up may increase the power supply current dramatically, causing thermal damages to the device. 2. Unused pins handling IM • For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. • Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). EL • Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latchup, those resistors should be more than 2 kΩ. • Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. External clock usage PR • The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 1. Single phase external clock • When using a single phase external clock, X0 pin must be driven and X1 pin left open. X0 X1 2. Opposite phase external clock 2008-4-18 59 MB96390 Series FME-MB96390 rev 1 • When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. X0 Y X1 4. Unused sub clock signal AR • If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. 5. Notes on PLL clock mode operation 6. Power supply pins (VCC/VSS) IN • If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. • It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. IM • VCC and VSS must be connected to the device from the power supply with lowest possible impedance. • As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between VCC and VSS as close as possible to VCC and VSS pins. 7. Crystal oscillator circuit EL • Noise at X0 or X1 pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. • It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. PR • It is highly recommended to evaluate the quartz/MCU system at the quartz manufacturer. 8. Turn on sequence of power supply to A/D converter and analog inputs • It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. • It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. Pin handling when not using the A/D converter • It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on energization • To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50µs from 0.2 V to 2.7 V. 60 2008-4-18 MB96390 Series FME-MB96390 rev 1 11. Stabilization of power supply voltage • If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching. • All DVSS pins must be set to the same level as the VSS pins. Y 12. SMC power supply pins PR EL IM IN AR • The DVCC power supply level can be set independently of the VCC power supply level. However note that the SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, we recommend to always power VCC before DVCC. 2008-4-18 61 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 62 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Power supply voltage AD Converter voltage references SMC Power supply LCD power supply voltage Rating Min Max Unit Remarks Y Symbol VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V AVRH, AVRL VSS - 0.3 VSS + 6.0 V AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS DVCC VSS - 0.3 VSS + 6.0 V See *7 V0 to V3 VSS - 0.3 VSS + 6.0 V V0 to V3 must not exceed VCC AR Parameter VCC = AVCC *1 VI VSS - 0.3 VSS + 6.0 V VI ≤ (D)VCC + 0.3V Output voltage VO VSS - 0.3 VSS + 6.0 V VO ≤ (D)VCC + 0.3V *2 “L” level maximum output current +4.0 mA Applicable to general purpose I/ O pins *3 Σ|ICLAMP| - 40 mA Applicable to general purpose I/ O pins *3 IOL1 - 15 mA Normal outputs with driving strength set to 5mA IOLSMC - 40 mA High current outputs with driving strength set to 30mA IOLAV1 - 5 mA Normal outputs with driving strength set to 5mA IOLAVSMC - 30 mA High current outputs with driving strength set to 30mA ΣIOL1 - 100 mA Normal outputs ΣIOLSMC - 330 mA High current outputs ΣIOLAV1 - 50 mA Normal outputs ΣIOLAVSMC - 250 mA High current outputs IOH1 - -15 mA IOHSMC - -40 mA High current outputs with driving strength set to 30mA IOHAV1 - -5 mA Normal outputs with driving strength set to 5mA IOHAVSMC - -30 mA High current outputs with driving strength set to 30mA ΣIOH1 - -100 mA Normal outputs ΣIOHSMC - -330 mA High current outputs “L” level average output current PR “L” level maximum overall output current “L” level average overall output current ”H” level maximum output current ”H” level average output current ”H” level maximum overall output current 2008-4-18 -4.0 EL Total Maximum Clamp Current *2 ICLAMP IM Maximum Clamp Current IN Input voltage Normal outputs with driving strength set to 5mA 63 MB96390 Series FME-MB96390 rev 1 Parameter Symbol ”H” level average overall output current Rating Remarks ΣIOHAV1 - -50 mA Normal outputs ΣIOHASMC - -250 mA High current outputs - *5 290 mW TA=105oC - 580*5 mW TA=85oC - 950*5 mW TA=60oC - 360*5 mW TA=125oC, no Flash program/ erase *6 - 660*5 mW TA=105oC, no Flash program/ erase *6 0 Operating ambient temperature TA -40 -40 -55 MB96V300B +70 +105 o C +125 +150 *6 o C IN TSTG AR PD Y Max Permitted Power dissipation (MB96F395) *4 Storage temperature Unit Min *1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on. IM *2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of high current ports depend on DVCC. Input/output voltages of standard ports depend on VCC. PR EL *3: • Applicable to all general purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality. • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). • No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins). 64 2008-4-18 MB96390 Series FME-MB96390 rev 1 • Sample recommended circuits: Protective Diode VCC Limiting resistance P-ch +B input (0V to 16V) AR R Y N-ch IM IN *4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator. IA is the analog current consumption into AVCC. *5: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *6: Please contact Fujitsu for reliability limitations when using under these conditions. PR EL *7: If DVCC is powered before VCC, then SMC I/O pins state is undefined. To avoid this, we recommend to always power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value. 2008-4-18 65 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 66 2008-4-18 MB96390 Series FME-MB96390 rev 1 2. Recommended Conditions Power supply voltage Smoothing capacitor at C pin Symbol Value Unit Min Typ Max VCC, DVCC 3.0 - 5.5 V CS 4.7 - 10 µF Remarks Use a low inductance capacitor (for example X7R ceramic capacitor) Y Parameter AR WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the devices electrical characteristics are guaranteed when the device is operated within these ranges. Semiconductor devices must always be operated within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. PR EL IM IN No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 2008-4-18 67 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 68 2008-4-18 MB96390 Series FME-MB96390 rev 1 3. DC characteristics (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Pin Condition Input “H“ voltage CMOS Hysteresis 0.8/0.2 input selected Max 0.8 VCC - (D)VCC + 0.3 V - (D)VCC + 0.3 V (D)VCC ≥ 4.5V - (D)VCC + 0.3 V (D)VCC < 4.5V 0.7 VCC 0.74 VCC 0.8 VCC - (D)VCC + 0.3 V TTL input selected 2.0 - (D)VCC + 0.3 V X0 External clock in “Fast Clock Input mode” 0.8 VCC - VCC + 0.3 V VIHX0S X0,X1, X0A,X1A External clock in “oscillation mode” 2.5 - VCC + 0.3 V VIHR RSTX - 0.8 VCC - VCC + 0.3 V VIHM MD2-MD0 - VCC 0.3 - VCC + 0.3 V CMOS Hysteresis 0.8/0.2 input selected VSS 0.3 - 0.2 (D)VCC V CMOS Hysteresis 0.7/0.3 input sePort inputs lected VSS 0.3 - 0.3 (D)VCC V VSS 0.3 - 0.5 (D)VCC V VSS 0.3 - 0.46 (D)VCC TTL input selected VSS 0.3 - 0.8 V IM EL Pnn_m PR VIL AUTOMOTIVE Hysteresis input selected Remarks Typ VIHX0F Input “L” voltage 2008-4-18 Unit Min AR VIH CMOS Hysteresis Port inputs 0.7/0.3 input selected Pnn_m AUTOMOTIVE Hysteresis input selected Value Y Symbol IN Parameter CMOS Hysteresis input (D)VCC ≥ 4.5V (D)VCC < 4.5V VILX0F X0 External clock in “Fast Clock Input mode” VSS 0.3 - 0.2 VCC V VILX0S X0,X1, X0A,X1A External clock in “oscillation mode” VSS 0.3 - 0.4 V VILR RSTX - VSS 0.3 - 0.2 VCC V VILM MD2-MD0 - VSS 0.3 - VSS + 0.3 V CMOS Hysteresis input 69 MB96390 Series FME-MB96390 rev 1 (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Symbol Pin Normal and High Current outputs IOH = -2mA 3.0V ≤ (D)VCC < 4.5V Max (D)VCC - 0.5 - - (D)VCC - 0.5 - - V Driving strength set to 5mA DVCC 0.5 - - V Driving strength set to 30mA VCC 0.5 - - V - - 0.4 V Driving strength set to 2mA - - 0.4 V Driving strength set to 5mA - - 0.5 V Driving strength set to 30mA - - 0.4 V -1 - +1 µA IOH = -5mA 3.0V ≤ (D)VCC < 4.5V IOH = -3mA 4.5V ≤ DVCC ≤ 5.5V IOH = -30mA 3.0V ≤ DVCC < 4.5V IN VOH30 V Y 4.5V ≤ (D)VCC ≤ 5.5V Normal and High Current outputs High current outputs Remarks Typ IOH = -1.6mA VOH5 Unit Min 4.5V ≤ (D)VCC ≤ 5.5V Output “H” voltage VOH2 Value Condition AR Parameter Driving strength set to 2mA IOH = -20mA 4.5V ≤ VCC ≤ 5.5V I2C outputs IOH = -3mA 3.0V ≤ VCC < 4.5V IM VOH3 IOH = -2mA 4.5V ≤ (D)VCC ≤ 5.5V Output “L” voltage IOL = +2mA 3.0V ≤ (D)VCC < 4.5V EL VOL2 Normal and High Current outputs IOL = +1.6mA IOL = +5mA PR VOL5 Normal and High Current outputs 4.5V ≤ (D)VCC ≤ 5.5V 3.0V ≤ (D)VCC < 4.5V IOL = +3mA 4.5V ≤ DVCC ≤ 5.5V VOL30 High current outputs IOL = +30mA 3.0V ≤ DVCC < 4.5V IOL = +20mA 4.5V ≤ VCC ≤ 5.5V VOL3 I2C outputs IOL = +3mA 3.0V ≤ VCC < 4.5V IOL = +2mA Input leak current 70 IIL Pnn_m DVCC = VCC = 5.5V VSS < VI < VCC 2008-4-18 MB96390 Series FME-MB96390 rev 1 (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Symbol Pin Condition Total LCD leakage current ΣIILCD all SEG/ COM pins VCC = 5.0V Internal LCD divide resistance RLCD Between V3 and VSS Pull-up resistance RUP Pnn_m, RSTX Value - Unit Remarks Min Typ Max -10 0.5 10 Maximum leakage µA current of all LCD pins 25 35 50 kΩ 25 Y Parameter 50 100 kΩ Condition ICCPLL PLL Run mode with CLKS1/2 = 48MHz, CLKB = CLKP1/2 = 24MHz IM Power supply current in Run modes* Symbol EL PLL Run mode with CLKS1/2 = 80MHz, CLKB = CLKP1 = 40MHz, CLKP2 = 20MHz ICCRCH 2008-4-18 Typ Max 35 44 Unit temp Remarks 25˚C CLKRC and CLKSC stopped. Core voltage at 1.9V mA 36 47 125˚C 0 Flash/ROM wait states 47 60 25˚C CLKRC and CLKSC stopped. Core voltage at 1.9V mA 1 Flash/ROM wait state 48 63 125˚C 4.5 5.5 25˚C Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz PR ICCMAIN Value IN Parameter AR Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC. (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) mA 5.1 8.5 125˚C 2.9 4 25˚C RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 2MHz mA 3.5 6.5 125˚C CLKPLL, CLKSC and CLKRC stopped 1 Flash/ROM wait state CLKMC, CLKPLL and CLKSC stopped 1 Flash/ROM wait state 71 MB96390 Series FME-MB96390 rev 1 (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Symbol Value Condition RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 0 Power supply current in Run modes* Typ Max 0.4 0.6 0.9 3.5 RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 1 CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode 125˚C 1 Flash/ROM wait state 0.25 25˚C mA 3.2 IN 0.65 0.1 125˚C 0.2 3 CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode, no Flash programming/erasing allowed. 1 Flash/ROM wait state 25˚C CLKMC, CLKPLL and CLKRC stopped, no Flash programming/ erasing allowed. 125˚C 1 Flash/ROM wait state mA PR EL IM 0.6 Remarks 25˚C AR 0.15 ICCSUB temp mA ICCRCL Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz Unit Y Parameter 72 2008-4-18 MB96390 Series FME-MB96390 rev 1 (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Condition ICCSPLL PLL Sleep mode with CLKS1/2 = 48MHz, CLKP1/2 = 24MHz PLL Sleep mode with CLKS1/2 = 80MHz, CLKP1 = 40MHz, CLKP2 = 20MHz Max 9 10.5 Unit temp 25˚C CLKRC and CLKSC stopped. Core voltage at 1.9V 9.7 13 125˚C 12.5 14.5 25˚C mA 17 125˚C 1.5 1.8 25˚C IN 13.3 2 4.5 125˚C 0.8 1.3 25˚C CLKMC, CLKPLL and CLKSC stopped mA 1.4 4 CLKRC and CLKSC stopped. Core voltage at 1.9V CLKPLL, CLKSC and CLKRC stopped mA RC Sleep mode with CLKS1/2 = CLKP1/2 = 2MHz Remarks 125˚C PR EL ICCSRCH Typ mA IM ICCSMAIN Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz Value Y Power supply current in Sleep Symbol AR Parameter 2008-4-18 73 MB96390 Series FME-MB96390 rev 1 (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Symbol Value Condition RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 0 Power supply current in Sleep modes* Typ Max 0.3 0.5 temp 25˚C mA 0.8 3.4 0.06 RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 1 125˚C AR ICCSRCL 0.15 IN 3 0.04 2.9 CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode 25˚C CLKMC, CLKPLL and CLKRC stopped mA 125˚C PR EL IM 0.54 CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode 125˚C 0.12 Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz Remarks 25˚C mA 0.56 ICCSSUB Unit Y Parameter 74 2008-4-18 MB96390 Series FME-MB96390 rev 1 (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Condition ICCTPLL PLL Timer mode with CLKMC = 4MHz, CLKPLL = 48MHz Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 ICCTMAIN Typ Max 1.6 2 IM Power supply current in Timer modes* EL CLKRC and CLKSC stopped. Core voltage at 1.9V 125˚C 0.35 0.5 25˚C mA 0.85 3.3 125˚C 0.1 0.15 25˚C mA 0.6 2.9 125˚C 0.35 0.5 25˚C mA 0.85 3.3 125˚C 0.1 0.15 25˚C mA 0.6 2.9 125˚C 0.3 0.45 25˚C RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 0 Remarks 25˚C 4.8 RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 1 PR temp 2.1 RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 ICCTRCH Unit mA IN Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 1 Value Y Symbol AR Parameter mA 0.8 3.2 125˚C 0.05 0.1 25˚C CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in high power mode CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode ICCTRCL RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 1 mA 0.55 2008-4-18 2.8 125˚C CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode 75 MB96390 Series FME-MB96390 rev 1 (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) ICCTSUB Value Condition Max 0.03 0.1 Sub Timer mode with CLKSC = 32kHz ICCH VRCR:LPMB[2:0] = “000” 0.53 2.8 0.02 0.08 0.52 2.8 0.015 0.06 0.4 2.3 90 ICCLVD temp Low voltage detector enabled (RCR:LVDE=’1’) Remarks 25˚C CLKMC, CLKPLL and CLKRC stopped 125˚C mA mA 140 IN Power supply current for active Low Voltage detector Unit mA VRCR:LPMB[2:0] = “110” Stop Mode Typ Y Power supply current in Timer modes* Symbol 25˚C 125˚C AR Parameter 25˚C 125˚C Core voltage at 1.8V Core voltage at 1.2V 25˚C µA This current must be added to all Power supply currents above 100 150 125˚C 4.5 mA - Must be added to all current above - Must be added to all current above ICCCLOMO Clock modulator enabled (CMCR:PDX = ‘1’) 3 Flash Write/Erase current ICCFLASH Current for one Flash module 15 40 mA Input capacitance CIN - 15 30 pF High current outputs pF Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, High current outputs CIN EL Input capacitance IM Clock modulator current - 5 15 PR * The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. 76 2008-4-18 MB96390 Series FME-MB96390 rev 1 4. AC Characteristics Source Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Clock frequency fFCI X0, X1 Clock frequency fCL X0A Max 3 - 16 MHz When using an oscillation circuit, PLL off 0 - 16 MHz When using an opposite phase external clock, PLL off 3.5 - 16 MHz When using an oscillation circuit or opposite phase external clock, PLL on 0 - 3.5 - 32 0 0 Clock frequency fCLKVCO Input clock pulse width PWH, PWL MHz When using a single phase external clock in “Fast Clock Input mode” , PLL off 40 MHz When using a single phase external clock in “Fast Clock Input mode” , PLL on 32.768 100 kHz When using an oscillation circuit - 100 kHz When using an opposite phase external clock - 50 kHz When using a single phase external clock 100 200 kHz When using slow frequency of RC oscillator - 1 2 4 MHz When using fast frequency of RC oscillator 50 - 200 MHz Permitted VCO output frequency of PLL (CLKVCO) X0,X1 8 - - ns PWHL, PWLL X0A,X1A 5 - - µs Duty ratio is about 30% to 70% PR Input clock pulse width - EL fCR 40 IM 50 Clock frequency Remarks Typ X0 X0A, X1A Unit Min Y fC Value Pin AR Clock frequency Symbol IN Parameter 2008-4-18 77 MB96390 Series FME-MB96390 rev 1 tCYL VIH X0 VIL PWH tCYLL Y PWL AR VIH X0A PWHL VIL PR EL IM IN PWLL 78 2008-4-18 MB96390 Series FME-MB96390 rev 1 Internal Clock timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Core Voltage Settings Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) fCLKS1, fCLKS2 fCLKB, fCLKP1 fCLKP2 1.9V Unit Remarks MHz Others than below Min Max Min Max 0 92 0 96 0 72 0 0 52 0 0 36 0 28 80 MHz MB96F395 56 MHz Others than below 0 40 MHz MB96F395 0 32 MHz PR EL IM IN Internal peripheral clock frequency (CLKP2) 1.8V Y Internal System clock frequency (CLKS1 and CLKS2) Symbol AR Parameter 2008-4-18 79 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 80 2008-4-18 MB96390 Series FME-MB96390 rev 1 External Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Reset input time Symbol Pin tRSTL RSTX Value Min Typ Max 500 - - tRSTL ns 0.2 VCC PR EL IM IN 0.2 VCC Remarks AR RSTX Unit Y Parameter 2008-4-18 81 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 82 2008-4-18 MB96390 Series FME-MB96390 rev 1 Power On Reset timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Power on rise time Power off time Symbol Pin tR tOFF Value Typ Max Vcc 0.05 - 30 ms Vcc 1 - - ms tR AR 2.7V VCC Unit Min Remarks Y Parameter 0.2 V 0.2 V 0.2 V tOFF IN If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. IM VCC Rising edge of 50 mV/ms maximum is allowed PR EL 3V 2008-4-18 83 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 84 2008-4-18 MB96390 Series FME-MB96390 rev 1 External Input timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Parameter Symbol Pin Value Condition INTn NMI Min Max 200 ⎯ Unit NMI General Purpose IO TINn Y tINH tINL External Interrupt ns Pnn_m Input pulse width Used Pin input function ⎯ TTGn 2*tCLKP1 + 200 (tCLKP1=1/ fCLKP1) ⎯ AR ADTG FRCKn INn ns Reload Timer PPG Trigger input AD Converter Trigger Free Running Timer external clock Input Capture External Pin input VIH IN Note : Relocated Resource Inputs have same characteristics VIH VIL VIL tINL PR EL IM tINH 2008-4-18 85 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 86 2008-4-18 MB96390 Series FME-MB96390 rev 1 Slew Rate High Current Outputs (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Output rise/fall time tR30 tF30 Pin Condition I/O circuit type M Output driving strength set to “30mA” Value Min Max 15 ⎯ Unit Remarks ns Y Parameter Symbol AR Note : Relocated Resource Inputs have same characteristics • Slew rate output timing VH VH VL VL VH = VOL30 + 0.9 × (VOH30 - VOL30) VL = VOL30 + 0.1 × (VOH30 - VOL30) tF30 PR EL IM IN tR30 2008-4-18 87 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 88 2008-4-18 MB96390 Series FME-MB96390 rev 1 USART timing WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. (TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) Pin Serial clock cycle time tSCYCI SCKn 4 tCLKP1 ⎯ 4 tCLKP1 ⎯ ns SCK ↓ → SOT delay time tSLOVI SCKn, SOTn -20 +20 -30 +30 ns SOT → SCK ↑ delay time tOVSHI SCKn, SOTn N*tCLKP1 - 20 *1 ⎯ N*tCLKP1 30 *1 ⎯ Valid SIN → SCK ↑ tIVSHI SCKn, SINn tCLKP1 + 45 ⎯ tCLKP1 + 55 ⎯ ns SCK ↑ → Valid SIN hold time tSHIXI SCKn, SINn 0 ⎯ 0 ⎯ ns Serial clock “L” pulse width tSLSHE SCKn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns Serial clock “H” pulse width tSHSLE SCKn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns SCK ↓ → SOT delay time tSLOVE SCKn, SOTn ⎯ 2 tCLKP1 + 45 ⎯ 2 tCLKP1 + 55 ns Valid SIN → SCK ↑ tIVSHE SCKn, SINn tCLKP1/2 + 10 ⎯ tCLKP1/2 + 10 ⎯ ns SCK ↑ → Valid SIN hold time tSHIXE SCKn, SINn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns SCK fall time tFE SCKn ⎯ 20 ⎯ 20 ns SCK rise time tRE SCKn ⎯ 20 ⎯ 20 ns AR Y Condition VCC = AVCC= 4.5V VCC = AVCC= 3.0V to 5.5V to 4.5V Unit Min Max Min Max Symbol IM IN Internal Shift Clock Mode External Shift Clock Mode EL Parameter PR Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL” • tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns *1: Parameter N depends on tSCYCI and can be calculated as follows: • if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 • if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI N 2008-4-18 4*tCLKP1 2 5*tCLKP1, 6*tCLKP1 3 7*tCLKP1, 8*tCLKP1 4 ... ... 89 MB96390 Series FME-MB96390 rev 1 tSCYCI SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC SCK for ESCR:SCES = 1 0.8*VCC Y 0.8*VCC 0.2*VCC tOVSHI AR tSLOVI 0.8*VCC SOT 0.2*VCC tSHIXI tIVSHI VIH VIH VIL VIL IN SIN IM Internal Shift Clock Mode tSLSHE SCK for ESCR:SCES = 0 VIH SIN tSLOVE PR SOT VIH VIL VIL VIH VIL tFE VIH VIL VIL EL SCK for ESCR:SCES = 1 VIH tSHSLE tRE 0.8*VCC 0.2*VCC tIVSHE tSHIXE VIH VIH VIL VIL External Shift Clock Mode 90 2008-4-18 MB96390 Series FME-MB96390 rev 1 I2C Timing (TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Standard-mode Condition Fast-mode*4 Unit Max Min Max fSCL 0 100 0 400 kHz tHDSTA 4.0 ⎯ 0.6 ⎯ µs “L” width of the SCL clock tLOW 4.7 ⎯ 1.3 ⎯ µs “H” width of the SCL clock tHIGH 4.0 ⎯ 0.6 ⎯ µs Set-up time for a repeated START condition SCL↑→SDA↓ tSUSTA 4.7 ⎯ 0.6 ⎯ µs Data hold time SCL↓→SDA↓↑ tHDDAT 0 3.45*2 0 0.9*3 µs Data set-up time SDA↓↑→SCL↑ tSUDAT 250 ⎯ 100 ⎯ ns Set-up time for STOP condition SCL↑→SDA↑ tSUSTO 4.0 ⎯ 0.6 ⎯ µs 4.7 ⎯ 1.3 ⎯ µs Bus free time between a STOP and START condition AR Hold time (repeated) START condition SDA↓→SCL↓ R = 1.7 kΩ, C = 50 pF*1 IN SCL clock frequency Y Min tBUS IM *1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. EL *4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. SDA tSUDAT SCL tHDSTA 2008-4-18 PR tLOW tHDDAT tHIGH tBUS tHDSTA tSUSTA tSUSTO 91 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 92 2008-4-18 MB96390 Series FME-MB96390 rev 1 5. Analog Digital Converter (TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Resolution - Total error Value Unit Typ Max - - - 10 bit - - -3 - +3 LSB Nonlinearity error - - -2.5 - +2.5 LSB Differential nonlinearity error - - -1.9 - VOT ANn AVRL 1.5 AVRL+ 0.5 VFST ANn AVRH 3.5 Compare time - - Sampling time - - Analog port input current IAIN ANn Analog input voltage range VAIN Reference voltage range Reference voltage current Offset between input channels AVRL + LSB 2.5 AR 2.0 LSB AVRH - AVRH + LSB 1.5 0.5 - 16,500 µs 4.5V ≤ ΑVCC ≤ 5.5V - - µs 3.0V ≤ ΑVCC < 4.5V 0.5 - - µs 4.5V ≤ ΑVCC ≤ 5.5V 1.2 - - µs 3.0V ≤ ΑVCC < 4.5V -1 - +1 µA TA = 25 ˚C -3 - +3 µA TA = 125 ˚C ANn AVRL - AVRH V AVRH AVRH 0.75 AVcc - AVcc V AVRL AVRL AVSS - 0.25 AVCC V IA AVcc - 2.5 5 mA AD Converter active IAH AVcc - - 5 µA AD Converter not operated IR AVRH/ AVRL - 0.7 1 mA AD Converter active IRH AVRH/ AVRL - - 5 µA AD Converter not operated - ANn - - TBD LSB PR Power supply current 1.0 +1.9 IN voltage IM Full scale reading EL Zero reading voltage Remarks Y Min Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller. Definition of A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and linear error. 2008-4-18 93 MB96390 Series FME-MB96390 rev 1 Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics. Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Y Total error 3FE AR 3FF 1.5 LSB Actual conversion characteristics {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (Actually-measured value) IN Digital output 3FD 003 Actual conversion characteristics Ideal characteristics 002 0.5 LSB AVRL IM 001 AVRH Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL 1 LSB = (Ideal value) [V] 1024 [LSB] EL Total error of digital output “N” = N: A/D converter digital output value VOT (Ideal value) = AVRL + 0.5 LSB [V] PR VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N − 1) to N. 94 2008-4-18 MB96390 Series FME-MB96390 rev 1 Non linearity error Differential linearity error Ideal characteristics 3FF Actual conversion characteristics {1 LSB × (N − 1) + VOT } VNT (actual measurement value) 004 Actual conversion characteristics 003 002 Ideal characteristics N N−1 N−2 001 VOT (actual measurement value) AVRL Y VFST (actual measurement value) Actual conversion characteristics AR Digital output 3FD N+1 Digital output 3FE AVRH Actual conversion characteristics AVRL Non linearity error of digital output N = IM Differential linearity error of digital output N = 1 LSB = AVRH Analog input IN Analog input V (N + 1) T (actual measurement value) VNT (actual measurement value) VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 [LSB] −1 LSB [LSB] [V] EL N : A/D converter digital output value VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” PR Notes on A/D Converter Section • About the external impedance of the analog input and the sampling time of the A/D converter (with sample and hold circuit): If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • analog input circuit model: R Comparator Analog input C Sampling switch Reference value: • C = 8.5 pF (Max) 2008-4-18 95 MB96390 Series FME-MB96390 rev 1 To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum sampling time must be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be decreased so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7τ, where τ = RC. If the external input resistance (Rext) connected to the analog input is included, the sampling time is expressed as follows: Tsamp [min] = 7 × (Rext + 2.6kΩ) × C for 4.5 ≤ AVcc ≤ 5.5 Tsamp [min] = 7 × (Rext + 12.1kΩ) × C for 3.0 ≤ AVcc ≤ 4.5 • About the error PR EL IM IN AR The accuracy gets worse as |AVRH - AVRL| becomes smaller. Y If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. 96 2008-4-18 MB96390 Series FME-MB96390 rev 1 6. Alarm Comparator (TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V) Value Pin IA5ALMF Power supply current AVCC IA5ALMS IA5ALMH ALARM pin input voltage range VALIN External low threshold high->low transition VEVTL(H->L) External low threshold low->high transition VEVTL(L->H) External high threshold high->low transition VEVTH(H->L) External high threshold low->high transition VEVTH(L->H) Internal low threshold high->low transition VIVTL(H->L) Internal low threshold low->high transition µA Alarm comparator enabled in fast mode (one channel) 10 µA Alarm comparator enabled in slow mode (one channel) 5 µA Alarm comparator disabled - +1 µA TA = 25 ˚C - +3 µA TA = 125 ˚C - AVCC Max - 25 40 - 7 - - -1 -3 0 0.36 * AVCC 0.36 * AVCC -0.25 -0.1 0.36 * AVCC 0.36 * AVCC +0.1 +0.25 0.78 * AVCC 0.78 * AVCC -0.25 -0.1 ALARM0, ALARM1 V V IN IALIN Remarks Typ IM ALARM pin input current Unit Min Y Symbol AR Parameter V INTREF = 0 V 0.78 * AVCC 0.78 * AVCC +0.1 +0.25 V 1.1 - V VIVTL(L->H) - 1.3 1.55 V Internal high threshold high->low transition VIVTH(H->L) 2.2 2.4 - V Internal high threshold low->high transition VIVTH(L->H) - 2.6 2.85 V VHYS 50 - 300 mV tCOMPF - 0.3 2 µs CMD = 1 (fast) tCOMPS - 2 100 µs CMD = 0 (slow) PR Switching hysteresis Comparison time 2008-4-18 EL 0.9 INTREF = 1 97 MB96390 Series FME-MB96390 rev 1 Comparator Output Y H VxVTx(H->L) AR L VHYS PR EL IM IN VxVTx(L->H) VALIN 98 2008-4-18 MB96390 Series FME-MB96390 rev 1 7. Low Voltage Detector characteristics (TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V) Parameter Symbol Stabilization time Value Unit Remarks Max TLVDSTAB 60 75 µs Level 0 VDL0 2.7 2.9 V CILCR:LVL[3:0]=”0000” Level 1 VDL1 2.9 3.1 V CILCR:LVL[3:0]=”0001” Level 2 VDL2 3.1 3.3 V CILCR:LVL[3:0]=”0010” Level 3 VDL3 3.5 3.75 V CILCR:LVL[3:0]=”0011” Level 4 VDL4 3.6 3.85 V CILCR:LVL[3:0]=”0100” Level 5 VDL5 3.7 3.95 V CILCR:LVL[3:0]=”0101” Level 6 VDL6 3.8 4.05 V CILCR:LVL[3:0]=”0110” Level 7 VDL7 3.9 4.15 V CILCR:LVL[3:0]=”0111” Level 8 VDL8 4.0 4.25 V CILCR:LVL[3:0]=”1000” Level 9 VDL9 4.1 4.35 V CILCR:LVL[3:0]=”1001” Level 10 VDL10 not used Level 11 VDL11 not used Level 12 VDL12 not used Level 13 VDL13 not used Level 14 VDL14 Level 15 VDL15 IM IN AR Y Min not used EL not used Levels 10 to 15 are not used in this device. V For correct detection, the slope of the voltage level must satisfy dV ≤ 0.004 ----- . dt µs Faster variations are regarded as noise and may not be detected. PR The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7V. The electrical characteristics however are only valid in the specified range (usually down to 3.0V). 2008-4-18 99 MB96390 Series FME-MB96390 rev 1 Low Voltage Detector Operation In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. Voltage [V] VCC Y VDLx, Max VDLx, Min dV AR dt Low Voltage Reset Assertion Power Reset Extension Time PR EL IM IN Normal Operation Time [s] 2008-4-18 100 MB96390 Series FME-MB96390 rev 1 8. FLASH memory program/erase characteristics (TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V) Value Unit Remarks 3.6 s Erasure programming time not included n*0.9 n*3.6 s n is the number of Flash sector of the device 23 370 us System overhead time not included Min Typ Max Sector erase time - 0.9 Chip erase time - Word (16-bit width) programming time - cycle Flash data retention time year AR Programme/Erase cycle 10 000 Y Parameter 20 *1 PR EL IM IN *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) 2008-4-18 101 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 102 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ PACKAGE DIMENSION MB96F39x LQFP 100P Lead pitch 0.50 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max AR Y 100-pin plastic LQFP 100-pin plastic LQFP (FPT-100P-M20) 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 51 76 1 EL PR 100 0.50(.020) 2005 FUJITSU LIMITED F100031S-c-2-1 2008-4-18 P-LFQFP100-14×14-0.50 50 INDEX C Code (Reference) IM 75 0.65 g IN (FPT-100P-M20) Weight 0.20±0.05 (.008±.002) 0.08(.003) Details of "A" part +0.20 +.008 1.50 –0.10 .059 –.004 (Mounting height) 26 0˚~8˚ "A" (0.50(.020)) 0.25(.010) 0.60±0.15 (.024±.006) 25 0.08(.003) 0.10±0.10 (.004±.004) (Stand off) M 0.145±0.055 (.0057±.0022) Dimensions in mm (inches). Note: The values in parentheses are reference values 103 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 104 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ ORDERING INFORMATION Subclock MB96F395YSA PMC-GSE2 *1 MB96F395RSA PMC-GSE2 *1 MB96F395YWA PMC-GSE2 Persistent Low Voltage Reset No 100 pin Plastic LQFP (FPT-100P-M20) Yes Yes No Yes 416 pin Plastic BGA For evaluation (BGA416-M02) No AR MB96V300BRB-ES Remarks Yes No *1 MB96F395RWA PMC-GSE2 *1 Package Y Part number PR EL IM IN *1: These devices are under development and specification is preliminary. These products under development may change its specification without notice. 2008-4-18 105 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 106 2008-4-18 MB96390 Series FME-MB96390 rev 1 ■ REVISION HISTORY Revision Modification 2008-04-18 Initial Draft PR EL IM IN AR Y Prelim 1 Date 2008-4-18 107 MB96390 Series FME-MB96390 rev 1 FUJITSU LIMITED PR EL AR IM IN The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Y All Rights Reserved. Edited Strategic Business Development Dept. MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 MB96390 Series PR EL IM IN AR Y FME-MB96390 rev 1 110 2008-4-18