MB96F633ABPMC-GSE1

MB96630 Series F2MC-16FX 16-Bit Microcontroller MB96630 series is based on Cypress’s advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like 2 performance). The CPU uses the same instruction set as the established F MC-16LX family thus allowing for easy migration of 2 2 F MC-16LX Software to the new F MC-16FX products. F2MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features  Technology  DMA 0.18m CMOS Automatic transfer function independent of CPU, can be assigned freely to resources  CPU F 2 MC-16FX CPU instruction set for controller applications (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers)  8-byte instruction queue  Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available  Interrupts  Fast Interrupt processing programmable priority levels  Non-Maskable Interrupt (NMI)  Optimized 8  CAN  Supports CAN protocol version 2.0 part A and B certified  Bit rates up to 1Mbps  32 message objects  Each message object has its own identifier mask  Programmable FIFO mode (concatenation of message objects)  Maskable interrupt  Disabled Automatic Retransmission mode for Time Triggered CAN applications  Programmable loop-back mode for self-test operation  ISO16845  System clock PLL clock multiplier (1 to 8, 1 when PLL stop) to 8MHz crystal oscillator (maximum frequency when using ceramic resonator depends on Q-factor)  Up to 8MHz external clock for devices with fast clock input feature  32.768kHz subsystem quartz clock  100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog  Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals  The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power or External reset  Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)  On-chip  4MHz  USART  Full duplex USARTs (SCI/LIN) range of baud rate settings using a dedicated reload timer  Special synchronous options for adapting to different synchronous serial protocols  LIN functionality working either as master or slave LIN device  Extended support for LIN-Protocol to reduce interrupt load  Wide  On-chip voltage regulator Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption  I2 C  Low voltage detection function  Up to 400kbps and Slave functionality, 7-bit and 10-bit addressing  Master Reset is generated when supply voltage falls below programmable reference voltage  Code Security Protects Flash Memory content from unintended read-out Cypress Semiconductor Corporation Document Number: 002-04719 Rev.*A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 19, 2016 MB96630 Series  A/D converter  Real Time Clock  SAR-type  Operational  8/10-bit resolution  Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger, reload timers and PPGs  Range Comparator Function  Scan Disable Function  Source Clock Timers Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)  Hardware Watchdog Timer  Hardware watchdog timer is active after reset function of Watchdog Timer is used to select the lower window limit of the watchdog interval  Window  Reload Timers  16-bit wide 1 2 3 4 5 6  Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency  Event count function  Free-Running Timers  Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4) 1 2 3 4 5 6 7 8  Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency  Input Capture Units  16-bit wide an interrupt upon external event  Rising edge, Falling edge or Both (rising & falling) edges sensitive  Signals  Output Compare Units  16-bit wide  Signals an interrupt when a match with Free-running Timer occurs  A pair of compare registers can be used to generate an output signal  Programmable Pulse Generator  16-bit down counter, cycle and duty setting registers be used as 2 × 8-bit PPG  Interrupt at trigger, counter borrow and/or duty match  PWM operation and one-shot operation  Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer underflow as clock input  Can be triggered by software or reload timer  Can trigger ADC conversion  Timing point capture  Start delay  Can  Quadrature Position/Revolution Counter (QPRC)  Up/down count mode, Phase difference count mode, Count mode with direction  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers with interrupt  Detection edge of the three external event input pins AIN, BIN and ZIN is configurable Document Number: 002-04719 Rev.*A on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)  Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)  Read/write accessible second/minute/hour registers  Can signal interrupts every half second/second/minute/hour/day  Internal clock divider and prescaler provide exact 1s clock  External Interrupts  Edge or Level sensitive mask bit per channel  Each available CAN channel RX has an external interrupt for wake-up  Selected USART channels SIN have an external interrupt for wake-up  Interrupt  Non Maskable Interrupt  Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block  Once enabled, can not be disabled other than by reset  High or Low level sensitive  Pin shared with external interrupt 0  I/O Ports  Most of the external pins can be used as general purpose I/O 2  All push-pull outputs (except when used as I C SDA/SCL line)  Bit-wise programmable as input/output or peripheral signal  Bit-wise programmable input enable  One input level per GPIO-pin (either Automotive or CMOS hysteresis)  Bit-wise programmable pull-up resistor  Built-in On Chip Debugger (OCD)  One-wire debug tool interface function: • Hardware break: 6 points (shared with code event) • Software break: 4096 points  Event function • Code event: 6 points (shared with hardware break) • Data event: 6 points • Event sequencer: 2 levels + reset  Execution time measurement function  Trace function: 42 branches  Security function  Break  Flash Memory  Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank  Command sequencer for automatic execution of programming algorithm and for supporting DMA for programming of the Flash Memory  Supports automatic programming, Embedded Algorithm  Write/Erase/Erase-Suspend/Resume commands  A flag indicating completion of the automatic algorithm  Erase can be performed on each sector individually  Sector protection  Flash Security feature to protect the content of the Flash  Low voltage detection during Flash erase or write Page 2 of 69 MB96630 Series Contents 1. Product Lineup .................................................................................................................................................................. 5 2. Block Diagram ................................................................................................................................................................... 6 3. Pin Assignment ................................................................................................................................................................. 7 4. Pin Description .................................................................................................................................................................. 8 5. Pin Circuit Type ............................................................................................................................................................... 10 6. I/O Circuit Type ............................................................................................................................................................... 13 7. Memory Map .................................................................................................................................................................... 18 8. RAMSTART Addresses................................................................................................................................................... 19 9. User ROM Memory Map For Flash Devices .................................................................................................................. 20 10. Serial Programming Communication Interface ............................................................................................................ 21 11. Interrupt Vector Table ..................................................................................................................................................... 22 12. Handling Precautions ..................................................................................................................................................... 26 12.1 Precautions for Product Design ................................................................................................................................... 26 12.2 Precautions for Package Mounting .............................................................................................................................. 27 12.3 Precautions for Use Environment ................................................................................................................................ 28 13. Handling Devices ............................................................................................................................................................ 29 13.1 Latch-up prevention ..................................................................................................................................................... 29 13.2 Unused pins handling .................................................................................................................................................. 29 13.3 External clock usage ................................................................................................................................................... 30 13.3.1 Single phase external clock for Main oscillator............................................................................................................. 30 13.3.2 Single phase external clock for Sub oscillator .............................................................................................................. 30 13.3.3 Opposite phase external clock ..................................................................................................................................... 30 13.4 Notes on PLL clock mode operation ............................................................................................................................ 30 13.5 Power supply pins (Vcc/Vss) ......................................................................................................................................... 30 13.6 Crystal oscillator and ceramic resonator circuit ........................................................................................................... 31 13.7 Turn on sequence of power supply to A/D converter and analog inputs ..................................................................... 31 13.8 Pin handling when not using the A/D converter ........................................................................................................... 31 13.9 Notes on Power-on ...................................................................................................................................................... 31 13.10 Stabilization of power supply voltage .......................................................................................................................... 31 13.11 Serial communication .................................................................................................................................................. 31 13.12 Mode Pin (MD) ............................................................................................................................................................ 31 14. Electrical Characteristics ............................................................................................................................................... 32 14.1 Absolute Maximum Ratings ......................................................................................................................................... 32 14.2 Recommended Operating Conditions ......................................................................................................................... 34 14.3 DC Characteristics ...................................................................................................................................................... 35 14.3.1 Current Rating .............................................................................................................................................................. 35 14.3.2 Pin Characteristics ....................................................................................................................................................... 39 14.4 AC Characteristics ....................................................................................................................................................... 41 14.4.1 Main Clock Input Characteristics .................................................................................................................................. 41 14.4.2 Sub Clock Input Characteristics ................................................................................................................................... 42 14.4.3 Built-in RC Oscillation Characteristics .......................................................................................................................... 43 14.4.4 Internal Clock Timing ................................................................................................................................................... 43 14.4.5 Operating Conditions of PLL ........................................................................................................................................ 44 14.4.6 Reset Input ................................................................................................................................................................... 44 14.4.7 Power-on Reset Timing ................................................................................................................................................ 45 14.4.8 USART Timing ............................................................................................................................................................. 46 Document Number: 002-04719 Rev.*A Page 3 of 69 MB96630 Series 14.4.9 External Input Timing ................................................................................................................................................... 48 14.4.10 I2C Timing ................................................................................................................................................................. 49 14.5 A/D Converter .............................................................................................................................................................. 50 14.5.1 Electrical Characteristics for the A/D Converter ........................................................................................................... 50 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time ......................................................................................... 51 14.5.3 Definition of A/D Converter Terms ............................................................................................................................... 52 14.6 Low Voltage Detection Function Characteristics ......................................................................................................... 54 14.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 56 15. Example Characteristics ................................................................................................................................................ 57 16. Ordering Information ...................................................................................................................................................... 60 17. Package Dimension ........................................................................................................................................................ 61 18. Major Changes ................................................................................................................................................................ 62 Document History ................................................................................................................................................................. 68 Document Number: 002-04719 Rev.*A Page 4 of 69 MB96630 Series 1. Product Lineup Features Product Type Subclock Dual Operation Flash Memory 64.5KB + 32KB 128.5KB + 32KB 256.5KB + 32KB 384.5KB + 32KB RAM 10KB 16KB 24KB 28KB Package DMA USART with automatic LIN-Header transmission/reception with 16 byte RX-and TX-FIFO 2 MB96630 Flash Memory Product Subclock can be set by software MB96F633R, MB96F633A MB96F635R, MB96F635A MB96F636R MB96F637R LQFP-80 FPT-80P-M21 4ch 5ch Product Options R: MCU with CAN A: MCU without CAN Yes (only 1ch) LIN-USART 0 2ch 8/10-bit A/D Converter 21ch with Data Buffer with Range Comparator with Scan Disable with ADC Pulse Detection 16-bit Reload Timer (RLT) 16-bit Free-Running Timer (FRT) No Yes Yes No 3ch 3ch 7ch (1 channel for LIN-USART) 16-bit Output Compare Unit (OCU) 7ch 8/16-bit Programmable Pulse Generator (PPG) with Timing point capture with Start delay with Ramp Quadrature Position/Revolution Counter (QPRC) 15ch (16-bit) / 20ch (8-bit) Yes Yes No CAN Interface 1ch External Interrupts (INT) Non-Maskable Interrupt (NMI) Real Time Clock (RTC) Clock Calibration Unit (CAL) Clock Output Function 15ch 1ch 1ch 62 (Dual clock mode) 64 (Single clock mode) 1ch 2ch Low Voltage Detection Function Yes Hardware Watchdog Timer On-chip RC-oscillator On-chip Debugger Yes Yes Yes I/O Ports LIN-USART 0/2/4/5/7 No IC 16-bit Input Capture Unit (ICU) Remark 2ch I2C 0/1 AN 2 to 4/6 to 8/ 10 to 12/15 to 17/20 to 28 RLT 0/1/6 FRT 0 to 2 ICU 0/1/4 to 7/9 (ICU 9 for LIN-USART) OCU 0 to 4/6/7 (OCU 4 for FRT clear) PPG 0 to 4/6 to 15 QPRC 0/1 CAN 0 32 Message Buffers INT 0 to 13/15 Low voltage detection function can be disabled by software Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the general I/O port according to your function use. Document Number: 002-04719 Rev.*A Page 5 of 69 MB96630 Series 2. Block Diagram DEBUG I/F CKOT0_R, CKOT1, CKOT1_R CKOTX0, CKOTX1, CKOTX1_R X0, X1 X0A, X1A RSTX MD NMI Interrupt Controller 16FX CPU OCD Flash Memory A Clock & Mode Controller 16FX Core Bus (CLKB) Peripheral Bus Bridge Watchdog AVcc AVss AVRH AN2 to AN4, AN6 to AN8 AN10 to AN12, AN15 to AN17 AN20 to AN28 ADTG TIN0, TIN1 TOT0, TOT1 FRCK0, FRCK0_R IN0, IN0_R, IN1_R OUT0 to OUT3 OUT0_R, OUT2_R FRCK1 IN6, IN7 IN4_R, IN5_R, IN7_R OUT6, OUT7 FRCK2 INT0, INT4 to INT13, INT15 INT1_R to INT3_R INT6_R, INT7_R Document Number: 002-04719 Rev.*A 2 IC 2ch 8/10-bit ADC 21ch 16-bit Reload Timer 0/1/6 3ch I/O Timer 0 FRT0 ICU 0/1 OCU 0/1/2/3 I/O Timer 1 FRT1 ICU 4/5/6/7 OCU 4/6/7 Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) SDA0, SDA1 SCL0, SCL1 RAM CAN Interface 1ch USART 5ch Peripheral Bus 1 (CLKP1) DMA Controller PPG 15ch (16-bit)/ 20ch (8-bit) RX0 Voltage Regulator Vcc Vss C TX0 SIN0, SIN2, SIN4, SIN5, SIN7, SIN5_R, SIN7_R SOT0, SOT2, SOT4, SOT7, SOT5_R, SOT7_R SCK0, SCK2, SCK4, SCK5_R, SCK7_R TTG0, TTG2 to TTG4, TTG6, TTG7, TTG12 to TTG14 PPG0, PPG1, PPG3, PPG4, PPG6 PPG0_R to PPG2_R, PPG8_R to PPG13_R PPG6_B to PPG11_B, PPG14_B, PPG15_B AIN0, AIN1 QPRC 2ch BIN0, BIN1 ZIN0, ZIN1 I/O Timer 2 FRT2 ICU 9 External Interrupt 15ch Boot ROM Real Time Clock WOT, WOT_R Page 6 of 69 MB96630 Series 3. Pin Assignment Vss Vss DEBUG I/F P17_0 MD X0 X1 Vss P04_0 / X0A *3 P04_1 / X1A *3 RSTX P11_1 / PPG0_R P11_2 / PPG1_R P11_3 / PPG2_R P11_6 / FRCK0_R / ZIN1 P11_7 / IN0_R / AIN1 P12_0 / IN1_R / BIN1 P12_3 / OUT2_R P12_7 / INT1_R P00_0 / INT3_R / FRCK2 Vcc (Top view) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 61 Vcc P00_3 / INT6_R / PPG8_B 62 39 P10_2 / SCK2 / PPG6 *1 P00_4 / INT7_R / PPG9_B 63 38 P10_1 / SOT2 P00_5 / IN6 / TTG2 / TTG6 / PPG10_B 64 37 P10_0 / SIN2 / AN28 / INT11 *1 P00_6 / IN7 / TTG3 / TTG7 / PPG11_B 65 36 P17_2 / PPG13_R P01_1 / CKOT1 / OUT0 / SOT7 66 35 P17_1 / PPG12_R P01_2 / CKOTX1 / OUT1 / INT15 / SIN7 *1 67 34 P09_3 / AN27 / PPG11_R P01_4 / SIN4 / INT8 *1 68 33 P09_2 / AN26 / PPG10_R P01_5 / SOT4 69 32 P09_1 / AN25 / PPG9_R P01_6 / SCK4 / TTG12 *1 70 31 P09_0 / AN24 / PPG8_R P01_7 / CKOTX1_R / INT9 / TTG13 / ZIN0 / SCK7_R *1 71 30 P08_7 / AN23 / PPG7_B P02_0 / CKOT1_R / INT10 / TTG14 / AIN0 / SOT7_R 72 29 P08_6 / AN22 / PPG6_B P02_2 / IN7_R / CKOT0_R / INT12 / BIN0 / SIN7_R *1 73 28 P08_5 / AN21 / OUT7 P02_5 / OUT0_R / INT13 / SIN5_R *1 74 27 P04_7 / SCL1*2 P03_2 / PPG14_B / SOT5_R 75 26 P04_6 / SDA1*2 P03_3 / PPG15_B / SCK5_R *1 76 25 P08_4 / AN20 / OUT6 P03_4 / RX0 / INT4 *1 77 24 P08_1 / AN17 P03_5 / TX0 78 23 P08_0 / AN16 P03_6 / INT0 / NMI 79 22 P05_7 / AN15 Vcc 80 21 P05_4 / AN12 / INT2_R / WOT_R P05_3 / AN11 / OUT3 P05_2 / AN10 / OUT2 P05_0 / AN8 AVss AVRH AVcc P06_7 / AN7 / TOT1 / IN5_R 10 11 12 13 14 15 16 17 18 19 20 P06_6 / AN6 / TIN1 / IN4_R 9 P06_4 / AN4 / IN0 / TTG0 / TTG4 8 P06_3 / AN3 / FRCK0 P13_3 / PPG1 / TOT0 / WOT 7 P06_2 / AN2 / INT5 / SIN5 *1 P13_2 / PPG0 / TIN0 / FRCK1 6 P04_5 / PPG4 / SCL0 *2 C 5 P04_4 / PPG3 / SDA0 *2 4 P13_6 / SCK0 / CKOTX0 *1 3 P13_5 / SOT0 / ADTG / INT7 2 P13_4 / SIN0 / INT6 *1 1 Vss LQFP - 80 (FPT-80P-M21) *1 : CMOS input level only *2 : CMOS input level only for I2C *3 : Please set ROM Configuration Block (RCB) to use the subclock. Other than those above, general-purpose pins have only Automotive input level. Document Number: 002-04719 Rev.*A Page 7 of 69 MB96630 Series 4. Pin Description Pin name Feature Description ADTG ADC A/D converter trigger input pin AINn QPRC Quadrature Position/Revolution Counter Unit n input pin ANn ADC A/D converter channel n input pin AVcc Supply Analog circuits power supply pin AVRH ADC A/D converter high reference voltage input pin AVss Supply Analog circuits power supply pin BINn QPRC Quadrature Position/Revolution Counter Unit n input pin C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock Output function Clock Output function n output pin CKOTn_R Clock Output function Relocated Clock Output function n output pin CKOTXn Clock Output function Clock Output function n inverted output pin CKOTXn_R Clock Output function Relocated Clock Output function n inverted output pin DEBUG I/F OCD On Chip Debugger input/output pin FRCKn Free-Running Timer Free-Running Timer n input pin FRCKn_R Free-Running Timer Relocated Free-Running Timer n input pin INn ICU Input Capture Unit n input pin INn_R ICU Relocated Input Capture Unit n input pin INTn External Interrupt External Interrupt n input pin INTn_R External Interrupt Relocated External Interrupt n input pin MD Core Input pin for specifying the operating mode NMI External Interrupt Non-Maskable Interrupt input pin OUTn OCU Output Compare Unit n waveform output pin OUTn_R OCU Relocated Output Compare Unit n waveform output pin Pnn_m GPIO General purpose I/O pin PPGn PPG Programmable Pulse Generator n output pin (16bit/8bit) PPGn_R PPG Relocated Programmable Pulse Generator n output pin (16bit/8bit) PPGn_B PPG Programmable Pulse Generator n output pin (16bit/8bit) RSTX Core Reset input pin RXn CAN CAN interface n RX input pin SCKn USART USART n serial clock input/output pin SCKn_R USART Relocated USART n serial clock input/output pin 2 SCLn IC I2C interface n clock I/O input/output pin SDAn I2C I2C interface n serial data I/O input/output pin SINn USART USART n serial data input pin SINn_R USART Relocated USART n serial data input pin SOTn USART USART n serial data output pin SOTn_R USART Relocated USART n serial data output pin TINn Reload Timer Reload Timer n event input pin TOTn Reload Timer Reload Timer n output pin TTGn PPG Programmable Pulse Generator n trigger input pin Document Number: 002-04719 Rev.*A Page 8 of 69 MB96630 Series Pin name Feature Description TXn CAN CAN interface n TX output pin Vcc Supply Power supply pin Vss Supply Power supply pin WOT RTC Real Time clock output pin WOT_R RTC Relocated Real Time clock output pin X0 Clock Oscillator input pin X0A Clock Subclock Oscillator input pin X1 Clock Oscillator output pin X1A Clock Subclock Oscillator output pin ZINn QPRC Quadrature Position/Revolution Counter Unit n input pin Document Number: 002-04719 Rev.*A Page 9 of 69 MB96630 Series 5. Pin Circuit Type Pin no. I/O circuit type* Pin name 1 Supply Vss 2 F C 3 H P13_2 / PPG0 / TIN0 / FRCK1 4 H P13_3 / PPG1 / TOT0 / WOT 5 M P13_4 / SIN0 / INT6 6 H P13_5 / SOT0 / ADTG / INT7 7 M P13_6 / SCK0 / CKOTX0 8 N P04_4 / PPG3 / SDA0 9 N P04_5 / PPG4 / SCL0 10 I P06_2 / AN2 / INT5 / SIN5 11 K P06_3 / AN3 / FRCK0 12 K P06_4 / AN4 / IN0 / TTG0 / TTG4 13 K P06_6 / AN6 / TIN1 / IN4_R 14 K P06_7 / AN7 / TOT1 / IN5_R 15 Supply AVcc 16 G AVRH 17 Supply AVss 18 K P05_0 / AN8 19 K P05_2 / AN10 / OUT2 20 K P05_3 / AN11 / OUT3 21 K P05_4 / AN12 / INT2_R / WOT_R 22 K P05_7 / AN15 23 K P08_0 / AN16 24 K P08_1 / AN17 25 K P08_4 / AN20 / OUT6 26 N P04_6 / SDA1 27 N P04_7 / SCL1 28 K P08_5 / AN21 / OUT7 29 K P08_6 / AN22 / PPG6_B 30 K P08_7 / AN23 / PPG7_B 31 K P09_0 / AN24 / PPG8_R 32 K P09_1 / AN25 / PPG9_R 33 K P09_2 / AN26 / PPG10_R 34 K P09_3 / AN27 / PPG11_R 35 H P17_1 / PPG12_R 36 H P17_2 / PPG13_R 37 I P10_0 / SIN2 / AN28 / INT11 38 H P10_1 / SOT2 Document Number: 002-04719 Rev.*A Page 10 of 69 MB96630 Series Pin no. I/O circuit type* Pin name 39 M P10_2 / SCK2 / PPG6 40 Supply Vcc 41 Supply Vss 42 O DEBUG I/F 43 H P17_0 44 C MD 45 A X0 46 A X1 47 Supply Vss 48 B P04_0 / X0A 49 B P04_1 / X1A 50 C RSTX 51 H P11_1 / PPG0_R 52 H P11_2 / PPG1_R 53 H P11_3 / PPG2_R 54 H P11_6 / FRCK0_R / ZIN1 55 H P11_7 / IN0_R / AIN1 56 H P12_0 / IN1_R / BIN1 57 H P12_3 / OUT2_R 58 H P12_7 / INT1_R 59 H P00_0 / INT3_R / FRCK2 60 Supply Vcc 61 Supply Vss 62 H P00_3 / INT6_R / PPG8_B 63 H P00_4 / INT7_R / PPG9_B 64 H P00_5 / IN6 / TTG2 / TTG6 / PPG10_B 65 H P00_6 / IN7 / TTG3 / TTG7 / PPG11_B 66 H P01_1 / CKOT1 / OUT0 / SOT7 67 M P01_2 / CKOTX1 / OUT1 / INT15 / SIN7 68 M P01_4 / SIN4 / INT8 69 H P01_5 / SOT4 70 M P01_6 / SCK4 / TTG12 71 M P01_7 / CKOTX1_R / INT9 / TTG13 / ZIN0 / SCK7_R 72 H P02_0 / CKOT1_R / INT10 / TTG14 / AIN0 / SOT7_R 73 M P02_2 / IN7_R / CKOT0_R / INT12 / BIN0 / SIN7_R 74 M P02_5 / OUT0_R / INT13 / SIN5_R 75 H P03_2 / PPG14_B / SOT5_R 76 M P03_3 / PPG15_B / SCK5_R 77 M P03_4 / RX0 / INT4 Document Number: 002-04719 Rev.*A Page 11 of 69 MB96630 Series Pin no. I/O circuit type* Pin name 78 H P03_5 / TX0 79 H P03_6 / INT0 / NMI 80 Supply Vcc *: See “I/O Circuit Type” for details on the I/O circuit types. Document Number: 002-04719 Rev.*A Page 12 of 69 MB96630 Series 6. I/O Circuit Type Circuit Type A X1 R 0 1 X out Remarks High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Feedback resistor = approx. 1.0MΩ • The amplitude: 1.8V±0.15V to operate by the internal supply voltage FCI X0 FCI or Osc disable Document Number: 002-04719 Rev.*A Page 13 of 69 MB96630 Series Circuit Type B Pull-up control P-ch Standby control for input shutdown P-ch Pout N-ch Nout Remarks Low-speed oscillation circuit shared with GPIO functionality: • Feedback resistor = approx. 5.0MΩ • GPIO functionality selectable (CMOS level output (IOL = 4mA, IOH = -4mA), Automotive input with input shutdown function and programmable pull-up resistor) R Automotive input X1A R X out 0 1 FCI X0A FCI or Osc disable Pull-up control P-ch Standby control for input shutdown P-ch Pout N-ch Nout R C Document Number: 002-04719 Rev.*A Automotive input CMOS hysteresis input pin Page 14 of 69 MB96630 Series Circuit Type F Remarks Power supply input protection circuit P-ch N-ch • A/D converter ref+ (AVRH) power supply input pin with protection circuit • Without protection circuit against VCC for pins AVRH G P-ch N-ch H Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor R Standby control for input shutdown Automotive input I Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor • Analog input R Hysteresis input Standby control for input shutdown Analog input Document Number: 002-04719 Rev.*A Page 15 of 69 MB96630 Series Circuit Type K Remarks Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor • Analog input R Automotive input Standby control for input shutdown Analog input M Pull-up control P-ch P-ch Pout N-ch Nout R • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor Hysteresis input Standby control for input shutdown N Pull-up control P-ch R P-ch Pout N-ch Nout* • CMOS level output (IOL = 3mA, IOH = -3mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor *: N-channel transistor has slew rate control according to I2C spec, irrespective of usage. Hysteresis input Standby control for input shutdown Document Number: 002-04719 Rev.*A Page 16 of 69 MB96630 Series Circuit Type O Remarks • Open-drain I/O • Output 25mA, Vcc = 2.7V • TTL input N-ch Nout R Standby control for input shutdown Document Number: 002-04719 Rev.*A TTL input Page 17 of 69 MB96630 Series 7. Memory Map FF:FFFFH USER ROM*1 DE:0000H DD:FFFFH Reserved 10:0000H 0F:C000H Boot-ROM Peripheral 0E:9000H Reserved 01:0000H 00:8000H RAMSTART0*2 ROM/RAM MIRROR Internal RAM bank0 Reserved 00:0C00H 00:0380H Peripheral 00:0180H GPR*3 00:0100H DMA 00:00F0H Reserved 00:0000H Peripheral *1 : For details about USER ROM area, see “User ROM Memory Map For Flash Devices” on the following pages. *2 : For RAMSTART Addresses, see the table on the next page. *3 : Unused GPR banks can be used as RAM area. GPR: General-Purpose Register The DMA area is only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. Document Number: 002-04719 Rev.*A Page 18 of 69 MB96630 Series 8. RAMSTART Addresses Bank 0 RAM size Devices RAMSTART0 MB96F633 10KB 00:5A00H MB96F635 16KB 00:4200H MB96F636 24KB 00:2200H MB96F637 28KB 00:1200H Document Number: 002-04719 Rev.*A Page 19 of 69 MB96630 Series 9. User ROM Memory Map For Flash Devices CPU mode address Flash memory mode address FF:FFFFH 3F:FFFFH FF:0000H 3F:0000H FE:FFFFH 3E:FFFFH FE:0000H 3E:0000H FD:FFFFH 3D:FFFFH FD:0000H 3D:0000H FC:FFFFH 3C:FFFFH FC:0000H 3C:0000H FB:FFFFH 3B:FFFFH FB:0000H 3B:0000H FA:FFFFH 3A:FFFFH FA:0000H 3A:0000H MB96F633 MB96F635 MB96F636 Flash size Flash size Flash size MB96F637 Flash size 64.5KB + 32KB 128.5KB + 32KB 256.5KB + 32KB 384.5KB + 32KB SA39 - 64KB SA39 - 64KB SA39 - 64KB SA39 - 64KB SA38 - 64KB SA38 - 64KB SA38 - 64KB SA37 - 64KB SA37 - 64KB SA36 - 64KB SA36 - 64KB Bank A of Flash A SA35 - 64KB SA34 - 64KB F9:FFFFH Reserved Reserved Reserved Reserved DF:A000H DF:9FFFH 1F:9FFFH DF:8000H 1F:8000H DF:7FFFH 1F:7FFFH DF:6000H 1F:6000H DF:5FFFH 1F:5FFFH DF:4000H 1F:4000H DF:3FFFH 1F:3FFFH DF:2000H 1F:2000H DF:1FFFH 1F:1FFFH DF:0000H 1F:0000H DE:FFFFH DE:0000H SA4 - 8KB SA4 - 8KB SA4 - 8KB SA4 - 8KB SA3 - 8KB SA3 - 8KB SA3 - 8KB SA3 - 8KB SA2 - 8KB SA2 - 8KB SA2 - 8KB SA2 - 8KB SA1 - 8KB SA1 - 8KB SA1 - 8KB SA1 - 8KB SAS - 512B* SAS - 512B* SAS - 512B* SAS - 512B* Reserved Reserved Reserved Reserved Bank B of Flash A Bank A of Flash A *: Physical address area of SAS-512B is from DF:0000H to DF:01FFH. Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B. Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH. SAS can not be used for E2PROM emulation. Document Number: 002-04719 Rev.*A Page 20 of 69 MB96630 Series 10. Serial Programming Communication Interface USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode) MB96630 Pin Number USART Number 5 6 Normal Function SIN0 USART0 SOT0 7 SCK0 37 SIN2 38 USART2 SOT2 39 SCK2 68 SIN4 69 USART4 70 Document Number: 002-04719 Rev.*A SOT4 SCK4 Page 21 of 69 MB96630 Series 11. Interrupt Vector Table Vector number Offset in vector table Index in ICR to program Cleared by DMA Vector name Description 0 3FCH CALLV0 No - CALLV instruction 1 3F8H CALLV1 No - CALLV instruction 2 3F4H CALLV2 No - CALLV instruction 3 3F0H CALLV3 No - CALLV instruction 4 3ECH CALLV4 No - CALLV instruction 5 3E8H CALLV5 No - CALLV instruction 6 3E4H CALLV6 No - CALLV instruction 7 3E0H CALLV7 No - CALLV instruction 8 3DCH RESET No - Reset vector 9 3D8H INT9 No - INT9 instruction 10 3D4H EXCEPTION No - Undefined instruction execution 11 3D0H NMI No - Non-Maskable Interrupt 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Clock Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH LVDI No 16 Low Voltage Detector 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H EXTINT1 Yes 18 External Interrupt 1 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H EXTINT5 Yes 22 External Interrupt 5 23 3A0H EXTINT6 Yes 23 External Interrupt 6 24 39CH EXTINT7 Yes 24 External Interrupt 7 25 398H EXTINT8 Yes 25 External Interrupt 8 26 394H EXTINT9 Yes 26 External Interrupt 9 27 390H EXTINT10 Yes 27 External Interrupt 10 28 38CH EXTINT11 Yes 28 External Interrupt 11 29 388H EXTINT12 Yes 29 External Interrupt 12 30 384H EXTINT13 Yes 30 External Interrupt 13 31 380H - - 31 Reserved 32 37CH EXTINT15 Yes 32 External Interrupt 15 33 378H CAN0 No 33 CAN Controller 0 34 374H - - 34 Reserved 35 370H - - 35 Reserved 36 36CH - - 36 Reserved 37 368H - - 37 Reserved 38 364H PPG0 Yes 38 Programmable Pulse Generator 0 39 360H PPG1 Yes 39 Programmable Pulse Generator 1 Document Number: 002-04719 Rev.*A Page 22 of 69 MB96630 Series 40 35CH PPG2 Yes Index in ICR to program 40 41 358H PPG3 Yes 41 Programmable Pulse Generator 3 42 354H PPG4 Yes 42 Programmable Pulse Generator 4 43 350H - - 43 Reserved 44 34CH PPG6 Yes 44 Programmable Pulse Generator 6 45 348H PPG7 Yes 45 Programmable Pulse Generator 7 46 344H PPG8 Yes 46 Programmable Pulse Generator 8 47 340H PPG9 Yes 47 Programmable Pulse Generator 9 48 33CH PPG10 Yes 48 Programmable Pulse Generator 10 49 338H PPG11 Yes 49 Programmable Pulse Generator 11 50 334H PPG12 Yes 50 Programmable Pulse Generator 12 51 330H PPG13 Yes 51 Programmable Pulse Generator 13 52 32CH PPG14 Yes 52 Programmable Pulse Generator 14 53 328H PPG15 Yes 53 Programmable Pulse Generator 15 54 324H - - 54 Reserved 55 320H - - 55 Reserved 56 31CH - - 56 Reserved 57 318H - - 57 Reserved 58 314H RLT0 Yes 58 Reload Timer 0 59 310H RLT1 Yes 59 Reload Timer 1 60 30CH - - 60 Reserved 61 308H - - 61 Reserved 62 304H - - 62 Reserved 63 300H - - 63 Reserved 64 2FCH RLT6 Yes 64 Reload Timer 6 65 2F8H ICU0 Yes 65 Input Capture Unit 0 66 2F4H ICU1 Yes 66 Input Capture Unit 1 67 2F0H - - 67 Reserved 68 2ECH - - 68 Reserved 69 2E8H ICU4 Yes 69 Input Capture Unit 4 70 2E4H ICU5 Yes 70 Input Capture Unit 5 71 2E0H ICU6 Yes 71 Input Capture Unit 6 72 2DCH ICU7 Yes 72 Input Capture Unit 7 73 2D8H - - 73 Reserved 74 2D4H ICU9 Yes 74 Input Capture Unit 9 75 2D0H - - 75 Reserved 76 2CCH - - 76 Reserved 77 2C8H OCU0 Yes 77 Output Compare Unit 0 78 2C4H OCU1 Yes 78 Output Compare Unit 1 79 2C0H OCU2 Yes 79 Output Compare Unit 2 80 2BCH OCU3 Yes 80 Output Compare Unit 3 81 2B8H OCU4 Yes 81 Output Compare Unit 4 Vector number Offset in vector table Cleared by DMA Vector name Document Number: 002-04719 Rev.*A Description Programmable Pulse Generator 2 Page 23 of 69 MB96630 Series 82 2B4H - - Index in ICR to program 82 83 2B0H OCU6 Yes 83 Output Compare Unit 6 84 2ACH OCU7 Yes 84 Output Compare Unit 7 85 2A8H - - 85 Reserved 86 2A4H - - 86 Reserved 87 2A0H - - 87 Reserved 88 29CH - - 88 Reserved 89 298H FRT0 Yes 89 Free-Running Timer 0 90 294H FRT1 Yes 90 Free-Running Timer 1 91 290H FRT2 Yes 91 Free-Running Timer 2 92 28CH - - 92 Reserved 93 288H RTC0 No 93 Real Time Clock 94 284H CAL0 No 94 Clock Calibration Unit 95 280H - - 95 Reserved 96 27CH IIC0 Yes 96 I2C interface 0 97 278H IIC1 Yes 97 I2C interface 1 98 274H ADC0 Yes 98 A/D Converter 0 99 270H - - 99 Reserved 100 26CH - - 100 Reserved 101 268H LINR0 Yes 101 LIN USART 0 RX 102 264H LINT0 Yes 102 LIN USART 0 TX 103 260H - - 103 Reserved 104 25CH - - 104 Reserved 105 258H LINR2 Yes 105 LIN USART 2 RX 106 254H LINT2 Yes 106 LIN USART 2 TX 107 250H - - 107 Reserved 108 24CH - - 108 Reserved 109 248H LINR4 Yes 109 LIN USART 4 RX 110 244H LINT4 Yes 110 LIN USART 4 TX 111 240H LINR5 Yes 111 LIN USART 5 RX 112 23CH LINT5 Yes 112 LIN USART 5 TX 113 238H - - 113 Reserved 114 234H - - 114 Reserved 115 230H LINR7 Yes 115 LIN USART 7 RX 116 22CH LINT7 Yes 116 LIN USART 7 TX 117 228H - - 117 Reserved 118 224H - - 118 Reserved 119 220H - - 119 Reserved 120 21CH - - 120 Reserved 121 218H - - 121 Reserved 122 214H - - 122 Reserved 123 210H - - 123 Reserved Vector number Offset in vector table Cleared by DMA Vector name Document Number: 002-04719 Rev.*A Description Reserved Page 24 of 69 MB96630 Series 124 20CH - - Index in ICR to program 124 125 208H - - 125 Reserved 126 204H - - 126 Reserved 127 200H - - 127 Reserved 128 1FCH - - 128 Reserved 129 1F8H - - 129 Reserved 130 1F4H - - 130 Reserved 131 1F0H - - 131 Reserved 132 1ECH - - 132 Reserved 133 1E8H FLASHA Yes 133 Flash memory A interrupt 134 1E4H - - 134 Reserved 135 1E0H - - 135 Reserved 136 1DCH - - 136 Reserved 137 1D8H QPRC0 Yes 137 Quadrature Position/Revolution counter 0 138 1D4H QPRC1 Yes 138 Quadrature Position/Revolution counter 1 139 1D0H ADCRC0 No 139 A/D Converter 0 - Range Comparator 140 1CCH - - 140 Reserved 141 1C8H - - 141 Reserved 142 1C4H - - 142 Reserved 143 1C0H - - 143 Reserved Vector number Offset in vector table Cleared by DMA Vector name Document Number: 002-04719 Rev.*A Description Reserved Page 25 of 69 MB96630 Series 12. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 12.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence.  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-04719 Rev.*A Page 26 of 69 MB96630 Series  Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 12.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions.  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-04719 Rev.*A Page 27 of 69 MB96630 Series  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 12.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04719 Rev.*A Page 28 of 69 MB96630 Series 13. Handling Devices Special care is required for the following when handling the device: • • • • • • • • • • • • Latch-up prevention Unused pins handling External clock usage Notes on PLL clock mode operation Power supply pins (Vcc/Vss) Crystal oscillator and ceramic resonator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on Power-on Stabilization of power supply voltage Serial communication Mode Pin (MD) 13.1 Latch-up prevention CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between Vcc pins and Vss pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 13.2 Unused pins handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which should be more than 2k. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. Document Number: 002-04719 Rev.*A Page 29 of 69 MB96630 Series 13.3 External clock usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 13.3.1 Single phase external clock for Main oscillator When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open. And supply 1.8V power to the external clock. X0 X1 13.3.2 Single phase external clock for Sub oscillator When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO. 13.3.3 Opposite phase external clock When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V. X0 X1 13.4 Notes on PLL clock mode operation If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 13.5 Power supply pins (Vcc/Vss) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance. The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs. Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F between Vcc and Vss pins as close as possible to Vcc and Vss pins. Document Number: 002-04719 Rev.*A Page 30 of 69 MB96630 Series 13.6 Crystal oscillator and ceramic resonator circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 13.7 Turn on sequence of power supply to A/D converter and analog inputs It is required to turn the A/D converter power supply (AVCC, AVRH) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, AVRH must not exceed AVCC . Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 13.8 Pin handling when not using the A/D converter If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC = VCC , AVSS = AVRH = VSS. 13.9 Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50s from 0.2V to 2.7V. 13.10 Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation safety range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50Hz to 60Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for power supply switching. 13.11 Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. 13.12 Mode Pin (MD) Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a low-impedance connection. Document Number: 002-04719 Rev.*A Page 31 of 69 MB96630 Series 14. Electrical Characteristics 14.1 Absolute Maximum Ratings VCC - Rating Min Max VSS - 0.3 VSS + 6.0 AVCC - VSS - 0.3 VSS + 6.0 V AVRH - VSS - 0.3 VSS + 6.0 V VI VO - VSS - 0.3 VSS - 0.3 VSS + 6.0 VSS + 6.0 V V Maximum Clamp Current ICLAMP - -4.0 +4.0 mA Total Maximum Clamp Current Σ|ICLAMP| - - 21 mA IOL - - 15 mA IOLAV - - 4 mA ΣIOL - - 52 mA ΣIOLAV - - 26 mA IOH - - -15 mA IOHAV - - -4 mA ΣIOH - - -52 mA ΣIOHAV - - -26 Parameter Power supply voltage* Analog power supply voltage*1 Analog reference voltage*1 Input voltage*1 Output voltage*1 "L" level maximum output current "L" level average output current "L" level maximum overall output current "L" level average overall output current "H" level maximum output current "H" level average output current "H" level maximum overall output current "H" level average overall output current Power consumption*5 Operating ambient temperature Storage temperature Symbol 1 PD Condition TA= +125°C - Unit V Remarks VCC = AVCC*2 AVCC ≥ AVRH, AVRH ≥ AVSS VI ≤ VCC + 0.3V*3 VO ≤ VCC + 0.3V*3 Applicable to general purpose I/O pins *4 Applicable to general purpose I/O pins *4 mA *6 396 TA - -40 +125 TSTG - -55 +150 *7 mW °C °C *1 : This parameter is based on VSS = AVSS = 0V. *2 : AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3 : VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/Output voltages of standard ports depend on VCC. *4 : Applicable to all general purpose I/O pins (Pnn_m). • • • • Use within recommended operating conditions. Use at DC voltage (current). The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset. Document Number: 002-04719 Rev.*A Page 32 of 69 MB96630 Series • The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current (4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6.0V. • Sample recommended circuits: Protective diode VCC Limiting resistance P-ch +B input (0V to 16V) N-ch R *5 : The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = Σ (VOL  IOL + VOH  IOH) (I/O load power dissipation, sum is performed on all I/O ports) PINT = VCC  (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming. IA is the analog current consumption into AVCC. *6 : Worst case value for a package mounted on single layer PCB at specified TA without air flow. *7 : Write/erase to a large sector in flash memory is warranted with TA ≤ + 105°C. WARNING Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04719 Rev.*A Page 33 of 69 MB96630 Series 14.2 Recommended Operating Conditions (VSS = AVSS = 0V) Parameter Symbol Power supply voltage VCC, AVCC Smoothing capacitor at C pin CS Min 2.7 2.0 0.5 Value Typ Unit - Max 5.5 5.5 V V 1.0 to 3.9 4.7 F Remarks Maintains RAM data in stop mode 1.0F (Allowance within ± 50%) 3.9µF (Allowance within ± 20%) Please use the ceramic capacitor or the capacitor of the frequency response of this level. The smoothing capacitor at VCC must use the one of a capacity value that is larger than CS. WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04719 Rev.*A Page 34 of 69 MB96630 Series 14.3 DC Characteristics 14.3.1 Current Rating (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Pin name Conditions mA TA = +25°C - - 37 mA TA = +105°C - - 38.5 mA TA = +125°C Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz - 3.5 - mA TA = +25°C Flash 0 wait - - 8 mA TA = +105°C (CLKPLL, CLKSC and CLKRC stopped) - - 9.5 mA TA = +125°C - 1.8 - mA TA = +25°C Flash 0 wait - - 6 mA TA = +105°C (CLKMC, CLKPLL and CLKSC stopped) - - 7.5 mA TA = +125°C RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz - 0.16 - mA TA = +25°C Flash 0 wait - - 3.5 mA TA = +105°C (CLKMC, CLKPLL and CLKSC stopped) - - 5 mA TA = +125°C Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz - 0.1 - mA TA = +25°C Flash 0 wait - - 3.3 mA TA = +105°C (CLKMC, CLKPLL and CLKRC stopped) - - 4.8 mA TA = +125°C RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz ICCRCH Vcc ICCRCL ICCSUB Document Number: 002-04719 Rev.*A Remarks - (CLKRC and CLKSC stopped) Power supply current in Run modes*1 Unit 27 Flash 0 wait ICCMAIN Max - PLL Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32MHz ICCPLL Value Typ Min Page 35 of 69 MB96630 Series Parameter Symbol Pin name ICCSMAIN ICCSRCH ICCSRCL ICCSSUB Document Number: 002-04719 Rev.*A Vcc Value Typ Min Max Unit Remarks - 8.5 - mA TA = +25°C - - 14 mA TA = +105°C - - 15.5 mA TA = +125°C Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) - 1 - mA TA = +25°C - - 4.5 mA TA = +105°C - - 6 mA TA = +125°C RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped) - 0.6 - mA TA = +25°C - - 3.8 mA TA = +105°C - - 5.3 mA TA = +125°C - 0.07 - mA TA = +25°C - - 2.8 mA TA = +105°C - - 4.3 mA TA = +125°C - 0.04 - mA TA = +25°C - - 2.5 mA TA = +105°C - - 4 mA TA = +125°C PLL Sleep mode with CLKS1/2 = CLKP1/2 = 32MHz (CLKRC and CLKSC stopped) ICCSPLL Power supply current in Sleep modes*1 Conditions RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 100kHz (CLKMC, CLKPLL and CLKSC stopped) Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz, (CLKMC, CLKPLL and CLKRC stopped) Page 36 of 69 MB96630 Series Parameter Symbol Pin name PLL Timer mode with CLKPLL = 32MHz (CLKRC and CLKSC stopped) ICCTPLL Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) ICCTMAIN Power supply current in Timer modes*2 ICCTRCH Conditions Vcc ICCTRCL ICCTSUB Document Number: 002-04719 Rev.*A RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped) RC Timer mode with CLKRC = 100kHz (CLKPLL, CLKMC and CLKSC stopped) Sub Timer mode with CLKSC = 32kHz (CLKMC, CLKPLL and CLKRC stopped) Value Typ Min Max Unit Remarks - 1800 2250 A TA = +25°C - - 3220 A TA = +105°C - - 4205 A TA = +125°C - 285 330 A TA = +25°C - - 1195 A TA = +105°C - - 2165 A TA = +125°C - 160 215 A TA = +25°C - - 1095 A TA = +105°C - - 2075 A TA = +125°C - 35 75 A TA = +25°C - - 905 A TA = +105°C - - 1880 A TA = +125°C - 25 65 A TA = +25°C - - 885 A TA = +105°C - - 1850 A TA = +125°C Page 37 of 69 MB96630 Series Parameter Power supply current in Stop mode*3 Flash Power Down current Symbol Pin name ICCH Conditions - ICCFLASHPD - Value Typ Min Max Unit Remarks - 20 60 A TA = +25°C - - 880 A TA =+105°C - - 1845 A TA =+125°C - 36 70 A - 5 - A TA = +25°C - - 12.5 A TA =+125°C - 12.5 - mA TA = +25°C - - 20 mA TA =+125°C Vcc Power supply current for active Low Voltage detector*4 ICCLVD Flash Write/ Erase current*5 ICCFLASH Low voltage detector enabled - *1 : The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Current for "On Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write / Erase current. *2 : The power supply current in Timer mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not included. *3 : The power supply current in Stop mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. *4 : When low voltage detector is enabled, ICCLVD must be added to Power supply current. *5 : When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current. Document Number: 002-04719 Rev.*A Page 38 of 69 MB96630 Series 14.3.2 Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol VIH "H" level input voltage "L" level input voltage Pin name Port inputs Pnn_m External clock in "Fast Clock Input mode" External clock in "Oscillation mode" VIHX0S X0 VIHX0AS X0A VIHR RSTX - VIHM MD - VIHD DEBUG I/F - VIL Port inputs Pnn_m External clock in "Fast Clock Input mode" External clock in "Oscillation mode" VILX0S X0 VILX0AS X0A VILR RSTX - VILM MD - VILD DEBUG I/F - VOH4 4mA type VOH3 3mA type VOL4 4mA type VOL3 3mA type VOLD DEBUG I/F "H" level output voltage "L" level output voltage Conditions Document Number: 002-04719 Rev.*A 4.5V ≤ VCC ≤ 5.5V IOH = -4mA 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOH = -3mA 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOL = +4mA 2.7V ≤ VCC < 4.5V IOL = +1.7mA 2.7V ≤ VCC < 5.5V IOL = +3mA VCC = 2.7V IOL = +25mA Min VCC  0.7 VCC  0.8 VD  0.8 VCC  0.8 VCC  0.8 VCC - 0.3 2.0 VSS - 0.3 VSS - 0.3 VSS VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Value Typ - Max VCC + 0.3 VCC + 0.3 VD VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC  0.3 VCC  0.5 VD  0.2 VCC  0.2 VCC  0.2 VSS + 0.3 Unit Remarks V CMOS Hysteresis input V AUTOMOTIVE Hysteresis input V VD=1.8V±0.15V V V CMOS Hysteresis input V CMOS Hysteresis input V TTL Input V CMOS Hysteresis input V AUTOMOTIVE Hysteresis input V VD=1.8V±0.15V V V CMOS Hysteresis input V CMOS Hysteresis input TTL Input - 0.8 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V - - 0.4 V - - 0.4 V 0 - 0.25 V Page 39 of 69 MB96630 Series Parameter Symbol Pin name Conditions Min Value Typ Max Unit Input leak current IIL Pnn_m VSS < VI < VCC AVSS < VI < AVCC, AVRH -1 - +1 A Pull-up resistance value RPU Pnn_m VCC = 5.0V ±10% 25 50 100 k CIN Other than C, Vcc, Vss, AVcc, AVss, AVRH - - 5 15 pF Input capacitance Document Number: 002-04719 Rev.*A Remarks Page 40 of 69 MB96630 Series 14.4 AC Characteristics 14.4.1 Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Input frequency Symbol fC fFCI Pin name X0, X1 Value Typ Min Unit Max 4 - 8 MHz - - 8 MHz 4 - 8 MHz - - 8 MHz 4 - 8 MHz X0 Input clock cycle tCYLH - 125 - - ns Input clock pulse width PWH, PWL - 55 - - ns Document Number: 002-04719 Rev.*A Remarks When using a crystal oscillator, PLL off When using an opposite phase external clock, PLL off When using a crystal oscillator or opposite phase external clock, PLL on When using a single phase external clock in “Fast Clock Input mode”, PLL off When using a single phase external clock in “Fast Clock Input mode”, PLL on Page 41 of 69 MB96630 Series 14.4.2 Sub Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Pin name Symbol fCL Value Conditions Min Typ Max Unit - - 32.768 - kHz - - - 100 kHz X0A - - - 50 kHz X0A, X1A Input clock cycle tCYLL - - 10 - - s Input clock pulse width - - PWH/tCYLL, PWL/tCYLL 30 - 70 % Document Number: 002-04719 Rev.*A Remarks When using an oscillation circuit When using an opposite phase external clock When using a single phase external clock Page 42 of 69 MB96630 Series 14.4.3 Built-in RC Oscillation Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Clock frequency RC clock stabilization time 14.4.4 Value Symbol Min Typ Unit Max 50 100 200 kHz 1 2 4 MHz 80 160 320 s 64 128 256 s Remarks When using slow frequency of RC oscillator When using fast frequency of RC oscillator When using slow frequency of RC oscillator (16 RC clock cycles) When using fast frequency of RC oscillator (256 RC clock cycles) fRC tRCSTAB Internal Clock Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Value Symbol Min Max Unit Internal System clock frequency (CLKS1 and CLKS2) fCLKS1, fCLKS2 - 54 MHz Internal CPU clock frequency (CLKB), Internal peripheral clock frequency (CLKP1) fCLKB, fCLKP1 - 32 MHz Internal peripheral clock frequency (CLKP2) fCLKP2 - 32 MHz Document Number: 002-04719 Rev.*A Page 43 of 69 MB96630 Series 14.4.5 Operating Conditions of PLL (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Value Min Typ Unit Max Remarks PLL oscillation stabilization wait time tLOCK 1 - 4 ms PLL input clock frequency fPLLI 4 - 8 MHz PLL oscillation clock frequency fCLKVCO 56 - 108 MHz Permitted VCO output frequency of PLL (CLKVCO) PLL phase jitter tPSKEW -5 - +5 ns For CLKMC (PLL input clock) ≥ 4MHz 14.4.6 For CLKMC = 4MHz Reset Input (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Reset input time tRSTL Value Pin name Min 10 - s 1 - s RSTX Rejection of reset input time Unit Max tRSTL RSTX 0.2VCC Document Number: 002-04719 Rev.*A 0.2VCC Page 44 of 69 MB96630 Series 14.4.7 Power-on Reset Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Power on rise time Power off time Symbol tR tOFF Document Number: 002-04719 Rev.*A Pin name Vcc Vcc Value Min 0.05 1 Typ - Unit Max 30 - ms ms Page 45 of 69 MB96630 Series 14.4.8 USART Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C, CL=50pF) Symbo l Parameter Serial clock cycle time Pin name tSCYC SCKn SCK   SOT delay time tSLOVI SCKn, SOTn SOT  SCK  delay time tOVSHI SCKn, SOTn SIN  SCK  setup time tIVSHI SCK   SIN hold time tSHIXI Serial clock "L" pulse width tSLSH SCKn Serial clock "H" pulse width tSHSL SCKn SCK   SOT delay time tSLOVE SCKn, SOTn SIN  SCK  setup time tIVSHE SCK   SIN hold time tSHIXE SCK fall time SCK rise time tF tR Conditions Internal shift clock mode SCKn, SINn SCKn, SINn SCKn, SINn SCKn, SINn SCKn SCKn 4.5V  VCC 5.5V Min Max 4tCLKP1 - - 20 + 20 NtCLKP1 – 20* - tCLKP1 + 45 - 0 - tCLKP1 + 10 tCLKP1 + 10 External shift clock mode Unit ns 1 - 30 + 30 ns - ns - ns - ns - ns - ns 2tCLKP1 + 55 ns - ns - ns 20 20 ns ns NtCL - - 2tCLKP1 + 45 tCLKP1/2 + 10 - tCLKP1 + 10 - 2.7V  VCC  4.5V Min Max 4tCLKP - 20 20 KP1 – 30* tCLKP1 + 55 0 tCLKP1 + 10 tCLKP1 + 10 tCLKP1/ 2 + 10 tCLKP1 + 10 - Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “MB96600 series HARDWARE MANUAL”. • tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns • These characteristics only guarantee the same relocate port number. For example, the combination of SCKn and SOTn_R is not guaranteed. *: Parameter N depends on tSCYC and can be calculated as follows: • If tSCYC = 2  k  tCLKP1, then N = k, where k is an integer > 2 • If tSCYC = (2  k + 1)  tCLKP1, then N = k + 1, where k is an integer > 1 Examples: tSCYC N 4  tCLKP1 2 5  tCLKP1, 6  tCLKP1 3 7  tCLKP1, 8  tCLKP1 4 … … Document Number: 002-04719 Rev.*A Page 46 of 69 MB96630 Series tSCYC VOH SCK VOL VOL tOVSHI tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Internal shift clock mode SCK tSHSL tSLSH VIH VIH VIL tF SOT VIL VIH tR tSLOVE VOH VOL SIN tIVSHE VIH VIL tSHIXE VIH VIL External shift clock mode Document Number: 002-04719 Rev.*A Page 47 of 69 MB96630 Series 14.4.9 External Input Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input pulse width Symbol tINH, tINL Value Pin name Min Max Unit Remarks Pnn_m General Purpose I/O ADTG A/D Converter trigger input TINn TTGn FRCKn, FRCKn_R INn, INn_R 2tCLKP1 +200 (tCLKP1= 1/fCLKP1)* AINn, BINn, ZINn INTn, INTn_R NMI - 200 - ns ns Reload Timer PPG trigger input Free-Running Timer input clock Input Capture Quadrature Position/Revolution Counter External Interrupt Non-Maskable Interrupt *: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode. tINH External input timing VIH tINL VIH VIL Document Number: 002-04719 Rev.*A VIL Page 48 of 69 MB96630 Series 14.4.10 I2C Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter fSCL Typical mode Min Max 0 100 High-speed mode*4 Min Max 0 400 kHz tHDSTA 4.0 - 0.6 - s tLOW tHIGH 4.7 4.0 - 1.3 0.6 - s s 4.7 - 0.6 - s 0 3.45*2 0 0.9*3 s tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - s tBUS 4.7 - 1.3 - s 0 (1-1.5) tCLKP1*5 0 (1-1.5) tCLKP1*5 ns Symbol SCL clock frequency (Repeated) START condition hold time SDA   SCL  SCL clock "L" width SCL clock "H" width (Repeated) START condition setup time SCL   SDA  Data hold time SCL   SDA   Data setup time SDA    SCL  STOP condition setup time SCL   SDA  Bus free time between "STOP condition" and "START condition" Pulse width of spikes which will be suppressed by input noise filter Conditions tSUSTA CL = 50pF, R = (Vp/IOL)*1 tHDDAT tSP - *1 : R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2 : The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal. *3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250ns". *4 : For use at over 100kHz, set the peripheral clock1 (CLKP1) to at least 6MHz. *5 : tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time. Unit SDA tSUDAT tSUSTA tBUS tLOW SCL tHDSTA Document Number: 002-04719 Rev.*A tHDDAT tHIGH tHDSTA tSP tSUSTO Page 49 of 69 MB96630 Series 14.5 A/D Converter 14.5.1 Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Value Typ Symbol Pin name Resolution - - - - 10 bit Total error - - - 3.0 - + 3.0 LSB Nonlinearity error - - - 2.5 - + 2.5 LSB - - - 1.9 - + 1.9 LSB VOT ANn Typ - 20 Typ + 20 mV VFST ANn Typ - 20 Typ + 20 mV Compare time* - - Sampling time* - - 5.0 8.0 3.1 s s s s mA Differential Nonlinearity error Zero transition voltage Full scale transition voltage IA Power supply current Reference power supply current (between AVRH and AVSS ) Analog input capacity IAH AVCC IR Min Max Unit 1.0 2.2 0.5 1.2 - AVSS +0.5LSB AVRH - 1.5LSB 2.0 - - 3.3 A - 520 810 A A/D Converter active - - 1.0 A A/D Converter not operated AVRH IRH Remarks 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V A/D Converter active A/D Converter not operated CVIN ANn - - 15.9 pF Analog impedance RVIN ANn - - 2050 3600   4.5V ≤ AVCC ≤ 5.5V 2.7V ≤ AVCC < 4.5V Analog port input current (during conversion) IAIN ANn - 0.3 - + 0.3 A AVSS VAIN  AVCC, AVRH Analog input voltage VAIN ANn AVSS - AVRH V - AVRH AVCC - 0.1 - AVCC V - ANn - - 4.0 LSB Reference voltage range Variation between channels *: Time for each channel. Document Number: 002-04719 Rev.*A Page 50 of 69 MB96630 Series 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time (Tsamp) depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVCC voltage level. The following replacement model can be used for the calculation: MCU Rext Analog input RVIN Source Comparator Cext CVIN Sampling switch (During sampling:ON) Rext: External driving impedance Cext: Capacitance of PCB at A/D converter input CVIN: Analog input capacity (I/O, analog switch and ADC are contained) RVIN: Analog input impedance (I/O, analog switch and ADC are contained) The following approximation formula for the replacement model above can be used: Tsamp = 7.62  (Rext  Cext + (Rext + RVIN)  CVIN) • Do not select a sampling time below the absolute minimum permitted value. (0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V) • If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin. • A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor. • The accuracy gets worse as |AVRH - AVSS| becomes smaller. Document Number: 002-04719 Rev.*A Page 51 of 69 MB96630 Series 14.5.3 Definition of A/D Converter Terms • Resolution • Nonlinearity error transition point • • • • : Analog variation that is recognized by an A/D converter. : Deviation of the actual conversion characteristics from a straight line that connects the zero (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→ 0b1111111111). Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the output code by 1LSB. Total error : Difference between the actual value and the theoretical value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Zero transition voltage : Input voltage which results in the minimum conversion value. Full scale transition voltage: Input voltage which results in the maximum conversion value. Nonlinearity error of digital output N = VNT - {1LSB  (N - 1) + VOT} 1LSB Differential nonlinearity error of digital output N = 1LSB = N VOT VFST VNT : : : : V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VOT 1022 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0x3FE to 0x3FF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-04719 Rev.*A Page 52 of 69 MB96630 Series 1LSB (Ideal value) = Total error of digital output N = AVRH - AVSS 1024 [V] VNT - {1LSB  (N - 1) + 0.5LSB} 1LSB N : A/D converter digital output value. VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN. VOT (Ideal value) = AVSS + 0.5LSB[V] VFST (Ideal value) = AVRH - 1.5LSB[V] Document Number: 002-04719 Rev.*A Page 53 of 69 MB96630 Series 14.6 Low Voltage Detection Function Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Conditions Value Typ 2.90 3.00 3.20 3.50 3.70 4.00 4.20 Max 3.10 3.21 3.42 3.74 3.95 4.27 4.49 V V V V V V V Unit Detected voltage*1 VDL0 VDL1 VDL2 VDL3 VDL4 VDL5 VDL6 CILCR:LVL = 0000B CILCR:LVL = 0001B CILCR:LVL = 0010B CILCR:LVL = 0011B CILCR:LVL = 0100B CILCR:LVL = 0111B CILCR:LVL = 1001B Min 2.70 2.79 2.98 3.26 3.45 3.73 3.91 Power supply voltage change rate*2 dV/dt - - 0.004 - + 0.004 V/s Hysteresis width VHYS CILCR:LVHYS=0 - - 50 mV CILCR:LVHYS=1 80 100 120 mV Stabilization time TLVDSTAB - - - 75 s Detection delay time td - - - 30 s *1 : If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a possibility that the low voltage detection will occur or stop after the power supply voltage passes the detection range. *2 : In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation of the power supply voltage within the limits of the change ration of power supply voltage. Document Number: 002-04719 Rev.*A Page 54 of 69 MB96630 Series Voltage Vcc dV Detected Voltage dt VDLX max VDLX min Time RCR:LVDE ···Low voltage detection function enable Document Number: 002-04719 Rev.*A Low voltage detection function disable Stabilization time TLVDSTAB Low voltage detection function enable··· Page 55 of 69 MB96630 Series 14.7 Flash Memory Write/Erase Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Sector erase time Word (16-bit) write time Conditions Min Value Typ Unit Max Large Sector TA ≤ + 105°C - 1.6 7.5 s Small Sector - - 0.4 2.1 s Security Sector - - 0.31 1.65 s Large Sector TA ≤ + 105°C - 25 400 s Small Sector - - 25 400 s TA ≤ + 105°C - 11.51 55.05 s Chip erase time Remarks Includes write time prior to internal erase. Not including system-level overhead time. Includes write time prior to internal erase. Note: While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system where the external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function. To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/s to +0.004V/s) after the external power falls below the detection voltage (VDLX)*1. Write/Erase cycles and data hold time Write/Erase cycles (cycle) 1,000 10,000 100,000 *1 Data hold time (year) 20 *2 10 *2 5 *2 : See "Low Voltage Detection Function Characteristics". *2 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85C). Document Number: 002-04719 Rev.*A Page 56 of 69 MB96630 Series 15. Example Characteristics This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.  MB96F637 Run Mode (VCC = 5.5V) 100.00 PLL clock (32MHz) 10.00 ICC [mA] Main osc. (4MHz) 1.00 RC clock (2MHz) RC clock (100kHz) 0.10 Sub osc. (32kHz) 0.01 -50 0 50 100 150 TA [ºC] Sleep Mode (VCC = 5.5V) 100.000 PLL clock (32MHz) ICC [mA] 10.000 Main osc. (4MHz) 1.000 RC clock (2MHz) 0.100 RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04719 Rev.*A Page 57 of 69 MB96630 Series  MB96F637 Timer Mode (VCC = 5.5V) 10.000 PLL clock (32MHz) ICC [mA] 1.000 Main osc. (4MHz) 0.100 RC clock (2MHz) RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Stop Mode (VCC = 5.5V) 1.000 ICC [mA] 0.100 0.010 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04719 Rev.*A Page 58 of 69 MB96630 Series  Used setting Selected Source Clock Mode Run mode Sleep mode PLL CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz Main osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz RC clock fast CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz RC clock slow CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz Sub osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKMC = 4MHz, CLKPLL = 32MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 4MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 2MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 100kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode CLKMC = 32 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode (All clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode PLL Main osc. RC clock fast RC clock slow Sub osc. Timer mode PLL Main osc. RC clock fast RC clock slow Sub osc. Stop mode Clock/Regulator and FLASH Settings stopped Document Number: 002-04719 Rev.*A Page 59 of 69 MB96630 Series 16. Ordering Information MCU with CAN controller Part number MB96F633RBPMC-GSE1 MB96F633RBPMC-GSE2 MB96F635RBPMC-GSE1 MB96F635RBPMC-GSE2 MB96F636RBPMC-GSE1 MB96F636RBPMC-GSE2 MB96F637RBPMC-GSE1 MB96F637RBPMC-GSE2 Flash memory Flash A (96.5KB) Package* 80-pin plastic LQFP (FPT-80P-M21) Flash A (160.5KB) 80-pin plastic LQFP (FPT-80P-M21) Flash A (288.5KB) 80-pin plastic LQFP (FPT-80P-M21) Flash A (416.5KB) 80-pin plastic LQFP (FPT-80P-M21) *: For details about package, see "Package Dimension". MCU without CAN controller Part number MB96F633ABPMC-GSE1 MB96F633ABPMC-GSE2 MB96F635ABPMC-GSE1 MB96F635ABPMC-GSE2 Flash memory Flash A (96.5KB) Package* 80-pin plastic LQFP (FPT-80P-M21) Flash A (160.5KB) 80-pin plastic LQFP (FPT-80P-M21) *: For details about package, see "Package Dimension". Document Number: 002-04719 Rev.*A Page 60 of 69 MB96630 Series 17. Package Dimension 80-pin plastic LQFP (FPT-80P-M21) 80-pin plastic LQFP (FPT-80P-M21) Lead pitch 0.50 mm Package width × package length 12 mm × 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.47 g Code (Reference) P-LFQFP80-12×12-0.50 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ * 12.00±0.10(.472±.004)SQ 60 0.145±0.055 (.006±.002) 41 61 40 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 0°~8° 80 21 "A" LEAD No. 1 20 0.50(.020) C 0.10±0.05 (.004±.002) (Stand off) 0.20±0.05 (.008±.002) 2006-2010 FUJITSU SEMICONDUCTOR LIMITED F80035S-c-2-4 Document Number: 002-04719 Rev.*A 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) M Dimensions in mm (inches). Note: The values in parentheses are reference values Page 61 of 69 MB96630 Series 18. Major Changes Spansion Publication Number: MB96F636-DS704-00012 Page Section Revision 1.0 Features 2 4 Product Lineup 5 Block Diagram 6 Pin Description 8 I/O Circuit Type 13 14 Memory Map 17 User Rom Memory Map For Flash Devices 19 Document Number: 002-04719 Rev.*A Change Results PRELIMINARY → Data sheet Changed the description of “System clock” Up to 16 MHz external clock for devices with fast clock input feature → Up to 8 MHz external clock for devices with fast clock input feature Changed the description of “External Interrupts” Interrupt mask and pending bit per channel → Interrupt mask bit per channel Changed the description of “Built-in On Chip Debugger” - Event sequencer: 2 levels → - Event sequencer: 2 levels + reset Added the Product Changed the Remark of RLT RLT 0/1/6 Only RLT6 can be used as PPG clock source → RLT 0/1/6 Deleted the block of RLT6 from PPG block Changed the RLT block 2ch → 0/1/6 3ch Changed the Description of PPGn_B Programmable Pulse Generator n output (8bit) → Programmable Pulse Generator n output (16bit/8bit) Changed the figure of type B Changed the Remarks of type B (CMOS hysteresis input with input shutdown function, IOL = 4mA, IOH = -4mA, Programmable pull-up resister) → (CMOS level output (IOL = 4mA, IOH = -4mA), Automotive input with input shutdown function and programmable pull-up resistor) Changed the figure of type G Changed the START addresses of Boot-ROM 0F:E000H → 0F:C000H Changed the annotation Others (from DF:0200H to DF:1FFFH) are all mirror area of SAS-512B. → Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B. Page 62 of 69 MB96630 Series Page Section Interrupt Vector Table 21 22 25 to 28 Handling Precautions Handling Devices Change Results Changed the Description of CALLV0 to CALLV7 Reserved → CALLV instruction Changed the Description of RESET Reserved → Reset vector Changed the Description of INT9 Reserved → INT9 instruction Changed the Description of EXCEPTION Reserved → Undefined instruction execution Changed the Vector name of Vector number 64 PPGRLT → RLT6 Changed the Description of Vector number 64 Reload Timer 6 can be used as PPG clock source → Reload Timer 6 Added a section Added the description to “3. External clock usage” (3) Opposite phase external clock Changed the description in “7. Turn on sequence of power supply to A/D converter and analog inputs” 30 31 Electrical Characteristics 1. Absolute Maximum Ratings 33 1. Absolute Maximum Ratings 33 2. Recommended Operating Conditions 35 Document Number: 002-04719 Rev.*A In this case, the voltage must not exceed AVRH or AVCC → In this case, AVRH must not exceed AVCC. Input voltage for ports shared with analog input ports also must not exceed AVCC Added the description “12. Mode Pin (MD)” Changed the annotation *4 Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). → Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset. Added the annotation *4 The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current (4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6.0V. Added the Value and Remarks to “Power supply voltage” Min: 2.0V Typ: Max: 5.5V Remarks: Maintains RAM data in stop mode Changed the Value of “Smoothing capacitor at C pin” Typ: 1.0F → 1.0F to 3.9F Max: 1.5F → 4.7F Changed the Remarks of “Smoothing capacitor at C pin” Deleted “(Target value)” Added “3.9F (Allowance within ± 20%)” Page 63 of 69 MB96630 Series Page Section 3. DC Characteristics (1) Current Rating 36 37 38 Document Number: 002-04719 Rev.*A Change Results Deleted “(Target value)” from Remarks Added the Symbol to “Power supply current in Run modes” ICCRCH, ICCRCL Changed the Conditions of ICCPLL, ICCMAIN, ICCSUB in “Power supply current in Run modes” “Flash 0 wait” is added Changed the Value of “Power supply current in Run modes” ICCPLL Max: 37.5mA → 37mA (TA = +105°C) Max: 39mA → 38.5mA (TA = +125°C) ICCMAIN Max: 9mA → 8mA (TA = +105°C) Max: 10.5mA → 9.5mA (TA = +125°C) ICCSUB Max: 6mA → 3.3mA (TA = +105°C) Max: 7.5mA → 4.8mA (TA = +125°C) Added the Symbol to “Power supply current in Sleep modes” ICCSRCH, ICCSRCL Changed the Conditions of ICCSMAIN in “Power supply current in Sleep modes” “SMCR:LPMSS=0” is added Changed the Value of “Power supply current in Sleep modes” ICCSPLL Typ: 10mA → 8.5mA (TA = +25°C) Max : 15mA → 14mA (TA = +105°C) Max : 16.5mA → 15.5mA (TA = +125°C) ICCSMAIN Max: 7mA → 4.5m A (TA = +105°C) Max : 8.5mA → 6mA (TA = +125°C) ICCSSUB Typ: 0.08mA → 0.04m A (TA = +25°C) Max: 4mA → 2.5m A (TA = +105°C) Max : 5.5mA → 4mA (TA = +125°C) Added the Symbol to “Power supply current in Timer modes” ICCTPLL Changed the Conditions of ICCTMAIN, ICCTRCH in “Power supply current in Timer modes” “SMCR:LPMSS=0” is added Changed the Value of “Power supply current in Timer modes” ICCTMAIN Max: 355A → 330A (TA = +25°C) Max: 1300A → 1195A (TA = +105°C) Max: 2310A → 2165A (TA = +125°C) ICCTRCH Max: 245A → 215A (TA = +25°C) Max: 1215A → 1095A (TA = +105°C) Max: 2215A → 2075A (TA = +125°C) ICCTRCL Max: 105A → 75A (TA = +25°C) Max: 1010A → 905A (TA = +105°C) Max: 2015A → 1880A (TA = +125°C) ICCTSUB Max: 90A → 65A (TA = +25°C) Max: 985A → 885A (TA = +105°C) Max: 1990A → 1850A (TA = +125°C) Page 64 of 69 MB96630 Series Page Section 3. DC Characteristics (1) Current Rating 39 40 3. DC Characteristics (2) Pin Characteristics 41 4. AC Characteristics (1) Main Clock Input Characteristics 42 43 4. AC Characteristics (2) Sub Clock Input Characteristics Document Number: 002-04719 Rev.*A Change Results Changed the Value of “Power supply current in Stop modes” ICCH Max: 90A → 60A (TA = +25°C) Max: 985A → 880A (TA = +105°C) Max: 1985A → 1845A (TA = +125°C) Added the Symbol ICCFLASHPD Changed the Value and condition of “Power supply current for active Low Voltage detector” ICCLVD Typ: 5A, Max: 15A, Remarks: nothing → Typ: 5A, Max: -, Remarks: TA = +25°C Typ: -, Max: 12.5A, Remarks: TA = +125°C Changed the condition of “Flash Write/Erase current” ICCFLASH Typ: 12.5mA, Max: 20mA, Remarks: nothing → Typ: 12.5mA, Max: -, Remarks: TA = +25°C Typ: -, Max: 20mA, Remarks: TA = +125°C Changed the annotation *2 The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. → When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not included. Added the Symbol for DEBUG I/F pin VOLD Changed the Pin name of “Input capacitance” Other than Vcc, Vss, AVcc, AVss, AVRH → Other than C, Vcc, Vss, AVcc, AVss, AVRH Deleted the annotation “IOH and IOL are target value.” Changed MAX frequency for f FCI in all conditions 16→8 Changed MIN frequency for tCYLH 62.5→125 Changed MIN, MAX and Unit for PWH , PWL MIN: 30→55 MAX: 70→Unit: %→ns Added the figure (tCYLH) when using the external clock Added the figure (tCYLL) when using the crystal oscillator clock Page 65 of 69 MB96630 Series Page 44 Section 4. AC Characteristics (3) Built-In RC Oscillation Characteristics 4. AC Characteristics (5) Operating Conditions Of PLL 45 4. Ac Characteristics (6) Reset Input 4. Ac Characteristics (8) Usart Timing 47 48 50 4. AC Characteristics 2 (10) I C Timing 51 5. A/D Converter (1) Electrical Characteristics For The A/D Converter 52 5. A/D Converter (2) Accuracy And Setting Of The A/D Converter Sampling Time 5. A/D Converter (3) Definition Of A/D Converter Terms 53 6. Low Voltage Detection Function Characteristics 55 56 Document Number: 002-04719 Rev.*A Change Results Added “RC clock stabilization time” Changed the Value of “PLL input clock frequency” Max: 16MHz → 8MHz Changed the Symbol of “PLL oscillation clock frequency” fPLLO → fCLKVCO Added Remarks to “PLL oscillation clock frequency” Added “ PLL phase jitter” and the figure Added the figure for reset input time (tRSTL) Changed the condition (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C) → (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C, CL=50pF) Changed the HARDWARE MANUAL “MB96630 series HARDWARE MANUAL” → “MB96600 series HARDWARE MANUAL” Changed the figure for “Internal shift clock mode” Added parameter, “Noise filter” and an annotation *5 for it Added tSP to the figure Added “Analog impedance” Added “Variation between channels” Added the annotation Deleted the unit “[Min]” from approximation formula of Sampling time Changed the Description and the figure “Linearity” → “Nonlinearity” “Differential linearity error” → “Differential nonlinearity error” Changed the Description Linearity error: Deviation of the line between the zero-transition point (0b0000000000←→0b0000000001) and the full-scale transition point (0b1111111110←→0b1111111111) from the actual conversion characteristics. → Nonlinearity error: Deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→ 0b1111111111). Added the Description “Zero transition voltage” “Full scale transition voltage” Added the Value of “ Power supply voltage change rate” Max: +0.004 V/s Added “Hysteresis width” (VHYS) Added “Stabilization time” (TLVDSTAB) Added “Detection delay time” (td) Deleted the Remarks Added the annotation *1, *2 Added the figure for “Hysteresis width” Added the figure for “Stabilization time” Page 66 of 69 MB96630 Series Page Section 7. Flash Memory Write/Erase Characteristics 57 58 to 60 Example Characteristics Ordering Information 61 Ordering Information 61 Revision 1.1 - Change Results Changed the Value of “Sector erase time” Added “Security Sector” to “Sector erase time” Changed the Parameter “Half word (16 bit) write time” → “Word (16-bit) write time” Changed the Value of “Chip erase time” Changed the Remarks of “Sector erase time” Excludes write time prior to internal erase → Includes write time prior to internal erase Added the Note and annotation *1 Deleted “(targeted value)” from title “ Write/Erase cycles and data hold time” Added a section Changed part number MCU with CAN controller MB96F636RAPMC-GSE1* → MB96F636RBPMC-GSE1 MB96F636RAPMC-GSE2* → MB96F636RBPMC-GSE2 MB96F637RAPMC-GSE1* → MB96F637RBPMC-GSE1 MB96F637RAPMC-GSE2* → MB96F637RBPMC-GSE2 Added part number MCU with CAN controller MB96F633RBPMC-GSE1 MB96F633RBPMC-GSE2 MB96F635RBPMC-GSE1 MB96F635RBPMC-GSE2 MCU without CAN controller MB96F633ABPMC-GSE1 MB96F633ABPMC-GSE2 MB96F635ABPMC-GSE1 MB96F635ABPMC-GSE2 Company name and layout design change NOTE: Please see “Document History” about later revised information. Document Number: 002-04719 Rev.*A Page 67 of 69 MB96630 Series Document History Document Title: MB96630 Series F2MC-16FX 16-Bit Microcontroller Document Number: 002-04719 Revision ECN ** - Orig. of Submission Change Date KSUN 01/31/2014 Description of Change Migrated to Cypress and assigned document number 002-04719. No change to document contents or format. *A 5138484 KSUN Document Number: 002-04719 Rev.*A 02/19/2016 Updated to Cypress format. Page 68 of 69 MB96630 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface Lighting & Power Control cypress.com/go/interface cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF Spansion Products psoc.cypress.com/solutions cypress.com/go/wireless cypress.com/spansionproducts © Cypress Semiconductor Corporation 2011-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. 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Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04719 Rev.*A February 19, 2016 Page 69 of 69