MB96F655ABPMC-GSE1

The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB96650 Series F2MC-16FX 16-bit Microcontroller MB96650 series is based on Cypress’s advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of F 2MC-16LX Software to the new F2MC-16FX products. F2MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology Low voltage detection function 0.18m CMOS Reset is generated when supply voltage falls below programmable reference voltage CPU Code Security  F2MC-16FX CPU Protects Flash Memory content from unintended read-out  Optimized instruction set for controller applications (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers) DMA Automatic transfer function independent of CPU, can be assigned freely to resources  8-byte instruction queue  Signed multiply (16-bit  16-bit) and divide (32-bit/16-bit) instructions available Interrupts System clock  Fast Interrupt processing  On-chip PLL clock multiplier (1 to 8, 1 when PLL stop)  8 programmable priority levels  4MHz to 8MHz crystal oscillator  Non-Maskable Interrupt (NMI) (maximum frequency when using ceramic resonator depends on Q-factor)  Up to 8MHz external clock for devices with fast clock input feature  100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog  Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals  The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power or External reset  Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)  Bit rates up to 1Mbps  32 message objects  Each message object has its own identifier mask  Programmable FIFO mode (concatenation of message objects)  Maskable interrupt  Disabled Automatic Retransmission mode for Time Triggered CAN applications  Programmable loop-back mode for self-test operation USART On-chip voltage regulator Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption Document Number: 002-04707 Rev. *B  Supports CAN protocol version 2.0 part A and B  ISO16845 certified  32.768kHz subsystem quartz clock Cypress Semiconductor Corporation CAN •  Full duplex USARTs (SCI/LIN) 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 9, 2018 MB96650 Series  Wide range of baud rate settings using a dedicated reload timer  Special synchronous options for adapting to different synchronous serial protocols  LIN functionality working either as master or slave LIN device  Extended support for LIN-Protocol to reduce interrupt load Output Compare Units  16-bit wide  Signals an interrupt when a match with Free-running Timer occurs  A pair of compare registers can be used to generate an output signal I2C Programmable Pulse Generator  Up to 400kbps  16-bit down counter, cycle and duty setting registers  Master and Slave functionality, 7-bit and 10-bit addressing  Can be used as 2  8-bit PPG A/D converter  Interrupt at trigger, counter borrow and/or duty match  SAR-type  PWM operation and one-shot operation  8/10-bit resolution  Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock  Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger, reload timers and PPGs as counter clock or of selected Reload timer underflow as clock input  Can be triggered by software or reload timer  Can trigger ADC conversion  Range Comparator Function  Timing point capture  Scan Disable Function  Start delay Source Clock Timers Quadrature Position/Revolution Counter (QPRC) Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) Hardware Watchdog Timer  Hardware watchdog timer is active after reset  Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval  Up/down count mode, Phase difference count mode, Count mode with direction  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers with interrupt  Detection edge of the three external event input pins AIN, BIN and ZIN is configurable Reload Timers  16-bit wide  Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency  Event count function Real Time Clock  Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)  Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) Free-Running Timers  Read/write accessible second/minute/hour registers  Signals an interrupt on overflow, supports timer clear upon  Can signal interrupts every half match with Output Compare (0, 4)  Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28 of second/second/minute/hour/day  Internal clock divider and prescaler provide exact 1s clock peripheral clock frequency External Interrupts Input Capture Units  Edge or Level sensitive  16-bit wide  Interrupt mask bit per channel  Signals an interrupt upon external event  Each available CAN channel RX has an external interrupt for  Rising edge, Falling edge or Both (rising & falling) edges sensitive wake-up  Selected USART channels SIN have an external interrupt for wake-up Document Number: 002-04707 Rev. *B Page 2 of 66 MB96650 Series Non Maskable Interrupt Flash Memory  Disabled after reset, can be enabled by Boot-ROM  Dual operation flash allowing reading of one Flash bank depending on ROM configuration block  Once enabled, can not be disabled other than by reset  High or Low level sensitive while programming or erasing the other bank  Command sequencer for automatic execution of programming algorithm and for supporting DMA for programming of the Flash Memory  Pin shared with external interrupt 0  Supports automatic programming, Embedded Algorithm I/O Ports  Write/Erase/Erase-Suspend/Resume commands  Most of the external pins can be used as general purpose I/O  A flag indicating completion of the automatic algorithm  All push-pull outputs (except when used as I2C SDA/SCL  Erase can be performed on each sector individually line)  Sector protection  Bit-wise programmable as input/output or peripheral signal  Flash Security feature to protect the content of the Flash  Bit-wise programmable input enable  Low voltage detection during Flash erase or write  One input level per GPIO-pin (either Automotive or CMOS hysteresis)  Bit-wise programmable pull-up resistor Built-in On Chip Debugger (OCD)  One-wire debug tool interface  Break function:  Hardware  -Software break: 6 points (shared with code event) break: 4096 points  Event function  Code event: 6 points (shared with hardware break) event: 6 points  Event sequencer: 2 levels + reset  -Data  Execution time measurement function  Trace function: 42 branches  Security function Document Number: 002-04707 Rev. *B Page 3 of 66 MB96650 Series Contents 1. Product Lineup .................................................................................................................................................................. 5 2. Block Diagram ................................................................................................................................................................... 6 3. Pin Assignment ................................................................................................................................................................. 7 4. Pin Description .................................................................................................................................................................. 8 5. Pin Circuit Type ............................................................................................................................................................... 10 6. I/O Circuit Type................................................................................................................................................................ 14 7. Memory Map .................................................................................................................................................................... 19 8. Ramstart Addresses ....................................................................................................................................................... 20 9. User ROM Memory Map for Flash Devices ................................................................................................................... 21 10. Serial Programming Communication Interface ............................................................................................................ 22 11. Interrupt Vector Table ..................................................................................................................................................... 23 12. Handling Precautions ..................................................................................................................................................... 27 12.1 Precautions for Product Design ................................................................................................................................... 27 12.2 Precautions for Package Mounting .............................................................................................................................. 28 12.3 Precautions for Use Environment ................................................................................................................................ 29 13. Handling Devices ............................................................................................................................................................ 30 14. Electrical Characteristics ............................................................................................................................................... 33 14.1 Absolute Maximum Ratings ......................................................................................................................................... 33 14.2 Recommended Operating Conditions.......................................................................................................................... 35 14.3 DC Characteristics....................................................................................................................................................... 36 14.3.1 Current Rating .............................................................................................................................................................. 36 14.3.2 Pin Characteristics ....................................................................................................................................................... 40 14.4 AC Characteristics ....................................................................................................................................................... 42 14.4.1 Main Clock Input Characteristics .................................................................................................................................. 42 14.4.2 Sub Clock Input Characteristics ................................................................................................................................... 44 14.4.3 Built-in RC Oscillation Characteristics .......................................................................................................................... 45 14.4.4 Internal Clock Timing ................................................................................................................................................... 45 14.4.5 Operating Conditions of PLL ........................................................................................................................................ 46 14.4.6 Reset Input ................................................................................................................................................................... 46 14.4.7 Power-on Reset Timing................................................................................................................................................ 47 14.4.8 USART Timing ............................................................................................................................................................. 48 14.4.9 External Input Timing ................................................................................................................................................... 50 14.4.10 I2C Timing ................................................................................................................................................................. 51 14.5 A/D Converter .............................................................................................................................................................. 52 14.5.1 Electrical Characteristics for the A/D Converter ........................................................................................................... 52 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time ......................................................................................... 53 14.5.3 Definition of A/D Converter Terms ............................................................................................................................... 54 14.6 Low Voltage Detection Function Characteristics ......................................................................................................... 56 14.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 58 15. Example Characteristics ................................................................................................................................................ 59 16. Ordering Information ...................................................................................................................................................... 62 17. Package Dimension ........................................................................................................................................................ 63 18. Major Changes ................................................................................................................................................................ 64 Document History ................................................................................................................................................................. 65 Document Number: 002-04707 Rev. *B Page 4 of 66 MB96650 Series 1. Product Lineup Features Product Type Subclock Dual Operation Flash Memory 64.5KB + 32KB 128.5KB + 32KB 256.5KB + 32KB 384.5KB + 32KB Package DMA USART with automatic LIN-Header transmission/reception with 16 byte RX- and TX-FIFO I2C 8/10-bit A/D Converter with Data Buffer with Range Comparator with Scan Disable with ADC Pulse Detection 16-bit Reload Timer (RLT) 16-bit Free-Running Timer (FRT) MB96650 RAM 10KB 16KB 24KB 28KB 16-bit Input Capture Unit (ICU) Product Options R: MCU with CAN A: MCU without CAN Yes (only 1ch) LIN-USART 0 LIN-USART 0 to 2/4/5/7 No 2ch 29ch No Yes Yes No 5ch 3ch 7ch (1 channel for LIN-USART) 16-bit Output Compare Unit (OCU) 7ch 8/16-bit Programmable Pulse Generator (PPG) with Timing point capture with Start delay with Ramp Quadrature Position/Revolution Counter (QPRC) 16ch (16-bit) / 32ch (8-bit) Yes Yes No CAN Interface 1ch External Interrupts (INT) Non-Maskable Interrupt (NMI) Real Time Clock (RTC) Clock Calibration Unit (CAL) Clock Output Function 16ch 1ch 1ch 99 (Dual clock mode) 101 (Single clock mode) 1ch 2ch Low Voltage Detection Function Yes Hardware Watchdog Timer On-chip RC-oscillator On-chip Debugger Yes Yes Yes I/O Ports Remark Flash Memory Product Subclock can be set by software MB96F653R, MB96F653A MB96F655R, MB96F655A MB96F656R MB96F657R LQFP-120: LQM120 4ch 6ch 2ch I2C 0/1 AN 0 to 28 RLT 0 to 3/6 FRT 0 to 2 ICU 0/1/4 to 7/9 ICU 9 for LIN-USART OCU 0 to 4/6/7 (OCU 4 for FRT clear) PPG 0 to 15 QPRC 0/1 CAN 0 32 Message Buffers INT 0 to 15 Low voltage detection function can be disabled by software Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the general I/O port according to your function use. Document Number: 002-04707 Rev. *B Page 5 of 66 MB96650 Series 2. Block Diagram NMI CKOT0, CKOT0_R, CKOT1, CKOT1_R CKOTX0, CKOTX1, CKOTX1_R X0, X1 X0A, X1A RSTX MD Interrupt Controller Flash Memory A DEBUG I/F 16FX CPU OCD Clock & Mode Controller 16FX Core Bus (CLKB) Peripheral Bus Bridge Watchdog 2 IC 2ch AVcc AVss AVRH AVRL AN0 to AN28 ADTG 8/10-bit ADC 29ch TIN0 to TIN3 TIN1_R, TIN2_R TOT0 to TOT3 TOT1_R, TOT2_R 16-bit Reload Timer 0/1/2/3/6 5ch FRCK0, FRCK0_R IN0, IN0_R, IN1, IN1_R I/O Timer 0 FRT0 ICU 0/1 OCU 0/1/2/3 OUT0 to OUT3 OUT0_R to OUT3_R FRCK1 IN6, IN7 IN4_R to IN7_R OUT6, OUT7 I/O Timer 1 FRT1 ICU 4/5/6/7 OCU 4/6/7 Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) SDA0, SDA1 SCL0, SCL1 RAM CAN Interface 1ch USART 6ch Peripheral Bus 1 (CLKP1) DMA Controller Boot ROM Voltage Regulator RX0 Vcc Vss C TX0 SIN0 to SIN2, SIN4, SIN5, SIN7, SIN5_R, SIN7_R SOT0 to SOT2, SOT4, SOT5, SOT7, SOT5_R, SOT7_R SCK0 to SCK2, SCK4, SCK5, SCK7, SCK5_R, SCK7_R TTG0 to TTG7, TTG12 to TTG15 PPG 16ch (16-bit)/ 32ch (8-bit) PPG0 to PPG7, PPG12 to PPG15 PPG0_R to PPG5_R, PPG8_R to PPG13_R PPG0_B to PPG15_B AIN0, AIN1 QPRC 2ch BIN0, BIN1 ZIN0, ZIN1 FRCK2 INT0 to INT15 INT1_R to INT7_R Document Number: 002-04707 Rev. *B I/O Timer 2 FRT2 ICU 9 External Interrupt 16ch Real Time Clock WOT, WOT_R Page 6 of 66 MB96650 Series 3. Pin Assignment Vcc P00_2 / INT5_R P00_1 / INT4_R P00_0 / INT3_R / FRCK2 P12_7 / INT1_R P12_6 / TOT2_R / PPG3_B P12_5 / TIN2_R / PPG2_B P12_4 / OUT3_R P12_3 / OUT2_R P12_2 / TOT1_R / PPG1_B P12_1 / TIN1_R / PPG0_B P12_0 / IN1_R / BIN1 P11_7 / IN0_R / AIN1 P11_6 / FRCK0_R / ZIN1 P11_5 / PPG4_R P11_4 / PPG3_R P11_3 / PPG2_R P11_2 / PPG1_R P11_1 / PPG0_R P11_0 RSTX P04_1 / X1A*3 P04_0 / X0A*3 Vss X1 X0 MD P17_0 DEBUG I/F Vss (Top view) 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 91 59 92 58 93 57 94 56 95 55 96 54 97 53 98 52 99 51 100 50 101 49 102 48 103 47 104 46 105 45 106 44 107 43 108 42 109 41 110 40 111 39 112 38 113 37 114 36 115 35 116 34 117 33 118 32 119 31 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LQFP - 120 Vcc P10_3 / PPG7 P10_2 / SCK2 / PPG6*1 P10_1 / SOT2 / TOT3 P10_0 / SIN2 / TIN3 / AN28 / INT11*1 P09_7 / PPG15 P17_2 / PPG13_R P17_1 / PPG12_R P09_6 / PPG14 P09_5 / PPG13 P09_4 / PPG12 P09_3 / AN27 / PPG11_R P09_2 / AN26 / PPG10_R P09_1 / AN25 / PPG9_R P09_0 / AN24 / PPG8_R P08_7 / AN23 / PPG7_B P08_6 / AN22 / PPG6_B P08_5 / AN21 / OUT7 P04_7 / SCL1*2 P04_6 / SDA1*2 P08_4 / AN20 / OUT6 P08_3 / AN19 P08_2 / AN18 P08_1 / AN17 P08_0 / AN16 P05_7 / AN15 / TOT2 P05_6 / AN14 / TIN2 P05_5 / AN13 P05_4 / AN12 / INT2_R / WOT_R Vss Vss C P03_7 / INT1 / SIN1*1 P13_0 / INT2 / SOT1 P13_1 / INT3 / SCK1*1 P13_2 / PPG0 / TIN0 / FRCK1 P13_3 / PPG1 / TOT0 / WOT P13_4 / SIN0 / INT6*1 P13_5 / SOT0 / ADTG / INT7 P13_6 / SCK0 / CKOTX0*1 P13_7 / PPG2 / CKOT0 P04_4 / PPG3 / SDA0*2 P04_5 / PPG4 / SCL0*2 P06_0 / AN0 / SCK5*1 P06_1 / AN1 / SOT5 P06_2 / AN2 / INT5 / SIN5*1 P06_3 / AN3 / FRCK0 P06_4 / AN4 / IN0 / TTG0 / TTG4 P06_5 / AN5 / IN1 / TTG1 / TTG5 P06_6 / AN6 / TIN1 / IN4_R P06_7 / AN7 / TOT1 / IN5_R AVcc AVRH AVRL AVss P05_0 / AN8 P05_1 / AN9 P05_2 / AN10 / OUT2 P05_3 / AN11 / OUT3 Vcc Vss P00_3 / INT6_R / PPG8_B P00_4 / INT7_R / PPG9_B P00_5 / IN6 / TTG2 / TTG6 / PPG10_B P00_6 / IN7 / TTG3 / TTG7 / PPG11_B P00_7 / INT14 P01_0 / SCK7*1 P01_1 / CKOT1 / OUT0 / SOT7 P01_2 / CKOTX1 / OUT1 / INT15 / SIN7*1 P01_3 / PPG5 P01_4 / SIN4 / INT8*1 P01_5 / SOT4 P01_6 / SCK4 / TTG12*1 P01_7 / CKOTX1_R / INT9 / TTG13 / ZIN0 / SCK7_R*1 P02_0 / CKOT1_R / INT10 / TTG14 / AIN0 / SOT7_R P02_1 / IN6_R / TTG15 P02_2 / IN7_R / CKOT0_R / INT12 / BIN0 / SIN7_R*1 P02_3 / PPG12_B P02_4 / PPG13_B P02_5 / OUT0_R / INT13 / SIN5_R*1 P02_6 / OUT1_R P02_7 / PPG5_R P03_0 / PPG4_B P03_1 / PPG5_B P03_2 / PPG14_B / SOT5_R P03_3 / PPG15_B / SCK5_R*1 P03_4 / RX0 / INT4*1 P03_5 / TX0 P03_6 / INT0 / NMI Vcc (LQM120) *1: CMOS input level only *2: CMOS input level only for I2C *3: Please set ROM Configuration Block (RCB) to use the subclock. Other than those above, general-purpose pins have only Automotive input level. Document Number: 002-04707 Rev. *B Page 7 of 66 MB96650 Series 4. Pin Description Pin name Feature Description ADTG ADC A/D converter trigger input pin AINn QPRC Quadrature Position/Revolution Counter Unit n input pin ANn ADC A/D converter channel n input pin AVcc Supply Analog circuits power supply pin AVRH ADC A/D converter high reference voltage input pin AVRL ADC A/D converter low reference voltage input pin AVss Supply Analog circuits power supply pin BINn QPRC Quadrature Position/Revolution Counter Unit n input pin C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock Output function Clock Output function n output pin CKOTn_R Clock Output function Relocated Clock Output function n output pin CKOTXn Clock Output function Clock Output function n inverted output pin CKOTXn_R Clock Output function Relocated Clock Output function n inverted output pin DEBUG I/F OCD On Chip Debugger input/output pin FRCKn Free-Running Timer Free-Running Timer n input pin FRCKn_R Free-Running Timer Relocated Free-Running Timer n input pin INn ICU Input Capture Unit n input pin INn_R ICU Relocated Input Capture Unit n input pin INTn External Interrupt External Interrupt n input pin INTn_R External Interrupt Relocated External Interrupt n input pin MD Core Input pin for specifying the operating mode NMI External Interrupt Non-Maskable Interrupt input pin OUTn OCU Output Compare Unit n waveform output pin OUTn_R OCU Relocated Output Compare Unit n waveform output pin Pnn_m GPIO General purpose I/O pin PPGn PPG Programmable Pulse Generator n output pin (16bit/8bit) PPGn_R PPG Relocated Programmable Pulse Generator n output pin (16bit/8bit) PPGn_B PPG Programmable Pulse Generator n output pin (16bit/8bit) RSTX Core Reset input pin RXn CAN CAN interface n RX input pin SCKn USART USART n serial clock input/output pin SCKn_R USART Relocated USART n serial clock input/output pin 2 SCLn IC I2C interface n clock I/O input/output pin SDAn I2C I2C interface n serial data I/O input/output pin SINn USART USART n serial data input pin SINn_R USART Relocated USART n serial data input pin SOTn USART USART n serial data output pin SOTn_R USART Relocated USART n serial data output pin TINn Reload Timer Reload Timer n event input pin TINn_R Reload Timer Relocated Reload Timer n event input pin Document Number: 002-04707 Rev. *B Page 8 of 66 MB96650 Series Pin name Feature Description TOTn Reload Timer Reload Timer n output pin TOTn_R Reload Timer Relocated Reload Timer n output pin TTGn PPG Programmable Pulse Generator n trigger input pin TXn CAN CAN interface n TX output pin Vcc Supply Power supply pin Vss Supply Power supply pin WOT RTC Real Time clock output pin WOT_R RTC Relocated Real Time clock output pin X0 Clock Oscillator input pin X0A Clock Subclock Oscillator input pin X1 Clock Oscillator output pin X1A Clock Subclock Oscillator output pin ZINn QPRC Quadrature Position/Revolution Counter Unit n input pin Document Number: 002-04707 Rev. *B Page 9 of 66 MB96650 Series 5. Pin Circuit Type Pin no. I/O circuit type* Pin name 1 Supply Vss 2 F C 3 M P03_7 / INT1 / SIN1 4 H P13_0 / INT2 / SOT1 5 M P13_1 / INT3 / SCK1 6 H P13_2 / PPG0 / TIN0 / FRCK1 7 H P13_3 / PPG1 / TOT0 / WOT 8 M P13_4 / SIN0 / INT6 9 H P13_5 / SOT0 / ADTG / INT7 10 M P13_6 / SCK0 / CKOTX0 11 H P13_7 / PPG2 / CKOT0 12 N P04_4 / PPG3 / SDA0 13 N P04_5 / PPG4 / SCL0 14 I P06_0 / AN0 / SCK5 15 K P06_1 / AN1 / SOT5 16 I P06_2 / AN2 / INT5 / SIN5 17 K P06_3 / AN3 / FRCK0 18 K P06_4 / AN4 / IN0 / TTG0 / TTG4 19 K P06_5 / AN5 / IN1 / TTG1 / TTG5 20 K P06_6 / AN6 / TIN1 / IN4_R 21 K P06_7 / AN7 / TOT1 / IN5_R 22 Supply AVcc 23 G AVRH 24 G AVRL 25 Supply AVss 26 K P05_0 / AN8 27 K P05_1 / AN9 28 K P05_2 / AN10 / OUT2 29 K P05_3 / AN11 / OUT3 30 Supply Vcc 31 Supply Vss 32 K P05_4 / AN12 / INT2_R / WOT_R 33 K P05_5 / AN13 34 K P05_6 / AN14 / TIN2 35 K P05_7 / AN15 / TOT2 36 K P08_0 / AN16 Document Number: 002-04707 Rev. *B Page 10 of 66 MB96650 Series Pin no. I/O circuit type* Pin name 37 K P08_1 / AN17 38 K P08_2 / AN18 39 K P08_3 / AN19 40 K P08_4 / AN20 / OUT6 41 N P04_6 / SDA1 42 N P04_7 / SCL1 43 K P08_5 / AN21 / OUT7 44 K P08_6 / AN22 / PPG6_B 45 K P08_7 / AN23 / PPG7_B 46 K P09_0 / AN24 / PPG8_R 47 K P09_1 / AN25 / PPG9_R 48 K P09_2 / AN26 / PPG10_R 49 K P09_3 / AN27 / PPG11_R 50 H P09_4 / PPG12 51 H P09_5 / PPG13 52 H P09_6 / PPG14 53 H P17_1 / PPG12_R 54 H P17_2 / PPG13_R 55 H P09_7 / PPG15 56 I P10_0 / SIN2 / TIN3 / AN28 / INT11 57 H P10_1 / SOT2 / TOT3 58 M P10_2 / SCK2 / PPG6 59 H P10_3 / PPG7 60 Supply Vcc 61 Supply Vss 62 O DEBUG I/F 63 H P17_0 64 C MD 65 A X0 66 A X1 67 Supply Vss 68 B P04_0 / X0A 69 B P04_1 / X1A 70 C RSTX 71 H P11_0 72 H P11_1 / PPG0_R 73 H P11_2 / PPG1_R 74 H P11_3 / PPG2_R 75 H P11_4 / PPG3_R Document Number: 002-04707 Rev. *B Page 11 of 66 MB96650 Series Pin no. I/O circuit type* Pin name 76 H P11_5 / PPG4_R 77 H P11_6 / FRCK0_R / ZIN1 78 H P11_7 / IN0_R / AIN1 79 H P12_0 / IN1_R / BIN1 80 H P12_1 / TIN1_R / PPG0_B 81 H P12_2 / TOT1_R / PPG1_B 82 H P12_3 / OUT2_R 83 H P12_4 / OUT3_R 84 H P12_5 / TIN2_R / PPG2_B 85 H P12_6 / TOT2_R / PPG3_B 86 H P12_7 / INT1_R 87 H P00_0 / INT3_R / FRCK2 88 H P00_1 / INT4_R 89 H P00_2 / INT5_R 90 Supply Vcc 91 Supply Vss 92 H P00_3 / INT6_R / PPG8_B 93 H P00_4 / INT7_R / PPG9_B 94 H P00_5 / IN6 / TTG2 / TTG6 / PPG10_B 95 H P00_6 / IN7 / TTG3 / TTG7 / PPG11_B 96 H P00_7 / INT14 97 M P01_0 / SCK7 98 H P01_1 / CKOT1 / OUT0 / SOT7 99 M P01_2 / CKOTX1 / OUT1 / INT15 / SIN7 100 H P01_3 / PPG5 101 M P01_4 / SIN4 / INT8 102 H P01_5 / SOT4 103 M P01_6 / SCK4 / TTG12 104 M P01_7 / CKOTX1_R / INT9 / TTG13 / ZIN0 / SCK7_R 105 H P02_0 / CKOT1_R / INT10 / TTG14 / AIN0 / SOT7_R 106 H P02_1 / IN6_R / TTG15 107 M P02_2 / IN7_R / CKOT0_R / INT12 / BIN0 / SIN7_R 108 H P02_3 / PPG12_B 109 H P02_4 / PPG13_B 110 M P02_5 / OUT0_R / INT13 / SIN5_R 111 H P02_6 / OUT1_R 112 H P02_7 / PPG5_R 113 H P03_0 / PPG4_B 114 H P03_1 / PPG5_B Document Number: 002-04707 Rev. *B Page 12 of 66 MB96650 Series Pin no. I/O circuit type* Pin name 115 H P03_2 / PPG14_B / SOT5_R 116 M P03_3 / PPG15_B / SCK5_R 117 M P03_4 / RX0 / INT4 118 H P03_5 / TX0 119 H P03_6 / INT0 / NMI 120 Supply Vcc *: See “ I/O circuit type” for details on the I/O circuit types. Document Number: 002-04707 Rev. *B Page 13 of 66 MB96650 Series 6. I/O Circuit Type Type Circuit Remarks A High-speed oscillation circuit:  Programmable between X1 oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) R 0 1 FCI X0 X out  Feedback resistor = approx. 1.0M  The amplitude: 1.8V±0.15V to operate by the internal supply voltage FCI or Osc disable Document Number: 002-04707 Rev. *B Page 14 of 66 MB96650 Series Type Circuit Remarks B Pull-up control Low-speed oscillation circuit shared with GPIO functionality:  Feedback resistor = approx. 5.0M P-ch Standby control for input shutdown P-ch N-ch  GPIO functionality selectable Pout (CMOS level output (IOL = 4mA, IOH = -4mA), Automotive input with input shutdown function and programmable pull-up resistor) Nout R Automotive input X1A R X out 0 1 FCI X0A FCI or Osc disable Pull-up control P-ch Standby control for input shutdown P-ch Pout N-ch Nout R C Document Number: 002-04707 Rev. *B Automotive input CMOS hysteresis input pin Page 15 of 66 MB96650 Series Type Circuit Remarks F Power supply input protection circuit P-ch N-ch G  A/D converter ref+ (AVRH)/ ref- (AVRL) power supply input pin with protection circuit P-ch  Without protection circuit against VCC for pins AVRH/AVRL N-ch H  CMOS level output Pull-up control (IOL = 4mA, IOH = -4mA)  Automotive input with input shutdown function P-ch P-ch Pout N-ch Nout  Programmable pull-up resistor R Standby control for input shutdown Automotive input I  CMOS level output Pull-up control (IOL = 4mA, IOH = -4mA)  CMOS hysteresis input with input shutdown function P-ch P-ch Pout  Programmable pull-up resistor  Analog input N-ch Nout R Hysteresis input Standby control for input shutdown Analog input Document Number: 002-04707 Rev. *B Page 16 of 66 MB96650 Series Type Circuit Remarks K  CMOS level output Pull-up control (IOL = 4mA, IOH = -4mA)  Automotive input with input P-ch P-ch Pout shutdown function  Programmable pull-up resistor  Analog input N-ch Nout R Automotive input Standby control for input shutdown Analog input M  CMOS level output Pull-up control (IOL = 4mA, IOH = -4mA)  CMOS hysteresis input with input shutdown function P-ch P-ch Pout N-ch Nout R  Programmable pull-up resistor Hysteresis input Standby control for input shutdown N  CMOS level output Pull-up control (IOL = 3mA, IOH = -3mA)  CMOS hysteresis input with input shutdown function P-ch P-ch N-ch R Pout Nout*  Programmable pull-up resistor *: N-channel transistor has slew rate control according to I2C spec, irrespective of usage. Hysteresis input Standby control for input shutdown Document Number: 002-04707 Rev. *B Page 17 of 66 MB96650 Series Type Circuit Remarks O  Open-drain I/O  Output 25mA, Vcc = 2.7V  TTL input N-ch Nout R Standby control for input shutdown Document Number: 002-04707 Rev. *B TTL input Page 18 of 66 MB96650 Series 7. Memory Map FF:FFFFH USER ROM*1 DE:0000H DD:FFFFH Reserved 10:0000H 0F:C000H Boot-ROM Peripheral 0E:9000H Reserved 01:0000H 00:8000H RAMSTART0*2 ROM/RAM MIRROR Internal RAM bank0 Reserved 00:0C00H 00:0380H Peripheral 00:0180H GPR*3 00:0100H DMA 00:00F0H Reserved 00:0000H Peripheral *1: For details about USER ROM area, see “ USER ROM MEMORY MAP FOR FLASH DEVICES” on the following pages. *2: For RAMSTART addresses, see the table on the next page. *3: Unused GPR banks can be used as RAM area. GPR: General-Purpose Register The DMA area is only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. Document Number: 002-04707 Rev. *B Page 19 of 66 MB96650 Series 8. Ramstart Addresses Bank 0 RAM size Devices RAMSTART0 MB96F653 10KB 00:5A00H MB96F655 16KB 00:4200H MB96F656 24KB 00:2200H MB96F657 28KB 00:1200H Document Number: 002-04707 Rev. *B Page 20 of 66 MB96650 Series 9. User ROM Memory Map for Flash Devices CPU mode address Flash memory mode address FF:FFFFH 3F:FFFFH FF:0000H 3F:0000H FE:FFFFH 3E:FFFFH FE:0000H 3E:0000H FD:FFFFH 3D:FFFFH FD:0000H 3D:0000H FC:FFFFH 3C:FFFFH FC:0000H 3C:0000H FB:FFFFH 3B:FFFFH FB:0000H 3B:0000H FA:FFFFH 3A:FFFFH FA:0000H 3A:0000H MB96F653 MB96F655 MB96F656 Flash size Flash size Flash size Flash size 64.5KB + 32KB 128.5KB + 32KB 256.5KB + 32KB 384.5KB + 32KB SA39 - 64KB SA39 - 64KB SA39 - 64KB SA39 - 64KB SA38 - 64KB SA38 - 64KB SA38 - 64KB SA37 - 64KB SA37 - 64KB SA36 - 64KB SA36 - 64KB MB96F657 Bank A of Flash A SA35 - 64KB SA34 - 64KB F9:FFFFH Reserved Reserved Reserved Reserved DF:A000H DF:9FFFH 1F:9FFFH DF:8000H 1F:8000H DF:7FFFH 1F:7FFFH DF:6000H 1F:6000H DF:5FFFH 1F:5FFFH DF:4000H 1F:4000H DF:3FFFH 1F:3FFFH DF:2000H 1F:2000H DF:1FFFH 1F:1FFFH DF:0000H 1F:0000H SA4 - 8KB SA4 - 8KB SA4 - 8KB SA3 - 8KB SA3 - 8KB SA3 - 8KB SA3 - 8KB SA2 - 8KB SA2 - 8KB SA2 - 8KB SA2 - 8KB SA1 - 8KB SA1 - 8KB SA1 - 8KB SA1 - 8KB SAS - 512B* SAS - 512B* SAS - 512B* SAS - 512B* Reserved Reserved Reserved Reserved SA4 - 8KB Bank B of Flash A DE:FFFFH DE:0000H Bank A of Flash A *: Physical address area of SAS-512B is from DF:0000H to DF:01FFH. Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B. Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH. SAS can not be used for E2PROM emulation. Document Number: 002-04707 Rev. *B Page 21 of 66 MB96650 Series 10. Serial Programming Communication Interface USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode) MB96650 Pin Number USART Number 8 9 Normal Function SIN0 USART0 SOT0 10 SCK0 3 SIN1 4 USART1 SOT1 5 SCK1 56 SIN2 57 USART2 SOT2 58 SCK2 101 SIN4 102 USART4 103 Document Number: 002-04707 Rev. *B SOT4 SCK4 Page 22 of 66 MB96650 Series 11. Interrupt Vector Table Vector number Offset in vector table Index in ICR to program Cleared by DMA Vector name Description 0 3FCH CALLV0 No - CALLV instruction 1 3F8H CALLV1 No - CALLV instruction 2 3F4H CALLV2 No - CALLV instruction 3 3F0H CALLV3 No - CALLV instruction 4 3ECH CALLV4 No - CALLV instruction 5 3E8H CALLV5 No - CALLV instruction 6 3E4H CALLV6 No - CALLV instruction 7 3E0H CALLV7 No - CALLV instruction 8 3DCH RESET No - Reset vector 9 3D8H INT9 No - INT9 instruction 10 3D4H EXCEPTION No - Undefined instruction execution 11 3D0H NMI No - Non-Maskable Interrupt 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Clock Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH LVDI No 16 Low Voltage Detector 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H EXTINT1 Yes 18 External Interrupt 1 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H EXTINT5 Yes 22 External Interrupt 5 23 3A0H EXTINT6 Yes 23 External Interrupt 6 24 39CH EXTINT7 Yes 24 External Interrupt 7 25 398H EXTINT8 Yes 25 External Interrupt 8 26 394H EXTINT9 Yes 26 External Interrupt 9 27 390H EXTINT10 Yes 27 External Interrupt 10 28 38CH EXTINT11 Yes 28 External Interrupt 11 29 388H EXTINT12 Yes 29 External Interrupt 12 30 384H EXTINT13 Yes 30 External Interrupt 13 31 380H EXTINT14 Yes 31 External Interrupt 14 32 37CH EXTINT15 Yes 32 External Interrupt 15 33 378H CAN0 No 33 CAN Controller 0 34 374H - - 34 Reserved 35 370H - - 35 Reserved 36 36CH - - 36 Reserved 37 368H - - 37 Reserved 38 364H PPG0 Yes 38 Programmable Pulse Generator 0 39 360H PPG1 Yes 39 Programmable Pulse Generator 1 Document Number: 002-04707 Rev. *B Page 23 of 66 MB96650 Series Vector number Offset in vector table Index in ICR to program Cleared by DMA Vector name Description 40 35CH PPG2 Yes 40 Programmable Pulse Generator 2 41 358H PPG3 Yes 41 Programmable Pulse Generator 3 42 354H PPG4 Yes 42 Programmable Pulse Generator 4 43 350H PPG5 Yes 43 Programmable Pulse Generator 5 44 34CH PPG6 Yes 44 Programmable Pulse Generator 6 45 348H PPG7 Yes 45 Programmable Pulse Generator 7 46 344H PPG8 Yes 46 Programmable Pulse Generator 8 47 340H PPG9 Yes 47 Programmable Pulse Generator 9 48 33CH PPG10 Yes 48 Programmable Pulse Generator 10 49 338H PPG11 Yes 49 Programmable Pulse Generator 11 50 334H PPG12 Yes 50 Programmable Pulse Generator 12 51 330H PPG13 Yes 51 Programmable Pulse Generator 13 52 32CH PPG14 Yes 52 Programmable Pulse Generator 14 53 328H PPG15 Yes 53 Programmable Pulse Generator 15 54 324H - - 54 Reserved 55 320H - - 55 Reserved 56 31CH - - 56 Reserved 57 318H - - 57 Reserved 58 314H RLT0 Yes 58 Reload Timer 0 59 310H RLT1 Yes 59 Reload Timer 1 60 30CH RLT2 Yes 60 Reload Timer 2 61 308H RLT3 Yes 61 Reload Timer 3 62 304H - - 62 Reserved 63 300H - - 63 Reserved 64 2FCH RLT6 Yes 64 Reload Timer 6 65 2F8H ICU0 Yes 65 Input Capture Unit 0 66 2F4H ICU1 Yes 66 Input Capture Unit 1 67 2F0H - - 67 Reserved 68 2ECH - - 68 Reserved 69 2E8H ICU4 Yes 69 Input Capture Unit 4 70 2E4H ICU5 Yes 70 Input Capture Unit 5 71 2E0H ICU6 Yes 71 Input Capture Unit 6 72 2DCH ICU7 Yes 72 Input Capture Unit 7 73 2D8H - - 73 Reserved 74 2D4H ICU9 Yes 74 Input Capture Unit 9 75 2D0H - - 75 Reserved 76 2CCH - - 76 Reserved 77 2C8H OCU0 Yes 77 Output Compare Unit 0 78 2C4H OCU1 Yes 78 Output Compare Unit 1 79 2C0H OCU2 Yes 79 Output Compare Unit 2 80 2BCH OCU3 Yes 80 Output Compare Unit 3 Document Number: 002-04707 Rev. *B Page 24 of 66 MB96650 Series Vector number Offset in vector table Index in ICR to program Cleared by DMA Vector name Description 81 2B8H OCU4 Yes 81 Output Compare Unit 4 82 2B4H - - 82 Reserved 83 2B0H OCU6 Yes 83 Output Compare Unit 6 84 2ACH OCU7 Yes 84 Output Compare Unit 7 85 2A8H - - 85 Reserved 86 2A4H - - 86 Reserved 87 2A0H - - 87 Reserved 88 29CH - - 88 Reserved 89 298H FRT0 Yes 89 Free-Running Timer 0 90 294H FRT1 Yes 90 Free-Running Timer 1 91 290H FRT2 Yes 91 Free-Running Timer 2 92 28CH - - 92 Reserved 93 288H RTC0 No 93 Real Time Clock 94 284H CAL0 No 94 Clock Calibration Unit 95 280H - - 95 Reserved 96 27CH IIC0 Yes 96 I2C interface 0 97 278H IIC1 Yes 97 I2C interface 1 98 274H ADC0 Yes 98 A/D Converter 0 99 270H - - 99 Reserved 100 26CH - - 100 Reserved 101 268H LINR0 Yes 101 LIN USART 0 RX 102 264H LINT0 Yes 102 LIN USART 0 TX 103 260H LINR1 Yes 103 LIN USART 1 RX 104 25CH LINT1 Yes 104 LIN USART 1 TX 105 258H LINR2 Yes 105 LIN USART 2 RX 106 254H LINT2 Yes 106 LIN USART 2 TX 107 250H - - 107 Reserved 108 24CH - - 108 Reserved 109 248H LINR4 Yes 109 LIN USART 4 RX 110 244H LINT4 Yes 110 LIN USART 4 TX 111 240H LINR5 Yes 111 LIN USART 5 RX 112 23CH LINT5 Yes 112 LIN USART 5 TX 113 238H - - 113 Reserved 114 234H - - 114 Reserved 115 230H LINR7 Yes 115 LIN USART 7 RX 116 22CH LINT7 Yes 116 LIN USART 7 TX 117 228H - - 117 Reserved 118 224H - - 118 Reserved 119 220H - - 119 Reserved 120 21CH - - 120 Reserved Document Number: 002-04707 Rev. *B Page 25 of 66 MB96650 Series Vector number Offset in vector table Cleared by DMA Vector name Index in ICR to program Description 121 218H - - 121 Reserved 122 214H - - 122 Reserved 123 210H - - 123 Reserved 124 20CH - - 124 Reserved 125 208H - - 125 Reserved 126 204H - - 126 Reserved 127 200H - - 127 Reserved 128 1FCH - - 128 Reserved 129 1F8H - - 129 Reserved 130 1F4H - - 130 Reserved 131 1F0H - - 131 Reserved 132 1ECH - - 132 Reserved 133 1E8H FLASHA Yes 133 Flash memory A interrupt 134 1E4H - - 134 Reserved 135 1E0H - - 135 Reserved 136 1DCH - - 136 Reserved 137 1D8H QPRC0 Yes 137 Quad Position/Revolution counter 0 138 1D4H QPRC1 Yes 138 Quad Position/Revolution counter 1 139 1D0H ADCRC0 No 139 A/D Converter 0 - Range Comparator 140 1CCH - - 140 Reserved 141 1C8H - - 141 Reserved 142 1C4H - - 142 Reserved 143 1C0H - - 143 Reserved Document Number: 002-04707 Rev. *B Page 26 of 66 MB96650 Series 12. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 12.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence.  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-04707 Rev. *B Page 27 of 66 MB96650 Series  Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 12.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions.  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-04707 Rev. *B Page 28 of 66 MB96650 Series  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 12.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04707 Rev. *B Page 29 of 66 MB96650 Series 13. Handling Devices Special care is required for the following when handling the device:  Latch-up prevention  Unused pins handling  External clock usage  Notes on PLL clock mode operation  Power supply pins (Vcc/Vss)  Crystal oscillator and ceramic resonator circuit  Turn on sequence of power supply to A/D converter and analog inputs  Pin handling when not using the A/D converter  Notes on Power-on  Stabilization of power supply voltage  Serial communication  Mode Pin (MD) 1. Latch-up prevention CMOS IC chips may suffer latch-up under the following conditions: - A voltage higher than VCC or lower than VSS is applied to an input or output pin. - A voltage higher than the rated voltage is applied between Vcc pins and Vss pins. - The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 2. Unused pins handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which should be more than 2k. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. Document Number: 002-04707 Rev. *B Page 30 of 66 MB96650 Series 3. External clock usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: (1) Single phase external clock for Main oscillator When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open. And supply 1.8V power to the external clock. X0 X1 (2) Single phase external clock for Sub oscillator When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO. (3) Opposite phase external clock When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V. X0 X1 4. Notes on PLL clock mode operation If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 5. Power supply pins (Vcc/Vss) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance. The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs. Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F between Vcc and Vss pins as close as possible to Vcc and Vss pins. Document Number: 002-04707 Rev. *B Page 31 of 66 MB96650 Series 6. Crystal oscillator and ceramic resonator circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 7. Turn on sequence of power supply to A/D converter and analog inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, AVRH must not exceed AVCC . Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 8. Pin handling when not using the A/D converter If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AV CC = VCC, AVSS = AVRH =AVRL = VSS. 9. Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50s from 0.2V to 2.7V. 10. Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation safety range of the V CC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50Hz to 60Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for power supply switching. 11. Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. 12. Mode Pin (MD) Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a low-impedance connection. Document Number: 002-04707 Rev. *B Page 32 of 66 MB96650 Series 14. Electrical Characteristics 14.1 Absolute Maximum Ratings Parameter Symbol Condition Rating Unit VCC - AVCC - VSS - 0.3 VSS + 6.0 V VCC = AVCC*2 Analog reference voltage*1 AVRH, AVRL - VSS - 0.3 VSS + 6.0 V AVCC≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS Input voltage*1 Output voltage*1 Maximum Clamp Current Total Maximum Clamp Current "L" level maximum output current "L" level average output current "L" level maximum overall output current "L" level average overall output current "H" level maximum output current "H" level average output current "H" level maximum overall output current "H" level average overall output current Power consumption*5 Operating ambient temperature Storage temperature VI VO - VSS - 0.3 VSS - 0.3 VSS + 6.0 VSS + 6.0 V V ICLAMP - -4.0 +4.0 mA Σ|ICLAMP| - - 33 mA IOL - - 15 mA IOLAV - - 4 mA ΣIOL - - 82 mA ΣIOLAV - - 41 mA IOH - - -15 mA IOHAV - - -4 mA ΣIOH - - -82 mA ΣIOHAV - - -41 Power supply voltage* Analog power supply voltage*1 1 Max VSS + 6.0 V Remarks Min VSS - 0.3 VI ≤ VCC + 0.3V*3 VO ≤ VCC + 0.3V*3 Applicable to general purpose I/O pins *4 Applicable to general purpose I/O pins *4 mA *6 PD TA= +125°C - 446 mW TA - -40 +125*7 °C TSTG - -55 +150 °C *1: This parameter is based on VSS = AVSS = 0V. *2: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the I CLAMP rating supersedes the VI rating. Input/Output voltages of standard ports depend on VCC. *4: • Applicable to all general purpose I/O pins (Pnn_m). • Use within recommended operating conditions. • Use at DC voltage (current). • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the V CC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset. • The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current (4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6.0V. Document Number: 002-04707 Rev. *B Page 33 of 66 MB96650 Series • Sample recommended circuits: Protective diode VCC Limiting resistance P-ch +B input (0V to 16V) N-ch R *5: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = Σ (VOL  IOL + VOH  IOH) (I/O load power dissipation, sum is performed on all I/O ports) PINT = VCC  (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming. IA is the analog current consumption into AVCC. *6: Worst case value for a package mounted on single layer PCB at specified T A without air flow. *7: Write/erase to a large sector in flash memory is warranted with TA ≤ + 105°C. WARNING Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04707 Rev. *B Page 34 of 66 MB96650 Series 14.2 Recommended Operating Conditions (VSS = AVSS = 0V) Parameter Symbol Power supply voltage VCC, AVCC Smoothing capacitor at C pin CS Value Typ Min Max Unit 2.7 - 5.5 V 2.0 - 5.5 V 0.5 1.0 to 3.9 4.7 F Remarks Maintains RAM data in stop mode 1.0F (Allowance within ± 50%) 3.9µF (Allowance within ± 20%) Please use the ceramic capacitor or the capacitor of the frequency response of this level. The smoothing capacitor at VCC must use the one of a capacity value that is larger than CS. WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04707 Rev. *B Page 35 of 66 MB96650 Series 14.3 DC Characteristics 14.3.1 Current Rating (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max - 27 - mA TA = +25°C - - 37 mA TA = +105°C - - 38.5 mA TA = +125°C - 3.5 - mA TA = +25°C - - 8 mA TA = +105°C - - 9.5 mA TA = +125°C - 1.8 - mA TA = +25°C - - 6 mA TA = +105°C - - 7.5 mA TA = +125°C - 0.16 - mA TA = +25°C - - 3.5 mA TA = +105°C - - 5 mA TA = +125°C - 0.1 - mA TA = +25°C - - 3.3 mA TA = +105°C - - 4.8 mA TA = +125°C PLL Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32MHz ICCPLL Flash 0 wait (CLKRC and CLKSC stopped) Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz ICCMAIN Flash 0 wait (CLKPLL, CLKSC and CLKRC stopped) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz Power supply current in Run modes*1 ICCRCH Vcc Flash 0 wait (CLKMC, CLKPLL and CLKSC stopped) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz ICCRCL Flash 0 wait (CLKMC, CLKPLL and CLKSC stopped) Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz ICCSUB Flash 0 wait (CLKMC, CLKPLL and CLKRC stopped) Document Number: 002-04707 Rev. *B Page 36 of 66 MB96650 Series Parameter Symbol Pin name PLL Sleep mode with CLKS1/2 = CLKP1/2 = 32MHz (CLKRC and CLKSC stopped) ICCSPLL Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) ICCSMAIN Power supply current in Sleep modes*1 ICCSRCH ICCSRCL ICCSSUB Document Number: 002-04707 Rev. *B Conditions Vcc RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped) RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 100kHz (CLKMC, CLKPLL and CLKSC stopped) Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz, (CLKMC, CLKPLL and CLKRC stopped) Value Typ Min Max Unit Remarks - 8.5 - mA TA = +25°C - - 14 mA TA = +105°C - - 15.5 mA TA = +125°C - 1 - mA TA = +25°C - - 4.5 mA TA = +105°C - - 6 mA TA = +125°C - 0.6 - mA TA = +25°C - - 3.8 mA TA = +105°C - - 5.3 mA TA = +125°C - 0.07 - mA TA = +25°C - - 2.8 mA TA = +105°C - - 4.3 mA TA = +125°C - 0.04 - mA TA = +25°C - - 2.5 mA TA = +105°C - - 4 mA TA = +125°C Page 37 of 66 MB96650 Series Parameter Symbol Pin name ICCTMAIN ICCTRCH Vcc ICCTRCL ICCTSUB Document Number: 002-04707 Rev. *B Value Typ Min Max Unit Remarks - 1800 2250 A TA = +25°C - - 3220 A TA = +105°C - - 4205 A TA = +125°C Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) - 285 330 A TA = +25°C - - 1195 A TA = +105°C - - 2165 A TA = +125°C RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped) - 160 215 A TA = +25°C - - 1095 A TA = +105°C - - 2075 A TA = +125°C - 35 75 A TA = +25°C - - 905 A TA = +105°C - - 1880 A TA = +125°C - 25 65 A TA = +25°C - - 885 A TA = +105°C - - 1850 A TA = +125°C PLL Timer mode with CLKPLL = 32MHz (CLKRC and CLKSC stopped) ICCTPLL Power supply current in Timer modes*2 Conditions RC Timer mode with CLKRC = 100kHz (CLKPLL, CLKMC and CLKSC stopped) Sub Timer mode with CLKSC = 32kHz (CLKMC, CLKPLL and CLKRC stopped) Page 38 of 66 MB96650 Series Parameter Power supply current in Stop mode*3 Flash Power Down current Symbol Pin name ICCH Conditions - ICCFLASHPD - Value Typ Min Unit Max Remarks - 20 60 A TA = +25°C - - 880 A TA = +105°C - - 1845 A TA = +125°C - 36 70 A - 5 - A TA = +25°C - - 12.5 A TA = +125°C - 12.5 - mA TA = +25°C - - 20 mA TA = +125°C Vcc Power supply current for active Low Voltage detector*4 Flash Write/ Erase current*5 ICCLVD ICCFLASH Low voltage detector enabled - *1: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Current for "On Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write / Erase current. *2: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not included. *3: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. *4: When low voltage detector is enabled, ICCLVD must be added to Power supply current. *5: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current. Document Number: 002-04707 Rev. *B Page 39 of 66 MB96650 Series 14.3.2 Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol VIH "H" level input voltage Port inputs Pnn_m Conditions External clock in "Fast Clock Input mode" External clock in "Oscillation mode" VIHX0S X0 VIHX0AS X0A VIHR RSTX - VIHM MD - VIHD DEBUG I/F - VIL Port inputs Pnn_m VILX0S "L" level input voltage Pin name X0 External clock in "Fast Clock Input mode" External clock in "Oscillation mode" VILX0AS X0A VILR RSTX - VILM MD - VILD DEBUG I/F - Document Number: 002-04707 Rev. *B Min VCC  0.7 VCC  0.8 VD  0.8 VCC  0.8 VCC  0.8 VCC - 0.3 2.0 VSS - 0.3 VSS - 0.3 VSS VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Value Typ - Max VCC + 0.3 VCC + 0.3 VD VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC  0.3 VCC  0.5 VD  0.2 VCC  0.2 VCC  0.2 VSS + 0.3 0.8 Unit Remarks V CMOS Hysteresis input V AUTOMOTIVE Hysteresis input V VD=1.8V±0.15V V V CMOS Hysteresis input V CMOS Hysteresis input V TTL Input V CMOS Hysteresis input V AUTOMOTIVE Hysteresis input V VD=1.8V±0.15V V V CMOS Hysteresis input V CMOS Hysteresis input V TTL Input Page 40 of 66 MB96650 Series Parameter Symbol Pin name VOH4 4mA type VOH3 3mA type VOL4 4mA type VOL3 3mA type VOLD DEBUG I/F IIL Pnn_m RPU Pnn_m CIN Other than C, Vcc, Vss, AVcc, AVss, AVRH, AVRL "H" level output voltage "L" level output voltage Input leak current Pull-up resistance value Input capacitance Document Number: 002-04707 Rev. *B Conditions 4.5V ≤ VCC ≤ 5.5V IOH = -4mA 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOH = -3mA 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOL = +4mA 2.7V ≤ VCC < 4.5V IOL = +1.7mA 2.7V ≤ VCC < 5.5V IOL = +3mA VCC = 2.7V IOL = +25mA VSS < VI < VCC AVSS, AVRL < VI < AVCC, AVRH Min Value Typ Max Unit VCC - 0.5 - VCC V VCC - 0.5 - VCC V - - 0.4 V - - 0.4 V 0 - 0.25 V -1 - +1 A VCC = 5.0V ±10% 25 50 100 k - - 5 15 pF Remarks Page 41 of 66 MB96650 Series 14.4 AC Characteristics 14.4.1 Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Symbol fC Pin name X0, X1 fFCI Unit Max 4 - 8 MHz - - 8 MHz 4 - 8 MHz Input frequency Value Typ Min - 8 When using a crystal oscillator, PLL off When using an opposite phase external clock, PLL off When using a crystal oscillator or opposite phase external clock, PLL on MHz When using a single phase external clock in “Fast Clock Input mode”, PLL off When using a single phase external clock in “Fast Clock Input mode”, PLL on X0 4 - 8 MHz Input clock cycle tCYLH - 125 - - ns Input clock pulse width PWH, PWL - 55 - - ns Document Number: 002-04707 Rev. *B Remarks Page 42 of 66 MB96650 Series Document Number: 002-04707 Rev. *B Page 43 of 66 MB96650 Series 14.4.2 Sub Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Pin name Symbol fCL Value Conditions Min Typ Max Unit - - 32.768 - kHz - - - 100 kHz X0A - - - 50 kHz X0A, X1A Input clock cycle tCYLL - - 10 - - s Input clock pulse width - - PWH/tCYLL, PWL/tCYLL 30 - 70 % Document Number: 002-04707 Rev. *B Remarks When using an oscillation circuit When using an opposite phase external clock When using a single phase external clock Page 44 of 66 MB96650 Series 14.4.3 Built-in RC Oscillation Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Value Symbol Clock frequency Min Typ Unit Max 50 100 200 kHz 1 2 4 MHz 80 160 320 s 64 128 256 s Remarks When using slow frequency of RC oscillator When using fast frequency of RC oscillator When using slow frequency of RC oscillator (16 RC clock cycles) When using fast frequency of RC oscillator (256 RC clock cycles) fRC RC clock stabilization time tRCSTAB 14.4.4 Internal Clock Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Value Symbol Min Max Unit Internal System clock frequency (CLKS1 and CLKS2) fCLKS1, fCLKS2 - 54 MHz Internal CPU clock frequency (CLKB), Internal peripheral clock frequency (CLKP1) fCLKB, fCLKP1 - 32 MHz Internal peripheral clock frequency (CLKP2) fCLKP2 - 32 MHz Document Number: 002-04707 Rev. *B Page 45 of 66 MB96650 Series 14.4.5 Operating Conditions of PLL (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time tLOCK 1 - 4 ms For CLKMC = 4MHz PLL input clock frequency fPLLI 4 - 8 MHz PLL oscillation clock frequency fCLKVCO 56 - 108 MHz Permitted VCO output frequency of PLL (CLKVCO) PLL phase jitter tPSKEW -5 - +5 ns For CLKMC (PLL input clock) ≥ 4MHz 14.4.6 Reset Input (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Reset input time tRSTL Value Pin name Min 10 - s 1 - s RSTX Rejection of reset input time Unit Max tRSTL RSTX 0.2VCC Document Number: 002-04707 Rev. *B 0.2VCC Page 46 of 66 MB96650 Series 14.4.7 Power-on Reset Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Value Pin name Min Typ Unit Max Power on rise time tR Vcc 0.05 - 30 ms Power off time tOFF Vcc 1 - - ms Document Number: 002-04707 Rev. *B Page 47 of 66 MB96650 Series 14.4.8 USART Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C, CL=50pF) Symbo l Pin name Serial clock cycle time tSCYC SCK   SOT delay time tSLOVI SOT  SCK  delay time tOVSHI SIN  SCK  setup time tIVSHI SCK   SIN hold time tSHIXI SCKn SCKn, SOTn SCKn, SOTn SCKn, SINn SCKn, SINn Parameter Serial clock "L" pulse width tSLSH SCKn Serial clock "H" pulse width tSHSL SCKn SCK   SOT delay time tSLOVE SIN  SCK  setup time tIVSHE SCK   SIN hold time tSHIXE SCK fall time SCK rise time tF tR Notes: SCKn, SOTn SCKn, SINn SCKn, SINn SCKn SCKn Conditions Internal shift clock mode 4.5V  VCC 5.5V Min Max 2.7V  VCC  4.5V Min Max Uni t 4tCLKP1 - 4tCLKP1 - ns - 20 + 20 - 30 + 30 ns - ns - ns - ns - ns - ns 2tCLKP1 + 55 ns - ns - ns 20 20 ns ns NtCLKP1 – 20* tCLKP1 + 45 0 tCLKP1 + 10 tCLKP1 + 10 External shift clock mode tCLKP1/2 + 10 tCLKP1 + 10 - 2tCLKP1 + 45 20 20 NtCLKP1 – 30* tCLKP1 + 55 0 tCLKP1 + 10 tCLKP1 + 10 tCLKP1/2 + 10 tCLKP1 + 10 - • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “MB96600 series HARDWARE MANUAL”. • tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns • These characteristics only guarantee the same relocate port number.  For example, the combination of SCKn and SOTn_R is not guaranteed. *: Parameter N depends on tSCYC and can be calculated as follows: • If tSCYC = 2  k  tCLKP1, then N = k, where k is an integer > 2 • If tSCYC = (2  k + 1)  tCLKP1, then N = k + 1, where k is an integer > 1 Examples: tSCYC N 4  tCLKP1 2 5  tCLKP1, 6  tCLKP1 3 7  tCLKP1, 8  tCLKP1 4 ... ... Document Number: 002-04707 Rev. *B Page 48 of 66 MB96650 Series tSCYC VOH SCK VOL VOL tOVSHI tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Internal shift clock mode SCK tSHSL tSLSH VIH VIH VIL tF SOT VIL VIH tR tSLOVE VOH VOL SIN tIVSHE VIH VIL tSHIXE VIH VIL External shift clock mode  Document Number: 002-04707 Rev. *B Page 49 of 66 MB96650 Series 14.4.9 External Input Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input pulse width Symbol tINH, tINL Value Pin name Min Max Unit Remarks Pnn_m General Purpose I/O ADTG A/D Converter trigger input TINn, TINn_R TTGn FRCKn, FRCKn_R INn, INn_R Reload Timer PPG trigger input 2tCLKP1 +200 (tCLKP1= 1/fCLKP1)* - ns Free-Running Timer input clock Input Capture AINn, BINn, ZINn Quadrature Position/Revolution Counter INTn, INTn_R NMI 200 - ns External Interrupt Non-Maskable Interrupt *: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode. tINH External input timing VIH tINL VIH VIL Document Number: 002-04707 Rev. *B VIL Page 50 of 66 MB96650 Series 14.4.10 I2C Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol SCL clock frequency (Repeated) START condition hold time SDA   SCL  SCL clock "L" width SCL clock "H" width (Repeated) START condition setup time SCL   SDA  Data hold time SCL   SDA   Data setup time SDA    SCL  STOP condition setup time SCL   SDA  Bus free time between "STOP condition" and "START condition" Pulse width of spikes which will be suppressed by input noise filter Conditions Typical mode High-speed mode*4 Unit fSCL Min 0 Max 100 Min 0 Max 400 kHz tHDSTA 4.0 - 0.6 - s tLOW tHIGH 4.7 4.0 - 1.3 0.6 - s s tSUSTA 4.7 - 0.6 - s 0 3.45*2 0 0.9*3 s tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - s tBUS 4.7 - 1.3 - s 0 (1-1.5) tCLKP1*5 0 (1-1.5) tCLKP1*5 ns tHDDAT tSP CL = 50pF, R = (Vp/IOL)*1 - *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal. *3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250ns". *4: For use at over 100kHz, set the peripheral clock1 (CLKP1) to at least 6MHz. *5: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time. SDA tSUDAT tSUSTA tBUS tLOW SCL tHDSTA tHDDAT Document Number: 002-04707 Rev. *B tHIGH tHDSTA tSP tSUSTO Page 51 of 66 MB96650 Series 14.5 A/D Converter 14.5.1 Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Value Typ Symbol Pin name Resolution - - - - 10 bit Total error - - - 3.0 - + 3.0 LSB Nonlinearity error - - - 2.5 - + 2.5 LSB Differential Nonlinearity error - - - 1.9 - + 1.9 LSB VOT ANn Typ - 20 Typ + 20 mV VFST ANn Typ - 20 Typ + 20 mV Compare time* - - Sampling time* - - 5.0 8.0 3.1 s s s s mA Zero transition voltage Full scale transition voltage IA Power supply current Reference power supply current (between AVRH and AVRL) Analog input capacity IAH AVCC IR Min Max Unit 1.0 2.2 0.5 1.2 - AVRL + 0.5LSB AVRH - 1.5LSB 2.0 - - 3.3 A - 520 810 A A/D Converter active - - 1.0 A A/D Converter not operated - - 15.9 2050 3600 pF   AVRH IRH CVIN ANn Analog impedance RVIN ANn Analog port input current (during conversion) IAIN ANn - 0.3 - + 0.3 A Analog input voltage VAIN ANn AVRL - AVRH V - AVRH AVCC - 0.1 - AVCC V V LSB Reference voltage range Variation between channels Remarks - AVRL AVSS - AVSS + 0.1 - ANn - - 4.0 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V A/D Converter active A/D Converter not operated 4.5V ≤ AVCC ≤ 5.5V 2.7V ≤ AVCC < 4.5V AVSS , AVRL VAIN  AVCC, AVRH *: Time for each channel. Document Number: 002-04707 Rev. *B Page 52 of 66 MB96650 Series 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time (Tsamp) depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin C ext and the AVCC voltage level. The following replacement model can be used for the calculation: MCU Rext Analog input RVIN Source Comparator Cext CVIN Sampling switch (During sampling:ON) Rext: External driving impedance Cext: Capacitance of PCB at A/D converter input CVIN: Analog input capacity (I/O, analog switch and ADC are contained) RVIN: Analog input impedance (I/O, analog switch and ADC are contained) The following approximation formula for the replacement model above can be used: Tsamp = 7.62  (Rext  Cext + (Rext + RVIN)  CVIN)  Do not select a sampling time below the absolute minimum permitted value. (0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V)  If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin.  A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor.  The accuracy gets worse as |AVRH - AVRL| becomes smaller. Document Number: 002-04707 Rev. *B Page 53 of 66 MB96650 Series 14.5.3 Definition of A/D Converter Terms Resolution Nonlinearity error : Analog variation that is recognized by an A/D converter. : Deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→ 0b1111111111). Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the output code by 1LSB. Total error : Difference between the actual value and the theoretical value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Zero transition voltage: Input voltage which results in the minimum conversion value. Full scale transition voltage: Input voltage which results in the maximum conversion value. Nonlinearity error of digital output N = VNT - {1LSB  (N - 1) + VOT} 1LSB Differential nonlinearity error of digital output N = V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VOT 1022 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0x3FE to 0x3FF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. 1LSB = N VOT VFST VNT : : : : Document Number: 002-04707 Rev. *B Page 54 of 66 MB96650 Series 1LSB (Ideal value) = AVRH - AVRL 1024 Total error of digital output N = [V] VNT - {1LSB  (N - 1) + 0.5LSB} 1LSB N : A/D converter digital output value. VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN. VOT (Ideal value) = AVRL + 0.5LSB[V] VFST (Ideal value) = AVRH - 1.5LSB[V] Document Number: 002-04707 Rev. *B Page 55 of 66 MB96650 Series 14.6 Low Voltage Detection Function Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Conditions Value Typ Min Max Unit VDL0 VDL1 CILCR:LVL = 0000B CILCR:LVL = 0001B 2.70 2.79 2.90 3.00 3.10 3.21 V V VDL2 CILCR:LVL = 0010B 2.98 3.20 3.42 V VDL3 CILCR:LVL = 0011B 3.26 3.50 3.74 V VDL4 CILCR:LVL = 0100B 3.45 3.70 3.95 V VDL5 CILCR:LVL = 0111B 3.73 4.00 4.27 V VDL6 CILCR:LVL = 1001B 3.91 4.20 4.49 V Power supply voltage change rate*2 dV/dt - - 0.004 - + 0.004 V/s CILCR:LVHYS=0 - - 50 mV Hysteresis width VHYS CILCR:LVHYS=1 80 100 120 mV Detected voltage *1 Stabilization time TLVDSTAB - - - 75 s Detection delay time td - - - 30 s *1: If the power supply voltage fluctuates within the time less than the detection delay time (t d), there is a possibility that the low voltage detection will occur or stop after the power supply voltage passes the detection range. *2: In order to perform the low voltage detection at the detection voltage (V DLX), be sure to suppress fluctuation of the power supply voltage within the limits of the change ration of power supply voltage. Document Number: 002-04707 Rev. *B Page 56 of 66 MB96650 Series Voltage Vcc dV Detected Voltage dt VDLX max VDLX min Time RCR:LVDE ···Low voltage detection function enable Document Number: 002-04707 Rev. *B Low voltage detection function disable Stabilization time TLVDSTAB Low voltage detection function enable··· Page 57 of 66 MB96650 Series 14.7 Flash Memory Write/Erase Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Sector erase time Word (16-bit) write time Conditions Min Value Typ Unit Max Large Sector TA ≤ + 105°C - 1.6 7.5 s Small Sector - - 0.4 2.1 s Security Sector - - 0.31 1.65 s Large Sector TA ≤ + 105°C - 25 400 s Small Sector - - 25 400 s TA ≤ + 105°C - 11.51 55.05 s Chip erase time Remarks Includes write time prior to internal erase. Not including system-level overhead time. Includes write time prior to internal erase. Note: While the Flash memory is written or erased, shutdown of the external power (V CC) is prohibited. In the application system where the external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function. To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/s to +0.004V/s) after the external power falls below the detection voltage (V DLX)*1. Write/Erase cycles and data hold time Write/Erase cycles (cycle) 1,000 10,000 100,000 Data hold time (year) 20 *2 10 *2 5 *2 *1: See "6. Low Voltage Detection Function Characteristics". *2: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85C). Document Number: 002-04707 Rev. *B Page 58 of 66 MB96650 Series 15. Example Characteristics This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.  MB96F657 Run Mode (VCC = 5.5V) 100.00 PLL clock (32MHz) 10.00 ICC [mA] Main osc. (4MHz) 1.00 RC clock (2MHz) RC clock (100kHz) 0.10 Sub osc. (32kHz) 0.01 -50 0 50 100 150 TA [ºC] Sleep Mode (VCC = 5.5V) 100.000 PLL clock (32MHz) ICC [mA] 10.000 Main osc. (4MHz) 1.000 RC clock (2MHz) 0.100 RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04707 Rev. *B Page 59 of 66 MB96650 Series  MB96F657 Timer Mode (VCC = 5.5V) 10.000 PLL clock (32MHz) ICC [mA] 1.000 Main osc. (4MHz) 0.100 RC clock (2MHz) RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Stop Mode (VCC = 5.5V) 1.000 ICC [mA] 0.100 0.010 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04707 Rev. *B Page 60 of 66 MB96650 Series  Used setting Selected Source Clock Mode Run mode Sleep mode CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz Main osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz RC clock fast CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz RC clock slow CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz Sub osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz PLL CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKMC = 4MHz, CLKPLL = 32MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 4MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 2MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 100kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode CLKMC = 32 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode (All clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode Main osc. RC clock fast RC clock slow Sub osc. Timer mode PLL Main osc. RC clock fast RC clock slow Sub osc. Stop mode Clock/Regulator and FLASH Settings PLL stopped Document Number: 002-04707 Rev. *B Page 61 of 66 MB96650 Series 16. Ordering Information MCU with CAN controller Part number MB96F653RBPMC-GSE1 MB96F653RBPMC-GSE2 MB96F655RBPMC-GSE1 MB96F655RBPMC-GSE2 MB96F656RBPMC-GSE1 MB96F656RBPMC-GSE2 MB96F657RBPMC-GSE1 MB96F657RBPMC-GSE2 Flash memory Package* Flash A (96.5KB) 120-pin plastic LQFP (LQM120) Flash A (160.5KB) 120-pin plastic LQFP (LQM120) Flash A (288.5KB) 120-pin plastic LQFP (LQM120) Flash A (416.5KB) 120-pin plastic LQFP (LQM120) *: For details about package, see "Package Dimension". MCU without CAN controller Part number MB96F653ABPMC-GSE1 MB96F653ABPMC-GSE2 MB96F655ABPMC-GSE1 MB96F655ABPMC-GSE2 Flash memory Package* Flash A (96.5KB) 120-pin plastic LQFP (LQM120) Flash A (160.5KB) 120-pin plastic LQFP (LQM120) *: For details about package, see "Package Dimension". Document Number: 002-04707 Rev. *B Page 62 of 66 MB96650 Series 17. Package Dimension 4 D 5 7 D1 90 61 91 61 60 90 91 60 E1 E 4 5 7 3 6 31 120 1 31 30 e 3 b 0.20 C A-B D 30 2 5 7 0.10 0.08 1 C A-B D C A-B D BOTTOM VIEW 8 TOP VIEW 2 A 9 c θ A A' 0.08 C SEATI N G PLA N E 0.25 A1 10 b SECTION A -A' L SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. 0.05 0.15 A A1 1. 70 b 0.17 c 0.115 0.22 D 18.00 BSC D1 16.00 BSC e 0.50 BSC E 18.00 BSC E1 L θ 0.27 0.195 16.00 BSC 0.45 0° 0.60 0.75 8° 002-16172 ** PACKAGE OUTLINE, 120 LEAD LQFP 18.0X18.0X1.7 M M LQM 120 REV** Document Number: 002-04707 Rev. *B Page 63 of 66 MB96650 Series 18. Major Changes Spansion Publication Number: MB96650_DS704-00003 Page Section Change Results Revision 1.0 - - Initial release Revision 2.0 39 Electrical Characteristics Changed the Value of “Power supply current in Timer modes” DC Characteristics ICCTPLL Current Rating Typ: 2485μA → 1800μA (TA = +25°C) Max: 2715μA → 2250μA (TA = +25°C) Max: 4095μA → 3220μA (TA = +105°C) Max: 5065μA → 4205μA (TA = +125°C) Revision 2.1 - - Company name and layout design change NOTE: Please see “Document History” about later revised information. Page Section Change Results Revision *B 5, 7, 62, 63 1. Product Lineup 3. Pin Assignment 16. Ordering Information 17. Package Dimension Document Number: 002-04707 Rev. *B Package description modified to JEDEC description. FPT-120P-M21 → LQM120 Page 64 of 66 MB96650 Series Document History Document Title: MB96650 Series, F2MC-16FX 16-bit Microcontroller Document Number: 002-04707 Revision ECN Orig. of Change Submission Date **  KSUN 01/31/2014 *A 5164895 KSUN 03/14/2016 Updated to Cypress template *B 6005555 KSUN 01/09/2018 Document Number: 002-04707 Rev. *B Description of Change Migrated to Cypress and assigned document number 002-04707. No change to document contents or format. Updated the Cypress logo, Sales information and legal. Refer to 18. Major Changes. Page 65 of 66 MB96650 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 002-04707 Rev. *B January 9, 2018 Page 66 of 66