MB96F6B5RBPMC-GSE1

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY966B0 Series F2MC-16FX 16-Bit Microcontroller CY966B0 series is based on Cypress advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of F2MC-16LX Software to the new F2MC-16FX products. F2MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features  Technology  Interrupts  Fast Interrupt processing programmable priority levels  Non-Maskable Interrupt (NMI) 0.18m CMOS 8  CPU  F2MC-16FX CPU instruction set for controller applications (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers)  8-byte instruction queue  Signed multiply (16-bit  16-bit) and divide (32-bit/16-bit) instructions available  Optimized  CAN  Supports CAN protocol version 2.0 part A and B certified  Bit rates up to 1Mbps  32 message objects  Each message object has its own identifier mask  Programmable FIFO mode (concatenation of message objects)  Maskable interrupt  Disabled Automatic Retransmission mode for Time Triggered CAN applications  Programmable loop-back mode for self-test operation  ISO16845  System clock PLL clock multiplier (1 to 8, 1 when PLL stop) to 8MHz crystal oscillator (maximum frequency when using ceramic resonator depends on Q-factor)  Up to 8MHz external clock for devices with fast clock input feature  32.768kHz subsystem quartz clock  100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog  Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals  The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power or External reset  Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)  On-chip  4MHz  USART  Full duplex USARTs (SCI/LIN) range of baud rate settings using a dedicated reload timer  Special synchronous options for adapting to different synchronous serial protocols  LIN functionality working either as master or slave LIN device  Extended support for LIN-Protocol with 16-byte FIFO for selected channels to reduce interrupt load  Wide  I2 C  On-chip voltage regulator  Up Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption to 400kbps and Slave functionality, 7-bit and 10-bit addressing  Master  A/D converter  SAR-type  Low voltage detection function  8/10-bit resolution interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger, reload timers and PPGs  Range Comparator Function  Scan Disable Function  ADC Pulse Detection Function Reset is generated when supply voltage falls below programmable reference voltage  Signals  Code Security Protects Flash Memory content from unintended read-out  DMA Automatic transfer function independent of CPU, can be assigned freely to resources  Source Clock Timers Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) Cypress Semiconductor Corporation Document Number: 002-04721 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 21, 2019 CY966B0 Series  Hardware Watchdog Timer  Hardware watchdog timer is active after reset  Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval  Reload Timers  16-bit wide with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency  Event count function  Prescaler  Free-Running Timers  Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0)  Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28 of peripheral clock frequency  Input Capture Units  16-bit wide an interrupt upon external event  Rising edge, Falling edge or Both (rising & falling) edges sensitive  Signals  Output Compare Units  16-bit wide an interrupt when a match with Free-running Timer occurs  A pair of compare registers can be used to generate an output signal  Signals  Programmable Pulse Generator  16-bit down counter, cycle and duty setting registers be used as 2 × 8-bit PPG  Interrupt at trigger, counter borrow and/or duty match  PWM operation and one-shot operation  Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer underflow as clock input  Can be triggered by software or reload timer  Can trigger ADC conversion  Timing point capture  Start delay  Can  Quadrature Position/Revolution Counter (QPRC)  Up/down count mode, Phase difference count mode, Count mode with direction  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers with interrupt  Detection edge of the three external event input pins AIN, BIN and ZIN is configurable  LCD Controller controller with up to 4COM  36SEG or external voltage generation  Duty cycle: Selectable from options: 1/2, 1/3 and 1/4  Fixed 1/3 bias  Programmable frame period  Clock source selectable from four options (main clock, peripheral clock, subclock or RC oscillator clock)  Internal divider resistors or external divider resistors  On-chip data memory for display  LCD display can be operated in Timer Mode  Blank display: selectable  LCD  Internal Document Number: 002-04721 Rev. *C  All SEG, COM and V pins can be switched between general and specialized purposes  Sound Generator  8-bit PWM signal is mixed with tone frequency from 16-bit reload counter  PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock  Real Time Clock  Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)  Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)  Read/write accessible second/minute/hour registers  Can signal interrupts every half second/second/minute/hour/day  Internal clock divider and prescaler provide exact 1s clock  External Interrupts  Edge or Level sensitive mask bit per channel  Each available CAN channel RX has an external interrupt for wake-up  Selected USART channels SIN have an external interrupt for wake-up  Interrupt  Non Maskable Interrupt  Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block  Once enabled, cannot be disabled other than by reset  High or Low level sensitive  Pin shared with external interrupt 0  I/O Ports  Most of the external pins can be used as general purpose I/O  All push-pull outputs (except when used as I2C SDA/SCL line)  Bit-wise programmable as input/output or peripheral signal  Bit-wise programmable input enable  One input level per GPIO-pin (either Automotive or CMOS hysteresis)  Bit-wise programmable pull-up resistor  Some pins offer high current output capability for LED driving.  Built-in On Chip Debugger (OCD)  One-wire debug tool interface function: • Hardware break: 6 points (shared with code event) • Software break: 4096 points  Event function • Code event: 6 points (shared with hardware break) • Data event: 6 points • Event sequencer: 2 levels + reset  Execution time measurement function  Trace function: 42 branches  Security function  Break Page 2 of 75 CY966B0 Series  Flash Memory  Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank  Command sequencer for automatic execution of programming algorithm and for supporting DMA for programming of the Flash Memory  Supports automatic programming, Embedded Algorithm  Write/Erase/Erase-Suspend/Resume commands Document Number: 002-04721 Rev. *C  A flag indicating completion of the automatic algorithm can be performed on each sector individually  Sector protection  Flash Security feature to protect the content of the Flash  Low voltage detection during Flash erases or writes  Erase Page 3 of 75 CY966B0 Series Contents 1. Product Lineup .................................................................................................................................................................. 6 2. Block Diagram ................................................................................................................................................................... 7 3. Pin Assignment ................................................................................................................................................................. 8 4. Pin Description .................................................................................................................................................................. 9 5. Pin Circuit Type ............................................................................................................................................................... 11 6. I/O Circuit Type ............................................................................................................................................................... 14 7. Memory Map .................................................................................................................................................................... 21 8. RAMSTART Addresses................................................................................................................................................... 22 9. User Rom Memory Map for Flash Devices .................................................................................................................... 23 10. Serial Programming Communication Interface ............................................................................................................ 24 11. Interrupt Vector Table ..................................................................................................................................................... 25 12. Handling Precautions ..................................................................................................................................................... 29 12.1 Precautions for Product Design ................................................................................................................................... 29 12.2 Precautions for Package Mounting .............................................................................................................................. 30 12.3 Precautions for Use Environment ................................................................................................................................ 31 13. Handling Devices ............................................................................................................................................................ 32 13.1 Latch-Up Prevention .................................................................................................................................................... 32 13.2 Unused Pins Handling ................................................................................................................................................. 32 13.3 External Clock Usage .................................................................................................................................................. 32 13.3.1 Single Phase External Clock for Main Oscillator .......................................................................................................... 32 13.3.2 Single Phase External Clock for Sub Oscillator ........................................................................................................... 33 13.3.3 Opposite Phase External Clock.................................................................................................................................... 33 13.4 Notes on PLL Clock Mode Operation .......................................................................................................................... 33 13.5 Power Supply Pins (Vcc/Vss) ........................................................................................................................................ 33 13.6 Crystal Oscillator and ceramic resonator Circuit .......................................................................................................... 33 13.7 Turn on Sequence of Power Supply to A/D Converter and Analog Inputs................................................................... 33 13.8 Pin Handling when not using the A/D Converter ......................................................................................................... 34 13.9 Notes on Power-on ...................................................................................................................................................... 34 13.10 Stabilization of Power Supply Voltage ......................................................................................................................... 34 13.11 Serial Communication ................................................................................................................................................. 34 13.12 Mode Pin (MD) ............................................................................................................................................................ 34 14. Electrical Characteristics ............................................................................................................................................... 35 14.1 Absolute Maximum Ratings ......................................................................................................................................... 35 14.2 Recommended Operating Conditions ......................................................................................................................... 37 14.3 DC Characteristics ...................................................................................................................................................... 38 14.3.1 Current Rating .............................................................................................................................................................. 38 14.3.2 Pin Characteristics ....................................................................................................................................................... 42 14.4 AC Characteristics ....................................................................................................................................................... 44 14.4.1 Main Clock Input Characteristics .................................................................................................................................. 44 14.4.2 Sub Clock Input Characteristics ................................................................................................................................... 45 14.4.3 Built-in RC Oscillation Characteristics .......................................................................................................................... 46 14.4.4 Internal Clock Timing ................................................................................................................................................... 46 14.4.5 Operating Conditions of PLL ........................................................................................................................................ 47 14.4.6 Reset Input ................................................................................................................................................................... 47 14.4.7 Power-on Reset Timing ................................................................................................................................................ 48 14.4.8 USART Timing ............................................................................................................................................................. 49 Document Number: 002-04721 Rev. *C Page 4 of 75 CY966B0 Series 14.4.9 External Input Timing ................................................................................................................................................... 51 14.4.10 I2C Timing ................................................................................................................................................................. 52 14.5 A/D Converter .............................................................................................................................................................. 53 14.5.1 Electrical Characteristics for the A/D Converter ........................................................................................................... 53 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time ......................................................................................... 54 14.5.3 Definition of A/D Converter Terms ............................................................................................................................... 55 14.6 High Current Output Slew Rate ................................................................................................................................... 57 14.7 Low Voltage Detection Function Characteristics ......................................................................................................... 58 14.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 60 15. Example Characteristics ................................................................................................................................................ 61 16. Ordering Information ...................................................................................................................................................... 64 17. Package Dimension ........................................................................................................................................................ 65 18. Major Changes ................................................................................................................................................................ 66 Document History ................................................................................................................................................................. 74 Sales, Solutions, and Legal Information ............................................................................................................................. 75 Document Number: 002-04721 Rev. *C Page 5 of 75 CY966B0 Series 1. Product Lineup Features Product Type Subclock Dual Operation Flash Memory RAM CY966B0 Flash Memory Product Subclock can be set by software - 128.5KB + 32KB 8KB CY96F6B5R, CY96F6B5A 256.5KB + 32KB 16KB CY96F6B6R LQFP-100 LQI100 4ch 5ch Package DMA USART with automatic LIN-Header transmission/reception with 16 byte RX- and TX-FIFO Remark Product Options R: MCU with CAN A: MCU without CAN LIN-USART 0 to 2/4/5 2ch LIN-USART 0/1 I2 C 1ch 8/10-bit A/D Converter 27ch I2 C 0 AN 2 to 4/6 to 8/10 to 12/ 14 to 31 with Data Buffer with Range Comparator with Scan Disable with ADC Pulse Detection 16-bit Reload Timer (RLT) 16-bit Free-Running Timer (FRT) No Yes Yes Yes 5ch 2ch 16-bit Input Capture Unit (ICU) 6ch (5 channels for LIN-USART) 16-bit Output Compare Unit (OCU) 8/16-bit Programmable Pulse Generator (PPG) with Timing point capture with Start delay with Ramp Quadrature Position/Revolution Counter (QPRC) 4ch 12ch (16-bit) / 16ch (8-bit) Yes Yes No CAN Interface 1ch External Interrupts (INT) Non-Maskable Interrupt (NMI) Sound Generator (SG) 16ch 1ch 2ch LCD Controller 4COM × 36SEG Real Time Clock (RTC) Clock Calibration Unit (CAL) Clock Output Function 1ch 77 (Dual clock mode) 79 (Single clock mode) 1ch 2ch Low Voltage Detection Function Yes I/O Ports Hardware Watchdog Timer On-chip RC-oscillator On-chip Debugger Note: 2ch RLT 0 to 3/6 FRT 0/1 ICU 0/1/4 to 7 (ICU 0/1/4 to 6 for LIN-USART) OCU 0 to 3 PPG 0 to 7/12 to 15 QPRC 0/1 CAN 0 32 Message Buffers INT 0 to 15 SG 0/1 COM 0 to 3 SEG 0 to 4/7/11 to 28/30/ 33/36 to 45 Low voltage detection function can be disabled by software Yes Yes Yes All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the general I/O port according to your function use. Document Number: 002-04721 Rev. *C Page 6 of 75 CY966B0 Series 2. Block Diagram CKOT0_R, CKOT1, CKOT1_R CKOTX0, CKOTX1, CKOTX1_R X0, X1 X0A, X1A RSTX MD NMI DEBUG I/F 16FX CPU OCD Interrupt Controller Clock & Mode Controller Flash Memory A 16FX Core Bus (CLKB) 2 SDA0 SCL0 AVcc AVss AVRH AVRL AN2 to AN4 AN6 to AN8 AN10 to AN12 AN14 to AN31 ADTG TIN0 to TIN3 TOT0 to TOT3 FRCK0 FRCK0_R IN0 IN0_R, IN1_R OUT0 to OUT3 OUT0_R, OUT2_R IC 1ch 8/10-bit ADC 27ch 16-bit Reload Timer 0/1/2/3/6 5ch I/O Timer 0 FRT0 ICU 0/1 OCU 0/1/2/3 RA M CAN Interface 1ch Sound Generator 2ch USART 5ch PPG 12ch (16-bit) / 16ch (8-bit) Boot ROM Voltage Regulator RX0 Vcc Vss C TX0 SGO0, SGO1, SGO1_R SGA0, SGA1, SGA1_R SIN0 to SIN2, SIN4, SIN5, SIN5_R SOT0 to SOT2, SOT4, SOT5_R SCK0 to SCK2, SCK4, SCK5_R TTG0, TTG2 to TTG4, TTG6, TTG7 TTG12 to TTG14 PPG0, PPG1, PPG3 to PPG7 PPG0_R to PPG4_R, PPG12_R, PPG13_R PPG4_B to PPG7_B, PPG14_B, PPG15_B AIN0, AIN1 QPRC 2ch FRCK1 IN6, IN7 IN4_R, IN5_R, IN7_R V0 to V3 COM0 to COM3 SEG0 to SEG4, SEG7 SEG11 to SEG28 SEG30, SEG33 SEG36 to SEG45 Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) Peripheral Bus Bridge Watchdog Peripheral Bus 1 (CLKP1) DMA Controller ZIN0, ZIN1 I/O Timer 1 FRT1 ICU 4/5/6/7 LCD controller/ driver 4COM×36SEG Document Number: 002-04721 Rev. *C BIN0, BIN1 Real Time Clock WOT, WOT_R External Interrupt 16ch INT0 to INT15 INT1_R to INT7_R Page 7 of 75 CY966B0 Series 3. Pin Assignment Vss P17_0 DEBUG I/F X0 MD Vss X1 P04_1 / X1A*3 P04_0 / X0A*3 P11_0 / COM0 RSTX P11_2 / COM2 / PPG1_R P11_1 / COM1 / PPG0_R P11_4 / SEG0 / PPG3_R P11_3 / COM3 / PPG2_R P11_6 / SEG2 / FRCK0_R / ZIN1 P11_5 / SEG1 / PPG4_R P12_0 / SEG4 / IN1_R / BIN1 P11_7 / SEG3 / IN0_R / AIN1 P12_7 / SEG11 / INT1_R P12_3 / SEG7 / OUT2_R P00_1 / SEG13 / INT4_R P00_0 / SEG12 / INT3_R Vcc Vss P00_2 / SEG14 / INT5_R (Top view) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 Vcc P00_3 / SEG15 / INT6_R 77 49 P10_3 / PPG7 / AN31 P00_4 / SEG16 / INT7_R 78 48 P10_2 / SCK2 / PPG6 / AN30*1 P00_5 / SEG17 / IN6 / TTG2 / TTG6 79 47 P10_1 / SOT2 / TOT3 / AN29 P00_6 / SEG18 / IN7 / TTG3 / TTG7 80 46 P10_0 / SIN2 / TIN3 / INT11 / AN28*1 P00_7 / SEG19 / SGO0 / INT14 81 45 Vss P01_0 / SEG20 / SGA0 82 44 Vcc P01_1 / SEG21 / CKOT1 / OUT0 83 43 P09_3 / AN27 P01_2 / SEG22 / CKOTX1 / OUT1 / INT15 84 42 P09_2 / AN26 P01_3 / SEG23 / PPG5 85 41 P09_1 / AN25 86 40 P09_0 / AN24 39 P08_7 / AN23 / PPG7_B 38 P08_6 / AN22 / PPG6_B 1 P01_4 / SEG24 / SIN4 / INT8* P01_5 / SEG25 / SOT4 1 P01_6 / SEG26 / SCK4 / TTG12* 87 LQFP - 100 88 P01_7 / SEG27 / CKOTX1_R / INT9 / TTG13 / ZIN0 89 37 P08_5 / AN21 P02_0 / SEG28 / CKOT1_R / INT10 / TTG14 / AIN0 90 36 P17_2 / PPG13_R P02_2 / SEG30 / IN7_R / CKOT0_R / INT12 / BIN0 91 35 P17_1 / PPG12_R P02_5 / SEG33 / OUT0_R / INT13 / SIN5_R*1 92 34 P08_4 / AN20 P03_0 / V0 / SEG36 / PPG4_B 93 33 P08_3 / AN19 P03_1 / V1 / SEG37 / PPG5_B 94 32 P08_2 / AN18 P03_2 / V2 / SEG38 / PPG14_B / SOT5_R 95 31 P08_1 / AN17 P03_3 / V3 / SEG39 / PPG15_B / SCK5_R*1 96 30 P08_0 / AN16 P03_4 / RX0 / INT4*1 97 29 P05_7 / AN15 / TOT2 / SGA1_R P03_5 / TX0 98 28 P05_6 / AN14 / TIN2 / SGO1_R P03_6 / INT0 / NMI 99 27 P05_4 / AN12 / INT2_R / WOT_R Vss Vcc P05_3 / AN11 / OUT3 / SGA1 P05_2 / AN10 / OUT2 / SGO1 AVss P05_0 / AN8 AVRL AVRH AVcc P06_7 / AN7 / TOT1 / IN5_R P13_4 / SIN0 / INT6 / SEG45*1 P06_6 / AN6 / TIN1 / IN4_R P13_3 / PPG1 / TOT0 / WOT / SEG44 P06_4 / AN4 / IN0 / TTG0 / TTG4 P13_1 / INT3 / SCK1 / SEG42*1 P13_2 / PPG0 / TIN0 / FRCK1 / SEG43 P06_3 / AN3 / FRCK0 P13_0 / INT2 / SOT1 / SEG41 P06_2 / AN2 / INT5 / SIN5* 8 1 7 P04_5 / PPG4 / SCL0*2 6 P04_4 / PPG3 / SDA0*2 5 P13_6 / SCK0 / CKOTX0*1 4 P13_5 / SOT0 / ADTG / INT7 3 P03_7 / INT1 / SIN1 / SEG40*1 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 C 100 1 Vss Vcc (LQI100) *1: CMOS input level only *2: CMOS input level only for I2C *3: Please set ROM Configuration Block (RCB) to use the subclock. Other than those above, general-purpose pins have only Automotive input level. Document Number: 002-04721 Rev. *C Page 8 of 75 CY966B0 Series 4. Pin Description Pin Name Feature Description ADTG ADC A/D converter trigger input pin AINn QPRC Quadrature Position/Revolution Counter Unit n input pin ANn ADC A/D converter channel n input pin AVcc Supply Analog circuits power supply pin AVRH ADC A/D converter high reference voltage input pin AVRL ADC A/D converter low reference voltage input pin AVss Supply Analog circuits power supply pin BINn QPRC Quadrature Position/Revolution Counter Unit n input pin C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock Output function Clock Output function n output pin CKOTn_R Clock Output function Relocated Clock Output function n output pin CKOTXn Clock Output function Clock Output function n inverted output pin CKOTXn_R Clock Output function Relocated Clock Output function n inverted output pin COMn LCD LCD Common driver pin DEBUG I/F OCD On Chip Debugger input/output pin FRCKn Free-Running Timer Free-Running Timer n input pin FRCKn_R Free-Running Timer Relocated Free-Running Timer n input pin INn ICU Input Capture Unit n input pin INn_R ICU Relocated Input Capture Unit n input pin INTn External Interrupt External Interrupt n input pin INTn_R External Interrupt Relocated External Interrupt n input pin MD Core Input pin for specifying the operating mode NMI External Interrupt Non-Maskable Interrupt input pin OUTn OCU Output Compare Unit n waveform output pin OUTn_R OCU Relocated Output Compare Unit n waveform output pin Pnn_m GPIO General purpose I/O pin PPGn PPG Programmable Pulse Generator n output pin (16bit/8bit) PPGn_R PPG Relocated Programmable Pulse Generator n output pin (16bit/8bit) PPGn_B PPG Programmable Pulse Generator n output pin (16bit/8bit) RSTX Core Reset input pin RXn CAN CAN interface n RX input pin SCKn USART USART n serial clock input/output pin SCKn_R USART Relocated USART n serial clock input/output pin SCLn I2 C I2C interface n clock I/O input/output pin SDAn I2 C I2C interface n serial data I/O input/output pin SEGn LCD LCD Segment driver pin SGAn Sound Generator Sound Generator amplitude output pin SGAn_R Sound Generator Relocated Sound Generator amplitude output pin SGOn Sound Generator Sound Generator sound/tone output pin SGOn_R Sound Generator Relocated Sound Generator sound/tone output pin SINn USART USART n serial data input pin Document Number: 002-04721 Rev. *C Page 9 of 75 CY966B0 Series Pin Name Feature Description SINn_R USART Relocated USART n serial data input pin SOTn USART USART n serial data output pin SOTn_R USART Relocated USART n serial data output pin TINn Reload Timer Reload Timer n event input pin TOTn Reload Timer Reload Timer n output pin TTGn PPG Programmable Pulse Generator n trigger input pin TXn CAN CAN interface n TX output pin Vn LCD LCD voltage reference pin Vcc Supply Power supply pin Vss Supply Power supply pin WOT RTC Real Time clock output pin WOT_R RTC Relocated Real Time clock output pin X0 Clock Oscillator input pin X0A Clock Subclock Oscillator input pin X1 Clock Oscillator output pin X1A Clock Subclock Oscillator output pin ZINn QPRC Quadrature Position/Revolution Counter Unit n input pin Document Number: 002-04721 Rev. *C Page 10 of 75 CY966B0 Series 5. Pin Circuit Type Pin No. I/O Circuit Type* Pin Name 1 Supply Vss 2 F C 3 P P03_7 / INT1 / SIN1 / SEG40 4 J P13_0 / INT2 / SOT1 / SEG41 5 P P13_1 / INT3 / SCK1 / SEG42 6 J P13_2 / PPG0 / TIN0 / FRCK1 / SEG43 7 J P13_3 / PPG1 / TOT0 / WOT / SEG44 8 P P13_4 / SIN0 / INT6 / SEG45 9 H P13_5 / SOT0 / ADTG / INT7 10 M P13_6 / SCK0 / CKOTX0 11 N P04_4 / PPG3 / SDA0 12 N P04_5 / PPG4 / SCL0 13 I P06_2 / AN2 / INT5 / SIN5 14 K P06_3 / AN3 / FRCK0 15 K P06_4 / AN4 / IN0 / TTG0 / TTG4 16 K P06_6 / AN6 / TIN1 / IN4_R 17 K P06_7 / AN7 / TOT1 / IN5_R 18 Supply AVcc 19 G AVRH 20 G AVRL 21 Supply AVss 22 K P05_0 / AN8 23 K P05_2 / AN10 / OUT2 / SGO1 24 K P05_3 / AN11 / OUT3 / SGA1 25 Supply Vcc 26 Supply Vss 27 K P05_4 / AN12 / INT2_R / WOT_R 28 K P05_6 / AN14 / TIN2 / SGO1_R 29 K P05_7 / AN15 / TOT2 / SGA1_R 30 V P08_0 / AN16 31 V P08_1 / AN17 32 V P08_2 / AN18 33 V P08_3 / AN19 34 V P08_4 / AN20 35 H P17_1 / PPG12_R 36 H P17_2 / PPG13_R 37 V P08_5 / AN21 38 V P08_6 / AN22 / PPG6_B Document Number: 002-04721 Rev. *C Page 11 of 75 CY966B0 Series Pin No. I/O Circuit Type* Pin Name 39 V P08_7 / AN23 / PPG7_B 40 V P09_0 / AN24 41 V P09_1 / AN25 42 V P09_2 / AN26 43 V P09_3 / AN27 44 Supply Vcc 45 Supply Vss 46 W P10_0 / SIN2 / TIN3 / INT11 / AN28 47 V P10_1 / SOT2 / TOT3 / AN29 48 W P10_2 / SCK2 / PPG6 / AN30 49 V P10_3 / PPG7 / AN31 50 Supply Vcc 51 Supply Vss 52 O DEBUG I/F 53 H P17_0 54 C MD 55 A X0 56 A X1 57 Supply Vss 58 B P04_0 / X0A 59 B P04_1 / X1A 60 C RSTX 61 J P11_0 / COM0 62 J P11_1 / COM1 / PPG0_R 63 J P11_2 / COM2 / PPG1_R 64 J P11_3 / COM3 / PPG2_R 65 J P11_4 / SEG0 / PPG3_R 66 J P11_5 / SEG1 / PPG4_R 67 J P11_6 / SEG2 / FRCK0_R / ZIN1 68 J P11_7 / SEG3 / IN0_R / AIN1 69 J P12_0 / SEG4 / IN1_R / BIN1 70 J P12_3 / SEG7 / OUT2_R 71 J P12_7 / SEG11 / INT1_R 72 J P00_0 / SEG12 / INT3_R 73 J P00_1 / SEG13 / INT4_R 74 J P00_2 / SEG14 / INT5_R 75 Supply Vcc 76 Supply Vss 77 J P00_3 / SEG15 / INT6_R Document Number: 002-04721 Rev. *C Page 12 of 75 CY966B0 Series Pin No. I/O Circuit Type* Pin Name 78 J P00_4 / SEG16 / INT7_R 79 J P00_5 / SEG17 / IN6 / TTG2 / TTG6 80 J P00_6 / SEG18 / IN7 / TTG3 / TTG7 81 J P00_7 / SEG19 / SGO0 / INT14 82 J P01_0 / SEG20 / SGA0 83 J P01_1 / SEG21 / CKOT1 / OUT0 84 J P01_2 / SEG22 / CKOTX1 / OUT1 / INT15 85 J P01_3 / SEG23 / PPG5 86 P P01_4 / SEG24 / SIN4 / INT8 87 J P01_5 / SEG25 / SOT4 88 P P01_6 / SEG26 / SCK4 / TTG12 89 J P01_7 / SEG27 / CKOTX1_R / INT9 / TTG13 / ZIN0 90 J P02_0 / SEG28 / CKOT1_R / INT10 / TTG14 / AIN0 91 J P02_2 / SEG30 / IN7_R / CKOT0_R / INT12 / BIN0 92 P P02_5 / SEG33 / OUT0_R / INT13 / SIN5_R 93 L P03_0 / V0 / SEG36 / PPG4_B 94 L P03_1 / V1 / SEG37 / PPG5_B 95 L P03_2 / V2 / SEG38 / PPG14_B / SOT5_R 96 Q P03_3 / V3 / SEG39 / PPG15_B / SCK5_R 97 M P03_4 / RX0 / INT4 98 H P03_5 / TX0 99 H P03_6 / INT0 / NMI 100 Supply Vcc *: See “I/O Circuit Type” for details on the I/O circuit types. Document Number: 002-04721 Rev. *C Page 13 of 75 CY966B0 Series 6. I/O Circuit Type Type Circuit Remarks A X1 R 0 1 X out High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Feedback resistor = approx. 1.0M • The amplitude: 1.8V±0.15V to operate by the internal supply voltage FCI X0 FCI or Osc disable Document Number: 002-04721 Rev. *C Page 14 of 75 CY966B0 Series Type Circuit Remarks B Pull-up control P-ch Standby control for input shutdown P-ch Pout N-ch Nout Low-speed oscillation circuit shared with GPIO functionality: • Feedback resistor = approx. 5.0M • GPIO functionality selectable (CMOS level output (IOL = 4mA, IOH = -4mA), Automotive input with input shutdown function and programmable pull-up resistor) R Automotive input X1A R X out 0 1 FCI X0A FCI or Osc disable Pull-up control P-ch Standby control for input shutdown P-ch Pout N-ch Nout R C Document Number: 002-04721 Rev. *C Automotive input CMOS hysteresis input pin Page 15 of 75 CY966B0 Series Type Circuit Remarks F Power supply input protection circuit P-ch N-ch • A/D converter ref+ (AVRH)/ ref(AVRL) power supply input pin with protection circuit • Without protection circuit against VCC for pins AVRH/AVRL G P-ch N-ch H Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor R Standby control for input shutdown Automotive input I Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor • Analog input R Hysteresis input Standby control for input shutdown Analog input Document Number: 002-04721 Rev. *C Page 16 of 75 CY966B0 Series Type Circuit Remarks J Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor • SEG or COM output R Automotive input Standby control for input shutdown SEG or COM output K Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor • Analog input R Automotive input Standby control for input shutdown Analog input L Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor • Vn input or SEG output R Automotive input Standby control for input shutdown Vn input or SEG output Document Number: 002-04721 Rev. *C Page 17 of 75 CY966B0 Series Type Circuit Remarks M Pull-up control P-ch P-ch Pout N-ch Nout R • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor Hysteresis input Standby control for input shutdown N Pull-up control P-ch P-ch Pout N-ch Nout* R • CMOS level output (IOL = 3mA, IOH = -3mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor *: N-channel transistor has slew rate control according to I2C spec, irrespective of usage. Hysteresis input Standby control for input shutdown • Open-drain I/O • Output 25mA, Vcc = 2.7V • TTL input O N-ch Nout R Standby control for input shutdown Document Number: 002-04721 Rev. *C TTL input Page 18 of 75 CY966B0 Series Type Circuit Remarks P Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis inputs with input shutdown function • Programmable pull-up resistor • SEG or COM output R Hysteresis input Standby control for input shutdown SEG or COM output Q Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis inputs with input shutdown function • Programmable pull-up resistor • Vn input or SEG output R Hysteresis input Standby control for input shutdown Vn input or SEG output V Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (programmable IOL = 4mA, IOH = -4mA and IOL = 20mA, IOH = -20mA) • Automotive input with input shutdown function • Programmable pull-up resistor • Analog input R Automotive input Standby control for input shutdown Analog input Document Number: 002-04721 Rev. *C Page 19 of 75 CY966B0 Series Type Circuit Remarks W Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (programmable IOL = 4mA, IOH = -4mA and IOL = 20mA, IOH = -20mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor • Analog input R Hysteresis input Standby control for input shutdown Analog input Document Number: 002-04721 Rev. *C Page 20 of 75 CY966B0 Series 7. Memory Map FF:FFFFH USER ROM*1 DE:0000H DD:FFFFH Reserved 10:0000H 0F:C000H Boot-ROM Peripheral 0E:9000H Reserved 01:0000H 00:8000H RAMSTART0*2 ROM/RAM MIRROR Internal RAM bank0 Reserved 00:0C00H 00:0380H Peripheral 00:0180H GPR*3 00:0100H DMA 00:00F0H Reserved 00:0000H Peripheral *1: For details about USER ROM area, see “User Rom Memory Map for Flash Devices” on the following pages. *2: For RAMSTART Addresses, see the table on the next page. *3: Unused GPR banks can be used as RAM area. GPR: General-Purpose Register The DMA area is only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. Document Number: 002-04721 Rev. *C Page 21 of 75 CY966B0 Series 8. RAMSTART Addresses Bank 0 RAM Size Devices RAMSTART0 CY96F6B5 8KB 00:6200H CY96F6B6 16KB 00:4200H Document Number: 002-04721 Rev. *C Page 22 of 75 CY966B0 Series 9. User Rom Memory Map for Flash Devices *: Physical address area of SAS-512B is from DF:0000H to DF:01FFH. Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B. Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH. SAS cannot be used for E2PROM emulation. Document Number: 002-04721 Rev. *C Page 23 of 75 CY966B0 Series 10. Serial Programming Communication Interface USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode) CY966B0 Pin Number USART Number 8 9 Normal Function SIN0 USART0 SOT0 10 SCK0 3 SIN1 4 USART1 SOT1 5 SCK1 46 SIN2 47 USART2 SOT2 48 SCK2 86 SIN4 87 USART4 88 Document Number: 002-04721 Rev. *C SOT4 SCK4 Page 24 of 75 CY966B0 Series 11. Interrupt Vector Table Vector Number Offset in Vector Table Index in ICR to Program Cleared by DMA Vector Name Description 0 3FCH CALLV0 No - CALLV instruction 1 3F8H CALLV1 No - CALLV instruction 2 3F4H CALLV2 No - CALLV instruction 3 3F0H CALLV3 No - CALLV instruction 4 3ECH CALLV4 No - CALLV instruction 5 3E8H CALLV5 No - CALLV instruction 6 3E4H CALLV6 No - CALLV instruction 7 3E0H CALLV7 No - CALLV instruction 8 3DCH RESET No - Reset vector 9 3D8H INT9 No - INT9 instruction 10 3D4H EXCEPTION No - Undefined instruction execution 11 3D0H NMI No - Non-Maskable Interrupt 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Clock Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH LVDI No 16 Low Voltage Detector 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H EXTINT1 Yes 18 External Interrupt 1 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H EXTINT5 Yes 22 External Interrupt 5 23 3A0H EXTINT6 Yes 23 External Interrupt 6 24 39CH EXTINT7 Yes 24 External Interrupt 7 25 398H EXTINT8 Yes 25 External Interrupt 8 26 394H EXTINT9 Yes 26 External Interrupt 9 27 390H EXTINT10 Yes 27 External Interrupt 10 28 38CH EXTINT11 Yes 28 External Interrupt 11 29 388H EXTINT12 Yes 29 External Interrupt 12 30 384H EXTINT13 Yes 30 External Interrupt 13 31 380H EXTINT14 Yes 31 External Interrupt 14 32 37CH EXTINT15 Yes 32 External Interrupt 15 33 378H CAN0 No 33 CAN Controller 0 34 374H - - 34 Reserved 35 370H - - 35 Reserved 36 36CH - - 36 Reserved 37 368H - - 37 Reserved 38 364H PPG0 Yes 38 Programmable Pulse Generator 0 39 360H PPG1 Yes 39 Programmable Pulse Generator 1 Document Number: 002-04721 Rev. *C Page 25 of 75 CY966B0 Series Vector Number Offset in Vector Table Index in ICR to Program Cleared by DMA Vector Name Description 40 35CH PPG2 Yes 40 Programmable Pulse Generator 2 41 358H PPG3 Yes 41 Programmable Pulse Generator 3 42 354H PPG4 Yes 42 Programmable Pulse Generator 4 43 350H PPG5 Yes 43 Programmable Pulse Generator 5 44 34CH PPG6 Yes 44 Programmable Pulse Generator 6 45 348H PPG7 Yes 45 Programmable Pulse Generator 7 46 344H - - 46 Reserved 47 340H - - 47 Reserved 48 33CH - - 48 Reserved 49 338H - - 49 Reserved 50 334H PPG12 Yes 50 Programmable Pulse Generator 12 51 330H PPG13 Yes 51 Programmable Pulse Generator 13 52 32CH PPG14 Yes 52 Programmable Pulse Generator 14 53 328H PPG15 Yes 53 Programmable Pulse Generator 15 54 324H - - 54 Reserved 55 320H - - 55 Reserved 56 31CH - - 56 Reserved 57 318H - - 57 Reserved 58 314H RLT0 Yes 58 Reload Timer 0 59 310H RLT1 Yes 59 Reload Timer 1 60 30CH RLT2 Yes 60 Reload Timer 2 61 308H RLT3 Yes 61 Reload Timer 3 62 304H - - 62 Reserved 63 300H - - 63 Reserved 64 2FCH RLT6 Yes 64 Reload Timer 6 65 2F8H ICU0 Yes 65 Input Capture Unit 0 66 2F4H ICU1 Yes 66 Input Capture Unit 1 67 2F0H - - 67 Reserved 68 2ECH - - 68 Reserved 69 2E8H ICU4 Yes 69 Input Capture Unit 4 70 2E4H ICU5 Yes 70 Input Capture Unit 5 71 2E0H ICU6 Yes 71 Input Capture Unit 6 72 2DCH ICU7 Yes 72 Input Capture Unit 7 73 2D8H - - 73 Reserved 74 2D4H - - 74 Reserved 75 2D0H - - 75 Reserved 76 2CCH - - 76 Reserved 77 2C8H OCU0 Yes 77 Output Compare Unit 0 78 2C4H OCU1 Yes 78 Output Compare Unit 1 79 2C0H OCU2 Yes 79 Output Compare Unit 2 80 2BCH OCU3 Yes 80 Output Compare Unit 3 81 2B8H - - 81 Reserved Document Number: 002-04721 Rev. *C Page 26 of 75 CY966B0 Series Vector Number Offset in Vector Table Index in ICR to Program Cleared by DMA Vector Name Description 82 2B4H - - 82 Reserved 83 2B0H - - 83 Reserved 84 2ACH - - 84 Reserved 85 2A8H - - 85 Reserved 86 2A4H - - 86 Reserved 87 2A0H - - 87 Reserved 88 29CH - - 88 Reserved 89 298H FRT0 Yes 89 Free-Running Timer 0 90 294H FRT1 Yes 90 Free-Running Timer 1 91 290H - - 91 Reserved 92 28CH - - 92 Reserved 93 288H RTC0 No 93 Real Time Clock 94 284H CAL0 No 94 Clock Calibration Unit 95 280H SG0 No 95 Sound Generator 0 96 27CH IIC0 Yes 96 I2C interface 0 97 278H - - 97 Reserved 98 274H ADC0 Yes 98 A/D Converter 0 99 270H - - 99 Reserved 100 26CH - - 100 Reserved 101 268H LINR0 Yes 101 LIN USART 0 RX 102 264H LINT0 Yes 102 LIN USART 0 TX 103 260H LINR1 Yes 103 LIN USART 1 RX 104 25CH LINT1 Yes 104 LIN USART 1 TX 105 258H LINR2 Yes 105 LIN USART 2 RX 106 254H LINT2 Yes 106 LIN USART 2 TX 107 250H - - 107 Reserved 108 24CH - - 108 Reserved 109 248H LINR4 Yes 109 LIN USART 4 RX 110 244H LINT4 Yes 110 LIN USART 4 TX 111 240H LINR5 Yes 111 LIN USART 5 RX 112 23CH LINT5 Yes 112 LIN USART 5 TX 113 238H - - 113 Reserved 114 234H - - 114 Reserved 115 230H - - 115 Reserved 116 22CH - - 116 Reserved 117 228H - - 117 Reserved 118 224H - - 118 Reserved 119 220H - - 119 Reserved 120 21CH - - 120 Reserved Document Number: 002-04721 Rev. *C Page 27 of 75 CY966B0 Series 121 218H SG1 No Index in ICR to Program 121 122 214H - - 122 Reserved 123 210H - - 123 Reserved 124 20CH - - 124 Reserved 125 208H - - 125 Reserved 126 204H - - 126 Reserved 127 200H - - 127 Reserved 128 1FCH - - 128 Reserved 129 1F8H - - 129 Reserved 130 1F4H - - 130 Reserved 131 1F0H - - 131 Reserved 132 1ECH - - 132 Reserved 133 1E8H FLASHA Yes 133 Flash memory A interrupt 134 1E4H - - 134 Reserved 135 1E0H - - 135 Reserved 136 1DCH - - 136 137 1D8H QPRC0 Yes 137 138 1D4H QPRC1 Yes 138 139 1D0H ADCRC0 No 139 Reserved Quadrature Position/Revolution counter 0 Quadrature Position/Revolution counter 1 A/D Converter 0 - Range Comparator 140 1CCH ADCPD0 No 140 A/D Converter 0 - Pulse detection 141 1C8H - - 141 Reserved 142 1C4H - - 142 Reserved 143 1C0H - - 143 Reserved Vector Number Offset in Vector Table Document Number: 002-04721 Rev. *C Cleared by DMA Vector Name Description Sound Generator 1 Page 28 of 75 CY966B0 Series 12. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 12.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence.  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-04721 Rev. *C Page 29 of 75 CY966B0 Series  Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 12.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions.  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-04721 Rev. *C Page 30 of 75 CY966B0 Series  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies. 12.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04721 Rev. *C Page 31 of 75 CY966B0 Series 13. Handling Devices Special Care is Required for the following when Handling the Device: • • • • • • • • • • • • Latch-up prevention Unused pins handling External clock usage Notes on PLL clock mode operation Power supply pins (Vcc/Vss) Crystal oscillator and ceramic resonator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on Power-on Stabilization of power supply voltage Serial communication Mode Pin (MD) 13.1 Latch-Up Prevention CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between Vcc pins and Vss pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 13.2 Unused Pins Handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which should be more than 2k. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 13.3 External Clock Usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 13.3.1 Single Phase External Clock for Main Oscillator When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open. And supply 1.8V power to the external clock. X0 X1 Document Number: 002-04721 Rev. *C Page 32 of 75 CY966B0 Series 13.3.2 Single Phase External Clock for Sub Oscillator When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO. 13.3.3 Opposite Phase External Clock When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V. X0 X1 13.4 Notes on PLL Clock Mode Operation If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 13.5 Power Supply Pins (Vcc/Vss) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance. The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs. Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F between Vcc and Vss pins as close as possible to Vcc and Vss pins. 13.6 Crystal Oscillator and ceramic resonator Circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines and to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 13.7 Turn on Sequence of Power Supply to A/D Converter and Analog Inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, AVRH must not exceed AVCC . Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). Document Number: 002-04721 Rev. *C Page 33 of 75 CY966B0 Series 13.8 Pin Handling when not using the A/D Converter If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 13.9 Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50s from 0.2V to 2.7V. 13.10 Stabilization of Power Supply Voltage If the power supply voltage varies acutely even within the operation safety range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50Hz to 60Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for power supply switching. 13.11 Serial Communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. 13.12 Mode Pin (MD) Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a low-impedance connection. Document Number: 002-04721 Rev. *C Page 34 of 75 CY966B0 Series 14. Electrical Characteristics 14.1 Absolute Maximum Ratings Parameter Power supply voltage*1 Analog power supply voltage*1 Analog reference voltage*1 Symbol Rating Condition Min Max Unit Remarks VCC - VSS - 0.3 VSS + 6.0 V AVCC - VSS - 0.3 VSS + 6.0 V VCC = AVCC*2 AVCC≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS AVRH, AVRL - VSS - 0.3 VSS + 6.0 V V0 to V3 - VSS - 0.3 VSS + 6.0 V VI VO - VSS - 0.3 VSS - 0.3 VSS + 6.0 VSS + 6.0 V V ICLAMP - -4.0 +4.0 mA Σ|ICLAMP| - - 26 mA IOL IOLHCO - - 15 20 mA mA V0 to V3 must not exceed VCC VI ≤ VCC + 0.3V*3 VO ≤ VCC + 0.3V*3 Applicable to general purpose I/O pins *4 Applicable to general purpose I/O pins *4 Normal port High current port "L" level average output current IOLAV - - 4 mA Normal port IOLAVHCO - - 15 mA High current port "L" level maximum overall output current ΣIOL - - 64 mA Normal port ΣIOLHCO - - 150 mA High current port "L" level average overall output current ΣIOLAV - - 32 mA Normal port ΣIOLAVHCO - - 100 mA High current port "H" level maximum output current IOH - - -15 mA Normal port IOHHCO IOHAV IOHAVHCO - - -20 -4 -15 mA mA mA High current port Normal port High current port "H" level maximum overall output current ΣIOH - - -64 mA Normal port ΣIOHHCO - - -150 mA High current port "H" level average overall output current ΣIOHAV - - -32 mA Normal port ΣIOHAVHCO - - -100 mA High current port mW LCD power supply voltage*1 Input voltage*1 Output voltage*1 Maximum Clamp Current Total Maximum Clamp Current "L" level maximum output current "H" level average output current Power consumption*5 Operating ambient temperature Storage temperature PD TA= +125°C - 416*6 TA - -40 +125*7 °C TSTG - -55 +150 °C *1: This parameter is based on VSS = AVSS = 0V. *2: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/Output voltages of general I/O ports depend on VCC. Document Number: 002-04721 Rev. *C Page 35 of 75 CY966B0 Series *4: Applicable to all general purpose I/O pins (Pnn_m). • • • • • • • • Use within recommended operating conditions. Use at DC voltage (current). The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset. The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current (4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6.0V. • Sample recommended circuits: Protective diode VCC Limiting resistance P-ch +B input (0V to 16V) N-ch R *5: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = Σ (VOL  IOL + VOH  IOH) (I/O load power dissipation, sum is performed on all I/O ports) PINT = VCC  (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming. IA is the analog current consumption into AVCC. *6: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *7: Write/erase to a large sector in flash memory is warranted with TA ≤ + 105°C. WARNING Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04721 Rev. *C Page 36 of 75 CY966B0 Series 14.2 Recommended Operating Conditions (VSS = AVSS = 0V) Parameter Symbol Power supply voltage VCC, AVCC Smoothing capacitor at C pin CS Min 2.7 2.0 0.5 Value Typ Unit - Max 5.5 5.5 V V 1.0 to 3.9 4.7 F Remarks Maintains RAM data in stop mode 1.0F (Allowance within ± 50%) 3.9µF (Allowance within ± 20%) Please use the ceramic capacitor or the capacitor of the frequency response of this level. The smoothing capacitor at VCC must use the one of a capacity value that is larger than CS. WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04721 Rev. *C Page 37 of 75 CY966B0 Series 14.3 DC Characteristics 14.3.1 Current Rating Parameter Symbol Pin Name (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Conditions Unit Remarks Min Typ Max PLL Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32MHz - 28 - mA TA = +25°C - - 38 mA TA = +105°C (CLKRC and CLKSC stopped) - - 39.5 mA TA = +125°C Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz - 3.5 - mA TA = +25°C Flash 0 wait - - 8 mA TA = +105°C (CLKPLL, CLKSC and CLKRC stopped) - - 9.5 mA TA = +125°C RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz - 1.8 - mA TA = +25°C Flash 0 wait - - 6 mA TA = +105°C (CLKMC, CLKPLL and CLKSC stopped) - - 7.5 mA TA = +125°C RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz - 0.16 - mA TA = +25°C Flash 0 wait - - 3.5 mA TA = +105°C (CLKMC, CLKPLL and CLKSC stopped) - - 5 mA TA = +125°C Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz - 0.1 - mA TA = +25°C Flash 0 wait - - 3.3 mA TA = +105°C (CLKMC, CLKPLL and CLKRC stopped) - - 4.8 mA TA = +125°C ICCPLL Flash 0 wait ICCMAIN Power supply current in Run modes*1 ICCRCH Vcc ICCRCL ICCSUB Document Number: 002-04721 Rev. *C Page 38 of 75 CY966B0 Series Parameter Symbol Pin Name ICCSMAIN ICCSRCH ICCSRCL ICCSSUB Document Number: 002-04721 Rev. *C Vcc Value Typ Min Max Unit Remarks - 9.5 - mA TA = +25°C - - 15 mA TA = +105°C - - 16.5 mA TA = +125°C Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) - 1.1 - mA TA = +25°C - - 4.7 mA TA = +105°C - - 6.2 mA TA = +125°C RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped) - 0.6 - mA TA = +25°C - - 4.1 mA TA = +105°C - - 5.6 mA TA = +125°C - 0.07 - mA TA = +25°C - - 2.9 mA TA = +105°C - - 4.4 mA TA = +125°C - 0.04 - mA TA = +25°C - - 2.7 mA TA = +105°C - - 4.2 mA TA = +125°C PLL Sleep mode with CLKS1/2 = CLKP1/2 = 32MHz (CLKRC and CLKSC stopped) ICCSPLL Power supply current in Sleep modes*1 Conditions RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 100kHz (CLKMC, CLKPLL and CLKSC stopped) Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz, (CLKMC, CLKPLL and CLKRC stopped) Page 39 of 75 CY966B0 Series Parameter Symbol Pin Name ICCTMAIN ICCTRCH Max 2250 A TA = +25°C - - 3220 A TA = +105°C - - 4200 A TA = +125°C Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) - 285 330 A TA = +25°C - - 1200 A TA = +105°C - - 2155 A TA = +125°C RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped) - 160 215 A TA = +25°C - - 1110 A TA = +105°C - - 2065 A TA = +125°C - 35 75 A TA = +25°C - - 910 A TA = +105°C - - 1870 A TA = +125°C - 25 65 A TA = +25°C - - 885 A TA = +105°C - - 1845 A TA = +125°C PLL Timer mode with CLKPLL = 32MHz (CLKRC and CLKSC stopped) ICCTPLL Power supply current in Timer modes*2 - Value Typ 1800 Conditions Vcc ICCTRCL ICCTSUB Document Number: 002-04721 Rev. *C RC Timer mode with CLKRC = 100kHz, (CLKPLL, CLKMC and CLKSC stopped) Sub Timer mode with CLKSC = 32kHz (CLKMC, CLKPLL and CLKRC stopped) Min Unit Remarks Page 40 of 75 CY966B0 Series Parameter Power supply current in Stop mode*3 Flash Power Down current Symbol Pin Name ICCH Conditions - ICCFLASHPD Vcc Power supply current for active Low Voltage detector*4 ICCLVD Flash Write/ Erase current*5 ICCFLASH Value Typ Min Max Unit Remarks - 20 60 A TA = +25°C - - 880 A TA = +105°C - - 1840 A TA = +125°C - 36 70 A - 5 - A TA = +25°C - - 12.5 A TA = +125°C - 12.5 - mA TA = +25°C - - 20 mA TA = +125°C Low voltage detector enabled - *1: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Current for "On Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write / Erase current. *2: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not included. *3: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. *4: When low voltage detector is enabled, ICCLVD must be added to Power supply current. *5: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current. Document Number: 002-04721 Rev. *C Page 41 of 75 CY966B0 Series 14.3.2 Pin Characteristics Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Symbol Pin Name VIH Port inputs Pnn_m VIHX0S X0 VIHX0AS X0A VIHR RSTX VIHM MD VIHD DEBUG I/F VIL Port inputs Pnn_m VILX0S X0 VILX0AS X0A VILR RSTX VILM MD VILD DEBUG I/F VOH4 4mA type VOH20 High Drive type* VOH3 3mA type VOL4 4mA type VOL20 High Drive type* VOL3 3mA type VOLD DEBUG I/F Document Number: 002-04721 Rev. *C (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Conditions Unit Remarks Min Typ Max VCC VCC CMOS Hysteresis V + 0.3 input  0.7 VCC VCC AUTOMOTIVE V + 0.3 Hysteresis input  0.8 VD External clock in VD V VD=1.8V±0.15V "Fast Clock Input mode"  0.8 VCC External clock in VCC V "Oscillation mode" + 0.3  0.8 VCC VCC CMOS Hysteresis V + 0.3 input  0.8 VCC VCC CMOS Hysteresis V - 0.3 + 0.3 input VCC 2.0 V TTL Input + 0.3 VCC VSS CMOS Hysteresis V - 0.3 input  0.3 VCC VSS AUTOMOTIVE V - 0.3 Hysteresis input  0.5 VD External clock in "Fast Clock VSS V VD=1.8V±0.15V Input mode"  0.2 VCC External clock in VSS V "Oscillation mode" - 0.3  0.2 VCC VSS CMOS Hysteresis V - 0.3 input  0.2 VSS VSS CMOS Hysteresis V - 0.3 + 0.3 input VSS 0.8 V TTL Input - 0.3 4.5V ≤ VCC ≤ 5.5V IOH = -4mA VCC VCC V - 0.5 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOH = -20mA VCC VCC V - 0.6 2.7V ≤ VCC < 4.5V IOH = -13mA 4.5V ≤ VCC ≤ 5.5V IOH = -3mA VCC VCC V - 0.5 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOL = +4mA 0.4 V 2.7V ≤ VCC < 4.5V IOL = +1.7mA 4.5V ≤ VCC ≤ 5.5V IOL = +20mA 0.6 V 2.7V ≤ VCC < 4.5V IOL = +13mA 2.7V ≤ VCC < 5.5V 0.4 V IOL = +3mA VCC = 2.7V 0 0.25 V IOL = +25mA Page 42 of 75 CY966B0 Series Parameter Symbol Pin Name Conditions Min Value Typ Max Unit Pnn_m VSS < VI < VCC AVSS, AVRL < VI < AVCC, AVRH -1 - +1 A P08_m, P09_m, P10_m VSS < VI < VCC AVSS, AVRL < VI < AVCC, AVRH -3 - +3 A Σ|IILCD| All SEG/ COM pin VCC = 5.0V - 0.5 10 A Internal LCD divide resistance RLCD Between V3 and V2, V2 and V1, V1 and V0 VCC = 5.0V 6.25 12.5 25 k Pull-up resistance value RPU Pnn_m VCC = 5.0V ±10% 25 50 100 k Other than C, Vcc, Vss, AVcc, AVss, AVRH, AVRL, P08_m, P09_m, P10_m - - 5 15 pF P08_m, P09_m, P10_m - - 15 30 pF Input leak current Total LCD leak current Input capacitance IIL CIN Remarks Single port pin except high current output I/O Maximum leakage current of all LCD pins *: In the case of high current outputs, set "1" to the bit in the Port High Drive Register. Document Number: 002-04721 Rev. *C Page 43 of 75 CY966B0 Series 14.4 AC Characteristics 14.4.1 Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Input frequency Pin Name Symbol fC fFCI X0, X1 Value Typ Min Max Unit 4 - 8 MHz - - 8 MHz 4 - 8 MHz - - 8 MHz 4 - 8 MHz X0 Input clock cycle tCYLH - 125 - - ns Input clock pulse width PWH, PWL - 55 - - ns Document Number: 002-04721 Rev. *C Remarks When using a crystal oscillator, PLL off When using an opposite phase external clock, PLL off When using a crystal oscillator or opposite phase external clock, PLL on When using a single phase external clock in “Fast Clock Input mode”, PLL off When using a single phase external clock in “Fast Clock Input mode”, PLL on Page 44 of 75 CY966B0 Series 14.4.2 Sub Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Pin Name Symbol fCL Value Conditions Min Typ Max Unit - - 32.768 - kHz - - - 100 kHz X0A - - - 50 kHz X0A, X1A Input clock cycle tCYLL - - 10 - - s Input clock pulse width - - PWH/tCYLL, PWL/tCYLL 30 - 70 % Document Number: 002-04721 Rev. *C Remarks When using an oscillation circuit When using an opposite phase external clock When using a single phase external clock Page 45 of 75 CY966B0 Series 14.4.3 Built-in RC Oscillation Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Clock frequency RC clock stabilization time 14.4.4 Value Symbol Min Typ Unit Max 50 100 200 kHz 1 2 4 MHz 80 160 320 s 64 128 256 s Remarks When using slow frequency of RC oscillator When using fast frequency of RC oscillator When using slow frequency of RC oscillator (16 RC clock cycles) When using fast frequency of RC oscillator (256 RC clock cycles) fRC tRCSTAB Internal Clock Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Value Symbol Min Max Unit Internal System clock frequency (CLKS1 and CLKS2) fCLKS1, fCLKS2 - 54 MHz Internal CPU clock frequency (CLKB), Internal peripheral clock frequency (CLKP1) fCLKB, fCLKP1 - 32 MHz Internal peripheral clock frequency (CLKP2) fCLKP2 - 32 MHz Document Number: 002-04721 Rev. *C Page 46 of 75 CY966B0 Series 14.4.5 Operating Conditions of PLL (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time tLOCK 1 - 4 ms PLL input clock frequency fPLLI 4 - 8 MHz PLL oscillation clock frequency fCLKVCO 56 - 108 MHz Permitted VCO output frequency of PLL (CLKVCO) PLL phase jitter tPSKEW -5 - +5 ns For CLKMC (PLL input clock) ≥ 4MHz 14.4.6 For CLKMC = 4MHz Reset Input (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Value Pin Name Min Reset input time tRSTL 10 - s 1 - s RSTX Rejection of reset input time Unit Max tRSTL RSTX 0.2VCC Document Number: 002-04721 Rev. *C 0.2VCC Page 47 of 75 CY966B0 Series 14.4.7 Power-on Reset Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Power on rise time Power off time Symbol tR tOFF Document Number: 002-04721 Rev. *C Pin Name Vcc Vcc Value Min 0.05 1 Typ - Unit Max 30 - ms ms Page 48 of 75 CY966B0 Series 14.4.8 USART Timing Serial clock cycle time Symbo l tSCYC SCK   SOT delay time tSLOVI SOT  SCK  delay time tOVSHI SIN SCK  setup time tIVSHI SCK  SIN hold time tSHIXI Serial clock "L" pulse width tSLSH Serial clock "H" pulse width tSHSL SCK   SOT delay time tSLOVE SIN  SCK setup time tIVSHE SCK SIN hold time tSHIXE SCK fall time SCK rise time tF tR Parameter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C, CL=50pF) 4.5V  VCC 5.5V 2.7V  VCC  4.5V Pin Unit Name Conditions Min Max Min Max SCKn 4tCLKP1 4tCLKP1 ns SCKn , - 20 + 20 - 30 + 30 ns SOTn SCKn NtCLKP1 NtCLKP1 , ns Internal shift – 20* – 30* SOTn clock mode SCKn tCLKP1 tCLKP1 , ns + 45 + 55 SINn SCKn , 0 0 ns SINn tCLKP1 tCLKP1 SCKn ns + 10 + 10 tCLKP1 tCLKP1 SCKn ns + 10 + 10 SCKn 2tCLKP1 2tCLKP1 , ns + 45 + 55 SOTn External SCKn shift tCLKP1/2 tCLKP1/2 , clock mode ns + 10 + 10 SINn SCKn tCLKP1 tCLKP1 , ns + 10 + 10 SINn SCKn 20 20 ns SCKn 20 20 ns Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “CY96600 series HARDWARE MANUAL”. • tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns • These characteristics only guarantee the same relocate port number. For example, the combination of SCKn and SOTn_R is not guaranteed. *: Parameter N depends on tSCYC and can be calculated as follows: • If tSCYC = 2  k  tCLKP1, then N = k, where k is an integer > 2 • If tSCYC = (2  k + 1) tCLKP1, then N = k + 1, where k is an integer > 1 Document Number: 002-04721 Rev. *C Page 49 of 75 CY966B0 Series tSCYC N 4  tCLKP1 2 5 3 tCLKP1, 6 tCLKP1 7  tCLKP1, 8  tCLKP1 4 ... ... tSCYC VOH SCK VOL VOL tOVSHI tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Internal shift clock mode SCK tSHSL tSLSH VIH VIH VIL tF VIL VIH tR tSLOVE SOT VOH VOL SIN tIVSHE VIH VIL tSHIXE VIH VIL External shift clock mode Document Number: 002-04721 Rev. *C Page 50 of 75 CY966B0 Series 14.4.9 External Input Timing Parameter Symbol Pin Name Pnn_m Input pulse width tINH, tINL (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Unit Remarks Min Max General Purpose I/O ADTG A/D Converter trigger input TINn TTGn FRCKn, FRCKn_R INn, INn_R Reload Timer PPG trigger input Free-Running Timer input clock Input Capture 2tCLKP1 +200 (tCLKP1= 1/fCLKP1)* - AINn, BINn, ZINn INTn, INTn_R 200 NMI *: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode. tINH External input timing VIH ns Quadrature Position/Revolution Counter External Interrupt Non-Maskable Interrupt tINL VIH VIL Document Number: 002-04721 Rev. *C ns VIL Page 51 of 75 CY966B0 Series 14.4.10 I2C Timing Parameter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) High-Speed Typical Mode Mode*4 Conditions Unit Min Max Min Max 0 100 0 400 kHz Symbol SCL clock frequency (Repeated) START condition hold time SDA   SCL  SCL clock "L" width SCL clock "H" width (Repeated) START condition setup time SCL  SDA  Data hold time SCL   SDA   Data setup time SDA    SCL  STOP condition setup time SCL   SDA  Bus free time between "STOP condition" and "START condition" Pulse width of spikes which will be suppressed by input noise filter fSCL tHDSTA 4.0 - 0.6 - s tLOW tHIGH 4.7 4.0 - 1.3 0.6 - s s 4.7 - 0.6 - s 0 3.45*2 0 0.9*3 s tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - s tBUS 4.7 - 1.3 - s 0 (1-1.5) tCLKP1*5 0 (1-1.5) tCLKP1*5 ns tSUSTA CL = 50pF, R = (Vp/IOL)*1 tHDDAT tSP - *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal. *3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250ns". *4: For use at over 100 kHz, set the peripheral clock1 (CLKP1) to at least 6MHz. *5: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time. SDA tSUDAT tSUSTA tBUS tLOW SCL tHDSTA Document Number: 002-04721 Rev. *C tHDDAT tHIGH tHDSTA tSP tSUSTO Page 52 of 75 CY966B0 Series 14.5 A/D Converter 14.5.1 Electrical Characteristics for the A/D Converter Resolution - - - (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Unit Remarks Typ Max 10 bit Total error - - - 3.0 - + 3.0 LSB Nonlinearity error - - - 2.5 - + 2.5 LSB - - - 1.9 - + 1.9 LSB VOT ANn Typ - 20 Typ + 20 mV VFST ANn Typ - 20 Typ + 20 mV Compare time* - - Sampling time* - - 5.0 8.0 3.1 s s s s mA Parameter Differential Nonlinearity error Zero transition voltage Full scale transition voltage Power supply current Reference power supply current (between AVRH and AVRL) Analog input capacity Analog impedance Analog port input current (during conversion) Analog input voltage Reference voltage range Variation between channels Pin Name Symbol IA IAH AVCC IR Min 1.0 2.2 0.5 1.2 - AVRL + 0.5LSB AVRH - 1.5LSB 2.0 - - 3.3 A - 520 810 A A/D Converter active - - 1.0 A A/D Converter not operated - - 16.0 pF Normal outputs - - 17.8 pF High current outputs - - 2050 3600   4.5V ≤ AVCC ≤ 5.5V 2.7V ≤ AVCC < 4.5V - 0.3 - + 0.3 A - 3.0 - + 3.0 A AVRH IRH CVIN AN2 to 4, 6 to 8, 10 to 12, 14, 15 AN16 to 31 RVIN ANn IAIN AN2 to 4, 6 to 8, 10 to 12, 14, 15 AN16 to 31 VAIN ANn AVRL - AVRH V - AVRH AVCC - 0.1 - AVCC V - AVRL AVSS - AVSS + 0.1 V - ANn - - 4.0 LSB 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V A/D Converter active A/D Converter not operated AVSS , AVRL VAIN  AVCC, AVRH *: Time for each channel. Document Number: 002-04721 Rev. *C Page 53 of 75 CY966B0 Series 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time (Tsamp) depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVCC voltage level. The following replacement model can be used for the calculation: MCU Rext Analog input RVIN Source Comparator Cext CVIN Sampling switch (During sampling:ON) Rext: External driving impedance Cext: Capacitance of PCB at A/D converter input CVIN: Analog input capacity (I/O, analog switch and ADC are contained) RVIN: Analog input impedance (I/O, analog switch and ADC are contained) The following approximation formula for the replacement model above can be used: Tsamp = 7.62  (Rext  Cext + (Rext + RVIN)  CVIN) • Do not select a sampling time below the absolute minimum permitted value. (0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V) • If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin. • A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor. • The accuracy gets worse as |AVRH - AVRL| becomes smaller. Document Number: 002-04721 Rev. *C Page 54 of 75 CY966B0 Series 14.5.3 Definition of A/D Converter Terms • Resolution • Nonlinearity error • • • • : Analog variation that is recognized by an A/D converter. : Deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→ 0b1111111111). Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the output code by 1LSB. Total error : Difference between the actual value and the theoretical value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Zero transition voltage : Input voltage which results in the minimum conversion value. Full scale transition voltage: Input voltage which results in the maximum conversion value. Nonlinearity error of digital output N = Differential nonlinearity error of digital output N = : : : : V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VOT 1022 1LSB = N VOT VFST VNT VNT - {1LSB  (N - 1) + VOT} 1LSB A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0x3FE to 0x3FF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-04721 Rev. *C Page 55 of 75 CY966B0 Series 1LSB (Ideal value) = Total error of digital output N = AVRH - AVRL 1024 [V] VNT - {1LSB  (N - 1) + 0.5LSB} 1LSB N : A/D converter digital output value. VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN. VOT (Ideal value) = AVRL + 0.5LSB[V] VFST (Ideal value) = AVRH - 1.5LSB[V] Document Number: 002-04721 Rev. *C Page 56 of 75 CY966B0 Series 14.6 High Current Output Slew Rate Parameter Output rise/fall time Symbol tR20, tF20 Pin Name Conditions P08_m, P09_m, P10_m Outputs driving strength set to "20mA" (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Unit Remarks Min Typ Max 15 - 75 Voltage ns CL=85pF VH=VOL20+0.9 × (V OH20-VOL20) VL=VOL20+0.1 × (V OH20-VOL20) VH VH VL VL tR20 tF20 Time Document Number: 002-04721 Rev. *C Page 57 of 75 CY966B0 Series 14.7 Low Voltage Detection Function Characteristics Detected voltage*1 VDL0 VDL1 VDL2 VDL3 VDL4 VDL5 VDL6 (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Conditions Unit Min Typ Max CILCR:LVL = 0000B 2.70 2.90 3.10 V CILCR:LVL = 0001B 2.79 3.00 3.21 V CILCR:LVL = 0010B 2.98 3.20 3.42 V CILCR:LVL = 0011B 3.26 3.50 3.74 V CILCR:LVL = 0100B 3.45 3.70 3.95 V CILCR:LVL = 0111B 3.73 4.00 4.27 V CILCR:LVL = 1001B 3.91 4.20 4.49 V Power supply voltage change rate*2 dV/dt - - 0.004 - + 0.004 V/s Hysteresis width VHYS CILCR:LVHYS=0 - - 50 mV CILCR:LVHYS=1 80 100 120 mV Stabilization time TLVDSTAB - - - 75 s Detection delay time td - - - 30 s Parameter Symbol *1: If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a possibility that the low voltage detection will occur or stop after the power supply voltage passes the detection range. *2: In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation of the power supply voltage within the limits of the change ration of power supply voltage. Document Number: 002-04721 Rev. *C Page 58 of 75 CY966B0 Series Voltage Vcc dV Detected Voltage dt VDLX max VDLX min Time RCR:LVDE ···Low voltage detection function enable Document Number: 002-04721 Rev. *C Low voltage detection function disable Stabilization time TLVDSTAB Low voltage detection function enable··· Page 59 of 75 CY966B0 Series 14.8 Flash Memory Write/Erase Characteristics Parameter Sector erase time Word (16-bit) write time Conditions (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Unit Remarks Min Typ Max Large Sector TA ≤ + 105°C - 1.6 7.5 s Small Sector - - 0.4 2.1 s Security Sector - - 0.31 1.65 s Large Sector TA ≤ + 105°C - 25 400 s Small Sector - - 25 400 s TA ≤ + 105°C - 8.31 40.05 s Chip erase time Includes write time prior to internal erase. Not including system-level overhead time. Includes write time prior to internal erase. Note: While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system where the external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function. To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/s to +0.004V/s) after the external power falls below the detection voltage (VDLX)*1. Write/Erase cycles and data hold time Write/Erase Cycles (Cycle) 1,000 10,000 100,000 Data Hold Time (Year) 20 *2 10 *2 5 *2 *1: See "14.7 Low Voltage Detection Function Characteristics". *2: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85C). Document Number: 002-04721 Rev. *C Page 60 of 75 CY966B0 Series 15. Example Characteristics This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.  CY96F6B6 Run Mode (VCC = 5.5V) 100.00 PLL clock (32MHz) 10.00 ICC [mA] Main osc. (4MHz) 1.00 RC clock (2MHz) RC clock (100kHz) 0.10 Sub osc. (32kHz) 0.01 -50 0 50 100 150 TA [ºC] Sleep Mode (VCC = 5.5V) 100.000 PLL clock (32MHz) 10.000 ICC [mA] Main osc. (4MHz) 1.000 RC clock (2MHz) 0.100 RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04721 Rev. *C Page 61 of 75 CY966B0 Series  CY96F6B6 Timer Mode (VCC = 5.5V) 10.000 PLL clock (32MHz) ICC [mA] 1.000 Main osc. (4MHz) 0.100 RC clock (2MHz) RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Stop Mode (VCC = 5.5V) 1.000 ICC [mA] 0.100 0.010 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04721 Rev. *C Page 62 of 75 CY966B0 Series  Used setting Selected Source Clock Mode Run mode Sleep mode PLL CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz Main osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz RC clock fast CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz RC clock slow CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz Sub osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz PLL CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKMC = 4MHz, CLKPLL = 32MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 4MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 2MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 100kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode CLKMC = 32 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode (All clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode Main osc. RC clock fast RC clock slow Sub osc. Timer mode PLL Main osc. RC clock fast RC clock slow Sub osc. Stop mode Clock/Regulator and FLASH Settings stopped Document Number: 002-04721 Rev. *C Page 63 of 75 CY966B0 Series 16. Ordering Information MCU with CAN Controller Part Number Flash Memory Flash A CY96F6B5RBPMC-GS-UJE1 (160.5KB) CY96F6B6RBPMC-GS-UJE1 Flash A (288.5KB) CY96F6B6RBPMC-GS-UJE2 *: For details about package, see “Package Dimension ". Document Number: 002-04721 Rev. *C Package* 100-pin plastic LQFP (LQI100) 100-pin plastic LQFP (LQI100) Page 64 of 75 CY966B0 Series 17. Package Dimension D D1 75 4 D 5 7 51 D1 51 50 76 4 5 7 75 50 76 E1 E 5 4 7 E1 E 5 4 7 3 6 26 100 1 26 25 1 25 2 5 7 e 100 BOTTOM VIEW 0.1 0 C A-B D 3 0.2 0 C A-B D b TOP VIEW 8 0.0 8 C A-B D 2 A 9 A SEATIN G PLA N E A' 0.25 L1 0.0 8 C c A1 b 10 SECTIO N A-A ' L SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. 0.05 0.15 1.70 A A1 DETAIL A b 0.15 0.27 c 0.09 0.20 D 16.00 BSC D1 14.00 BSC e 0.50 BSC E 16.00 BSC E1 14.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 NOTES : 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE M OLD PARTING LINE COINCIDENT W ITH W HERE THE LEAD EXITS THE BODY. 3. DATUM S A-B AND D TO BE DETERM INED AT DATUM PLANE H. 4. TO BE DETERM INED AT SEATING PLANE C. 5. DIM ENSIONS D1 AND E1 DO NOT INCLUDE M OLD PROTRUSION. ALLOW ABLEPROTRUSION IS 0.25m m PRE SIDE. DIM ENSIONS D1 AND E1 INCLUDE M OLD M ISM ATCH AND ARE DETERM INED AT DATUM PLANE H. 6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT M UST BE LOCATED W ITHIN THE ZONE INDICATED. 7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOW ER BODY SECTIONS. DIM ENSIONS D1 AND E1 ARE DETERM INED AT THE LARGEST FEATURE OF THE BODY EXCLUSIVE OF M OLD FLASH AND GATE BURRS. BUT INCLUDING ANY M ISM ATCH BETW EEN THE UPPER AND LOW ER SECTIONS OF THE M OLDER BODY. 8. DIM ENSION b DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAM BAR PROTRUSION (S) SHALL NOT CAUSE THE LEAD W IDTH TO EXCEED b M AXIM UM BY M ORE THAN 0.08m m . DAM BAR CANNOT BE LOCATED ON THE LOW ER RADIUS OR THE LEAD FOOT. 9. THESE DIM ENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETW EEN 0.10m m AND 0.25m m FROM THE LEAD TIP. 10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOW EST POINT OF THE PACKAGE BODY. 002-11500 *A PACKAGE OUTLINE, 100 LEAD LQFP 14.0X14.0X1.7 M M LQI100 REV*A Document Number: 002-04721 Rev. *C Page 65 of 75 CY966B0 Series 18. Major Changes Spansion Publication Number: MB966B0-DS704-00013 Page Section Revision 1.0 Features 2 4 5 Product Lineup 6 Block Diagram 8 Pin Assignment 9 Pin Description 10 Document Number: 002-04721 Rev. *C Change Results PRELIMINARY → Data sheet Changed the description of “System clock” Up to 16 MHz external clock for devices with fast clock input feature → Up to 8 MHz external clock for devices with fast clock input feature Changed the description of “LCD Controller” On-chip drivers for internal divider resistors or external divider resistors → Internal divider resistors or external divider resistors Added “Sound Generator” Changed the description of “External Interrupts” Interrupt mask and pending bit per channel → Interrupt mask bit per channel Added the description of “I/O Ports” “Some pins offer high current output capability for LED driving.” Changed the description of “Built-in On Chip Debugger” - Event sequencer: 2 levels → - Event sequencer: 2 levels + reset Added the Product Changed the Remark of RLT RLT 0/1/2/3/6 Only RLT6 can be used as PPG clock source → RLT 0 to 3/6 Added the Feature of Sound Generator Added the block of Sound Generator Deleted the block of RLT6 from PPG block Changed the RLT block 4ch → 0/1/2/3/6 5ch Added the Pin Pin no.23, SGO1 Pin no.24, SGA1 Pin no.28, SGO1_R Pin no.29, SGA1_R Pin no.81, SGO0 Pin no.82, SGA0 Changed the Description of PPGn_B Programmable Pulse Generator n output (8bit) → Programmable Pulse Generator n output (16bit/8bit) Added the Pin SGAn SGAn_R SGOn SGOn_R Page 66 of 75 CY966B0 Series Page Section Pin Circuit Type 12 13 14 I/O Circuit Type 16 17 20 21 Memory Map 22 User Rom Memory Map For Flash Devices 24 Interrupt Vector Table 26 Interrupt Vector Table 27 Document Number: 002-04721 Rev. *C Change Results Added the Pin name Pin no.23, SGO1 Pin no.24, SGA1 Pin no.28, SGO1_R Pin no.29, SGA1_R Changed the I/O circuit type Pin no.30 to 34, 37 to 40 K→V Changed the I/O circuit type Pin no.41 to 43, 47, 49 K→V Pin no.46, 48 I→W Added the Pin name Pin no.81, SGO0 Pin no.82, SGA0 Changed the figure of type B Changed the Remarks of type B (CMOS hysteresis input with input shutdown function, IOL = 4mA, IOH = -4mA, Programmable pull-up resister) → (CMOS level output (IOL = 4mA, IOH = -4mA), Automotive input with input shutdown function and programmable pull-up resistor) Changed the figure of type G Added the Type V Added the Type W Changed the START addresses of Boot-ROM 0F:E000H → 0F:C000H Changed the annotation Others (from DF:0200H to DF:1FFFH) are all ROM Mirror area for SAS-512B. → Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B. Changed the Description of CALLV0 to CALLV7 Reserved → CALLV instruction Changed the Description of RESET Reserved → Reset vector Changed the Description of INT9 Reserved → INT9 instruction Changed the Description of EXCEPTION Reserved → Undefined instruction execution Changed the Vector name of Vector number 64 PPGRLT → RLT6 Page 67 of 75 CY966B0 Series Page Section 28 29 30 to 33 Handling Precautions Handling Devices 35 36 Electrical Characteristics 1. Absolute Maximum Ratings 37 38 2. Recommended Operating Conditions 39 40 3. DC Characteristics (1) Current Rating Document Number: 002-04721 Rev. *C Change Results Changed the Description of Vector number 64 Reload Timer 6 can be used as PPG clock source → Reload Timer 6 Added Vector name to Vector number 95 SG0 Added Vector name to Vector number 121 SG1 Added a section Added the description to “3. External clock usage” (3) Opposite phase external clock Changed the description in “7. Turn on sequence of power supply to A/D converter and analog inputs” In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). → In this case, AVRH must not exceed AVCC. Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). Added the description “12. Mode Pin (MD)” Added Symbols of High current port Changed the annotation *3 Input/Output voltages of standard ports depend on VCC. → Input/Output voltages of general I/O ports depend on VCC. Changed the annotation *4 Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). → Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset. Added the annotation *4 The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current (4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6.0V. Added the Value and Remarks to “Power supply voltage” Min: 2.0V Typ: Max: 5.5V Remarks: Maintains RAM data in stop mode Changed the Value of “Smoothing capacitor at C pin” Typ: 1.0F → 1.0F to 3.9F Max: 1.5F → 4.7F Changed the Remarks of “Smoothing capacitor at C pin” Deleted “(Target value)” Added “3.9F (Allowance within ± 20%)” Deleted “(Target value)” from Remarks Added the Symbol to “Power supply current in Run modes” ICCRCH, ICCRCL Page 68 of 75 CY966B0 Series Page Section 41 42 3. DC Characteristics (1) Current Rating 42 43 Document Number: 002-04721 Rev. *C Change Results Changed the Conditions of ICCPLL, ICCMAIN, ICCSUB in “Power supply current in Run modes” “Flash 0 wait” is added Changed the Value of “Power supply current in Run modes” ICCPLL TYP:28.5mA→ 28mA (TA = +25°C) ICCMAIN TYP:5mA→ 3.5mA (TA = +25°C) Max: 10mA → 8mA (TA = +105°C) Max: 11.5mA → 9.5mA (TA = +125°C) ICCSUB TYP:0.5mA→ 0.1mA (TA = +25°C) Max: 6mA → 3.3mA (TA = +105°C) Max: 7.5mA → 4.8mA (TA = +125°C) Added the Symbol to “Power supply current in Sleep modes” ICCSRCH, ICCSRCL Changed the Conditions of ICCSMAIN in “Power supply current in Sleep modes” “SMCR:LPMSS=0” is added Changed the Value of “Power supply current in Sleep modes” ICCSPLL Typ: 10mA → 9.5mA (TA = +25°C) ICCSMAIN Typ: 3mA → 1.1mA (TA = +25°C) Max: 8mA → 4.7mA (TA = +105°C) Max: 9.5mA → 6.2mA (TA = +125°C) ICCSSUB Typ: 0.3mA → 0.04mA (TA = +25°C) Max: 4.5mA → 2.7mA (TA = +105°C) Max: 6mA → 4.2mA (TA = +125°C) Added the Symbol to “Power supply current in Timer modes” ICCTPLL Changed the Conditions of ICCTMAIN, ICCTRCH in “Power supply current in Timer modes” “SMCR:LPMSS=0” is added Changed the Value of “Power supply current in Timer modes” ICCTMAIN Max: 335μA → 330μA (TA = +25°C) Max: 1320μA → 1200μA (TA = +105°C) Max: 2300μA → 2155μA (TA = +125°C) ICCTRCH Max: 245μA → 215μA (TA = +25°C) Max: 1230μA → 1110μA (TA = +105°C) Max: 2205μA → 2065μA (TA = +125°C) ICCTRCL Max: 105μA → 75μA (TA = +25°C) Max: 1030μA → 910μA (TA = +105°C) Max: 2005μA → 1870μA (TA = +125°C) ICCTSUB Max: 90μA → 65μA (TA = +25°C) Max: 1000μA → 885μA (TA = +105°C) Max: 1980μA → 1845μA (TA = +125°C) Changed the Value of “Power supply current in Stop mode” ICCH Max: 90μA → 60μA (TA = +25°C) Max: 1000μA → 880μA (TA = +105°C) Max: 1980μA → 1840μA (TA = +125°C) Added the Symbol ICCFLASHPD Page 69 of 75 CY966B0 Series Page 44 Section 3. DC Characteristics (2) Pin Characteristics 3. DC Characteristics (2) Pin Characteristics 45 Document Number: 002-04721 Rev. *C Change Results Changed the Value and condition of “Power supply current for active Low Voltage detector” ICCLVD Typ: 5μA, Max: 15μA, Remarks: nothing → Typ: 5μA, Max: -, Remarks: TA = +25°C Typ: -, Max: 12.5μA, Remarks: TA = +125°C Changed the condition of “Flash Write/Erase current” ICCFLASH Typ: 12.5mA, Max: 20mA, Remarks: nothing → Typ: 12.5mA, Max: -, Remarks: TA = +25°C Typ: -, Max: 20mA, Remarks: TA = +125°C Changed the annotation *2 The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. → When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not included. Added the Symbol for High Drive type VOH20, VOL20 Added the Symbol for DEBUG I/F pin VOLD Changed the Pin name of “Input capacitance” Other than Vcc, Vss, AVcc, AVss, AVRH, AVRL, P08_m, P09_m, P10_m → Other than C, Vcc, Vss, AVcc, AVss, AVRH, AVRL, P08_m, P09_m, P10_m Deleted the annotation “IOH and IOL are target value.” Added the annotation “In the case of high current outputs, set “1” to the bit in the Port High Drive Register.” Page 70 of 75 CY966B0 Series Page Section 4. AC Characteristics (1) Main Clock Input Characteristics 46 47 48 4. AC Characteristics (2) Sub Clock Input Characteristics 4. AC Characteristics (3) Built-in RC Oscillation Characteristics 4. AC Characteristics (5) Operating Conditions of PLL 49 4. AC Characteristics (6) Reset Input 4. AC Characteristics (8) USART Timing 51 52 54 55 56 4. AC Characteristics (10) I2C timing 5. A/D Converter (1) Electrical Characteristics for the A/D Converter 5. A/D Converter (2) Accuracy and Setting of the A/D Converter Sampling Time 5. A/D Converter (3) Definition of A/D Converter Terms 57 Document Number: 002-04721 Rev. *C Change Results Changed MAX frequency for fFCI in all conditions 16 → 8 Changed MIN frequency for tCYLH 62.5 → 125 Changed MIN, MAX and Unit for PWH, PWL MIN: 30 → 55 MAX: 70 → Unit: % → ns Added the figure (tCYLH) when using the external clock Added the figure (tCYLL) when using the crystal oscillator clock Added “RC clock stabilization time” Changed the Value of “PLL input clock frequency” Max: 16MHz → 8MHz Changed the Symbol of “PLL oscillation clock frequency” fPLLO → fCLKVCO Added Remarks to “PLL oscillation clock frequency” Added “ PLL phase jitter” and the figure Added the figure for reset input time (tRSTL) Changed the condition (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) → (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C, CL=50pF) Changed the HARDWARE MANUAL “MB966B0 series HARDWARE MANUAL” → “MB96600 series HARDWARE MANUAL” Changed the figure for “Internal shift clock mode” Added parameter, “Noise filter” and an annotation *5 for it Added tSP to the figure Added “Analog impedance” Added “Variation between channels” Added the annotation Deleted the unit “[Min]” from approximation formula of Sampling time Changed the Description and the figure “Linearity” → “Nonlinearity” “Differential linearity error” → “Differential nonlinearity error” Changed the Description Linearity error: Deviation of the line between the zero-transition point (0b0000000000←→0b0000000001) and the full-scale transition point (0b1111111110←→0b1111111111) from the actual conversion characteristics. → Nonlinearity error: Deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→ 0b1111111111). Page 71 of 75 CY966B0 Series Page 59 Section 6. High Current Output Slew Rate 7. Low Voltage Detection Function Characteristics 60 61 8. Flash Memory Write/Erase Characteristics 62 63 to 65 Example Characteristics Ordering Information 66 Change Results Added the Description “Zero transition voltage” “Full scale transition voltage” Added the item of “6. High Current Output Slew Rate” Added the Value of “ Power supply voltage change rate” Max: +0.004 V/s Added “Hysteresis width” (VHYS) Added “Stabilization time” (TLVDSTAB) Added “Detection delay time” (td) Deleted the Remarks Added the annotation *1, *2 Added the figure for “Hysteresis width” Added the figure for “Stabilization time” Changed the Value of “Sector erase time” Added “Security Sector” to “Sector erase time” Changed the Parameter “Half word (16 bit) write time” → “Word (16-bit) write time” Changed the Value of “Chip erase time” Changed the Remarks of “Sector erase time” Excludes write time prior to internal erase → Includes write time prior to internal erase Added the Note and annotation *1 Deleted “(targeted value)” from title “ Write/Erase cycles and data hold time” Added a section Changed part number MCU with CAN controller CY96F6B6RAPMC-GSE1* → CY96F6B6RBPMC-GSE1 CY96F6B6RAPMC-GSE2* → CY96F6B6RBPMC-GSE2 Added part number MCU with CAN controller CY96F6B5RBPMC-GSE1 CY96F6B5RBPMC-GSE2 MCU without CAN controller CY96F6B5ABPMC-GSE1 CY96F6B5ABPMC-GSE2 Revision 1.1 Company name and layout design change Rev.*B Marketing Part Numbers changed from an MB prefix to a CY prefix. 6, 8, 1. Product Lineup Package description modified to JEDEC description. 64, 65 3. Pin Assignment FPT-100P-M20 → LQI100 16. Ordering Information 17. Package Dimension Document Number: 002-04721 Rev. *C Page 72 of 75 CY966B0 Series Page 64 Section 16. Ordering Information Change Results Revised Marketing Part Numbers as follows: Before) MCU with CAN controller MB96F6B5RBPMC-GSE1 MB96F6B5RBPMC-GSE2 MB96F6B6RBPMC-GSE1 MB96F6B6RBPMC-GSE2 MCU without CAN controller MB96F6B5ABPMC-GSE1 MB96F6B5ABPMC-GSE2 After) MCU with CAN controller CY96F6B5RBPMC-GS-UJE1 CY96F6B6RBPMC-GS-UJE1 CY96F6B6RBPMC-GS-UJE2 NOTE: Please see “Document History” about later revised information. Document Number: 002-04721 Rev. *C Page 73 of 75 CY966B0 Series Document History Document Title: CY966B0 Series F2MC-16FX 16-Bit Microcontroller Document Number: 002-04721 Revision ECN Orig. of Change Submission Date ** - KSUN 01/31/2014 Migrated to Cypress and assigned document number 002-04721 No change to document contents or format. *A 5126730 KSUN 03/03/2016 Updated to Cypress template. *B 6003420 MIYH 12/25/2017 Revised the following items: Marketing Part Numbers changed from an MB prefix to a CY prefix. 1. Product Lineup 3. Pin Assignment 16. Ordering Information 17. Package Dimension For details, please see 18. Major Changes. Description of Change Updated to new template. Completing Sunset Review. *C 6578271 KSUN Document Number: 002-04721 Rev. *C 05/21/2019 Updated to new template. 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You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04721 Rev. *C Revised May 21, 2019 Page 75 of 75