MB9AF111KPMC-G-JNE2

MB9A110K Series 32-bit ARMTM CortexTM-M3 based Microcontroller MB9AF111K, MB9AF112K Data Sheet (Full Production) Publication Number MB9AF112K-DS706-00030 CONFIDENTIAL Revision 1.1 Issue Date January 31, 2014 D a t a S h e e t 2 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 MB9A110K Series 32-bit ARMTM CortexTM-M3 based Microcontroller MB9AF111K, MB9AF112K Data Sheet (Full Production)  DESCRIPTION The MB9A110K Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and low cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE5 product categories in "FM3 Famliy PERIPHERAL MANUAL". Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries. Publication Number MB9AF112K-DS706-00030 Revision 1.1 Issue Date January 31, 2014 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. CONFIDENTIAL D a t a S h e e t  FEATURES  32-bit ARM Cortex-M3 Core  Processor version: r2p1  Up to 40MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC) : 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick) : System timer for OS task management  On-chip Memories [Flash memory] This Series are based on two independent on-chip Flash memories.  MainFlash  Up to 128Kbyte  Read cycle : 0 wait-cycle  Security function for code protection  WorkFlash  32Kbyte  Read cycle : 0 wait-cycle  Security function is shared with code protection [SRAM] This Series contain a total of up to 16Kbyte on-chip SRAM memories. This is composed of two independent SRAM (SRAM0, SRAM1) . SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0 : 8 Kbyte  SRAM1 : 8 Kbyte 2 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  Multi-function Serial Interface (Max 4channels)  2 channels with 16-steps × 9-bits FIFO (ch.0, ch.1), 2 channels without FIFO (ch.3, ch.5)  Operation mode is selectable from the followings for each channel. (In ch.5, only UART and LIN are available.)  UART  CSIO  LIN  I 2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)  Various error detect functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detect function available [LIN]  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generate (can be changed 13 to 16-bit length)  LIN break delimiter generate (can be changed 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors) [I2C] Standard mode (Max 100kbps) / High-speed mode (Max 400kbps) supported  DMA Controller (4channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.        8 independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32-bit (4Gbyte) Transfer mode: Block transfer/Burst transfer/Demand transfer Transfer data type: byte/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to 65536  A/D Converter (Max 8channels) [12-bit A/D Converter]  Successive Approximation Register type  Built-in 2unit  Conversion time: 1.0μs@5V  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 3 D a t a S h e e t  Base Timer (Max 8channels) Operation mode is selectable from the followings for each channel.     16-bit PWM timer 16-bit PPG timer 16/32-bit reload timer 16/32-bit PWC timer  General Purpose I/O Port This series can use its pins as General Purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.      Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up 36 fast General Purpose I/O Ports Some pin is 5V tolerant I/O. See "PIN DESCRIPTION" to confirm the corresponding pins.  Multi-function Timer The Multi-function timer is composed of the following blocks.       16-bit free-run timer × 3ch. Input capture × 4ch. Output compare × 6ch. A/D activating compare × 3ch. Waveform generator × 3ch. 16-bit PPG timer × 3ch. The following function can be used to achieve the motor control.       PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function  Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.  Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. 4 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  Quadrature Position/Revolution Counter (QPRC) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.     The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers  Dual Timer (32/16-bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot  Watch Counter The Watch counter is used for wake up from Low Power Consumption mode. Interval timer: up to 64s (Max) @ Sub Clock : 32.768kHz  External Interrupt Controller Unit  Up to 6 external interrupt input pin  Include one non-maskable interrupt (NMI)  Watchdog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, ”Hardware" watchdog is active in any power saving mode except RTC and STOP and Deep stand-by RTC and Deep stand-by STOP.  CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 5 D a t a S h e e t  Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.      Main Clock : 4MHz to 48MHz Sub Clock : 32.768kHz High-speed internal CR Clock : 4MHz Low-speed internal CR Clock : 100kHz Main PLL Clock [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low-voltage detector reset  Clock supervisor reset  Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  External OSC clock failure (clock stop) is detected, reset is asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted.  Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation  Low Power Consumption Mode Six Low Power Consumption modes supported.       SLEEP TIMER RTC STOP Deep stand-by RTC Deep stand-by STOP  Debug Serial Wire JTAG Debug Port (SWJ-DP)  Power Supply Wide range voltage: VCC = 2.7V to 5.5V 6 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  PRODUCT LINEUP  Memory size Product name MainFlash On-chip Flash WorkFlash SRAM0 On-chip SRAM1 SRAM Total MB9AF111K 64Kbyte 32Kbyte 8Kbyte 8Kbyte 16Kbyte MB9AF112K 128Kbyte 32Kbyte 8Kbyte 8Kbyte 16Kbyte  Function MB9AF111K MB9AF112K Product name Pin count CPU Freq. Power supply voltage range DMAC Multi-function Serial Interface (UART/CSIO/LIN/I2C) 48/52 Cortex-M3 40MHz 2.7V to 5.5V 4ch. (Max) 4ch. (Max) with 16-steps × 9-bits FIFO : ch.0, ch.1 without FIFO : ch.3, ch.5 (In ch.5, only UART and LIN are available.) Base Timer 8ch. (Max) (PWC/ Reload timer/PWM/PPG) A/D activation 3ch. compare Input 4ch. capture Free-run MF3ch. 1 unit (Max) Timer timer Output 6ch. compare Waveform 3ch. generator PPG 3ch. QPRC 1ch. (Max) Dual Timer 1 unit Real-time clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 6pins (Max) + NMI × 1 General Purpose I/O ports 36pins (Max) 12-bit A/D converter 8ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. High-speed 4MHz (±2%) Internal OSC Low-speed 100kHz (Typ) Debug Function SWJ-DP Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the General I/O port according to your function use. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 7 D a t a S h e e t  PACKAGES Product name Package LQFP: FPT-48P-M49 (0.5mm pitch) QFN: LCC-48P-M73 (0.5mm pitch) LQFP: FPT-52P-M02 (0.65mm pitch) MB9AF111K MB9AF112K    : Supported Note : See "PACKAGE DIMENSIONS" for detailed information on each package. 8 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  PIN ASSIGNMENT  FPT-48P-M49 VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3 P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P21/SIN0_0/INT06_1/WKUP2 P50/INT00_0/AIN0_2/SIN3_1 2 35 P22/AN07/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 34 P23/AN06/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 33 AVSS P39/DTTI0X_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/IC03_2 P3C/RTO02_0/TIOA2_1 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1 VSS 12 25 P10/AN00 13 14 15 16 17 18 19 20 21 22 23 24 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 48 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 9 D a t a S h e e t  LCC-48P-M73 VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3 P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P21/SIN0_0/INT06_1/WKUP2 P50/INT00_0/AIN0_2/SIN3_1 2 35 P22/AN07/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 34 P23/AN06/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 33 AVSS P39/DTTI0X_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/IC03_2 P3C/RTO02_0/TIOA2_1 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1 VSS 12 25 P10/AN00 13 14 15 16 17 18 19 20 21 22 23 24 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 48 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 10 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  FPT-52P-M02 VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3 P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX NC 52 51 50 49 48 47 46 45 44 43 42 41 40 (TOP VIEW) VCC 1 39 P21/SIN0_0/INT06_1/WKUP2 P50/INT00_0/AIN0_2/SIN3_1 2 38 P22/AN07/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 37 P23/AN06/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 36 NC NC 5 35 AVSS P39/DTTI0X_0/ADTG_2 6 34 AVRH P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 7 33 AVCC P3B/RTO01_0/TIOA1_1 8 32 P15/AN05/SOT0_1/IC03_2 P3C/RTO02_0/TIOA2_1 9 31 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 10 30 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1 11 29 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 12 28 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1 VSS 13 27 P10/AN00 14 15 16 17 18 19 20 21 22 23 24 25 26 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 NC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 52 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 11 D a t a S h e e t  PIN DESCRIPTION The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-48 LQFP-52 QFN-48 1 1 2 2 3 3 4 4 - 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 12 CONFIDENTIAL Pin Name VCC P50 INT00_0 AIN0_2 SIN3_1 P51 INT01_0 BIN0_2 SOT3_1 P52 INT02_0 ZIN0_2 SCK3_1 NC P39 DTTI0X_0 ADTG_2 P3A RTO00_0 TIOA0_1 RTCCO_2 SUBOUT_2 P3B RTO01_0 TIOA1_1 P3C RTO02_0 TIOA2_1 P3D RTO03_0 TIOA3_1 P3E RTO04_0 TIOA4_1 P3F RTO05_0 TIOA5_1 VSS I/O circuit type Pin state type - I* H I* H I* H E I G I G I G I G I G I G I - MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Pin No LQFP-48 LQFP-52 QFN-48 13 14 14 15 15 16 16 17 17 18 18 19 19 20 - 21 20 22 21 23 22 24 23 25 24 26 25 27 26 28 27 29 28 30 29 31 January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL Pin Name C VCC P46 X0A P47 X1A INITX P49 TIOB0_0 P4A TIOB1_0 NC PE0 MD1 MD0 PE2 X0 PE3 X1 VSS P10 AN00 P11 AN01 SIN1_1 INT02_1 FRCK0_2 IC02_0 WKUP1 P12 AN02 SOT1_1 IC00_2 P13 AN03 SCK1_1 IC01_2 RTCCO_1 SUBOUT_1 P14 AN04 SIN0_1 INT03_1 IC02_2 I/O circuit type Pin state type - D M D N B C E I E I - C P J D A A A B - F K F F F K F K F L 13 D a t a S h e e t Pin No LQFP-48 LQFP-52 QFN-48 30 32 31 32 33 - 33 34 35 36 34 37 35 38 36 39 - 40 37 41 38 42 39 43 40 44 41 45 42 46 43 47 14 CONFIDENTIAL Pin Name P15 AN05 SOT0_1 IC03_2 AVCC AVRH AVSS NC P23 AN06 SCK0_0 TIOA7_1 P22 AN07 SOT0_0 TIOB7_1 P21 SIN0_0 INT06_1 WKUP2 NC P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 P61 SOT5_0 TIOB2_2 UHCONX DTTI0X_2 I/O circuit type Pin state type F K - F K F K E G E E E E E E E E E E E J E I MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Pin No LQFP-48 LQFP-52 QFN-48 44 48 45 46 47 48 *: 5V tolerant I/O 49 50 51 52 January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL Pin Name P60 SIN5_0 TIOA2_2 INT15_1 IC00_0 WKUP3 VCC P80 P81 VSS I/O circuit type Pin state type I* G H H O O - 15 D a t a S h e e t  SIGNAL DESCRIPTION The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Module Pin name ADC ADTG_2 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 TIOA0_1 TIOB0_0 TIOA1_1 TIOB1_0 TIOA2_1 TIOA2_2 TIOB2_2 A/D converter external trigger input pin Base timer ch.2 TIOB pin LQFP-48 QFN-48 5 25 26 27 28 29 30 34 35 6 18 7 19 8 44 43 TIOA3_1 Base timer ch.3 TIOA pin 9 10 TIOA4_1 Base timer ch.4 TIOA pin 10 11 TIOA5_1 Base timer ch.5 TIOA pin 11 12 TIOA7_1 TIOB7_1 SWCLK Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input/output pin Serial wire viewer output pin J-TAG test clock input pin J-TAG test data input pin J-TAG debug data output pin J-TAG test mode state input/output pin J-TAG test reset Input pin External interrupt request 00 input pin External interrupt request 01 input pin 34 35 38 37 38 42 40 44 41 38 39 41 40 37 2 3 4 26 29 36 44 42 45 42 43 45 44 41 2 3 4 28 31 39 48 46 Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 7 Debugger SWDIO External Interrupt 16 CONFIDENTIAL SWO TCK TDI TDO TMS TRSTX INT00_0 INT01_0 INT02_0 INT02_1 INT03_1 INT06_1 INT15_1 NMIX Function A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 06 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin LQFP-52 6 27 28 29 30 31 32 37 38 7 19 8 20 9 48 47 MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Pin No Module Pin name GPIO P00 P01 P02 P03 P04 P0F P10 P11 P12 P13 P14 P15 P21 P22 P23 P39 P3A P3B P3C P3D P3E P3F P46 P47 P49 P4A P50 P51 P52 P60 P61 P80 P81 PE0 PE2 PE3 Function General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL LQFP-48 QFN-48 37 38 39 40 41 42 25 26 27 28 29 30 36 35 34 5 6 7 8 9 10 11 15 16 18 19 2 3 4 44 43 46 47 20 22 23 LQFP-52 41 42 43 44 45 46 27 28 29 30 31 32 39 38 37 6 7 8 9 10 11 12 16 17 19 20 2 3 4 48 47 50 51 22 24 25 17 D a t a S h e e t Pin No. Module Pin name Multifunction Serial 0 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Multifunction Serial 1 SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) 18 CONFIDENTIAL Function Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation modes 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). LQFP-48 QFN-48 36 29 LQFP-52 39 31 35 38 30 32 34 37 26 28 27 29 28 30 MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Pin No. Module Multifunction Serial 3 Pin name SIN3_1 SOT3_1 (SDA3_1) SCK3_1 (SCL3_1) Multifunction Serial 5 SIN5_0 SOT5_0 January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL Function Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/LIN (operation modes 0, 1, 3). LQFP-48 QFN-48 LQFP-52 2 2 3 3 4 4 44 48 43 47 19 D a t a S h e e t Pin No Module Pin name Multifunction Timer 0 DTTI0X_0 DTTI0X_2 FRCK0_2 IC00_0 IC00_2 IC01_2 IC02_0 IC02_2 IC03_2 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) 20 CONFIDENTIAL Function LQFP-48 QFN-48 LQFP-52 Input signal controlling wave form generator outputs RTO00 to RTO05 of multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 5 6 43 47 26 28 16-bit input capture ch.0 input pin of multi-function timer 0. ICxx describes channel number. 44 27 28 26 29 30 48 29 30 28 31 32 6 7 7 8 8 9 9 10 10 11 11 12 Wave form generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Pin No Module Pin name Quadrature Position/ Revolution Counter 0 AIN0_2 Real-time clock RTCCO_0 Function LQFP-48 QFN-48 LQFP-52 QPRC ch.0 AIN input pin 2 2 BIN0_2 QPRC ch.0 BIN input pin 3 3 ZIN0_2 QPRC ch.0 ZIN input pin 4 4 42 46 28 30 6 42 7 46 28 30 6 7 RTCCO_1 0.5 seconds pulse output pin of Real-time clock pin RTCCO_2 SUBOUT_0 SUBOUT_1 Sub clock output pin SUBOUT_2 Low Power Consumption Mode WKUP0 Deep stand-by mode return signal input pin 0 42 46 WKUP1 Deep stand-by mode return signal input pin 1 26 28 36 39 44 48 WKUP2 WKUP3 January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL Deep stand-by mode return signal input pin 2 Deep stand-by mode return signal input pin 3 21 D a t a S h e e t Pin No Module RESET Pin name INITX Mode MD0 MD1 POWER GND CLOCK ADC POWER ADC GND C pin NC pin VCC VCC VCC VSS VSS VSS X0 X0A X1 X1A CROUT_1 LQFP-52 17 18 21 23 20 22 1 14 45 12 24 48 22 15 23 16 42 1 15 49 13 26 52 24 16 25 17 46 A/D converter analog power pin 31 33 AVRH A/D converter analog reference voltage input pin 32 34 AVSS A/D converter GND pin 33 35 Power stabilization capacity pin 13 14 - 5 - 21 - 36 - 40 C NC NC NC CONFIDENTIAL External Reset Input. A reset is valid when INITX="L". Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Power supply Pin Power supply Pin Power supply Pin GND Pin GND Pin GND Pin Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Internal CR-osc clock output port LQFP-48 QFN-48 AVCC NC 22 Function NC pin. NC pin should be kept open. NC pin. NC pin should be kept open. NC pin. NC pin should be kept open. NC pin. NC pin should be kept open. MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  I/O CIRCUIT TYPE Type Circuit Remarks A It is possible to select the main oscillation / GPIO function P-ch P-ch Digital output X1 N-ch Digital output R Pull-up resistor control Digital input Standby mode Control When the main oscillation is selected.  Oscillation feedback resistor : Approximately 1MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH= -4mA, IOL= 4mA Clock input Standby mode Control Digital input Standby mode Control R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control  CMOS level hysteresis input  Pull-up resistor : Approximately 50kΩ B Pull-up resistor Digital input January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 23 D a t a S h e e t Type Circuit Remarks  Open drain output  CMOS level hysteresis input C Digital input Digital output N-ch D It is possible to select the sub oscillation / GPIO function P-ch P-ch When the sub oscillation is selected.  Oscillation feedback resistor : Approximately 5MΩ  With Standby mode control Digital output X1A N-ch Digital output R Pull-up resistor control Digital input Standby mode Control Clock input When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH= -4mA, IOL= 4mA Standby mode Control Digital input Standby mode Control R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control 24 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Type Circuit Remarks E P-ch P-ch N-ch Digital output  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH= -4mA, IOL= 4mA Digital output R Pull-up resistor control Digital input Standby mode Control F P-ch P-ch N-ch R Digital output Digital output  CMOS level output  CMOS level hysteresis input  With input control  Analog input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH= -4mA, IOL= 4mA Pull-up resistor control Digital input Standby mode Control Analog input Input control January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 25 D a t a S h e e t Type Circuit Remarks  CMOS level output  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH= -12mA, IOL= 12mA G P-ch P-ch N-ch Digital output Digital output R Pull-up resistor control Digital input Standby mode Control  CMOS level output  CMOS level hysteresis input  With standby mode control  IOH= -20.5mA, IOL=18.5mA H P-ch N-ch Digital output Digital output R Digital input Standby mode Control 26 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Type Circuit Remarks I P-ch P-ch N-ch Digital output Digital output R  CMOS level output  CMOS level hysteresis input  5V tolerant  With pull-up resistor control  With standby mode control  Pull-up resistor : Approximately 50kΩ  IOH= -4mA, IOL= 4mA  Available to control of PZR registers. Pull-up resistor control Digital input Standby mode Control J CMOS level hysteresis input Mode input January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 27 D a t a S h e e t  HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-1Ea 28 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.  Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion 's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 29 D a t a S h e e t  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 30 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 31 D a t a S h e e t  HANDLING DEVICES  Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins and GND pins near this device.  Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation.  Using an external clock When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A pin should be kept open.  Example of Using an External Clock Device X0(X0A) Open X1(X1A)  Handling when using Multi-function serial pin as I2C pin If it is using Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF. 32 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  C pin As this series includes an internal regulator, always connect a bypass capacitor of approximately 4.7 µF to the C pin for use by the regulator. C Device 4.7μF VSS GND  Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise.  NC pins NC pin should be kept open.  Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC =VCC and AVSS = VSS. Turning on :VCC → AVCC → AVRH Turning off : AVRH → AVCC → VCC  Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data.  Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.  Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 33 D a t a S h e e t  BLOCK DIAGRAM MB9AF111K, MB9AF112K TRSTX,TCK, TDI,TMS TDO SRAM0 8 Kbyte SWJ-DP ROM Table SRAM1 8 Kbyte Multi-layer AHB (Max 42 MHz) Cortex-M3 Core I @42 MHz(Max) D NVIC Sys AHB-APB Bridge: APB0(Max 42 MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) MainFlash I/F Security WorkFlash I/F Main Osc Sub Osc AHB-AHB Bridge RST CLK AVCC, AVSS, AVRH PLL CR 4MHz CR 100kHz 12-bit A/D Converter Unit 0 Power On Reset AN[07:00] Unit 1 LVD Ctrl ADTG_2 AIN0 BIN0 ZIN0 QPRC 1ch. A/D Activation Compare 3ch. IC0x FRCKx 16-bit Input Capture 4ch. 16-bit Free-Run Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTOx Waveform Generator 3ch. LVD Regulator Deep Standby Ctrl AHB-APB Bridge : APB2 (Max 42 MHz) TIOBx Base Timer 16-bit 8ch./ 32-bit 4ch. AHB-APB Bridge : APB1 (Max 42 MHz) TIOAx WorkFlash 32 Kbyte DMAC 4ch. CSV X0 X1 X0A X1A MainFlash 64 Kbyte/ 128 Kbyte C WKUP[3:0] RTCCO, SUBOUT Real-Time Clock IRQ-Monitor CRC Accelerator Watch Counter External Interrupt Controller 6-pin + NMI INTx NMIX MODE-Ctrl MD[1:0] P0x, P1x, GPIO PIN-Function-Ctrl ・ ・ PFx 16-bit PPG 3ch. Multi-Function Timer Multi-Function Serial I/F 4ch. (with FIFO ch.0 - ch.1) SCKx SINx SOTx  MEMORY SIZE See "Memory size" in "PRODUCT LINEUP" to confirm the memory size. 34 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  MEMORY MAP  Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF 0x4006_1000 Reserved 0x4006_0000 DMAC 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved 0x4003_C000 External Device 0x4003_B000 RTC Area 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4003_8000 MFS 0x6000_0000 Reserved 0x4003_6000 Reserved 0x4400_0000 0x4200_0000 0x4000_0000 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 32Mbyte Bit band alias 0x4003_3000 GPIO 0x4003_2000 Reserved Peripherals 0x4003_1000 Int-Req. Read 0x4003_0000 0x4002_F000 Reserved 0x4002_E000 0x2400_0000 0x2200_0000 32Mbyte Bit band alias Reserved 0x4002_8000 0x4002_7000 A/DC 0x200E_1000 Reserved 0x4002_6000 QPRC 0x200E_0000 WorkFlash I/F 0x4002_5000 Base Timer 0x200C_0000 WorkFlash 0x4002_4000 PPG 0x2008_0000 Reserved 0x2000_0000 SRAM1 See the next page "Memory Map (2)" for 0x1FFF_0000 the memory size 0x0010_2000 details. 0x0010_0000 SRAM0 Reserved 0x4002_1000 0x4002_0000 Reserved 0x4001_6000 Security/CR Trim 0x4001_5000 0x4001_3000 MainFlash 0x0000_0000 Reserved Dual Timer Reserved SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_0000 January 31, 2014, MB9AF112K-DS706-00030-1v1-E MFT unit0 0x4001_2000 0x4000_1000 CONFIDENTIAL EXTI Reserved CR Trim Reserved MainFlash I/F 35 D a t a S h e e t  Memory Map (2) MB9AF111K MB9AF112K 0x200E_0000 0x200E_0000 Reserved Reserved 0x200C_8000 0x200C_8000 WorkFlash WorkFlash 0x200C_0000 32Kbyte 0x200C_0000 Reserved Reserved 0x2000_2000 0x2000_2000 SRAM1 SRAM1 8Kbyte 8Kbyte 0x2000_0000 0x2000_0000 SRAM0 SRAM0 0x1FFF_E000 32Kbyte 8Kbyte 0x1FFF_E000 8Kbyte Reserved Reserved 0x0010_2000 0x0010_2000 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_0000 Security 0x0010_0000 Security Reserved Reserved 0x0002_0000 MainFlash 0x0001_0000 128Kbyte 0x0000_0000 36 CONFIDENTIAL MainFlash 0x0000_0000 64Kbyte MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  Peripheral Address Map Start address End address Bus 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low Voltage Detector 0x4003_5800 0x4003_5FFF 0x4003_6000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface AHB APB0 APB1 APB2 Peripherals MainFlash I/F register Reserved Software Watchdog timer Reserved Quadrature Position/Revolution Counter Deep stand-by mode Controller 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF 0x4006_1000 0x41FF_FFFF 0x200E_0000 0x200E_FFFF January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL AHB DMAC register Reserved WorkFlash I/F register 37 D a t a S h e e t  PIN STATUS IN EACH CPU STATE The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the "L" level.  INITX=1 This is the period when the INITX pin is the "H" level.  SPL=0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".  SPL=1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  GPIO selected In Deep stand-by mode, pins switch to the general-purpose I/O port. 38 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Pin status type  List of Pin Status Function group Power-on reset or Device Run mode INITX input low-voltage internal or sleep state detection reset state mode state state Power supply stable INITX = 1 INITX = 1 - Timer mode, RTC mode, or sleep mode state Power supply unstable - Power supply stable Power supply stable Power supply stable INITX = 0 - INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 GPIO Setting Setting Setting selected disabled disabled disabled Maintain Maintain previous previous state state A Main crystal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Input Input Input Input Input Input Input Input Input enabled enabled enabled enabled enabled enabled enabled enabled GPIO Setting Setting Setting Maintain Maintain selected disabled disabled disabled previous previous state state pin B Main crystal oscillator output pin D Hi-Z / Internal Power supply stable INITX = 1 - enabled oscillator input C Deep stand-by RTC Return from mode or Deep Deep stand-by STOP mode stand-by state mode state INITX input pin Hi-Z/ Internal input fixed at "0"/ or Input enable Hi-Z / Hi-Z / Internal Internal input fixed input fixed at "0" at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous state /When state /When state /When state /When state /When oscillation oscillation oscillation oscillation oscillation stop*1,Hi-Z/ stop*1,Hi-Z/ stop*1,Hi-Z/ stop*1,Hi-Z/ stop*1,Hi-Z// Internal Internal Internal Internal input fixed input fixed input fixed input fixed Internal input fixed at "0" at "0" at "0" at "0" at "0" Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Input Input Input Input Input Input Input Input Input enabled enabled enabled enabled enabled enabled enabled enabled enabled Mode Input Input Input Input Input Input Input Input Input input pin enabled enabled enabled enabled enabled enabled enabled enabled enabled Pull-up / Pull-up / Maintain Maintain Maintain Maintain Input Input previous previous previous previous enabled enabled state state state state JTAG selected Hi-Z E Maintain Maintain previous previous state state Hi-Z / GPIO Setting Setting Setting Internal selected disabled disabled disabled input fixed at "0" January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state 39 Pin status type D a t a S h e e t Function group Power-on reset or Device Run mode INITX input low-voltage internal or sleep state detection reset state mode state state Power supply stable Power supply stable Power supply stable INITX = 0 - INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 WKUP Setting Setting Setting enabled disabled disabled disabled Hi-Z / Internal selected Maintain Maintain WKUP previous previous previous input state state state enabled Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled previous state Setting Setting Setting disabled disabled disabled Maintain Maintain previous previous state state GPIO selected Setting Setting Setting enabled disabled disabled disabled interrupt enabled selected Setting Setting Setting disabled disabled disabled Resource other than above selected Hi-Z GPIO interrupt enabled selected H Hi-Z / Hi-Z / Input Input enabled enabled WKUP input state state state enabled Internal Setting Setting Setting disabled disabled disabled state Maintain Maintain previous previous state state GPIO Hi-Z / Input Input enabled enabled Hi-Z GPIO selected at "0" Maintain previous state Hi-Z / WKUP GPIO input selected enabled GPIO selected Hi-Z / Hi-Z / Internal GPIO selected input fixed Internal at "0" input fixed Maintain at "0" previous previous state state Maintain previous state selected resource selected enabled Maintain state Hi-Z / at "0" / Analog input previous state Hi-Z input fixed Maintain previous CONFIDENTIAL previous previous previous 40 at "0" Maintain than above GPIO Maintain previous Maintain selected Internal input fixed Maintain Maintain I Hi-Z / Hi-Z / Internal input fixed previous Resource other selected Hi-Z / Maintain selected External GPIO selected state WKUP External enabled at "0" / enabled selected selected selected at "0" / Maintain than above GPIO input at "0" / External Resource other WKUP at "0" / interrupt Power supply stable INITX = 1 - Hi-Z / Maintain input fixed input fixed input fixed input fixed input fixed input fixed input fixed Hi-Z F G Deep stand-by RTC Return from mode or Deep Deep stand-by STOP mode stand-by state mode state Power supply unstable - Analog input Power supply stable INITX = 1 INITX = 1 - Timer mode, RTC mode, or sleep mode state Hi-Z / Hi-Z / Maintain Maintain Input Input previous previous enabled enabled state state GPIO selected Hi-Z / Internal Maintain at "0" previous Hi-Z / input fixed at "0" Internal GPIO selected input fixed input fixed Internal Hi-Z / at "0" Maintain previous state state GPIO GPIO selected Maintain previous state Hi-Z / Internal input fixed at "0" selected Maintain previous state MB9AF112K-DS706-00030-1v1-E, January 31, 2014 Pin status type D a t a S h e e t Function group NMIX selected Power-on reset or Device Run mode INITX input low-voltage internal or sleep state detection reset state mode state state Power supply stable INITX = 1 INITX = 1 - Power supply stable Power supply stable Power supply stable INITX = 0 - INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Setting Setting Setting disabled disabled disabled than above selected Hi-Z GPIO selected previous state Maintain Maintain WKUP previous previous Hi-Z / input state state Internal enabled Input Input enabled enabled Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal input fixed L at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled Maintain Maintain previous previous state state Setting Setting Setting disabled disabled disabled Hi-Z / Internal Hi-Z / Internal Maintain at "0" previous state Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed input fixed input fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog input input input input input input input enabled enabled enabled enabled enabled enabled enabled previous state Setting Setting Setting disabled disabled disabled Maintain previous previous state state GPIO selected GPIO selected Hi-Z / Hi-Z / Internal Internal input fixed Maintain at "0" previous Setting Setting Setting selected disabled disabled disabled Maintain Maintain previous previous state state Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected input fixed at "0" Maintain previous state Maintain previous state GPIO GPIO selected previous Hi-Z / Maintain enabled at "0" Hi-Z / enabled selected at "0" / Analog input input fixed state Hi-Z input fixed Maintain Maintain selected GPIO selected Hi-Z / Internal input fixed External than above Maintain previous input fixed input fixed input fixed input fixed input fixed input fixed input fixed Hi-Z interrupt Resource other enabled at "0" selected selected GPIO selected input Hi-Z / than above Analog input WKUP Hi-Z / Resource other GPIO Hi-Z / state K selected Power supply stable INITX = 1 - Maintain selected Analog input Deep stand-by RTC Return from mode or Deep Deep stand-by STOP mode stand-by state mode state Power supply unstable - Resource other J Timer mode, RTC mode, or sleep mode state state Hi-Z / Internal input fixed at "0" Maintain previous state M Sub crystal oscillator input pin Input Input Input Input Input Input Input Input Input enabled enabled enabled enabled enabled enabled enabled enabled enabled January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 41 Pin status type D a t a S h e e t Function group Deep stand-by RTC Return from mode or Deep Deep stand-by STOP mode stand-by state mode state Power supply stable Power supply stable Power supply stable INITX = 0 - INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 GPIO Setting Setting Setting selected disabled disabled disabled Sub crystal oscillator output pin GPIO selected Hi-Z/ Internal input fixed at "0"/ or Input enable Hi-Z Power supply stable INITX = 1 INITX = 1 - Timer mode, RTC mode, or sleep mode state Power supply unstable - N O Power-on reset or Device Run mode INITX input low-voltage internal or sleep state detection reset state mode state state Hi-Z / Hi-Z / Internal Internal input fixed input fixed at "0" at "0" Maintain Maintain previous previous state state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed Power supply stable INITX = 1 Maintain previous state at "0" Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous state /When state /When state /When state /When state /When oscillation oscillation oscillation oscillation oscillation stop*2,Hi-Z/ stop*2,Hi-Z/ stop*2,Hi-Z/ stop*2,Hi-Z/ stop*2,Hi-Z/ Internal Internal Internal Internal input fixed input fixed input fixed input fixed at "0" Hi-Z / Hi-Z / Maintain Maintain Input Input previous previous enabled enabled state state at "0" Hi-Z / Internal input fixed at "0" at "0" Maintain previous state Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state at "0" Mode Input Input Input Input Input Input Input Input Input input pin enabled enabled enabled enabled enabled enabled enabled enabled enabled GPIO Setting Setting Setting Maintain Maintain Hi-Z / Maintain Hi-Z / Maintain selected disabled disabled disabled previous previous Input previous Input previous state state enabled state enabled state P *1 : Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep stand-by RTC mode, and Deep stand-by STOP mode. *2 : Oscillation is stopped at STOP mode and Deep stand-by STOP mode. 42 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage *1, *2 Analog power supply voltage *1, *3 Analog reference voltage *1, *3 Symbol Vcc AVcc AVRH Rating Min Max Unit Remarks Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss + 6.5 V Vss + 6.5 V Vss + 6.5 V Vcc + 0.5 Vss - 0.5 V (≤6.5V) Input voltage VI Vss - 0.5 Vss + 6.5 V 5V tolerant AVcc + 0.5 Analog pin input voltage VIA Vss - 0.5 V (≤6.5V) Vcc + 0.5 Output voltage VO Vss - 0.5 V (≤6.5V) 10 mA 4mA type "L" level maximum output current *4 IOL 20 mA 12mA type 4 mA 4mA type "L" level average output current *5 IOLAV 12 mA 12mA type "L" level total maximum output current ∑IOL 100 mA "L" level total average output current *6 ∑IOLAV 50 mA 10 mA 4mA type "H" level maximum output current *4 IOH - 20 mA 12mA type -4 mA 4mA type "H" level average output current *5 IOHAV - 12 mA 12mA type "H" level total maximum output current ∑IOH - 100 mA "H" level total average output current *6 ∑IOHAV - 50 mA Power consumption PD 300 mW Storage temperature TSTG - 55 + 150 °C *1 : These parameters are based on the condition that VSS = AVSS = 0.0V. *2 : Vcc must not drop below VSS - 0.5V. *3 : Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on. *4 : The maximum output current is the peak value for a single pin. *5 : The average output is the average current for a single pin over a period of 100 ms. *6 : The total average output current is the average current for all pins over a period of 100 ms. Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 43 D a t a S h e e t 2. Recommended Operating Conditions (Vss = AVss = 0.0V) Parameter Power supply voltage Analog power supply voltage Analog reference voltage Operating temperature Symbol Conditions Vcc AVcc AVRH Ta - Value Min Max 2.7 2.7 AVss - 40 5.5 5.5 AVcc + 105 Unit V V V °C Remarks AVcc=Vcc The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 44 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t 3. DC Characteristics (1) Current Rating (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Min Value Unit Typ Max Power supply current VCC Iccs ICCH ICCT 32 41 mA - 21 28 mA Normal operation (high-speed internal CR) - 3.9 7.7 mA Normal operation (sub oscillation) - 0.15 3.2 mA Normal operation (low-speed internal CR) - 0.2 3.3 mA - 10 15 mA - 1.2 4.4 mA Peripheral : 4MHz *1, *2 - 0.1 3.1 mA Peripheral : 32kHz *1 - 0.1 3.1 mA Peripheral : 100kHz *1 - 35 200 μA - - 3 mA - 60 230 μA - - 3.1 mA SLEEP operation (PLL) SLEEP operation (high-speed internal CR) SLEEP operation (sub oscillation) SLEEP operation (low-speed internal CR) STOP mode TIMER mode (sub oscillation) January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL CPU : 40MHz, Peripheral : 40MHz, MainFlash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1 CPU : 40MHz, Peripheral : 40MHz, MainFlash 3Wait FRWTR.RWT = 00 FSYNDN.SD = 011 *1 CPU/Peripheral : 4MHz *1, *2 MainFlash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/Peripheral : 32kHz MainFlash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1 CPU/Peripheral : 100kHz MainFlash 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1 Peripheral : 40MHz *1 Normal operation (PLL) Icc Remarks Ta = + 25°C, When LVD is off *1 Ta = + 105°C, When LVD is off *1 Ta = + 25°C, When LVD is off *1 Ta = + 105°C, When LVD is off *1 45 D a t a S h e e t Parameter Symbol Pin name ICCR Conditions Min Value Typ Max Unit - 50 210 μA - - 3.1 μA 20 150 μA 23 150 μA - 600 μA - 610 μA 30 160 μA 33 160 μA - 600 μA - 610 μA 4 7 μA RTC mode - Deep stand-by STOP mode ICCHD Power supply current - VCC - ICCRD Deep stand-by RTC mode - Low-voltage detection circuit (LVD) ICCLVD At operation power supply current *1: When all ports are fixed. *2: When setting it to 4MHz by trimming. *3: When using sub crystal oscillator. *4: RAM hold setting is on-chip SRAM only. 46 CONFIDENTIAL - Remarks Ta = + 25°C, When LVD is off *1, *3 Ta = + 105°C, When LVD is off *1, *3 Ta = + 25°C, When LVD is off RAM hold off *1, *4 Ta = + 25°C, When LVD is off RAM hold on *1, *4 Ta = + 105°C, When LVD is off RAM hold off *1, *4 Ta = + 105°C, When LVD is off RAM hold on *1, *4 Ta = + 25°C, When LVD is off RAM hold off *1, *3, *4 Ta = + 25°C, When LVD is off RAM hold on *1, *3, *4 Ta = + 105°C, When LVD is off RAM hold off *1, *3, *4 Ta = + 105°C, When LVD is off RAM hold on *1, *3, *4 For occurrence of interrupt MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t (2) Pin Characteristics (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name "H" level input voltage (hysteresis input) VIHS "L" level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin 4mA type "H" level output voltage VOH 12mA type P80/P81 January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL Conditions Min Value Typ Max Unit Remarks - Vcc × 0.8 - Vcc + 0.3 V - Vcc × 0.8 - Vss + 5.5 V - Vss - 0.3 - Vcc × 0.2 V - Vss - 0.3 - Vcc × 0.2 V Vcc - 0.5 - Vcc V Vcc - 0.5 - Vcc V Vcc - 0.4 - Vcc V Vcc ≥ 4.5 V IOH = - 4mA Vcc < 4.5 V IOH = - 2mA Vcc ≥ 4.5 V IOH = - 12mA Vcc < 4.5 V IOH = - 8mA Vcc ≥ 4.5 V IOH = - 20.5 mA Vcc < 4.5 V IOH = - 13.0 mA 47 D a t a S h e e t Parameter Symbol Pin name 4mA type "L" level output voltage VOL 12mA type P80/P81 Input leak current Pull-up resistance value Input capacitance 48 CONFIDENTIAL IIL - RPU Pull-up pin CIN Other than VCC, VSS, AVCC, AVSS, AVRH Conditions Value Unit Remarks Min Typ Max Vss - 0.4 V Vss - 0.4 V Vss - 0.4 V - -5 - +5 μA Vcc ≥ 4.5 V 25 50 100 Vcc < 4.5 V 30 80 200 - - 5 15 Vcc ≥ 4.5 V IOL = 4mA Vcc < 4.5 V IOL = 2mA Vcc ≥ 4.5 V IOL = 12mA Vcc < 4.5 V IOL = 8mA Vcc ≥ 4.5 V IOL = 18.5mA Vcc< 4.5 V IOL = 10.5mA kΩ pF MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t 4. AC Characteristics (1) Main Clock Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin Conditions name Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V PWH/tCYLH PWL/tCYLH Value Min Max 4 4 4 4 20.83 50 48 20 48 20 250 250 Unit Remarks When crystal oscillator is connected Input frequency FCH When using external MHz clock X0 When using external Input clock cycle tCYLH ns X1 clock Input clock pulse When using external 45 55 % width clock Input clock rise tCF, When using external 5 ns time and fall time tCR clock Base clock FCC 42 MHz (HCLK/FCLK) Internal operating FCP0 42 MHz APB0 bus clock*2 clock frequency*1 FCP1 42 MHz APB1 bus clock*2 FCP2 42 MHz APB2 bus clock*2 Base clock tCYCC 23.8 ns (HCLK/FCLK) Internal operating t 23.8 ns APB0 bus clock*2 CYCP0 clock cycle time*1 tCYCP1 23.8 ns APB1 bus clock*2 tCYCP2 23.8 ns APB2 bus clock*2 *1: For more information about each internal operating clock, see "Chapter: Clock" in "FM3 Family PERIPHERAL MANUAL". *2: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data sheet. MHz X0 January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 49 D a t a S h e e t (2) Sub Clock Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Input frequency Symbol Min Value Typ Max - - 32.768 - kHz - 32 - 100 kHz Pin Conditions name Unit 1/ tCYLL X0A X1A Input clock cycle tCYLL - 10 - 31.25 μs Input clock pulse width - PWH/tCYLL PWL/tCYLL 45 - 55 % Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock X0A (3) Internal CR Oscillation Characteristics  High-speed Internal CR (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Ta = + 25°C Min Value Typ Max 3.96 4 4.04 Unit Remarks Ta = When trimming* 3.84 4 4.16 0°C to + 70°C Clock frequency FCRH MHz Ta = 3.8 4 4.2 - 40°C to + 85°C Ta = 3 4 5 When not trimming - 40°C to + 85°C *: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.  Low-speed Internal CR (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Clock frequency 50 CONFIDENTIAL Symbol Conditions FCRL - Min Value Typ Max 50 100 150 Unit Remarks kHz MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t (4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Min Typ Max Remarks PLL oscillation stabilization wait time* tLOCK 100 μs (LOCK UP time) PLL input clock frequency FPLLI 4 16 MHz PLL multiple rate 13 75 multiple PLL macro oscillation clock frequency FPLLO 200 300 MHz *: Time from when the PLL starts operating until the oscillation stabilizes. (4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Value Unit Min Typ Max Remarks PLL oscillation stabilization wait time* tLOCK 100 μs (LOCK UP time) PLL input clock frequency FPLLI 3.8 4 4.2 MHz PLL multiple rate 50 71 multiple PLL macro oscillation clock frequency FPLLO 190 300 MHz *: Time from when the PLL starts operating until the oscillation stabilizes. Note : It needs to input to PLL by internal CR trimming frequency. (5) Reset Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Reset input time Symbol tINITX Value Pin Conditions name Min Max INITX 500 - - Unit Remarks ns (6) Power-on Reset Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Power supply rising time Tr Power supply shut down time Toff Pin name VCC Tr Value Unit Min Max 0 - ms 1 - ms Remarks Toff 2.7V Vcc 0.2V January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 0.2V 0.2V 51 D a t a S h e e t (7) Base Timer Input Timing  Timer input timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Input pulse width Symbol Pin name Conditions tTIWH tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK TIN VIHS VIHS VILS VILS  Trigger input timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Input pulse width Symbol Pin name Conditions tTRGH tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which Base Timer is connected to, see "BLOCK DIAGRAM" in this data sheet. 52 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t (8) UART Timing  Synchronous serial (SPI = 0, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin Conditions name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK fall time SCK rise time tF tR SCKx SCKx SOTx Internal shift clock SCKx operation SINx SCKx SINx SCKx External shift SOTx clock SCKx operation SINx SCKx SINx SCKx SCKx Vcc < 4.5V Min Max Vcc ≥ 4.5V Min Max Unit 4tcycp - 4tcycp - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tcycp 10 tcycp + 10 - 2tcycp 10 tcycp + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30pF. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 53 D a t a S h e e t tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI SIN tSHIXI VIH VIL VIH VIL MS bit = 0 tSLSH SCK VIH tF SOT SIN VIL tSHSL VIL VIH VIH tR tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 54 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  Synchronous serial (SPI = 0, SCINV = 1) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin Conditions name Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK fall time SCK rise time tF tR SCKx SCKx SOTx Internal shift clock SCKx operation SINx SCKx SINx SCKx External shift SOTx clock SCKx operation SINx SCKx SINx SCKx SCKx Vcc < 4.5V Min Max Vcc ≥ 4.5V Min Max Unit 4tcycp - 4tcycp - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tcycp 10 tcycp + 10 - 2tcycp 10 tcycp + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30pF. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 55 D a t a S h e e t tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI SIN VIH VIL tSLIXI VIH VIL MS bit = 0 tSHSL SCK VIH SIN VIH VIL tR SOT tSLSH VIL VIL tF tSHOVE VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 56 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  Synchronous serial (SPI = 1, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin Conditions name Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK fall time SCK rise time tF tR SCKx SCKx SOTx SCKx Internal shift clock SINx operation SCKx SINx SCKx SOTx SCKx External shift SOTx clock SCKx operation SINx SCKx SINx SCKx SCKx Vcc < 4.5V Min Max Vcc ≥ 4.5V Min Max Unit 4tcycp - 4tcycp - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns - ns 2tcycp 30 2tcycp 10 tcycp + 10 - 2tcycp 30 2tcycp 10 tcycp + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30pF. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 57 D a t a S h e e t tSCYC VOH VOL SCK SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK VIH tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN VIH VIL tF * SOT VIL tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register 58 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  Synchronous serial (SPI = 1, SCINV = 1) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin Conditions name Vcc < 4.5V Min Max Vcc ≥ 4.5V Min Max Unit Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns SCK ↓ → SOT delay time tSLOVI SCKx SOTx -30 +30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI - ns Serial clock "L" pulse width tSLSH SCKx - ns Serial clock "H" pulse width tSHSL SCKx - ns SCK ↓→ SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK fall time SCK rise time tF tR SCKx Internal shift clock SINx operation SCKx SINx SCKx SOTx SCKx External shift SOTx clock SCKx operation SINx SCKx SINx SCKx SCKx 2tcycp 30 2tcycp 10 tcycp + 10 - 2tcycp 30 2tcycp 10 tcycp + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.  When the external load capacitance = 30pF. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 59 D a t a S h e e t tSCYC VOH SCK VOH VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VIH VIL MS bit = 0 tSHSL tR SCK VIL tSLSH VIH VIH tF VIL VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL MS bit = 1  External clock (EXT = 1) : asynchronous only (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Serial clock "L" pulse width Serial clock "H" pulse width SCK fall time SCK rise time tSLSH tSHSL tF tR CL = 30pF tR SCK VIL 60 CONFIDENTIAL Min Max tcycp + 10 tcycp + 10 - 5 5 tSHSL VIH VIL ns ns ns ns tF tSLSH VIH Unit Remarks VIL VIH MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t (9) External Input Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Remarks A/D converter trigger input 2tCYCP*1 ns Free-run timer input FRCKx clock ICxx Input capture tINH, Input pulse width Wave form tINL DTTIxX 2tCYCP*1 ns generator 2tCYCP + 100*1 ns External interrupt INT00 to INT15 NMIX 500*2 ns NMI Deep stand-by wake WKUPx 820*3 ns up *1 : tCYCP indicates the APB bus clock cycle time except stop when in stop mode, in rtc mode, in timer mode. About the APB bus number which A/D converter, Multi-function Timer, External interrupt are connected to, see "BLOCK DIAGRAM" in this data sheet. *2 : When in stop mode, in rtc mode, in timer mode. *3 : When in deep stand-by stop mode, in deep stand-by rtc mode. ADTG January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 61 D a t a S h e e t (10) Quadrature Position/Revolution Counter timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Min Max Unit AIN pin "H" width tAHL AIN pin "L" width tALL BIN pin "H" width tBHL BIN pin "L" width tBLL BIN rise time from PC_Mode2 or tAUBU AIN pin "H" level PC_Mode3 AIN fall time from PC_Mode2 or tBUAD BIN pin "H" level PC_Mode3 BIN fall time from PC_Mode2 or tADBD AIN pin "L" level PC_Mode3 AIN rise time from PC_Mode2 or tBDAU BIN pin "L" level PC_Mode3 AIN rise time from PC_Mode2 or 2tCYCP* ns tBUAU BIN pin "H" level PC_Mode3 BIN fall time from PC_Mode2 or tAUBD AIN pin "H" level PC_Mode3 AIN fall time from PC_Mode2 or tBDAD BIN pin "L" level PC_Mode3 BIN rise time from PC_Mode2 or tADBU AIN pin "L" level PC_Mode3 ZIN pin "H" width tZHL QCR:CGSC="0" ZIN pin "L" width tZLL QCR:CGSC="0" AIN/BIN rise and fall time tZABE QCR:CGSC="1" from determined ZIN level Determined ZIN level from tABEZ QCR:CGSC="1" AIN/BIN rise and fall time *: tCYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "BLOCK DIAGRAM" in this data sheet. AIN BIN 62 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t BIN AIN ZIN ZIN AIN/BIN January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 63 D a t a S h e e t (11) I2C Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions High-speed mode Unit Remarks Max Min Max Typical mode Min SCL clock frequency FSCL 0 100 0 400 kHz (Repeated) START condition hold time tHDSTA 4.0 0.6 μs SDA ↓→ SCL ↓ SCLclock "L" width tLOW 4.7 1.3 μs SCLclock "H" width tHIGH 4.0 0.6 μs (Repeated) START setup time tSUSTA 4.7 0.6 μs SCL ↑→ SDA ↓ CL = 30pF, Data hold time tHDDAT R = (Vp/IOL)*1 0 3.45*2 0 0.9*3 μs SCL ↓→ SDA ↓ ↑ Data setup time tSUDAT 250 100 ns SDA ↓ ↑ → SCL ↑ STOP condition setup time tSUSTO 4.0 0.6 μs SCL ↑→ SDA ↑ Bus free time between "STOP condition" and tBUF 4.7 1.3 μs "START condition" Noise filter tSP 2 tCYCP*4 2 tCYCP*4 ns *1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4 : tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet. To use I2C, set the peripheral bus clock at 8 MHz or more. SDA SCL 64 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t (12) JTAG Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions TCK, TMS, TDI TCK, TMS, TDI Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V Vcc < 4.5V Vcc ≥ 4.5V TMS, TDI setup time tJTAGS TMS, TDI hold time tJTAGH TDO delay time tJTAGD TCK, TDO Vcc < 4.5V Value Min Max Unit 15 - ns 15 - ns - 25 - 45 Remarks ns Note: When the external load capacitance = 30pF. TCK TMS/TDI TDO January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 65 D a t a S h e e t 5. 12-bit A/D Converter  Electrical characteristics for the A/D converter (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 105°C) Parameter Resolution Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Compare clock cycle*3 State transition time to operation permission Power supply current (analog + digital) Reference power supply current (between AVRH to AVSS) Pin name Min Value Typ Max - - 4.5 - 12 + 4.5 bit LSB - -2.5 - + 2.5 LSB - + 20 mV AN0 to - 20 AN7 AN0 to AVRH - 20 AN7 1.0*1 *2 Ts *2 - - μs ns Tcck 50 - 2000 ns Tstt 1.0 - - μs AVCC - 0.57 0.06 0.72 20 - 1.1 1.96 - 0.06 4 12.9 AVRH Cin - - Analog input resistance Rin - - Remarks AVRH = 2.7V to 5.5V AVRH + 20 mV - Analog input capacity Interchannel disparity Analog port input current Unit 2 3.8 4 AVcc ≥ 4.5V AVcc ≥ 4.5V AVcc < 4.5V AVcc ≥ 4.5V AVcc < 4.5V mA A/D 1unit operation μA When A/D stop A/D 1unit operation mA AVRH=5.5V μA When A/D stop (1unit) pF kΩ AVcc ≥ 4.5V AVcc < 4.5V LSB AN0 to 5 μA AN7 AN0 to Analog input voltage AVSS AVRH V AN7 Reference voltage AVRH 2.7 AVCC V *1: Conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is the value of sampling time: 300ns, the value of sampling time: 700ns (AVcc ≥ 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4 of sampling time and compare clock cycle, see "Chapter:A/D Converter" in "FM3 Family PERIPHERAL MANUAL Analog Macro Part". *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: Compare time (Tc) is the value of (Equation 2). *4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. Sampling clock and compare clock are set in base clock (HCLK). About the APB bus number which A/D Converter is connected to, see "BLOCK DIAGRAM" in this data sheet. 66 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t Rext AN0 to AN7 Analog input pin Comparator Rin Analog signal source Cin (Equation 1) Ts ≥ ( Rin + Rext ) × Cin × 9 Ts : Sampling time Rin : input resistance of A/D = 2kΩ at 4.5 < AVCC < 5.5 input resistance of A/D = 3.8kΩ at 2.7 < AVCC < 4.5 Cin : input capacity of A/D = 12.9pF at 2.7 < AVCC < 5.5 Rext : Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc : Compare time Tcck : Compare clock cycle January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 67 D a t a S h e e t  Definition of 12-bit A/D Converter Terms  Resolution  Linearity error : Analog variation that is recognized by an A/D converter. : Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics.  Differential linearity error : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Linearity error Differential linearity error 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VOT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VOT (Actually-measured value) AVss Actual conversion characteristics AVRH AVss AVRH Analog input Linearity error of digital output N = Analog input VNT - {1LSB × (N - 1) + VOT} 1LSB Differential linearity error of digital output N = 1LSB = N VOT VFST VNT 68 CONFIDENTIAL : : : : V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VOT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t 6. Low-voltage Detection Characteristics (1) Low-voltage Detection Reset (Ta = - 40°C to + 105°C) Parameter Detected voltage Released voltage Symbol Conditions VDL VDH - Min Value Typ Max 2.25 2.30 2.45 2.50 2.65 2.70 Unit V V Remarks When voltage drops When voltage rises (2) Interrupt of Low-voltage Detection (Ta = - 40°C to + 105°C) Parameter Symbol Conditions Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH LVD stabilization wait time TLVDW SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0111 SVHI = 1000 SVHI = 1001 - Min Value Typ Max 2.58 2.67 2.76 2.85 2.94 3.04 3.31 3.40 3.40 3.50 3.68 3.77 3.77 3.86 3.86 3.96 2.8 2.9 3.0 3.1 3.2 3.3 3.6 3.7 3.7 3.8 4.0 4.1 4.1 4.2 4.2 4.3 3.02 3.13 3.24 3.34 3.45 3.56 3.88 3.99 3.99 4.10 4.32 4.42 4.42 4.53 4.53 4.64 V V V V V V V V V V V V V V V V - - 2240 × tcycp* μs Unit Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 69 D a t a S h e e t 7. MainFlash Memory Write/Erase Characteristics (Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C) Parameter Sector erase time Min Large Sector Value Typ Max 0.7 3.7 Small Sector Unit Includes write time prior to internal erase s 0.3 1.1 Half word (16-bit) write time - 12 384 μs Chip erase time - 3.8 16.2 s Remarks Not including system-level overhead time Includes write time prior to internal erase Erase/write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* 10,000 10* 100,000 5* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85°C) . 8. WorkFlash Memory Write/Erase Characteristics (Vcc = 2.7V to 5.5V, Ta = - 40°C to + 105°C) Min Value Typ Max Sector erase time - 0.3 1.5 s Half word (16-bit) write time - 20 384 μs Chip erase time - 1.2 6 s Parameter Unit Remarks Includes write time prior to internal erase Not including system-level overhead time Includes write time prior to internal erase Erase/write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* 10,000 10* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85°C) . 70 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  ORDERING INFORMATION Part number MB9AF111KPMC MB9AF112KPMC MB9AF111KPMC1 MB9AF112KPMC1 MB9AF111KQN MB9AF112KQN January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL Package Plastic  LQFP 48-pin (0.5mm pitch), (FPT-48P-M49) Plastic  LQFP 52-pin (0.65mm pitch), (FPT-52P-M02) Plastic  QFN 48-pin (0.5mm pitch), (LCC-48P-M73) 71 D a t a S h e e t  PACKAGE DIMENSIONS 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.17 g (FPT-48P-M49) 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00 ± 0.20(.354 ± .008)SQ *7.00± 0.10(.276 ± .004)SQ 36 0.145± 0.055 (.006 ± .002) 25 37 24 0.08(.003) Details of "A" part +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 INDEX 48 13 "A" 0°~8° 1 0.50(.020) C 0.10 ± 0.10 (.004 ± .004) (Stand off) 12 0.22 ± 0.05 (.008 ± .002) 0.08(.003) 0.25(.010) M 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 0.60 ± 0.15 (.024 ± .006) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 72 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t 48-pin plastic QFN Lead pitch 0.5 mm Package width× package length 7.00 mm × 7.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX Weight – (LCC-48P-M73) 48-pin plastic QFN (LCC-48P-M73) 7.00±0.10 (.276±.004) 5.50±0.10 (.217±.004) 7.00±0.10 (.276±.004) 0.25±0.05 (.010±.002) 5.50±0.10 (.217±.004) INDEX AREA 0.45 (.018) 1PIN ID (0.20R (.008R)) 0.85±0.05 (.033±.002) 0.05 (.002) MAX C 0.50 (.020) (TYP) 0.40±0.05 (.016±.002) (0.20(.008)) 2011 FUJITSU SEMICONDUCTOR LIMITED HMbC48-73Sc-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 73 D a t a S h e e t 52-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 10.00 × 10.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g Code (Reference) P-LFQFP52-10×10-0.65 (FPT-52P-M02) 52-pin plastic LQFP (FPT-52P-M02) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00± 0.20(.472 ±. 008)SQ *10.00± 0.10(.394 ±. 004)SQ 39 0.145± 0.055 (.006 ±. 002) 27 40 Details of "A" part 26 +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 0.25(.010) INDEX 0.10(.004) 52 14 "A" 1 13 0.65(.026) C 0~8˚ +0.065 0.30 –0.035 +.0026 .012 –.0014 0.13(.005) M 2010 FUJITSU SEMICONDUCTOR LIMITED F52002Sc-2-1 0.50 ± 0.20 (.020 ±. 008) 0.10 ± 0.10 (.004 ±. 004) (Stand off) 0.60 ± 0.15 (.024 ±. 006) Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 74 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t  MAJOR CHANGES Page Revision 1.0 7 8 23 Section Change Results PRODUCT LINEUP PRELIMINARY → Data sheet Added the pin count. PACKAGES I/O CIRCUIT TYPE Revised from "Planning". Corrected the following description to "TypeB". Digital output → Digital input Corrected the following description. Function BLOCK DIAGRAM  AHB (Max 40MHz) → AHB (Max 42MHz)  APB0 (Max 40MHz) → APB0 (Max 42MHz)  APB1 (Max 40MHz) → APB1 (Max 42MHz)  APB2 (Max 40MHz) → APB2 (Max 42MHz) 34 Deleted the description for "USB Clock Ctrl / PLL". ELECTRICAL CHARACTERISTICS 3. DC Characteristics (1) Current Rating 45, 46 61 (9) External Input Timing 5. 12-bit A/D Converter 66  Electrical characteristics for the A/D converter 70 7. MainFlash Memory Write/Erase Characteristics Erase/write cycles and data hold time 8. WorkFlash Memory Write/Erase Characteristics Erase/write cycles and data hold time Revision 1.1 - - January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL  Revised the value of "TBD".  Corrected the value. - Power supply current (ICCR) Typ: 60 → 50 - Power supply current (ICCRD) (RAM hold off) Typ: 45 → 30 - Power supply current (ICCRD) (RAM hold on) Typ: 48 → 33 Revised the value of "TBD".  Deleted "(Preliminary value)".  Corrected the value of "Compare clock cycle". Max: 10000 → 2000 Deleted"(targeted value)". Company name and layout design change 75 D a t a S h e e t 76 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 D a t a S h e e t January 31, 2014, MB9AF112K-DS706-00030-1v1-E CONFIDENTIAL 77 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2012-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 78 CONFIDENTIAL MB9AF112K-DS706-00030-1v1-E, January 31, 2014 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Spansion Inc.: MB9AF111KPMC-G-JNE2