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MB9AF121LPMC1-G-JNE2

MB9AF121LPMC1-G-JNE2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    LQFP-64

  • 描述:

    ICMCU32BIT64KBFLASH64LQFP

  • 数据手册
  • 价格&库存
MB9AF121LPMC1-G-JNE2 数据手册
Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9A120L Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller The CY9A120L Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE11 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM® Cortex®-M3 Core [UART]  Processor version: r2p1  Full duplex double buffer  Up to 40 MHz frequency operation  Selection with or without parity supported  Integrated Nested Vectored Interrupt Controller (NVIC): 1  Built-in dedicated baud rate generator NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit system timer (Sys Tick): System timer for OS task management  External clock available as a serial clock  Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] On-Chip Memories  Full duplex double buffer [Flash memory]  Built-in dedicated baud rate generator  64 Kbytes  Overrun error detection function available  Read cycle: 0 wait-cycle  Security function for code protection [LIN] [SRAM]  Full duplex double buffer  LIN protocol Rev.2.1 supported This series contains 4 Kbyte on-chip SRAM memories that is connected to System bus of Cortex-M3 core.  Master/Slave mode supported  SRAM1: 4 Kbyte  LIN break field generation (can be changed to 13-bit to 16-bit Multi-function Serial Interface (Max four channels)  LIN break delimiter generation (can be changed to 1-bit to length) 4-bit length)  4 channels without FIFO (ch.0, ch.1, ch.3, ch.5)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2 C Cypress Semiconductor Corporation Document Number: 002-05669 Rev. *C  Various error detection functions available (parity errors, framing errors, and overrun errors) [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 7, 2019 CY9A120L Series A/D Converter (Max eight channels) Multi-function Timer The Multi-function timer is composed of the following blocks. [12-bit A/D Converter]  16-bit free-run timer × 3 ch.  Successive Approximation type  Input capture × 3 ch.  Conversion time: 0.8 μs @ 5 V  Output compare × 6 ch.  Priority conversion available (priority at 2 levels)  A/D activation compare × 1 ch.  Scanning conversion mode  Waveform generator × 3 ch.  Built-in FIFO for conversion data storage (for SCAN  16-bit PPG timer × 3 ch. conversion: 16 steps, for Priority conversion: 4 steps) D/A Converter (Max one channel) IGBT mode is contained  R-2R type The following function can be used to achieve the motor control.  10-bit resolution  PWM signal output function Base Timer (Max eight channels) Operation mode is selectable from the followings for each channel.  DC chopper waveform output function  Dead time function  Input capture function  16-bit PWM timer  A/D convertor activate function  16-bit PPG timer  DTIF (Motor emergency stop) interrupt function  16-/32-bit reload timer  16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built-in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 51 high-speed general-purpose I/O Ports@64 pin Package Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. External Interrupt Controller Unit  Some ports are 5V tolerant  Up to 19 external interrupt input pins @ 64 pin Package  See List of Pin Functions and I/O Circuit Type to confirm the  Include one non-maskable interrupt (NMI) input pin corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot Document Number: 002-05669 Rev. *C Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. The Hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption modes except RTC, Stop modes. Page 2 of 90 CY9A120L Series Clock and Reset Low-Voltage Detector (LVD) [Clocks] This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).  Main Clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  LVD1: error reporting via interrupt  LVD2: auto-reset operation  Built-in high-speed CR Clock: 4 MHz Low-Power Consumption Mode  Built-in low-speed CR Clock: 100 kHz  Sleep  Main PLL Clock  Timer [Resets]  RTC  Reset requests from INITX pin  Stop  Power-on reset Debug  Software reset Serial Wire JTAG Debug Port (SWJ-DP)  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset Clock Super Visor (CSV) Four low-power consumption modes supported. Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage: VCC = 2.7 V to 5.5 V Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. Document Number: 002-05669 Rev. *C Page 3 of 90 CY9A120L Series Contents 1. Product Lineup .................................................................................................................................................................. 6 2. Packages ........................................................................................................................................................................... 7 3. Pin Assignment ................................................................................................................................................................. 8 4. List of Pin Functions....................................................................................................................................................... 13 5. I/O Circuit Type ............................................................................................................................................................... 24 6. Handling Precautions ..................................................................................................................................................... 31 6.1 Precautions for Product Design ................................................................................................................................... 31 6.2 Precautions for Package Mounting .............................................................................................................................. 32 6.3 Precautions for Use Environment ................................................................................................................................ 33 7. Handling Devices ............................................................................................................................................................ 34 8. Block Diagram ................................................................................................................................................................. 36 9. Memory Size .................................................................................................................................................................... 36 10. Memory Map .................................................................................................................................................................... 37 11. Pin Status in Each CPU State ........................................................................................................................................ 40 12. Electrical Characteristics ............................................................................................................................................... 45 12.1 Absolute Maximum Ratings ......................................................................................................................................... 45 12.2 Recommended Operating Conditions ......................................................................................................................... 47 12.3 DC Characteristics ...................................................................................................................................................... 48 12.3.1 Current Rating .............................................................................................................................................................. 48 12.3.2 Pin Characteristics ....................................................................................................................................................... 51 12.4 AC Characteristics ....................................................................................................................................................... 52 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 52 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 53 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 54 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL) ......................................... 55 12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL) .............. 55 12.4.6 Reset Input Characteristics .......................................................................................................................................... 56 12.4.7 Power-on Reset Timing ................................................................................................................................................ 56 12.4.8 Base Timer Input Timing .............................................................................................................................................. 57 12.4.9 CSIO/UART Timing ...................................................................................................................................................... 58 12.4.10 External Input Timing ................................................................................................................................................ 66 12.4.11 I2C Timing ................................................................................................................................................................. 67 12.4.12 JTAG Timing............................................................................................................................................................. 68 12.5 12-bit A/D Converter .................................................................................................................................................... 69 12.6 10-bit D/A Converter .................................................................................................................................................... 72 12.7 Low-Voltage Detection Characteristics ........................................................................................................................ 73 12.7.1 Low-Voltage Detection Reset ....................................................................................................................................... 73 12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 74 12.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 75 12.8.1 Write / Erase time......................................................................................................................................................... 75 12.8.2 Write cycles and data hold time ................................................................................................................................... 75 12.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 76 12.9.1 Return Factor: Interrupt ................................................................................................................................................ 76 12.9.2 Return Factor: Reset .................................................................................................................................................... 78 13. Ordering Information ...................................................................................................................................................... 80 14. Package Dimensions ...................................................................................................................................................... 81 15. Major Changes ................................................................................................................................................................ 87 Document Number: 002-05669 Rev. *C Page 4 of 90 CY9A120L Series Document History ................................................................................................................................................................. 89 Sales, Solutions, and Legal Information ............................................................................................................................. 90 Document Number: 002-05669 Rev. *C Page 5 of 90 CY9A120L Series 1. Product Lineup Memory Size Product name CY9AF121K/L On-chip Flash memory 64 Kbytes On-chip SRAM 4 Kbytes SRAM1 Function Product name Pin count CPU Freq. Power supply voltage range Multi-function Serial Interface (UART/CSIO/LIN/I2C) Base Timer (PWC/Reload timer/PWM/PPG) A/D activation 1 ch. compare Input capture 3 ch. Free-run timer 3 ch. MFOutput compare 6 ch. Timer Waveform 3 ch. generator PPG 3 ch. (IGBT mode) Dual Timer Real-Time Clock Watchdog timer External Interrupts I/O ports 12-bit A/D converter 10-bit D/A converter CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in CR Low-speed Debug Function Unique ID CY9AF121K 48/52 Cortex-M3 40 MHz 2.7 V to 5.5 V 4 ch. (Max) ch.0, ch.1, ch.3, ch.5: No FIFO (In ch.5, only UART and LIN are available.) CY9AF121L 64 4 ch. (Max) ch.0, ch.1, ch.3, ch.5: No FIFO 8 ch. (Max) 1 unit 1 unit 1 unit 1 ch. (SW) + 1 ch. (HW) 14 pins (Max) + NMI × 1 36 pins (Max) 8 ch. (1 unit) 1 ch. (Max) Yes 2 ch. 4 MHz 100 kHz SWJ-DP Yes 19 pins (Max) + NMI × 1 51 pins (Max) Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 12.4 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: 002-05669 Rev. *C Page 6 of 90 CY9A120L Series 2. Packages Product name Package LQFP: QFN: LQFP: LQFP: LQFP: QFN: LQA048 (0.5 mm pitch) WNY048 (0.5 mm pitch) LQC052 (0.65 mm pitch) LQD064 (0.5 mm pitch) LQG064 (0.65 mm pitch) WNS064 (0.5 mm pitch) CY9AF121K    - CY9AF121L    : Supported Note: − See Package Dimensions for detailed information on each package. Document Number: 002-05669 Rev. *C Page 7 of 90 CY9A120L Series 3. Pin Assignment LQD064/ LQG064 P0C/TIOA6_1/INT19_0 P0A/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 54 53 52 51 50 49 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 57 P0B/TIOB6_1/INT18_0 P62/SCK5_0/ADTG_3 58 55 P61/SOT5_0/TIOB2_2/DTTI0X_2 59 56 P80/INT16_1 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 P81/INT17_1 62 60 P82 63 61 VSS 64 (TOP VIEW) VCC 1 48 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 47 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 46 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 45 P19 P30/TIOB0_1/INT03_2 5 44 P18 P31/TIOB1_1/INT04_2 6 43 AVRL P32/TIOB2_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/INT06_0/ADTG_2 9 40 P17/INT04_1 P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10 39 P15/AN05/SOT0_1/INT14_0/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/SIN0_1/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1/INT18_2 12 37 AVSS P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1/INT19_2 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00/SCK1_1 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SOT3_2/INT20_1/DA0_0 P4A/TIOB1_0/SCK3_2/INT21_1 P4B/TIOB2_0/INT22_1/IGTRG_0 P4C/TIOB3_0/INT12_0 P4D/TIOB4_0/INT13_0 P4E/TIOB5_0/INT06_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP- 64 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05669 Rev. *C Page 8 of 90 CY9A120L Series WNS064 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 52 51 50 49 57 P0A/INT00_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 58 53 P62/SCK5_0/ADTG_3 59 54 P61/SOT5_0/TIOB2_2/DTTI0X_2 60 P0C/TIOA6_1/INT19_0 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 61 P0B/TIOB6_1/INT18_0 P80/INT16_1 62 55 P81/INT17_1 63 56 VSS P82 64 (TOP VIEW) VCC 1 48 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 47 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 46 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 45 P19 P30/TIOB0_1/INT03_2 5 44 P18 P31/TIOB1_1/INT04_2 6 43 AVRL P32/TIOB2_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/INT06_0/ADTG_2 9 40 P17/INT04_1 P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10 39 P15/AN05/SOT0_1/INT14_0/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/SIN0_1/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1/INT18_2 12 37 AVSS P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1/INT19_2 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00/SCK1_1 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SOT3_2/INT20_1/DA0_0 P4A/TIOB1_0/SCK3_2/INT21_1 P4B/TIOB2_0/INT22_1/IGTRG_0 P4C/TIOB3_0/INT12_0 P4D/TIOB4_0/INT13_0 P4E/TIOB5_0/INT06_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN- 64 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05669 Rev. *C Page 9 of 90 CY9A120L Series LQA048 VCC P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 40 39 38 37 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/TDO/SWO 42 41 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 P61/SOT5_0/TIOB2_2/DTTI0X_2 44 43 P81/INT17_1 P80/INT16_1 46 45 VSS P82 48 47 (TOP VIEW) 1 36 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 35 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 34 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 33 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2 VSS 12 25 P10/AN00/SCK1_1 21 22 23 24 MD0 PE3/X1 VSS PE0/MD1 PE2/X0 19 20 P4A/TIOB1_0/INT21_1 17 18 INITX 15 16 P46/X0A P47/X1A P49/TIOB0_0/INT20_1/DA0_0 13 14 C VCC LQFP- 48 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05669 Rev. *C Page 10 of 90 CY9A120L Series WNY048 P02/TDI P00/TRSTX 37 P03/TMS/SWDIO 40 P01/TCK/SWCLK P04/TDO/SWO 41 38 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 42 39 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 P80/INT16_1 45 P61/SOT5_0/TIOB2_2/DTTI0X_2 P81/INT17_1 46 43 P82 47 44 VSS 48 (TOP VIEW) VCC 1 36 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 35 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 34 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 33 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2 VSS 12 25 P10/AN00/SCK1_1 13 14 15 16 17 18 19 20 21 22 23 24 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/INT20_1/DA0_0 P4A/TIOB1_0/INT21_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN- 48 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05669 Rev. *C Page 11 of 90 CY9A120L Series LQC052 P80/INT16_1 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 P61/SOT5_0/TIOB2_2/DTTI0X_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX NC 47 46 45 44 43 42 41 40 P81/INT17_1 50 48 P82 51 49 VSS 52 (TOP VIEW) VCC 1 39 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 38 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 37 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 36 NC NC 5 35 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 6 34 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 7 33 AVCC P3B/RTO01_0/TIOA1_1 8 32 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 9 31 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 10 30 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 11 29 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 12 28 P11/AN01/SIN1_1/INT02_1/FRCK0_2 VSS 13 27 P10/AN00/SCK1_1 14 15 16 17 18 19 20 21 22 23 24 25 26 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/INT20_1/DA0_0 P4A/TIOB1_0/INT21_1 NC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP- 52 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05669 Rev. *C Page 12 of 90 CY9A120L Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-52 1 1 1 2 2 2 3 3 3 4 4 4 5 - - 6 - - 7 - - 8 - - 9 6 5 10 7 6 11 8 7 Document Number: 002-05669 Rev. *C I/O circuit type Pin Name VCC P50 INT00_0 SIN3_1 P51 INT01_0 SOT3_1 (SDA3_1) P52 INT02_0 SCK3_1 (SCL3_1) P30 TIOB0_1 INT03_2 P31 TIOB1_1 INT04_2 P32 TIOB2_1 INT05_2 P33 INT04_0 TIOB3_1 ADTG_6 P39 DTTI0X_0 INT06_0 ADTG_2 P3A RTO00_0 (PPG00_0) TIOA0_1 INT07_0 SUBOUT_2 RTCCO_2 P3B RTO01_0 (PPG00_0) TIOA1_1 Pin state type H*1 K H*2 K H*2 K E K E K E K E K E K G K G J Page 13 of 90 CY9A120L Series Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-52 12 9 8 13 10 9 14 11 10 15 12 11 16 17 18 13 14 15 12 13 14 19 16 15 20 17 16 21 18 17 19 18 22 - - 20 19 23 - - 24 - - 25 - - 26 - - Document Number: 002-05669 Rev. *C I/O circuit type Pin Name P3C RTO02_0 (PPG02_0) TIOA2_1 INT18_2 P3D RTO03_0 (PPG02_0) TIOA3_1 P3E RTO04_0 (PPG04_0) TIOA4_1 INT19_2 P3F RTO05_0 (PPG04_0) TIOA5_1 VSS C VCC P46 X0A P47 X1A INITX P49 TIOB0_0 INT20_1 DA0_0 SOT3_2 (SDA3_2) P4A TIOB1_0 INT21_1 SCK3_2 (SCL3_2) P4B TIOB2_0 INT22_1 IGTRG_0 P4C TIOB3_0 INT12_0 P4D TIOB4_0 INT13_0 Pin state type G K G J G K G J D F D G B C K K E K E K E K E K Page 14 of 90 CY9A120L Series Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-52 27 - - 28 22 20 29 23 21 30 24 22 31 25 23 32 33 26 - 24 - 34 27 25 35 28 26 36 29 27 37 30 28 38 31 29 39 32 30 40 - - 41 42 43 44 45 33 34 35 - 31 32 33 - Document Number: 002-05669 Rev. *C I/O circuit type Pin Name P4E TIOB5_0 INT06_2 PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 AN00 SCK1_1 (SCL1_1) P11 AN01 SIN1_1 INT02_1 FRCK0_2 P12 AN02 SOT1_1 (SDA1_1) IC00_2 AVSS P14 AN04 SIN0_1 INT03_1 IC02_2 P15 AN05 SOT0_1 (SDA0_1) INT14_0 IC03_2 P17 INT04_1 AVCC AVRH AVRL P18 P19 Pin state type E K C E J D A A A B F L F M F L - F M F M E K E E J J Page 15 of 90 CY9A120L Series Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-52 46 37 34 47 38 35 48 39 36 49 41 37 50 42 38 51 43 39 52 44 40 53 45 41 54 - - 55 - - 56 - - 57 46 42 58 - - Document Number: 002-05669 Rev. *C Pin Name P23 AN12 SCK0_0 (SCL0_0) TIOA7_1 P22 AN13 SOT0_0 (SDA0_0) TIOB7_1 P21 AN14 SIN0_0 INT06_1 P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P0A INT00_2 P0B TIOB6_1 INT18_0 P0C TIOA6_1 INT19_0 P0F NMIX SUBOUT_0 CROUT_1 RTCCO_0 P62 SCK5_0 (SCL5_0) ADTG_3 I/O circuit type Pin state type I*2 M I*2 M I*1 M E I E I E I E I E I E K E K E K E H E J Page 16 of 90 CY9A120L Series Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-52 59 47 43 60 48 44 61 49 45 62 50 46 63 64 - 51 52 5, 21, 36, 40 47 48 - Pin Name P61 SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 P60 SIN5_0 TIOA2_2 INT15_1 IGTRG_1 P80 INT16_1 P81 INT17_1 P82 VSS NC I/O circuit type Pin state type E J I*2 K L K L K L - J *1: 5 V tolerant I/O, without PZR function *2: 5 V tolerant I/O, with PZR function Document Number: 002-05669 Rev. *C Page 17 of 90 CY9A120L Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Debugger Pin No Pin name ADTG_2 ADTG_3 ADTG_6 AN00 AN01 AN02 AN04 AN05 AN12 AN13 AN14 TIOA0_1 TIOB0_0 TIOB0_1 TIOA1_1 TIOB1_0 TIOB1_1 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_1 TIOB3_0 TIOB3_1 TIOA4_1 TIOB4_0 TIOA5_1 TIOB5_0 TIOA6_1 TIOB6_1 TIOA7_1 TIOB7_1 SWCLK SWDIO SWO TCK TDI TDO TMS TRSTX Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin JTAG test reset input pin Document Number: 002-05669 Rev. *C LQFP-64 QFN-64 LQFP-52 LQFP-48 QFN-48 9 58 8 34 35 36 38 39 46 47 48 10 22 5 11 23 6 12 60 24 7 59 13 25 8 14 26 15 27 56 55 46 47 50 6 27 28 29 31 32 37 38 39 7 19 8 20 9 48 47 10 11 12 37 38 42 5 25 26 27 29 30 34 35 36 6 18 7 19 8 44 43 9 10 11 34 35 38 52 44 40 53 50 51 53 52 49 45 42 43 45 44 41 41 38 39 41 40 37 Page 18 of 90 CY9A120L Series Pin function External Interrupt Pin No Pin name INT00_0 INT00_2 INT01_0 INT02_0 INT02_1 INT03_1 INT03_2 Function description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin INT04_0 INT04_1 External interrupt request 04 input pin INT04_2 INT05_2 External interrupt request 05 input pin INT06_0 INT06_1 External interrupt request 06 input pin INT06_2 LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-52 2 2 2 54 - - 3 3 3 4 4 4 35 28 26 38 31 29 5 - - 8 - - 40 - - 6 - - 7 - - 9 6 5 48 39 36 27 - - INT07_0 External interrupt request 07 input pin 10 7 6 INT12_0 External interrupt request 12 input pin 25 - - INT13_0 External interrupt request 13 input pin 26 - - INT14_0 External interrupt request 14 input pin 39 32 30 INT15_1 External interrupt request 15 input pin 60 48 44 INT16_1 External interrupt request 16 input pin 61 49 45 INT17_1 External interrupt request 17 input pin 62 50 46 55 - - 12 9 8 56 - - 14 11 10 INT18_0 INT18_2 INT19_0 INT19_2 External interrupt request 18 input pin External interrupt request 19 input pin INT20_1 External interrupt request 20 input pin 22 19 18 INT21_1 External interrupt request 21 input pin 23 20 19 INT22_1 External interrupt request 22 input pin 24 - - NMIX Non-Maskable Interrupt input pin 57 46 42 Document Number: 002-05669 Rev. *C Page 19 of 90 CY9A120L Series Pin function GPIO Pin No Pin name P00 P01 P02 P03 P04 P0A P0B P0C P0F P10 P11 P12 P14 P15 P17 P18 P19 P21 P22 P23 P30 P31 P32 P33 P39 P3A P3B P3C P3D P3E P3F P46 P47 P49 P4A P4B P4C P4D P4E P50 P51 P52 P60 P61 P62 P80 P81 P82 PE0 PE2 PE3 Function description General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Document Number: 002-05669 Rev. *C LQFP-64 QFN-64 49 50 51 52 53 54 55 56 57 34 35 36 38 39 40 44 45 48 47 46 5 6 7 8 9 10 11 12 13 14 15 19 20 22 23 24 25 26 27 2 3 4 60 59 58 61 62 63 28 30 31 LQFP-52 41 42 43 44 45 46 27 28 29 31 32 39 38 37 6 7 8 9 10 11 12 16 17 19 20 2 3 4 48 47 49 50 51 22 24 25 LQFP-48 QFN-48 37 38 39 40 41 42 25 26 27 29 30 36 35 34 5 6 7 8 9 10 11 15 16 18 19 2 3 4 44 43 45 46 47 20 22 23 Page 20 of 90 CY9A120L Series Pin function Multifunction Serial 0 Pin No Pin name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Multifunction Serial 1 SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) Multifunction Serial 3 SIN3_1 SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Function description Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation mode 2) and as SCL3 when it is used in an I2C (operation mode 4). Document Number: 002-05669 Rev. *C LQFP-64 QFN-64 48 38 39 31 LQFP-48 QFN-48 36 29 47 38 35 39 32 30 46 37 34 35 28 26 36 29 27 34 27 25 2 2 2 3 3 3 22 - - 4 4 4 23 - - LQFP-52 Page 21 of 90 CY9A120L Series Pin function Multifunction Serial 5 Pin No Pin name SIN5_0 SOT5_0 (SDA5_0) SCK5_0 (SCL5_0) Multifunction Timer 0 DTTI0X_0 DTTI0X_2 FRCK0_2 IC00_2 IC02_2 IC03_2 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) Function description Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 16-bit input capture input pin of Multi-function timer 0. ICxx describes channel number. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. LQFP-64 QFN-64 60 48 LQFP-48 QFN-48 44 59 47 43 58 - - 9 6 5 59 47 43 35 28 26 36 38 39 29 31 32 27 29 30 10 7 6 11 8 7 LQFP-52 RTO02_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 12 9 8 RTO03_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 13 10 9 RTO04_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 14 11 10 RTO05_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 15 12 11 IGTRG_0 IGTRG_1 PPG IGBT mode external trigger input pin 24 60 48 44 Document Number: 002-05669 Rev. *C Page 22 of 90 CY9A120L Series Pin function Real-time clock DAC Reset Pin No Pin name RTCCO_0 RTCCO_2 SUBOUT_0 SUBOUT_2 DA0_0 INITX Mode MD0 MD1 Function description 0.5 seconds pulse output pin of Real-time clock Sub clock output pin D/A converter ch.0 analog output pin External Reset Input pin. A reset is valid when INITX="L". Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Power Analog Power 21 18 17 29 23 21 28 22 20 1 15 13 26 52 24 16 25 17 1 14 12 24 48 22 15 23 16 Power supply Pin VSS GND Pin X0 X0A X1 X1A Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin 1 18 33 16 32 64 30 19 31 20 CROUT_1 Built-in high-speed CR-osc clock output port 57 46 42 41 33 31 42 34 32 37 30 28 43 35 33 AVCC AVRH Analog GND 46 7 46 7 19 LQFP-48 QFN-48 42 6 42 6 18 LQFP-52 VCC GND Clock LQFP-64 QFN-64 57 10 57 10 22 AVSS AVRL A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin A/D converter and D/A converter GND pin A/D converter analog reference voltage input pin Power supply stabilization capacity pin C pin C 17 14 13 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05669 Rev. *C Page 23 of 90 CY9A120L Series 5. I/O Circuit Type Type A Circuit Remarks It is possible to select the main oscillation / GPIO function Pull-up When the main oscillation is selected. resistor • Oscillation feedback resistor : Approximately 1 MΩ • With Standby mode control P-ch P-ch Digital output X1A When the GPIO is selected. N-ch Digital output R Pull-up resistor control • • • • • CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH= -4 mA, IOL= 4 mA Digital input Standby mode control Clock input Feedback resistor Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control Document Number: 002-05669 Rev. *C Page 24 of 90 CY9A120L Series Type B Circuit Remarks • CMOS level hysteresis input • Pull-up resistor : Approximately 50 kΩ Pull-up resistor Digital input C Digital input N-ch Document Number: 002-05669 Rev. *C • Open drain output • CMOS level hysteresis input Digital output Page 25 of 90 CY9A120L Series Type D Circuit Remarks It is possible to select the sub oscillation / GPIO function Pull-up resistor P-ch When the sub oscillation is selected. P-ch Digital output X1A • Oscillation feedback resistor : Approximately 5 MΩ • With Standby mode control When the GPIO is selected. N-ch Digital output R Pull-up resistor control • • • • • CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH= -4 mA, IOL= 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control Document Number: 002-05669 Rev. *C Page 26 of 90 CY9A120L Series Type E Circuit Remarks • • • • • P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH= -4 mA, IOL= 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off • +B input is available R Pull-up resistor control Digital input Standby mode control F P-ch P-ch N-ch R Digital output Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH= -4 mA, IOL= 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off • +B input is available Pull-up resistor control Digital input Standby mode control Analog input Input control Document Number: 002-05669 Rev. *C Page 27 of 90 CY9A120L Series Type G Circuit Remarks • • • • • P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH= -12 mA, IOL= 12 mA • +B input is available Digital output R Pull-up resistor control Digital input Standby mode control Digital output • • • • • • Digital output • • • • H P-ch P-ch N-ch R CMOS level output CMOS level hysteresis input 5 V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -4 mA, IOL= 4 mA Available to control PZR registers. Only P51, P52. When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Document Number: 002-05669 Rev. *C Page 28 of 90 CY9A120L Series Type I Circuit P-ch Remarks P-ch N-ch R Digital output Digital output • • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input 5 V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH= -4 mA, IOL= 4 mA • Available to control PZR registers. Only P23, P22, P60. • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Analog input Input control J CMOS level hysteresis input Mode input Document Number: 002-05669 Rev. *C Page 29 of 90 CY9A120L Series Type K Circuit P-ch Remarks P-ch N-ch Digital output Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control R Digital input Standby mode control Analog output • • • • L P-ch N-ch CMOS level output CMOS level hysteresis input With standby mode control IOH= -4 mA, IOL= 4 mA Digital output Digital output R Digital input Standby mode control Document Number: 002-05669 Rev. *C Page 30 of 90 CY9A120L Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-05669 Rev. *C Page 31 of 90 CY9A120L Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-05669 Rev. *C Page 32 of 90 CY9A120L Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05669 Rev. *C Page 33 of 90 CY9A120L Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin, between AVRH pin and AVRL pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. • Surface mount type Size: Load capacitance: • Lead type Load capacitance: More than 3.2 mm × 1.5 mm Approximately 6 pF to 7 pF Approximately 6 pF to 7 pF Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. Document Number: 002-05669 Rev. *C X1(PE3), X1A (P47) Set as External clock input Page 34 of 90 CY9A120L Series Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC → AVCC → AVRH Turning off : AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Document Number: 002-05669 Rev. *C Page 35 of 90 CY9A120L Series 8. Block Diagram CY9AF121K/L TRSTX,TCK, TDI,TMS TDO SWJ-DP ROM Table Multi-layer AHB (Max 40MHz) Cortex-M3 Core I @40MHz (Max) D NVIC Sys AHB-APB Bridge : APB0(Max 40MHz) Dual-Timer WatchDog Timer ( Software) INITX Clock Reset Generator WatchDog Timer ( Hardware ) SRAM1 4 Kbytes Flash I/F Security On- Chip Flash 64 Kbytes CSV CLK X0 X1 X0A X1A CROUT AVCC, AVSS, AVRH, AVRL ANxx Main Osc Sub Osc Source clock PLL CR 4 MHz CR 100kHz 12- bit A /D Converter Unit 0 ADTG_x T IOBx Base Timer 16 -bit 8ch./ 32 -bit 4ch. A /D Activation Compare 1ch. IC0x 16 - bit Input Capture 3ch. FRCKx 16- bit Free-run Timer 3ch. 16 - bit Output Compare 6ch. DTTI0X RTO0x LVD Regulator AHB-APB Bridge : APB2 (Max 40MHz) TIOAx LVD Ctrl AHB-APB Bridge : APB1 (Max 40MHz) DAx Power-On Reset 10-bit D/A Converter 1 units Waveform Generator 3ch. C IRQ - Monitor Real -Time Colck RTCCO_x, SUBOUT_ x External Interrupt Controller 19 pin + NMI INTx NMIX MD0, MD1 P0x, P1x, MODE-Ctrl GPIO PIN- Function-Ctrl ・ ・ ・ Pxx Multi - function Serial I /F 4ch. ( without FIFO ch.0/1/3/5) SCKx SINx SOTx IGTRG_x 16- bit PPG 3ch. Multi -function Timer 9. Memory Size See Memory size in Product Lineup to confirm the memory size. Document Number: 002-05669 Rev. *C Page 36 of 90 CY9A120L Series 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved 0x6000_0000 Reserved 0x4400_0000 0x4200_0000 0x4000_0000 0x2400_0000 0x2200_0000 0x2008_0000 0x2000_0000 0x1FF8_0000 See "  Memory Map (2)" for the memory size details. 0x0020_8000 0x0020_0000 0x0010_0008 0x0010_0000 32Mbytes Bit band alias Peripherals Reserved 32Mbytes Bit band alias Reserved SRAM1 Reserved Reserved Reserved Reserved Security/CR Trim Flash 0x4006_4000 0x4006_3000 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 0x4003_C000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_7000 0x4003_6000 0x4003_5800 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4002_9000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 Reserved Reserved Reserved Reserved Reserved RTC Reserved Reserved MFS Reserved Reserved Reserved LVD Reserved GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved D/AC A/DC Reserved Base Timer PPG Reserved 0x4002_1000 0x4002_0000 MFT unit0 0x4001_6000 0x4001_5000 Dual Timer 0x0000_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 002-05669 Rev. *C Reserved Reserved Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F Page 37 of 90 CY9A120L Series Memory Map (2) *: See CY9A420L/120L/CY9B120J Series Flash Programming Manual to confirm the detail of Flash memory. Document Number: 002-05669 Rev. *C Page 38 of 90 CY9A120L Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Resister 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF 0x4006_1000 0x4006_2FFF 0x4006_3000 0x4006_3FFF Reserved 0x4006_4000 0x41FF_FFFF Reserved Document Number: 002-05669 Rev. *C AHB APB0 APB1 APB2 AHB Flash Memory I/F register Reserved Software Watchdog timer Reserved Reserved A/D Converter Reserved Reserved Reserved Reserved Page 39 of 90 CY9A120L Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled. Document Number: 002-05669 Rev. *C Page 40 of 90 CY9A120L Series Pin status type List of Pin Status A Function group Power-on reset or low-voltage detection state Power supply unstable - INITX input state Device internal reset state Power supply stable INITX = 0 - INITX = 1 - Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 - SPL = 0 INITX = 1 SPL = 1 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 B Main crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled E Document Number: 002-05669 Rev. *C Page 41 of 90 Pin status type CY9A120L Series F Function group Power-on reset or low-voltage detection state Power supply unstable - INITX input state Device internal reset state Power supply stable INITX = 0 - INITX = 1 - Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 - SPL = 0 INITX = 1 SPL = 1 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state/When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z / Internal input fixed at 0 NMIX selected Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Pull-up / Input enabled Pull-up / Input enabled G H Resource other than above selected Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected JTAG selected Maintain previous state Maintain previous state I GPIO selected Setting disabled Document Number: 002-05669 Rev. *C Setting disabled Setting disabled Maintain previous state Hi-Z / Internal input fixed at 0 Page 42 of 90 Pin status type CY9A120L Series Function group Power-on reset or low-voltage detection state Power supply unstable - INITX input state Device internal reset state Power supply stable Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 0 - INITX = 1 - INITX = 1 - SPL = 0 INITX = 1 SPL = 1 Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Setting disabled Setting disabled Setting disabled Resource selected J GPIO selected K External interrupt enabled selected Resource other than above selected Maintain previous state Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled L Resource other than above selected GPIO selected Analog input selected M Maintain previous state Hi-Z GPIO selected Analog input selected Maintain previous state Hi-Z / Internal input fixed at 0 External interrupt enabled selected Resource other than above selected Maintain previous state Setting disabled GPIO selected Document Number: 002-05669 Rev. *C Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Page 43 of 90 Pin status type CY9A120L Series N Function group Power-on reset or low-voltage detection state INITX input state Power supply unstable - Device internal reset state Power supply stable INITX = 0 - INITX = 1 - Analog output selected Setting disabled Setting disabled Setting disabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 - INITX = 1 SPL = 0 *3 SPL = 1 *4 Maintain previous state Maintain previous state Resource other than above selected Maintain previous state Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode. *2: Oscillation is stopped at Stop mode. *3: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *4: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode. Document Number: 002-05669 Rev. *C Page 44 of 90 CY9A120L Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage*1, *2 Analog power supply voltage*1, *3 Analog reference voltage*1, *3 VCC AVCC AVRH Input voltage*1 VI Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 Analog pin input voltage*1 VIA VSS - 0.5 Output voltage*1 VO VSS - 0.5 Clamp maximum current Clamp total maximum current ICLAMP Σ[ICLAMP] -2 L level maximum output current*4 IOL - L level average output current*5 IOLAV - L level total maximum output current L level total average output current*6 ∑IOL ∑IOLAV - H level maximum output current*4 IOH - H level average output current*5 IOHAV - H level total maximum output current H level total average output current*6 Power consumption Storage temperature ∑IOH ∑IOHAV PD TSTG - 55 Max VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5 V) VSS + 6.5 AVCC + 0.5 (≤ 6.5 V) VCC + 0.5 (≤ 6.5 V) +2 +20 10 20 4 12 100 50 - 10 - 20 -4 - 12 - 100 - 50 350 + 150 Unit Remarks V V V V V 5 V tolerant V V mA mA *7 *7 mA mA mA mA mA mA mA mA mA mA mA mA mW °C 4 mA type 12 mA type 4 mA type 12 mA type 4 mA type 12 mA type 4 mA type 12 mA type *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. Document Number: 002-05669 Rev. *C Page 45 of 90 CY9A120L Series *7: • • • • • See List of Pin Functions and I/O Circuit Type about +B input available pin. Use within recommended operating conditions. Use at DC voltage (current) the +B input. The +B signal should always be applied a limiting resistance placed between the +B signal and the device. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices. • Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • The following is a recommended circuit example (I/O equivalent circuit). Protection Diode VCC VCC P-ch Limiting resistor Digital output +B input (0V to 16V) N-ch Digital input R AVCC Analog input WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-05669 Rev. *C Page 46 of 90 CY9A120L Series 12.2 Recommended Operating Conditions (VSS = AVSS = AVRL = 0.0V) Parameter Power supply voltage Analog power supply voltage Analog reference voltage Smoothing capacitor LQG064, LQC052, Operating LQD064, temperature LQA048, WNS064, WNY048 Symbol VCC AVCC AVRH AVRL CS TA Conditions When mounted on four-layer PCB When mounted on double-sided single-layer PCB Value Min Max 2.7*2 5.5 2.7 5.5 2.7 AVCC AVSS AVSS 1 10 Unit V V V V μF - 40 + 105 °C - 40 + 85 °C Remarks AVCC = VCC For Regulator*1 *1: See C Pin in Handling Devices for the connection of the smoothing capacitor. *2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions, or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-05669 Rev. *C Page 47 of 90 CY9A120L Series 12.3 DC Characteristics 12.3.1 Current Rating (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Pin name Symbol Conditions PLL Run mode Run mode current ICC VCC Sleep mode current ICCS High-speed CR Run mode Sub Run mode Low-speed CR Run mode PLL Sleep mode High-speed CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode Value Unit Remarks Typ Max 15.5 16 mA *1, *5 9 10.6 mA *1, *5 14 15 mA *1 CPU/ Peripheral: 4 MHz*2 Instruction on Flash 1.7 3.0 mA *1 CPU/ Peripheral: 32 kHz Instruction on Flash 63 900 μA *1, *6 CPU/ Peripheral: 100 kHz Instruction on Flash 88 920 μA *1 Peripheral: 40 MHz 9 12 mA *1, *5 Peripheral: 4 MHz*2 1 2.1 mA *1 Peripheral: 32 kHz 58 880 μA *1, *6 Peripheral: 100 kHz 71 890 μA *1 CPU: 40 MHz, Peripheral: 40 MHz Instruction on Flash CPU: 40 MHz, Peripheral: the clock stops NOP operation Instruction on Flash CPU: 40 MHz, Peripheral: 40 MHz Instruction on RAM *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=5.5 V *4: TA=+105°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) Document Number: 002-05669 Rev. *C Page 48 of 90 CY9A120L Series (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Pin name Symbol Conditions Main Timer mode ICCT Timer mode current Sub Timer mode ICCT VCC RTC mode current ICCR Stop mode current ICCH RTC mode Stop mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off Value Typ Max Unit 1.8 2.1 mA *1 - 2.7 mA *1 13 44 μA *1 - 730 μA *1 10 38 μA *1 - 570 μA *1 9 32 μA *1 - 540 μA *1 Remarks *1: When all ports are fixed. *2: VCC=5.5 V *3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) LVD current Parameter Low-Voltage detection circuit (LVD) power supply current Symbol ICCLVD Pin name VCC (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Value Conditions Unit Remarks Typ Max At operation for reset 0.13 0.3 μA At not detect Vcc = 5.5 V At operation for interrupt 0.13 0.3 μA At not detect Vcc = 5.5 V Flash memory current Parameter Flash memory write/erase current Symbol ICCFLASH Pin name VCC Document Number: 002-05669 Rev. *C (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Value Conditions Unit Remarks Typ Max At Write/Erase 9.5 11.2 mA Page 49 of 90 CY9A120L Series A/D convertor current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Power supply current ICCAD AVCC Reference power supply current ICCAVRH AVRH Conditions Value Unit Remarks At operation At stop Typ 0.7 0.13 Max 0.9 13 At operation 1.1 1.97 mA AVRH=5.5V At stop 0.1 1.7 μA AVRH=5.5V mA μA D/A convertor current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name IDDA Power supply current AVCC IDSA Value Conditions At operation AVCC = 3.3 V At operation AVCC = 5.0 V At stop Unit Remarks Typ Max 315 380 μA * 475 580 μA * - 8 μA * *: No-load Document Number: 002-05669 Rev. *C Page 50 of 90 CY9A120L Series 12.3.2 Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) Symbol VIHS VILS Pin name CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin 4mA type H level output voltage VOH 12mA type 4mA type L level output voltage VOL 12mA type Input leak current IIL Pull-up resistance value RPU Input capacitance CIN - Conditions Value Typ Max - VCC × 0.8 - VCC + 0.3 V - VCC × 0.8 - VSS + 5.5 V - VSS - 0.3 - VCC × 0.2 V - VSS - 0.3 - VCC × 0.2 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VSS - 0.4 V VSS - 0.4 V -5 - +5 μA VCC ≥ 4.5 V 33 50 90 VCC < 4.5 V - - 180 - 5 15 VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 2 mA VCC ≥ 4.5 V, IOH = - 12 mA VCC < 4.5 V, IOH = - 8 mA VCC ≥ 4.5 V, IOL = 4 mA VCC < 4.5 V, IOL = 2 mA VCC ≥ 4.5 V, IOL = 12 mA VCC < 4.5 V, IOL = 8 mA - Pull-up pin Other than VCC, VSS, AVCC, AVSS, AVRH, AVRL Document Number: 002-05669 Rev. *C Unit Min Remarks kΩ - pF Page 51 of 90 CY9A120L Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Input frequency Pin name X0, X1 tCYLH Input clock pulse width Input clock rising time and falling time tCF, tCR Internal operating clock frequency*1 Internal operating clock cycle time*1 Unit Remarks Max 4 4 48 20 MHz When crystal oscillator is connected - 4 48 MHz When using external Clock - 20.83 250 ns 45 55 % - - 5 ns PWH/tCYLH, PWL/tCYLH - Value Min VCC ≥ 4.5 V VCC < 4.5 V fCH Input clock cycle Conditions When using external Clock When using external Clock When using external Clock fCM - - - 40 MHz Master clock fCC fCP0 fCP1 fCP2 - - - 40 40 40 40 MHz MHz MHz MHz Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 tCYCC tCYCP0 tCYCP1 tCYCP2 - - 25 25 25 25 - ns ns ns ns Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 Document Number: 002-05669 Rev. *C Page 52 of 90 CY9A120L Series 12.4.2 Sub Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Input frequency Input clock cycle Input clock pulse width Symbol Pin name fCL tCYLL X0A, X1A - Conditions Value Unit Remarks Min Typ Max - - 32.768 - kHz - 32 - 100 kHz When crystal oscillator is connected When using external clock PWH/tCYLL, PWL/tCYLL 10 - 31.25 μs When using external clock 45 - 55 % When using external clock *: See Sub crystal oscillator in Handling Devices for the crystal oscillator used. X0A Document Number: 002-05669 Rev. *C Page 53 of 90 CY9A120L Series 12.4.3 Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions TA = + 25°C, 3.6 V < VCC ≤ 5.5 V Clock frequency fCRH TA =0°C to + 85°C, 3.6 V < VCC ≤ 5.5 V TA = - 40°C to + 105°C, 3.6 V < VCC ≤ 5.5 V TA = + 25°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 20°C to + 85°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 20°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 40°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 40°C to + 105°C Frequency stabilization time tCRWT Value Min Typ Max 3.92 4 4.08 3.9 4 4.1 3.88 4 4.12 3.94 4 4.06 3.92 4 4.08 3.9 4 4.1 3.88 4 4.12 2.8 4 5.2 - - 30 Unit Remarks When trimming*1 MHz - When not trimming μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming. *2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Clock frequency Symbol fCRL Document Number: 002-05669 Rev. *C Conditions - Value Min Typ Max 50 100 150 Unit Remarks kHz Page 54 of 90 CY9A120L Series 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Symbol Value Unit Min Typ Max tLOCK 100 - - μs fPLLI fPLLO fCLKPLL 4 5 75 - - 16 37 150 40 MHz multiplier MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Symbol Value Unit Min Typ Max tLOCK 100 - - μs fPLLI fPLLO fCLKPLL 3.8 19 72 - 4 - 4.2 35 150 40 MHz multiplier MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main PLL connection K divider PLL input clock PLL macro oscillation clock Main PLL M divider Main PLL clock (CLKPLL) N divider Document Number: 002-05669 Rev. *C Page 55 of 90 CY9A120L Series 12.4.6 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Reset input time 12.4.7 Pin name Symbol tINITX Value Conditions INITX - Min Max 500 - Unit Remarks ns Power-on Reset Timing (VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Power supply shut down time Pin name Value Conditions tOFF Min Typ Max 1 - - - Unit Remarks ms *1 Power ramp rate dV/dt Vcc:0.2 V to 2.7 V 1.2 1000 mV/μs *2 VCC Time until releasing Power-on tPRT 0.34 3.15 ms reset *1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6. 2.7V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST CPU Operation RST Active 0.2V tOFF release start Glossary VDH: detection voltage of Low Voltage detection reset. See “12.7 Low-Voltage Detection Characteristics” Document Number: 002-05669 Rev. *C Page 56 of 90 CY9A120L Series 12.4.8 Base Timer Input Timing Timer input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Input pulse width Symbol tTIWH, tTIWL Pin name Conditions TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger input timing Parameter Input pulse width Symbol tTRGH, tTRGL Pin name Conditions TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Value Unit Remarks Min Max 2tCYCP - ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. Document Number: 002-05669 Rev. *C Page 57 of 90 CY9A120L Series 12.4.9 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions VCC < 4.5 V Min Max - VCC ≥ 4.5 V Min Max Unit - 8 - 8 4tCYCP - 4tCYCP - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Master mode Slave mode Notes: − − − − The above characteristics apply to clock synchronous mode. − When the external load capacitance CL = 30 pF. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. Document Number: 002-05669 Rev. *C Page 58 of 90 CY9A120L Series tSCYC VOH SCK VOL VOL tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Master mode tSLSH SCK tSHSL VIH VIH tF VIL VIL VIH tR tSLOVE SOT VOH VOL tIVSHE SIN VIH VIL tSHIXE VIH VIL Slave mode Document Number: 002-05669 Rev. *C Page 59 of 90 CY9A120L Series CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK falling time SCK rising time tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5 V Min Max Conditions - VCC ≥ 4.5 V Min Max Unit - 8 - 8 4tCYCP - 4tCYCP - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Master mode Slave mode Notes: − − − − The above characteristics apply to clock synchronous mode. − When the external load capacitance CL = 30 pF. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. Document Number: 002-05669 Rev. *C Page 60 of 90 CY9A120L Series tSCYC VOH SCK VOH VOL tSHOVI VOH SOT VOL tIVSLI SIN tSLIXI VIH VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05669 Rev. *C Page 61 of 90 CY9A120L Series CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓→ SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓→ SIN hold time tSLIXE SCK falling time SCK rising time tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions VCC < 4.5 V Min Max - VCC ≥ 4.5 V Min Max Unit - 8 - 8 4tCYCP - 4tCYCP - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Master mode Slave mode Notes: − − − − The above characteristics apply to clock synchronous mode. − When the external load capacitance CL = 30 pF. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. Document Number: 002-05669 Rev. *C Page 62 of 90 CY9A120L Series tSCYC VOH SCK VOL SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH VIH SCK tR VOH VOL tIVSLE SIN VIL tF * SOT VIL tSHSL VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register Document Number: 002-05669 Rev. *C Page 63 of 90 CY9A120L Series CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Baud rate Serial clock cycle time tSCYC SCKx SCK ↓ → SOT delay time tSLOVI SCKx, SOTx SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI SOT → SCK ↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time tF tR SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions VCC < 4.5 V Min Max - VCC ≥ 4.5 V Min Max Unit - 8 - 8 4tCYCP - 4tCYCP - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Master mode Slave mode Notes: − − − − The above characteristics apply to clock synchronous mode. − When the external load capacitance CL = 30 pF. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. Document Number: 002-05669 Rev. *C Page 64 of 90 CY9A120L Series tSCYC VOH SCK VOH VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VIH VIL Master mode tR tF tSHSL SCK tSLSH VIH VIH VIL VIL VIL tSLOVE VOH VOL SOT VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time Value Conditions tSLSH tSHSL tF tR CL = 30 pF Min Max tCYCP + 10 tCYCP + 10 - 5 5 tR Document Number: 002-05669 Rev. *C VIL Remarks ns ns ns ns tF tSHSL SCK Unit VIH tSLSH VIH VIL VIL Page 65 of 90 CY9A120L Series 12.4.10 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Min Max Unit ADTG Input pulse width tINH, tINL FRCKx ICxx DTTIxX IGTRG INTxx, NMIX Remarks A/D converter trigger input - 2tCYCP*1 - ns *2 *3 2tCYCP*1 2tCYCP*1 2tCYCP + 100*1 500 - ns ns ns ns Free-run timer input clock Input capture Waveform enerator PPG IGBT mode External interrupt, NMI *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in stop mode, in RTC mode, in timer mode. Document Number: 002-05669 Rev. *C Page 66 of 90 CY9A120L Series 12.4.11 I2C Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter SCL clock frequency (Repeated) Start condition hold time SDA ↓ → SCL ↓ SCLclock L width SCLclock H width (Repeated) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between Stop condition and Start condition Noise filter Symbol Conditions fSCL Standard-mode Min Max 0 100 Fast-mode Min Max 0 400 Unit kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP*4 - 2 tCYCP*4 - ns tSUSTA tHDDAT tSP CL = 30 pF, R= (Vp/IOL)*1 - Remarks *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: 002-05669 Rev. *C Page 67 of 90 CY9A120L Series 12.4.12 JTAG Timing Parameter Symbol Pin name TMS, TDI setup time tJTAGS TCK, TMS, TDI TMS, TDI hold time tJTAGH TCK, TMS, TDI TDO delay time tJTAGD TCK, TDO Conditions VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Value Unit Remarks Min Max 15 - ns 15 - ns - 25 - 45 ns Note: − When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO Document Number: 002-05669 Rev. *C Page 68 of 90 CY9A120L Series 12.5 12-bit A/D Converter Electrical characteristics for the A/D converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage Full-scale transition voltage Symbol Pin name Value Unit VZT ANxx Min - Typ ± 2.0 ± 1.5 ±8 Max 12 ± 4.5 ± 2.5 ± 15 VFST ANxx - AVRH ± 8 AVRH ± 15 mV 0.8*1 - 10 1000 μs μs μs ns - Conversion time - - bit LSB LSB mV Sampling time*2 Compare clock cycle*3 State transition time to operation permission Analog input capacity tS tCCK - 1.0*1 0.24 40 tSTT - - - 1.0 μs CAIN - - - pF Analog input resistor RAIN - - - - - - 9.7 1.5 2.2 4 LSB Interchannel disparity Analog port input leak current Analog input voltage - Reference voltage - kΩ - ANxx - - 5 μA - ANxx AVRH AVRL AVRL 2.7 AVSS - AVRH AVCC AVSS V Remarks AVRH = 2.7 V to 5.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 4.5 V, HCLK=25 MHz sampling time: 240 ns, compare time: 560 ns AVCC < 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2). Document Number: 002-05669 Rev. *C Page 69 of 90 CY9A120L Series Comparator REXT ANxx Analog signal source RAIN CAIN (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: Input resistor of A/D = 1.3 kΩ at 4.5 V < AVCC < 5.5 V ch.0 to ch.2, ch.4, ch.5 Input resistor of A/D = 1.5 kΩ at 4.5 V < AVCC < 5.5 V ch.12 to ch.14 Input resistor of A/D = 1.9 kΩ at 2.7 V < AVCC < 4.5 V ch.0 to ch.2, ch.4, ch.5 Input resistor of A/D = 2.2 kΩ at 2.7 V < AVCC < 4.5 V ch.12 to ch.14 CAIN: Input capacity of A/D = 9.7 pF at 2.7 V < AVCC < 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-05669 Rev. *C Page 70 of 90 CY9A120L Series Definition of 12-bit A/D Converter Terms • Resolution: • Integral Nonlinearity: • Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Ideal characteristics (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVRL Actual conversion characteristics AVRH AVRL Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: V(N+1)T 0x(N-1) AVRH Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-05669 Rev. *C Page 71 of 90 CY9A120L Series 12.6 10-bit D/A Converter Electrical Characteristics for the D/A Converter Parameter Symbol Resolution - Integral Nonlinearity Differential Nonlinearity tC20 tC100 INL DNL Output Voltage offset VOFF Analog output impedance RO Output undefined period tR Conversion time (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Value Pin Unit Remarks name Min Typ Max DAx 0.47 2.37 - 4.0 - 0.9 - 20.0 3.10 2.0 - 0.58 2.90 3.80 - 10 0.69 3.43 + 4.0 + 0.9 10.0 + 5.4 4.50 70 bit μs μs LSB LSB mV mV kΩ MΩ ns Load 20 pF Load 100 pF * * Code is 0x000 Code is 0x3FF D/A operation D/A stop *: No-load Document Number: 002-05669 Rev. *C Page 72 of 90 CY9A120L Series 12.7 Low-Voltage Detection Characteristics 12.7.1 Low-Voltage Detection Reset (TA = - 40°C to + 105°C) Parameter Symbol Conditions Min Value Typ Max 2.25 2.45 2.65 V When voltage drops 2.30 2.50 2.70 V When voltage rises 2.39 2.60 2.81 V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises Unit Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH LVD stabilization wait time tLVDW - - - 8160 × tCYCP*2 μs LVD detection delay time tLVDDL - - - 200 μs SVHR*1 = 00000 SVHR*1 = 00001 SVHR*1 = 00010 SVHR*1 = 00011 SVHR*1 = 00100 SVHR*1 = 00101 SVHR*1 = 00110 SVHR*1 = 00111 SVHR*1 = 01000 SVHR*1 = 01001 SVHR*1 = 01010 Same as SVHR = 0000 value 2.48 2.70 2.92 Same as SVHR = 0000 value 2.58 2.80 3.02 Same as SVHR = 0000 value 2.76 3.00 3.24 Same as SVHR = 0000 value 2.94 3.20 3.46 Same as SVHR = 0000 value 3.31 3.60 3.89 Same as SVHR = 0000 value 3.40 3.70 4.00 Same as SVHR = 0000 value 3.68 4.00 4.32 Same as SVHR = 0000 value 3.77 4.10 4.43 Same as SVHR = 0000 value 3.86 4.20 4.54 Same as SVHR = 0000 value Remarks *1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low voltage detection reset. *2: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05669 Rev. *C Page 73 of 90 CY9A120L Series 12.7.2 Interrupt of Low-Voltage Detection (TA = - 40°C to + 105°C) Parameter Detected voltage Symbol Conditions VDL Min Value Typ Max 2.58 2.80 3.02 V When voltage drops 2.67 2.90 3.13 V When voltage rises 2.76 3.00 3.24 V When voltage drops 2.85 3.10 3.35 V When voltage rises 2.94 3.20 3.46 V When voltage drops 3.04 3.30 3.56 V When voltage rises 3.31 3.60 3.89 V When voltage drops 3.40 3.70 4.00 V When voltage rises 3.40 3.70 4.00 V When voltage drops 3.50 3.80 4.10 V When voltage rises 3.68 4.00 4.32 V When voltage drops 3.77 4.10 4.43 V When voltage rises 3.77 4.10 4.43 V When voltage drops 3.86 4.20 4.54 V When voltage rises 3.86 4.20 4.54 V When voltage drops 3.96 4.30 4.64 V When voltage rises Unit Remarks SVHI = 00011 Released voltage VDH Detected voltage VDL SVHI = 00100 Released voltage VDH Detected voltage VDL SVHI = 00101 Released voltage VDH Detected voltage VDL SVHI = 00110 Released voltage VDH Detected voltage VDL SVHI = 00111 Released voltage VDH Detected voltage VDL SVHI = 01000 Released voltage VDH Detected voltage VDL SVHI = 01001 Released voltage VDH Detected voltage VDL SVHI = 01010 Released voltage VDH LVD stabilization wait time tLVDW - - - 8160 × tCYCP* μs LVD detection delay time tLVDDL - - - 200 μs *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05669 Rev. *C Page 74 of 90 CY9A120L Series 12.8 Flash Memory Write/Erase Characteristics 12.8.1 Write / Erase time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Value Unit Remarks Typ Max Sector erase time 0.3 0.7 s Includes write time prior to internal erase Half word (16-bit) write time 16 282 μs Not including system-level overhead time Chip erase time 2.4 5.6 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write. 12.8.2 Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* 10,000 10* Remarks *: At average + 85C Document Number: 002-05669 Rev. *C Page 75 of 90 CY9A120L Series 12.9 Return Time from Low-Power Consumption Mode 12.9.1 Return Factor: Interrupt The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Value Typ Max* Unit μs tCYCC 43 83 μs 310 620 μs Sub Timer mode 534 724 μs RTC mode, Stop mode 278 479 μs Low-speed CR Timer mode tICNT Remarks *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-05669 Rev. *C Page 76 of 90 CY9A120L Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. Document Number: 002-05669 Rev. *C Page 77 of 90 CY9A120L Series 12.9.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Value Parameter Symbol Unit Typ Max* 149 264 μs 149 264 μs 318 603 μs Sub Timer mode 308 583 μs RTC/Stop mode 248 443 μs Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode tRCNT Remarks *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation Document Number: 002-05669 Rev. *C Start Page 78 of 90 CY9A120L Series Operation example of return from low power consumption mode (by internal resource reset*) Internal Resource RST Internal RST RST Active Release Trcnt CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. − The time during the power-on reset/low-voltage detection reset is excluded. See (12.4.7) Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-05669 Rev. *C Page 79 of 90 CY9A120L Series 13. Ordering Information On-chip Flash memory On-chip SRAM Package CY9AF121KWQN-G-JNE2 64 Kbyte 4 Kbyte Plastic・QFN (0.5 mm pitch), 48-pin (WNY048) CY9AF121KPMC-G-JNE2 64 Kbyte 4 Kbyte Plastic・LQFP (0.5 mm pitch), 48-pin (LQA048) CY9AF121KPMC1-G-JNE2 64 Kbyte 4 Kbyte Plastic・LQFP (0.65 mm pitch), 52-pin (LQC052) Part number CY9AF121LPMC1-G-JNE2 64 Kbyte 4 Kbyte Plastic・LQFP (0.5 mm pitch), 64-pin (LQD064) CY9AF121LPMC-G-JNE2 64 Kbyte 4 Kbyte Plastic・LQFP (0.65 mm pitch), 64-pin (LQG064) CY9AF121LWQN-G-JNE2 64 Kbyte 4 Kbyte Plastic・QFN (0.5 mm pitch), 64-pin (WNS064) Document Number: 002-05669 Rev. *C Packing Tray Page 80 of 90 CY9A120L Series 14. Package Dimensions Package Type Package Code LQFP 64 LQD064 4 D D1 48 5 7 33 33 32 49 48 32 49 17 64 5 7 E1 E 4 3 6 17 64 1 16 e 1 16 2 5 7 3 BOTTOM VIEW 0.1 0 C A-B D 0.2 0 C A-B D b 0.0 8 C A-B D 8 TOP VIEW A 2 9 A A' 0.0 8 C SEATING PLAN E L1 0.25 L A1 c b SECTION A-A' 10 SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. A A1 1. 70 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E 12.00 BSC. E1 10.00 BSC. L 0.45 0.60 0.75 L1 0.30 0.50 0.70 PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 M M LQD064 Rev** 002-13879 ** Document Number: 002-05669 Rev. *C Page 81 of 90 CY9A120L Series Package Type Package Code LQFP 64 LQG064 D D1 48 4 5 7 33 33 32 49 48 32 49 17 64 E1 E 5 7 4 3 17 64 1 16 e 0.20 1 16 2 5 7 3 BOTTOM VIEW 0.10 C A-B D C A-B D b 0.13 C A-B D 8 TOP VIEW 2 A θ A A' 0.10 C SEATI N G PLA N E 0.2 5 L1 L 9 A1 10 c b SECTION A -A' SIDE VIEW SYM BOL DIM ENSION M IN. NOM . M AX. 1.70 A A1 0.00 0.20 b 0.27 c 0.09 0.32 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E 14.00 BSC E1 0.37 12.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 64 LEAD LQFP 12.0X12.0X1.7 M M LQG064 REV** 002-13881 ** Document Number: 002-05669 Rev. *C Page 82 of 90 CY9A120L Series Package Type Package Code LQFP 48 LQA048 4 D 5 7 D1 36 25 37 24 E1 24 37 13 48 E 5 7 3 36 25 4 6 48 13 1 12 e 1 12 2 5 7 0.10 C A-B D 3 0.20 C A-B D b 0.80 C A-B D 8 2 A θ A A' 0.80 C SYM BOL L1 0.25 L A1 c b 10 SECTION A-A' D IM EN SIONS M IN . N OM . M AX. 0.00 0.20 1.70 A A1 9 SEATING PLANE b 0.15 0.27 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC e 0.50 BSC E 9.00 BSC E1 7.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 48 LEAD LQFP 7.0X7.0X1.7 M M LQA048 REV** 002-13731 ** Document Number: 002-05669 Rev. *C Page 83 of 90 CY9A120L Series Package Type Package Code LQFP 52 LQC052 4 D 5 7 D1 39 27 26 40 39 27 26 40 14 52 E1 E 4 5 7 3 6 14 52 1 2 5 7 13 e b 0.20 C A-B D 0.13 C A-B 1 13 0.10 C A-B D 3 BOTTOM VIEW D 8 TOP VIEW 2 A θ 0.25 A A' 0.10 C SEATIN G PLA N E L1 L A1 10 9 c b SECTIO N A-A' SIDE VIEW SYM BOL DIM ENSION M IN. NOM . M AX. 1.70 A A1 0.00 0.20 b 0.265 c 0.09 0.30 0.365 0.20 D 12.00 BSC D1 10.00 BSC e 0.65 BSC E 12.00 BSC 10.00 BSC E1 L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 52 LEAD LQFP 10.0X10.0X1.7 M M LQC052 REV** 002-13880 ** Document Number: 002-05669 Rev. *C Page 84 of 90 CY9A120L Series Package Type Package Code QFN 48 WNY048 0.15 D A D2 25 C A B 36 0.10 C 24 2X 37 0.15 (ND-1)× e E C A B E2 5 13 9 INDEX M ARK 8 48 12 B L b 0.10 C TOP VIEW 0.10 0.05 C A B C 4 BOTTOM VIEW 2X A 0.05 C A1 c 1 e SEATING PLANE 9 C SIDE VIEW NOTE DIMENSIONS SYMBOL M IN. NOM. MAX. 1. ALL DIMENSIONS ARE IN M ILLIMETERS. 2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTALNUM BER OF TERMINALS. A A1 0.80 0.00 D 7.00 BSC E b 0.05 7.00 BSC 0.18 0.25 D2 4.65 BSC E2 4.65 BSC e 0.50 BSC c 0.30 REF L 0.45 0.50 4. DIMENSION "b"APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETW EEN 0.15 AND 0.30m m FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALSON D OR E SIDE. 0.30 6. MAX. PACKAGE W ARPAGE IS 0.05m m. 7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP W ILLBE LOCATED W ITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT SINK SLUG AS W ELL AS THE TERMINALS. 0.55 10. JEDEC SPECIFICATION NO. REF : N/A PACKAGE OUTLINE, 48 LEAD QFN 7.00X7.00X0.80 M M WNY048 4.65X4.65 M M EPAD (SAWN) REV** 002-16422 ** Document Number: 002-05669 Rev. *C Page 85 of 90 CY9A120L Series Package Type Package Code QFN 64 WNS064 D D2 A 33 0.15 C A B 49 0.15 48 0.10 C 32 2X (ND-1)× e E C A B E2 5 64 17 16 INDEX MARK 8 9 B e L b 0.10 C TOP VIEW 0.10 0.05 C A B C 4 BOTTOM VIEW 2X A 0.05 C A1 c 1 SEATING PLANE 9 C SIDE VIEW NOTE DIMENSIONS SYMBOL M IN. NOM. MAX. 1. ALL DIMENSIONS ARE IN M ILLIMETERS. 2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTALNUM BER OF TERMINALS. A A1 0.80 0.00 D 9.00 BSC E b 0.05 9.00 BSC 0.20 0.25 4. DIMENSION "b"APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETW EEN 0.15 AND 0.30m m FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALSON D OR E SIDE. 0.30 6. MAX. PACKAGE W ARPAGE IS 0.05m m. D2 7.20 BSC E2 7.20 BSC 8. PIN #1 ID ON TOP W ILLBE LOCATED W ITHIN INDICATED ZONE. e 0.50 BSC c 0.50 REF 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT SINK SLUG AS W ELL AS THE TERMINALS. L 0.35 0.40 7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS. 0.45 10. JEDEC SPECIFICATION NO. REF : N/A PACKAGE OUTLINE, 64 LEAD QFN 9.00X9.00X0.80 M M WNS064 7.20X7.20 M M EPAD (SAWN) REV** 002-16424 ** Document Number: 002-05669 Rev. *C Page 86 of 90 CY9A120L Series 15. Major Changes Spansion Publication Number: DS706-00064 Page Section Revision 0.1 Revision 0.2 Revision 1.0 2 Features 3 Features 4 Features 6 17 29 37 47 48,49 49 55 66 68 71 72,73 74 Product Lineup List Of Pin Function ・List of pin numbers I/O Circuit Type Block Diagram Electrical Characteristics 2. Recommended Operating Conditions Electrical Characteristics 3.DC Characteristics (1) Current Rating Electrical Characteristics 3.DC Characteristics (1) Current Rating ・A/D converter current Electrical Characteristics 3.AC Characteristics (6)Power-on Reset Timing  Electrical Characteristics 3.AC Characteristics (10) I2C Timing Electrical Characteristics 5. 12-bit A/D Converter Electrical Characteristics 6. 10-bit D/A Converter Electrical Characteristics 7. Low-Voltage Detection Characteristics Electrical Characteristics 8. Flash Memory Write/Erase Characteristics Electrical Characteristics 9. Return Time from Low-Power Consumption Mode 84,85 Package Dimensions Revision 2.0 26 I/O Circuit Type Memory Map 39 · Memory map(2) 75,77 Document Number: 002-05669 Rev. *C Change Results Initial release Company name and layout design change Preliminary → Full Production Revised I2C operation mode name Revised the value of A/D conversion time Revised Channel number of MFT A/D activation compare ・Added notes of Built-in high speed CR accuracy ・Revised channel number of MFT A/D activation compare Corrected I/O circuit type of P80,P81,P82 Added the remarks of type L Revised Channel number of MFT A/D activation compare Corrected the minimum value of AVRH voltage Revised the values of “TBD” ・Corrent the pin name of power supply current ・Added the at stop condition of power supply current ・Added the remark of reference power supply current Revised the values of “TBD” ・Revised I2C operation mode name ・Revised the value of noise filter ・Revised the value of zero transition valtage and full-scale transiton valtage ・Revised the value of conversion time, sampling time, compare clock cycle ・Corrected the value of state transition time to operation permission ・Corrected the minimum value of AVRH voltage ・Revised the notes explanation ・Delete (Preliminary value) description ・Delete (Preliminary value) description ・Corrected the values of SVHR and SVHI ・Revised the values of “TBD” ・Revised the values of typical ・Revised the notes of Erase/write cycles and data hold time ・Delete (target value) description Revised the values of “TBD” Added the figures of LCC-48P-M74 and LCC-64P-M25 Added about +B input Added the summary of Flash memory sector and the note Page 87 of 90 CY9A120L Series Page 46, 47 48 49, 50 56 57 59-66 Section Electrical Characteristics 1. Absolute Maximum Ratings Electrical Characteristics 2. Recommended Operation Conditions Electrical Characteristics 3. DC Characteristics (1) Current rating Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing Electrical Characteristics 4. AC Characteristics (8) CSIO/UART Timing 70 Electrical Characteristics 5. 12bit A/D Converter 81 Ordering Information Change Results · Added the Clamp maximum current · Added about +B input Added the note about less than the minimum power supply voltage · Changed the table format · Added Main TIMER mode current Added the figure of Main PLL connection Changed the figure of timing · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage Changed notation of part number NOTE: Please see “Document History” about later revised information. Document Number: 002-05669 Rev. *C Page 88 of 90 CY9A120L Series Document History Document Title: CY9A120L Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller Document Number: 002-05669 Revision ECN Orig. of Change ** - AKIH Submission Date Description of Change 03/31/2015 Migrated to Cypress and assigned document number 002-05669. No change to document contents. *A 5168181 AKIH 03/28/2016 Updated to Cypress template. *B 5658524 YSKA 03/13/2017 Updated “12.4.7 Power-On Reset Timing”: Changed parameter from “Power Supply rise time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments (Page 56). Modified RTC description in “Features, Real-Time Clock(RTC)” as below Changed starting count value from 01 to 00. Deleted “second, or day of the week” in the Interrupt function (Page 2). Added Notes for JTAG (Page 23), Changed “J-TAG” to” JTAG” in “4 List of Pin Functions” (Page 18). Updated Package code and dimensions as follows (Page 7-12, 47, 80-86) FPT-48P-M49 -> LQA048, LCC-48P-M74 -> WNY048, FPT-52P-M02 -> LQC052, FPT-64P-M38 -> LQD064, FPT-64P-M39 -> LQG064, LCC-64P-M25 -> WNS064. Added the Baud rate spec in “12.4.9 CSIO/UART Timing” (Page 58, 60, 62, 64). Completing Sunset Review. *C 6516677 HUAL 05/07/2019 Updated Document Title to read as “CY9A120L Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller”. Replaced “MB9A120L Series” with “CY9A120L Series” in all instances across the document. Updated Ordering Information: Updated part numbers. Updated to new template. Document Number: 002-05669 Rev. *C Page 89 of 90 CY9A120L Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-05669 Rev. *C May 7, 2019 Page 90 of 90
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