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MB9AF132LBQN-G-AVE2

MB9AF132LBQN-G-AVE2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    VFQFN64_EP

  • 描述:

    ARM® Cortex®-M3 FM3 MB9A130LB Microcontroller IC 32-Bit 20MHz 128KB (128K x 8) FLASH 64-QFN (9x9)

  • 数据手册
  • 价格&库存
MB9AF132LBQN-G-AVE2 数据手册
Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9A130LB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller The CY9A130LB Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power consumption mode and competitive cost. The CY9A130LB Series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE3 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM® Cortex®-M3 Core [CSIO]  Processor version: r2p1  Full-duplex double buffer  Up to 20 MHz Operation Frequency  Built-in dedicated baud rate generator  Integrated Nested Vectored Interrupt Controller (NVIC): 1  Overrun error detection function available channel NMI (non-maskable interrupt) and 32 channels' peripheral interrupts and 8 priority levels [I2C]  24-bit System timer (Sys Tick): System timer for OS task Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported On-chip Memories A/D Converter (Max 8 channels) [Flash memory] [12-bit A/D Converter]  Up to 128 Kbytes  Successive Approximation type  Read cycle: 0 wait-cycle  Conversion time: Min. 1.0 μs  Security function for code protection  Priority conversion available (priority at 2 levels) management  Scanning conversion mode [SRAM] This series contains 8 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core.  SRAM1: 8 Kbytes  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) Base Timer (Max 8 channels) Multi-function Serial Interface (Max 8 channels) Operation mode is selectable from the followings for each channel.  UART Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  CSIO  16-/32-bit PWC timer  I2 C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detection functions available (parity errors, framing errors, and overrun errors) Cypress Semiconductor Corporation Document Number: 002-05671 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 17, 2019 CY9A130LB Series General Purpose I/O Port Watchdog Timer (2 channels) This series can use its pins as general purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. A watchdog timer can generate interrupts or a reset when a time-out value is reached.  Capable of pull-up control per pin Hardware watchdog timer is clocked by built-in Low-speed CR oscillator. Therefore, Hardware watchdog is active in any low power consumption mode except RTC and Stop and Deep Standby RTC and Deep Standby Stop modes.  Capable of reading pin level directly  Built-in the port relocate function  Up to 52 fast general purpose I/O Ports@64 pin Package  Some pins are 5V tolerant I/O See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Multi-function Timer This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL) that are dynamically selectable. The Multi-function timer is composed of the following blocks.  Main Clock: 4 MHz to 20 MHz  16-bit free-run timer × 3 ch.  Sub Clock: 32.768 kHz  Input capture × 4 ch.  Built-in High-speed CR Clock: 4 MHz  Output compare × 6 ch.  Built-in Low-speed CR Clock: 100 kHz  A/D activation compare × 1 ch.  Main PLL Clock  Waveform generator × 3 ch.  16-bit PPG timer × 3 ch. The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. Low Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has been set, Low Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation External Interrupt Controller Unit  Up to 8 external interrupt input pins  Include one non-maskable interrupt (NMI) input pin Document Number: 002-05671 Rev. *D Page 2 of 86 CY9A130LB Series Low Power Consumption Mode Debug Six low power consumption modes supported. Serial Wire JTAG Debug Port (SWJ-DP)  Sleep  Timer Power Supply Wide range voltage: VCC = 1.8 V to 5.5 V  RTC  Stop  Deep Standby RTC  Deep Standby Stop Back up register is 16 bytes. Document Number: 002-05671 Rev. *D Page 3 of 86 CY9A130LB Series Contents 1. Product Lineup .................................................................................................................................................................. 6 2. Packages ........................................................................................................................................................................... 7 3. Pin Assignment ................................................................................................................................................................. 8 4. List of Pin Functions....................................................................................................................................................... 12 5. I/O Circuit Type ............................................................................................................................................................... 25 6. Handling Precautions ..................................................................................................................................................... 30 6.1 Precautions for Product Design ................................................................................................................................... 30 6.2 Precautions for Package Mounting .............................................................................................................................. 31 6.3 Precautions for Use Environment ................................................................................................................................ 32 7. Handling Devices ............................................................................................................................................................ 33 8. Block Diagram ................................................................................................................................................................. 35 9. Memory Size .................................................................................................................................................................... 36 10. Memory Map .................................................................................................................................................................... 36 11. Pin Status in Each CPU State ........................................................................................................................................ 39 12. Electrical Characteristics ............................................................................................................................................... 45 12.1 Absolute Maximum Ratings ......................................................................................................................................... 45 12.2 Recommended Operating Conditions ......................................................................................................................... 46 12.3 DC Characteristics ...................................................................................................................................................... 47 12.3.1 Current Rating .............................................................................................................................................................. 47 12.3.2 Pin Characteristics ....................................................................................................................................................... 50 12.4 AC Characteristics ....................................................................................................................................................... 51 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 51 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 52 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 52 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 53 12.4.5 Operating Conditions of Main PLL (In the case of using built-in High-speed CR clock for input clock of Main PLL) .... 53 12.4.6 Reset Input Characteristics .......................................................................................................................................... 54 12.4.7 Power-on Reset Timing ................................................................................................................................................ 54 12.4.8 Base Timer Input Timing .............................................................................................................................................. 55 12.4.9 CSIO/UART Timing ...................................................................................................................................................... 56 12.4.10 External Input Timing ................................................................................................................................................ 64 12.4.11 I2C Timing ................................................................................................................................................................. 65 12.4.12 JTAG Timing............................................................................................................................................................. 66 12.5 12-bit A/D Converter .................................................................................................................................................... 67 12.6 Low-Voltage Detection Characteristics ........................................................................................................................ 70 12.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 70 12.6.2 Interrupt of Low-voltage Detection ............................................................................................................................... 71 12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 73 12.7.1 Write / Erase time......................................................................................................................................................... 73 12.7.2 Write cycles and data hold time ................................................................................................................................... 73 12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 74 12.8.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 74 12.8.2 Return Factor: Reset .................................................................................................................................................... 76 13. Ordering Information ...................................................................................................................................................... 78 14. Package Dimensions ...................................................................................................................................................... 79 15. Major Changes ................................................................................................................................................................ 84 Document Number: 002-05671 Rev. *D Page 4 of 86 CY9A130LB Series Document History ................................................................................................................................................................. 85 Sales, Solutions, and Legal Information ............................................................................................................................. 86 Document Number: 002-05671 Rev. *D Page 5 of 86 CY9A130LB Series 1. Product Lineup Memory size Product name On-chip Flash On-chip SRAM SRAM1 CY9AF131KB/LB CY9AF132KB/LB 64 Kbytes 8 Kbytes 128 Kbytes 8 Kbytes CY9AF131KB CY9AF132KB 48 CY9AF131LB CY9AF132LB 64 Function Product name Pin count CPU Freq. Power supply voltage range MF Serial Interface (UART/CSIO/I2C) Base Timer (PWC/ Reload timer/PWM/PPG) A/D activation 1 ch. compare Input capture 4 ch. Free-run timer 3 ch. MFOutput Timer 6 ch. compare Waveform 3 ch. generator PPG 3 ch. Real-time clock Watchdog timer External Interrupts general purpose I/O ports 12-bit A/D converter CSV (Clock Super Visor) LVD (Low Voltage Detector) High-speed Built-in CR Low-speed Debug Function Cortex-M3 20 MHz 1.8 V to 5.5 V 4 ch. (Max) (CSIO and I2C is Max 3 ch.) 8 ch. (Max) 8 ch. (Max) 1 unit (Max) 1 unit 1 ch. (SW) + 1 ch. (HW) 6 pins (Max) + NMI × 1 8 pins (Max) + NMI × 1 37 pins (Max) 52 pins (Max) 6 ch. (1 unit) 8 ch. (1 unit) Yes 2 ch. 4 MHz 100 kHz SWJ-DP Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics (12.4) AC Characteristics (12.4.3) Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: 002-05671 Rev. *D Page 6 of 86 CY9A130LB Series 2. Packages Product name Package CY9AF131KB CY9AF132KB CY9AF131LB CY9AF132LB LQFP: LQA048 (0.5mm pitch)  - QFN: VNA048  - LQFP: LQD064 (0.5mm pitch) -  LQFP: LQG064 (0.65mm pitch) -  QFN: VNC064 -  : Supported Note: − See Package Dimensions for detailed information on each package. Document Number: 002-05671 Rev. *D Page 7 of 86 CY9A130LB Series 3. Pin Assignment LQA048 P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 39 38 37 P04 / TDO / SWO P03 / TMS / SWDIO 41 40 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 43 42 P81 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 46 45 44 VSS P82 48 47 (TOP VIEW) VCC 1 36 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 35 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 34 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 33 AVSS P39 / DTTI0X_0 / ADTG_2 5 32 AVRH P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 6 31 AVCC P3B / TIOA1_1 / RTO01_0 7 30 P15 / AN05 / IC03_2 P3C / TIOA2_1 / RTO02_0 8 29 P14 / AN04 / INT03_1 / IC02_2 P3D / TIOA3_1 / RTO03_0 9 28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3E / TIOA4_1 / RTO04_0 10 27 P12 / AN02 / SOT1_1 / IC00_2 P3F / TIOA5_1 / RTO05_0 11 26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 VSS 12 25 P10 / AN00 22 23 24 PE2 / X0 VSS MD0 PE3 / X1 20 21 PE0 / MD1 18 19 P49 / TIOB0_0 INITX P4A / TIOB1_0 15 16 17 P46 / X0A P47 / X1A 13 14 C VCC LQFP - 48 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05671 Rev. *D Page 8 of 86 CY9A130LB Series VNA048 37 P00 / TRSTX 38 P01 / TCK / SWCLK 39 P02 / TDI 40 P03 / TMS / SWDIO 41 P04 / TDO / SWO 42 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 43 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 44 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 45 P80 46 P81 47 P82 48 VSS (TOP VIEW) VCC 1 36 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 35 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 34 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 33 AVSS P39 / DTTI0X_0 / ADTG_2 5 32 AVRH P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 6 P3B / TIOA1_1 / RTO01_0 7 P3C / TIOA2_1 / RTO02_0 8 29 P14 / AN04 / INT03_1 / IC02_2 P3D / TIOA3_1 / RTO03_0 9 28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 31 AVCC QFN - 48 30 P15 / AN05 / IC03_2 P3E / TIOA4_1 / RTO04_0 10 27 P12 / AN02 / SOT1_1 / IC00_2 P3F / TIOA5_1 / RTO05_0 11 26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 VSS 24 PE3 / X1 23 PE2 / X0 22 MD0 21 PE0 / MD1 20 P4A / TIOB1_0 19 P49 / TIOB0_0 18 INITX 17 P47 / X1A 16 P46 / X0A 15 C 13 25 P10 / AN00 VCC 14 VSS 12 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05671 Rev. *D Page 9 of 86 CY9A130LB Series LQD064/LQG064 P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 52 51 50 49 P0A / SIN4_0 / INT00_2 P04 / TDO / SWO 54 53 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 56 55 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 59 58 57 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 61 60 VSS P82 P81 64 63 62 (TOP VIEW) VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 41 AVCC P39 / DTTI0X_0 / ADTG_2 9 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 16 33 VCC 29 30 31 32 MD0 PE2 / X0 PE3 / X1 VSS 27 28 PE0 / MD1 P4D / SOT7_1 / TIOB4_0 P4E / SIN7_1 / TIOB5_0 / INT06_2 25 26 P4C / SCK7_1 / TIOB3_0 22 23 24 P49 / TIOB0_0 P4A / TIOB1_0 INITX P4B / TIOB2_0 20 21 P47 / X1A 17 18 19 C VCC P46 / X0A LQFP - 64 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05671 Rev. *D Page 10 of 86 CY9A130LB Series VNC064 50 P01 / TCK / SWCLK 49 P00 / TRSTX 52 P03 / TMS / SWDIO 51 P02 / TDI 54 P0A / SIN4_0 / INT00_2 53 P04 / TDO / SWO 56 P0C / SCK4_0 / TIOA6_1 55 P0B / SOT4_0 / TIOB6_1 58 P62 / SCK5_0 / ADTG_3 57 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 60 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 59 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 62 P81 61 P80 64 VSS 63 P82 (TOP VIEW) VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 P39 / DTTI0X_0 / ADTG_2 9 42 AVRH 41 AVCC QFN - 64 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 16 VSS 32 PE3 / X1 31 MD0 29 PE2 / X0 30 PE0 / MD1 28 P4E / SIN7_1 / TIOB5_0 / INT06_2 27 P4D / SOT7_1 / TIOB4_0 26 P4C / SCK7_1 / TIOB3_0 25 P4A / TIOB1_0 23 P4B / TIOB2_0 24 INITX 21 P49 / TIOB0_0 22 P46 / X0A 19 P47 / X1A 20 C 17 VCC 18 33 VCC Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05671 Rev. *D Page 11 of 86 CY9A130LB Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-64 QFN-64 1 1 2 2 3 3 4 4 5 - 6 - 7 - 8 - 9 5 10 6 Document Number: 002-05671 Rev. *D I/O circuit type Pin name LQFP-48 QFN-48 VCC P50 INT00_0 SIN3_1 P51 INT01_0 SOT3_1 (SDA3_1) P52 INT02_0 SCK3_1 (SCL3_1) P30 TIOB0_1 INT03_2 P31 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 P32 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 P33 INT04_0 TIOB3_1 SIN6_1 ADTG_6 P39 DTTI0X_0 ADTG_2 P3A RTO00_0 (PPG00_0) TIOA0_1 RTCCO_2 SUBOUT_2 Pin state type G F G F G F E F E F E F E F E H E H Page 12 of 86 CY9A130LB Series Pin No LQFP-64 QFN-64 I/O circuit type Pin name LQFP-48 QFN-48 Pin state type P3B 11 7 RTO01_0 (PPG00_0) E H E H E H E H E H TIOA1_1 P3C 12 8 RTO02_0 (PPG02_0) TIOA2_1 P3D 13 9 RTO03_0 (PPG02_0) TIOA3_1 P3E 14 10 RTO04_0 (PPG04_0) TIOA4_1 P3F 15 11 RTO05_0 (PPG04_0) TIOA5_1 16 12 VSS - 17 13 C - 18 14 VCC - 19 15 20 16 21 17 22 18 23 19 24 - Document Number: 002-05671 Rev. *D P46 X0A P47 X1A INITX P49 TIOB0_0 P4A TIOB1_0 P4B TIOB2_0 D M D N B C E H E H E H Page 13 of 86 CY9A130LB Series Pin No LQFP-64 QFN-64 I/O circuit type Pin name LQFP-48 QFN-48 Pin state type P4C 25 - TIOB3_0 SCK7_1 (SCL7_1) E H E H E F C P H D A A A B P4D 26 - TIOB4_0 SOT7_1 (SDA7_1) P4E 27 - TIOB5_0 INT06_2 SIN7_1 PE0 28 20 29 21 30 22 31 23 32 24 VSS - 33 - VCC - 34 25 MD1 MD0 PE2 X0 PE3 X1 P10 AN00 F J F L F J F J P11 AN01 SIN1_1 35 26 INT02_1 FRCK0_2 IC02_0 WKUP1 P12 AN02 36 27 SOT1_1 (SDA1_1) IC00_2 P13 AN03 37 28 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 Document Number: 002-05671 Rev. *D Page 14 of 86 CY9A130LB Series Pin No LQFP-64 QFN-64 I/O circuit type Pin name LQFP-48 QFN-48 Pin state type P14 38 29 AN04 INT03_1 F K F J F K IC02_2 P15 39 30 AN05 IC03_2 P17 40 - AN07 SIN2_2 INT04_1 41 31 AVCC - 42 32 AVRH - 43 33 AVSS - P18 44 - 45 - AN08 SOT2_2 (SDA2_2) F J E H G H G H G G E E E E E E P19 SCK2_2 (SCL2_2) P23 46 34 SCK0_0 (SCL0_0) TIOA7_1 P22 47 35 SOT0_0 (SDA0_0) TIOB7_1 P21 48 36 SIN0_0 INT06_1 WKUP2 49 37 P00 TRSTX P01 50 38 TCK SWCLK 51 39 Document Number: 002-05671 Rev. *D P02 TDI Page 15 of 86 CY9A130LB Series Pin No LQFP-64 QFN-64 I/O circuit type Pin name LQFP-48 QFN-48 Pin state type P03 52 40 TMS E E E E E F E H E H E I I H I H I G SWDIO P04 53 41 TDO SWO P0A 54 - SIN4_0 INT00_2 P0B 55 - SOT4_0 (SDA4_0) TIOB6_1 P0C 56 - SCK4_0 (SCL4_0) TIOA6_1 P0F NMIX 57 42 CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 P62 58 - SCK5_0 (SCL5_0) ADTG_3 P61 59 43 SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 P60 SIN5_0 60 44 TIOA2_2 INT15_1 IC00_0 WKUP3 61 45 P80 G O 62 46 P81 G O 63 47 P82 G O 64 48 VSS - Document Number: 002-05671 Rev. *D Page 16 of 86 CY9A130LB Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Debugger Pin name ADTG_2 ADTG_3 ADTG_6 AN00 AN01 AN02 AN03 AN04 AN05 AN07 AN08 TIOA0_1 TIOB0_0 TIOB0_1 TIOA1_1 TIOB1_0 TIOB1_1 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_1 TIOB3_0 TIOB3_1 TIOA4_1 TIOB4_0 TIOA5_1 TIOB5_0 TIOA6_1 TIOB6_1 TIOA7_1 TIOB7_1 SWCLK SWDIO SWO TRSTX TCK TDI TMS TDO Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG reset Input pin JTAG test clock input pin JTAG test data input pin JTAG test mode state input/output pin JTAG debug data output pin Document Number: 002-05671 Rev. *D Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 9 5 58 8 34 25 35 26 36 27 37 28 38 29 39 30 40 44 10 6 22 18 5 11 7 23 19 6 12 8 60 44 24 7 59 43 13 9 25 8 14 10 26 15 11 27 56 55 46 34 47 35 50 38 52 40 53 41 49 37 50 38 51 39 52 40 53 41 Page 17 of 86 CY9A130LB Series Pin function External Interrupt GPIO Pin name INT00_0 INT00_2 INT01_0 INT02_0 INT02_1 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_2 INT06_1 INT06_2 INIT15_1 NMIX P00 P01 P02 P03 P04 P0A P0B P0C P0F P10 P11 P12 P13 P14 P15 P17 P18 P19 P21 P22 P23 Function description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 Document Number: 002-05671 Rev. *D Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 2 2 54 3 3 4 4 35 26 38 29 5 8 40 6 7 48 36 27 60 44 57 42 49 37 50 38 51 39 52 40 53 41 54 55 56 57 42 34 25 35 26 36 27 37 28 38 29 39 30 40 44 45 48 36 47 35 46 34 Page 18 of 86 CY9A130LB Series Pin function GPIO Pin name P30 P31 P32 P33 P39 P3A P3B P3C P3D P3E P3F P46 P47 P49 P4A P4B P4C P4D P4E P50 P51 P52 P60 P61 P62 P80 P81 P82 PE0 PE2 PE3 Function description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Document Number: 002-05671 Rev. *D Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 5 6 7 8 9 5 10 6 11 7 12 8 13 9 14 10 15 11 19 15 20 16 22 18 23 19 24 25 26 27 2 2 3 3 4 4 60 44 59 43 58 61 45 62 46 63 47 28 20 30 22 31 23 Page 19 of 86 CY9A130LB Series Pin function Multifunction Serial 0 Multifunction Serial 1 Multifunction Serial 2 Pin name Function description Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 SIN0_0 Multi-function serial interface ch.0 input pin 48 36 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). 47 35 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). 46 34 SIN1_1 Multi-function serial interface ch.1 input pin 35 26 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). 36 27 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 37 28 SIN2_2 Multi-function serial interface ch.2 input pin 40 - SOT2_2 (SDA2_2) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). 44 - SCK2_2 (SCL2_2) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 45 - Document Number: 002-05671 Rev. *D Page 20 of 86 CY9A130LB Series Pin function Multifunction Serial 3 Multifunction Serial 4 Pin name Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 2 2 SIN3_1 Multi-function serial interface ch.3 input pin SOT3_1 (SDA3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). 3 3 SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 4 4 SIN4_0 Multi-function serial interface ch.4 input pin 54 - SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 55 - 56 - 60 44 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). 59 43 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 58 - SCK4_0 (SCL4_0) Multifunction Serial 5 Function description SIN5_0 Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 input pin Document Number: 002-05671 Rev. *D Page 21 of 86 CY9A130LB Series Pin name Multifunction Serial 6 SIN6_1 Multi-function serial interface ch.6 input pin SOT6_1 (SDA6_1) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). 7 - SCK6_1 (SCL6_1) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). 6 - SIN7_1 Multi-function serial interface ch.7 input pin 27 - SOT7_1 (SDA7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). 26 - SCK7_1 (SCL7_1) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). 25 - Multifunction Serial 7 Function description Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 8 - Pin function Document Number: 002-05671 Rev. *D Page 22 of 86 CY9A130LB Series Pin function Multifunction Timer 0 Pin name DTTI0X_0 DTTI0X_2 FRCK0_2 IC00_0 IC00_2 IC01_2 IC02_0 IC02_2 IC03_2 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) Real-time clock Low Power Consumption Mode RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 WKUP0 WKUP1 WKUP2 WKUP3 Function description Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0 16-bit free-run timer ch.0 external clock input pin 16-bit input capture input pin of Multi-function timer 0. ICxx describes a channel number. Waveform generator output pin of Multifunction timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Waveform generator output pin of Multifunction timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Waveform generator output pin of Multifunction timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Waveform generator output pin of Multifunction timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Waveform generator output pin of Multifunction timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Waveform generator output pin of Multifunction timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Deep stand-by mode return signal input pin 0 Deep stand-by mode return signal input pin 1 Deep stand-by mode return signal input pin 2 Deep stand-by mode return signal input pin 3 Document Number: 002-05671 Rev. *D Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 9 5 59 43 35 26 60 36 37 35 38 39 44 27 28 26 29 30 10 6 11 7 12 8 13 9 14 10 15 11 57 37 10 57 37 10 57 35 48 60 42 28 6 42 28 6 42 26 36 44 Page 23 of 86 CY9A130LB Series Pin function Reset Pin name INITX Mode MD0 MD1 Function description External Reset Input pin. A reset is valid when INITX = L. Mode 0 pin. During normal operation, MD0 = L must be input During serial programming to flash memory, MD0 = H must be input. Mode 1 pin. During normal operation, input is not needed During serial programming to flash memory, MD1 = L must be input. Power VCC Power supply pin VSS GND pin X0 X0A X1 X1A CROUT_1 AVCC Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in High-speed CR-osc clock output port A/D converter analog power pin A/D converter analog reference voltage input pin GND Clock ADC Power ADC GND C pin AVRH Pin No LQFP-64 LQFP-48 QFN-64 QFN-48 21 17 29 21 28 20 1 18 33 16 32 64 30 19 31 20 57 41 1 14 12 24 48 22 15 23 16 42 31 42 32 AVSS A/D converter GND pin 43 33 C Power stabilization capacity pin 17 13 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05671 Rev. *D Page 24 of 86 CY9A130LB Series 5. I/O Circuit Type Type A Circuit Remarks It is possible to select the main oscillation / GPIO function. When the main oscillation is selected. Pull-up resistor P-ch P-ch Digital output X1 N-ch Digital output R • Oscillation feedback resistor : Approximately 1 MΩ • With Standby control When the GPIO is selected. • CMOS level output. • CMOS level hysteresis input • With pull-up resistor control • With standby control • Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA Pull-up resistor control Digital input Standby mode Control Clock input Feedback resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control Document Number: 002-05671 Rev. *D Page 25 of 86 CY9A130LB Series Type B Circuit Remarks • CMOS level hysteresis input • Pull-up resistor : Approximately 50 kΩ Pull-up resistor Digital input C Digital input N-ch Document Number: 002-05671 Rev. *D • Open drain output • CMOS level hysteresis input Digital output Page 26 of 86 CY9A130LB Series Type Circuit Remarks D It is possible to select the sub oscillation / GPIO function Pull-up resistor P-ch P-ch Digital output X1A N-ch Digital output R Pull-up resistor control When the sub oscillation is selected. • Oscillation feedback resistor : Approximately 5 MΩ • With Standby control When the GPIO is selected. • CMOS level output. • CMOS level hysteresis input • With pull-up resistor control • With standby control • Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA Digital input Standby mode Control Clock input Feedback resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control Document Number: 002-05671 Rev. *D Page 27 of 86 CY9A130LB Series Type Circuit Remarks E • • • • • P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output R Pull-up resistor control Digital input Standby mode Control F P-ch P-ch N-ch R Digital output Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode Control Analog input Input control Document Number: 002-05671 Rev. *D Page 28 of 86 CY9A130LB Series Type Circuit Remarks G P-ch N-ch Digital output Digital output • • • • • • CMOS level output CMOS level hysteresis input With standby control 5 V tolerant input IOH = -4 mA, IOL = 4 mA Available to control of PZR registers. Only P22, P23, P51, P52 • When this pin is used as an I2C pin, the digital output P-ch transistor is always off R Digital input Standby mode control H CMOS level hysteresis input Mode input I • • • • • P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With standby control IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output R Digital input Standby mode control Document Number: 002-05671 Rev. *D Page 29 of 86 CY9A130LB Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-05671 Rev. *D Page 30 of 86 CY9A130LB Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 3. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 4. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 5. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 6. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-05671 Rev. *D Page 31 of 86 CY9A130LB Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05671 Rev. *D Page 32 of 86 CY9A130LB Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins and GND pins, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pins.  Example of Using an External Clock Device X0/PE2 (X0A/P46) Can be used as general-purpose I/O ports. X1/PE3 (X1A/P47) Set as generalpurpose I/O ports. Handling when using Multi-function serial pin as I2C pin If it is using the Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF. Document Number: 002-05671 Rev. *D Page 33 of 86 CY9A130LB Series C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7uF would be recommended for this series. C Device CS VSS GND Mode pins (MD0, MD1) Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on: VCC → AVCC → AVRH Turning off: AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Document Number: 002-05671 Rev. *D Page 34 of 86 CY9A130LB Series 8. Block Diagram MB9AF131/132 TRSTX,TCK, TDI,TMS TDO ROM Table SWJ-DP Cortex-M3 Core I @20MHz(Max) D Multi-layer AHB (Max 20MHz) Sys AHB-APB Bridge: APB0 (Max 20MHz) NVIC Flash I/F Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) Security On-Chip Flash 64/128Kbytes SRAM1 8Kbytes CSV CLK X0 X1 X0A X1A Main Osc Sub Osc PLL Source Clock CR 4MHz CR 100kHz CROUT AVCC, AVSS,AVRH ANxx Deep Standby Ctrl WKUPx 12-bit A/D Converter Unit 0 ADTG_x A/D Activation Compare 1ch. IC0x FRCK0 16-bit Input Capture 4ch. 16-bit FreeRun Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x LVD Ctrl AHB-APB Bridge : APB2 (Max 20MHz) TIOBx Power On Reset Base Timer 16-bit 8ch. / 32-bit 4ch. AHB-APB Bridge : APB1 (Max 20MHz) TIOAx Regulator C IRQ-Monitor RTCCO SUBOUT Real-Time Clock External Interrupt Controller 8-pin + NMI INTxx NMIX MD1, MD0 MODE-Ctrl GPIO Waveform Generator 3ch. 16-bit PPG 3ch. LVD Multi-Function Serial I/F 8ch. PIN-Function-Ctrl P0x, P1x, . . Pxx SCKx SINx SOTx Multi-Function Timer ×1 Document Number: 002-05671 Rev. *D Page 35 of 86 CY9A130LB Series 9. Memory Size See Memory size in Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved Reserved 0x4003_C000 0x4003_B000 0x4003_9000 0x4003_8000 0x4400_0000 0x4200_0000 0x4000_0000 32Mbytes Bit band alias Peripherals Reserved 0x2400_0000 0x2200_0000 32Mbytes Bit band alias Reserved 0x2008_0000 0x2000_0000 SRAM1 Reserved See "lMemory map(2)" for the memory size details. 0x0010_0008 0x0010_0000 0x4003_6000 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 RTC Reserved MFS Reserved LVD/DS mode Reserved GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved A/DC Reserved Base Timer PPG Reserved Security/CR Trim 0x4002_1000 0x4002_0000 MFT unit0 Flash Reserved 0x0000_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 SW WDT HW WDT Clock/Reset Reserved 0x4000_1000 0x4000_0000 Document Number: 002-05671 Rev. *D Flash I/F Page 36 of 86 CY9A130LB Series Memory Map (2) *: See CY9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory. Document Number: 002-05671 Rev. *D Page 37 of 86 CY9A130LB Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Reserved 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_50FF Low Voltage Detector 0x4003_5100 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF Reserved 0x4006_1000 0x4006_1FFF 0x4006_2000 0x4006_2FFF Reserved 0x4006_3000 0x4006_3FFF Reserved 0x4006_4000 0x41FF_FFFF Reserved Document Number: 002-05671 Rev. *D AHB APB0 APB1 APB2 AHB Flash I/F register Reserved Software Watchdog timer Reserved Base Timer Reserved Deep stand-by mode Controller Reserved Reserved Page 38 of 86 CY9A130LB Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX = 0 This is the period when the INITX pin is the L level.  INITX = 1 This is the period when the INITX pin is the H level.  SPL = 0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 0.  SPL = 1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep Standby mode, pins switch to the general-purpose I/O port. Document Number: 002-05671 Rev. *D Page 39 of 86 CY9A130LB Series Pin status type List of Pin Status Poweron reset Device INITX or low internal input voltage reset state detection state Function state group Power Power supply supply stable unstable INITX = 0 INITX = 1 Main crystal Input Input Input oscillator enabled enabled enabled input pin External main clock input A selected GPIO selected Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Run mode or Sleep mode state Power supply stable INITX = 1 Input enabled Maintain previous state Maintain previous state Maintain previous state / Main Hi-Z / Hi-Z / Hi-Z / When crystal Internal Internal Internal oscillation oscillator input input input stop*1, Hioutput pin fixed at 0 fixed at 0 fixed at 0 Z output / B Internal input fixed at 0 C Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply stable Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 INITX = 1 - Input enabled Maintain previous state / When oscillation stop*1, output maintain previous state / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Maintain previous state / When oscillation stop*1, HiZ output / Internal input fixed at 0 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Document Number: 002-05671 Rev. *D Input enabled Input enabled Input enabled Hi-Z / Input enabled / When oscillation stop*1, Hi-Z / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal GPIO selected input fixed at 0 Output maintain Hi-Z / previous Internal state / input Internal fixed at 0 input fixed at 0 Maintain Maintain previous previous state / state / When When oscillation oscillation stop*1, Hi- stop*1, Hi-Z Z output / output / Internal Internal input input fixed fixed at 0 at 0 Hi-Z / Maintain Internal previous input state fixed at 0 Pull-up / Pull-up / Input Input enabled enabled Input enabled Hi-Z / Internal Maintain input previous state fixed at 0 Maintain previous state / When oscillation stop*1, HiZ output / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Pull-up / Input enabled Maintain previous state / When oscillation stop*1, Hi-Z output / Internal input fixed at "0" Maintain previous state Pull-up / Input enabled Page 40 of 86 CY9A130LB Series Pin status type PowerReturn Run on reset Device Deep Standby RTC from INITX or Timer mode, or low internal mode mode or Deep Deep input Sleep RTC mode, or voltage reset Stop mode Standby state mode Stop mode state Standbystate detection state mode state Function state state group Power Power Power Power supply Power supply Power supply supply supply supply stable stable stable unstable stable stable INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 SPL = 0 SPL = 1 SPL = 0 SPL = 1 Mode Input Input Input Input Input Input Input Input Input D input pin enabled enabled enabled enabled enabled enabled enabled enabled enabled JTAG selected Hi-Z GPIO selected Setting disabled Pull-up / Input enabled Pull-up / Input enabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Setting disabled Setting disabled Maintain previous state E External interrupt Setting enabled disabled selected Resource F other than above selected Hi-Z GPIO selected WKUP enabled Setting disabled External interrupt Setting enabled disabled G selected Resource other than above selected Hi-Z GPIO selected Resource selected H GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled Setting disabled Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled Document Number: 002-05671 Rev. *D Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / WKUP Internal input input enabled fixed at 0 Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state GPIO Hi-Z / selected Internal Maintain input fixed at 0 previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state GPIO Hi-Z / selected Internal input fixed at 0 Maintain previous state Hi-Z / WKUP input enabled GPIO selected GPIO Hi-Z / selected Internal input fixed at 0 Maintain previous state GPIO Hi-Z / selected Internal Maintain input fixed at 0 previous state Page 41 of 86 Pin status type CY9A130LB Series PowerRun on reset Device INITX mode or or low internal input Sleep voltage reset state mode detection state state Function state group Power Power Power supply supply supply stable unstable stable INITX = 0 INITX = 1 INITX = 1 NMIX selected I Resource other than above selected Setting disabled Hi-Z GPIO selected Analog input selected Hi-Z J Resource other than above selected Setting disabled GPIO selected Analog input selected Hi-Z External K interrupt enabled selected Resource Setting other than disabled above selected Setting disabled Setting disabled Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Timer mode, RTC mode, or Stop mode state Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Return Deep Standby RTC from mode or Deep Deep Standby Stop mode Standby state mode state Power Power supply supply stable stable INITX = 1 SPL = 0 SPL = 1 WKUP input Hi-Z / enabled Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO Hi-Z / selected Internal Setting Setting input disabled disabled fixed at 0 Maintain previous state Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal input input input input input input fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 / / / / / / Analog Analog Analog Analog Analog Analog input input input input input input enabled enabled enabled enabled enabled enabled Maintain previous state Maintain previous state Maintain previous state Setting disabled GPIO selected Document Number: 002-05671 Rev. *D Setting disabled Maintain previous state Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / WKUP input enabled INITX = 1 - GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO Hi-Z / selected Internal input fixed at 0 Maintain previous state Hi-Z / Hi-Z / Internal Internal input input fixed at 0 fixed at 0 / / Analog Analog input input enabled enabled GPIO Hi-Z / selected Internal input fixed at 0 Maintain previous state Page 42 of 86 Pin status type CY9A130LB Series Poweron reset Device INITX or low internal input voltage reset state detection state Function state group Power Power supply supply stable unstable INITX = 0 INITX = 1 Hi-Z / Hi-Z / Internal Internal input input Analog fixed at 0 fixed at 0 input Hi-Z / / selected Analog Analog input input enabled enabled Run mode or Sleep mode state Power supply stable INITX = 1 Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled L External interrupt enabled selected Setting disabled Resource other than above selected Setting disabled Setting disabled Maintain previous state Timer mode, RTC mode, or Stop mode state Power supply stable INITX = 1 SPL = 0 SPL = 1 Hi-Z / Hi-Z / Internal Internal input input fixed at 0 fixed at 0 / / Analog Analog input input enabled enabled Hi-Z / Internal input fixed at 0 Maintain previous state Input enabled External sub clock Setting input disabled M selected GPIO selected Setting disabled INITX = 1 SPL = 0 SPL = 1 Hi-Z / Hi-Z / Internal Internal input input fixed at 0 fixed at 0 / / Analog Analog input input enabled enabled Hi-Z / WKUP WKUP input input enabled enabled Input enabled Input enabled Input enabled Setting disabled Setting disabled Maintain previous state Setting disabled Setting disabled Maintain previous state Document Number: 002-05671 Rev. *D Input enabled Maintain previous state / When oscillation stop*2, output maintain previous state / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Input enabled GPIO selected Input enabled Maintain previous state / When oscillation stop*2, output maintain previous state / Internal input fixed at 0 Output maintain Hi-Z / previous Internal state / input Internal fixed at 0 input fixed at 0 Hi-Z / Input enabled / When oscillation stop*2, Hi-Z / Internal input fixed at 0 INITX = 1 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Sub crystal oscillator input pin Maintain previous state Return Deep Standby RTC from mode or Deep Deep Standby Stop mode Standby state mode state Power Power supply supply stable stable Hi-Z / Internal input fixed at 0 Maintain previous state Input enabled Input enabled Hi-Z / Input enabled / When oscillation stop*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When Return from Deep Stand-by STOP mode, GPIO selected Hi-Z / Maintain Internal previous input state fixed at 0 Page 43 of 86 Pin status type CY9A130LB Series N PowerRun on reset Device INITX mode or or low internal input Sleep voltage reset state mode detection state state Function state group Power Power Power supply supply supply stable unstable stable INITX = 0 INITX = 1 INITX = 1 - Sub Hi-Z / Hi-Z / Hi-Z / crystal Internal Internal Internal oscillator input input input output pin fixed at 0 fixed at 0 fixed at 0 Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 INITX = 1 - Maintain previous state / When Maintain oscillation previous stops*2, state Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state GPIO Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state GPIO/ Hi-Z / Hi-Z / Internal Internal Internal input input input fixed at 0 fixed at 0 fixed at 0 Maintain previous state Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled Maintain previous state Hi-Z / Input enabled Maintain previous state GPIO selected O Timer mode, RTC mode, or Stop mode state Return Deep Standby RTC from mode or Deep Deep Standby Stop mode Standby state mode state Power Power supply supply stable stable P *1: Oscillation is stopped at Sub run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. Document Number: 002-05671 Rev. *D Page 44 of 86 CY9A130LB Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter voltage*1,*2 Symbol Power supply Analog power supply voltage*1,*3 Analog reference voltage*1,*3 VCC AVCC AVRH Input voltage*1 VI Min VSS - 0.5 VSS - 0.5 VSS - 0.5 Rating VSS - 0.5 VSS - 0.5 Analog pin input voltage*1 VIA VSS - 0.5 Output voltage*1 VO VSS - 0.5 L level maximum output current*4 L level average output current*5 L level total maximum output current L level total average output current*6 H level maximum output current*4 H level average output current*5 H level total maximum output current H level total average output current*6 Power consumption Storage temperature IOL IOLAV ∑IOL ∑IOLAV IOH IOHAV ∑IOH ∑IOHAV PD TSTG - 55 Max VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5 V) VSS + 6.5 AVCC + 0.5 (≤ 6.5 V) VCC + 0.5 (≤ 6.5 V) 10 4 60 30 -10 -4 -60 -30 400 + 150 Unit Remarks V V V V V 5V tolerant V V mA mA mA mA mA mA mA mA mW °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. WARNING: − Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-05671 Rev. *D Page 45 of 86 CY9A130LB Series 12.2 Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Symbol Conditions Power supply voltage Analog power supply voltage VCC AVCC - Analog reference voltage AVRH - Smoothing capacitor CS - Min 1.8 1.8 2.7 AVCC 1 TA - - 40 Operating Temperature LQA048, VNA048, LQD064, LQG064, VNC064 Value Max 5.5 5.5 AVCC AVCC 10 + 85 Unit V V V μF Remarks AVCC = VCC AVCC ≥ 2.7 V AVCC < 2.7 V For built-in Regulator * °C *: See C Pin in Handling Devices for the connection of the smoothing capacitor. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-05671 Rev. *D Page 46 of 86 CY9A130LB Series 12.3 DC Characteristics 12.3.1 Current Rating (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name PLL Run mode High-speed CR Run mode ICC Power supply current VCC Sub Run mode Low-speed CR Run mode ICCS Value Typ*3 Max*4 Conditions PLL Sleep mode High-speed CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode CPU: 20 MHz, Peripheral: 20 MHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU: 20 MHz, Peripheral: clock stopped, NOP operation CPU/Peripheral: 4 MHz*2 Flash memory 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/Peripheral: 32 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU/Peripheral: 100 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 Unit Remarks 20 25 mA *1, *5 10 15 mA *1, *5 4.5 5 mA *1 0.25 0.35 mA *1, *6 0.3 0.45 mA *1 Peripheral: 20 MHz 9 13 mA *1, *5 Peripheral: 4 MHz*2 2 2.5 mA *1 Peripheral: 32 kHz 0.1 0.2 mA *1, *6 Peripheral: 100 kHz 0.2 0.35 mA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.3 V *4: TA=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Document Number: 002-05671 Rev. *D Page 47 of 86 CY9A130LB Series Parameter Symbol Pin name Conditions Main Timer mode ICCT Sub Timer mode ICCR Power supply current RTC mode VCC ICCH ICCRD ICCHD Stop mode Deep Standby RTC mode Deep Standby Stop mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off Typ*2 Value Max*3 Unit Remarks 1 3.6 mA *1, *4 1.7 3.9 mA *1, *4 8.5 70 μA *1, *5 18 170 μA *1, *5 1.8 7.5 μA *1, *5 7 62 μA *1, *5 0.7 7 μA *1 6 60 μA *1 1.6 3 μA *1, *5 3.6 14.5 μA *1, *5 0.5 2.5 μA *1 2.5 12.5 μA *1 *1: When all ports are fixed. *2: VCC = 3.3 V *3: VCC = 5.5 V *4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Document Number: 002-05671 Rev. *D Page 48 of 86 CY9A130LB Series Low Voltage Detection Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Low-voltage detection circuit (LVD) power supply current Symbol ICCLVD Pin name VCC Value Typ* Max Conditions For occurrence of reset or for occurrence of interrupt in normal mode operation For occurrence of reset and for occurrence of interrupt in normal mode operation For occurrence of interrupt in lowpower mode operation 10 20 Unit Remarks μA When not detected 14 30 μA 0.3 2 μA When not detected *: When VCC = 3.3 V Flash Memory Current Parameter Flash memory write/erase current Symbol ICCFLASH Pin name VCC Conditions At Write/Erase (VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C) Value Unit Remarks Typ Max 10.8 11.9 mA A/D Converter Current Parameter Power supply current Reference power supply current Symbol ICCAD ICCAVRH Document Number: 002-05671 Rev. *D Pin name AVCC AVRH (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Value Conditions Unit Remarks Typ Max At 1unit operation 1.4 2.5 mA At stop 0.1 0.35 μA At 1unit operation AVRH=5.5 V 0.8 1.5 mA At stop 0.1 0.3 μA Page 49 of 86 CY9A130LB Series 12.3.2 Pin Characteristics (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) H level output voltage L level output voltage Input leak current Pull-up resistance value Input capacitance Symbol VIHS VILS VOH Pin name MD0, MD1, PE0, PE2, PE3, P46, P47, INITX P21, P22, P23, P50, P51, P52, P80, P81, P82 CMOS hysteresis input pins other than the above MD0, MD1, PE0, PE2, PE3, P46, P47, INITX CMOS hysteresis input pins other than the above Pxx VOL Pxx IIL - RPU Pull-up pin CIN Other than VCC, VSS, AVCC, AVSS, AVRH Document Number: 002-05671 Rev. *D Conditions Value Typ Min Unit Max - VCC × 0.8 - VCC + 0.3 V - VCC× 0.7 - VSS + 5.5 V - VCC × 0.7 - VCC + 0.3 V - VSS 0.3 - VCC× 0.2 V - VSS 0.3 - VCC× 0.3 V VCC ≥ 4.5 V IOH = - 4 mA VCC 0.5 - VCC VCC < 4.5 V IOH = - 1 mA VCC 0.5 - VCC VSS - 0.4 V - -5 - +5 μA VCC ≥ 4.5 V 25 50 100 VCC < 4.5 V 40 100 400 - - 5 15 VCC ≥ 4.5 V IOL = 4 mA VCC < 4.5 V IOL = 2 mA Remarks 5V tolerant V kΩ pF Page 50 of 86 CY9A130LB Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Input frequency fCH Input clock cycle tCYLH Input clock pulse width - Input clock rise time and fall time tCF, tCR Internal operating clock*1 frequency Internal operating clock*1 cycle time Pin name X0, X1 Value Conditions Min Max Unit VCC ≥ 2.0 V VCC < 2.0 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V PWH/tCYLH, PWL/tCYLH 4 4 4 4 50 62.5 20 4 20 16 250 250 MHz MHz MHz MHz ns ns 45 55 % - - 5 ns Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock When using external clock fCM - - - 20 MHz Master clock fCC - - - 20 MHz Base clock (HCLK/FCLK) fCP0 - - - 20 MHz APB0 bus clock*2 fCP1 - - - 20 MHz APB1 bus clock*2 fCP2 - - - 20 MHz APB2 bus clock*2 tCYCC - - 50 - ns Base clock (HCLK/FCLK) tCYCP0 - - 50 - ns APB0 bus clock*2 tCYCP1 - - 50 - ns APB1 bus clock*2 tCYCP2 - - 50 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 Document Number: 002-05671 Rev. *D Page 51 of 86 CY9A130LB Series 12.4.2 Sub Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Input frequency fCL Input clock cycle tCYLL Input clock pulse width Pin name X0A, X1A - Value Condition s Min Typ Max Unit Remarks - 32 32.768 - 100 kHz kHz When crystal oscillator is connected When using external clock - 10 - 31.25 μs When using external clock PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock X0A 12.4.3 Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol VCC ≥ 2.2 V Clock frequency fCRH VCC < 2.2 V Frequency stabilization time Value Conditions tCRWT Min TA = + 25°C TA = - 40°C to + 85°C TA = - 40°C to + 85°C TA = + 25°C TA = - 40°C to + 85°C TA = - 40°C to + 85°C - Typ Max 3.92 4 4.08 3.8 4 4.2 2.3 - 7.03 3.4 4 4.6 3.16 4 4.84 2.3 - 7.03 - - 10 Unit Remarks When trimming*1 MHz When not trimming When trimming*1 MHz When not trimming μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Clock frequency Symbol fCRL Conditions - Document Number: 002-05671 Rev. *D Value Min 50 Typ 100 Max 150 Unit Remarks kHz Page 52 of 86 CY9A130LB Series 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Value Min Typ Unit Max tLOCK 200 - - μs fPLLI fPLLO fCLKPLL 4 1 10 - - 20 5 20 20 MHz multiplier MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 12.4.5 Operating Conditions of Main PLL (In the case of using built-in High-speed CR clock for input clock of Main PLL) (VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Symbol Value Min Typ Max Unit tLOCK 200 - - μs fPLLI fPLLO fCLKPLL 3.8 3 11.4 - 4 - 4.2 4 16.8 16.8 MHz multiplier MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: − Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Document Number: 002-05671 Rev. *D Page 53 of 86 CY9A130LB Series 12.4.6 Reset Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Reset input time 12.4.7 Pin name Symbol tINITX INITX Value Conditions Min - Unit Max 500 - ns 1.5 - ms 1.5 - ms Remarks When RTC mode or Stop mode When Deep Standby mode Power-on Reset Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Pin name Min Typ Max Unit Remarks Power supply rising time dV/dt 0.1 - - V/ms Power supply shut down time tOFF 1 - - ms Reset release voltage VDETH 1.44 1.60 1.76 V When voltage rises 1.39 1.55 1.71 V When voltage drops VCC Reset detection voltage VDETL Time until releasing Power-on reset tPRT 0.46 - 11.4 ms dV/dt ≥ 0.1mV/μs Reset detection delay time tOFFD - - 0.4 ms dV/dt ≥ -0.04mV/μs VDETH VDETL VCC dV 0.2V dt 0.2V tOFF tPRT Internal reset CPU Operation Document Number: 002-05671 Rev. *D Reset active tOFFD Release Reset active start Page 54 of 86 CY9A130LB Series 12.4.8 Base Timer Input Timing Timer input timing Parameter Input pulse width Symbol Pin name Conditions TIOAn/TIOBn (when using as ECK,TIN) tTIWH, tTIWL - (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Remarks Min Max 2tCYCP tTIWH - ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger input timing Parameter Input pulse width Symbol tTRGH, tTRGL Pin name Conditions TIOAn/TIOBn (when using as TGIN) - 2tCYCP tTRGH TGIN VIHS (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Remarks Min Max - ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. Document Number: 002-05671 Rev. *D Page 55 of 86 CY9A130LB Series 12.4.9 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) Parameter Baud rate Serial clock cycle time SCK ↓ → SOT delay time SIN → SCK ↑ setup time SCK ↑ → SIN hold time Serial clock L pulse width Serial clock H pulse width Symbol Pin name - - tSCYC SCKx tSLOVI tIVSHI tSHIXI SCKx, SOTx SCKx, SINx SCKx, SINx Conditions - - (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) 2.7 V ≤ VCC < 2.7 V VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max Min Max 5 5 5 Mbps 4tCYCP - 4tCYCP - 4tCYCP - ns -40 +40 -30 +30 -20 +20 ns 75 - 50 - 30 - ns 0 - 0 - 0 - ns Master mode tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 75 - 50 - 30*1 40*2 ns SIN → SCK ↑ setup time tIVSHE 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns SCK ↑ → SIN hold time SCK falling time SCK rising time tSHIXE tF tR SCKx, SINx SCKx, SINx SCKx SCKx Slave mode *1 When PZR = 0. *2 When PZR = 1. Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05671 Rev. *D Page 56 of 86 CY9A130LB Series tSCYC VOH SCK VOH VOL tSHOVI VOH SOT VOL tIVSLI SIN tSLIXI VIH VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05671 Rev. *D Page 57 of 86 CY9A130LB Series CSIO (SPI = 0, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Baud rate Serial clock cycle time Symbol - - tSCYC SCKx SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time Serial clock L pulse width Serial clock H pulse width tSLIXI SCKx, SOTx SCKx, SINx SCKx, SINx VCC < 2.7 V Conditions Min - 2.7 V ≤ VCC < 4.5 V Min Max 5 - Max 5 - 4tCYCP - 4tCYCP -40 +40 75 VCC ≥ 4.5 V Min Unit - Max 5 Mbps - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns 0 - 0 - 0 - ns Master mode tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time SCK falling time SCK rising time Pin name tSLIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 30*1 - 75 - 50 - 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode 40*2 ns *1 When PZR = 0. *2 When PZR = 1. Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05671 Rev. *D Page 58 of 86 CY9A130LB Series tSCYC VOH SCK VOH VOL tSHOVI VOH SOT VOL tIVSLI SIN tSLIXI VIH VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05671 Rev. *D Page 59 of 86 CY9A130LB Series CSIO (SPI = 1, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Baud rate Serial clock cycle time Symbol - - tSCYC SCKx SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI SOT → SCK ↓ delay time Serial clock L pulse width Serial clock H pulse width tSOVLI SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx VCC < 2.7 V Conditions Min - Master mode 2.7 V ≤ VCC < 4.5 V Min Max 5 - Max 5 - 4tCYCP - 4tCYCP -40 +40 75 VCC ≥ 4.5 V Min Unit - Max 5 Mbps - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns 0 - 0 - 0 - ns 2tCYCP – 30 - 2tCYCP - 30 - 2tCYCP - 30 - ns tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time SCK falling time SCK rising time Pin name tSLIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 30*1 - 75 - 50 - 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode 40*2 ns *1 When PZR = 0. *2 When PZR = 1. Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05671 Rev. *D Page 60 of 86 CY9A130LB Series tSCYC VOH SCK VOL SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH SCK VIH tR VOH VOL tIVSLE SIN VIL tF * SOT VIL tSHSL VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register Document Number: 002-05671 Rev. *D Page 61 of 86 CY9A130LB Series CSIO (SPI = 1, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) 2.7 V ≤ VCC < 2.7 V VCC ≥ 4.5 V VCC < 4.5 V Unit Min Max Min Max Min Max 5 5 5 Mbps Symbol Pin name - - tSCYC SCKx 4tCYCP - 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN → SCK ↑ setup time tIVSHI 75 - 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI 0 - 0 - 0 - ns 2tCYCP - 30 - 2tCYCP – 30 - 2tCYCP - 30 - ns Parameter Baud rate Serial clock cycle time SOT → SCK ↑ delay time Serial clock L pulse width Serial clock H pulse width tSOVHI SCKx, SINx SCKx, SINx SCKx, SOTx Conditions - Master mode - tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 75 - 50 - 30*1 40*2 ns SIN → SCK ↑ setup time tIVSHE 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns SCK ↑ → SIN hold time SCK falling time SCK rising time tSHIXE tF tR SCKx, SINx SCKx, SINx SCKx SCKx Slave mode *1 When PZR = 0. *2 When PZR = 1. Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05671 Rev. *D Page 62 of 86 CY9A130LB Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL Master mode tR tF tSHSL SCK tSLSH VIH VIH VIL VIL VIL tSLOVE SOT VOH VOL VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode UART external clock input (EXT = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time Symbol tSLSH tSHSL tF tR Conditions CL = 50 pF Min tCYCP + 10 tCYCP + 10 - Unit Max 5 5 Remarks ns ns ns ns tF tR tSHSL SCK V IL Document Number: 002-05671 Rev. *D Value V IH t SLSH V IH V IL V IL V IH Page 63 of 86 CY9A130LB Series 12.4.10 External Input Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Min Condition s Max Unit ADTG Input pulse width tINH, tINL FRCKx ICxx DTTIxX INTxx, NMIX WKUPx - 2tCYCP*1 - ns - 2tCYCP*1 2tCYCP + 100*1 500 500 - ns - ns - ns ns *2 *3 *4 Remarks A/D converter trigger input Free-run timer input clock Input capture Waveform generator External interrupt NMI Deep Standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which A/D converter, Multi-function Timer, External interrupt, Deep Standby mode Controller is connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Timer mode, in RTC mode, in Stop mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode. Document Number: 002-05671 Rev. *D Page 64 of 86 CY9A130LB Series 12.4.11 I2C Timing Parameter SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between STOP condition and START condition Noise filter fSCL (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Standard-mode Fast-mode Unit Remarks Min Max Min Max 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP*4 - 2 tCYCP*4 - ns Symbol tSUSTA tHDDAT tSP Conditions CL = 50 pF, R= (VP/IOL)*1 - *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: 002-05671 Rev. *D Page 65 of 86 CY9A130LB Series 12.4.12 JTAG Timing Parameter Symbol Pin name TMS,TDI setup time tJTAGS TCK, TMS,TDI TMS,TDI hold time tJTAGH TCK, TMS,TDI TDO delay time tJTAGD TCK, TDO Conditions VCC ≥ 4.5 V Min (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Remarks Max 15 - ns 15 - ns VCC ≥ 4.5 V - 30 2.7 V ≤ VCC < 4.5 V VCC < 2.7 V - 45 60 VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V ns Note: − When the external load capacitance CL = 50 pF. TCK TMS/TDI TDO Document Number: 002-05671 Rev. *D Page 66 of 86 CY9A130LB Series 12.5 12-bit A/D Converter Electrical characteristics for the A/D converter Resolution - Pin name - Integral Nonlinearity INL - Differential Nonlinearity DNL - Zero transition voltage VZT Full-scale transition voltage Parameter Symbol Min (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Value Unit Remarks Typ Max 12 bit ± 3.0 LSB AVCC ≥ 2.7 V ± 5.0 LSB AVCC < 2.7 V ± 1.9 LSB AVCC ≥ 2.7 V ± 2.9 LSB AVCC < 2.7 V ± 20 mV AVRH ± mV 20 AVCC ≥ 2.7 V μs AVCC < 2.7 V AVCC ≥ 2.7 V 10 μs AVCC < 2.7 V AVCC ≥ 2.7 V 1000 ns AVCC < 2.7 V ANxx - - VFST ANxx - - Conversion time*1 - - Sampling time*2 tS - Compare clock cycle*3 tCCK - Period of operation enable state transitions Analog input capacity tSTT - - - 1 μs CAIN - - - pF Analog input resistor RAIN - - - Interchannel disparity Analog port input leak current Analog input voltage - - - - 15 0.9 1.6 4.0 4 - ANxx - - 0.3 μA - ANxx - AVRH V Reference voltage - AVR H AVSS 2.7 AVCC - AVCC V 1.0 4.0 0.3 1.2 50 200 - kΩ AVCC ≥ 4.5 V 2.7 V ≤ AVCC < 4.5 V AVCC < 2.7 V LSB AVCC ≥ 2.7 V AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V, HCLK=20 MHz sampling time: 0.3 μs, compare time: 0.7 μs AVCC < 2.7 V, HCLK=20 MHz sampling time: 1.2 μs, compare time: 2.8 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure to set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2). Document Number: 002-05671 Rev. *D Page 67 of 86 CY9A130LB Series ANxx Analog input pin Analog signal source Rext Comparator RAIN CAIN (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: Input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V Input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V Input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V CAIN: Input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-05671 Rev. *D Page 68 of 86 CY9A130LB Series Definition of 12-bit A/D Converter Terms • Resolution • Integral Nonlinearity • Differential Nonlinearity : Analog variation that is recognized by an A/D converter. : Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD Differential Nonlinearity Actual conversion characteristics Ideal characteristics 0x002 0x001 0xN Actual conversion characteristics Ideal characteristics VNT Actual conversion characteristics AVRH AVSS Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: (Actually-measured value) (Actually-measured value) 0x(N-2) VZT (Actually-measured value) AVSS V(N+1)T 0x(N-1) AVRH Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-05671 Rev. *D Page 69 of 86 CY9A130LB Series 12.6 Low-Voltage Detection Characteristics 12.6.1 Low-Voltage Detection Reset (TA = - 40°C to + 85°C) Parameter Symbol Conditions Min 1.43 1.53 1.80 1.90 Value Typ 1.53 1.63 1.93 2.03 Max 1.63 1.73 2.06 2.16 Unit Detected voltage Released voltage Detected voltage Released voltage VDLR VDHR VDLR VDHR LVD stabilization wait time tLVDRW - - - 633 × tCYCP * μs Detection delay time tLVDRD dV/dt ≥ -4mV/µs - - 60 μs SVHR = 0001 SVHR = 0100 V V V V Remarks When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05671 Rev. *D Page 70 of 86 CY9A130LB Series 12.6.2 Interrupt of Low-voltage Detection Normal mode (TA = - 40°C to + 85°C) Parameter Symbol Conditions Min 1.87 1.97 1.96 2.06 2.05 2.15 2.15 2.25 2.24 2.34 2.33 2.43 2.43 2.53 2.61 2.71 2.80 2.90 2.99 3.09 3.36 3.46 3.45 3.55 3.73 3.83 3.83 3.93 3.92 4.02 Value Typ 2.00 2.10 2.10 2.20 2.20 2.30 2.30 2.40 2.40 2.50 2.50 2.60 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 2.13 2.23 2.24 2.34 2.35 2.45 2.45 2.55 2.56 2.66 2.67 2.77 2.77 2.87 2.99 3.09 3.20 3.30 3.41 3.51 3.84 3.94 3.95 4.05 4.27 4.37 4.37 4.47 4.48 4.58 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Max Unit Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI LVD stabilization wait time tLVDIW - - - 633 × tCYCP* μs Detection delay time tLVDID dV/dt ≥ 4mV/µs - - 60 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05671 Rev. *D Page 71 of 86 CY9A130LB Series Low power mode Parameter Symbol Conditions Min 1.80 1.90 1.89 1.99 1.98 2.08 2.07 2.17 2.16 2.26 2.25 2.35 2.34 2.44 2.52 2.62 2.70 2.80 2.88 2.98 3.24 3.34 3.33 3.43 3.60 3.70 3.69 3.79 3.78 3.88 Value Typ 2.00 2.10 2.10 2.20 2.20 2.30 2.30 2.40 2.40 2.50 2.50 2.60 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 (TA = - 40°C to + 85°C) Max 2.20 2.30 2.31 2.41 2.42 2.52 2.53 2.63 2.64 2.74 2.75 2.85 2.86 2.96 3.08 3.18 3.30 3.40 3.52 3.62 3.96 4.06 4.07 4.17 4.40 4.50 4.51 4.61 4.62 4.72 Unit Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL LVD stabilization wait time tLVDILW - - - 8039 × tCYCP * μs Detection delay time tLVDILD dV/dt ≥ 0.4mV/μs - - 800 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05671 Rev. *D Page 72 of 86 CY9A130LB Series 12.7 Flash Memory Write/Erase Characteristics 12.7.1 Write / Erase time (VCC = 2.0V to 5.5V, TA = - 40°C to + 85°C) Parameter Typ* Unit Max* Remarks 1.6 0.4 7.5 2.1 s Includes write time prior to internal erase Half word (16-bit) write time 25 400 μs Not including system-level overhead time. Chip erase time 4 19.2 s Includes write time prior to internal erase Sector erase time Large Sector Small Sector Value *: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write. 12.7.2 Write cycles and data hold time Erase/write cycles (cycle) 1,000 10,000 100,000 Data hold time (year) Remarks 20* 10* 5* *: At average + 85C Document Number: 002-05671 Rev. *D Page 73 of 86 CY9A130LB Series 12.8 Return Time from Low-Power Consumption Mode 12.8.1 Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Typ Value Max* Unit Sleep mode tCYCC High-speed CR Timer mode, Main Timer mode, PLL Timer mode 40 80 μs 630 1260 μs 630 1260 μs 1083 2100 μs 1099 2127 μs Low-speed CR Timer mode Sub Timer mode tICNT RTC mode, Stop mode Deep Standby RTC mode Deep Standby Stop mode Remarks μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-05671 Rev. *D Page 74 of 86 CY9A130LB Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. Document Number: 002-05671 Rev. *D Page 75 of 86 CY9A130LB Series 12.8.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Typ Value Unit Max* 359 647 μs 359 647 μs 929 1787 μs Sub Timer mode 929 1787 μs RTC/Stop mode 1099 2127 μs Deep Standby RTC mode Deep Standby Stop mode 1099 2127 μs Low-speed CR Timer mode tRCNT Remarks *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation Document Number: 002-05671 Rev. *D Start Page 76 of 86 CY9A130LB Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − − − − − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-05671 Rev. *D Page 77 of 86 CY9A130LB Series 13. Ordering Information Part number On-chip Flash memory On-chip SRAM CY9AF131KBPMC-G-SNE2 64 Kbyte 8 Kbyte CY9AF132KBPMC-G-SNE2 128 Kbyte 8 Kbyte CY9AF131KBQN-G-AVE2 64 Kbyte 8 Kbyte CY9AF132KBQN-G-AVE2 128 Kbyte 8 Kbyte CY9AF131LBPMC1-G-SNE2 64 Kbyte 8 Kbyte CY9AF132LBPMC1-G-SNE2 128 Kbyte 8 Kbyte CY9AF131LBPMC-G-SNE2 64 Kbyte 8 Kbyte CY9AF132LBPMC-G-UNE2 128 Kbyte 8 Kbyte CY9AF131LBQN-G-AVE2 64 Kbyte 8 Kbyte CY9AF132LBQN-G-AVE2 128 Kbyte 8 Kbyte Document Number: 002-05671 Rev. *D Package Packing Plastic  LQFP (0.5mm pitch), 48-pin (LQA048) Plastic  QFN (0.5mm pitch), 48-pin (VNA048) Plastic  LQFP (0.5mm pitch), 64-pin (LQD064) Tray Plastic  LQFP (0.65mm pitch), 64-pin (LQG064) Plastic  QFN (0.5mm pitch), 64-pin (VNC064) Page 78 of 86 CY9A130LB Series 14. Package Dimensions Package Type Package Code LQFP 48 (0.5mm pitch) LQA048 4 D 5 7 D1 36 25 37 24 E1 24 37 13 48 E 5 7 3 36 25 4 6 48 13 1 12 e 1 12 2 5 7 0.10 C A-B D 3 0.20 C A-B D b 0.80 C A-B D 8 2 A θ A A' 0.80 C SYM BOL L1 0.25 L A1 c b 10 SECTION A-A' D IM EN SIONS M IN . N OM . M AX. 0.00 0.20 1.70 A A1 9 SEATING PLANE b 0.15 0.27 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC e 0.50 BSC E 9.00 BSC E1 7.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° 002-13731 ** PACKAGE OUTLINE, 48 LEAD LQFP 7.0X7.0X1.7 M M LQA048 REV** Document Number: 002-05671 Rev. *D Page 79 of 86 CY9A130LB Series Package Type Package Code QFN 48 VNA048 0.10 D C A B D2 A 25 36 0.10 C 24 2X 0.10 37 (ND-1)× e E C A B E2 5 13 9 INDEX M ARK 8 48 12 R 1 L B TOP VIEW e b 4 0.10 C 0.10 0.05 C A B C BOTTOM VIEW 2X 0.10 C A 0.05 C SEATING PLANE A1 9 C SIDE VIEW DIMENSIONS SYMBOL MIN. NOM . A A1 0.90 0.00 0.05 D 7.00 BSC E 7.00 BSC b 0.20 0.25 D2 5.50 BSC E2 5.50 BSC e 0.50 BSC R 0.20 REF L MAX. 0.35 0.40 NOTE 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. DIMENSION "b"APPLIES TO METALLIZED TERMINAL AND IS M EASURED BETW EEN 0.15 AND 0.30m m FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUSAREA. 5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE. 0.30 6. MAX. PACKAGE W ARPAGE IS 0.05m m . 7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP W ILL BE LOCATED W ITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS W ELL AS THE TERMINALS. 0.45 10. JEDEC SPEC IFICATIONNO . REF : N/A PACKAGE OUTLINE, 48 LEAD QFN 7.0X7.0X0.9 M M VNA048 5.5X5.5 M M EPAD (SAWN) REV** 002-15528 ** Document Number: 002-05671 Rev. *D Page 80 of 86 CY9A130LB Series Package Type Package Code LQFP 64 (0.5mm pitch) LQD064 4 D D1 48 5 7 33 33 32 49 48 32 49 17 64 5 7 E1 E 4 3 6 17 64 1 16 e 1 16 2 5 7 3 BOTTOM VIEW 0.1 0 C A-B D 0.2 0 C A-B D b 0.0 8 C A-B D 8 TOP VIEW A 2 9 A A' 0.0 8 C SEATING PLAN E L1 0.25 L A1 c b SECTION A-A' 10 SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. A A1 1. 70 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E 12.00 BSC. E1 10.00 BSC. L 0.45 0.60 0.75 L1 0.30 0.50 0.70 002-11499 ** PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 M M LQD064 Rev** Document Number: 002-05671 Rev. *D Page 81 of 86 CY9A130LB Series Package Type Package Code LQFP 64 (0.65mm pitch) LQG064 D D1 48 4 5 7 33 33 32 49 48 32 49 17 64 E1 E 5 7 4 3 17 64 1 16 e 0.20 1 16 2 5 7 3 BOTTOM VIEW 0.10 C A-B D C A-B D b 0.13 C A-B D 8 TOP VIEW 2 A θ A A' 0.10 C SEATI N G PLA N E 0.2 5 L1 L 9 A1 10 c b SECTION A -A' SIDE VIEW SYM BOL DIM ENSION M IN. NOM . M AX. 1.70 A A1 0.00 b 0.27 0.20 c 0.09 0.32 0.37 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E 14.00 BSC E1 12.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 64 LEAD LQFP 12.0X12.0X1.7 M M LQG064 REV** 002-13881 ** Document Number: 002-05671 Rev. *D Page 82 of 86 CY9A130LB Series Package Type Package Code QFN 64 VNC064 0.10 D 0.10 C 2X D2 A 48 33 33 32 49 C A B 48 32 49 0.10 C A B 5 (ND-1)× e E 17 64 1 INDEXMARK 8 E2 16 16 9 B e L 0.10 C TOP VIEW 64 17 BOTTOM VIEW 2X b 1 4 0.10 0.05 C A B C 0.10 C A 0.05 C SEATINGPLANE C A1 SIDE VIEW DIM ENSIONS NOTES: SYMBOL M IN. NOM . M AX. A A1 0.90 0.00 0.05 D 9.00 BSC E 9.00 BSC 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DIM ENSIONING AND TOLERANCING CONFORM S TO ASM E Y14.5M -1994. 3. N IS THE TOTAL NUM BER OF TERM INALS. 4 b 0.20 0.25 0.30 D2 6.00 BSC E2 6.00 BSC 6. 7. e 0.50 BSC 8 R 0.20 REF L 0.35 0.40 N 64 ND 16 5 9 0.45 DIM ENSION "b "APPLIES TO M ETALLIZED TERM INAL AND IS M EASURED BETW EEN 0.15 AND 0.30m m FROM TERM INAL TIP. IF THE TERM INAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERM INAL, THE DIM ENSION "b "SHOULD NOT BE M EASURED IN THAT RADIUS AREA. ND REFERS TO THE NUM BER OF TERM INALS ON D SIDE OR E SIDE. M AX. PACKAGE W ARPAGE IS 0.05m m . M AXIM UM ALLOW ABLE BURR IS 0.076m m IN ALL DIRECTIONS. PIN #1 ID ON TOP W ILL BE LOCATED W ITHIN THE INDICATED ZONE. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS W ELL AS THE TERM INALS. PACKAGE OUTLINE, 64 LEAD QFN 9.0X9.0X0.9 M M VNC064 6.0X6.0 M M EPAD (SAW N) Rev*.* 002-13234 ** Document Number: 002-05671 Rev. *D Page 83 of 86 CY9A130LB Series 15. Major Changes Spansion Publication Number: DS706-00066 Page Section Revision 1.0 Revision 2.0 Features 2 · On-chip Memories 33 Handling Devices Change Results Initial release Changed the description of on-chip SRAM Added "· Stabilizing power supply voltage" Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board." 33 Handling Devices Crystal oscillator circuit 37 Memory Map Memory map(2) Added the summary of Flash memory sector 47 - 49 Electrical Characteristics 3. DC Characteristics (1) Current rating · Changed the table format · Added Timer mode current · Added Flash Memory Current · Moved A/D Converter Current 53 54 Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing 56 - 63 Electrical Characteristics 4. AC Characteristics (8) CSIO/UART Timing 67 Electrical Characteristics 5. 12bit A/D Converter 70 73 74 - 77 78 Electrical Characteristics 7. Low-voltage Detection Characteristics Electrical Characteristics 8. Flash Memory Write/Erase Characteristics Electrical Characteristics 9. Return Time from Low-Power Consumption Mode Ordering Information · Added the figure of Main PLL connection · Changed the figure of timing · Changed from Reset release delay time(tOND) to Time until releasing Power-on reset(tPRT) · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode · Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage · Added Conversion time at AVCC < 2.7 V Deleted the figure Change to the erase time of include write time prior to internal erase Added Return Time from Low-Power Consumption Mode Changed notation of part number NOTE: Please see “Document History” about later revised information. Document Number: 002-05671 Rev. *D Page 84 of 86 CY9A130LB Series Document History Document Title: CY9A130LB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller Document Number: 002-05671 Revision ECN ** - Orig. of Submission Change Date AKIH Description of Change 06/09/2015 Migrated to Cypress and assigned document number 002-05671. No change to document contents. *A 5162460 AKIH 03/10/2016 Updated to Cypress template. *B 5742425 YSKA 05/23/2017 Adapted new Cypress logo Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed starting count value from 01 to 00. Deleted “second, or day of the week” in the Interrupt function. Changed package code as the following in chapter: 2. Packages 3. Pin Assignment 13. Ordering Information 14. Package Dimensions. FPT-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048 FTP-64P-M38 -> LQD064, FPT-64P-M39 -> LQG064, LCC-64P-M24 -> VNC064 Corrected “J-TAG" to “JTAG" in 4. List of Pin Functions. Added Note for JTAG pin in 4. List of Pin Functions. Added the Baud rate spec in 12.4.9 CSIO/UART Timing. *C 5883538 HUAL 09/14/2017 Modified Part number as below due to Fab transfer MB9AF132LBPMC-G-SNE2 => MB9AF132LBPMC-G-UNE2 *D 6575948 XITO 05/17/2019 Updated Document Title to read as “CY9A130LB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller”. Replaced “MB9A130LB Series” with “CY9A130LB Series” in all instances across the document. Updated Ordering Information: Updated part numbers. Updated to new template. Completing Sunset Review. Document Number: 002-05671 Rev. *D Page 85 of 86 CY9A130LB Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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