0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
MB9AF311KQN-G-AVE2

MB9AF311KQN-G-AVE2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    WFQFN48_EP

  • 描述:

    ICMCU32BIT96KBFLASH48QFN

  • 数据手册
  • 价格&库存
MB9AF311KQN-G-AVE2 数据手册
The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB9A310K Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller The MB9A310K Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and low cost. These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I 2C, LIN). The products which are described in this Datasheet are placed into TYPE5 product categories in "FM3 Family Peripheral Manual". Features 32-bit ARM Cortex-M3 Core [USB device]  Processor version: r2p1  USB2.0 Full-Speed supported  Up to 40MHz Frequency Operation  Max 6 EndPoint supported  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] This Series are based on two independent on-chip Flash memories.  MainFlash  EndPoint 0 is control transfer 1, 2 can be selected Bulk-transfer, Interrupttransfer or Isochronous-transfer  EndPoint 3 to 5 can be selected Bulk-transfer or Interrupttransfer  EndPoint 1 to 5 is comprised Double Buffer  The size of each EndPoint is as follows. • EndPoint 0, 2 to 5: 64 bytes • EndPoint 1: 256 bytes  EndPoint [USB host]  USB2.0 Full/Low-speed supported  Bulk-transfer, interrupt-transfer and Isochronous-transfer  Up to 128Kbyte cycle: 0 wait-cycle  Security function for code protection support  Read  USB Device connected/dis-connected automatically detect  WorkFlash  IN/OUT token handshake packet automatically  32Kbyte  Read cycle: 0 wait-cycle  Security function is shared with code protection  Max 256-byte packet-length supported  Wake-up function supported [SRAM] Multi-function Serial Interface (Max 4 channels) This Series contain a total of up to 16Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  2 channels with 16-steps × 9-bits FIFO (ch.0, ch.1), 2  SRAM0: 8 Kbyte  SRAM1: 8 Kbyte USB Interface USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. Cypress Semiconductor Corporation Document Number: 002-05625 Rev.*B • channels without FIFO (ch.3, ch.5)  Operation mode is selectable from the followings for each channel. (In ch.5, only UART and LIN are available.)  UART  CSIO  LIN  I2 C 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 22, 2017 MB9A310K Series [UART] A/D Converter (Max 8 channels)  Full-duplex double buffer  Selection with or without parity supported [12-bit A/D Converter]  Successive Approximation Register type  Built-in dedicated baud rate generator  Built-in 2 unit  External clock available as a serial clock  Conversion time: 1.0 μs@5 V  Hardware Flow control: Automatically control the  Priority conversion available (priority at 2 levels) transmission by CTS/RTS (only ch.4)  Various error detect functions available (parity errors, framing errors, and overrun errors) [CSIO]  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)  Full-duplex double buffer Base Timer (Max 8 channels)  Built-in dedicated baud rate generator Operation mode is selectable from the followings for each channel.  Overrun error detect function available  16-bit PWM timer [LIN]  16-bit PPG timer  LIN protocol Rev.2.1 supported  16-/32-bit reload timer  Full-duplex double buffer  16-/32-bit PWC timer  Master/Slave mode supported General Purpose I/O Port  LIN break field generate (can be changed 13 to 16-bit This series can use its pins as General Purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. length)  LIN break delimiter generate (can be changed 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors) [I2C]  Standard mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported DMA Controller (4 channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the builtin peripherals  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up 36 fast General Purpose I/O Ports  Some pin is 5V tolerant I/O. See "Pin Description" to confirm the corresponding pins. Multi-function Timer The Multi-function timer is composed of the following blocks.  16-bit free-run timer × 3 ch.  Input capture × 4 ch.  Output compare × 6 ch.  Transfer address area: 32-bit (4 Gbyte)  A/D activating compare × 3 ch.  Transfer mode: Block transfer/Burst transfer/Demand  Waveform generator × 3 ch. transfer  16-bit PPG timer × 3 ch.  Transfer data type: byte/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function Document Number: 002-05625 Rev.*B Page 2 of 87 MB9A310K Series  DTIF (Motor emergency stop) interrupt function CRC (Cyclic Redundancy Check) Accelerator Real-time clock (RTC) The CRC accelerator helps a verify data transmission or storage integrity. The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  Interrupt function with specifying date and time  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  CCITT CRC16 Generator Polynomial: 0x1021 Clock and Reset [Clocks]  Capable of rewriting the time with continuing the time count. Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.  Leap year automatic count is available.  Main Clock: 4 MHz to 48 MHz Quadrature Position/Revolution Counter (QPRC)  Sub Clock: 32.768 kHz The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  The detection edge of the three external event input pins  Main PLL Clock AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers [Resets]  Reset requests from INITX pin  Power on reset  Software reset Dual Timer (32-/16-bit Down Counter)  Watchdog timers reset The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Low-voltage detector reset  Free-running  Clock supervisor reset Clock Super Visor (CSV)  Periodic ( = Reload) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  One-shot  External OSC clock failure (clock stop) is detected, reset is Watch Counter The Watch counter is used for wake up from Low Power Consumption mode. asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted.  Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz Low-Voltage Detector (LVD) External Interrupt Controller Unit This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset.  Up to 6 external interrupt input pin  Include one non-maskable interrupt (NMI) Watchdog Timer (2channels)  LVD1: error reporting via interrupt  LVD2: auto-reset operation A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, ”Hardware" watchdog is active in any power saving mode except RTC and STOP and Deep standby RTC and Deep stand-by STOP. Document Number: 002-05625 Rev.*B Page 3 of 87 MB9A310K Series Low Power Consumption Mode Power Supply Six Low Power Consumption modes supported.  Wide range voltage:  SLEEP  TIMER  RTC VCC = 2.7 V to 5.5 V  Power supply for USB I/O: USBVCC0 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  STOP  Deep stand-by RTC  Deep stand-by STOP Debug Serial Wire JTAG Debug Port (SWJ-DP) Document Number: 002-05625 Rev.*B Page 4 of 87 MB9A310K Series Contents 1. Product Lineup............................................................................................................................................................. 7 2. Packages ............................................................................................................................................................. 8 3. Pin Assignment ............................................................................................................................................................ 9 4. List of Pin Functions ................................................................................................................................................. 12 5. I/O Circuit Type .......................................................................................................................................................... 21 6. Handling Precautions ................................................................................................................................................ 26 6.1 Precautions for Product Design.................................................................................................................................. 26 6.2 Precautions for Package Mounting ............................................................................................................................ 27 6.3 Precautions for Use Environment ............................................................................................................................... 28 7. Handling Devices ....................................................................................................................................................... 29 8. Block Diagram ........................................................................................................................................................... 32 9. Memory Size ........................................................................................................................................................... 32 10. Memory Map ........................................................................................................................................................... 33 11. Pin Status in Each CPU State ................................................................................................................................... 36 12. Electrical Characteristics .......................................................................................................................................... 42 12.1 Absolute Maximum Ratings........................................................................................................................................ 42 12.2 Recommended Operating Conditions ........................................................................................................................ 44 12.3 DC Characteristics ..................................................................................................................................................... 45 12.3.1 Current Rating ............................................................................................................................................................ 45 12.3.2 Pin Characteristics ..................................................................................................................................................... 48 12.4 AC Characteristics ..................................................................................................................................................... 49 12.4.1 Main Clock Input Characteristics ................................................................................................................................ 49 12.4.2 Sub Clock Input Characteristics ................................................................................................................................. 50 12.4.3 Internal CR Oscillation Characteristics ....................................................................................................................... 50 12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL .................................. 51 12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)...................................................... 51 12.4.6 Reset Input Characteristics ........................................................................................................................................ 52 12.4.7 Power-on Reset Timing .............................................................................................................................................. 52 12.4.8 Base Timer Input Timing ............................................................................................................................................ 53 12.4.9 CSIO/UART Timing .................................................................................................................................................... 54 12.4.10 External Input Timing ................................................................................................................................................. 62 12.4.11 Quadrature Position/Revolution Counter timing ......................................................................................................... 63 12.4.12 I2C Timing .................................................................................................................................................................. 65 12.4.13 JTAG Timing .............................................................................................................................................................. 66 12.5 12-bit A/D Converter .................................................................................................................................................. 67 12.6 USB Characteristics ................................................................................................................................................... 70 12.7 Low-voltage Detection Characteristics ....................................................................................................................... 74 12.7.1 Low-voltage Detection Reset ..................................................................................................................................... 74 12.7.2 Interrupt of Low-voltage Detection ............................................................................................................................. 74 12.8 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 75 12.8.1 Write / Erase time....................................................................................................................................................... 75 12.8.2 Erase/write cycles and data hold time ........................................................................................................................ 75 12.9 WorkFlash Memory Write/Erase Characteristics ........................................................................................................ 75 12.9.1 Write / Erase time....................................................................................................................................................... 75 12.9.2 Erase/write cycles and data hold time ........................................................................................................................ 75 12.10 Return Time from Low-Power Consumption Mode .................................................................................................... 76 12.10.1 Return Factor: Interrupt/WKUP .................................................................................................................................. 76 12.10.2 Return Factor: Reset .................................................................................................................................................. 78 13. Ordering Information ................................................................................................................................................. 80 14. Package Dimensions ................................................................................................................................................. 81 15. Major Changes ........................................................................................................................................................... 84 Document Number: 002-05625 Rev.*B Page 5 of 87 MB9A310K Series Document History ........................................................................................................................................................... 86 Sales, Solutions, and Legal Information ............................................................................................................................. 87 Document Number: 002-05625 Rev.*B Page 6 of 87 MB9A310K Series 1. Product Lineup Memory size Product name On-chip Flash memory MB9AF311K MB9AF312K MainFlash 64 Kbyte 128 Kbyte WorkFlash 32 Kbyte 32 Kbyte SRAM0 8 Kbyte 8 Kbyte On-chip SRAM SRAM1 8 Kbyte 8 Kbyte Total 16 Kbyte 16 Kbyte Function Product name Pin count CPU Freq. Power supply voltage range USB2.0 (Device/Host) DMAC Multi-function Serial Interface (UART/CSIO/LIN/I2C) Base Timer (PWC/ Reload timer/PWM/PPG) A/D activation 3 ch. compare Input capture 4 ch. Free-run timer 3 ch. MFOutput Timer 6 ch. compare Waveform 3 ch. generator PPG 3 ch. QPRC Dual Timer Real-time clock Watch Counter CRC Accelerator Watchdog timer External Interrupts General Purpose I/O ports 12-bit A/D converter CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in OSC Low-speed Debug Function MB9AF311K MB9AF312K 48/52 Cortex-M3 40 MHz 2.7 V to 5.5 V (USBVCC: 3.0 V to 3.6 V) 1 ch. (Max) 4 ch. (Max) 4 ch. (Max) with 16-steps × 9-bits FIFO : ch.0, ch.1 without FIFO : ch.3, ch.5 (In ch.5, only UART and LIN are available.) 8 ch. (Max) 1 unit (Max) 1 ch. (Max) 1 unit 1 unit 1 unit Yes 1 ch. (SW) + 1 ch. (HW) 6 pins (Max) + NMI × 1 36 pins (Max) 8 ch. (2 units) Yes 2 ch. 4 MHz 100 kHz SWJ-DP Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the General I/O port according to your function use. See "12. Electrical Characteristics 12.4. AC Characteristics" for accuracy of built-in CR. Document Number: 002-05625 Rev.*B Page 7 of 87 MB9A310K Series 2. Packages Product name Package MB9AF311K MB9AF312K LQFP: LQA048 (0.5 mm pitch)  QFN: VNA048 (0.5 mm pitch)  LQFP: LQC052 (0.65 mm pitch)  : Supported Note: − See "14.Package Dimensions" for detailed information on each package. Document Number: 002-05625 Rev.*B Page 8 of 87 MB9A310K Series 3. Pin Assignment LQA048 VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3 P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P21/SIN0_0/INT06_1/WKUP2 P50/INT00_0/AIN0_2/SIN3_1 2 35 P22/AN07/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 34 P23/AN06/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 33 AVSS P39/DTTI0X_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/IC03_2 P3C/RTO02_0/TIOA2_1 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1 VSS 12 25 P10/AN00 13 14 15 16 17 18 19 20 21 22 23 24 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 48 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05625 Rev.*B Page 9 of 87 MB9A310K Series VNA048 VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3 P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P21/SIN0_0/INT06_1/WKUP2 P50/INT00_0/AIN0_2/SIN3_1 2 35 P22/AN07/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 34 P23/AN06/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 33 AVSS P39/DTTI0X_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/IC03_2 P3C/RTO02_0/TIOA2_1 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1 VSS 12 25 P10/AN00 13 14 15 16 17 18 19 20 21 22 23 24 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 48 Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05625 Rev.*B Page 10 of 87 MB9A310K Series LQC052 VSS P81/UDP0 P80/UDM0 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3 P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX NC 52 51 50 49 48 47 46 45 44 43 42 41 40 (TOP VIEW) VCC 1 39 P21/SIN0_0/INT06_1/WKUP2 P50/INT00_0/AIN0_2/SIN3_1 2 38 P22/AN07/SOT0_0/TIOB7_1 P51/INT01_0/BIN0_2/SOT3_1 3 37 P23/AN06/SCK0_0/TIOA7_1 P52/INT02_0/ZIN0_2/SCK3_1 4 36 NC NC 5 35 AVSS P39/DTTI0X_0/ADTG_2 6 34 AVRH P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 7 33 AVCC P3B/RTO01_0/TIOA1_1 8 32 P15/AN05/SOT0_1/IC03_2 P3C/RTO02_0/TIOA2_1 9 31 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 10 30 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1 11 29 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 12 28 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1 VSS 13 27 P10/AN00 14 15 16 17 18 19 20 21 22 23 24 25 26 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 NC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 52 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05625 Rev.*B Page 11 of 87 MB9A310K Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-48 QFN-48 LQFP-52 1 1 Pin Name I/O circuit type VCC Pin state type - P50 2 2 INT00_0 AIN0_2 I *1 H I *1 H I *1 H SIN3_1 P51 3 3 INT01_0 BIN0_2 SOT3_1 P52 4 4 INT02_0 ZIN0_2 SCK3_1 - 5 NC - P39 5 6 DTTI0X_0 E I G I G I G I G I G I G I ADTG_2 P3A RTO00_0 6 7 TIOA0_1 RTCCO_2 SUBOUT_2 P3B 7 8 RTO01_0 TIOA1_1 P3C 8 9 RTO02_0 TIOA2_1 P3D 9 10 RTO03_0 TIOA3_1 P3E 10 11 RTO04_0 TIOA4_1 P3F 11 12 RTO05_0 TIOA5_1 Document Number: 002-05625 Rev.*B Page 12 of 87 MB9A310K Series Pin No LQFP-48 QFN-48 LQFP-52 12 13 13 14 15 16 16 17 17 18 18 19 19 20 - 21 20 22 21 23 22 24 23 25 24 26 25 27 Pin Name I/O circuit type Pin state type VSS - 14 C - 15 VCC - P46 X0A P47 X1A INITX P49 TIOB0_0 P4A TIOB1_0 D M D N B C E I E I NC PE0 MD1 MD0 PE2 X0 PE3 X1 C P J D A A A B VSS P10 AN00 F K F F F K F K P11 AN01 SIN1_1 26 28 INT02_1 FRCK0_2 IC02_0 WKUP1 P12 27 29 AN02 SOT1_1 IC00_2 P13 AN03 28 30 SCK1_1 IC01_2 RTCCO_1 SUBOUT_1 Document Number: 002-05625 Rev.*B Page 13 of 87 MB9A310K Series Pin No LQFP-48 QFN-48 LQFP-52 Pin Name I/O circuit type Pin state type F L F K P14 AN04 29 31 SIN0_1 INT03_1 IC02_2 30 32 31 32 33 - 33 34 35 36 34 37 35 38 36 39 - 40 37 41 38 42 39 43 40 44 41 45 42 46 Document Number: 002-05625 Rev.*B P15 AN05 SOT0_1 IC03_2 AVCC AVRH AVSS NC P23 AN06 SCK0_0 TIOA7_1 P22 AN07 SOT0_0 TIOB7_1 P21 SIN0_0 INT06_1 WKUP2 NC P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 - F K F K E G E E E E E E E E E E E J Page 14 of 87 MB9A310K Series Pin No LQFP-48 QFN-48 LQFP-52 43 47 44 48 45 49 46 50 47 51 48 52 Pin Name P61 SOT5_0 TIOB2_2 UHCONX DTTI0X_2 P60 SIN5_0 TIOA2_2 INT15_1 IC00_0 WKUP3 USBVCC P80 UDM0 P81 UDP0 VSS I/O circuit type Pin state Type E I I *1 G H O H O - *1: 5V tolerant I/O Document Number: 002-05625 Rev.*B Page 15 of 87 MB9A310K Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module Pin name ADC ADTG_2 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 TIOA0_1 TIOB0_0 TIOA1_1 TIOB1_0 TIOA2_1 TIOA2_2 TIOB2_2 A/D converter external trigger input pin Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 7 Debugger External Interrupt Function Pin No LQFP-48 LQFP-52 QFN-48 Base timer ch.2 TIOB pin 5 25 26 27 28 29 30 34 35 6 18 7 19 8 44 43 6 27 28 29 30 31 32 37 38 7 19 8 20 9 48 47 TIOA3_1 Base timer ch.3 TIOA pin 9 10 TIOA4_1 Base timer ch.4 TIOA pin 10 11 TIOA5_1 Base timer ch.5 TIOA pin 11 12 TIOA7_1 TIOB7_1 SWCLK SWDIO SWO TCK TDI TDO TMS TRSTX INT00_0 INT01_0 INT02_0 INT02_1 INT03_1 INT06_1 INT15_1 NMIX Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input/output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin JTAG test reset Input pin External interrupt request 00 input pin External interrupt request 01 input pin 34 35 38 40 41 38 39 41 40 37 2 3 4 26 29 36 44 42 37 38 42 44 45 42 43 45 44 41 2 3 4 28 31 39 48 46 Document Number: 002-05625 Rev.*B A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 06 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin Page 16 of 87 MB9A310K Series Module Pin name GPIO P00 P01 P02 P03 P04 P0F P10 P11 P12 P13 P14 P15 P21 P22 P23 P39 P3A P3B P3C P3D P3E P3F P46 P47 P49 P4A P50 P51 P52 P60 P61 P80 P81 PE0 PE2 PE3 Document Number: 002-05625 Rev.*B Function General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Pin No LQFP-48 LQFP-52 QFN-48 37 38 39 40 41 42 25 26 27 28 29 30 36 35 34 5 6 7 8 9 10 11 15 16 18 19 2 3 4 44 43 46 47 20 22 23 41 42 43 44 45 46 27 28 29 30 31 32 39 38 37 6 7 8 9 10 11 12 16 17 19 20 2 3 4 48 47 50 51 22 24 25 Page 17 of 87 MB9A310K Series Module Pin name Multi- function Serial 0 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Multi- function Serial 1 SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) Multi- function Serial 3 SIN3_1 SOT3_1 (SDA3_1) SCK3_1 (SCL3_1) Multi- function Serial 5 SIN5_0 SOT5_0 Document Number: 002-05625 Rev.*B Function Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation modes 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/LIN (operation modes 0, 1, 3). Pin No. LQFP-48 LQFP-52 QFN-48 36 29 39 31 35 38 30 32 34 37 26 28 27 29 28 30 2 2 3 3 4 4 44 48 43 47 Page 18 of 87 MB9A310K Series Module Pin name Multi- function Timer 0 DTTI0X_0 DTTI0X_2 FRCK0_2 IC00_0 IC00_2 IC01_2 IC02_0 IC02_2 IC03_2 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) Quadrature Position/ Revolution Counter 0 Real-time clock Function Input signal controlling wave form generator outputs RTO00 to RTO05 of multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 16-bit input capture ch.0 input pin of multi-function timer 0. ICxx describes channel number. Wave form generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 6 43 26 44 27 28 26 29 30 47 28 48 29 30 28 31 32 6 7 7 8 8 9 9 10 10 11 11 12 QPRC ch.0 AIN input pin 2 2 BIN0_2 QPRC ch.0 BIN input pin 3 3 ZIN0_2 QPRC ch.0 ZIN input pin 4 4 42 46 28 30 RTCCO_0 0.5 seconds pulse output pin of Real-time clock RTCCO_2 6 7 SUBOUT_0 42 46 28 30 6 7 SUBOUT_1 Sub clock output pin SUBOUT_2 USB 5 AIN0_2 RTCCO_1 Low Power Consumption Mode Pin No LQFP-48 LQFP-52 QFN-48 WKUP0 Deep stand-by mode return signal input pin 0 42 46 WKUP1 Deep stand-by mode return signal input pin 1 26 28 WKUP2 Deep stand-by mode return signal input pin 2 36 39 WKUP3 Deep stand-by mode return signal input pin 3 44 48 UDM0 USB ch.0 device/host D – pin 46 50 UDP0 USB ch.0 device/host D + pin 47 51 USB external pull-up control pin 43 47 UHCONX Document Number: 002-05625 Rev.*B Page 19 of 87 MB9A310K Series Module Reset Pin name VCC VCC USBVCC VSS VSS VSS X0 X0A X1 X1A CROUT_1 Built-in high-speed CR-osc clock output port 42 46 AVCC A/D converter analog power pin 31 33 AVRH A/D converter analog reference voltage input pin 32 34 AVSS A/D converter GND pin 33 35 Power stabilization capacity pin 13 14 MD0 MD1 GND Clock Analog Power Analog GND C pin NC pin Pin No LQFP-48 LQFP-52 QFN-48 External Reset Input pin. A reset is valid when INITX = "L". Mode 0 pin. During normal operation, MD0 = "L" must be input. During serial programming to Flash memory, MD0 = "H" must be input. Mode 1 pin. During serial programming to Flash memory, MD1 = "L" must be input. Power supply Pin Power supply Pin 3.3V Power supply port for USB I/O GND Pin GND Pin GND Pin Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin INITX Mode Power Function C 17 18 21 23 20 22 1 14 45 12 24 48 22 15 23 16 1 15 49 13 26 52 24 16 25 17 NC NC pin. NC pin should be kept open. - 5 NC NC pin. NC pin should be kept open. - 21 NC NC pin. NC pin should be kept open. - 36 NC NC pin. NC pin should be kept open. - 40 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05625 Rev.*B Page 20 of 87 MB9A310K Series 5. I/O Circuit Type Type Circuit Remarks It is possible to select the main oscillation / GPIO function When the main oscillation is selected. − Oscillation feedback resistor : Approximately 1 MΩ A Pull-up resistor − P-ch P-ch Digital output X1 N-ch Digital output R With Standby mode control When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor: Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − CMOS level hysteresis input − Pull-up resistor : Approximately 50 kΩ Pull-up resistor control Digital input Standby mode Control Feedback Clock input resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control B Pull-up resistor Digital input Document Number: 002-05625 Rev.*B Page 21 of 87 MB9A310K Series Type Circuit Remarks C Digital input − Open drain output − CMOS level hysteresis input Digital output N-ch It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. − Oscillation feedback resistor : Approximately 5 MΩ D Pull-up resistor P-ch P-ch Digital output With Standby mode control When the GPIO is selected. − CMOS level output. X1A N-ch − Digital output R − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA Pull-up resistor control Digital input Standby mode Control Feedback Clock input resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control Document Number: 002-05625 Rev.*B Page 22 of 87 MB9A310K Series Type Circuit Remarks E P-ch P-ch N-ch − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is always off − +B input is available − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is always off − +B input is available Digital output Digital output R Pull-up resistor control Digital input Standby mode Control F P-ch P-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode Control Analog input Input control Document Number: 002-05625 Rev.*B Page 23 of 87 MB9A310K Series Type Circuit Remarks G P-ch Digital output P-ch N-ch − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA − +B input is available Digital output R Pull-up resistor control Digital input Standby mode Control H GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output UDP/P81 USB Full-speed/Low-speed control It is possible to select the USB I/O / GPIO function. When the USB I/O is selected. − Full-speed, Low-speed control When the GPIO is selected. − CMOS level output − CMOS level hysteresis input − With standby mode control IOH = -20.5 mA, IOL = 18.5 mA UDP input Differential UDM/P80 Differential input USB/GPIO select UDM input UDM output USB Digital input/output direction GPIO Digital input GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: 002-05625 Rev.*B Page 24 of 87 MB9A310K Series Type Circuit Remarks I P-ch P-ch N-ch Digital output − CMOS level output − CMOS level hysteresis input − 5V tolerant − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − Available to control of PZR registers. − CMOS level hysteresis input Digital output R Pull-up resistor control Digital input Standby mode Control J Mode input Document Number: 002-05625 Rev.*B Page 25 of 87 MB9A310K Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the Datasheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-05625 Rev.*B Page 26 of 87 MB9A310K Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Document Number: 002-05625 Rev.*B Page 27 of 87 MB9A310K Series Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05625 Rev.*B Page 28 of 87 MB9A310K Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins and GND pins, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A pin should be kept open.  Example of Using an External Clock Device X0(X0A) Open X1(X1A) Handling when using Multi-function serial pin as I2C pin If it is using Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I 2C pins need to keep the electrical characteristic like other pins and not to connect to external I 2C bus system with power OFF. Document Number: 002-05625 Rev.*B Page 29 of 87 MB9A310K Series C pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. NC pins NC pin should be kept open. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on: VCC → USBVCC VCC → AVCC → AVRH Turning off: AVRH → AVCC → VCC USBVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Document Number: 002-05625 Rev.*B Page 30 of 87 MB9A310K Series Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Document Number: 002-05625 Rev.*B Page 31 of 87 MB9A310K Series 8. Block Diagram MB9AF311K, F312K TRSTX,TCK, TDI,TMS TDO SRAM0 8 Kbyte SWJ-DP ROM Table SRAM1 8 Kbyte Multi-layer AHB (Max 42 MHz) Cortex-M3 Core I @40 MHz(Max) D NVIC Sys AHB-APB Bridge: APB0(Max 42 MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) MainFlash I/F Security MainFlash 64 Kbyte/ 128 Kbyte WorkFlash I/F WorkFlash 32 Kbyte USB2.0 PHY (Host/ Func) USBVCC UDP0,UDM0 UHCONX DMAC 4ch. CSV X0 X1 X0A Main Osc Sub Osc PLL AHB-AHB Bridge CLK Source Clock CR 4MHz CR 100kHz CROUT AVCC, AVSS, AVRH USB Clock Ctrl 12-bit A/D Converter Unit 0 Power-On Reset AN[07:00] Unit 1 LVD Ctrl ADTG_2 AIN0 BIN0 ZIN0 QPRC 1ch. A/D Activation Compare 3ch. IC0x FRCKx 16-bit Input Capture 4ch. 16-bit Free-Run Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTOx Deep Standby Ctrl Waveform Generator 3ch. 16-bit PPG 3ch. Multi-Function Timer AHB-APB Bridge : APB2 (Max 42 MHz) TIOBx LVD Regulator Base Timer 16-bit 8ch./ 32-bit 4ch. AHB-APB Bridge : APB1 (Max 42 MHz) TIOAx PLL C WKUP[3:0] RTCCO, SUBOUT Real-Time Clock IRQ-Monitor CRC Accelerator Watch Counter External Interrupt Controller 6-pin + NMI INTx NMIX MODE-Ctrl GPIO Multi-Function Serial I/F 4ch. (with FIFO ch.0 - ch.1) MD[1:0] PIN-Function-Ctrl P0x, P1x, . . . PFx SCKx SINx SOTx 9. Memory Size See "Memory size" in "0. " to confirm the memory size. Document Number: 002-05625 Rev.*B Page 32 of 87 MB9A310K Series 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved 0x7000_0000 0x6000_0000 External Device Area Reserved 0x4400_0000 0x4200_0000 0x4000_0000 32Mbyte Bit band alias Peripherals Reserved 32Mbyte Bit band alias 0x4001_2000 0x2200_0000 0x200E_1000 Reserved 0x200E_0000 WorkFlash I/F 0x200C_0000 WorkFlash 0x2008_0000 Reserved 0x2000_0000 SRAM1 0x1FFF_0000 SRAM0 0x0010_2000 0x0010_0000 Reserved RTC Watch Counter CRC MFS Reserved USB Clock Ctrl LVD/DS mode Reserved GPIO Reserved Int-Req. Read EXTI Reserved CR Trim Reserved A/DC QPRC Base Timer PPG Reserved 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x2400_0000 See the next page "Memory Map (2)" for the memory size details. 0x4003_C000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_7000 0x4003_6000 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 DMAC Reserved USB ch.0 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 MFT unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved MainFlash I/F Reserved Security/CR Trim MainFlash 0x0000_0000 Document Number: 002-05625 Rev.*B Page 33 of 87 MB9A310K Series Memory Map (2) MB9AF312K MB9AF311K 0x200E_0000 0x200E_0000 Reserved Reserved 0x200C_8000 SA0-3 (8KBx4) WorkFlash 32Kbyte SA0-3 (8KBx4) WorkFlash 32Kbyte 0x200C_8000 0x200C_0000 0x200C_0000 Reserved Reserved 0x2000_2000 0x2000_2000 SRAM1 8Kbyte SRAM1 8Kbyte 0x2000_0000 0x2000_0000 SRAM0 8Kbyte 0x1FFF_E000 SRAM0 8Kbyte 0x1FFF_E000 Reserved Reserved 0x0010_2000 0x0010_2000 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_0000 Security 0x0010_0000 Security Reserved Reserved 0x0002_0000 SA4-7 (8KBx4) 0x0001_0000 SA8-9 (16KBx2) 0x0000_0000 MainFlash 64Kbyte 0x0000_0000 MainFlash 128Kbyte SA8-9 (48KBx2) SA4-7 (8KBx4) See "MB9A310K/110K Series Flash programming Manual" for sector structure of Flash. Document Number: 002-05625 Rev.*B Page 34 of 87 MB9A310K Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF AHB APB0 MainFlash I/F register Reserved Software Watchdog timer Reserved Base Timer APB1 Quadrature Position/Revolution Counter A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter APB2 Deep stand-by mode Controller USB clock generator 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF USB ch.0 0x4005_0000 0x4005_FFFF 0x4006_0000 0x4006_0FFF 0x4006_1000 0x41FF_FFFF Reserved 0x200E_0000 0x200E_FFFF WorkFlash I/F register Document Number: 002-05625 Rev.*B Reserved AHB DMAC register Page 35 of 87 MB9A310K Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX = 0 This is the period when the INITX pin is the "L" level.  INITX = 1 This is the period when the INITX pin is the "H" level.  SPL = 0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".  SPL = 1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  GPIO selected In Deep stand-by mode, pins switch to the general-purpose I/O port. Document Number: 002-05625 Rev.*B Page 36 of 87 MB9A310K Series Pin status type List of Pin Status Function group Power-on reset or low-voltage detection state Power supply unstable - INITX input state Device internal reset state Power supply stable INITX = 0 - INITX = 1 - Run mode or sleep mode state Power supply stable INITX = 1 - Timer mode, RTC mode, or sleep mode state Deep stand-by RTC mode or Deep stand-by STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 Hi-Z / Maintain Internal previous input fixed state at "0" INITX = 1 SPL = 0 SPL = 1 Hi-Z / Maintain Internal previous input fixed state at "0" Return from Deep stand-by mode state Power supply stable INITX = 1 - GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Main crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Maintain previous state /When oscillation stop *1, Hi-Z/ Internal input fixed at "0" Maintain previous state /When oscillation stop *1, Hi-Z/ Internal input fixed at "0" Maintain previous state /When oscillation stop *1, Hi-Z/ Internal input fixed at "0" Maintain previous state /When oscillation stop *1, Hi-Z/ Internal input fixed at "0" A Main crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state Maintain previous state /When oscillation stop *1, Hi-Z/ Internal input fixed at "0" C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B Document Number: 002-05625 Rev.*B Page 37 of 87 Pin status type MB9A310K Series Function group Power-on reset or low-voltage detection state Power supply unstable - JTAG selected Hi-Z INITX input state Device internal reset state Power supply stable INITX = 0 - INITX = 1 - Pull-up / Input enabled Pull-up / Input enabled Run mode or sleep mode state Power supply stable INITX = 1 - Maintain previous state E Timer mode, RTC mode, or sleep mode state Deep stand-by RTC mode or Deep stand-by STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Power supply stable INITX = 1 - Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Analog input selected F External interrupt enabled selected Resource other than above selected Maintain previous state Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO selected WKUP enabled G Return from Deep stand-by mode state External interrupt enabled selected Resource other than above selected Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Hi-Z GPIO selected Document Number: 002-05625 Rev.*B Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Hi-Z / Internal input fixed at "0" Maintain previous state WKUP input enabled GPIO selected Maintain previous state GPIO selected Maintain previous state Hi-Z / WKUP input enabled Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected Maintain previous state Page 38 of 87 Pin status type MB9A310K Series H Function group Power-on reset or low-voltage detection state Power supply unstable - External interrupt enabled selected Resource other than above selected Setting disabled NMIX selected J Resource other than above selected INITX = 1 - Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled Run mode or sleep mode state Power supply stable INITX = 1 - Timer mode, RTC mode, or sleep mode state Deep stand-by RTC mode or Deep stand-by STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Hi-Z / Input enabled Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Hi-Z GPIO selected Document Number: 002-05625 Rev.*B GPIO selected Maintain previous state GPIO selected Maintain previous state Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Input enabled K Resource other than above selected INITX = 0 - Hi-Z / Input enabled Hi-Z GPIO selected Analog input selected Power supply stable Hi-Z / Input enabled resource selected GPIO selected Device internal reset state Hi-Z / Input enabled GPIO selected I INITX input state WKUP input enabled Hi-Z / WKUP input enabled Return from Deep stand-by mode state Power supply stable INITX = 1 - GPIO selected Maintain previous state GPIO selected Maintain previous state GPIO selected Maintain previous state Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected Maintain previous state Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected Maintain previous state Page 39 of 87 Pin status type MB9A310K Series Function group Power supply unstable - Analog input selected L Power-on reset or low-voltage detection state External interrupt enabled selected Resource other than above selected Hi-Z INITX input state Device internal reset state Power supply stable INITX = 0 Hi-Z / Internal input fixed at "0" / Analog input enabled INITX = 1 Hi-Z / Internal input fixed at "0" / Analog input enabled Run mode or sleep mode state Power supply stable INITX = 1 Hi-Z / Internal input fixed at "0" / Analog input enabled Timer mode, RTC mode, or sleep mode state Deep stand-by RTC mode or Deep stand-by STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Maintain previous state Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO selected Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" Maintain previous state Return from Deep stand-by mode state Power supply stable INITX = 1 Hi-Z / Internal input fixed at "0" / Analog input enabled GPIO selected Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Sub crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Sub crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enable Maintain previous state Maintain previous state /When oscillation stop*2,HiZ/ Internal input fixed at "0" M N Document Number: 002-05625 Rev.*B Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state /When oscillation stop*2,HiZ/ Internal input fixed at "0" Maintain previous state Maintain previous state /When oscillation stop*2,HiZ/ Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state /When oscillation stop*2,HiZ/ Internal input fixed at "0" Maintain previous state Maintain previous state /When oscillation stop*2,Hi-Z/ Internal input fixed at "0" Page 40 of 87 Pin status type MB9A310K Series Function group Power-on reset or low-voltage detection state Power supply unstable - INITX input state Device internal reset state Run mode or sleep mode state INITX = 0 - INITX = 1 - Power supply stable INITX = 1 - Power supply stable Deep stand-by RTC mode or Deep stand-by STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 Hi-Z / Maintain Internal previous input fixed state at "0" GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state USB I/O pin Setting disabled Setting disabled Setting disabled Maintain previous state Mode input pin Input enabled Input enabled Input enabled Input enabled INITX = 1 SPL = 0 SPL = 1 Hi-Z / Maintain Internal previous input fixed state at "0" Hi-Z at Hi-Z at transmistransmission / Input sion/ Input enabled/ enabled/ Internal Internal input fixed input fixed at "0" at at "0" at reception reception Input Input enabled enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state O P Timer mode, RTC mode, or sleep mode state Hi-Z / Input enabled Return from Deep stand-by mode state Power supply stable INITX = 1 Maintain previous state Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled Input enabled Input enabled Input enabled Maintain previous state Hi-Z / Input enabled Maintain previous state *1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep stand-by RTC mode, and Deep stand-by STOP mode. *2: Oscillation is stopped at STOP mode and Deep stand-by STOP mode. Document Number: 002-05625 Rev.*B Page 41 of 87 MB9A310K Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Power supply voltage*1, *2 Power supply voltage (for USB) *1, *3 Analog power supply voltage*1, *4 Analog reference voltage *1, *2 Symbol Rating Max Vcc Vss - 0.5 Vss + 6.5 V USBVcc Vss - 0.5 Vss + 6.5 V AVcc AVRH Vss - 0.5 Vss - 0.5 Vss + 6.5 Vss + 6.5 Vcc + 0.5 (≤6.5 V) USBVcc0 + 0.5 (≤6.5 V) V V Vss + 6.5 Vss - 0.5 Input voltage VI Vss - 0.5 Vss - 0.5 Analog pin input voltage Output voltage Clamp maximum current Clamp total maximum current "L" level maximum output current*5 "L" level average output current*6 "L" level total maximum output current "L" level total average output current*7 "H" level maximum output current*5 "H" level average output current*6 "H" level total maximum output current "H" level total average output current*7 Power consumption Storage temperature Unit Min VIA Vss - 0.5 VO Vss - 0.5 ICLAMP Σ[ICLAMP] -2 IOL - IOLAV - ∑IOL ∑IOLAV - IOH - IOHAV - ∑IOH ∑IOHAV PD TSTG - 55 Remarks V Except for USB pin V USB pin V 5V tolerant AVcc + 0.5 (≤6.5 V) Vcc + 0.5 (≤6.5 V) +2 +20 10 20 39 4 12 18.5 100 50 mA mA mA mA mA mA mA mA mA mA *8 *8 4mA type 12mA type P80, P81 4mA type 12mA type P80, P81 - 10 mA 4mA type - 20 - 39 -4 - 12 - 20.5 - 100 - 50 300 + 150 mA mA mA mA mA mA mA mW °C 12mA type P80, P81 4mA type 12mA type P80, P81 V V *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: Vcc must not drop below VSS - 0.5 V. *3: USBVcc must not drop below VSS - 0.5 V. *4: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on. *5: The maximum output current is the peak value for a single pin. *6: The average output is the average current for a single pin over a period of 100 ms. *7: The total average output current is the average current for all pins over a period of 100 ms. Document Number: 002-05625 Rev.*B Page 42 of 87 MB9A310K Series *8: • • • • • See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin. Use within recommended operating conditions. Use at DC voltage (current) the +B input. The +B signal should always be applied a limiting resistance placed between the +B signal and the device. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices. • Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • The following is a recommended circuit example (I/O equivalent circuit). VCC Protection Diode VCC P-ch Limiting resistor Digital output +B input (0V to 16V) N-ch Digital input R AVCC Analog input WARNING: − Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-05625 Rev.*B Page 43 of 87 MB9A310K Series 12.2 Recommended Operating Conditions (Vss = AVss = 0.0V) Parameter Power supply voltage Power supply voltage for USB Symbol Conditions Vcc - USBVcc Value Min Max 2.7*4 5.5 3.0 3.6 (≤Vcc) - Unit V *1 V AVcc AVRH - 2.7 2.7 5.5 (≤Vcc) 5.5 AVcc Smoothing capacitor CS - 1 10 μF Operating temperature TA - - 40 + 105 °C 2.7 Analog power supply voltage Analog reference voltage Remarks *2 V V AVcc = Vcc For built-in regulator*3 *1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80). *3: See "C Pin" in "Handling Devices" for the connection of the smoothing capacitor. *4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the Datasheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-05625 Rev.*B Page 44 of 87 MB9A310K Series 12.3 DC Characteristics 12.3.1 Current Rating (Vcc = AVcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = AVss = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin Name Conditions PLL RUN mode RUN mode current Icc High-speed CR RUN mode VCC Sub RUN mode Low-speed CR RUN mode SLEEP mode current Iccs PLL SLEEP mode High-speed CR SLEEP mode Sub SLEEP mode Low-speed CR SLEEP mode CPU: 40 MHz, Peripheral: 40 MHz, MainFlash 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU: 40 MHz, Peripheral: 40 MHz, MainFlash 3 Wait FRWTR.RWT = 00 FSYNDN.SD = 011 Value Typ*3 Max*4 Unit Remarks 32 41 mA *1, *5 21 28 mA *1, *5 3.9 7.7 mA *1 0.15 3.2 mA *1, *6 0.2 3.3 mA *1 Peripheral: 40 MHz 10 15 mA *1, *5 Peripheral: 4 MHz *2 1.2 4.4 mA *1 Peripheral: 32 kHz 0.1 3.1 mA *1, *6 Peripheral: 100 kHz 0.1 3.1 mA *1 CPU/ Peripheral: 4 MHz*2 MainFlash 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/ Peripheral: 32 kHz MainFlash 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/ Peripheral: 100 kHz MainFlash 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1: When all ports are input and are fixed at "0". *2: When setting it to 4 MHz by trimming. *3: TA = +25°C, VCC = 5.5V *4:TA = +105°C, VCC = 5.5V *5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) Document Number: 002-05625 Rev.*B Page 45 of 87 MB9A310K Series (Vcc = AVcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = AVss = 0V, TA = - 40°C to + 105°C) Parameter TIMER mode current Symbol Pin Name Conditions Main TIMER mode ICCT Sub TIMER mode RTC mode current ICCR STOP mode current ICCH RTC mode STOP mode VCC ICCRD Deep stand-by RTC mode Deep stand-by mode current ICCHD Deep stand-by STOP mode TA = + 25°C, When LVD is off TA = + 105°C, When LVD is off TA = + 25°C, When LVD is off TA = + 105°C, When LVD is off TA = + 25°C, When LVD is off TA = + 105°C, When LVD is off TA = + 25°C, When LVD is off TA = + 105°C, When LVD is off TA = + 25°C, When LVD is off RAM hold off TA = + 25°C, When LVD is off RAM hold on TA = + 105°C, When LVD is off RAM hold off TA = + 105°C, When LVD is off RAM hold on TA = + 25°C, When LVD is off RAM hold off TA = + 25°C, When LVD is off RAM hold on TA = + 105°C, When LVD is off RAM hold off TA = + 105°C, When LVD is off RAM hold on Value Unit Remarks Typ*2 Max*2 5.2 6 mA *1, *3 - 9 mA *1, *3 60 230 μA *1, *4 - 3.1 mA *1, *4 50 210 μA *1, *4 - 3.1 mA *1, *4 35 200 μA *1 - 3 mA *1 30 160 μA *1, *4 33 160 mA *1, *4 - 600 μA *1 - 610 mA *1 20 150 μA *1, *4 23 150 mA *1, *4 - 600 μA *1 - 610 mA *1 *1: When all ports are input and are fixed at "0". *2: VCC = 5.5 V *3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) Document Number: 002-05625 Rev.*B Page 46 of 87 MB9A310K Series Low-Voltage Detection Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Low-voltage detection circuit (LVD) power supply current Symbol ICCLVD Pin name VCC Conditions At operation for interrupt Vcc = 5.5 V Value Typ Max 4 7 Unit μA Remarks At not detect Flash Memory Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Flash memory write/erase current Symbol ICCFLASH Pin name VCC Conditions MainFlash At Write/Erase WorkFlash At Write/Erase Value Unit Typ Max 11.4 13.1 mA 11.4 13.1 mA Remarks A/D Converter Current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Power supply current Reference power supply current Symbol ICCAD ICCAVRH Document Number: 002-05625 Rev.*B Pin name Conditions Value Unit Typ Max At 1unit operation 0.57 0.72 mA At stop 0.06 20 μA At 1unit operation AVRH = 5.5 V 1.1 1.96 mA At stop 0.06 4 μA Remarks AVCC AVRH Page 47 of 87 MB9A310K Series 12.3.2 Pin Characteristics (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 105°C) Value Parameter Symbol "H" level input voltage (hysteresis input) VIHS "L" level input voltage (hysteresis input) VILS Pin name CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin 4mA type "H" level output voltage VOH 12mA type P80/P81 4mA type "L" level output voltage VOL 12mA type P80/P81 Input leak current IIL - Pull-up resistance Value RPU Pull-up pin Input capacitance CIN Other than VCC, USBVCC, VSS, AVCC, AVSS, AVRH Document Number: 002-05625 Rev.*B Conditions Unit Min Typ Max - Vcc × 0.8 - Vcc + 0.3 V - Vcc × 0.8 - Vss + 5.5 V - Vss - 0.3 - Vcc × 0.2 V - Vss - 0.3 - Vcc × 0.2 V Vcc - 0.5 - Vcc V Vcc - 0.5 - Vcc V USBVcc - 0.4 - USBVcc V Vss - 0.4 V Vss - 0.4 V Vss - 0.4 V -5 - +5 μA Vcc ≥ 4.5 V 25 50 100 Vcc < 4.5 V 30 80 200 - 5 15 Vcc ≥ 4.5 V IOH = - 4 mA Remarks Vcc < 4.5 V IOH = - 2 mA Vcc ≥ 4.5 V IOH = - 12 mA Vcc < 4.5 V IOH = - 8 mA USBVcc ≥ 4.5 V IOH = - 20.5 mA USBVcc < 4.5 V IOH = - 13.0 mA Vcc ≥ 4.5 V IOL = 4 mA Vcc < 4.5 V IOL = 2 mA Vcc ≥ 4.5 V IOL = 12 mA Vcc < 4.5 V IOL = 8 mA USBVcc ≥ 4.5 V IOL = 18.5 mA USBVcc< 4.5 V IOL = 10.5 mA - - kΩ pF Page 48 of 87 MB9A310K Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Parameter Input frequency Pin name Symbol FCH Input clock cycle tCYLH Input clock pulse width - Input clock rise time and fall time tCF, tCR Internal operating clock frequency*1 Internal operating clock cycle time*1 X0 X1 Conditions Value Unit Min Max 4 4 4 4 20.83 50 48 20 48 20 250 250 45 55 % - - 5 ns Vcc ≥ 4.5 V Vcc < 4.5 V Vcc ≥ 4.5 V Vcc < 4.5 V Vcc ≥ 4.5 V Vcc < 4.5 V PWH/tCYLH PWL/tCYLH Remarks MHz When crystal oscillator is connected MHz When using external Clock ns When using external Clock When using external Clock When using external Clock FCM - - - 42 MHz Master clock FCC - - - 42 MHz Base clock (HCLK/FCLK) FCP0 FCP1 - - - 42 42 MHz MHz APB0 bus clock*2 APB1 bus clock*2 FCP2 - - - 42 MHz APB2 bus clock*2 tCYCC - - 23.8 - ns Base clock (HCLK/FCLK) tCYCP0 tCYCP1 - - 23.8 23.8 - ns ns APB0 bus clock*2 APB1 bus clock*2 tCYCP2 - - 23.8 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual". *2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this datasheet. X0 Document Number: 002-05625 Rev.*B Page 49 of 87 MB9A310K Series 12.4.2 Sub Clock Input Characteristics Parameter Symbol Input frequency 1/ tCYLL Input clock cycle tCYLL Input clock pulse width Pin name Conditions - kHz - 100 kHz When crystal oscillator is connected When using external clock - 31.25 μs When using external clock - 55 % When using external clock - - 32.768 - 32 - 10 PWH/tCYLL PWL/tCYLL 45 X0A X1A - Min (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Unit Remarks Typ Max X0A 12.4.3 Internal CR Oscillation Characteristics High-speed Internal CR (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Parameter Clock frequency Frequency stability time Symbol FCRH tCRWT Conditions Value Min Typ Max TA = + 25°C 3.96 4 4.04 TA = 0°C to + 70°C 3.84 4 4.16 TA = - 40°C to + 85°C 3.8 4 4.2 TA = - 40°C to + 85°C 3 4 5 - - 90 - Unit MHz Remarks When trimming*1 When not trimming μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Low-speed Internal CR Parameter Clock frequency Symbol FCRL Document Number: 002-05625 Rev.*B Conditions - Min 50 (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Unit Remarks Typ Max 100 150 kHz Page 50 of 87 MB9A310K Series 12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Parameter Symbol Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency*2 USB clock frequency*3 tLOCK FPLLI FPLLO FCLKPLL FCLKSPLL 100 - - μs 4 13 200 - - 16 75 300 40 48 MHz multiple MHz MHz MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual". *3: For more information about USB clock, see "Chapter 2-2: USB Clock Generation" in "FM3 Family Peripheral Manual Communication Macro Part". 12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR) (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Parameter Symbol Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency*2 tLOCK FPLLI FPLLO FCLKPLL 100 - - μs 3.8 50 190 - 4 - 4.2 71 300 42 MHz multiple MHz MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual". When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Document Number: 002-05625 Rev.*B Page 51 of 87 MB9A310K Series 12.4.6 Reset Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Parameter Symbol Reset input time tINITX Pin name Conditions INITX - Unit Min Max 500 - Remarks ns 12.4.7 Power-on Reset Timing (Vss = 0V, TA = - 40°C to + 85°C) Parameter Symbol Power supply shut down time Power ramp rate Conditions VCC Unit Remarks Min Typ Max - 50 - - ms *1 VCC: 0.2 V to 2.70 V 0.7 - 1000 mV/µs *2 - 0.66 - 0.89 ms tOFF dV/dt Time until releasing Power-on reset Pin Name Value tPRT *1: VCC must be held below 0.2 V for a minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms). Note: − tOFF must be satisfied. When tOFF cannot be satisfied, assert external reset (INITX) at power-up and at any brownout event. 2.7V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST CPU Operation RST Active 0.2V tOFF release start Glossary  VDH: detection voltage of Low-Voltage detection reset. See 12.7 Low-voltage Detection Characteristics. Document Number: 002-05625 Rev.*B Page 52 of 87 MB9A310K Series 12.4.8 Base Timer Input Timing Timer input timing Parameter Input pulse width Symbol tTIWH tTIWL (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Unit Remarks Min Max Pin name Conditions TIOAn/TIOBn (when using as ECK, TIN) - tTIWH 2tCYCP - ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger input timing Parameter Input pulse width Symbol tTRGH tTRGL (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Conditions Unit Remarks Min Max Pin name TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS 2tCYCP - ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet. Document Number: 002-05625 Rev.*B Page 53 of 87 MB9A310K Series 12.4.9 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) Parameter Symbol Baud rate - Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock "L" pulse width Serial clock "H" pulse width tSLSH tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin name (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Vcc < 4.5 V Vcc ≥ 4.5 V Conditions Unit Min Max Min Max SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx - Master mode Slave mode - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this Datasheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-05625 Rev.*B Page 54 of 87 MB9A310K Series tSCYC VOH SCK VOL VOL tSLOVI SOT VOH VOL tIVSHI SIN VIH VIL tSHIXI VIH VIL Master mode tSLSH SCK VIH tF VIL tSHSL VIH VIL tR tSLOVE SOT SIN VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL Slave mode Document Number: 002-05625 Rev.*B Page 55 of 87 MB9A310K Series CSIO (SPI = 0, SCINV = 1) Parameter Symbol Baud rate (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Vcc < 4.5 V Vcc ≥ 4.5 V Conditions Unit Min Max Min Max - 8 - 8 Mbps tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx SOTx -30 +30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI 0 - 0 - ns Serial clock "L" pulse width Serial clock "H" pulse width tSLSH tSHSL 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns SCK ↑ → SOT delay time tSHOVE - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE 20 - 20 - ns SCK fall time SCK rise time tF tR - 5 5 - 5 5 ns ns Serial clock cycle time - Pin name - SCKx SINx SCKx SINx SCKx SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx - Master mode Slave mode Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this Datasheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-05625 Rev.*B Page 56 of 87 MB9A310K Series tSCYC VOH SCK VOH VOL tSHOVI SOT VOH VOL tIVSLI SIN VIH VIL tSLIXI VIH VIL Master mode tSHSL tSLSH VIH SCK VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05625 Rev.*B Page 57 of 87 MB9A310K Series CSIO (SPI = 1, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Parameter Symbol Baud rate Conditions - - Vcc ≥ 4.5 V Vcc < 4.5 V Min Max Unit Min Max - 8 - 8 Mbps tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx SOTx -30 +30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width Serial clock "H" pulse width tSLSH tSHSL 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns SCK ↑ → SOT delay time tSHOVE - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE 20 - 20 - ns SCK fall time SCK rise time tF tR - 5 5 - 5 5 ns ns Serial clock cycle time - Pin name SCKx SINx SCKx SINx SCKx SOTx SCKx SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx Master mode Slave mode Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this Datasheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-05625 Rev.*B Page 58 of 87 MB9A310K Series tSCYC VOH SCK VOL VOH VOL SOT VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH SCK VIH VIH VIL tF * SOT VIL tSHSL tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN tSLIXE VIH VIL VIH VIL Slave mode Changes when writing to TDR register Document Number: 002-05625 Rev.*B Page 59 of 87 MB9A310K Series CSIO (SPI = 1, SCINV = 1) Parameter Symbol Baud rate - Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI SOT → SCK ↑ delay time tSOVHI Serial clock "L" pulse width Serial clock "H" pulse width tSLSH tSHSL SCK ↓→ SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin name (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Vcc < 4.5 V Vcc ≥ 4.5 V Conditions Unit Min Max Min Max SCKx - SCKx SOTx SCKx SINx SCKx SINx SCKx SOTx SCKx SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx Master mode Slave mode 4tCYCP 8 - 4tCYCP 8 - Mbps ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this datasheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-05625 Rev.*B Page 60 of 87 MB9A310K Series tSCYC VOH SCK tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL Master mode tSHSL tR SCK tSLSH VIH VIH VIL VIL tF VIH VIL tSLOVE SOT VOH VOL VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode UART external clock (EXT = 1) (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Parameter Serial clock "L" pulse width Serial clock "H" pulse width SCK fall time SCK rise time Symbol tSLSH tSHSL tF tR Conditions CL = 30 pF tR SCK VIL Document Number: 002-05625 Rev.*B Min Max Unit tCYCP + 10 tCYCP + 10 - 5 5 ns ns ns ns tSHSL VIH tF tSLSH VIH VIL Remarks VIL VIH Page 61 of 87 MB9A310K Series 12.4.10 External Input Timing Parameter Symbol Pin name Conditions (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Value Unit Remarks Min Max ADTG Input pulse width tINH, tINL FRCKx ICxx DTTIxX INTxx NMIX WKUPx A/D converter trigger input - 2tCYCP*1 - ns - 2tCYCP*1 2tCYCP + 100*1 500 820 - ns ns ns ns *2 *3 *4 Free-run timer input clock Input capture Wave form generator External interrupt NMI Deep stand-by wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which A/D converter, Multi-function Timer, External interrupt are connected to, see "Block Diagram" in this Datasheet. *2: When in run mode, in sleep mode. *3: When in stop mode, in rtc mode, in timer mode. *4: When in deep stand-by stop mode, in deep stand-by rtc mode. Document Number: 002-05625 Rev.*B Page 62 of 87 MB9A310K Series 12.4.11 Quadrature Position/Revolution Counter timing (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Parameter AIN pin "H" width AIN pin "L" width BIN pin "H" width BIN pin "L" width BIN rise time from AIN pin "H" level AIN fall time from BIN pin "H" level BIN fall time from AIN pin "L" level AIN rise time from BIN pin "L" level AIN rise time from BIN pin "H" level BIN fall time from AIN pin "H" level AIN fall time from BIN pin "L" level BIN rise time from AIN pin "L" level ZIN pin "H" width ZIN pin "L" width AIN/BIN rise and fall time from determined ZIN level Determined ZIN level from AIN/BIN rise and fall time Symbol Conditions tAHL tALL tBHL tBLL - tAUBU PC_Mode2 or PC_Mode3 tBUAD PC_Mode2 or PC_Mode3 tADBD PC_Mode2 or PC_Mode3 tBDAU PC_Mode2 or PC_Mode3 tBUAU PC_Mode2 or PC_Mode3 tAUBD PC_Mode2 or PC_Mode3 tBDAD PC_Mode2 or PC_Mode3 tADBU PC_Mode2 or PC_Mode3 tZHL tZLL QCR:CGSC = "0" QCR:CGSC = "0" tZABE QCR:CGSC = "1" tABEZ QCR:CGSC = "1" Value Min Max 2tCYCP*1 - Unit ns *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "Block Diagram" in this Datasheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 002-05625 Rev.*B tBLL Page 63 of 87 MB9A310K Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN Document Number: 002-05625 Rev.*B Page 64 of 87 MB9A310K Series 12.4.12 I2C Timing (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Standard-mode Parameter SCL clock frequency (Repeated) START condition hold time SDA ↓→ SCL ↓ SCLclock "L" width SCLclock "H" width (Repeated) START setup time SCL ↑→ SDA ↓ Data hold time SCL ↓→ SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑→ SDA ↑ Bus free time between "STOP condition" and "START condition" Noise filter Symbol Conditions Fast-mode Unit Min Max Min Max FSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs tSUSTA 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP*4 - 2 tCYCP*4 - ns tHDDAT tSP CL = 30pF, R = (Vp/IOL) *1 - Remarks *1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (t LOW) of device's SCL signal. *3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "Block Diagram" in this Datasheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: 002-05625 Rev.*B Page 65 of 87 MB9A310K Series 12.4.13 JTAG Timing (Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions TMS, TDI setup time tJTAGS TCK, TMS, TDI Vcc ≥ 4.5 V Vcc < 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI Vcc < 4.5 V TDO delay time tJTAGD TCK, TDO Min Value Max Unit 15 - ns 15 - ns Vcc ≥ 4.5 V - 25 Vcc < 4.5 V - 45 Vcc ≥ 4.5 V Remarks ns Note: − When the external load capacitance = 30 pF. TCK TMS/TDI TDO Document Number: 002-05625 Rev.*B Page 66 of 87 MB9A310K Series 12.5 12-bit A/D Converter Electrical characteristics for the A/D converter (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 105°C) Symbol Pin name VZT VFST ANxx ANxx - - Ts - Compare clock cycle*3 Tcck State transition time to operation permission Parameter Value Unit Min Typ Max - 4.5 -2.5 - 20 AVRH - 20 1.0*1 1.2*1 - 12 + 4.5 + 2.5 + 20 AVRH + 20 - *2 - - *2 - - - 50 - 2000 ns Tstt - - - 1.0 μs Analog input capacity CAIN - - - 12.9 pF Analog input resistance RAIN - - - Interchannel disparity Analog port input leak current - ANxx - Analog input voltage - ANxx Reference voltage - AVRH Resolution Integral nonlinearity Differential nonlinearity Zero transition voltage Full-scale transition voltage Conversion time Sampling time 2 bit LSB LSB mV mV μs ns kΩ - 3.8 4 5 LSB μA AVSS - AVRH V 2.7 - AVCC V Remarks AVRH = 2.7 V to 5.5 V AVcc ≥ 4.5 V AVcc < 4.5 V AVcc ≥ 4.5 V AVcc < 4.5 V AVcc ≥ 4.5 V AVcc < 4.5 V *1: Conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is the following. AVcc ≥ 4.5V, HCLK = 40 MHz sampling time: 300 ns, compare time: 700 ns AVcc < 4.5V, HCLK = 40 MHz sampling time: 500 ns, compare time: 700 ns Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting of sampling time and compare clock cycle, see "Chapter 1-1:A/D Converter" in "FM3 Famliy Peripheral Manual Analog Macro Part". The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this Datasheet. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: Compare time (Tc) is the value of (Equation 2). Document Number: 002-05625 Rev.*B Page 67 of 87 MB9A310K Series Rext ANxx Analog input pin Comparator RAIN Analog signal source CAIN (Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9 Ts: Sampling time RAIN: Input resistance of A/D = 2kΩ at 4.5 V < AVCC < 5.5 V Input resistance of A/D = 3.8kΩ at 2.7 V < AVCC < 4.5 V CAIN: Input capacity of A/D = 12.9pF at 2.7 V < AVCC < 5.5 V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc: Compare time Tcck: Compare clock cycle Document Number: 002-05625 Rev.*B Page 68 of 87 MB9A310K Series Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral nonlinearity: Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics.  Differential nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral nonlinearity Differential nonlinearity 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics 0x002 VNT Ideal characteristics (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVss Actual conversion characteristics AVRH AVss Analog input Integral nonlinearity of digital output N = Differential nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: AVRH Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-05625 Rev.*B Page 69 of 87 MB9A310K Series 12.6 USB Characteristics (Vcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = 0V, TA = - 40°C to + 105°C) Parameter Input characteristics Pin name Conditions Value Min Max Unit Remarks Input "H" level voltage VIH - 2.0 USBVcc + 0.3 V *1 Input "L" level voltage VIL - Vss - 0.3 0.8 V *1 Differential input sensitivity VDI - 0.2 - V *2 Different common mode input voltage VCM - 0.8 2.5 V *2 2.8 3.6 V *3 0.0 0.3 V *3 1.3 4 4 90 28 75 75 80 2.0 20 20 111.11 44 300 300 125 V ns ns % Ω ns ns % *4 *5 *5 *5 *6 *7 *7 *7 Output "H" level voltage Output characterstics Symbol VOH Output "L" level voltage VOL Crossover voltage Rise time Fall time Rise/ fall time matching Output impedance Rise time Fall time Rise/ fall time matching VCRS tFR tFF tFRFM ZDRV tLR tLF tLRFM UDP0, UDM0 External pulldown resistance = 15 kΩ External pull-up resistance = 1.5 kΩ Full-Speed Full-Speed Full-Speed Full-Speed Low-Speed Low-Speed Low-Speed *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. Minimum differential input sensitivity [V] *2: Use differential-Receiver to receive USB differential data signal. Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. Common mode input voltage [V] Document Number: 002-05625 Rev.*B Page 70 of 87 MB9A310K Series *3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 1.5 kΩ load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. Rising time Document Number: 002-05625 Rev.*B Falling time Page 71 of 87 MB9A310K Series *6: USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28Ω to 44Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25Ω to 30Ω (recommendation value 27Ω) Series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rising time Falling time See Figure "Low-Speed Load (Compliance Load)" for conditions of external load. Document Number: 002-05625 Rev.*B Page 72 of 87 MB9A310K Series Low-Speed Load (Upstream Port Load) - Reference 1 CL = 50pF to 150pF CL = 50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL = 200pF to 600pF CL = 200pF to 600pF Low-Speed Load (Compliance Load) CL = 200pF to 450pF CL = 200pF to 450pF Document Number: 002-05625 Rev.*B Page 73 of 87 MB9A310K Series 12.7 Low-voltage Detection Characteristics 12.7.1 Low-voltage Detection Reset (TA = - 40°C to + 105°C) Value Parameter Detected voltage Released voltage Symbol Conditions VDL VDH - Min Typ Max 2.25 2.30 2.45 2.50 2.65 2.70 Unit V V Remarks When voltage drops When voltage rises 12.7.2 Interrupt of Low-voltage Detection (TA = - 40°C to + 105°C) Value Parameter Symbol Detected voltage Released voltage Detected voltage VDL VDH VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH LVD stabilization wait time TLVDW Conditions SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0111 SVHI = 1000 SVHI = 1001 - Unit Remarks Min Typ Max 2.58 2.67 2.76 2.8 2.9 3.0 3.02 3.13 3.24 V V V When voltage drops When voltage rises When voltage drops 2.85 3.1 3.34 V When voltage rises 2.94 3.2 3.45 V When voltage drops 3.04 3.3 3.56 V When voltage rises 3.31 3.6 3.88 V When voltage drops 3.40 3.7 3.99 V When voltage rises 3.40 3.7 3.99 V When voltage drops 3.50 3.8 4.10 V When voltage rises 3.68 4.0 4.32 V When voltage drops 3.77 4.1 4.42 V When voltage rises 3.77 4.1 4.42 V When voltage drops 3.86 4.2 4.53 V When voltage rises 3.86 4.2 4.53 V When voltage drops 3.96 4.3 4.64 V When voltage rises - - 2240 × tcycp*1 μs *1: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05625 Rev.*B Page 74 of 87 MB9A310K Series 12.8 MainFlash Memory Write/Erase Characteristics 12.8.1 Write / Erase time (Vcc = 2.7V to 5.5V, TA = - 40°C to + 105°C) Value Parameter Typ*1 Max*1 Large Sector 0.7 3.7 Small Sector 0.3 1.1 Half word (16-bit) write time 12 Chip erase time 3.8 Sector erase time Unit Remarks s Includes write time prior to internal erase 384 μs Not including system-level overhead time 16.2 s Includes write time prior to internal erase *1: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. 12.8.2 Erase/write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20*1 10,000 10*1 100,000 5*1 *1: At average + 85°C 12.9 WorkFlash Memory Write/Erase Characteristics 12.9.1 Write / Erase time (Vcc = 2.7V to 5.5V, TA = - 40°C to + 105°C) Value Parameter Unit Remarks Typ*1 Max*1 Sector erase time 0.3 1.5 s Includes write time prior to internal erase Half word (16-bit) write time 20 384 μs Not including system-level overhead time Chip erase time 1.2 6 s Includes write time prior to internal erase *1: The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycle of erase/write. 12.9.2 Erase/write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20*1 10,000 10*1 *1: At average + 85°C Document Number: 002-05625 Rev.*B Page 75 of 87 MB9A310K Series 12.10 Return Time from Low-Power Consumption Mode 12.10.1 Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Value Parameter Symbol Max*1 Typ SLEEP mode tCYCC High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode Unit ns 40 80 μs 370 740 μs Sub TIMER mode 699 929 μs STOP mode 505 834 μs Low-speed CR TIMER mode Ticnt Remarks *1: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*1) Ext.INT Interrupt factor accept Active Ticnt CPU Operation Interrupt factor clear by CPU Start *1: External interrupt is set to detecting fall edge. Document Number: 002-05625 Rev.*B Page 76 of 87 MB9A310K Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*1) Internal Resource INT Interrupt factor accept Active Ticnt CPU Operation Interrupt factor clear by CPU Start *1: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. − See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual about the return factor from Low-Power consumption mode. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual". Document Number: 002-05625 Rev.*B Page 77 of 87 MB9A310K Series 12.10.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Value Symbol Typ Max*1 Unit 365 554 μs 365 554 μs 555 934 μs Sub TIMER mode 608 976 μs STOP mode 475 774 μs SLEEP mode High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode Low-speed CR TIMER mode Trcnt Remarks *1: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX Internal RST RST Active Release Trcnt CPU Operation Document Number: 002-05625 Rev.*B Start Page 78 of 87 MB9A310K Series Operation example of return from low power consumption mode (by internal resource reset *1) Internal Resource RST Internal RST RST Active Release Trcnt CPU Operation *1: Internal resource reset Start is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual". − The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics" for the detailon the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-05625 Rev.*B Page 79 of 87 MB9A310K Series 13. Ordering Information Part number MB9AF311KPMC-G-JNE2 MB9AF312KPMC-G-JNE2 MB9AF311KPMC1-G-JNE2 MB9AF312KPMC1-G-JNE2 MB9AF311KQN-G-AVE2 MB9AF312KQN-G-AVE2 Document Number: 002-05625 Rev.*B On-chip Flash memory Main: 64 Kbyte Work: 32 Kbyte Main: 128 Kbyte Work: 32 Kbyte Main: 64 Kbyte Work: 32 Kbyte Main: 128 Kbyte Work: 32 Kbyte Main: 64 Kbyte Work: 32 Kbyte Main: 128 Kbyte Work: 32 Kbyte On-chip SRAM 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte Package Packing Plastic LQFP 48-pin (0.5 mm pitch), (LQA048) Plastic LQFP 52-pin (0.65 mm pitch), (LQC052 ) Tray Plastic QFN 48-pin (0.5 mm pitch), (VNA048) Page 80 of 87 MB9A310K Series 14. Package Dimensions Package Type Package Code LQFP 48pin (0.5mm pitch) LQA048 4 D D1 5 7 36 25 37 24 E1 24 37 13 48 E 5 7 3 36 25 4 6 48 13 1 12 e 1 12 2 5 7 0.10 C A-B D 3 0.20 C A-B D b 0.80 C A-B D 8 2 A 9 A A' 0.80 C SYMBOL L1 0.25 L A1 c b 10 SECTION A-A' DIMENSIONS MIN. NOM. MAX. 0.00 0.20 1.70 A A1 SEATING PLANE b 0.15 0.27 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC e 0.50 BSC E 9.00 BSC E1 7.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 0 8 002-13731 ** PACKAGE OUTLINE, 48 LEAD LQFP 7.0X7.0X1.7 MM LQA048 REV** Document Number: 002-05625 Rev.*B Page 81 of 87 MB9A310K Series Package Type Package Code QFN 48pin (0.5mm pitch) VNA048 0.10 D C A B D2 A 25 36 0.10 C 24 2X (ND-1) E 0.10 37 e C A B E2 5 13 9 INDEX MARK 8 48 12 R 1 L B TOP VIEW e b 4 0.10 C 0.10 0.05 C A B C BOTTOM VIEW 2X 0.10 C A 0.05 C SEATING PLANE A1 9 C SIDE VIEW DIMENSIONS SYMBOL MIN. NOM. A A1 0.90 0.00 0.05 D 7.00 BSC E 7.00 BSC b 0.20 0.25 D2 5.50 BSC E2 5.50 BSC e 0.50 BSC R 0.20 REF L MAX. 0.35 0.40 NOTE 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE. 0.30 6. MAX. PACKAGE WARPAGE IS 0.05mm. 7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT SINK SLUG AS WELL AS THE TERMINALS. 0.45 10. JEDEC SPEC IFICATIONNO . REF : N/A 002-15528 ** PACKAGE OUTLINE, 48 LEAD QFN 7.0X7.0X0.9 MMVNA048 5.5X5.5 MMEPAD(SAWN) REV** Document Number: 002-05625 Rev.*B Page 82 of 87 MB9A310K Series Package Type Package Code LQFP 52pin (0.65mm pitch) LQC052 4 D D1 39 5 7 27 26 40 39 27 26 40 14 52 E1 E 4 5 7 3 6 14 52 1 2 5 7 13 e b 0.20 C A-B D 0.13 C A-B 1 13 0.10 C A-B D 3 BOTTOM VIEW D 8 TOP VIEW A 2 0.25 A A' 0.10 C SEAT ING PLA NE L1 L A1 10 9 c b SECTION A-A' SIDE VIEW SYMBOL DIMENSION MIN. NOM. MAX. A1 0.00 0.20 b 0.265 c 0.09 1.70 A 0.30 0.365 0.20 D 12.00 BSC D1 10.00 BSC e 0.65 BSC E 12.00 BSC E1 10.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 0 PACKAGE OUTLINE, 52 LEAD LQFP 10.0X10.0X1.7 MM LQC052 REV** 002-13880 ** Document Number: 002-05625 Rev.*B Page 83 of 87 MB9A310K Series 15. Major Changes Spansion Publication Number: DS706-00029 Page Section Revision 1.0 Product lineup 7  function Packages 8 I/O Circuit Type 23 Change Results PRELIMINARY → Datasheet Added the pin count. Revised from "Planning". Corrected the following description to "TypeB". Digital output → Digital input Block Diagram Corrected the following description.  AHB (Max 40MHz) → AHB (Max 42MHz) 34  APB0 (Max 40MHz) → APB0 (Max 42MHz)  APB1 (Max 40MHz) → APB1 (Max 42MHz)  APB2 (Max 40MHz) → APB2 (Max 42MHz) Electrical Characteristics  Revised the value of "TBD". 3. DC Characteristics  Corrected the value. (1) Current Rating - "Power supply current (ICCR)" Typ: 60 → 50 45, 46 - "Power supply current (ICCRD)" (RAM hold off) Typ: 45 → 30 - "Power supply current (ICCRD)" (RAM hold on) Typ: 48 → 33 (9) External Input Timing Revised the value of "TBD". 61 5. 12-bit A/D Converter  Deleted"(Preliminary value)". 66  Electrical characteristics for the A/D converter  Corrected the value of "Compare clock cycle". Max: 10000 → 2000 8. MainFlash Memory Write/Erase Deleted"(targeted value)". Characteristics Erase/write cycles and data hold time 74 9. WorkFlash Memory Write/Erase Characteristics Erase/write cycles and data hold time Revision 1.1 Company name and layout design change Revision 2.0 Features 2 Added the description of PLL for USB USB Interface 25 I/O Circuit Type Added the description of I2C to the type of E and F 25, 26 I/O Circuit Type Added about +B input 32 Handling Devices Added "Stabilizing power supply voltage" Handling Devices Added the following description 32 Crystal oscillator circuit "Evaluate oscillation of your using crystal oscillator by your mount board." Handling Devices 33 Changed the description C Pin 35 Block Diagram Modified the block diagram Memory Map 36 Modified the area of "Extarnal Device Area" · Memory map(1) Memory Map 37 Added the summary of Flash memory sector and the note · Memory map(2) · Added the Clamp maximum current Electrical Characteristics 44, 45 · Added the output current of P80 and P81 1. Absolute Maximum Ratings · Added about +B input · Modified the minimum value of Analog reference voltage Electrical Characteristics 46 · Added Smoothing capacitor 2. Recommended Operation Conditions · Added the note about less than the minimum power supply voltage · Changed the table format Electrical Characteristics · Added Main TIMER mode current 47-49 3. DC Characteristics · Added Flash Memory Current (1) Current rating · Moved A/D Converter Current Document Number: 002-05625 Rev.*B Page 84 of 87 MB9A310K Series Page 52 53 54 55 57-64 70 79-82 83 Section Electrical Characteristics 4. AC Characteristics (1) Main Clock Input Characteristics Electrical Characteristics 4. AC Characteristics (3) Built-in CR Oscillation Characteristics Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main and USB PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing Electrical Characteristics 4. AC Characteristics (7) CSIO/UART Timing Electrical Characteristics 5. 12bit A/D Converter Electrical Characteristics 9. Return Time from Low-Power Consumption Mode Ordering Information Change Results Added Master clock at Ingernal operating clock frequency Added Frequency stability time at Built-in high-speed CR · Added Main PLL clock frequency · Added USB clock frequency · Added the figure of Main PLL connection and USB PLL connection · Added Time until releasing Power-on reset · Changed the figure of timing · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode · Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage · Added Conversion time at AVcc < 4.5V · Modified Stage transition time to operation permission · Modified the minimum value of Reference voltage Added Return Time from Low-Power Consumption Mode Changed the description of part number NOTE: Please see “Document History” about later revised information. Document Number: 002-05625 Rev.*B Page 85 of 87 MB9A310K Series Document History Document Title: MB9A310K Series 32-bit ARM® Cortex®-M3, FM3 Microcontroller Document Number: 002-05625 Revision ECN Orig. of Change Submission Date ** − TOYO 02/20/2015 Migrated to Cypress and assigned document number 002-05625. No change to document contents or format. *A 5232740 TOYO 04/21/2016 Updated to Cypress format. 03/22/2017 Corrected “USB Function" to “USB Device" in the following chapters. Features 1. Product Lineup 4. List of Pin Functions Changed an explanation from “from 01 to 99” to “from 00 to 99” in RealTime Clock (RTC) (Page 3) of Features, and Deleted “Second/A day of the week” of interrupt function. Changed package code as the following in chapter : 2. Packages 3. Pin Assignment 13. Ordering Information 14. Package Dimensions. FTP-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048, FPT-52P-M02 -> LQC052 Corrected “J-TAG" to “JTAG" in 4. List of Pin Functions. Added Note for JTAG pin in 4. List of Pin Functions. Changed remark [1] to "When all ports are input and are fixed at "0"." in 12.3.1 Current Rating. Changed Parameter “Power supply rising time (tVCCR)” to “Power ramp rate (dV/dt)” in 12.4.7 Power-on Reset Timing, Changed the minimum to 0.7mV/μs, Changed the maximum to 1000mV/μs, and Added remarks and note. Corrected "Analog port input current" to "Analog port input leak current" in 12.5 12-bit A/D Converter. Added the Baud rate spec in “12.4.9 CSIO/UART Timing”(Page 54, 56, 58, 60) *B 5561750 YSKA Document Number: 002-05625 Rev.*B Description of Change Page 86 of 87 MB9A310K Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory Microcontrollers cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/memory cypress.com/mcu PSoC cypress.com/psoc cypress.com/pmic USB Controllers Wireless/RF Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components cypress.com/iot Power Management ICs Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-05625 Rev.*B March 22, 2017 Page 87 of 87
MB9AF311KQN-G-AVE2 价格&库存

很抱歉,暂时无法提供与“MB9AF311KQN-G-AVE2”相匹配的价格&库存,您可以联系我们找货

免费人工找货