0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
MB9AFB44LBPMC-G-JNE2

MB9AFB44LBPMC-G-JNE2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    LQFP-64

  • 描述:

    ICMCU32BIT288KBFLASH64LQFP

  • 数据手册
  • 价格&库存
MB9AFB44LBPMC-G-JNE2 数据手册
Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9AB40NB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller The CY9AB40NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, LCDC and Communication Interfaces (USB, UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM Cortex-M3 Core USB Interface  Processor version: r2p1 The USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.  Up to 40 MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels [USB device]  24-bit System timer (Sys Tick): System timer for OS task management  USB2.0 Full-Speed supported  Max 6 EndPoint supported  [Flash memory]   Dual operation Flash memory     EndPoint 0 is control transfer EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer EndPoint 1 to 5 is comprised of Double Buffers. The size of each endpoint is according to the follows. Endpoint 0, 2 to 5: 64 bytes Endpoint 1: 256 bytes  On-chip Memories Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank) Work area: 32 Kbytes (lower bank)  • • [USB host]  USB2.0 Full/Low-speed supported  Bulk-transfer, interrupt-transfer and Isochronous-transfer  Read cycle: 0 wait-cycle support  Security function for code protection  USB Device connected/disconnected automatic detection [SRAM]  Automatic processing of the IN/OUT token handshake This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: Up to 16 Kbytes packet  Max 256-byte packet-length supported  Wake-up function supported LCD Controller (LCDC)  SRAM1: Up to 16 Kbytes  Up to 40 SEG × 8 COM External Bus Interface*  8 COM or 4 COM mode can be selected.  Supports SRAM, NOR Flash memory device  Built-in internal dividing resistor  Up to 8 chip selects  LCD drive power supply (bias) pin (VV4 to VV0)  8-/16-bit Data width  With blinking function  Up to 25-bit Address bit  Maximum area size : Up to 256 Mbytes  Supports Address/Data multiplex  Supports external RDY function *: CY9AFB41LB, FB42LB and FB44LB do not support External Bus Interface. Cypress Semiconductor Corporation Document Number: 002-05631 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 9, 2019 CY9AB40NB Series Multi-function Serial Interface (Max 8channels) Base Timer (Max 8 channels)  4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 Operation mode is selectable from the following for each channel. channels without FIFO (ch.0 to ch.3)  Operation mode is selectable from the following for each channel.  UART  CSIO  I2 C  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer [UART] General-Purpose I/O Port  Full-duplex double buffer  Built-in dedicated baud rate generator This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.  External clock available as a serial clock  Capable of pull-up control per pin  Hardware Flow control* : Automatically control the  Capable of reading pin level directly  Selection with or without parity supported transmission by CTS/RTS (only ch.4)  Various error detection functions available (parity errors, framing errors, and overrun errors) *: CY9AFB41LB, FB42LB and FB44LB do not support Hardware Flow control.  Built-in the port relocate function  Up to 83 fast general-purpose I/O Ports@100 pin Package  Some ports are 5 V tolerant. See Pin Assignment to confirm the corresponding pins. [CSIO] Dual Timer (32-/16-bit Down Counter)  Full-duplex double buffer  Overrun error detection function available The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the following for each channel. [I2C]  Free-running  Built-in dedicated baud rate generator Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported DMA Controller (8 channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: byte/half-word/word  Periodic (=Reload)  One-shot HDMI-CEC/Remote Control Receiver (Up to 2 channels) [HDMI-CEC transmitter]  Header block automatic transmission by judging Signal free  Generating status interrupt by detecting Arbitration lost  Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data  Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)  Transfer block count: 1 to 16 [HDMI-CEC receiver]  Number of transfers: 1 to 65536  Automatic ACK reply function available A/D Converter (Max 24 channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 2 units  Line error detection function available [Remote control receiver]  4 bytes reception buffer  Repeat code detection function available  Conversion time: 2.0 μs @ 2.7 V to 3.6 V  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) Document Number: 002-05631 Rev. *C Page 2 of 128 CY9AB40NB Series Real-time clock (RTC) [Resets] The Real-time clock can count year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  Reset requests from INITX pin  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Power on reset  Software reset  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count. Clock Super Visor (CSV)  Leap year automatic count is available. Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. Watch Counter  External clock failure (clock stop) is detected, reset is  The Watch counter is used for wake up from sleep and timer mode.  Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz asserted.  External frequency anomaly is detected, interrupt or reset is asserted. External Interrupt Controller Unit Low-Voltage Consumption Detector (LVD)  Up to 16 external interrupt input pins  This Series includes 2-stage monitoring of voltage on the  Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2 channels)  A watchdog timer can generate interrupts or a reset when a time-out value is reached.  This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.  The Hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC, Deep Standby Stop modes. VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-Power Consumption Mode  Six low-power consumption modes supported.     CRC (Cyclic Redundancy Check) Accelerator  The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage.  Sleep Timer RTC Stop Deep Standby RTC (selectable between keeping the value of RAM and not) Deep Standby Stop (selectable between keeping the value of RAM and not) CCITT CRC16 and IEEE-802.3 CRC32 are supported. Debug  CCITT CRC16 Generator Polynomial: 0x1021  Serial Wire JTAG Debug Port (SWJ-DP)  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7  Embedded Trace Macrocells (ETM).* Clock and Reset *: CY9AFB41LB/MB, FB42LB/MB, FB44LB/MB support only SWJ-DP. [Clocks] Unique ID  Selectable from five clock sources (2 external oscillators, 2 Unique value of the device (41-bit) is set. built-in CR oscillators, and Main PLL).  Main Clock: 4 MHz to 48 MHz Power Supply  Sub Clock: 32.768 kHz Wide range voltage:  Built-in high-speed CR Clock: 4 MHz VCC = 1.65 V to 3.6 V  Built-in low-speed CR Clock: 100 kHz VCC = 3.0 V to 3.6 V (when USB is used)  Main PLL Clock VCC = 2.2 V to 3.6 V (when LCDC is used) Document Number: 002-05631 Rev. *C Page 3 of 128 CY9AB40NB Series Contents Features .......................................................................................................................................................................... 1 1. Product Lineup ...................................................................................................................................................... 6 2. Packages................................................................................................................................................................ 7 3. Pin Assignment ..................................................................................................................................................... 8 4. List of Pin Functions ........................................................................................................................................... 15 4.1 List of Pin Numbers ............................................................................................................................................ 15 4.2 List of Pin Functions ........................................................................................................................................... 26 5. I/O Circuit Type .................................................................................................................................................... 41 6. Handling Precautions ......................................................................................................................................... 48 6.1 Precautions for Product Design .......................................................................................................................... 48 6.2 Precautions for Package Mounting ..................................................................................................................... 49 6.3 Precautions for Use Environment ....................................................................................................................... 51 7. Handling Devices ................................................................................................................................................ 52 8. Block Diagram ..................................................................................................................................................... 54 9. Memory Size ........................................................................................................................................................ 54 10. Memory Map ........................................................................................................................................................ 55 11. Pin Status in Each CPU State ............................................................................................................................. 58 12. List of Pin Status ................................................................................................................................................. 59 13. Electrical Characteristics ................................................................................................................................... 66 13.1 Absolute Maximum Ratings ................................................................................................................................ 66 13.2 Recommended Operating Conditions................................................................................................................. 67 13.3 DC Characteristics ............................................................................................................................................. 68 13.3.1 Current rating ...................................................................................................................................................... 68 13.3.2 Pin Characteristics .............................................................................................................................................. 71 13.4 LCD Characteristics............................................................................................................................................ 72 13.5 AC Characteristics .............................................................................................................................................. 73 13.5.1 Main Clock Input Characteristics ......................................................................................................................... 73 13.5.2 Sub Clock Input Characteristics .......................................................................................................................... 74 13.5.3 Built-in CR Oscillation Characteristics ................................................................................................................. 74 13.5.4 Operating Conditions of Main and USB PLL ....................................................................................................... 75 13.5.5 Reset Input Characteristics ................................................................................................................................. 76 13.5.6 Power-on Reset Timing ....................................................................................................................................... 77 13.5.7 External Bus Timing ............................................................................................................................................ 78 13.5.8 Base Timer Input Timing ..................................................................................................................................... 85 13.5.9 CSIO/UART Timing ............................................................................................................................................. 86 13.5.10 External Input Timing ....................................................................................................................................... 94 13.5.11 I2C Timing ........................................................................................................................................................ 95 13.5.12 ETM Timing ..................................................................................................................................................... 96 13.5.13 JTAG Timing.................................................................................................................................................... 97 13.6 12-bit A/D Converter ........................................................................................................................................... 98 13.7 USB Characteristics ......................................................................................................................................... 101 13.8 Low-Voltage Detection Characteristics ............................................................................................................. 105 13.8.1 Interrupt of Low-Voltage Detection .................................................................................................................... 106 13.9 Flash Memory Write/Erase Characteristics ...................................................................................................... 107 13.9.1 Write / Erase time.............................................................................................................................................. 107 13.9.2 Write cycles and data hold time ........................................................................................................................ 107 13.10 Return Time from Low-Power Consumption Mode ........................................................................................... 108 13.10.1 Return Factor: Interrupt/WKUP ...................................................................................................................... 108 13.10.2 Return Factor: Reset ..................................................................................................................................... 109 14. Ordering Information ........................................................................................................................................ 111 Document Number: 002-05631 Rev. *C Page 4 of 128 CY9AB40NB Series 15. Package Dimensions ........................................................................................................................................ 112 16. Errata .................................................................................................................................................................. 121 16.1 Part Numbers Affected ..................................................................................................................................... 121 16.2 Qualification Status .......................................................................................................................................... 121 16.3 Errata Summary ............................................................................................................................................... 121 17. Major Changes .................................................................................................................................................. 125 Document History ...................................................................................................................................................... 127 Sales, Solutions, and Legal Information .................................................................................................................. 128 Document Number: 002-05631 Rev. *C Page 5 of 128 CY9AB40NB Series 1. Product Lineup Memory size Product name On-chip Flash memory On-chip SRAM CY9AFB41LB/MB/NB CY9AFB42LB/MB/NB CY9AFB44LB/MB/NB Main area 64 Kbytes 128 Kbytes 256 Kbytes Work area 32 Kbytes 32 Kbytes 32 Kbytes SRAM0 8 Kbytes 8 Kbytes 16 Kbytes SRAM1 8 Kbytes 8 Kbytes 16 Kbytes Total 16 Kbytes 16 Kbytes 32 Kbytes Function Product name Pin count CPU Freq. Power supply voltage range USB2.0 (Device/Host) DMAC CY9AFB41LB CY9AFB41MB CY9AFB41NB CY9AFB42LB CY9AFB42MB CY9AFB42NB CY9AFB44LB CY9AFB44MB 80/96 CY9AFB44NB 100/112 Addr: 21-bit (Max) R/W Data: 8-bit (Max) CS: 4 (Max) Support: SRAM, NOR Flash memory 33 SEG × 8 COM (Max) Addr: 25-bit (Max) R/W Data: 8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR Flash memory 40 SEG × 8 COM (Max) 64 Cortex-M3 40 MHz 1.65 V to 3.6 V 1 ch. 8 ch. External Bus Interface - LCD Controller 20 SEG × 8 COM (Max) MF Serial Interface (UART/CSIO/I2C) 8 ch. (Max) ch.4 to ch.7: FIFO (16 steps × 9-bit) ch.0 to ch.3: No FIFO Base Timer (PWC/Reload timer/PWM/PPG) 8 ch. (Max) Dual Timer 1 unit HDMI-CEC/ Remote Control Receiver Real-Time Clock Watch Counter CRC Accelerator Watchdog timer External Interrupts I/O ports 12-bit A/D converter CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in CR Low-speed Debug Function Unique ID 2 ch. (Max) 1 unit 1 unit Yes 1 ch. (SW) + 1 ch. (HW) 8 pins (Max) + NMI × 1 51 pins (Max) 12 ch. (2 units) Yes 2 ch. 4 MHz 100 kHz SWJ-DP Yes 11 pins (Max) + NMI × 1 66 pins (Max) 17 ch. (2 units) 16 pins (Max) + NMI × 1 83 pins (Max) 24 ch. (2 units) SWJ-DP/ETM Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. − See Electrical Characteristics12.5 AC Characteristics 12.5.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: 002-05631 Rev. *C Page 6 of 128 CY9AB40NB Series 2. Packages Product name Package CY9AFB41LB CY9AFB41MB CY9AFB41NB CY9AFB42LB CY9AFB42MB CY9AFB42NB CY9AFB44LB CY9AFB44MB CY9AFB44NB    - - - - - - LQFP: LQD064 (0.5mm pitch) LQFP: LQG064 (0.65mm pitch) QFN: VNC064 (0.5mm pitch) LQFP: LQH080 (0.5mm pitch) - LQFP: LQJ080 (0.65mm pitch) - BGA: FDG096 (0.5mm pitch) - LQFP: LQI100 (0.5mm pitch) - - QFP: PQH100 (0.65mm pitch) - - BGA: LBC112 (0.8mm pitch) - -    -    : Supported Note: − See Package Dimensions for detailed information on each package. Document Number: 002-05631 Rev. *C Page 7 of 128 CY9AB40NB Series 3. Pin Assignment LQI100 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 VCC 78 77 76 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_1 81 80 79 P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/SEG08/MCSX4_1 P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/SEG09/MCSX5_1 83 82 P09/TRACECLK/TIOB0_2/RTS4_2/SEG05/MCSX2_1 P08/AN23/TRACED3/TIOA0_2/CTS4_2/SEG06/MCSX3_1 P07/AN22/TRACED2/ADTG_0/SCK4_2/SEG07/MCLKOUT_1 86 85 84 P0C/SCK4_0/TIOA6_1/MALE_1 P0B/SOT4_0/TIOB6_1/MCSX0_1 P0A/SIN4_0/INT00_2/MCSX1_1 89 88 87 P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1 P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1 92 91 90 P62/SCK5_0/ADTG_3/SEG01/MOEX_1 P63/INT03_0/SEG02/MWEX_1 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 94 93 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX/SEG00 97 96 99 98 95 VSS P81/UDP0 P80/UDM0 100 (TOP VIEW) VCC 1 75 VSS P50/INT00_0/SIN3_1/VV4/MADATA00_1 2 74 P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1 P51/INT01_0/SOT3_1/VV3/MADATA01_1 3 73 P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11 P52/INT02_0/SCK3_1/VV2/MADATA02_1 4 72 P22/AN17/SOT0_0/TIOB7_1/SEG12 P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1 5 71 P23/AN16/SCK0_0/TIOA7_1/SEG13 P54/SOT6_0/TIOB1_2/VV0/MADATA04_1 6 70 P1F/AN15/ADTG_5/MAD23_1 P55/SCK6_0/ADTG_1/SEG39/MADATA05_1 7 69 P1E/AN14/RTS4_1/SEG14/MAD22_1 P56/INT08_2/SEG38/MADATA06_1 8 68 P1D/AN13/CTS4_1/SEG15/MAD21_1 P30/TIOB0_1/INT03_2/COM7/MADATA07_1 9 67 P1C/AN12/SCK4_1/SEG16/MAD20_1 P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1 10 66 P1B/AN11/SOT4_1/SEG17/MAD19_1 65 P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1 64 P19/AN09/SCK2_2/SEG19/MAD17_1 P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1 11 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1 12 P34/TIOB4_1/MADATA11_1 13 63 P18/AN08/SOT2_2/SEG20/MAD16_1 P35/TIOB5_1/INT08_1/MADATA12_1 14 62 AVSS LQFP - 100 48 49 50 PE2/X0 VSS MD0 PE3/X1 45 46 47 PE0/MD1 P4D/TIOB4_0/SOT7_1/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 43 44 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 40 41 42 P42/TIOA2_0 P4B/TIOB2_0/SEG29/MAD05_1 VCC P49/TIOB0_0/SOT3_2/SEG31/MAD03_1 51 P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1 25 37 P10/AN00/SEG28 VSS 38 52 39 24 INITX P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1 P3F/TIOA5_1/SEG35 P47/X1A 53 P48/INT14_1/SIN3_2/SEG32/MAD02_1 23 34 P12/AN02/SOT1_1/SEG26/MAD10_1 P3E/TIOA4_1/SEG36 35 54 36 22 VCC P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1 P3D/TIOA3_1/SEG37 P46/X0A P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1 55 32 56 21 33 20 P3C/TIOA2_1/COM0 C P15/AN05/SOT0_1/SEG23/MAD13_1 P3B/TIOA1_1/COM1 VSS 57 P45/TIOA5_0/SEG33/MAD01_1 19 29 P16/AN06/SCK0_1/SEG22/MAD14_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2 30 58 31 18 P43/TIOA3_0/ADTG_7 P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1 P39/ADTG_2/COM3 P44/TIOA4_0/SEG34/MAD00_1 59 26 17 27 AVCC P38/SCK5_2/INT11_1/MADATA15_1 28 AVRH 60 VCC 61 16 P40/TIOA0_0/INT12_1 15 P41/TIOA1_0/INT13_1 P36/SIN5_2/INT09_1/MADATA13_1 P37/SOT5_2/INT10_1/MADATA14_1 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05631 Rev. *C Page 8 of 128 CY9AB40NB Series PQH100 VCC VSS P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1 P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11 54 53 52 51 P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 57 56 55 P04/TDO/SWO P03/TMS/SWDIO 59 58 P07/AN22/TRACED2/ADTG_0/SCK4_2/SEG07/MCLKOUT_1 P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/SEG08/MCSX4_1 P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/SEG09/MCSX5_1 62 61 60 P0A/SIN4_0/INT00_2/MCSX1_1 P09/TRACECLK/TIOB0_2/RTS4_2/SEG05/MCSX2_1 P08/AN23/TRACED3/TIOA0_2/CTS4_2/SEG06/MCSX3_1 65 64 63 P0C/SCK4_0/TIOA6_1/MALE_1 P0B/SOT4_0/TIOB6_1/MCSX0_1 67 66 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1 P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1 70 69 68 P62/SCK5_0/ADTG_3/SEG01/MOEX_1 P63/INT03_0/SEG02/MWEX_1 72 71 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX/SEG00 75 74 73 VSS P81/UDP0 P80/UDM0 78 77 76 P50/INT00_0/SIN3_1/VV4/MADATA00_1 VCC 80 79 (TOP VIEW) P51/INT01_0/SOT3_1/VV3/MADATA01_1 81 50 P22/AN17/SOT0_0/TIOB7_1/SEG12 P52/INT02_0/SCK3_1/VV2/MADATA02_1 82 49 P23/AN16/SCK0_0/TIOA7_1/SEG13 P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1 83 48 P1F/AN15/ADTG_5/MAD23_1 P54/SOT6_0/TIOB1_2/VV0/MADATA04_1 84 47 P1E/AN14/RTS4_1/SEG14/MAD22_1 P55/SCK6_0/ADTG_1/SEG39/MADATA05_1 85 46 P1D/AN13/CTS4_1/SEG15/MAD21_1 P56/INT08_2/SEG38/MADATA06_1 86 45 P1C/AN12/SCK4_1/SEG16/MAD20_1 P30/TIOB0_1/INT03_2/COM7/MADATA07_1 87 44 P1B/AN11/SOT4_1/SEG17/MAD19_1 P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1 88 43 P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1 P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1 89 42 P19/AN09/SCK2_2/SEG19/MAD17_1 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1 90 41 P18/AN08/SOT2_2/SEG20/MAD16_1 P34/TIOB4_1/MADATA11_1 91 40 AVSS P35/TIOB5_1/INT08_1/MADATA12_1 92 39 AVRH P36/SIN5_2/INT09_1/MADATA13_1 93 38 AVCC P37/SOT5_2/INT10_1/MADATA14_1 94 37 P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1 P38/SCK5_2/INT11_1/MADATA15_1 95 36 P16/AN06/SCK0_1/SEG22/MAD14_1 P39/ADTG_2/COM3 96 35 P15/AN05/SOT0_1/SEG23/MAD13_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2 97 34 P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1 P3B/TIOA1_1/COM1 98 33 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1 P3C/TIOA2_1/COM0 99 32 P12/AN02/SOT1_1/SEG26/MAD10_1 P3D/TIOA3_1/SEG37 100 31 P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1 27 28 29 30 PE3/X1 VSS VCC P10/AN00/SEG28 24 25 26 MD0 PE0/MD1 PE2/X0 22 23 P4D/TIOB4_0/SOT7_1/MAD07_1 P4B/TIOB2_0/SEG29/MAD05_1 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 19 20 21 P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1 16 17 18 INITX P48/INT14_1/SIN3_2/SEG32/MAD02_1 14 15 P46/X0A P47/X1A P49/TIOB0_0/SOT3_2/SEG31/MAD03_1 11 12 13 C VSS VCC 9 10 P44/TIOA4_0/SEG34/MAD00_1 P45/TIOA5_0/SEG33/MAD01_1 6 7 8 P42/TIOA2_0 P41/TIOA1_0/INT13_1 P43/TIOA3_0/ADTG_7 3 4 5 VSS VCC P3F/TIOA5_1/SEG35 P40/TIOA0_0/INT12_1 1 2 P3E/TIOA4_1/SEG36 QFP - 100 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05631 Rev. *C Page 9 of 128 CY9AB40NB Series LQH080/LQJ080 P02/TDI/MCSX6_1 P01/TCK/SWCLK P00/TRSTX/MCSX7_1 63 62 61 P04/TDO/SWO P03/TMS/SWDIO 65 64 P0A/SIN4_0/INT00_2/MCSX1_1 P07/AN22/ADTG_0/SEG07/MCLKOUT_1 67 66 P0C/SCK4_0/TIOA6_1/MALE_1 P0B/SOT4_0/TIOB6_1/MCSX0_1 69 68 P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1 P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1 70 72 71 P62/SCK5_0/ADTG_3/SEG01/MOEX_1 P63/INT03_0/SEG02/MWEX_1 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 74 73 P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 P61/SOT5_0/TIOB2_2/UHCONX/SEG00 76 75 P80/UDM0 VCC 78 77 VSS P81/UDP0 80 79 (TOP VIEW) VCC 1 60 P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1 P50/INT00_0/SIN3_1/VV4/MADATA00_1 2 59 P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11 P51/INT01_0/SOT3_1/VV3/MADATA01_1 3 58 P22/AN17/SOT0_0/TIOB7_1/SEG12 P52/INT02_0/SCK3_1/VV2/MADATA02_1 4 57 P23/AN16/SCK0_0/TIOA7_1/SEG13 P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1 5 56 P1B/AN11/SOT4_1/SEG17/MAD19_1 P54/SOT6_0/TIOB1_2/VV0/MADATA04_1 6 55 P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1 P55/SCK6_0/ADTG_1/SEG39/MADATA05_1 7 54 P19/AN09/SCK2_2/SEG19/MAD17_1 P56/INT08_2/SEG38/MADATA06_1 8 53 P18/AN08/SOT2_2/SEG20/MAD16_1 P30/TIOB0_1/INT03_2/COM7/MADATA07_1 9 52 AVSS P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1 10 51 AVRH P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1 11 50 AVCC P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1 12 49 P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1 P39/ADTG_2/COM3 13 48 P16/AN06/SCK0_1/SEG22/MAD14_1 P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2 14 47 P15/AN05/SOT0_1/SEG23/MAD13_1 P3B/TIOA1_1/COM1 15 46 P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1 P3C/TIOA2_1/COM0 16 45 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1 P3D/TIOA3_1/SEG37 17 44 P12/AN02/SOT1_1/SEG26/MAD10_1 P3E/TIOA4_1/SEG36 18 43 P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1 P3F/TIOA5_1/SEG35 19 42 P10/AN00/SEG28 VSS 20 41 VCC 38 39 40 PE2/X0 VSS MD0 PE3/X1 36 37 PE0/MD1 34 35 P4D/TIOB4_0/SOT7_1/MAD07_1 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 32 33 P4B/TIOB2_0/SEG29/MAD05_1 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 31 29 30 P49/TIOB0_0/SOT3_2/SEG31/MAD03_1 P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1 27 28 INITX P47/X1A P48/INT14_1/SIN3_2/SEG32/MAD02_1 25 26 VCC P46/X0A 23 24 C VSS 21 22 P44/TIOA4_0/SEG34/MAD00_1 P45/TIOA5_0/SEG33/MAD01_1 LQFP - 80 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05631 Rev. *C Page 10 of 128 CY9AB40NB Series LQD064/LQG064 VSS P81/UDP0 P80/UDM0 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1 P61/SOT5_0/TIOB2_2/UHCONX/SEG00 P62/SCK5_0/ADTG_3/SEG01 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11 P50/INT00_0/SIN3_1/VV4 2 47 P22/AN17/SOT0_0/TIOB7_1/SEG12 P51/INT01_0/SOT3_1 3 46 P23/AN16/SCK0_0/TIOA7_1/SEG13 P52/INT02_0/SCK3_1 4 45 P19/AN09/SCK2_2/SEG19 P30/TIOB0_1/INT03_2/COM7 5 44 P18/AN08/SOT2_2/SEG20 P31/TIOB1_1/SCK6_1/INT04_2/COM6 6 43 AVSS P32/TIOB2_1/SOT6_1/INT05_2/COM5 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4 8 41 AVCC P39/ADTG_2/COM3 9 40 P17/AN07/SIN2_2/INT04_1/SEG21 P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2 10 39 P15/AN05/SEG23 P3B/TIOA1_1/COM1 11 38 P14/AN04/INT03_1/SEG24 P3C/TIOA2_1/COM0 12 37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25 P3D/TIOA3_1/SEG37 13 36 P12/AN02/SOT1_1/SEG26 P3E/TIOA4_1/SEG36 14 35 P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27 P3F/TIOA5_1/SEG35 15 34 P10/AN00/SEG28 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SEG31 P4A/TIOB1_0/SEG30 P4B/TIOB2_0/SEG29 P4C/TIOB3_0/SCK7_1/CEC0 P4D/TIOB4_0/SOT7_1 P4E/TIOB5_0/INT06_2/SIN7_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 64 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05631 Rev. *C Page 11 of 128 CY9AB40NB Series VNC064 VSS P81/UDP0 P80/UDM0 VCC P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1 P61/SOT5_0/TIOB2_2/UHCONX/SEG00 P62/SCK5_0/ADTG_3/SEG01 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0C/SCK4_0/TIOA6_1 P0B/SOT4_0/TIOB6_1 P0A/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11 P50/INT00_0/SIN3_1/VV4 2 47 P22/AN17/SOT0_0/TIOB7_1/SEG12 P51/INT01_0/SOT3_1 3 46 P23/AN16/SCK0_0/TIOA7_1/SEG13 P52/INT02_0/SCK3_1 4 45 P19/AN09/SCK2_2/SEG19 P30/TIOB0_1/INT03_2/COM7 5 44 P18/AN08/SOT2_2/SEG20 P31/TIOB1_1/SCK6_1/INT04_2/COM6 6 43 AVSS P32/TIOB2_1/SOT6_1/INT05_2/COM5 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4 8 41 AVCC P39/ADTG_2/COM3 9 40 P17/AN07/SIN2_2/INT04_1/SEG21 P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2 10 39 P15/AN05/SEG23 P3B/TIOA1_1/COM1 11 38 P14/AN04/INT03_1/SEG24 P3C/TIOA2_1/COM0 12 37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25 P3D/TIOA3_1/SEG37 13 36 P12/AN02/SOT1_1/SEG26 P3E/TIOA4_1/SEG36 14 35 P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27 P3F/TIOA5_1/SEG35 15 34 P10/AN00/SEG28 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SEG31 P4A/TIOB1_0/SEG30 P4B/TIOB2_0/SEG29 P4C/TIOB3_0/SCK7_1/CEC0 P4D/TIOB4_0/SOT7_1 P4E/TIOB5_0/INT06_2/SIN7_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 64 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05631 Rev. *C Page 12 of 128 CY9AB40NB Series LBC112 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS UDP0 UDM0 VCC P0E P0B AN22 TMS/ SWDIO TRSTX VCC VSS B VCC VSS P52 P61 P0F P0C AN23 TDO/ SWO TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0D P09 AN20 VSS AN19 AN18 D P53 P54 P55 VSS P56 P63 P0A VSS AN21 AN16 AN15 E P30 P31 P32 P33 Index AN17 AN14 AN12 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH G P37 P38 P3A P3D AN08 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 P43 P49 P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E MD1 VSS VCC L VSS C X0A VSS P41 P45 P4A MD0 X0 X1 VSS PFBGA - 112 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05631 Rev. *C Page 13 of 128 CY9AB40NB Series FDG096 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS UDP0 UDM0 VCC VSS P0F VSS AN22 TMS/ SWDIO TRSTX VSS B VCC VSS P52 P61 P63 P0D P0C TDO/ SWO TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0E P0B P0A VSS AN19 AN18 D P53 P54 P55 Index AN17 AN16 VSS E P56 P30 P31 AN11 AN10 AN09 F VSS VSS VSS AN08 AN07 AVRH G P32 P33 P39 AN06 AN05 AVSS H P3A P3B P3C AN04 AN03 AVCC J P3D P3E VSS P3F P48 P4A P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P45 P49 P4C P4E MD1 VSS VCC L VSS C X0A VSS P44 VSS P4B MD0 X0 X1 VSS Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. PFBGA - 96 Document Number: 002-05631 Rev. *C Page 14 of 128 CY9AB40NB Series 4. List of Pin Functions 4.1 List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No I/O LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 1 79 B1 1 B1 2 80 C1 2 C1 LQFP-64 Circuit 1 2 3 81 C2 3 C2 - - - - - - 3 4 82 B3 4 B3 - - - - - - 4 5 83 D1 5 D1 - 6 84 D2 6 D2 - Pin State Type Type QFN-64 - Document Number: 002-05631 Rev. *C Pin Name VCC P50 INT00_0 SIN3_1 VV4 MADATA00_1 P51 INT01_0 SOT3_1 (SDA3_1) VV3 MADATA01_1 P51 INT01_0 SOT3_1 (SDA3_1) P52 INT02_0 SCK3_1 (SCL3_1) VV2 MADATA02_1 P52 INT02_0 SCK3_1 (SCL3_1) P53 SIN6_0 TIOA1_2 INT07_2 VV1 MADATA03_1 P54 SOT6_0 (SDA6_0) TIOB1_2 VV0 MADATA04_1 - J Y J Y E L J Y E L J Y J X Page 15 of 128 CY9AB40NB Series Pin No LQFP-100 QFP-100 BGA-112 I/O LQFP-80 BGA-96 LQFP-64 85 D3 7 D3 - 8 86 D5 8 E1 - 9 87 E1 9 E2 5 - 88 E2 10 E3 6 - 11 89 E3 11 G1 7 - 12 90 E4 12 G2 Circuit 8 13 91 F1 - - - 14 92 F2 - - - Pin State Type Type QFN-64 7 10 Pin Name P55 SCK6_0 (SCL6_0) ADTG_1 SEG39 MADATA05_1 P56 INT08_2 SEG38 MADATA06_1 P30 TIOB0_1 INT03_2 COM7 MADATA07_1 P31 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 COM6 MADATA08_1 P32 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 COM5 MADATA09_1 P33 INT04_0 TIOB3_1 SIN6_1 ADTG_6 COM4 MADATA10_1 P34 TIOB4_1 MADATA11_1 P35 TIOB5_1 INT08_1 K U K V K V K V K V K V E K E L MADATA12_1 Document Number: 002-05631 Rev. *C Page 16 of 128 CY9AB40NB Series Pin No LQFP-100 QFP-100 BGA-112 I/O LQFP-80 BGA-96 LQFP-64 Circuit 93 F3 - - - - - - - F1 F2 F3 - 16 94 G1 - - - 17 95 G2 - - - 18 96 F4 13 G3 9 19 97 G3 14 H1 10 20 98 H1 15 H2 11 21 99 H2 16 H3 12 22 100 G4 17 J1 13 - - B2 - B2 - 23 1 H3 18 J2 14 24 2 J2 19 J4 15 25 26 3 4 L1 J1 20 - L1 - 16 - Pin State Type Type QFN-64 15 Document Number: 002-05631 Rev. *C Pin Name P36 SIN5_2 INT09_1 MADATA13_1 VSS VSS VSS P37 SOT5_2 (SDA5_2) INT10_1 MADATA14_1 P38 SCK5_2 (SCL5_2) INT11_1 MADATA15_1 P39 ADTG_2 COM3 P3A TIOA0_1 RTCCO_2 SUBOUT_2 COM2 P3B TIOA1_1 COM1 P3C TIOA2_1 COM0 P3D TIOA3_1 SEG37 VSS P3E TIOA4_1 SEG36 P3F TIOA5_1 SEG35 VSS VCC E L - E L E L K U K U K U K U K U K U K U - Page 17 of 128 CY9AB40NB Series Pin No BGA-96 LQFP-64 LQFP-100 QFP-100 BGA-112 LQFP-80 27 5 J4 - - - 28 6 L5 - - - 29 7 K5 - - - 30 8 J5 - - - 31 9 H5 21 L5 - 32 10 L6 22 K5 - 33 34 35 11 12 13 K2 J3 H4 L2 L4 K1 23 24 25 K2 J3 L6 L2 L4 K1 17 18 36 14 L3 26 L3 19 37 15 K3 27 K3 20 38 16 K4 28 K4 21 39 17 K6 29 J5 - 18 J6 30 K6 - Document Number: 002-05631 Rev. *C I/O Circuit Pin State Type Type QFN-64 22 40 Pin Name P40 TIOA0_0 INT12_1 P41 TIOA1_0 INT13_1 P42 TIOA2_0 P43 TIOA3_0 ADTG_7 P44 TIOA4_0 SEG34 MAD00_1 P45 TIOA5_0 SEG33 MAD01_1 VSS VSS VSS VSS C VSS VCC P46 X0A P47 X1A INITX P48 INT14_1 SIN3_2 SEG32 MAD02_1 P49 TIOB0_0 SEG31 SOT3_2 (SDA3_2) MAD03_1 E L E L E K E K K U K U D F D G B C K V K U Page 18 of 128 CY9AB40NB Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 19 L7 31 J6 - 42 20 K7 32 L7 24 - 43 21 H6 33 K7 25 - 44 22 J7 34 J7 26 - 45 23 K8 35 K8 27 46 24 K9 36 K9 28 47 25 L8 37 L8 29 48 26 L9 38 L9 30 49 27 L10 39 L10 31 50 51 28 29 L11 K11 40 41 L11 K11 32 33 52 30 J11 42 J11 34 53 31 J10 43 J10 35 - Document Number: 002-05631 Rev. *C I/O Circuit Pin State Type Type QFN-64 23 41 Pin Name P4A TIOB1_0 SEG30 SCK3_2 (SCL3_2) MAD04_1 P4B TIOB2_0 SEG29 MAD05_1 P4C TIOB3_0 SCK7_1 (SCL7_1) CEC0 MAD06_1 P4D TIOB4_0 SOT7_1 SDA7_1) MAD07_1 P4E TIOB5_0 INT06_2 SIN7_1 MAD08_1 MD1 PE0 MD0 X0 PE2 X1 PE3 VSS VCC P10 AN00 SEG28 P11 AN01 SIN1_1 INT02_1 WKUP1 SEG27 MAD09_1 K U K U I* S I* K I* L C E G D A A A B L W L R Page 19 of 128 CY9AB40NB Series Pin No LQFP-100 QFP-10 0 BGA-112 LQFP-80 I/O BGA-96 54 32 J8 44 J8 - - K10 J9 - K10 J9 55 33 H10 45 H10 LQFP-64 36 - 37 38 34 H9 46 H9 - 39 57 35 H7 47 G10 - 58 36 G10 48 G9 59 37 G9 49 F10 60 61 62 38 39 40 H11 F11 G11 50 51 52 H11 F11 G11 Document Number: 002-05631 Rev. *C Circuit - 40 41 42 43 Pin State Type Type QFN-64 - 56 Pin Name P12 AN02 SOT1_1.(SDA1_1) SEG26 MAD10_1 VSS VSS P13 AN03 SCK1_1 (SCL1_1) RTCCO_1 SEG25 SUBOUT_1 MAD11_1 P14 AN04 INT03_1 SEG24 SIN0_1 MAD12_1 P15 AN05 SEG23 SOT0_1 (SDA0_1) MAD13_1 P16 AN06 SCK0_1 (SCL0_1) SEG22 MAD14_1 P17 AN07 SIN2_2 INT04_1 SEG21 MAD15_1 AVCC AVRH AVSS L W - L W L N L W L W L N - Page 20 of 128 CY9AB40NB Series Pin No LQFP-100 63 QFP-100 41 BGA-112 G8 I/O LQFP-80 53 BGA-96 F9 LQFP-64 Circuit 44 45 64 42 F10 54 E11 - - H8 - - - 65 43 F9 55 E10 - 66 44 E11 56 E9 - 67 45 E10 - - - 68 46 F8 - - - 69 47 E9 - - - 70 48 D11 - - - pin state type Type QFN-64 - Document Number: 002-05631 Rev. *C Pin Name P18 AN08 SOT2_2 (SDA2_2) SEG20 MAD16_1 P19 AN09 SCK2_2 (SCL2_2) SEG19 MAD17_1 VSS P1A AN10 SIN4_1 INT05_1 SEG18 MAD18_1 P1B AN11 SOT4_1 (SDA4_1) SEG17 MAD19_1 P1C AN12 SCK4_1 (SCL4_1) SEG16 MAD20_1 P1D AN13 CTS4_1 SEG15 MAD21_1 P1E AN14 RTS4_1 SEG14 MAD22_1 P1F AN15 ADTG_5 MAD23_1 L W L W - L N L W L W L W L W F M Page 21 of 128 CY9AB40NB Series Pin No BGA-96 LQFP-64 LQFP-100 QFP-100 BGA-112 LQFP-80 - - B10 C9 - - B10 C9 D11 - 71 49 D10 57 D10 46 72 50 E8 58 D9 47 73 51 C11 59 C11 48 74 52 C10 60 C10 - 75 76 53 54 A11 A10 - A11 - - 77 55 A9 61 A10 56 B9 62 B9 79 57 B11 63 B11 49 50 51 - 80 81 58 59 A8 64 A9 52 B8 65 B8 53 Document Number: 002-05631 Rev. *C I/O Circuit Pin State Type Type QFN-64 78 Pin Name VSS VSS VSS P23 AN16 SCK0_0 (SCL0_0) TIOA7_1 SEG13 P22 AN17 SOT0_0 (SDA0_0) TIOB7_1 SEG12 P21 AN18 SIN0_0 INT06_1 WKUP2 SEG11 P20 AN19 INT05_0 CROUT_0 SEG10 MAD24_1 VSS VCC P00 TRSTX MCSX7_1 P01 TCK SWCLK P02 TDI MCSX6_1 P03 TMS SWDIO P04 TDO SWO - L W L W L R L N E J E J E J E J E J Page 22 of 128 CY9AB40NB Series Pin No LQFP-100 QFP-100 BGA-112 I/O LQFP-80 BGA-96 LQFP-64 60 C8 - - - - - D8 - - - 83 61 D9 - - - 66 A8 84 62 A7 - - - - - - A7 - 85 63 B7 - - - 86 64 C7 - - - 87 65 D7 67 C8 54 - Document Number: 002-05631 Rev. *C Circuit Pin State Type Type QFN-64 82 - Pin Name P05 AN20 TRACED0 TIOA5_2 SIN4_2 INT00_1 SEG09 MCSX5_1 VSS P06 AN21 TRACED1 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 SEG08 MCSX4_1 P07 AN22 ADTG_0 SEG07 MCLKOUT_1 TRACED2 SCK4_2 (SCL4_2) VSS P08 AN23 TRACED3 TIOA0_2 CTS4_2 SEG06 MCSX3_1 P09 TRACECLK TIOB0_2 RTS4_2 SEG05 MCSX2_1 P0A SIN4_0 INT00_2 MCSX1_1 L Q - L Q L P - L P K O I* L Page 23 of 128 CY9AB40NB Series Pin No LQFP-100 88 QFP-100 66 BGA-112 A6 LQFP-80 68 I/O BGA-96 C7 LQFP-64 55 56 89 67 B6 69 B7 - - D4 C3 - C3 - 90 68 C6 70 B6 - 91 69 A5 71 C6 - - - - - A5 - 92 70 B5 72 A6 57 93 71 D6 73 B5 - 94 72 C5 74 C5 58 - 73 B4 Document Number: 002-05631 Rev. *C 75 B4 Circuit 59 Pin State Type Type QFN-64 - 95 Pin Name P0B SOT4_0 (SDA4_0) TIOB6_1 MCSX0_1 P0C SCK4_0 (SCL4_0) TIOA6_1 MALE_1 VSS VSS P0D RTS4_0 TIOA3_2 SEG04 MDQM0_1 P0E CTS4_0 TIOB3_2 SEG03 MDQM1_1 VSS P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 P63 INT03_0 SEG02 MWEX_1 P62 SCK5_0 (SCL5_0) ADTG_3 SEG01 MOEX_1 P61 SOT5_0 (SDA5_0) TIOB2_2 UHCONX SEG00 I* K I* K - K U K U - E I K V K U K U Page 24 of 128 CY9AB40NB Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 I/O BGA-96 LQFP-64 Pin Name Circuit 60 74 C4 76 C4 97 75 A4 77 A4 61 98 76 A3 78 A3 62 99 77 A2 79 A2 63 100 78 A1 80 A1 64 Type Type QFN-64 96 Pin State P60 SIN5_0 TIOA2_2 INT15_1 WKUP3 CEC1 MRDY_1 VCC P80 UDM0 P81 UDP0 VSS I* T H H H H - - *: 5 V tolerant I/O Document Number: 002-05631 Rev. *C Page 25 of 128 CY9AB40NB Series 4.2 List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function ADC Pin No Pin Name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 Function Description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Document Number: 002-05631 Rev. *C LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 84 7 18 94 70 12 30 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 71 72 73 74 82 83 84 85 62 85 96 72 48 90 8 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 49 50 51 52 60 61 62 63 A7 D3 F4 C5 D11 E4 J5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 D10 E8 C11 C10 C8 D9 A7 B7 66 7 13 74 12 42 43 44 45 46 47 48 49 53 54 55 56 57 58 59 60 66 - A8 D3 G3 C5 G2 J11 J10 J8 H10 H9 G10 G9 F10 F9 E11 E10 E9 D10 D9 C11 C10 A8 - LQFP/ QFN-64 9 58 8 34 35 36 37 38 39 40 44 45 46 47 48 - Page 26 of 128 CY9AB40NB Series Pin Function Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Pin No Pin Name TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 TIOA6_1 TIOB6_1 Base Timer 7 TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 Function Description Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Document Number: 002-05631 Rev. *C LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 27 19 85 40 9 86 28 20 5 41 10 6 29 21 96 42 11 95 30 22 90 43 12 91 31 23 44 13 32 24 82 45 14 83 5 97 63 18 87 64 6 98 83 19 88 84 7 99 74 20 89 73 8 100 68 21 90 69 9 1 22 91 10 2 60 23 92 61 J4 G3 B7 J6 E1 C7 L5 H1 D1 L7 E2 D2 K5 H2 C4 K7 E3 B4 J5 G4 C6 H6 E4 A5 H5 H3 J7 F1 L6 J2 C8 K8 F2 D9 14 30 9 15 5 31 10 6 16 76 32 11 75 17 70 33 12 71 21 18 34 22 19 35 - H1 K6 E2 H2 D1 J6 E3 D2 H3 C4 L7 G1 B4 J1 B6 K7 G2 C6 L5 J2 J7 K5 J4 K8 - QFN-64 10 22 5 11 23 6 12 60 24 7 59 13 25 8 14 26 15 27 - 89 67 B6 69 B7 56 88 66 A6 68 C7 55 71 72 - 49 50 - D10 E8 - 57 58 - D10 D9 - 46 47 - Page 27 of 128 CY9AB40NB Series Pin Function Debugger Pin No Pin Name SWCLK SWDIO SWO TCK TDI TDO TMS TRACECL K TRACED0 TRACED1 TRACED2 TRACED3 TRSTX External Bus MAD00_1 MAD01_1 MAD02_1 MAD03_1 MAD04_1 MAD05_1 MAD06_1 MAD07_1 MAD08_1 MAD09_1 MAD10_1 MAD11_1 MAD12_1 MAD13_1 MAD14_1 MAD15_1 MAD16_1 MAD17_1 MAD18_1 MAD19_1 MAD20_1 MAD21_1 MAD22_1 MAD23_1 MAD24_1 Function Description LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 78 56 B9 62 B9 50 80 58 A8 64 A9 52 81 59 B8 65 B8 53 78 56 B9 62 B9 50 79 57 B11 63 B11 51 81 59 B8 65 B8 53 80 58 A8 64 A9 52 86 64 C7 - - - Trace data output pins of ETM 82 83 84 85 60 61 62 63 C8 D9 A7 B7 - - - JTAG test reset Input pin 77 55 A9 61 A10 49 External bus interface address bus 31 32 39 40 41 42 43 44 45 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 9 10 17 18 19 20 21 22 23 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 H5 L6 K6 J6 L7 K7 H6 J7 K8 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 21 22 29 30 31 32 33 34 35 43 44 45 46 47 48 49 53 54 55 56 60 L5 K5 J5 K6 J6 L7 K7 J7 K8 J10 J8 H10 H9 G10 G9 F10 F9 E11 E10 E9 C10 - Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin Trace CLK output pin of ETM Document Number: 002-05631 Rev. *C QFN-64 Page 28 of 128 CY9AB40NB Series Pin Function External Bus Pin Name MCSX0_1 MCSX1_1 MCSX2_1 MCSX3_1 MCSX4_1 MCSX5_1 MCSX6_1 MCSX7_1 MDQM0_1 MDQM1_1 MOEX_1 MWEX_1 MADATA00_1 MADATA01_1 MADATA02_1 MADATA03_1 MADATA04_1 MADATA05_1 MADATA06_1 MADATA07_1 MADATA08_1 MADATA09_1 MADATA10_1 MADATA11_1 MADATA12_1 MADATA13_1 MADATA14_1 MADATA15_1 MALE_1 MRDY_1 MCLKOUT_1 Pin No Function Description External bus interface chip select output pin External bus interface byte mask signal output pin External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM External bus interface data bus Address Latch enable signal for multiplex External bus RDY input signal External bus clock output pin Document Number: 002-05631 Rev. *C LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 88 87 86 85 83 82 79 77 90 66 65 64 63 61 60 57 55 68 A6 D7 C7 B7 D9 C8 B11 A9 C6 68 67 63 61 70 C7 C8 B11 A10 B6 QFN-64 - 91 69 A5 71 C6 - 94 72 C5 74 C5 - 93 71 D6 73 B5 - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 C1 C2 B3 D1 D2 D3 D5 E1 E2 E3 E4 F1 F2 F3 G1 G2 2 3 4 5 6 7 8 9 10 11 12 - C1 C2 B3 D1 D2 D3 E1 E2 E3 G1 G2 - - 89 67 B6 69 B7 - 96 74 C4 76 C4 - 84 62 A7 66 A8 - Page 29 of 128 CY9AB40NB Series Pin Function External Interrupt Pin No Pin Name INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT02_0 INT02_1 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_2 INT08_1 INT08_2 INT09_1 INT10_1 INT11_1 INT12_1 INT13_1 INT14_1 INT15_1 NMIX Function Description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin Document Number: 002-05631 Rev. *C LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 2 82 87 3 83 4 53 93 56 9 12 59 10 74 65 11 73 45 80 60 65 81 61 82 31 71 34 87 90 37 88 52 43 89 51 23 C1 C8 D7 C2 D9 B3 J10 D6 H9 E1 E4 G9 E2 C10 F9 E3 C11 K8 2 67 3 4 43 73 46 9 12 49 10 60 55 11 59 35 C1 C8 C2 B3 J10 B5 H9 E2 G2 F10 E3 C10 E10 G1 C11 K8 QFN-64 2 54 3 4 35 38 5 8 40 6 7 48 27 5 83 D1 5 D1 - 14 8 92 86 F2 D5 8 E1 - 15 93 F3 - - - 16 94 G1 - - - 17 95 G2 - - - 27 5 J4 - - - 28 6 L5 - - - 39 17 K6 29 J5 - 96 74 C4 76 C4 60 92 70 B5 72 A6 57 Page 30 of 128 CY9AB40NB Series Pin Pin Function Name GPIO P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P0F P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 Pin No Function Description General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 Document Number: 002-05631 Rev. *C LQFP-100 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 73 72 71 QFP-100 BGA-112 LQFP-80 BGA-96 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 51 50 49 A9 B9 B11 A8 B8 C8 D9 A7 B7 C7 D7 A6 B6 C6 A5 B5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 C11 E8 D10 61 62 63 64 65 66 67 68 69 70 71 72 42 43 44 45 46 47 48 49 53 54 55 56 60 59 58 57 A10 B9 B11 A9 B8 A8 C8 C7 B7 B6 C6 A6 J11 J10 J8 H10 H9 G10 G9 F10 F9 E11 E10 E9 C10 C11 D9 D10 LQFP/ QFN-64 49 50 51 52 53 54 55 56 57 34 35 36 37 38 39 40 44 45 48 47 46 Page 31 of 128 CY9AB40NB Series Pin Pin Function Name GPIO P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P80 P81 PE0 PE2 PE3 Pin No Function Description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Document Number: 002-05631 Rev. *C LQFP-100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 36 37 39 40 41 42 43 44 45 2 3 4 5 6 7 8 96 95 94 93 98 99 46 48 49 QFP-100 BGA-112 LQFP-80 BGA-96 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 5 6 7 8 9 10 14 15 17 18 19 20 21 22 23 80 81 82 83 84 85 86 74 73 72 71 76 77 24 26 27 E1 E2 E3 E4 F1 F2 F3 G1 G2 F4 G3 H1 H2 G4 H3 J2 J4 L5 K5 J5 H5 L6 L3 K3 K6 J6 L7 K7 H6 J7 K8 C1 C2 B3 D1 D2 D3 D5 C4 B4 C5 D6 A3 A2 K9 L9 L10 9 10 11 12 13 14 15 16 17 18 19 21 22 26 27 29 30 31 32 33 34 35 2 3 4 5 6 7 8 76 75 74 73 78 79 36 38 39 E2 E3 G1 G2 G3 H1 H2 H3 J1 J2 J4 L5 K5 L3 K3 J5 K6 J6 L7 K7 J7 K8 C1 C2 B3 D1 D2 D3 E1 C4 B4 C5 B5 A3 A2 K9 L9 L10 LQFP/ QFN-64 5 6 7 8 9 10 11 12 13 14 15 19 20 22 23 24 25 26 27 2 3 4 60 59 58 62 63 28 30 31 Page 32 of 128 CY9AB40NB Series Pin Function Multifunction Serial0 Pin No Pin Name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multifunction Serial1 SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) Function Description Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). Document Number: 002-05631 Rev. *C LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 73 51 C11 59 C11 QFN-64 48 56 34 H9 46 H9 - 72 50 E8 58 D9 47 57 35 H7 47 G10 - 71 49 D10 57 D10 46 58 36 G10 48 G9 - 53 31 J10 43 J10 35 54 32 J8 44 J8 36 55 33 H10 45 H10 37 Page 33 of 128 CY9AB40NB Series Pin No Pin Function Pin Name Function Description LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 QFN-6 4 Multifunction Serial 2 SIN2_2 SOT2_2 (SDA2_2) SCK2_2 (SCL2_2) Multifunction Serial 3 SIN3_1 SIN3_2 SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Multi-function serial interface ch.2 input pin Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). Document Number: 002-05631 Rev. *C 59 37 G9 49 F10 40 63 41 G8 53 F9 44 64 42 F10 54 E11 45 2 80 C1 2 C1 2 39 17 K6 29 J5 - 3 81 C2 3 C2 3 40 18 J6 30 K6 - 4 82 B3 4 B3 4 41 19 L7 31 J6 - Page 34 of 128 CY9AB40NB Series Pin Function Multifunction Serial 4 Pin No Pin Name SIN4_0 SIN4_1 Multi-function serial interface ch.4 input pin SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) RTS4_0 RTS4_1 RTS4_2 CTS4_0 CTS4_1 CTS4_2 Multifunction Serial 5 Function Description SIN5_0 SIN5_2 SOT5_0 (SDA5_0) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_2 (SCL5_2) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 RTS output pin Multi-function serial interface ch.4 CTS input pin Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). Document Number: 002-05631 Rev. *C LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 87 65 D7 67 C8 54 65 43 F9 55 E10 - 82 60 C8 - - - 88 66 A6 68 C7 55 66 44 E11 56 E9 - 83 61 D9 - - - 89 67 B6 69 B7 56 67 45 E10 - - - 84 62 A7 - - - 90 68 C6 70 B6 - 69 47 E9 - - - 86 64 C7 - - - 91 69 A5 71 C6 - 68 46 F8 - - - 85 63 B7 - - - 96 74 C4 76 C4 60 15 93 F3 - - - 95 73 B4 75 B4 59 16 94 G1 - - - 94 72 C5 74 C5 58 17 95 G2 - - - QFN-64 Page 35 of 128 CY9AB40NB Series Pin Function Multifunction Serial 6 Pin No Pin Name SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multifunction Serial 7 SIN7_1 SOT7_1 (SDA7_1) SCK7_1 (SCL7_1) Function Description Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). Document Number: 002-05631 Rev. *C LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 5 83 D1 5 D1 QFN-64 - 12 90 E4 12 G2 8 6 84 D2 6 D2 - 11 89 E3 11 G1 7 7 85 D3 7 D3 - 10 88 E2 10 E3 6 45 23 K8 35 K8 27 44 22 J7 34 J7 26 43 21 H6 33 K7 25 Page 36 of 128 CY9AB40NB Series Pin Function USB Pin Name UDM0 UDP0 UHCONX Real-time clock Low-Power Consumption Mode RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 WKUP0 WKUP1 WKUP2 WKUP3 HDMICEC/ Remote Control Reception LCDC Pin No Function Description USB device/host D – pin USB device/host D + pin USB external pull-up control pin 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 98 76 A3 78 A3 62 99 77 A2 79 A2 63 95 73 B4 75 B4 59 92 55 19 92 55 19 70 33 97 70 33 97 B5 H10 G3 B5 H10 G3 72 45 14 72 45 14 A6 H10 H1 A6 H10 H1 57 37 10 57 37 10 92 70 B5 72 A6 57 53 31 J10 43 J10 35 73 51 C11 59 C11 48 96 74 C4 76 C4 60 QFN-64 CEC0 HDMI-CEC/Remote Control Reception ch.0 input/output pin 43 21 H6 33 K7 25 CEC1 HDMI-CEC/Remote Control Reception ch.1 input/output pin 96 74 C4 76 C4 60 6 84 D2 6 D2 - 5 83 D1 5 D1 - 4 82 B3 4 B3 - VV3 3 81 C2 3 C2 - VV4 2 80 C1 2 C1 2 COM0 21 99 H2 16 H3 12 COM1 20 98 H1 15 H2 11 COM2 19 97 G3 14 H1 10 18 96 F4 13 G3 9 12 90 E4 12 G2 8 COM5 11 89 E3 11 G1 7 COM6 10 88 E2 10 E3 6 COM7 9 87 E1 9 E2 5 VV0 VV1 VV2 COM3 COM4 LCD drive power supply pin LCD common output pin Document Number: 002-05631 Rev. *C Page 37 of 128 CY9AB40NB Series Pin function LCDC Pin name SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 SEG08 SEG09 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 Pin No Function description LCD segment output pin Document Number: 002-05631 Rev. *C LQFP-100 QFP-100 BGA-112 LQFP-80 95 94 93 91 90 86 85 84 83 82 74 73 72 71 69 68 67 66 65 64 63 59 58 57 56 55 54 53 52 42 41 40 39 32 31 24 23 22 8 7 73 72 71 69 68 64 63 62 61 60 52 51 50 49 47 46 45 44 43 42 41 37 36 35 34 33 32 31 30 20 19 18 17 10 9 2 1 100 86 85 B4 C5 D6 A5 C6 C7 B7 A7 D9 C8 C10 C11 E8 D10 E9 F8 E10 E11 F9 F10 G8 G9 G10 H7 H9 H10 J8 J10 J11 K7 L7 J6 K6 L6 H5 J2 H3 G4 D5 D3 75 74 73 71 70 66 60 59 58 57 56 55 54 53 49 48 47 46 45 44 43 42 32 31 30 29 22 21 19 18 17 8 7 BGA-96 B4 C5 B5 C6 B6 A8 C10 C11 D9 D10 E9 E10 E11 F9 F10 G9 G10 H9 H10 J8 J10 J11 L7 J6 K6 J5 K5 L5 J4 J2 J1 E1 D3 LQFP/ QFN-64 59 58 48 47 46 45 44 40 39 38 37 36 35 34 24 23 22 15 14 13 - Page 38 of 128 CY9AB40NB Series Pin Pin Function Name Reset INITX Mode MD0 MD1 Pin No Function Description External Reset Input pin. A reset is valid when INITX=L. Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to Flash memory, MD0=H must be input. Mode 1 pin. During serial programming to Flash memory, MD1=L must be input. Power VCC Power supply Pin VSS GND Pin GND Document Number: 002-05631 Rev. *C LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP/ QFN-64 38 16 K4 28 K4 21 47 25 L8 37 L8 29 46 24 K9 36 K9 28 1 26 35 51 76 97 25 34 50 75 100 79 4 13 29 54 75 3 12 28 53 78 B1 J1 K1 K11 A10 A4 B2 L1 K2 J3 H4 L4 L11 K10 J9 H8 B10 C9 A11 D8 D4 C3 A1 1 25 41 77 20 24 40 80 B1 K1 K11 A4 F1 F2 F3 B2 L1 K2 J3 L6 L4 L11 K10 J9 B10 C9 D11 A11 A7 C3 A5 A1 1 18 33 61 16 32 64 Page 39 of 128 CY9AB40NB Series Pin Function Clock Pin No Pin Name X0 X0A X1 X1A CROUT_0 CROUT_1 ADC power AVCC AVRH ADC GND C pin Function Description Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter analog power supply pin A/D converter analog reference voltage input pin LQFP/ LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 48 26 L9 38 L9 30 36 14 L3 26 L3 19 49 27 L10 39 L10 31 37 15 K3 27 K3 20 74 92 52 70 C10 B5 60 72 C10 A6 57 60 38 H11 50 H11 41 61 39 F11 51 F11 42 QFN-64 AVSS A/D converter GND pin 62 40 G11 52 G11 43 C Power supply stabilization capacity pin 33 11 L2 23 L2 17 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05631 Rev. *C Page 40 of 128 CY9AB40NB Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. Pull-up resistor P-ch − P-ch Digital output − − X1 − − − N-ch Digital output − − R − Oscillation feedback resistor: Approximately 1 MΩ With Standby mode control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA Pull-up resistor control Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control Document Number: 002-05631 Rev. *C Page 41 of 128 CY9AB40NB Series Type Circuit Remarks B − − CMOS level hysteresis input Pull-up resistor: Approximately 33 kΩ − − Open drain output CMOS level hysteresis input Pull-up resistor Digital input C Digital input N-ch Document Number: 002-05631 Rev. *C Digital output Page 42 of 128 CY9AB40NB Series Type Circuit Remarks D It is possible to select the sub oscillation / GPIO function Pull-up When the sub oscillation is selected. resistor − P-ch P-ch Digital output − X1A Oscillation feedback resistor: Approximately 5 MΩ With Standby mode control When the GPIO is selected. N-ch Digital output R Pull-up resistor control − − − − − − CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control Document Number: 002-05631 Rev. *C Page 43 of 128 CY9AB40NB Series Type Circuit Remarks E − − − − − P-ch P-ch N-ch Digital output − − CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output R Pull-up resistor control Digital input Standby mode control F P-ch P-ch Digital output − − − − − − − − − N-ch R CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control Document Number: 002-05631 Rev. *C Page 44 of 128 CY9AB40NB Series Type Circuit Remarks G CMOS level hysteresis input Mode input H GPIO Digital output It is possible to select the USB I/O / GPIO function. GPIO Digital input/output direction When the USB I/O is selected. GPIO Digital input GPIO Digital input circuit control UDP output UDP0/P81 USB Full-speed/Low-speed control − Full-speed, Low-speed control When the GPIO is selected. − − − CMOS level output CMOS level hysteresis input With standby mode control − − − − − − CMOS level output CMOS level hysteresis input 5 V tolerant With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA Available to control PZR registers. When this pin is used as an I2C pin, the digital output P-ch transistor is always off UDP input Differential Differential input USB/GPIO select UDM0/P80 UDM input UDM output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control I P-ch P-ch Digital output − − − N-ch Digital output R Pull-up resistor control Digital input Standby mode control Document Number: 002-05631 Rev. *C Page 45 of 128 CY9AB40NB Series Type Circuit Remarks J P-ch P-ch Digital output − − − − − − − − − N-ch CMOS level output CMOS level hysteresis input With input control LCD-VV input/output With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Pull-up resistor control R Digital input Standby mode control LCD VV input/output LCD VV control K P-ch P-ch Digital output − − − − − − − − − N-ch R CMOS level output CMOS level hysteresis input With input control LCD output With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Pull-up resistor control Digital input Standby mode control LCD output LCD control Document Number: 002-05631 Rev. *C Page 46 of 128 CY9AB40NB Series Type Circuit Remarks L P-ch P-ch Digital output − − − − − − − − − N-ch R CMOS level output CMOS level hysteresis input With input control LCD output With pull-up resistor control With standby mode control Pull-up resistor: Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control LCD output LCD control Document Number: 002-05631 Rev. *C Page 47 of 128 CY9AB40NB Series 6. Handling Precautions Any semiconductor device has inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. 2. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Document Number: 002-05631 Rev. *C Page 48 of 128 CY9AB40NB Series Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Document Number: 002-05631 Rev. *C Page 49 of 128 CY9AB40NB Series Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. 2. 3. 4. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. When necessary, Cypress Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. 2. 3. 4. 5. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. Ground all fixtures and instruments, or protect with anti-static measures. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-05631 Rev. *C Page 50 of 128 CY9AB40NB Series 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05631 Rev. *C Page 51 of 128 CY9AB40NB Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device. Stabilizing supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF Lead type Load capacitance: Approximately 6 pF to 7 pF Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. Document Number: 002-05631 Rev. *C X1(PE3), X1A (P47) Set as External clock input Page 52 of 128 CY9AB40NB Series Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. C Device CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC →AVCC → AVRH Turning off : AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Document Number: 002-05631 Rev. *C Page 53 of 128 CY9AB40NB Series 8. Block Diagram TRSTX,TCK, TDI,TMS TDO TRACEDx, TRACECLK ETM*1 SWJ-DP TPIU* SRAM0 8/16 Kbyte ROM Table 1 Multi-layer AHB (Max 40 MHz) Cortex-M3 Core I @40 MHz(Max) D NVIC Sys AHB-APB Bridge: APB0(Max 40 MHz) Dual-Timer WatchDog Timer (Software) Clock Reset Generator INITX WatchDog Timer (Hardware) SRAM1 8/16 Kbyte On-Chip Flash 64+32 Kbyte/ 128+32 Kbyte/ 256+32 Kbyte Flash I/F Security USB2.0 PHY (Host/ Device) UDP0/UDM0 UHCONX DMAC 8ch. CSV Main Osc Sub Osc PLL CR 4 MHz AHB-AHB Bridge CLK X0 X1 X0A X1A CROUT Source Clock CR 100 kHz MADx External Bus I/F*2 ADTGx TIOAx TIOBx VVx COMx, SEGx CEC0,CEC1 RTCCO, SUBOUT WKUPx Unit 0 Unit 1 Base Timer 16-bit 8ch./ 32-bit 4ch. USB Clock Ctrl PLL Power-On Reset LVD Ctrl MCSXx, MOEX, MWEX, MALE, MRDY, MCLKOUT, MDQMx LVD Regulator C IRQ-Monitor AHB-APB Bridge : APB2 (Max 40 MHz) ANxx MADATAx 12-bit A/D Converter AHB-APB Bridge : APB1 (Max 40 MHz) AVCC, AVSS, AVRH CRC Accelerator Watch Counter External Interrupt Controller 16-pin + NMI INTx NMIX MODE-Ctrl MD0, MD1 P0x, P1x, LCDC GPIO PIN-Function-Ctrl HDMI-CEC/ Remote Reciver Control Real-Time Clock . . . PEx Multi-Function Serial I/F 8ch. (with FIFO ch.4 to ch.7) HW flow control(ch.4)*2 Deep Standby Ctrl SCKx SINx SOTx CTS4 RTS4 *1: For the CY9AFB41LB/MB, CY9AFB42LB/MB, and CY9AFB44LB/MB, ETM is not available. *2: For the CY9AFB41LB, CY9AFB42LB and CY9AFB44LB, the External Bus Interface is not available. And the Multi-function Serial Interface does not support hardware flow control in these products. 9. Memory Size See Memory size in Product Lineup to confirm the memory size. Document Number: 002-05631 Rev. *C Page 54 of 128 CY9AB40NB Series 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 0x4003_F000 Reserved 0x4003_C000 0x4003_B000 0x4003_A000 0x7000_0000 0x6000_0000 External Device Area Reserved 0x4003_9000 0x4003_8000 0x4003_7000 0x4003_6000 0x4003_5000 0x4400_0000 0x4200_0000 0x4000_0000 32Mbytes Bit band alias Peripherals Reserved 0x2400_0000 0x2200_0000 0x1FFF_0000 0x0020_8000 0x0020_0000 See the next page "lMemory Map (2)" for the memory size details. 0x0010_4000 0x0010_0000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 32Mbytes Bit band alias Reserved 0x2008_0000 0x2000_0000 0x4003_4000 0x4002_8000 Reserved 0x4002_7000 A/DC 0x4002_6000 Reserved 0x4002_5000 Base Timer SRAM1 SRAM0 Reserved Flash(Work area) Reserved Security/CR Trim Reserved 0x4001_6000 0x4001_5000 Flash(Main area) 0x0000_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 002-05631 Rev. *C DMAC Reserved USB ch.0 EXT-bus I/F Reserved RTC Watch Counter CRC MFS Reserved USB Clock Ctrl LVD/DS mode HDMI-CEC/ Remote Control Receiver GPIO LCDC Int-Req.Read EXTI Reserved CR Trim Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F Page 55 of 128 CY9AB40NB Series Memory Map (2) MB9AFB44LB/MB/NB MB9AFB42LB/MB/NB 0x2008_0000 MB9AFB41LB/MB/NB 0x2008_0000 Reserved 0x2008_0000 Reserved Reserved 0x2000_4000 0x2000_2000 SRAM1 16Kbytes 0x2000_0000 0x2000_0000 SRAM0 16Kbytes 0x1FFF_E000 0x2000_2000 SRAM1 8Kbytes SRAM0 8Kbytes 0x2000_0000 0x1FFF_E000 SRAM1 8Kbytes SRAM0 8Kbytes 0x1FFF_C000 SA4-7 (8 KBx4) Reserved 0x0010_4000 0x0010_2000 0x0010_0000 0x0020_0000 SA4-7 (8 KBx4) Reserved 0x0010_4000 CR trimming Security 0x0010_2000 0x0010_0000 0x0020_8000 0x0020_0000 SA4-7 (8 KBx4) Reserved Flash(Work area) 32 Kbytes 0x0020_0000 0x0020_8000 Reserved Flash(Work area) 32 Kbytes 0x0020_8000 Reserved Flash(Work area) 32 Kbytes Reserved 0x0010_4000 CR trimming Security 0x0010_2000 0x0010_0000 CR trimming Security Reserved Reserved Reserved 0x0000_0000 SA2-3 (8 KBx2) SA9 (64 KB) SA8 (48 KB) 0x0000_0000 SA2-3 (8 KBx2) 0x0001_0000 SA8 (48 KB) 0x0000_0000 Flash(Main area) 64 Kbytes SA8 (48 KB) 0x0002_0000 Flash(Main area) 128 Kbytes SA9-11 (64 KBx3) Flash(Main area) 256 Kbytes 0x0004_0000 SA2-3 (8 KBx2) Refer to the programming manual for the detail of Flash main area. CY9AB40N/A40N/340N/140N/150R, CY9B520M/320M/120M Series Flash Programming Manual Document Number: 002-05631 Rev. *C Page 56 of 128 CY9AB40NB Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_4FFF Reserved 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt 0x4003_1000 0x4003_1FFF Interrupt source check register 0x4003_2000 0x4003_2FFF LCDC 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/Remote control Receiver 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Memory interface 0x4004_0000 0x4004_FFFF USB ch.0 0x4005_0000 0x4005_FFFF 0x4006_0000 0x4006_0FFF 0x4006_1000 0x41FF_FFFF Document Number: 002-05631 Rev. *C AHB APB0 Flash memory I/F register Reserved Software Watchdog timer Reserved Reserved APB1 A/D Converter Deep standby mode Controller APB2 AHB USB clock generator Reserved DMAC register Reserved Page 57 of 128 CY9AB40NB Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. Document Number: 002-05631 Rev. *C Page 58 of 128 CY9AB40NB Series List of Pin Status Pin status type Power-on Function reset or INITX low-voltage input detection state state Device internal reset state mode or Timer mode, Sleep RTC mode, or mode Sleep mode state Deep standby from RTC mode or Deep Deep standby Stop mode standby state mode state state group Power supply Power Power supply stable unstable A Return Run supply Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable - INITX = 0 INITX = 1 INITX = 1 - - - - stable SPL = 0 SPL = 1 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state SPL = 0 GPIO selected Internal input fixed at 0 SPL = 1 - Hi-Z / Internal input fixed at 0 GPIO selected Input enabled Input enabled Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state/ When oscillation stops[1],, Hi-Z / Internal input fixed at 0 Maintain previous state/ When oscillation stops[1],, Hi-Z / Internal input fixed at 0 Maintain previous state/ When oscillation stops[1],, Hi-Z / Internal input fixed at 0 Maintain previous state/ When oscillation stops[1],, Hi-Z / Internal input fixed at 0 Maintain previous state/ When oscillation stops[1],, Hi-Z / Internal input fixed at 0 B Main crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state/ When oscillation stops[1], Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Document Number: 002-05631 Rev. *C Page 59 of 128 CY9AB40NB Series Pin status type Power-on Function reset or INITX low-voltage input detection state state Device internal reset state Return Run mode or Timer mode, Sleep RTC mode, or mode Sleep mode state Deep standby from RTC mode or Deep Deep standby Stop mode standby state mode state state group Power supply Power Power supply stable unstable supply Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable - INITX = 0 INITX = 1 INITX = 1 - - - - stable SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected E F GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z/ Internal input fixed at 0 Maintain previous state Maintain previous state Maintain previous state/Whe n oscillation stops[2], Hi-Z / Internal input fixed at 0 Maintain previous state/Whe n oscillation stops[2], Hi-Z / Internal input fixed at 0 Maintain previous state/Whe n oscillation stops[2], Hi-Z/ Internal input fixed at 0 Maintain previous state/Whe n oscillation stops[2], Hi-Z/ Internal input fixed at 0 Maintain previous state/Whe n oscillation stops[2], Hi-Z/ Internal input fixed at 0 G Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Document Number: 002-05631 Rev. *C Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Page 60 of 128 CY9AB40NB Series Pin status type Power-on Function reset or INITX low-voltage input detection state state Device internal reset state mode or Timer mode, Sleep RTC mode, or mode Sleep mode state Deep standby from RTC mode or Deep Deep standby Stop mode standby state mode state state group Power supply Power Power supply stable unstable GPIO selected supply INITX = 0 INITX = 1 INITX = 1 - - - - Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled USB I/O pin Setting disabled Setting disabled Setting disabled NMIX selected Setting disabled Setting disabled Setting disabled Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Pull-up / Input enabled Pull-up / Input enabled GPIO selected JTAG selected J GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Resource selected K GPIO selected Document Number: 002-05631 Rev. *C Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable - stable SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Hi-Z at transmission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z at transmission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected H I Return Run Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Page 61 of 128 CY9AB40NB Series Pin status type Power-on Function reset or INITX low-voltage input detection state state Device internal reset state mode or Timer mode, Sleep RTC mode, or mode Sleep mode state Deep standby from RTC mode or Deep Deep standby Stop mode standby state mode state state group Power supply Power Power supply stable unstable External interrupt enabled selected L Return Run Resource other than above selected INITX = 0 INITX = 1 INITX = 1 - - - - Setting disabled Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable - Setting disabled stable SPL = 0 SPL = 1 Maintain previous state Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 SPL = 0 SPL = 1 - GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 GPIO selected Analog input selected supply M Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Analog input selected N External interrupt enabled selected Resource other than above selected Maintain previous state Setting disabled GPIO selected Document Number: 002-05631 Rev. *C Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Page 62 of 128 CY9AB40NB Series Pin status type Power-on Function reset or INITX low-voltage input detection state state Device internal reset state Power supply Trace selected Timer mode, Sleep RTC mode, or mode Sleep mode state Resource other than above selected Analog input selected Deep standby Stop mode standby state mode state Power Power supply stable supply Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable INITX = 0 INITX = 1 INITX = 1 - - - - Setting disabled Power Power supply stable Setting disabled stable SPL = 0 Setting disabled Hi-Z Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected External interrupt enabled selected Resource other than above selected SPL = 0 SPL = 1 - GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Trace output Setting disabled Setting disabled Setting disabled Maintain previous state Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Analog input selected SPL = 1 Trace output Trace selected Resource other than above selected Q from RTC mode or Deep state - GPIO selected P mode or Deep standby group unstable O Return Run Setting disabled GPIO selected Document Number: 002-05631 Rev. *C Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Trace output Maintain previous state Hi-Z / Internal input fixed at 0 Page 63 of 128 CY9AB40NB Series Pin status type Power-on Function reset or INITX low-voltage input detection state state Device internal reset state Return Run mode or Timer mode, Sleep RTC mode, or mode Sleep mode state Power supply Analog input selected Deep standby Stop mode standby state mode state state Power Power supply stable supply Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable stable - INITX = 0 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP input enabled Hi-Z / WKUP input enabled Hi-Z WKUP enabled Maintain previous state R External interrupt enabled selected Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource other than above selected GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state CEC enabled WKUP enabled T from RTC mode or Deep group unstable S Deep standby External interrupt enabled selected Resource other than above selected Setting disabled Setting disabled Maintain previous state Setting disabled Maintain previous state Hi-Z GPIO selected Document Number: 002-05631 Rev. *C Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled GPIO selected Internal input fixed at 0 Maintain previous state Hi-Z / WKUP input enabled Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Page 64 of 128 CY9AB40NB Series Pin status type Power-on Function reset or INITX low-voltage input detection state state Device internal reset state Power supply GPIO selected External interrupt enabled selected Resource other than above selected Analog input selected Y Sleep mode state from RTC mode or Deep Deep standby Stop mode standby state mode state state Power Power supply stable Resource other than above selected resource selected GPIO selected External interrupt enabled selected Resource other than above selected GPIO selected supply Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable INITX = 1 INITX = 1 - - - - Hi-Z Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Setting disabled Setting disabled Setting disabled Maintain previous state stable SPL = 0 Maintain previous state SPL = 1 SPL = 0 SPL = 1 - Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Maintain previous state Maintain previous state Maintain previous state Hi-Z Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Setting disabled Setting disabled Setting disabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected X RTC mode, or mode INITX = 0 GPIO selected W Timer mode, Sleep resource selected V mode or Deep standby group unstable U Return Run Hi-Z Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. 2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. Document Number: 002-05631 Rev. *C Page 65 of 128 CY9AB40NB Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter [1],[2] Power supply voltage Analog power supply voltage[1],[3] Analog reference voltage[1],[3] LCD input voltage [1],[3] Input voltage[1] Symbol VCC AVCC AVRH VV0 to VV4 VI Rating Max VSS + 4.6 VSS + 4.6 VSS + 4.6 V V V VSS - 0.5 VSS + 4.6 V VSS - 0.5 VSS - 0.5 Analog pin input voltage [1] Unit Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VIA VSS - 0.5 Output voltage[1] VO VSS - 0.5 L level maximum output current[4] IOL - L level average output current[5] IOLAV - L level total maximum output current L level total average output current[6] ∑IOL ∑IOLAV - H level maximum output current[4] IOH - H level average output current[5] IOHAV - H level total maximum output current H level total average output current[6] Power consumption Storage temperature ∑IOH ∑IOHAV PD TSTG - 55 VCC + 0.5 (≤ 4.6 V) VSS + 6.5 AVCC + 0.5 (≤ 4.6 V) VCC + 0.5 (≤ 4.6 V) 10 Remarks V V 5 V tolerant V V mA 39 mA 4 10.5 27 100 50 - 10 mA mA mA mA mA mA 39 mA -4 12 27 - 100 - 50 300 + 150 mA mA mA mA mA mW °C P81/UDP0 , P80/UDM0 pins [7] [8] P81/UDP0 , P80/UDM0 pins [7] [8] 1: These parameters are based on the condition that VSS = AVSS = 0V. 2: VCC must not drop below VSS - 0.5V. 3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on. 4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. 5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. 6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms. 7: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). 8: Then P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.Do not exceed any of these ratings. Document Number: 002-05631 Rev. *C Page 66 of 128 CY9AB40NB Series 12.2 Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Power supply voltage LCD input voltage Analog power supply voltage Symbol VCC VVV4 AVCC Conditions - AVRH - Analog reference voltage AVRL Smoothing capacitor Operating temperature CS TA - Value Unit Min 1.65[6] 3.0[6] Max 3.6 3.6 V 2.2[6] 2.2 1.65 2.7 AVCC 3.6 VCC 3.6 AVCC AVCC V V V V AVSS 1 - 40 AVSS 10 + 85 V µF °C Remarks [1], [4] [2] [1], [3] AVCC = VCC AVCC ≥ 2.7 V AVCC< 2.7 V For Regulator[5] 1: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). 2: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). 3: When LCD Controller is used. 4: When LCD Controller is not used. 5: See C Pin in Handling Devices for the connection of the smoothing capacitor. 6: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-05631 Rev. *C Page 67 of 128 CY9AB40NB Series 12.3 DC Characteristics 12.3.1 Current rating (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin ICC Power supply current Conditions name VCC ICCS Value Unit Remarks Typ[3] Max[4] 15.5 21 mA [1], [5] 8.7 12 mA [1], [5] PLL Rrun mode CPU: 40 MHz, Peripheral: 40 MHz CPU: 40 MHz, Peripheral: the clock stops NOP operation High-speed CR Rrun mode CPU/ Peripheral: 4 MHz[2] 1.8 2.9 mA [1] CPU/ Peripheral: 32 kHz 110 680 μA [1], [6] CPU/ Peripheral: 100 kHz 125 700 μA [1] Peripheral: 40 MHz 9 12.5 mA [1], [5] Peripheral: 4 MHz[2] 0.8 1.6 mA [1] Peripheral: 32 kHz 96 670 μA [1], [6] Peripheral: 100 kHz 110 680 μA [1] Sub Rrun mode Low-speed CR Run mode PLL Sleep mode High-speed CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode 1: When all ports are fixed. 2: When setting it to 4 MHz by trimming. 3: TA=+25°C, VCC=3.6 V 4: TA=+85°C, VCC=3.6 V 5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) 6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) Document Number: 002-05631 Rev. *C Page 68 of 128 CY9AB40NB Series Parameter Symbol Pin Conditions name Main Timer mode ICCT Sub Timer mode ICCR RTC mode ICCH Power supply current Stop mode VCC ICCHD ICCRD Deep Standby Stop mode Deep Standby RTC mode Value Unit Remarks Typ[2] Max[2] 2.1 2.5 mA [1], [3] - 3.4 mA [1], [3] 12 35 μA [1], [4] - 330 μA [1], [4] 9.8 29 μA [1], [4] - 280 μA [1], [4] 9 28 μA [1] TA = + 85°C, When LVD is off - 270 μA [1] TA = + 25°C, When LVD is off, When RAM is off 1.25 7 μA [1], [4], [5] TA = + 25°C, When LVD is off, When RAM is on 5.3 18 μA [1], [4], [5] 70 μA [1], [4], [5] 100 μA [1], [4], [5] 1.9 9 μA [1], [5] TA = + 25°C, When LVD is off, When RAM is on 5.9 20 μA [1], [5] TA = + 85°C, When LVD is off, When RAM is off TA = + 85°C, When LVD is off, When RAM is on 75 μA [1], [5] 105 μA [1], [5] TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off, When RAM is off TA = + 85°C, When LVD is off, When RAM is on TA = + 25°C, When LVD is off, When RAM is off - 1: When all ports are fixed. 2: VCC=3.6 V 3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) 4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) 5: RAM on/off setting is on-chip SRAM only. Document Number: 002-05631 Rev. *C Page 69 of 128 CY9AB40NB Series Low-Voltage Detection Current (VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Low-voltage detection circuit (LVD) power supply current Pin Symbol ICCLVD name Conditions Value Typ Max Unit Remarks At operation for reset VCC = 3.6 V 0.13 0.3 μA At not detect At operation for interrupt VCC = 3.6 V 0.13 0.3 μA At not detect VCC Flash Memory Current (VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Flash memory write/erase current Pin Symbol ICCFLASH name VCC Conditions At Write/Erase Value Typ 9.5 Max 11.2 Unit mA Remarks * *: The current at which to write or erase Flash memory, ICCFLASH is added to ICC. A/D Converter Current (VCC = VCC28 = AVCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = AVSS = 0V, TA = - 40°C to +85°C) Parameter Power supply current Reference power supply current Pin Symbol ICCAD ICCAVRH name Conditions Value Typ Max Unit At 1unit operation 0.27 0.42 mA At stop 0.03 10 μA At 1unit operation AVRH=3.6 V 0.72 1.29 mA At stop 0.02 2.6 μA Remarks AVCC AVRH Document Number: 002-05631 Rev. *C Page 70 of 128 CY9AB40NB Series 12.3.2 Pin Characteristics (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Conditions Min H level input voltage (hysteresis input) L level input voltage (hysteresis input) CMOS hysteresis input pin, MD0, MD1 VIHS VCC ≥ 2.7 V VCC × 0.8 VCC < 2.7 V VCC × 0.7 VCC ≥ 2.7 V VCC × 0.8 VCC < 2.7 V VCC × 0.7 5V tolerant input pin CMOS hysteresis input pin, MD0, MD1 Max - VCC + 0.3 V - VSS + 5.5 V VCC ≥ 2.7 V Remark s VCC × 0.2 VSS - 0.3 - V VCC < 2.7 V VCC × 0.3 VCC ≥ 2.7 V VCC × 0.2 VILS 5V tolerant input pin VSS - 0.3 - VCC < 2.7 V 4mA type H level output voltage Unit Typ VOH The pin doubled as USB I/O V VCC × 0.3 VCC ≥ 2.7 V, IOH = - 4 mA VCC - 0.5 VCC < 2.7 V, IOH = - 2 mA VCC - 0.45 - VCC V VCC - 0.4 - VCC V VSS - 0.4 V VSS - 0.4 V VCC = AVCC = AVRH = VSS = AVSS = 0.0 V -5 - +5 μA - - +1.8 μA VCC ≥ 2.7 V 21 33 66 VCC < 2.7 V - - 134 - - 5 15 VCC ≥ 2.7 V, IOH = - 12 mA VCC < 2.7 V, IOH = - 6.5 mA VCC ≥ 2.7 V, IOL = 4 mA 4mA type L level output voltage VCC < 2.7 V, IOL = 2 mA VOL The pin doubled as USB I/O Input leak current Pull-up resistor value Input capacitance IIL RPU CIN CEC0, CEC1 VCC ≥ 2.7 V, IOL = 10.5 mA VCC < 2.7 V, IOL = 5 mA Pull-up pin Other than VCC, VSS, AVCC, AVSS, AVRH Document Number: 002-05631 Rev. *C kΩ pF Page 71 of 128 CY9AB40NB Series 12.4 LCD Characteristics (VCC = 2.2V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name VVV0 VV0 VVV1 VVV2 VVV3 VV1 VV2 VV3 VVV0 VV0 VVV1 VVV2 VVV3 VV1 VV2 VV3 VVV0 VV0 VVV1 VVV2 VVV3 VV1 VV2 VV3 IR100K VV4 IR10K VV4 IR100K VV4 IR10K VV4 IR100K VV4 IR10K VV4 VV4 Static current IOFF_VV4 VV4 VV0 Output Voltage in using external resistor VVV0E VV0 VV0 to VV3 Output voltage (1/4 bias) VV0 to VV3 Output voltage (1/3 bias) VV0 to VV3 Output voltage (1/2 bias) VV4 Active current (1/4 bias) VV4 Active current (1/3 bias) VV4 Active current (1/2 bias) Document Number: 002-05631 Rev. *C Value Conditions Min Unit Typ 0 - VVV4 × 5% VVV4 × 1/4-10% VVV4 × 1/2-10% VVV4 × 3/4-10% - VVV4 × 1/4+10% VVV4 × 1/2+10% VVV4 × 3/4+10% 0 - VVV4 × 5% VVV4 × 1/3-10% VVV4 × 2/3 -10% VVV4 × 2/3-10% - VVV4 × 1/3+10% VVV4 × 2/3+10% VVV4 × 2/3+10% 0 - VVV4 × 5% VVV4 × 1/2-10% VVV4 × 1/2-10% VVV4 × 1/2-10% - VVV4 × 1/2+10% VVV4 × 1/2+10% VVV4 × 1/2+10% V - 10 20 μA - 100 160 μA - 12 30 μA - 120 180 μA - 18 40 μA - 180 270 μA When LCD stops - 0.5 1.5 μA IOL=1 mA - - 0.66 V When using internal dividing resistor When using internal dividing resistor When using internal dividing resistor When using 100 kΩ internal dividing resistor When using 10 kΩ internal dividing resistor When using 100 kΩ internal dividing resistor When using 10 kΩ internal dividing resistor When using 100 kΩ internal dividing resistor When using 10 kΩ internal dividing resistor Remarks Max V V Page 72 of 128 CY9AB40NB Series 12.5 AC Characteristics 12.5.1 Main Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time Internal operating Clock[1] frequency Internal operating clock[1] cycle time Symbo Pin l name fCH tCYLH X0, X1 Value Conditions Min VCC ≥ 2.7 V VCC < 2.7 V 4 4 Max 48 20 - 4 - Unit Remarks MHz When crystal oscillator is connected 48 MHz When using external clock 20.83 250 ns When using external clock PWH/tCYLH, PWL/tCYLH 45 55 % - - 5 ns tCF, tCR fCM - - - 40 MHz When using external clock When using external clock Master clock fCC - - - 40 MHz Base clock (HCLK/FCLK) fCP0 fCP1 - - - 40 40 MHz MHz APB0 bus clock[2] APB1 bus clock[2] fCP2 - - - 40 MHz APB2 bus clock[2] tCYCC tCYCP0 tCYCP1 tCYCP2 - - 25 - ns Base clock (HCLK/FCLK) - - 25 - ns APB0 bus clock[2] - - 25 - ns APB1 bus clock[2] - - 25 - ns APB2 bus clock[2] - 1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 2: For about each APB bus which each peripheral is connected to, see Block Diagram in this datasheet. X0 Document Number: 002-05631 Rev. *C Page 73 of 128 CY9AB40NB Series 12.5.2 Sub Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input frequency Pin Symbol name Value Conditions Min Typ Unit Max - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs PWH/tCYLL, PWL/tCYLL 45 - 55 % When crystal oscillator is connected When using external clock When using external clock When using external clock fCL Input clock cycle tCYLL Input clock pulse width - X0A, X1A Remarks X0A 12.5.3 Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Clock frequency Frequency stabilization time Symbol fCRH tCRWT Value Conditions Min Typ Max TA = + 25°C VCC ≥ 2.7 V 3.96 4 4.04 TA = + 25°C VCC < 2.7 V 3.9 4 4.1 TA = - 40°C to + 85°C 3.84 4 4.16 TA = - 40°C to + 85°C 2.8 - 5.2 - - - 30 Unit MHz Remarks When trimming[1] When not trimming μs [2] 1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. 2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Document Number: 002-05631 Rev. *C Page 74 of 128 CY9AB40NB Series Built-in Low-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Clock frequency 12.5.4 fCRL Value Conditions - Min 50 Typ 100 Max 150 Unit Remarks kHz Operating Conditions of Main and USB PLL Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Value Symbol Min Typ Max [1] PLL oscillation stabilization wait time (LOCK UP time) PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency[2] USB clock frequency[3] Unit tLOCK 100 - - μs fPLLI fPLLO fCLKPLL 4 5 75 - - 16 37 150 40 MHz multiple MHz MHz fCLKSPLL - - 48 MHz Remarks After the M frequency division 1: Time from when the PLL starts operating until the oscillation stabilizes. 2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 3: For more information about USB clock, see Chapter 2-2: USB Clock Generation in FM3 Family Peripheral Manual Communication Macro Part. Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input Main PLL) clock of the (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Min Typ Unit PLL oscillation stabilization wait time[1] (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency[2] fPLLI fPLLO fCLKPLL 3.8 19 4 - 4.2 35 MHz multiple MHz MHz 72 - Remarks Max 150 40 1: Time from when the PLL starts operating until the oscillation stabilizes. 2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: − Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Document Number: 002-05631 Rev. *C Page 75 of 128 CY9AB40NB Series Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock Main PLL PLL macro oscillation clock Main PLL clock (CLKPLL) M divider N divider USB PLL connection Main clock (CLKMO) K divider PLL input clock USB PLL PLL macro oscillation clock USB clock M divider N divider 12.5.5 Reset Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Conditions Min Reset input time tINITX Document Number: 002-05631 Rev. *C INITX - 500 Unit Remarks Max - ns Page 76 of 128 CY9AB40NB Series 12.5.6 Power-on Reset Timing (VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Conditions Unit Min Power supply shut down time tOFF Power ramp rate dV/dt Time until releasing Power-on reset tPRT VCC Typ Remarks Max 1 - - ms *1 Vcc:0.2 V to 1.65 V 0.2 - 1000 mV/μs *2 - 1.34 - 16.09 ms *1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per “13. 5. 5.Reset Input Characteristics”. 1.65V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST RST Active CPU Operation 0.2V tOFF release start Glossary  VDH: detection voltage of Low Voltage detection reset. See “12.8 Low-Voltage Detection Characteristics” Document Number: 002-05631 Rev. *C Page 77 of 128 CY9AB40NB Series 12.5.7 External Bus Timing External bus clock output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Output frequency Symbol tCYCLE Pin name MCLKOUT* Value Conditions Min VCC ≥ 2.7 V - Max 40 VCC < 2.7 V - 20 Unit MHz MHz *: The external bus clock output (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual. When external bus clock is not output, this characteristic does not give any effect on external bus operation. MCLKOUT External bus signal input/output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions VIH Value Unit 0.8 × VCC V 0.2 × VCC V VOH 0.8 × VCC V VOL 0.2 × VCC V Remarks Signal input characteristics VIL Signal output characteristics Input signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL Document Number: 002-05631 Rev. *C Page 78 of 128 CY9AB40NB Series Separate Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter MOEX Min pulse width Symbol tOEW MCSX ↓ → Address output delay time tCSL – AV MOEX ↑ → Address hold time tOEH - AX MCSX ↓ → MOEX ↓ delay time tCSL - OEL Pin name MOEX MCSX[7:0], MAD[24:0] MOEX, MAD[24:0] MOEX, MCSX[7:0] MOEX ↑ → MCSX ↑ time tOEH - CSH MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX, MDQM[1:0] Data set up → MOEX ↑ time tDS - OE MOEX ↑ →Data hold time tDH - OE MWEX Min pulse width tWEW MWEX MWEX ↑ → Address output delay time tWEH - AX MWEX, MAD[24:0] MCSX ↓ → MWEX ↓ delay time tCSL - WEL MOEX, MADATA[15:0] MOEX, MADATA[15:0] MWEX, MCSX[7:0] MWEX ↑ → MCSX ↑ delay time tWEH - CSH MCSX ↓→ MDQM ↓ delay time tCSL-WDQML MCSX, MDQM[1:0] MWEX ↓→ Data output time tCSL - DV MWEX ↑ → Data hold time tWEH - DX MCSX, MADATA[15:0] MWEX, MADATA[15:0] Value Conditions VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V Min Max Unit MCLK×n-3 - -9 -12 MCLK×m-9 MCLK×m-12 30 38 +9 +12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 - 0 - ns MCLK×n-3 - ns 0 MCLK×m-9 MCLK×m-12 0 0 MCLK×n-9 MCLK×n-12 0 MCLK×n-9 MCLK×n-12 MCLK-9 MCLK-12 0 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK+9 MCLK+12 MCLK×m+9 MCLK×m+12 ns ns ns ns ns ns ns ns ns ns ns ns ns Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). Document Number: 002-05631 Rev. *C Page 79 of 128 CY9AB40NB Series MCLK MCSX[7:0] MAD[24:0] MOEX MDQM[1:0] MWEX MADATA[15:0] Document Number: 002-05631 Rev. *C Page 80 of 128 CY9AB40NB Series Separate Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Address delay time Symbol tAV Pin name MCLK, MAD[24:0] tCSL MCSX delay time MCLK, MCSX[7:0] tCSH tREL MOEX delay time MCLK, MOEX tREH Data set up → MCLK ↑ time tDS MCLK, MADATA[15:0] MCLK ↑ → Data hold time tDH MCLK, MADATA[15:0] tWEL MWEX delay time MCLK, MWEX tWEH tDQML MDQM[1:0] delay time MCLK, MDQM[1:0] tDQMH MCLK ↑ → Data output time tODS MCLK, MADATA[15:0] MCLK ↑ → Data hold time tOD MCLK, MADATA[15:0] Value Conditions VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC < 2.7 V VCC ≥ 2.7 V VCC
MB9AFB44LBPMC-G-JNE2 价格&库存

很抱歉,暂时无法提供与“MB9AFB44LBPMC-G-JNE2”相匹配的价格&库存,您可以联系我们找货

免费人工找货