MB9BF406RAPMC-G-JNE2

MB9B400A Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller The MB9B400A Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. ® ® The MB9B400A Series are based on the ARM Cortex -M3 Processor and on-chip Flash memory and SRAM, and peripheral 2 functions, including Motor Control Timers, ADCs and Communication Interfaces (CAN, UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE0 product categories in "FM3 Family Peripheral Manual". Features ® ® 32-bit ARM Cortex -M3 Core Multi-function Serial Interface (Max. 8 channels)  Processor version: r2p0  4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)  Up to 80MHz Frequency Operation  Memory Protection Unit (MPU): improve the reliability of an embedded system  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN 2 I C [UART]  Full-duplex double buffer On-chip Memories  Selection with or without parity supported [Flash memory]  Built-in dedicated baud rate generator  Up to 512 Kbyte  External clock available as a serial clock  Read cycle: 0wait-cycle@up to 60MHz, 2wait-cycle* above  Hardware Flow control : Automatically control the *: Instruction pre-fetch buffer is included. So when CPU access continuously, it becomes 0wait-cycle  Security function for code protection transmission by CTS/RTS (only ch.4)  Various error detect functions available (parity errors, framing errors, and overrun errors) [SRAM] [CSIO] This series contain a total of up to 64Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  Full-duplex double buffer  SRAM0: Up to 32 Kbyte  Built-in dedicated baud rate generator  Overrun error detect function available [LIN]  SRAM1: Up to 32 Kbyte  LIN protocol Rev.2.1 supported CAN Interface (Max. 2 channels)  Compatible with CAN Specification 2.0A/B  Maximum transfer rate: 1 Mbps  Full-duplex double buffer  Master/Slave mode supported  LIN break field generate (can be changed 13-16bit length)  Built-in 32 message buffer  LIN break delimiter generate (can be changed 1-4bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors) Cypress Semiconductor Corporation Document Number: 002-05610 Rev.*B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 28, 2016 MB9B400A Series 2 [I C] Multi-function Timer (Max. 2 units)  Standard-mode (Max.100kbps) / Fast-mode (Max.400Kbps) The Multi-function timer is composed of the following blocks. supported External Bus Interface  Supports SRAM, NOR& NAND Flash device  Up to 8 chip selects  8/16-bit Data width  Up to 25-bit Address bit  16-bit free-run timer × 3ch/unit  Input capture × 4ch/unit  Output compare × 6ch/unit  A/D activation compare × 3ch/unit  Waveform generator × 3ch/unit  16-bit PPG timer × 3ch/unit  Maximum area size : Up to 256 Mbytes The following function can be used to achieve the motor control. DMA Controller (8 channels)  PWM signal output function DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.  DC chopper waveform output function  8 independently configured and operated channels  Dead time function  Transfer can be started by software or request from the  Input capture function built-in peripherals  Transfer address area: 32bit(4Gbyte)  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: byte/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 Quadrature Position/Revolution Counter (QPRC) (Max. 2 units) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  The detection edge of the three external event input pins AIN, A/D Converter (Max. 16 channels) [12-bit A/D Converter]  Successive Approximation Register type  Built-in 3unit BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers  Conversion time: 1.0μs@5V Dual Timer (Two 32-/16-bit Down Counter)  Priority conversion available (priority at 2levels) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each channel.  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) Base Timer (Max. 8 channels) Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot  16-bit PWM timer Watch Counter  16-bit PPG timer  Interval timer: up to 64s (Max.)@ Sub Clock : 32.768 kHz The Watch counter is used for wake up from sleep mode.  16/32-bit reload timer  16/32-bit PWC timer Document Number: 002-05610 Rev.*B Page 2 of 105 MB9B400A Series Watch dog Timer (2 channels) Clock Super Visor (CSV) A watchdog timer can generate interrupts or a reset when a time-out value is reached. Clocks generated by CR oscillators are used to supervise abnormality of the external clocks. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.  External OSC clock failure (clock stop) is detected, reset is "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, "Hardware" watchdog is active in any low-power consumption modes except STOP mode.  External OSC frequency anomaly is detected, interrupt or asserted. reset is asserted. Low Voltage Detector (LVD) External Interrupt Controller Unit  Up to 16 external vectors  Include one non-maskable interrupt (NMI) This series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has been set, Low Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt General Purpose I/O Port  LVD2: auto-reset operation This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. Low-Power Consumption Mode  Capable of pull-up control per pin Three low-power consumption modes supported.  SLEEP  TIMER  Capable of reading pin level directly  STOP  Built-in the port relocate function  Up to 100 high-speed general-purpose I/O Ports@120pin Package Debug  Serial Wire JTAG Debug Port (SWJ-DP) CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity.  Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. CCITT CRC16 and IEEE-802.3 CRC32 are supported. Power Supply  CCITT CRC16 Generator Polynomial: 0x1021  VCC  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 = 2.7 V to 5.5 V: Correspond to the wide range voltage. Clock and Reset [Clocks] Five clock sources (2 ext. osc, 2 CR osc, and Main PLL) that are dynamically selectable.  Main Clock : 4 MHz to 48 MHz  Sub Clock : 32.768 kHz  Built-in high-speed CR Clock : 4 MHz  Built-in low-speed CR Clock : 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pins  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detector reset  Clock supervisor reset Document Number: 002-05610 Rev.*B Page 3 of 105 MB9B400A Series Contents 1. Product Lineup .................................................................................................................................................................. 6 2. Packages ........................................................................................................................................................................... 7 3. Pin Assignment ................................................................................................................................................................. 8 4. List of Pin Functions....................................................................................................................................................... 11 5. I/O Circuit Type................................................................................................................................................................ 39 6. Handling Precautions ..................................................................................................................................................... 43 6.1 Precautions for Product Design ................................................................................................................................... 43 6.2 Precautions for Package Mounting .............................................................................................................................. 44 6.3 Precautions for Use Environment ................................................................................................................................ 45 7. Handling Devices ............................................................................................................................................................ 46 8. Block Diagram ................................................................................................................................................................. 48 9. Memory Size .................................................................................................................................................................... 48 10. Memory Map .................................................................................................................................................................... 49 11. Pin Status in Each CPU State ........................................................................................................................................ 52 12. Electrical Characteristics ............................................................................................................................................... 57 12.1 Absolute Maximum Ratings ......................................................................................................................................... 57 12.2 Recommended Operating Conditions.......................................................................................................................... 59 12.3 DC Characteristics....................................................................................................................................................... 60 12.3.1 Current rating ............................................................................................................................................................... 60 12.3.2 Pin Characteristics ....................................................................................................................................................... 62 12.4 AC Characteristics ....................................................................................................................................................... 63 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 63 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 64 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 64 12.4.4 Operating Conditions of Main PLL(In the case of using main clock for input of PLL) ................................................... 65 12.4.5 Operating Conditions of Main PLL(In the case of using built-in high speed CR) .......................................................... 65 12.4.6 Reset Input Characteristics .......................................................................................................................................... 66 12.4.7 Power-on Reset Timing................................................................................................................................................ 66 12.4.8 External Bus Timing ..................................................................................................................................................... 67 12.4.9 Base Timer Input Timing .............................................................................................................................................. 72 12.4.10 CSIO/UART Timing .................................................................................................................................................. 73 12.4.11 External input timing ................................................................................................................................................. 81 12.4.12 Quadrature Position/Revolution Counter timing ........................................................................................................ 82 2 12.4.13 I C timing .................................................................................................................................................................. 84 12.4.14 ETM timing ............................................................................................................................................................... 85 12.4.15 JTAG timing .............................................................................................................................................................. 86 12.5 12bit A/D Converter ..................................................................................................................................................... 87 12.6 Low-Voltage Detection Characteristics ........................................................................................................................ 90 12.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 90 12.6.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 90 12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 91 12.7.1 Write / Erase time......................................................................................................................................................... 91 12.7.2 Erase/write cycles and data hold time .......................................................................................................................... 91 12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 92 12.8.1 Return Factor: Interrupt ................................................................................................................................................ 92 12.8.2 Return Factor: Reset .................................................................................................................................................... 94 Document Number: 002-05610 Rev.*B Page 4 of 105 MB9B400A Series 13. Example of Characteristic .............................................................................................................................................. 96 14. Ordering Information ...................................................................................................................................................... 98 15. Package Dimensions ...................................................................................................................................................... 99 16. Major Changes .............................................................................................................................................................. 102 Document History ............................................................................................................................................................... 104 Document Number: 002-05610 Rev.*B Page 5 of 105 MB9B400A Series 1. Product Lineup Memory size Product device On-chip Flash memory On-chip SRAM MB9BF404NA/RA 256 Kbyte 32 Kbyte MB9BF405NA/RA 384 Kbyte 48 Kbyte MB9BF406NA/RA 512 Kbyte 64 Kbyte Function MB9BF404NA MB9BF405NA MB9BF406NA Product device Pin count 100 Cortex-M3 80 MHz 2.7 V to 5.5 V 2 ch(Max) 8ch Addr: 25bit (Max.) Data: 8-/16-bit CS: 5(Max.) Support: SRAM, NOR Flash CPU Freq. Power supply voltage range CAN Interface DMAC External Bus Interface Multi-function Serial Interface 2 (UART/CSIO/LIN/I C) Base Timer MFTimer QPRC Dual Timer Watch Counter CRC Accelerator Watchdog timer External Interrupts I/O ports 12 bit A/D converter CSV (Clock Super Visor) LVD (Low Voltage Detector) High-speed Built-in CR Low-speed Debug Function 120 Addr: 25bit (Max.) Data: 8-/16-bit CS: 8(Max.) Support: SRAM, NOR & NAND Flash 8 ch (Max.) 8 ch (Max.) (PWC/ Reload timer/PWM/PPG) A/D activation compare Input capture Free-run timer Output compare Waveform generator PPG MB9BF404RA MB9BF405RA MB9BF406RA 3 ch. 4 ch. 3 ch. 6 ch. 2 units (Max.) 3 ch. 3 ch. 2 ch (Max.) 1 unit 1 unit Yes 1 ch(SW) + 1 ch(HW) 16 pins (Max.)+ NMI × 1 80 pins (Max.) 16 ch (3 units) Yes 2 ch 4 MHz 100 kHz SWJ-DP/ETM 100 pins (Max.) Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the General I/O port according to your function use. See “Electrical Characteristics 12.4 AC Characteristics (12.4.3) Built-in CR Oscillation Characteristics" for accuracy of built-in CR. Document Number: 002-05610 Rev.*B Page 6 of 105 MB9B400A Series 2. Packages Product name Package LQFP: LQI100 (0.5mm pitch) LQFP: LQM120 (0.5mm pitch) BGA: LBC112 (0.8mm pitch) MB9BF404NA MB9BF405NA MB9BF406NA   MB9BF404RA MB9BF405RA MB9BF406RA  -  : Supported Note: Refer to "Package Dimensions" for detailed information on each package. Document Number: 002-05610 Rev.*B Page 7 of 105 MB9B400A Series 3. Pin Assignment LQI100 VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1 P61/SOT5_0/TIOB2_2 P62/SCK5_0/ADTG_3/TX0_2/MAD00 P63/INT03_0/RX0_2/MAD01 P0F/NMIX/MAD02 P0E/CTS4_0/TIOB3_2/IC13_0/MAD03 P0D/RTS4_0/TIOA3_2/IC12_0/MAD04 P0C/SCK4_0/TIOA6_1/IC11_0/MAD05 P0B/SOT4_0/TIOB6_1/IC10_0/MAD06 P0A/SIN4_0/INT00_2/FRCK1_0/MAD07 P09/TRACECLK/TIOB0_2/RTS4_2 P08/TRACED3/TIOA0_2/CTS4_2 P07/TRACED2/ADTG_0/SCK4_2 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (TOP VIEW) VCC 1 75 VSS P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MDATA0 2 74 P20/INT05_0/CROUT/AIN1_1 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MDATA1 3 73 P21/SIN0_0/INT06_1/BIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MDATA2 4 72 P22/SOT0_0/TIOB7_1/ZIN1_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MDATA3 5 71 P23/SCK0_0/TIOA7_1/RTO00_1 P54/SOT6_0/TIOB1_2/RTO14_0/MDATA4 6 70 P1F/AN15/ADTG_5/FRCK0_1/MDATA15 P55/SCK6_0/ADTG_1/RTO15_0/MDATA5 7 69 P1E/AN14/RTS4_1/DTTI0X_1/MDATA14 P56/INT08_2/DTTI1X_0/MCSX7 8 68 P1D/AN13/CTS4_1/IC03_1/MDATA13 P30/AIN0_0/TIOB0_1/INT03_2/MDATA6 9 67 P1C/AN12/SCK4_1/IC02_1/MDATA12 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MDATA7 10 66 P1B/AN11/SOT4_1/IC01_1/MDATA11 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MDQM0 11 65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MDATA10 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MDQM1 12 64 P19/AN09/SCK2_2/MDATA9 P34/FRCK0_0/TIOB4_1/TX0_1/MAD24 13 63 P18/AN08/SOT2_2/MDATA8 P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MAD23 14 62 AVSS P36/IC02_0/SIN5_2/INT09_1/MCSX3 15 61 AVRH P37/IC01_0/SOT5_2/INT10_1/MCSX2 16 60 AVCC P38/IC00_0/SCK5_2/INT11_1 17 59 P17/AN07/SIN2_2/INT04_1/MWEX P39/DTTI0X_0/ADTG_2 18 58 P16/AN06/SCK0_1/MOEX LQFP - 100 42 43 44 45 46 47 48 49 50 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD12 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD11 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD10 MD1 MD0 X0 X1 VSS 39 P48/DTTI1X_1/INT14_1/SIN3_2/MAD16 41 38 INITX P4B/TIOB2_0/IC12_1/ZIN0_1/MAD13 37 P47/X1A 40 36 P46/X0A P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD15 35 VCC P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD14 34 VCC 33 51 VSS 25 32 P10/AN00 VSS C P11/AN01/SIN1_1/INT02_1/RX1_2 52 P45/TIOA5_0/RTO15_1/MAD17 53 24 31 23 P3F/RTO05_0/TIOA5_1 P44/TIOA4_0/RTO14_1/MAD18 P12/AN02/SOT1_1/TX1_2/MAD09 P3E/RTO04_0/TIOA4_1 30 54 29 22 P43/TIOA3_0/RTO13_1/ADTG_7/MAD19 P13/AN03/SCK1_1/MAD08 P3D/RTO03_0/TIOA3_1 28 55 P42/TIOA2_0/RTO12_1/MAD20 21 P41/TIOA1_0/RTO11_1/INT13_1/MAD21 P14/AN04/SIN0_1/INT03_1/MCSX1 P3C/RTO02_0/TIOA2_1 27 P15/AN05/SOT0_1/MCSX0 56 26 57 20 VCC 19 P40/TIOA0_0/RTO10_1/INT12_1/MAD22 P3A/RTO00_0/TIOA0_1 P3B/RTO01_0/TIOA1_1 Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05610 Rev.*B Page 8 of 105 MB9B400A Series LQM120 VSS P81 P80 VCC P60/SIN5_0/TIOA2_2/INT15_1 P61/SOT5_0/TIOB2_2 P62/SCK5_0/ADTG_3/TX0_2/MAD00 P63/INT03_0/SIN5_1/RX0_2/MAD01 P64/TIOA7_0/SOT5_1/INT10_2 P65/TIOB7_0/SCK5_1 P66/SIN3_0/ADTG_8/INT11_2 P67/SOT3_0/TIOA7_2 P68/SCK3_0/TIOB7_2/INT12_2 P0F/NMIX/MAD02 P0E/CTS4_0/TIOB3_2/IC13_0/MAD03 P0D/RTS4_0/TIOA3_2/IC12_0/MAD04 P0C/SCK4_0/TIOA6_1/IC11_0/MAD05 P0B/SOT4_0/TIOB6_1/IC10_0/MAD06 P0A/SIN4_0/INT00_2/FRCK1_0/MAD07 P09/TRACECLK/TIOB0_2/RTS4_2 P08/TRACED3/TIOA0_2/CTS4_2 P07/TRACED2/ADTG_0/SCK4_2 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VCC P41/TIOA1_0/RTO11_1/INT13_1/MAD21 P42/TIOA2_0/RTO12_1/MAD20 P43/TIOA3_0/RTO13_1/ADTG_7/MAD19 P44/TIOA4_0/RTO14_1/MAD18 P45/TIOA5_0/RTO15_1/MAD17 C VSS VCC P46/X0A P47/X1A INITX P48/DTTI1X_1/INT14_1/SIN3_2/MAD16 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD15 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD14 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD13 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD12 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD11 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD10 P70/TX0_0/TIOA4_2 P71/RX0_0/INT13_2/TIOB4_2 P72/SIN2_0/INT14_2 P73/SOT2_0/INT15_2 P74/SCK2_0 MD1 MD0 X0 X1 VSS LQFP - 120 P40/TIOA0_0/RTO10_1/INT12_1/MAD22 VCC P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MDATA0 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MDATA1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MDATA2 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MDATA3 P54/SOT6_0/TIOB1_2/RTO14_0/MDATA4 P55/SCK6_0/ADTG_1/RTO15_0/MDATA5 P56/SIN1_0/INT08_2/DTTI1X_0/MCSX7 P57/SOT1_0/MNALE P58/SCK1_0/MNCLE P59/SIN7_0/RX1_1/INT09_2/MNWEX P5A/SOT7_0/TX1_1/MNREX P5B/SCK7_0 P30/AIN0_0/TIOB0_1/INT03_2/MDATA6 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MDATA7 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MDQM0 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MDQM1 P34/FRCK0_0/TIOB4_1/TX0_1/MAD24 P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MAD23 P36/IC02_0/SIN5_2/INT09_1/MCSX3 P37/IC01_0/SOT5_2/INT10_1/MCSX2 P38/IC00_0/SCK5_2/INT11_1 P39/DTTI0X_0/ADTG_2 P3A/RTO00_0/TIOA0_1 P3B/RTO01_0/TIOA1_1 P3C/RTO02_0/TIOA2_1 P3D/RTO03_0/TIOA3_1 P3E/RTO04_0/TIOA4_1 P3F/RTO05_0/TIOA5_1 VSS 120 (TOP VIEW) VSS P20/INT05_0/CROUT/AIN1_1 P21/SIN0_0/INT06_1/BIN1_1 P22/SOT0_0/TIOB7_1/ZIN1_1 P23/SCK0_0/TIOA7_1/RTO00_1 P24/RX1_0/SIN2_1/INT01_2/RTO01_1 P25/TX1_0/SOT2_1/RTO02_1 P26/SCK2_1/RTO03_1/MCSX4 P27/INT02_2/RTO04_1/MCSX5 P28/ADTG_4/RTO05_1/MCSX6 P1F/AN15/ADTG_5/FRCK0_1/MDATA15 P1E/AN14/RTS4_1/DTTI0X_1/MDATA14 P1D/AN13/CTS4_1/IC03_1/MDATA13 P1C/AN12/SCK4_1/IC02_1/MDATA12 P1B/AN11/SOT4_1/IC01_1/MDATA11 P1A/AN10/SIN4_1/INT05_1/IC00_1/MDATA10 P19/AN09/SCK2_2/MDATA9 P18/AN08/SOT2_2/MDATA8 AVSS AVRH AVCC P17/AN07/SIN2_2/INT04_1/MWEX P16/AN06/SCK0_1/MOEX P15/AN05/SOT0_1/MCSX0 P14/AN04/SIN0_1/INT03_1/MCSX1 P13/AN03/SCK1_1/MAD08 P12/AN02/SOT1_1/TX1_2/MAD09 P11/AN01/SIN1_1/INT02_1/RX1_2 P10/AN00 VCC Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05610 Rev.*B Page 9 of 105 MB9B400A Series LBC112 Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05610 Rev.*B Page 10 of 105 MB9B400A Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin no. BGA-112 LQFP-100 1 B1 1 I/O circuit type Pin name LQFP-120 VCC Pin state type - P50 INT00_0 AIN0_2 2 C1 2 SIN3_1 E H E H E H E H E I RTO10_0 (PPG10_0) MDATA0 P51 INT01_0 BIN0_2 3 C2 3 SOT3_1 (SDA3_1) RTO11_0 (PPG10_0) MDATA1 P52 INT02_0 ZIN0_2 4 B3 4 SCK3_1 (SCL3_1) RTO12_0 (PPG12_0) MDATA2 P53 SIN6_0 TIOA1_2 5 D1 5 INT07_2 RTO13_0 (PPG12_0) MDATA3 P54 SOT6_0 (SDA6_0) 6 D2 6 TIOB1_2 RTO14_0 (PPG14_0) MDATA4 Document Number: 002-05610 Rev.*B Page 11 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P55 SCK6_0 (SCL6_0) 7 D3 7 ADTG_1 E I E H E I E I E H E I E I E H RTO15_0 (PPG14_0) MDATA5 P56 SIN1_0 (120pin only) 8 D5 8 INT08_2 DTTI1X_0 MCSX7 P57 - - 9 SOT1_0 (SDA1_0) MNALE P58 - - 10 SCK1_0 (SCL1_0) MNCLE P59 SIN7_0 - - 11 RX1_1 INT09_2 MNWEX P5A - - 12 SOT7_0 (SDA7_0) TX1_1 MNREX P5B - - 13 SCK7_0 (SCL7_0) P30 AIN0_0 9 E1 14 TIOB0_1 INT03_2 MDATA6 Document Number: 002-05610 Rev.*B Page 12 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P31 BIN0_0 TIOB1_1 10 E2 15 SCK6_1 (SCL6_1) E H E H E H E I E H E H E H INT04_2 MDATA7 P32 ZIN0_0 TIOB2_1 11 E3 16 SOT6_1 (SDA6_1) INT05_2 MDQM0 P33 INT04_0 12 E4 17 TIOB3_1 SIN6_1 ADTG_6 MDQM1 P34 FRCK0_0 13 F1 18 TIOB4_1 TX0_1 MAD24 P35 IC03_0 14 F2 19 TIOB5_1 RX0_1 INT08_1 MAD23 P36 IC02_0 15 F3 20 SIN5_2 INT09_1 MCSX3 P37 IC01_0 16 G1 21 SOT5_2 (SDA5_2) INT10_1 MCSX2 Document Number: 002-05610 Rev.*B Page 13 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P38 IC00_0 17 G2 22 SCK5_2 (SCL5_2) E H E I G I INT11_1 P39 18 F4 23 DTTI0X_0 ADTG_2 P3A 19 G3 24 RTO00_0 (PPG00_0) TIOA0_1 - B2 - VSS - P3B 20 H1 25 RTO01_0 (PPG00_0) G I G I G I G I G I TIOA1_1 P3C 21 H2 26 RTO02_0 (PPG02_0) TIOA2_1 P3D 22 G4 27 RTO03_0 (PPG02_0) TIOA3_1 P3E 23 H3 28 RTO04_0 (PPG04_0) TIOA4_1 P3F 24 J2 29 RTO05_0 (PPG04_0) TIOA5_1 25 L1 30 VSS - 26 J1 31 VCC - P40 TIOA0_0 27 J4 32 RTO10_1 (PPG10_1) G H INT12_1 MAD22 Document Number: 002-05610 Rev.*B Page 14 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P41 TIOA1_0 28 L5 33 RTO11_1 (PPG10_1) G H G I G I INT13_1 MAD21 P42 TIOA2_0 29 K5 34 RTO12_1 (PPG12_1) MAD20 P43 TIOA3_0 30 J5 35 RTO13_1 (PPG12_1) ADTG_7 MAD19 - K2 - VSS - - J3 - VSS - - H4 - VSS - P44 TIOA4_0 31 H5 36 RTO14_1 (PPG14_1) G I G I MAD18 P45 TIOA5_0 32 L6 37 RTO15_1 (PPG14_1) MAD17 33 L2 38 C - 34 L4 39 VSS - 35 K1 40 VCC - 36 L3 41 37 K3 42 38 K4 43 P46 X0A P47 X1A INITX D M D N B C E H P48 DTTI1X_1 39 K6 44 INT14_1 SIN3_2 MAD16 Document Number: 002-05610 Rev.*B Page 15 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P49 TIOB0_0 IC10_1 40 J6 45 AIN0_1 E I E I E I E I E I E H E I SOT3_2 (SDA3_2) MAD15 P4A TIOB1_0 IC11_1 41 L7 46 BIN0_1 SCK3_2 (SCL3_2) MAD14 P4B TIOB2_0 42 K7 47 IC12_1 ZIN0_1 MAD13 P4C TIOB3_0 IC13_1 43 H6 48 SCK7_1 (SCL7_1) AIN1_2 MAD12 P4D TIOB4_0 FRCK1_1 44 J7 49 SOT7_1 (SDA7_1) BIN1_2 MAD11 P4E TIOB5_0 INT06_2 45 K8 50 SIN7_1 ZIN1_2 MAD10 P70 - - 51 TX0_0 TIOA4_2 Document Number: 002-05610 Rev.*B Page 16 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P71 RX0_0 - - 52 INT13_2 E H E H E H TIOB4_2 P72 - - 53 SIN2_0 INT14_2 P73 - - 54 SOT2_0 (SDA2_0) INT15_2 P74 - - 55 SCK2_0 (SCL2_0) E I 46 K9 56 MD1 C D 47 L8 57 MD0 C D 48 L9 58 X0 A A 49 L10 59 X1 A B 50 L11 60 VSS - 51 K11 61 VCC - 52 J11 62 P10 AN00 F K F L P11 AN01 53 J10 63 SIN1_1 INT02_1 RX1_2 - K10 - VSS - - J9 - VSS - P12 AN02 54 J8 64 SOT1_1 (SDA1_1) F K F K TX1_2 MAD09 P13 AN03 55 H10 65 SCK1_1 (SCL1_1) MAD08 Document Number: 002-05610 Rev.*B Page 17 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P14 AN04 56 H9 66 SIN0_1 F L F K F K F L INT03_1 MCSX1 P15 AN05 57 H7 67 SOT0_1 (SDA0_1) MCSX0 P16 AN06 58 G10 68 SCK0_1 (SCL0_1) MOEX P17 AN07 59 G9 69 SIN2_2 INT04_1 MWEX 60 H11 70 AVCC - 61 F11 71 AVRH - 62 G11 72 AVSS - P18 AN08 63 G8 73 SOT2_2 (SDA2_2) F K F K F L MDATA8 P19 AN09 64 F10 74 SCK2_2 (SCL2_2) MDATA9 P1A AN10 65 F9 75 SIN4_1 INT05_1 IC00_1 MDATA10 - H8 Document Number: 002-05610 Rev.*B - VSS - Page 18 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P1B AN11 66 E11 76 SOT4_1 (SDA4_1) F K F K F K F K F K E I E H E I IC01_1 MDATA11 P1C AN12 67 E10 77 SCK4_1 (SCL4_1) IC02_1 MDATA12 P1D AN13 68 F8 78 CTS4_1 IC03_1 MDATA13 P1E AN14 69 E9 79 RTS4_1 DTTI0X_1 MDATA14 P1F AN15 70 D11 80 ADTG_5 FRCK0_1 MDATA15 P28 ADTG_4 - - 81 RTO05_1 (PPG04_1) MCSX6 P27 INT02_2 - - 82 RTO04_1 (PPG04_1) MCSX5 P26 - - 83 SCK2_1 (SCL2_1) RTO03_1 (PPG02_1) MCSX4 Document Number: 002-05610 Rev.*B Page 19 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 - - 84 - B10 C9 - - - 85 I/O circuit type Pin name LQFP-120 P25 TX1_0 SOT2_1 (SDA2_1) RTO02_1 (PPG02_1) VSS VSS P24 RX1_0 SIN2_1 E Pin state type I - E H E I E I E H E H INT01_2 RTO01_1 (PPG00_1) P23 SCK0_0 (SCL0_0) 71 D10 86 TIOA7_1 RTO00_1 (PPG00_1) 72 E8 87 P22 SOT0_0 (SDA0_0) TIOB7_1 ZIN1_1 P21 SIN0_0 73 C11 88 INT06_1 BIN1_1 74 C10 89 75 76 A11 A10 90 91 77 A9 92 78 B9 93 79 B11 94 Document Number: 002-05610 Rev.*B P20 INT05_0 CROUT AIN1_1 VSS VCC P00 TRSTX P01 TCK SWCLK P02 TDI E E E E E E Page 20 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P03 80 A8 95 TMS E E E E E F SWDIO P04 81 B8 96 TDO SWO P05 TRACED0 82 C8 97 TIOA5_2 SIN4_2 INT00_1 - D8 - VSS - P06 TRACED1 83 D9 98 TIOB5_2 SOT4_2 (SDA4_2) E F E G E G E G E H E I INT01_1 P07 TRACED2 84 A7 99 ADTG_0 SCK4_2 (SCL4_2) P08 85 B7 100 TRACED3 TIOA0_2 CTS4_2 P09 86 C7 101 TRACECLK TIOB0_2 RTS4_2 P0A SIN4_0 87 D7 102 INT00_2 FRCK1_0 MAD07 P0B SOT4_0 (SDA4_0) 88 A6 103 TIOB6_1 IC10_0 MAD06 Document Number: 002-05610 Rev.*B Page 21 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P0C SCK4_0 (SCL4_0) 89 B6 104 TIOA6_1 E I E I E I IC11_0 MAD05 P0D RTS4_0 90 C6 105 TIOA3_2 IC12_0 MAD04 P0E CTS4_0 91 A5 106 TIOB3_2 IC13_0 MAD03 - D4 - VSS - - C3 - VSS - P0F 92 B5 107 NMIX E J E H E I E H E I E H MAD02 P68 - - 108 SCK3_0 (SCL3_0) TIOB7_2 INT12_2 P67 - - 109 SOT3_0 (SDA3_0) TIOA7_2 P66 - - 110 SIN3_0 ADTG_8 INT11_2 P65 - - 111 TIOB7_0 SCK5_1 (SCL5_1) P64 TIOA7_0 - - 112 SOT5_1 (SDA5_1) INT10_2 Document Number: 002-05610 Rev.*B Page 22 of 105 MB9B400A Series Pin no. BGA-112 LQFP-100 I/O circuit type Pin name LQFP-120 Pin state type P63 93 D6 - - INT03_0 113 RX0_2 E H E I E I E H MAD01 SIN5_1 P62 SCK5_0 (SCL5_0) 94 C5 114 ADTG_3 TX0_2 MAD00 P61 95 B4 115 SOT5_0 (SDA5_0) TIOB2_2 P60 96 C4 116 SIN5_0 TIOA2_2 INT15_1 97 A4 117 VCC - 98 A3 118 P80 H O 99 A2 119 P81 H O 100 A1 120 VSS - Document Number: 002-05610 Rev.*B Page 23 of 105 MB9B400A Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module ADC Base Timer 0 Base Timer 1 Base Timer 2 Pin name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 Document Number: 002-05610 Rev.*B Function A/D converter external trigger input pin. A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin. Base timer ch.0 TIOB pin. Base timer ch.1 TIOA pin. Base timer ch.1 TIOB pin. Base timer ch.2 TIOA pin. Base timer ch.2 TIOB pin. LQFP-100 84 7 18 94 70 12 30 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 27 19 85 40 9 86 28 20 5 41 10 6 29 21 96 42 11 95 Pin No. BGA-112 A7 D3 F4 C5 D11 E4 J5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 J4 G3 B7 J6 E1 C7 L5 H1 D1 L7 E2 D2 K5 H2 C4 K7 E3 B4 LQFP-120 99 7 23 114 81 80 17 35 110 62 63 64 65 66 67 68 69 73 74 75 76 77 78 79 80 32 24 100 45 14 101 33 25 5 46 15 6 34 26 116 47 16 115 Page 24 of 105 MB9B400A Series Module Base Timer 3 LQFP-100 30 Pin No. BGA-112 J5 35 22 G4 27 TIOA3_2 90 C6 105 TIOB3_0 43 H6 48 12 E4 17 TIOB3_2 91 A5 106 TIOA4_0 31 H5 36 23 H3 28 TIOA4_2 - - 51 TIOB4_0 44 J7 49 13 F1 18 TIOB4_2 - - 52 TIOA5_0 32 L6 37 Pin name TIOA3_0 TIOA3_1 TIOB3_1 Base Timer 4 TIOA4_1 TIOB4_1 Base Timer 5 Function TIOA5_1 Base timer ch.3 TIOA pin. Base timer ch.3 TIOB pin. Base timer ch.4 TIOA pin. Base timer ch.4 TIOB pin. 24 J2 29 TIOA5_2 82 C8 97 TIOB5_0 45 K8 50 14 F2 19 83 D9 98 TIOB5_1 Base timer ch.5 TIOA pin. LQFP-120 Base timer ch.5 TIOB pin. TIOB5_2 Base Timer 6 TIOA6_1 Base timer ch.6 TIOA pin. 89 B6 104 TIOB6_1 Base timer ch.6 TIOB pin. 88 A6 103 Base Timer 7 TIOA7_0 - - 112 71 D10 86 TIOA7_2 - - 109 TIOB7_0 - - 111 TIOA7_1 TIOB7_1 CAN 0 72 E8 87 TIOB7_2 - - 108 TX0_0 - - 51 TX0_1 Base timer ch.7 TIOB pin. 13 F1 18 TX0_2 94 C5 114 RX0_0 - - 52 RX0_1 CAN 1 Base timer ch.7 TIOA pin. CAN interface ch.0 TX output. 14 F2 19 RX0_2 93 D6 113 TX1_0 - - 84 TX1_1 CAN interface ch.0 RX input. - - 12 TX1_2 54 J8 64 RX1_0 - - 85 - - 11 53 J10 63 RX1_1 RX1_2 Document Number: 002-05610 Rev.*B CAN interface ch.1 TX output. CAN interface ch.1 RX input. Page 25 of 105 MB9B400A Series Module Debugger External Bus Pin name SWCLK SWDIO SWO TCK TDI TDO TMS TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRSTX MAD00 MAD01 MAD02 MAD03 MAD04 MAD05 MAD06 MAD07 MAD08 MAD09 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 MAD16 MAD17 MAD18 MAD19 MAD20 MAD21 MAD22 MAD23 MAD24 MCSX0 MCSX1 MCSX2 MCSX3 MCSX4 MCSX5 MCSX6 MCSX7 Document Number: 002-05610 Rev.*B Function Serial wire debug interface clock input. Serial wire debug interface data input / output. Serial wire viewer output. JTAG test clock input. JTAG test data input. JTAG debug data output. JTAG test mode state input/output. Trace CLK output of ETM. Trace data output of ETM. JTAG test reset Input. External bus interface address bus. External bus interface chip select output pin. LQFP-100 78 80 81 78 79 81 80 86 82 83 84 85 77 94 93 92 91 90 89 88 87 55 54 45 44 43 42 41 40 39 32 31 30 29 28 27 14 13 57 56 16 15 8 Pin No. BGA-112 B9 A8 B8 B9 B11 B8 A8 C7 C8 D9 A7 B7 A9 C5 D6 B5 A5 C6 B6 A6 D7 H10 J8 K8 J7 H6 K7 L7 J6 K6 L6 H5 J5 K5 L5 J4 F2 F1 H7 H9 G1 F3 D5 LQFP-120 93 95 96 93 94 96 95 101 97 98 99 100 92 114 113 107 106 105 104 103 102 65 64 50 49 48 47 46 45 44 37 36 35 34 33 32 19 18 67 66 21 20 83 82 81 8 Page 26 of 105 MB9B400A Series Module External Bus Pin name MDATA0 MDATA1 MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 MDATA7 MDATA8 MDATA9 MDATA10 MDATA11 MDATA12 MDATA13 MDATA14 MDATA15 MDQM0 MDQM1 MNALE MNCLE MNREX MNWEX MOEX MWEX Function External bus interface data bus. External bus interface byte mask signal output. External bus interface ALE signal to control NAND Flash output pin. External bus interface CLE signal to control NAND Flash output pin. External bus interface read enable signal to control NAND Flash. External bus interface write enable signal to control NAND Flash. External bus interface read enable signal for SRAM. External bus interface write enable signal for SRAM. Document Number: 002-05610 Rev.*B LQFP-100 2 3 4 5 6 7 9 10 63 64 65 66 67 68 69 70 11 12 Pin No. BGA-112 C1 C2 B3 D1 D2 D3 E1 E2 G8 F10 F9 E11 E10 F8 E9 D11 E3 E4 2 3 4 5 6 7 14 15 73 74 75 76 77 78 79 80 16 17 - - 9 - - 10 - - 12 - - 11 58 59 G10 G9 68 69 LQFP-120 Page 27 of 105 MB9B400A Series Module External Interrupt Pin name INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT01_2 INT02_0 INT02_1 INT02_2 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_2 INT08_1 INT08_2 INT09_1 INT09_2 INT10_1 INT10_2 INT11_1 INT11_2 INT12_1 INT12_2 INT13_1 INT13_2 INT14_1 INT14_2 INT15_1 INT15_2 NMIX Document Number: 002-05610 Rev.*B Function External interrupt request 00 input pin. External interrupt request 01 input pin. External interrupt request 02 input pin. External interrupt request 03 input pin. External interrupt request 04 input pin. External interrupt request 05 input pin. External interrupt request 06 input pin. External interrupt request 07 input pin. External interrupt request 08 input pin. External interrupt request 09 input pin. External interrupt request 10 input pin. External interrupt request 11 input pin. External interrupt request 12 input pin. External interrupt request 13 input pin. External interrupt request 14 input pin. External interrupt request 15 input pin. Non-Maskable Interrupt input. LQFP-100 2 82 87 3 83 4 53 93 56 9 12 59 10 74 65 11 73 45 5 14 8 15 16 17 27 28 39 96 92 Pin No. BGA-112 C1 C8 D7 C2 D9 B3 J10 D6 H9 E1 E4 G9 E2 C10 F9 E3 C11 K8 D1 F2 D5 F3 G1 G2 J4 L5 K6 C4 B5 LQFP-120 2 97 102 3 98 85 4 63 82 113 66 14 17 69 15 89 75 16 88 50 5 19 8 20 11 21 112 22 110 32 108 33 52 44 53 116 54 107 Page 28 of 105 MB9B400A Series Module GPIO Pin name P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P0F P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 P24 P25 P26 P27 P28 Document Number: 002-05610 Rev.*B Function General-purpose I/O port 0. General-purpose I/O port 1. General-purpose I/O port 2. LQFP-100 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 73 72 71 - Pin No. BGA-112 A9 B9 B11 A8 B8 C8 D9 A7 B7 C7 D7 A6 B6 C6 A5 B5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 C11 E8 D10 - LQFP-120 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 62 63 64 65 66 67 68 69 73 74 75 76 77 78 79 80 89 88 87 86 85 84 83 82 81 Page 29 of 105 MB9B400A Series Module GPIO Pin name P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P5A P5B Document Number: 002-05610 Rev.*B Function General-purpose I/O port 3. General-purpose I/O port 4. General-purpose I/O port 5. LQFP-100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 36 37 39 40 41 42 43 44 45 2 3 4 5 6 7 8 - Pin No. BGA-112 E1 E2 E3 E4 F1 F2 F3 G1 G2 F4 G3 H1 H2 G4 H3 J2 J4 L5 K5 J5 H5 L6 L3 K3 K6 J6 L7 K7 H6 J7 K8 C1 C2 B3 D1 D2 D3 D5 - LQFP-120 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 41 42 44 45 46 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 Page 30 of 105 MB9B400A Series Module GPIO Multi Function Serial 0 Pin name P60 P61 P62 P63 P64 P65 P66 P67 P68 P70 P71 P72 P73 P74 P80 P81 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Multi Function Serial 1 SCK0_1 (SCL0_1) SIN1_0 SIN1_1 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Document Number: 002-05610 Rev.*B LQFP-100 96 95 94 93 98 99 73 56 Pin No. BGA-112 C4 B4 C5 D6 A3 A2 C11 H9 LQFP-120 116 115 114 113 112 111 110 109 108 51 52 53 54 55 118 119 88 66 Multifunction serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as 2 SDA0 when it is used in an I C (operation mode 4). 72 E8 87 57 H7 67 Multifunction serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 2 when it is used in an I C (operation mode 4). 71 D10 86 58 G10 68 53 J10 8 63 Multifunction serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as 2 SDA1 when it is used in an I C (operation mode 4). - - 9 54 J8 64 Multifunction serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 2 when it is used in an I C (operation mode 4). - - 10 55 H10 65 Function General-purpose I/O port 6. General-purpose I/O port 7. General-purpose I/O port 8. Multifunction serial interface ch.0 input pin. Multifunction serial interface ch.1 input pin. Page 31 of 105 MB9B400A Series Module Multi Function Serial 2 Multi Function Serial 3 Pin name SIN2_0 SIN2_1 SIN2_2 SOT2_0 (SDA2_0) SOT2_1 (SDA2_1) SOT2_2 (SDA2_2) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) SCK2_2 (SCL2_2) SIN3_0 SIN3_1 SIN3_2 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Document Number: 002-05610 Rev.*B Function Multifunction serial interface ch.2 input pin. Multifunction serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as 2 SDA2 when it is used in an I C (operation mode 4). Multifunction serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 2 when it is used in an I C (operation mode 4). Multifunction serial interface ch.3 input pin. Multifunction serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as 2 SDA3 when it is used in an I C (operation mode 4). Multifunction serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 2 when it is used in an I C (operation mode 4). LQFP-100 59 Pin No. BGA-112 G9 LQFP-120 53 85 69 - - 54 - - 84 63 G8 73 - - 55 - - 83 64 F10 74 - - 110 2 C1 2 39 K6 44 - - 109 3 C2 3 40 J6 45 - - 108 4 B3 4 41 L7 46 Page 32 of 105 MB9B400A Series Module Multi Function Serial 4 Multi Function Serial 5 Pin name SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) RTS4_0 RTS4_1 RTS4_2 CTS4_0 CTS4_1 CTS4_2 SIN5_0 SIN5_1 SIN5_2 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SCK5_2 (SCL5_2) Document Number: 002-05610 Rev.*B Function Multifunction serial interface ch.4 input pin. Multifunction serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as 2 SDA4 when it is used in an I C (operation mode 4). Multifunction serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 2 when it is used in an I C (operation mode 4). Multifunction serial interface ch.4 RTS output pin. Multifunction serial interface ch.4 CTS input pin. Multifunction serial interface ch.5 input pin. Multifunction serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as 2 SDA5 when it is used in an I C (operation mode 4). Multifunction serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 2 when it is used in an I C (operation mode 4). LQFP-100 87 65 82 Pin No. BGA-112 D7 F9 C8 LQFP-120 102 75 97 88 A6 103 66 E11 76 83 D9 98 89 B6 104 67 E10 77 84 A7 99 90 69 86 91 68 85 96 15 C6 E9 C7 A5 F8 B7 C4 F3 105 79 101 106 78 100 116 113 20 95 B4 115 - - 112 16 G1 21 94 C5 114 - - 111 17 G2 22 Page 33 of 105 MB9B400A Series Module Multi Function Serial 6 Multi Function Serial 7 LQFP-100 5 12 Pin No. BGA-112 D1 E4 LQFP-120 5 17 Multifunction serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 2 when it is used in an I C (operation mode 4). 6 D2 6 11 E3 16 Multifunction serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when 2 it is used in an I C (operation mode 4). 7 D3 7 10 E2 15 45 K8 11 50 Multifunction serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 2 when it is used in an I C (operation mode 4). - - 12 44 J7 49 Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when 2 it is used in an I C (operation mode 4). - - 13 43 H6 48 Pin name SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) SIN7_0 SIN7_1 SOT7_0 (SDA7_0) SOT7_1 (SDA7_1) SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) Function Multifunction serial interface ch.6 input pin. Multifunction serial interface ch.7 input pin. Document Number: 002-05610 Rev.*B Page 34 of 105 MB9B400A Series Module Multi Function Timer 0 Pin name DTTI0X_0 DTTI0X_1 FRCK0_0 FRCK0_1 IC00_0 IC00_1 IC01_0 IC01_1 IC02_0 IC02_1 IC03_0 IC03_1 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) Function Pin No. LQFP-100 BGA-112 LQFP-120 18 69 13 70 17 65 16 66 15 67 14 68 F4 E9 F1 D11 G2 F9 G1 E11 F3 E10 F2 F8 23 79 18 80 22 75 21 76 20 77 19 78 Wave form generator output of multi-function timer 0. This pin operates as PPG00 when it is used in PPG 0 output modes. 19 G3 24 71 D10 86 Wave form generator output of multi-function timer 0. This pin operates as PPG00 when it is used in PPG 0 output modes. 20 H1 25 - - 85 Wave form generator output of multi-function timer 0. This pin operates as PPG02 when it is used in PPG 0 output modes. 21 H2 26 - - 84 Wave form generator output of multi-function timer 0. This pin operates as PPG02 when it is used in PPG 0 output modes. 22 G4 27 - - 83 Wave form generator output of multi-function timer 0. This pin operates as PPG04 when it is used in PPG 0 output modes. 23 H3 28 - - 82 Wave form generator output of multi-function timer 0. This pin operates as PPG04 when it is used in PPG 0 output modes. 24 J2 29 - - 81 Input signal controlling wave form generator outputs RTO00 to RTO05 of multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin. 16-bit input capture ch.0 input pin of multi-function timer 0. ICxx desicribes chanel number. Document Number: 002-05610 Rev.*B Page 35 of 105 MB9B400A Series Module Multi Function Timer 1 Pin name DTTI1X_0 DTTI1X_1 FRCK1_0 FRCK1_1 IC10_0 IC10_1 IC11_0 IC11_1 IC12_0 IC12_1 IC13_0 IC13_1 RTO10_0 (PPG10_0) RTO10_1 (PPG10_1) RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) RTO14_1 (PPG14_1) RTO15_0 (PPG14_0) RTO15_1 (PPG14_1) Document Number: 002-05610 Rev.*B LQFP-100 8 39 87 44 88 40 89 41 90 42 91 43 Pin No. BGA-112 D5 K6 D7 J7 A6 J6 B6 L7 C6 K7 A5 H6 LQFP-120 8 44 102 49 103 45 104 46 105 47 106 48 Wave form generator output of multi-function timer 1. This pin operates as PPG10 when it is used in PPG 1 output modes. 2 C1 2 27 J4 32 Wave form generator output of multi-function timer 1. This pin operates as PPG10 when it is used in PPG 1 output modes. 3 C2 3 28 L5 33 Wave form generator output of multi-function timer 1. This pin operates as PPG12 when it is used in PPG 1 output modes. 4 B3 4 29 K5 34 Wave form generator output of multi-function timer 1. This pin operates as PPG12 when it is used in PPG 1 output modes. 5 D1 5 30 J5 35 6 D2 6 31 H5 36 7 D3 7 32 L6 37 Function Input signal controlling wave form generator outputs RTO10 to RTO15 of multi-function timer 1. 16-bit free-run timer ch.1 external clock input pin. 16-bit input capture ch.0 input pin of multi-function timer 1. ICxx desicribes chanel number. Wave form generator output of multi-function timer 1. This pin operates as PPG14 when it is used in PPG 1 output modes. Wave form generator output of multi-function timer 1. This pin operates as PPG14 when it is used in PPG 1 output modes. Page 36 of 105 MB9B400A Series Module Quadrature Position/ Revolution Counter 0 Pin name Function AIN0_0 AIN0_1 9 QPRC ch.0 AIN input pin. Pin No. BGA-112 E1 LQFP-120 14 40 J6 45 AIN0_2 2 C1 2 BIN0_0 10 E2 15 41 L7 46 3 C2 3 11 E3 16 42 K7 47 4 B3 4 74 C10 89 43 H6 48 73 C11 88 44 J7 49 72 E8 87 45 K8 50 BIN0_1 QPRC ch.0 BIN input pin. BIN0_2 ZIN0_0 ZIN0_1 QPRC ch.0 ZIN input pin. ZIN0_2 Quadrature Position/ Revolution Counter 1 LQFP-100 AIN1_1 AIN1_2 BIN1_1 BIN1_2 ZIN1_1 ZIN1_2 Document Number: 002-05610 Rev.*B QPRC ch.1 AIN input pin. QPRC ch.1 BIN input pin. QPRC ch.1 ZIN input pin. Page 37 of 105 MB9B400A Series LQFP-100 38 Pin No. BGA-112 K4 LQFP-120 43 47 L8 57 Main clock (oscillation) input pin. Sub clock (oscillation) input pin. Main clock (oscillation) I/O pin. Sub clock (oscillation) I/O pin. Built-in High-speed CR-osc clock output port. A/D converter analog power pin. A/D converter analog reference voltage input pin. 46 1 26 35 51 76 97 25 34 50 75 100 48 36 49 37 74 60 61 K9 B1 J1 K1 K11 A10 A4 B2 L1 K2 J3 H4 L4 L11 K10 J9 H8 B10 C9 A11 D8 D4 C3 A1 L9 L3 L10 K3 C10 H11 F11 56 1 31 40 61 91 117 30 39 60 90 120 58 41 59 42 89 70 71 AVSS A/D converter GND pin. 62 G11 72 C Power stabilization capacity pin. 33 L2 38 Module Reset Mode Pin name INITX MD0 Power GND Clock Analog Power Analog GND C-pin MD1 VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS X0 X0A X1 X1A CROUT AVCC AVRH Function External Reset Input. A reset is valid when INITX=L. Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to flash memory, MD0=H must be input. Mode 1 pin. Input must always be at the "L" level. Power Pin. GND Pin. Note:  While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05610 Rev.*B Page 38 of 105 MB9B400A Series 5. I/O Circuit Type Type Circuit Remarks • Oscillation feedback resistor : Approximately 1 MΩ • With Standby mode control A X1 Clock input X0 Standby mode control • CMOS level hysteresis input • pull-up resistor : Approximately 50 kΩ B Pull-up resistor Digital input • CMOS level hysteresis input C Mode input Document Number: 002-05610 Rev.*B Page 39 of 105 MB9B400A Series Type Circuit Remarks • It is possible to select the sub oscillation / GPIO function D Pull-up When the sub oscillation is selected. resistor P-ch P-ch Digital output X1A • Oscillation feedback resistor : Approximately 20 MΩ • With Standby mode control When the GPIO is selected. N-ch Digital output R Pull-up resistor control • • • • • CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control Document Number: 002-05610 Rev.*B Page 40 of 105 MB9B400A Series Type Circuit Remarks • • • • • E P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off • +B input is available Digital output R Pull-up resistor control Digital input Standby mode control F P-ch P-ch N-ch R Digital output Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off • +B input is available Pull-up resistor control Digital input Standby mode control Analog input Input control Document Number: 002-05610 Rev.*B Page 41 of 105 MB9B400A Series Type Circuit Remarks • • • • • G P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control pull-up resistor : Approximately 50 kΩ • IOH = -12 mA, IOL = 12 mA • +B input is available Digital output R Pull-up resistor control Digital input Standby mode control • • • • H P-ch N-ch CMOS level output CMOS level hysteresis input With standby mode control IOH = -25.3 mA, IOL = 19.7 mA Digital output Digital output R Digital input Standby mode Control Document Number: 002-05610 Rev.*B Page 42 of 105 MB9B400A Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-05610 Rev.*B Page 43 of 105 MB9B400A Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress 's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-05610 Rev.*B Page 44 of 105 MB9B400A Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05610 Rev.*B Page 45 of 105 MB9B400A Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1,X1A pin should be kept open. ・Example of Using an External Clock Device X0(X0A) Open X1(X1A) 2 Handling when using Multi function serial pin as I C pin 2 2 If it is using multi function serial pin as I C pins, P-ch transistor of digital output is always disable. However, I C pins need to keep the 2 electrical characteristic like other pins and not to connect to external I C bus system with power OFF. Document Number: 002-05610 Rev.*B Page 46 of 105 MB9B400A Series C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. C Device CS VSS GND Mode pins (MD0, MD1) Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC =VCC and AVSS = VSS. Turning on : VCC  AVCC  AVRH Turning off : AVRH  AVCC  VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between FLASH products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between FLASH products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Document Number: 002-05610 Rev.*B Page 47 of 105 MB9B400A Series 8. Block Diagram MB9BF404A/405A/406A TRSTX,TC KTDI,TMS TDO TRACED[3:0], TRACECLK SWJ-DP ETM TPIU ROM Table SRAM0 16/24/32 Kbyte Cortex-M3　Core I @80MHz(Max.) D NVIC Multi-layer AHB (Max.80MHz) MPU Flash I/F Sys AHB-APB Bridge: APB0(Max.40MHz) Dual-Timer WatchDog Timer (Software) Clock Reset Generator INITX WatchDog Timer (Hardware) Security SRAM1 16/24/32 Kbyte DMAC 8ch. CSV X1 X0A X1A CROUT AVCC, AVSS,AVRH Main Osc Sub Osc PLL CR 4MHz AHB-AHB Bridge CLK X0 On-Chip Flash 256/384/512K byte Source Clock CR 100kHz CAN TX0,RX0 CAN TX1,RX1 MAD[24:0] External Bus IF 12-bit A/D Converter MDATA[15:0] MCSX[7:0], MOEX,MWEX, MNALE, MNCLE MNWEX, MNREX, MDQM[1:0] Unit 0 AN[15:0] Unit 1 CAN Prescaler ADTG[8:0] Unit 2 AIN[1:0] BIN[1:0] QPRC 2ch. ZIN[1:0] A/D Activation Compare 3ch. IC0[3:0] IC1[3:0] FRCK[1:0] 16-bit Input Capture 4ch. 16-bit FreeRun Timer 3ch. LVD Ctrl AHB-APB Bridge : APB2 ( Max.40MHz) TIOB[7:0] Power On Reset Base Timer 16-bit 8ch. /32-bit 4ch. AHB-APB Bridge : APB1 (Max.40MHz) TIOA[7:0] Regulator CRC Accelerator Watch Counter External Interrupt Controller 16-pin + NMI INT[15:0] NMIX MD[1:0] MODE-Ctrl P0[F:0], P1[F:0], GPIO Waveform Generator 3ch. 16-bit PPG 3ch. C IRQ-Monitor 16-bit Output Compare 6ch. DTTI[1:0]X RTO0[5:0] RTO1[5:0] LVD PIN-Function-Ctrl ・ ・ Px[x:0], Multi-Function Serial I/F 8ch. (with FIFO ch.4～7) Multi Function Timer x2 *HW flow control(ch.4) SCK[7:0] SIN[7:0] SOT[7:0] CTS4 RTS4 9. Memory Size See “Memory size" in "1.Product Lineup" to confirm the memory size. Document Number: 002-05610 Rev.*B Page 48 of 105 MB9B400A Series 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF Reserved 0x4006_4000 Cortex-M3 Private Peripherals 0x4006_3000 0x4006_2000 0x4006_1000 0x4006_0000 0xE010_0000 0xE000_0000 CAN ch.1 CAN ch.0 Reserved DMAC Reserved 0x4005_0000 Reserved Reserved 0x4004_0000 0x4003_F000 Reserved 0x7000_0000 0x6000_0000 External Device Area Reserved 0x4400_0000 32Mbyte Bit band alias 0x4200_0000 Peripherals 0x4000_0000 Reserved 0x2400_0000 32Mbyte Bit band alias 0x2200_0000 0x2000_0000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_7000 0x4003_6000 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 SRAM1 SRAM0 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x0010_2000 0x0010_0000 A/DC QPRC Base Timer PPG Reserved 0x1FF8_0000 Please refer to the next page for the memory size details. Watch Counter CRC MFS CAN Prescaler Reserved LVD Reserved GPIO Reserved Int-Req. Read EXTI Reserved CR Trim Reserved 0x4002_8000 Reserved 0x2008_0000 EXT-bus I/F Reserved 0x4002_2000 0x4002_1000 Security/CR Trim 0x4002_0000 Flash 0x4001_6000 0x4001_5000 MFT unit1 MFT unit0 Reserved Dual Timer Reserved 0x0000_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 SW WDT HW WDT Clock/Reset Reserved 0x4000_1000 0x4000_0000 Document Number: 002-05610 Rev.*B Flash I/F Page 49 of 105 MB9B400A Series Memory Map (2) MB9BF406NA/RA 0x2008_0000 MB9BF405NA/RA 0x2008_0000 Reserved MB9BF404NA/RA 0x2008_0000 Reserved Reserved 0x2000_8000 0x2000_6000 SRAM1 32kbyte 0x2000_4000 SRAM1 24kbyte 0x2000_0000 0x2000_0000 0x2000_0000 SRAM0 24kbyte SRAM0 32Kbyte 0x1FFF_C000 SRAM1 16kbyte SRAM0 16kbyte 0x1FFF_A000 0x1FFF_8000 0x0010_2000 0x0010_1000 0x0010_0000 Reserved Reserved Reserved 0x0010_2000 0x0010_1000 0x0010_0000 CR trimming Security 0x0010_2000 0x0010_1000 0x0010_0000 CR trimming Security CR trimming Security Reserved Reserved Reserved 0x0008_0000 0x0006_0000 SA10-13(64KBx4) 0x0000_0000 SA4-7(8KBx4) SA8-9(48KBx2) 0x0000_0000 SA4-7(8KBx4) 0x0004_0000 SA10-11(64KBx2) SA8-9(48KBx2) 0x0000_0000 SA4-7(8KBx4) Flash 256Kbyte SA8-9(48KBx2) Flash 384Kbyte Flash 512Kbyte SA10-15(64KBx6) *: See "MB9B500/400/300/100/MB9A100 Series Flash programming Manual" for sector structure of Flash. Document Number: 002-05610 Rev.*B Page 50 of 105 MB9B400A Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_1FFF Multi-function timer unit1 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_5FFF Low Voltage Detector 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Memory interface 0x4004_0000 0x4004_FFFF Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x4006_3FFF CAN ch.1 0x4006_4000 0x41FF_FFFF Reserved Document Number: 002-05610 Rev.*B AHB APB0 APB1 APB2 AHB Flash Memory I/F register Reserved Software Watchdog timer Reserved Base Timer Quadrature Position/Revolution Counter Reserved Reserved Page 51 of 105 MB9B400A Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the "L" level.  INITX=1 This is the period when the INITX pin is the "H" level.  SPL=0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".  SPL=1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used. Document Number: 002-05610 Rev.*B Page 52 of 105 MB9B400A Series List of Pin Status Pin status type A B Function group Main crystal oscillator input pin Main crystal oscillator output pin Power-on reset or low voltage detection state Power supply unstable Input enabled INITX input state Device internal reset state Power supply stable INITX=0 Input enabled INITX=1 Input enabled H output/ Internal input fixed at "0"/ or Input enabled H output/ Internal input fixed at "0" H output/ Internal input fixed at "0" Pull-up/ Input enabled Input enabled Pull-up/ Input enabled Setting disabled C INITX input pin Pull-up/ Input enabled D Mode input pin Input enabled E JTAG selected Hi-Z GPIO selected Setting disabled Pull-up/ Input enabled Input enabled Pull-up/ Input enabled Setting disabled Trace selected External interrupt enabled selected Setting disabled Setting disabled Setting disabled GPIO selected, or other than above resource selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled F Document Number: 002-05610 Rev.*B Run mode or sleep mode state Timer mode or sleep mode state Power supply stable INITX=1 Input enabled SPL=0 Input enabled SPL=1 Input enabled Maintain previous state/ H output at oscillation stop (*1)/ Internal input fixed at "0" Pull-up/ Input enabled Input enabled Maintain previous state Maintain previous state/ H output at oscillation stop (*1)/ Internal input fixed at "0" Pull-up/ Input enabled Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state/ H output at oscillation stop (*1)/ Internal input fixed at "0" Pull-up/ Input enabled Input enabled Maintain previous state Hi-Z/ Internal input fixed at "0" Trace output Maintain previous state Hi-Z/ Internal input fixed at "0" Power supply stable INITX=1 Page 53 of 105 MB9B400A Series Pin status type G Function group Trace selected GPIO selected, or other than above resource selected H Power-on reset or low voltage detection state Power supply unstable Setting disabled Hi-Z INITX input state Device internal reset state Power supply stable INITX=0 Setting disabled Hi-Z/ Input enabled INITX=1 Setting disabled Hi-Z/ Input enabled Run mode or sleep mode state Timer mode or sleep mode state Power supply stable INITX=1 Maintain previous state SPL=0 Maintain previous state Maintain previous state Maintain previous state Power supply stable INITX=1 External interrupt enabled selected Setting disabled Setting disabled Setting disabled GPIO selected, or other than above resource selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled I GPIO selected, resource selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state Maintain previous state J NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO selected, or other than above resource selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Document Number: 002-05610 Rev.*B SPL=1 Trace output Hi-Z/ Internal input fixed at "0" Maintain previous state Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Hi-Z/ Internal input fixed at "0" Page 54 of 105 MB9B400A Series Pin status type K L M Function group Power-on reset or low voltage detection state Power supply unstable Hi-Z INITX input state Device internal reset state Power supply stable Power supply stable INITX=1 Hi-Z/ Internal input fixed at "0"/ Analog input enabled Maintain previous state GPIO selected, or other than above resource selected Setting disabled INITX=0 Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Analog input selected Hi-Z GPIO selected, or other than above resource selected Setting disabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Sub crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Analog input selected Document Number: 002-05610 Rev.*B INITX=1 Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled Run mode or sleep mode state Maintain previous state Hi-Z/ Internal input fixed at "0"/ Analog input enabled Maintain previous state Timer mode or sleep mode state Power supply stable INITX=1 SPL=0 SPL=1 Hi-Z/ Hi-Z/ Internal Internal input fixed at input fixed at "0"/ "0"/ Analog input Analog input enabled enabled Maintain Hi-Z/ previous Internal state input fixed at "0" Maintain Maintain previous previous state state Hi-Z/ Hi-Z/ Internal Internal input fixed at input fixed at "0"/ "0"/ Analog input Analog input enabled enabled Maintain Hi-Z/ previous Internal state input fixed at "0" Maintain Hi-Z/ previous Internal state input fixed at "0" Input enabled Input enabled Page 55 of 105 MB9B400A Series Pin status type N O Power-on reset or low voltage detection state Power supply unstable Setting disabled INITX=0 Setting disabled INITX=1 Setting disabled Sub crystal oscillator output pin Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state GPIO selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state Function group GPIO selected INITX input state Device internal reset state Power supply stable Run mode or sleep mode state Power supply stable INITX=1 Maintain previous state Timer mode or sleep mode state Power supply stable INITX=1 SPL=0 SPL=1 Maintain Hi-Z/ previous state Internal input fixed at "0" Maintain previous state/ Hi-Z at oscillation stop (*2)/ Internal input fixed at "0" Maintain previous state Maintain previous state/ Hi-Z at oscillation stop (*2)/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" *1: Oscillation is stopped at sub timer mode, Low speed CR timer mode, and stop mode. *2: Oscillation is stopped at stop mode. Document Number: 002-05610 Rev.*B Page 56 of 105 MB9B400A Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Rating VCC AVCC AVRH Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VI VSS - 0.5 VIA VSS - 0.5 VO VSS - 0.5 Clamp maximum current ICLAMP -2 Clamp total maximum current Σ[ICLAMP] 1, 2 Power supply voltage* * 1, 3 Analog power supply voltage* * 1, 3 Analog reference voltage* * Input voltage* 1 Analog pin input voltage* Output voltage* 1 1 "L" level maximum output current* "L" level average output current* 4 5 "L" level total maximum output current 6 "L" level total average output current* "H" level maximum output current* "H" level average output current* 4 5 "H" level total maximum output current 6 "H" level total average output current* Power consumption Storage temperature IOL - IOLAV - ∑IOL ∑IOLAV - IOH - IOHAV - ∑IOH ∑IOHAV PD TSTG - 55 Max VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5V) AVCC + 0.5 (≤ 6.5V) VCC + 0.5 (≤ 6.5V) +2 Unit Remarks V V V V V V mA *7 +20 mA *7 10 20 39 4 12 19.7 100 50 - 10 - 20 - 39 -4 - 12 - 25.3 - 100 - 50 800 + 150 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW 4mA type 12mA type P80, P81 4mA type 12mA type P80, P81 4mA type 12mA type P80, P81 4mA type 12mA type P80, P81 C *1: These parameters are based on the condition that VSS = AVSS = 0.0V. *2: VCC must not drop below VSS - 0.5V. *3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is the peak value for a single pin. *5: The average output is the average current for a single pin over a period of 100 ms. *6: The total average output current is the average current for all pins over a period of 100 ms. Document Number: 002-05610 Rev.*B Page 57 of 105 MB9B400A Series *7: • • • • • See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin. Use within recommended operating conditions. Use at DC voltage (current) the +B input. The +B signal should always be applied a limiting resistance placed between the +B signal and the device. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices. • Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. • The following is a recommended circuit example (I/O equivalent circuit). Protection Diode VCC VCC Limiting resistor P-ch Digital output +B input (0V to 16V) N-ch Digital input R AVCC Analog input WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-05610 Rev.*B Page 58 of 105 MB9B400A Series 12.2 Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Symbol Conditions Value Unit Remarks Power supply voltage Analog power supply voltage Analog reference voltage VCC AVCC AVRH - Min 2 2.7* 2.7 2.7 Smoothing capacitor CS - 1 10 μF - 40 + 85 C TA When mounted on four-layer PCB When mounted on double-sided single-layer PCB - 40 + 85 C ICC  100mA - 40 + 70 C ICC > 100mA Operating Temperature LQM120 LQI100 LBC112 Max 5.5 5.5 AVCC V V V AVCC = VCC For built-in 1 regulator* *1: See "C Pin" in "7.Handling Devices" for the connection of the smoothing capacitor. *2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-05610 Rev.*B Page 59 of 105 MB9B400A Series 12.3 DC Characteristics 12.3.1 Current rating (VCC = AVCC =2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions PLL RUN mode RUN mode current ICC Typ* CPU : 80 MHz, Peripheral : 40 MHz, FLASH 2Wait FRWTR.RWT = 10 FSYNDN.SD = 000 CPU : 60 MHz, Peripheral : 30 MHz, FLASH 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU : 80 MHz, Peripheral : 40 MHz, FLASH 5Wait FRWTR.RWT = 10 FSYNDN.SD = 011 CPU : 60 MHz, Peripheral : 30 MHz, FLASH 3Wait FRWTR.RWT = 00 FSYNDN.SD = 011 Value 4 Max* 3 Unit Remarks 96 118 mA *1, *5 76 94 mA *1, *5 66 82 mA *1, *5 52 65 mA *1, *5 6.0 9.2 mA *1 0.2 2.24 mA *1, *6 0.3 2.36 mA *1 43 54 mA *1, *5 Peripheral : 4 MHz* 3.5 6.2 mA *1 Peripheral : 32 kHz 0.15 2.18 mA *1, *6 Peripheral : 100 kHz 0.22 2.27 mA *1 2 VCC High-speed CR RUN mode Sub RUN mode Low-speed CR RUN mode SLEEP mode current ICCS PLL SLEEP mode High-speed CR SLEEP mode Sub SLEEP mode Low-speed CR SLEEP mode CPU/Peripheral : 4 MHz* FLASH 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/Peripheral : 32 kHz FLASH 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/Peripheral : 100 kHz FLASH 0Wait FRWTR.RWT = 00 FSYNDN.SD = 000 Peripheral : 40 MHz 2 *1: When all ports are fixed. *2: When setting it to 4MHz by trimming. *3: TA = +25°C, VCC = 3.3V *4: TA = +85°C, VCC = 5.5V *5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) Document Number: 002-05610 Rev.*B Page 60 of 105 MB9B400A Series (VCC = A VCC =2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter TIMER mode current Pin name Symbol Main TIMER mode ICCT VCC STOP mode current ICCH Value Conditions Sub TIMER mode STOP mode Typ* TA = + 25C, When LVD is off TA = + 85C, When LVD is off 2 Max* 3 Unit Remarks 2.4 2.5 mA *1, *4 - 5.4 mA *1, *4 TA = + 25C, When LVD is off 110 300 μA *1, *5 TA = + 85C, When LVD is off - 2.2 mA *1, *5 TA = + 25C, When LVD is off 50 200 μA *1 TA = + 85C, When LVD is off - 2 mA *1 *1: When all ports are fixed. *2: VCC = 3.3V *3: VCC = 5.5V *4: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) Low-Voltage Detection Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Low-Voltage detection circuit (LVD) power supply current Symbol ICCLVD Pin name VCC Value Conditions At operation for interrupt Typ 2 Max Unit μA 10 Remarks At not detect Flash Memory Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Flash memory write/erase current Symbol ICCFLASH Pin name VCC Value Conditions At Write/Erase Typ 13 Max 24 Unit Remarks mA A/D Converter Current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C) Parameter Power supply current Reference power supply current Symbol ICCAD ICCAVRH Document Number: 002-05610 Rev.*B Pin name Value Conditions Typ Max Unit At 1unit operation 2.3 3.6 mA At stop 0.1 2 μA At 1unit operation AVRH=5.5V 2.2 3.0 mA At stop 0.03 0.6 μA Remarks AVCC AVRH Page 61 of 105 MB9B400A Series 12.3.2 Pin Characteristics (VCC = A VCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter "H" level input voltage (hysteresis input) "L" level input voltage (hysteresis input) "H" level output voltage Symbol Pin name Unit Max - VCC × 0.8 - VCC + 0.3 V VILS CMOS hysteresis input pin, MD0,1 - VSS - 0.3 - VCC × 0.2 V 4mA type VCC  4.5 V IOH = - 4mA VCC < 4.5 V IOH = - 2mA VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC - 0.4 - VCC V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V μA VOH 12mA type VOL 12mA type P80, P81 Input capacitance Min VIHS 4mA type Input leak current Pull-up resistance value Value Typ CMOS hysteresis input pin, MD0,1 P80, P81 "L" level output voltage Conditions IIL - RPU Pull-up pin CIN Other than VCC, VSS, AVCC, AVSS, AVRH Document Number: 002-05610 Rev.*B VCC  4.5 V IOH = - 12mA VCC  4.5 V IOH = - 8mA VCC  4.5 V IOH = - 25.3mA VCC < 4.5 V IOH = - 13.4mA VCC  4.5 V IOL = 4mA VCC < 4.5 V IOL = 2mA VCC  4.5 V IOL = 12mA VCC  4.5 V IOL = 8mA VCC  4.5 V IOL = 19.7mA VCC < 4.5 V IOL = 11.9mA - -5 - 5 VCC  4.5 V 25 50 100 VCC  4.5 V 30 80 200 - - 5 15 Remarks kΩ pF Page 62 of 105 MB9B400A Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Pin name Symbol VCC  4.5 V Input frequency Max Unit 48 20 4 48 4 20.83 20 250 50 250 45 55 % - - 5 ns VCC  4.5 V X0 X1 Min 4 4 VCC  4.5 V VCC  4.5 V FCH Value Conditions VCC  4.5 V VCC  4.5 V PWH/tCYLH PWL/tCYLH Remarks MHz When crystal oscillator is connected MHz When using external clock ns When using external clock Input clock cycle tCYLH Input clock pulse width - Input clock rise time and fall time tCF tCR FCM - - - 80 MHz FCC - - - 80 MHz FCP0 FCP1 FCP2 - - - 40 40 40 MHz MHz MHz tCYCC - - 12.5 - ns tCYCP0 tCYCP1 tCYCP2 - - 25 - ns APB0 bus clock* 2 - - 25 - ns APB1 bus clock* 2 - - 25 - ns APB2 bus clock* 2 Internal operating 1 clock* frequency Internal operating 1 clock* cycle time When using external clock When using external clock Master clock Base clock (HCLK/FCLK) 2 APB0 bus clock* 2 APB1 bus clock* 2 APB2 bus clock* Base clock (HCLK/FCLK) *1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family Peripheral Manual". *2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet. Document Number: 002-05610 Rev.*B Page 63 of 105 MB9B400A Series 12.4.2 Sub Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Input frequency Pin name Symbol Value Conditions Min Typ Unit Max - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs PWH/tCYLL PWL/tCYLL 45 - 55 % FCL Input clock cycle tCYLL Input clock pulse width - X0A X1A Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock 12.4.3 Built-in CR Oscillation Characteristics Built-in high-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol TA = + 25C Clock frequency FCRH Value Conditions TA = 0C to + 70C TA = - 40C to + 85C TA = - 40C to + 85C Min Typ Max 3.92 4 4.08 3.84 4 4.16 3.8 4 4.2 3 4 5 Unit Remarks 1 When trimming* MHz When not trimming Frequency stability 2 tCRWT 50 μs * time *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Clock frequency Symbol FCRL Document Number: 002-05610 Rev.*B Conditions - Value Min 50 Typ 100 Max 150 Unit Remarks kHz Page 64 of 105 MB9B400A Series 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Value Min Typ Unit Max PLL oscillation stabilization wait time (LOCK UP 1 time)* tLOCK 100 - - μs PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency 2 Main PLL clock frequency* fPLLI fPLLO FCLKPLL 4 4 60 - - 30 30 120 80 MHz multiple MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". 12.4.5 Operating Conditions of Main PLL (In the case of using built-in high speed CR) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Value Min Typ Unit Max PLL oscillation stabilization wait time (LOCK UP 1 time)* tLOCK 100 - - μs PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency 2 Main PLL clock frequency* fPLLI fPLLO FCLKPLL 3.8 15 57 - 4 - 4.2 28 120 80 MHz multiple MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family Peripheral Manual". Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed. Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock PLL macro oscillation clock Main PLL M divider Main PLL clock (CLKPLL) N divider Document Number: 002-05610 Rev.*B Page 65 of 105 MB9B400A Series 12.4.6 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Reset input time tINITX Pin name Conditions INITX - Value Min Max 500 - Unit Remarks ns 12.4.7 Power-on Reset Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Power supply rising time Tr Power supply shut down time Toff Time until releasing Power-on reset Tprt Value Pin name VCC Min Max Unit 0 - ms 1 - ms 0.422 0.704 ms Remarks VCC_minimum VCC VDH_minimum 0.2V 0.2V 0.2V Tr Tprt Internal RST RST Active CPU Operation Toff Release start Glossary: • VCC_minimum: • VDH_minimum: Minimum VCC of recommended operating conditions Minimum release voltage of Low-Voltage detection reset. See "12.6 Low-Voltage Detection Characteristics" Document Number: 002-05610 Rev.*B Page 66 of 105 MB9B400A Series 12.4.8 External Bus Timing Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name MOEX Min pulse width tOEW MOEX MOEX   Address delay time tOEL - AV MOEX MAD24 to 00 MOEX   Address delay time tOEH - AX MOEX MAD24 to 00 MOEX   MCSX  delay time tOEL - CSL MOEX MCSX MOEX   MCSX  delay time tOEH - CSH MOEX MCSX Data set up MOEX  time tDS - OE MOEX MDATA15 to 0 MOEX   Data hold time tDH - OE MOEX MDATA15 to 0 MCSX   MWEX  delay time tCSL - WEL MCSX MWEX MWEX   MCSX  delay time tWEH - CSH MCSX MWEX Address  MWEX  delay time tAV - WEL MWEX MAD24 to 00 MWEX   Address delay time tWEH - AX MWEX MAD24 to 00 MWEX   MDQM  delay time tWEL - DQML MWEX MDQM0 to 1 MWEX   MDQM  delay time tWEH - DQMH MWEX MDQM0 to 1 MWEX Min pulse width tWEW MWEX MWEX   Data delay time tWEL - DV MWEX MDATA15 to 0 MWEX   Data delay time tWEH - DX MWEX MDATA15 to 0 Value Conditions VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V Min Max Unit THCLK×1 - 3 - 0 0 0 0 10 20 10 20 0 10 ns 0 10 ns 20 38 - ns 0 - ns THCLK×1 - 5 THCLK×1 - 10 THCLK×1 - 5 THCLK×1 - 10 THCLK×1 - 5 THCLK×1 - 15 THCLK×1 - 5 THCLK×1 - 15 0 0 0 0 5 10 5 10 THCLK×1 - 3 - -5 -15 THCLK×1 - 5 THCLK×1 - 15 5 15 - Remarks ns ns ns ns ns ns ns ns ns ns ns ns Note: When the external load capacitance CL = 50pF. Document Number: 002-05610 Rev.*B Page 67 of 105 MB9B400A Series SRAM read tCYC HCLK VOH VOH tOEH-CSH tOEL-CSL MCSX0 to 7 VOH VOL tOEL-AV MAD24 to 00 tOEH-AX VOH VOL VOH VOL tOEW MOEX VOH VOL tDS-OE MDATA15 to 0 VIH VIL Document Number: 002-05610 Rev.*B Read tDH-OE VIH VIL Page 68 of 105 MB9B400A Series SRAM write tCYC HCLK tW EH-CSH tCSL-W EL MCSX0 to 7 VOH VOL tAV-W EL MAD24 to 00 tW EH-AX VOH VOL VOH VOL tW EH-DQMH tW EL-DQML MDQM0 to 1 VOH VOL tW EW MWEX VOL VOH tW EH-DX tW EL-DV MDATA15 to 0 VOH VOL Document Number: 002-05610 Rev.*B Write VOH VOL Page 69 of 105 MB9B400A Series NAND FLASH mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name MNREX Min pulse width tNREW MNREX Data set up  MNREX  tiime tDS - NRE MNREX MDATA15 to 0 MNREX   Data hold time tDH - NRE MNREX MDATA15 to 0 MNALE   MNWEX delay time tALEH - NWEL MNALE MNWEX MNWEX   MNALE delay time tNWEH - ALEL MNALE MNWEX MNCLE   MNWEX delay time tCLEH - NWEL MNCLE MNWEX MNWEX   MNCLE delay time tNWEH - CLEL MNCLE MNWEX MNWEX Min pulse width tNWEW MNWEX MNWEX   Data delay time tNWEL - DV MNWEX MDATA15 to 0 MNWEX   Data delay time tNWEH - DX MNWEX MDATA15 to 0 Conditions VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V Value Min Max THCLK×1 - 3 - 20 38 0 0 THCLK×1 - 5 THCLK×1 - 15 THCLK×1 - 5 THCLK×1 - 15 THCLK×1 - 5 THCLK×1 - 15 THCLK×1 - 5 THCLK×1 - 15 - THCLK×1 - 3 - -5 -15 THCLK×1 - 5 THCLK×1 - 15 +5 +15 - Unit Remarks ns ns ns ns ns ns ns ns ns ns Note: when the external load capacitance CL = 50pF. Document Number: 002-05610 Rev.*B Page 70 of 105 MB9B400A Series NAND FLASH read tCYC VOH HCLK VOH tNREW MNREX VOH VOL tDS-NRE VIH MDATA15 to 0 tDH-NRE VIH Read VIL VIL NAND FLASH write tCYC HCLK tNW EH-ALEL tALEH-NW EL VOH VOL MNALE tNW EH-CLEL tCLEH-NW EL VOH VOL MNCLE tNW EW MNWEX VOL VOH tNW EH-DX tNW EL-DV MDATA15 to 0 VOH VOL Document Number: 002-05610 Rev.*B Write VOH VOL Page 71 of 105 MB9B400A Series 12.4.9 Base Timer Input Timing Timer input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Input pulse width Symbol Pin name Conditions TIOAn/TIOBn (when using as ECK,TIN) tTIWH tTIWL - 2tCYCP tTIWH VIHS Value Min Max - Unit Remarks ns tTIWL VIHS VILS VILS Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Input pulse width Symbol Pin name Conditions TIOAn/TIOBn (when using as TGIN) tTRGH tTRGL - TGIN 2tCYCP Max - Unit Remarks ns tTRGL tTRGH VIHS Value Min VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data sheet. Document Number: 002-05610 Rev.*B Page 72 of 105 MB9B400A Series 12.4.10 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Serial clock cycle time tSCYC SCK   SOT delay time tSLOVI SIN  SCK  setup time tIVSHI SCK   SIN hold time tSHIXI Serial clock "L" pulse width tSLSH Serial clock "H" pulse width tSHSL SCK   SOT delay time tSLOVE SIN  SCK  setup time tIVSHE SCK   SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin name SCKx SCKx SOTx SCKx SINx SCKx SINx VCC  4.5V Min Max Conditions VCC ≥ 4.5V Min Max Unit 4tcycp - 4tcycp - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns SCKx 2tcycp - 10 - - ns SCKx tcycp + 10 - - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx Master mode 2tcycp 10 tcycp + 10 Slave mode Notes: • The above characteristics apply to CLK synchronous mode. • tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. • These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. • When the external load capacitance CL = 50pF. Document Number: 002-05610 Rev.*B Page 73 of 105 MB9B400A Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL Master mode tSLSH SCK VIH tF VIL tSHSL VIH VIL tR tSLOVE SOT SIN VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL Slave mode Document Number: 002-05610 Rev.*B Page 74 of 105 MB9B400A Series CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK   SOT delay time tSHOVI SIN  SCK  setup time tIVSLI SCK   SIN hold time tSLIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK   SOT delay time tSHOVE SIN  SCK  setup time tIVSLE SCK   SIN hold time tSLIXE SCK fall time SCK rise time tF tR SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx VCC  4.5V Min Max Conditions Master mode VCC ≥ 4.5V Min Max Unit 4tcycp - 4tcycp - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - 2tcycp 10 - ns - tcycp + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns 2tcycp 10 tcycp + 10 Slave mode Notes: • The above characteristics apply to CLK synchronous mode. • tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. • These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. • When the external load capacitance CL = 50pF. Document Number: 002-05610 Rev.*B Page 75 of 105 MB9B400A Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05610 Rev.*B Page 76 of 105 MB9B400A Series CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK   SOT delay time tSHOVI SIN  SCK  setup time tIVSLI SCK   SIN hold time tSLIXI SOT  SCK  delay time tSOVLI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK   SOT delay time tSHOVE SIN  SCK  setup time tIVSLE SCK   SIN hold time tSLIXE SCK fall time SCK rise time tF tR SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SOTx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx Conditions Master mode VCC  4.5V Min Max 4tcycp - VCC ≥ 4.5V Min Max 4tcycp - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tcycp 30 2tcycp 10 tcycp + 10 - 2tcycp 30 2tcycp 10 Unit - tcycp + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Slave mode Notes: • The above characteristics apply to CLK synchronous mode. • tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. • These characteristics only guarantees the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. • When the external load capacitance CL = 50pF. Document Number: 002-05610 Rev.*B Page 77 of 105 MB9B400A Series tSCYC VOH VOL SCK VOH VOL SOT VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH SCK VIH tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN VIH VIL tF * SOT VIL tSHSL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register Document Number: 002-05610 Rev.*B Page 78 of 105 MB9B400A Series CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name VCC  4.5V Min Max Conditions VCC ≥ 4.5V Min Max Unit Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns SCK   SOT delay time tSLOVI SCKx SOTx -30 +30 - 20 + 20 ns SIN  SCK  setup time tIVSHI 50 - 30 - ns SCK  SIN hold time tSHIXI 0 - 0 - ns SOT  SCK  delay time tSOVHI - ns Serial clock "L" pulse width tSLSH SCKx - ns Serial clock "H" pulse width tSHSL SCKx SCK   SOT delay time tSLOVE SIN  SCK  setup time tIVSHE SCK   SIN hold time tSHIXE SCK fall time SCK rise time tF tR SCKx SINx SCKx SINx SCKx SOTx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx Master mode 2tcycp 30 2tcycp 10 tcycp + 10 - 2tcycp 30 2tcycp 10 - tcycp + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Slave mode Notes: • The above characteristics apply to CLK synchronous mode. • tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. • These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. • When the external load capacitance CL = 50pF. Document Number: 002-05610 Rev.*B Page 79 of 105 MB9B400A Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI SIN VOH VOL VIH VIL VIH VIL Master mode tSLSH tSHSL tR SCK VIL VIH VIH tF tSHIXE t IVSHE VIH VIL VIH VIL SIN VIH t SLOVE VOH VOL VOH VOL SOT VIL VIL Slave mode UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Serial clock "L" pulse width Serial clock "H" pulse width SCK fall time SCK rise time Symbol tSLSH tSHSL tF tR Conditions V IL Document Number: 002-05610 Rev.*B Max tcycp + 10 tcycp + 10 - CL = 50pF 5 5 Unit Remarks ns ns ns ns tF tR SCK Min tSHSL V IH tSLSH V IH V IL V IL V IH Page 80 of 105 MB9B400A Series 12.4.11 External input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Value Min Conditions Max Unit ADTG FRCKx Input pulse width tINH tINL ICxx DTTIxX INTxx, NMIX - 2tCYCP * - ns Except Timer mode, Stop mode Timer mode, Stop mode 2tCYCP * - ns 2tCYCP + 100 * - ns 500 - ns Remarks A/D converter trigger input Free-run timer input clock Input capture Wave form generator External interrupt NMI *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "Block Diagram" in this data sheet. tINH VILS Document Number: 002-05610 Rev.*B tINL VILS VIHS VIHS Page 81 of 105 MB9B400A Series 12.4.12 Quadrature Position/Revolution Counter timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol AIN pin "H" width AIN pin "L" width BIN pin "H" width BIN pin "L" width BIN rise time from AIN pin "H" level AIN fall time from BIN pin "H" level BIN fall time from AIN pin "L" level AIN rise time from BIN pin "L" level AIN rise time from BIN pin "H" level BIN fall time from AIN pin "H" level AIN fall time from BIN pin "L" level BIN rise time from AIN pin "L" level ZIN pin "H" width ZIN pin "L" width AIN/BIN rise and fall time from determined ZIN level Determined ZIN level from AIN/BIN rise and fall time Value Conditions Min tAHL tALL tBHL tBLL - tAUBU PC_Mode2 or PC_Mode3 tBUAD PC_Mode2 or PC_Mode3 tADBD PC_Mode2 or PC_Mode3 tBDAU PC_Mode2 or PC_Mode3 tBUAU PC_Mode2 or PC_Mode3 tAUBD PC_Mode2 or PC_Mode3 tBDAD PC_Mode2 or PC_Mode3 tADBU PC_Mode2 or PC_Mode3 tZHL tZLL QCR:CGSC="0" QCR:CGSC="0" tZABE QCR:CGSC="1" tABEZ QCR:CGSC="1" 2tCYCP * Max - Unit ns *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block Diagram" in this data sheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 002-05610 Rev.*B tBLL Page 82 of 105 MB9B400A Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN Document Number: 002-05610 Rev.*B Page 83 of 105 MB9B400A Series 2 12.4.13 I C timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter SCL clock frequency (Repeated) START condition hold time SDA   SCL  SCLclock "L" width SCLclock "H" width (Repeated) START setup time SCL   SDA  Data hold time SCL   SDA   Data setup time SDA    SCL  STOP condition setup time SCL   SDA  Bus free time between "STOP condition" and "START condition" Noise filter FSCL Standard-mode Min Max 0 100 Fast-mode Min Max 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs tSUSTA 4.7 - 0.6 - μs 0 3.45* 0 0.9* μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs - 2 tCYCP* - ns Symbol tHDDAT tSP Conditions CL = 50pF, 1 R = (Vp/IOL)* 4 - 2 tCYCP* 2 3 4 Unit Remarks *1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (t LOW) of device's SCL signal. 2 2 *3 : Fast-mode I C bus device can be used on Standard-mode I C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4 : tCYCP is the APB bus clock cycle time. 2 About the APB bus number that I C is connected to, see "Block Diagram" in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: 002-05610 Rev.*B Page 84 of 105 MB9B400A Series 12.4.14 ETM timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Data hold tETMH TRACECLK Frequency 1/tTRACE Pin name TRACECLK TRACED3 - 0 TRACECLK TRACECLK clock cycle time VCC ≥ 4.5 V Value Min Max 2 9 VCC  4.5 V 2 15 VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 31.25 - ns Conditions Unit Remarks ns tTRACE Note: When the external load capacitance CL = 50pF. HCLK TRACECLK TRACED[3:0] Document Number: 002-05610 Rev.*B Page 85 of 105 MB9B400A Series 12.4.15 JTAG timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name TMS,TDI setup time tJTAGS TCK TMS,TDI TMS,TDI hold time tJTAGH TCK TMS,TDI TDO delay time tJTAGD TCK TDO Conditions VCC ≥ 4.5 V Min Value Max Unit 15 - ns VCC  4.5 V 15 - ns VCC ≥ 4.5 V - 25 VCC  4.5 V - 45 VCC  4.5 V VCC ≥ 4.5 V Remarks ns Note: When the external load capacitance CL = 50pF. TCK TMS/TDI TDO Document Number: 002-05610 Rev.*B Page 86 of 105 MB9B400A Series 12.5 12bit A/D Converter Electrical characteristics for the A/D converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Pin name Symbol Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage Full-scale transition voltage VZT VFST ANxx ANxx Conversion time - - Sampling time Ts - Compare clock cycle *3 Tcck - State transition time to operation permission Tstt - Analog input capacity CAIN Analog input resistance Interchannel disparity Analog port input current Analog input voltage Reference voltage Value Typ Min 1 1.0* 1 2.666* *2 *2 55.5 Max Unit ±2 ±2 ±5 AVRH ± 10 - 12 ± 4.5 ± 2.5 ± 20 AVRH ± 20 - bit LSB LSB mV mV - 10000 ns - - 2.5 μs - - - 14.5 pF RAIN - - - - ANxx ANxx AVRH AVSS 2.7 - 166.6* 4 0.93 2.04 4 5 AVRH AVCC μs ns kΩ Remarks AVRH = 2.7V to 5.5V AVCC ≥ 4.5V AVCC < 4.5V AVCC ≥ 4.5V AVCC < 4.5V AVCC ≥ 4.5V AVCC < 4.5V AVCC ≥ 4.5V AVCC < 4.5V LSB μA V V *1: The Conversion time is the value of sampling time(Ts) + compare time(Tc). The condition of the minimum conversion time is the following. AVCC ≥ 4.5V, HCLK=72MHz sampling time: 0.222μs compare time: 0.778μs AVCC < 4.5V, HCLK=54MHz sampling time: 0.333μs compare time: 2.333μs Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family Peripheral Manual Analog Macro Part". The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1) *3: The Compare time (Tc) is the value of (Equation 2) *4: When 12bit A/D converter is used at AVCC