MB9BF566KQN-G-AVE2

The following document contains information on Cypress products. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. 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Other names used are for informational purposes only and may be trademarks of their respective owners. FUJITSU SEMICONDUCTOR DATA SHEET DS709-00005-1v0-E 610-PRE20110422E 32-bit ARMTM CortexTM-M4F based Microcontroller MB9B560L Series MB9BF564K/L, MB9BF565K/L, MB9BF566K/L  DESCRIPTION The MB9B560L Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN). Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries. Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.12 FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0 MB9B560L Series  FEATURES  32-bit ARM Cortex-M4F Core ・ Processor version: r0p1 ・ Up to 160 MHz Frequency Operation ・ FPU built-in ・ Support DSP instruction ・ Memory Protection Unit (MPU): improves the reliability of an embedded system ・ Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels ・ 24-bit System timer (Sys Tick): System timer for OS task management  On-chip Memories [Flash memory] These series are based on two independent on-chip Flash memories. ・ MainFlash memory ・ Up to 512 Kbytes ・ Built-in Flash Accelerator System with 16 Kbytes trace buffer memory ・ The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. ・ Security function for code protection ・ WorkFlash memory ・ 32 Kbytes ・ Read cycle: ・6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz ・4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz ・2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz ・0wait-cycle: the operation frequency up to 40MHz ・ Security function is shared with code protection [SRAM] This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. ・ SRAM0: Up to 32 Kbytes ・ SRAM1: Up to 16 Kbytes ・ SRAM2: Up to 16 Kbytes 2 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  USB Interface USB interface is composed of Function and Host. [USB function] ・ USB2.0 Full-Speed supported ・ Max 6 EndPoint supported ・ EndPoint 0 is control transfer ・ EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer ・ EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer ・ EndPoint 1 to 5 comprise Double Buffer ・ The size of each endpoint is according to the follows. - Endpoint 0, 2 to 5 : 64bytes - Endpoint 1 : 256bytes [USB host] ・ USB2.0 Full/Low-speed supported ・ Bulk-transfer, interrupt-transfer and Isochronous-transfer support ・ USB Device connected/dis-connected automatically detect ・ IN/OUT token handshake packet automatically ・ Max 256-byte packet-length supported ・ Wake-up function supported  CAN Interface (Max 1 channels) ・ Compatible with CAN Specification 2.0A/B ・ Maximum transfer rate: 1 Mbps ・ Built-in 32 message buffer  Multi-function Serial Interface (Max 6 channels) ・ 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.) ・ Operation mode is selectable from the followings for each channel. ・ UART ・ CSIO ・ LIN ・ I2 C [UART] ・ Full-duplex double buffer ・ Selection with or without parity supported ・ Built-in dedicated baud rate generator ・ External clock available as a serial clock ・ Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) ・ Various error detect functions available (parity errors, framing errors, and overrun errors) [CSIO] ・ Full-duplex double buffer ・ Built-in dedicated baud rate generator ・ Overrun error detect function available ・ Serial chip select function (ch.6 only) ・ Supports high-speed SPI (ch.0 and ch.6 only) ・ Data length 5 to 16-bit [LIN] ・ LIN protocol Rev.2.1 supported ・ Full-duplex double buffer ・ Master/Slave mode supported ・ LIN break field generation (can change to 13 to 16-bit length) ・ LIN break delimiter generation (can change to 1 to 4-bit length) ・ Various error detect functions available (parity errors, framing errors, and overrun errors) DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 3 r1.0 MB9B560L Series 2 [I C] ・ Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported ・ Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.4=ch.B) supported  DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously. ・ 8 independently configured and operated channels ・ Transfer can be started by software or request from the built-in peripherals ・ Transfer address area: 32-bit (4 Gbytes) ・ Transfer mode: Block transfer/Burst transfer/Demand transfer ・ Transfer data type: bytes/half-word/word ・ Transfer block count: 1 to 16 ・ Number of transfers: 1 to 65536  DSTC (Descriptor System data Transfer Controller) (128 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation and the chain activation functions.  A/D Converter (Max 15 channels) [12-bit A/D Converter] ・ Successive Approximation type ・ Built-in 2 units ・ Conversion time: 0.5μs @ 5V ・ Priority conversion available (priority at 2levels) ・ Scanning conversion mode ・ Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)  DA converter (Max 2 channels) ・ R-2R type ・ 12-bit resolution  Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel. ・ 16-bit PWM timer ・ 16-bit PPG timer ・ 16/32-bit reload timer ・ 16/32-bit PWC timer  General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. ・ Capable of pull-up control per pin ・ Capable of reading pin level directly ・ Built-in the port relocate function ・ Up to 48 high-speed general-purpose I/O ports @ 64pin Package ・ Some pin is 5V tolerant I/O. See "PIN DESCRIPTION" and "I/O CIRCUIT TYPE" for the corresponding pins. 4 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  Multi-function Timer (Max 2 units) The Multi-function timer is composed of the following blocks. Minimum resolution : 6.25 ns ・ 16-bit free-run timer × 3ch./unit ・ Input capture × 4ch./unit ・ Output compare × 6ch./unit ・ A/D activation compare × 6ch./unit ・ Waveform generator × 3ch./unit ・ 16-bit PPG timer × 3ch./unit The following function can be used to achieve the motor control. ・ PWM signal output function ・ DC chopper waveform output function ・ Dead time function ・ Input capture function ・ A/D convertor activate function ・ DTIF (Motor emergency stop) interrupt function  Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99. ・ Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. ・ Timer interrupt function after set time or each set time. ・ Capable of rewriting the time with continuing the time count. ・ Leap year automatic count is available.  Quadrature Position/Revolution Counter (QPRC) (Max 1 channel) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter. ・ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. ・ 16-bit position counter ・ 16-bit revolution counter ・ Two 16-bit compare registers  Dual Timer (32/16-bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each channel. ・ Free-running ・ Periodic (=Reload) ・ One-shot  Watch Counter The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 5 r1.0 MB9B560L Series  External Interrupt Controller Unit ・ External interrupt input pin: Max 16 pins ・ Include one non-maskable interrupt (NMI)  Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware" watchdog is active in any power saving mode except STOP.  CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported. ・ CCITT CRC16 Generator Polynomial: 0x1021 ・ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7  Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable. ・ Main clock ・ Sub Clock ・ High-speed internal CR Clock ・ Low-speed internal CR Clock ・ Main PLL Clock : 4 MHz to 48 MHz : 32.768 kHz : 4 MHz : 100 kHz [Resets] ・ Reset requests from INITX pin ・ Power on reset ・ Software reset ・ Watchdog timers reset ・ Low voltage detector reset ・ Clock supervisor reset  Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. ・ External OSC clock failure (clock stop) is detected, reset is asserted. ・ External OSC frequency anomaly is detected, interrupt or reset is asserted.  Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. ・ LVD1: error reporting via interrupt ・ LVD2: auto-reset operation 6 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  Low-power Consumption Mode Six low-power consumption modes are supported. ・ SLEEP ・ TIMER ・ RTC ・ STOP ・ Deep standby RTC (selectable from with/without RAM retention) ・ Deep standby stop (selectable from with/without RAM retention)  VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used. ・ RTC ・ 32 kHz oscillation circuit ・ Power-on circuit ・ Back up register : 32 bytes ・ Port circuit  Debug Serial Wire JTAG Debug Port (SWJ-DP)  Unique ID Unique value of the device (41-bit) is set.  Power Supply Three Power Supplies ・Wide range voltage : VCC = 2.7V to 5.5V ・Power supply for USB I/O : USBVCC = 3.0V to 3.6V (when USB is used) = 2.7V to 5.5V (when GPIO is used) ・Power supply for VBAT : VBAT = 2.7V to 5.5V DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 7 r1.0 MB9B560L Series  PRODUCT LINEUP  Memory size Product name MB9BF564K/L MB9BF565K/L MB9BF566K/L MainFlash memory WorkFlash memory On-chip SRAM SRAM0 SRAM1 SRAM2 256 Kbytes 32 Kbytes 32 Kbytes 16 Kbytes 8 Kbytes 8 Kbytes 384 Kbytes 32 Kbytes 48 Kbytes 24 Kbytes 12 Kbytes 12 Kbytes 512 Kbytes 32 Kbytes 64 Kbytes 32 Kbytes 16 Kbytes 16 Kbytes 8 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  Function MB9BF564K MB9BF565K MB9BF566K Product name Pin count 48 64 Cortex-M4F, MPU, NVIC 128ch. 160 MHz 2.7V to 5.5V 1ch. 1ch. 8ch. 128ch. 6ch. (Max) (In ch.1, only I2C is 6ch. (Max) available.) CPU Freq. Power supply voltage range USB2.0 (Function/Host) CAN DMAC DSTC Multi-function Serial Interface (UART/CSIO/LIN/I2C) MF Timer Base Timer (PWC/Reload timer/PWM/PPG) A/D activation compare Input capture Free-run timer Output compare Waveform generator PPG QPRC Dual Timer Real-Time Clock Watch Counter CRC Accelerator Watchdog Timer External Interrupts I/O Ports 12-bit A/D Converter MB9BF564L MB9BF565L MB9BF566L 8ch. (Max) 6ch. 4ch. 3ch. 6ch. 3ch. 3ch. 1 unit 2 units (Max) 1ch. 1 unit 1 unit 1 unit Yes 1ch. (SW) + 1ch. (HW) 15pins (Max) + NMI × 1 16pins (Max) + NMI × 1 33pins (Max) 48pins (Max) 8ch. (2 units) 15ch. (2 units) 12-bit D/A Converter 2 units (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. High-speed 4 MHz (±2%) Built-in CR Low-speed 100 kHz (Typ) Debug Function SWJ-DP Unique ID Yes Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 9 r1.0 MB9B560L Series  PACKAGES Product name Package LQFP: FPT-64P-M39 (0.65mm pitch) LQFP: FPT-64P-M38 (0.5mm pitch) LQFP: FPT-48P-M49 (0.5mm pitch) QFN: LCC-64P-M24 (0.5mm pitch) QFN: LCC-48P-M73 (0.5mm pitch) MB9BF564K MB9BF565K MB9BF566K - -  -  MB9BF564L MB9BF565L MB9BF566L    - : Supported Note : See "PACKAGE DIMENSIONS" for detailed information on each package. 10 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  PIN ASSIGNMENT  FPT-64P-M38/M39 VCC VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1 P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4 P64/AN11/SOT0_1/TIOB2_1/INT12_1 P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0 P66/AN09/INT10_1/IC13_0/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) 1 48 P26/AN08/SIN1_0/INT09_1/IC12_0 P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 2 47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0 P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 3 46 P24/AN06/SCK1_0/INT07_1/IC10_0 P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 4 45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0 P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 5 44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0 43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0 42 AVRH 41 AVRL P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 6 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 7 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 8 P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 9 40 AVSS P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10 39 AVCC P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13 36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14 35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15 34 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP INITX C VSS VCC P40/TIOA7_0/INT14_0 P41/TIOB7_0/INT15_0/ADTG_1/WKUP3 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 64 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 11 r5.0 MB9B560L Series  LCC-64P-M24 VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1 P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4 P64/AN11/SOT0_1/TIOB2_1/INT12_1 P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0 P66/AN09/INT10_1/IC13_0/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P26/AN08/SIN1_0/INT09_1/IC12_0 P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 2 47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0 3 46 P24/AN06/SCK1_0/INT07_1/IC10_0 P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 4 45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0 P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 5 44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0 P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 6 43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 7 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 8 42 AVRH QFN - 64 41 AVRL 24 25 26 27 28 29 30 31 32 VCC P40/TIOA7_0/INT14_0 P41/TIOB7_0/INT15_0/ADTG_1/WKUP3 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS 33 VCC VSS 16 23 34 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1 VSS C 15 22 35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 INITX 14 21 36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 P49/VWAKEUP 13 20 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 P48/VREGCTL 12 19 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 VBAT 11 18 39 AVCC P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 17 40 AVSS 10 P47/X1A 9 P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 P46/X0A P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 12 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r5.0 MB9B560L Series  FPT-48P-M49 VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P66/AN09/INT10_1/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P23/AN05/SCK0_0/TIOB1_1/INT06_1 P54/IC02_0/INT04_0/TIOA2_0 2 35 P22/AN04/SOT0_0/TIOA1_1/INT05_1 34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 3 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 4 33 AVRH P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 5 32 AVRL P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 6 P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 7 31 AVSS P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 8 29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 9 28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1 VSS 12 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1 LQFP - 48 13 14 15 16 17 18 19 20 21 22 23 24 P46/X0A P47/X1A VBAT INITX C VSS VCC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS 30 AVCC The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 13 r5.0 MB9B560L Series  LCC-48P-M73 VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P66/AN09/INT10_1/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P23/AN05/SCK0_0/TIOB1_1/INT06_1 P54/IC02_0/INT04_0/TIOA2_0 2 35 P22/AN04/SOT0_0/TIOA1_1/INT05_1 34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 3 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 4 33 AVRH P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 5 32 AVRL P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 6 P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 7 31 AVSS P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 8 29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1 28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1 QFN - 48 30 AVCC 16 17 18 19 20 21 22 23 24 C VSS VCC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1 INITX 12 15 VSS VBAT 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1 14 11 13 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 P47/X1A 9 10 P46/X0A P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 14 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r5.0 MB9B560L Series  PIN DESCRIPTION  List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP64 QFN64 1 LQFP48 QFN48 1 2 - 3 - 4 - 5 - 2 6 - 7 3 8 4 Pin Name VCC P50 AIN0_0 INT00_0 TIOA0_0 CTS4_0 P51 BIN0_0 INT01_0 TIOB0_0 RTS4_0 P52 IC00_0 ZIN0_0 INT02_0 TIOA1_0 SIN4_0 P53 IC01_0 INT03_0 TIOB1_0 SOT4_0 (SDA4_0) P54 IC02_0 INT04_0 TIOA2_0 SCK4_0 (SCL4_0) P55 IC03_0 INT05_0 TIOB2_0 SIN3_0 P56 FRCK0_0 INT06_0 TIOA3_0 SOT3_0 (SDA3_0) DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit type Pin state type - - E K E K I K N K N K I K N K 15 r5.0 MB9B560L Series Pin No LQFP64 QFN64 LQFP48 QFN48 9 5 10 6 11 7 12 8 13 9 14 10 15 11 Pin Name P57 DTTI0X_0 INT07_0 TIOB3_0 SCK3_0 (SCL3_0) ADTG_0 P30 RTO00_0 AIN0_1 INT08_0 TIOA4_0 SIN2_0 P31 RTO01_0 BIN0_1 INT09_0 TIOB4_0 SOT2_0 (SDA2_0) P32 RTO02_0 ZIN0_1 INT10_0 TIOA5_0 SCK2_0 (SCL2_0) P33 RTO03_0 INT11_0 TIOB5_0 SIN4_1 P34 RTO04_0 INT12_0 TIOA6_0 SOT4_1 (SDA4_1) P35 WKUP2 RTO05_0 INT13_0 TIOB6_0 SCK4_1 (SCL4_1) 16 FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit type Pin state type N K G K G K G K G K G K G Q DS709-00005-1v0-E r5.0 MB9B560L Series Pin No LQFP64 QFN64 16 LQFP48 QFN48 12 17 13 18 14 19 15 20 - 21 - 22 23 24 25 16 17 18 19 26 - 27 - 28 20 29 21 30 22 31 23 32 33 24 - 34 25 - 35 26 - Pin Name VSS P46 X0A P47 X1A VBAT P48 VREGCTL P49 VWAKEUP INITX C VSS VCC P40 TIOA7_0 INT14_0 P41 TIOB7_0 INT15_0 ADTG_1 WKUP3 PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 DA0 TIOA4_1 INT00_1 AIN0_2 IC03_1 RTO10_0 P11 DA1 ADTG_2 SCS6_0 TIOB4_1 INT01_1 BIN0_2 IC02_1 RTO11_0 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit type Pin state type - - P S Q T O U O U B - C - E K E Q C E J D A A A B - - R J R J 17 r5.0 MB9B560L Series Pin No LQFP64 QFN64 36 LQFP48 QFN48 27 - 37 28 - 38 39 40 41 42 43 29 30 31 32 33 34 - 44 35 - 45 36 - Pin Name P12 AN00 SCK6_0 TIOA7_1 INT02_1 ZIN0_2 IC01_1 RX0_1 RTO12_0 P13 AN01 SOT6_0 (SDA6_0) TIOB7_1 IC00_1 TX0_1 RTO13_0 P20 AN02 SIN6_0 TIOA0_1 INT03_1 RTCCO_1 SUBOUT_1 WKUP1 RTO14_0 AVCC AVSS AVRL AVRH P21 AN03 ADTG_3 SIN0_0 TIOB0_1 INT04_1 RTO15_0 P22 AN04 SOT0_0 (SDA0_0) TIOA1_1 INT05_1 FRCK1_0 P23 AN05 SCK0_0 (SCL0_0) TIOB1_1 INT06_1 DTTI1X_0 18 FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit type Pin state type M M M L F O - - F M F M F M DS709-00005-1v0-E r5.0 MB9B560L Series Pin No LQFP64 QFN64 LQFP48 QFN48 46 - 47 - 48 - 49 37 50 38 51 39 52 40 53 41 54 42 - 55 - 56 - Pin Name P24 AN06 SCK1_0 (SCL1_0) INT07_1 IC10_0 P25 AN07 SOT1_0 (SDA1_0) INT08_1 IC11_0 CROUT_0 P26 AN08 SIN1_0 INT09_1 IC12_0 P04 TDO SWO P03 TMS SWDIO P02 TDI P01 TCK SWCLK P00 TRSTX P66 AN09 INT10_1 CROUT_1 IC13_0 P65 AN10 SCK0_1 (SCL0_1) TIOA2_1 INT11_1 RTCCO_0 SUBOUT_0 P64 AN11 SOT0_1 (SDA0_1) TIOB2_1 INT12_1 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit type Pin state type F M F M F M E G E G E G E G E G F M L M L M 19 r5.0 MB9B560L Series Pin No LQFP64 QFN64 LQFP48 QFN48 57 - 58 - 59 43 60 44 61 45 62 46 63 47 64 48 Pin Name P63 AN12 SIN0_1 TX0_0 TIOA3_1 INT13_1 ADTG_4 P62 AN13 SIN1_1 RX0_0 TIOB3_1 INT14_1 P61 AN14 ADTG_5 SOT1_1 (SDA1_1) INT15_1 UHCONX0 IC00_2 P60 SCK1_1 (SCK1_1) NMIX WKUP0 IC01_2 USBVCC P80 UDM0 P81 UDP0 VSS 20 FUJITSU SEMICONDUCTOR CONFIDENTIAL I/O circuit type Pin state type F M F M F M I F - - H R H R - - DS709-00005-1v0-E r5.0 MB9B560L Series  List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Pin name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 TIOA0_0 TIOA0_1 TIOB0_0 TIOB0_1 TIOA1_0 TIOA1_1 TIOB1_0 TIOB1_1 TIOA2_0 TIOA2_1 TIOB2_0 TIOB2_1 TIOA3_0 TIOA3_1 TIOB3_0 TIOB3_1 TIOA4_0 TIOA4_1 TIOB4_0 TIOB4_1 TIOA5_0 TIOB5_0 Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin No LQFP64 QFN64 LQFP48 QFN48 9 27 35 43 57 59 36 37 38 43 44 45 46 47 48 54 55 56 57 58 59 2 38 3 43 4 44 5 45 6 55 7 56 8 57 9 58 10 34 11 35 12 13 5 26 34 43 27 28 29 34 35 36 42 43 29 34 35 36 2 3 4 5 6 25 7 26 8 9 21 r5.0 MB9B560L Series Pin function Base Timer 6 Base Timer 7 CAN 0 Debugger External Interrupt Pin name TIOA6_0 TIOB6_0 TIOA7_0 TIOA7_1 TIOB7_0 TIOB7_1 TX0_0 TX0_1 RX0_0 RX0_1 SWCLK SWDIO SWO TCK TDI TDO TMS TRSTX INT00_0 INT00_1 INT01_0 INT01_1 INT02_0 INT02_1 INT03_0 INT03_1 INT04_0 INT04_1 INT05_0 INT05_1 Pin No Function description Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin CAN interface ch.0 TX output pin CAN interface ch.0 RX output pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin J-TAG test clock input pin J-TAG test data input pin J-TAG debug data output pin J-TAG test mode state input/output pin J-TAG test reset Input pin External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin 22 FUJITSU SEMICONDUCTOR CONFIDENTIAL LQFP64 QFN64 LQFP48 QFN48 14 15 26 36 27 37 57 37 58 36 52 50 49 52 51 49 50 53 2 34 3 35 4 36 5 38 6 43 7 44 10 11 27 28 28 27 40 38 37 40 39 37 38 41 25 26 27 29 2 34 3 35 DS709-00005-1v0-E r5.0 MB9B560L Series Pin function External Interrupt GPIO Pin name INT06_0 INT06_1 INT07_0 INT07_1 INT08_0 INT08_1 INT09_0 INT09_1 INT10_0 INT10_1 INT11_0 INT11_1 INT12_0 INT12_1 INT13_0 INT13_1 INT14_0 INT14_1 INT15_0 INT15_1 NMIX P00 P01 P02 P03 P04 P10 P11 P12 P13 P20 P21 P22 P23 P24 P25 P26 P30 P31 P32 P33 P34 P35 Pin No Function description External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 General-purpose I/O port 3 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL LQFP64 QFN64 LQFP48 QFN48 8 45 9 46 10 47 11 48 12 54 13 55 14 56 15 57 26 58 27 59 60 53 52 51 50 49 34 35 36 37 38 43 44 45 46 47 48 10 11 12 13 14 15 4 36 5 6 7 8 42 9 10 11 43 44 41 40 39 38 37 25 26 27 28 29 34 35 36 6 7 8 9 10 11 23 r5.0 MB9B560L Series Pin function Pin name GPIO P40 P41 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P80 P81 PE0 PE2 PE3 Pin No Function description General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E 24 FUJITSU SEMICONDUCTOR CONFIDENTIAL LQFP64 QFN64 LQFP48 QFN48 26 27 17 18 20 21 2 3 4 5 6 7 8 9 60 59 58 57 56 55 54 62 63 28 30 31 13 14 2 3 4 5 44 43 42 46 47 20 22 23 DS709-00005-1v0-E r5.0 MB9B560L Series Pin function Multifunction Serial 0 Multifunction Serial 1 Multifunction Serial 2 Pin name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) SIN2_0 SOT2_0 (SDA2_0) SCK2_0 (SCL2_0) Pin No Function description Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation modes 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 input pin Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL LQFP64 QFN64 LQFP48 QFN48 43 57 34 - 44 35 56 - 45 36 55 - 48 58 - 47 - 59 43 46 - 60 44 10 6 11 7 12 8 25 r5.0 MB9B560L Series Pin function Multifunction Serial 3 Multifunction Serial 4 Multifunction Serial 6 Pin No Pin name Function description LQFP64 QFN64 LQFP48 QFN48 SIN3_0 Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). 7 3 8 4 9 5 4 13 9 5 - 14 10 6 - 15 11 2 3 38 29 37 28 36 27 35 26 SOT3_0 (SDA3_0) SCK3_0 (SCL3_0) SIN4_0 SIN4_1 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) CTS4_0 RTS4_0 SIN6_0 SOT6_0 (SDA6_0) SCK6_0 (SCL6_0) SCS6_0 Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 CTS input pin Multi-function serial interface ch.4 RTS output pin Multi-function serial interface ch.6 input pin This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 serial chip select pin 26 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r5.0 MB9B560L Series Pin function Pin name DTTI0X_0 FRCK0_0 IC00_0 IC00_1 IC00_2 IC01_0 IC01_1 IC01_2 IC02_0 IC02_1 IC03_0 IC03_1 Multifunction Timer 0 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) Pin No Function description Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 16-bit input capture ch.0 input pin of Multi-function timer 0. ICxx describes channel number. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL LQFP64 QFN64 LQFP48 QFN48 9 5 8 4 37 59 5 36 60 6 35 7 34 4 28 43 27 44 2 26 3 25 10 6 11 7 12 8 13 9 14 10 15 11 27 r5.0 MB9B560L Series Pin function Pin name DTTI1X_0 FRCK1_0 IC10_0 IC11_0 IC12_0 IC13_0 RTO10_0 (PPG10_0) Multifunction Timer 1 RTO11_0 (PPG10_0) RTO12_0 (PPG12_0) RTO13_0 (PPG12_0) RTO14_0 (PPG14_0) RTO15_0 (PPG14_0) Quadrature Position/ Revolution Counter 0 AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 Pin No Function description Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 16-bit free-run timer ch.1 external clock input pin 16-bit input capture ch.1 input pin of Multi-function timer 1. ICxx describes channel number. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin 28 FUJITSU SEMICONDUCTOR CONFIDENTIAL LQFP64 QFN64 LQFP48 QFN48 45 - 44 46 47 48 54 - 34 - 35 - 36 - 37 - 38 - 43 - 2 10 34 3 11 35 4 12 36 6 25 7 26 8 36 DS709-00005-1v0-E r5.0 MB9B560L Series Pin function Real-time clock USB Low-Power Consumpti on Mode DAC VBAT RESET RTCCO_0 RTCCO_1 SUBOUT_0 SUBOUT_1 UDM0 UDP0 UHCONX0 WKUP0 WKUP1 WKUP2 WKUP3 DA0 DA1 VREGCTL VWAKEUP INITX MD1 MODE MD0 POWER VCC USBVCC GND VSS CLOCK X0 X1 X0A X1A CROUT_0 CROUT_1 Analog POWER VBAT POWER Analog GND C pin Pin No Pin name AVCC AVRH VBAT AVSS AVRL C Function description 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Sub clock output pin USB function/host D – pin USB function/host D + pin USB external pull-up control pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 D/A converter ch.0 analog output pin D/A converter ch.1 analog output pin On-board regulator control pin The return signal input pin from a hibernation state External Reset Input pin. A reset is valid when INITX="L". Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Power supply Pin 3.3V Power supply port for USB I/O GND Pin Main clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) input pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin VBAT power supply pin. Backup power supply (battery etc.) and system power supply. A/D converter and D/A converter GND pin A/D converter analog reference voltage input pin Power supply stabilization capacity pin DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL LQFP64 QFN64 LQFP48 QFN48 55 38 55 38 62 63 59 60 38 15 27 34 35 20 21 29 29 46 47 43 44 29 11 25 26 - 22 16 28 20 29 21 1 25 33 61 16 24 32 64 30 31 17 18 47 54 1 19 45 12 18 24 48 22 23 13 14 42 39 30 42 33 19 15 40 31 41 23 32 17 29 r5.0 MB9B560L Series  I/O CIRCUIT TYPE Type Circuit Remarks A It is possible to select the main oscillation / GPIO function P-ch P-ch Digital output X1 N-ch R When the main oscillation is selected. ・ Oscillation feedback resistor : Approximately 1MΩ ・ With Standby mode control When the GPIO is selected. ・ CMOS level output. ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control Pull-up resistor control ・ Pull-up resistor : Approximately 50kΩ Digital input ・ IOH = -4mA, IOL = 4mA Digital output Standby mode control Clock input Standby mode control Digital input Standby mode control R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control ・ CMOS level hysteresis input ・Pull-up resistor : Approximately 50kΩ B Pull-up resistor Digital input 30 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series Type Circuit Remarks C Digital input ・ Open drain output ・CMOS level hysteresis input Digital output N-ch E P-ch Digital output P-ch ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ ・IOH = -4mA, IOL = 4mA Digital output N-ch R Pull-up resistor control Digital input Standby mode control F P-ch Digital output P-ch Digital output N-ch ・ CMOS level output ・ CMOS level hysteresis input ・ With input control ・ Analog input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ  IOH = -4mA, IOL = 4mA ・When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control R Digital input Standby mode control Analog input Input control DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 31 r1.0 MB9B560L Series Type Circuit Remarks G P-ch P-ch Digital output ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ  IOH = -12mA, IOL = 12mA ・When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output N-ch R Pull-up resistor control Digital input Standby mode control H GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control It is possible to select the USB I/O / GPIO function. When the USB I/O is selected. ・ Full-speed, Low-speed control UDP output UDP/Pxx USB Full-speed/Low-speed control UDP input Differential UDM/Pxx Differential input USB/GPIO select When the GPIO is selected. ・ CMOS level output ・ CMOS level hysteresis input ・ With standby mode control ・ IOH = -20.5mA, IOL = 18.5mA UDM input UDM output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control 32 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series Type Circuit Remarks I P-ch P-ch N-ch Digital output Digital output ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ 5V tolerant ・ With standby mode control ・ IOH = -4mA, IOL = 4mA  Available to control of PZR registers. ・When this pin is used as an I2C pin, the digital output P-ch transistor is always off R Pull-up resistor control Digital input Standby mode control J CMOS level hysteresis input Mode input L P-ch P-ch N-ch R Digital output ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ  IOH = -8mA, IOL = 8mA ・When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Pull-up resistor control Digital input Standby mode control DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 33 r1.0 MB9B560L Series Type Circuit Remarks M P-ch P-ch N-ch Digital output Digital output ・ CMOS level output ・ CMOS level hysteresis input ・ With input control ・ Analog input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ  IOH = -8mA, IOL = 8mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input R Standby mode control Analog input Input control N P-ch P-ch N-ch N-ch R Pull-up resistor control Digital output Digital output ・ CMOS level output ・ CMOS level hysteresis input ・With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ ・IOH = -4mA, IOL = 4mA (GPIO) ・IOL = 20mA  (Fast Mode Plus) When this pin is used as an I2C pin, the digital output P-ch transistor is always off Fast mode control Digital input Standby mode control 34 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series Type Circuit Remarks O P-ch P-ch N-ch Pull-up resistor control Digital output Digital output ・ CMOS level output ・ CMOS level hysteresis input ・5V tolerant ・With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ ・ IOH = -4mA, IOL = 4mA ・ For I/O setting, refer to VBAT Domain in the PERIPHERAL MANUAL R Digital input Standby mode control P P-ch P-ch X0A N-ch Pull-up resistor control Digital output ・ CMOS level output ・ CMOS level hysteresis input ・With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ ・ IOH = -4mA, IOL = 4mA ・ For I/O setting, refer to VBAT Domain in the PERIPHERAL MANUAL Digital output R Digital input Standby mode control OSC DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 35 r1.0 MB9B560L Series Type Circuit Remarks Q It is possible to select the sub oscillation / GPIO function Pull-up resistor control Digital output P-ch P-ch X1A Digital output N-ch R Digital input Standby mode control OSC When the sub oscillation is selected. ・ Oscillation feedback resistor : Approximately 10MΩ ・ With Standby mode control When the GPIO is selected. ・ CMOS level output. ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ ・ IOH = -4mA, IOL = 4mA ・ For I/O setting, refer to VBAT Domain in the PERIPHERAL MANUAL RX Standby mode control Clock input R P-ch P-ch N-ch R Digital output Digital output ・ CMOS level output ・ CMOS level hysteresis input ・ With input control ・ Analog output ・With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 50kΩ ・IOH = -12mA, IOL = 12mA (4.5V～5.5V) ・IOH = -8mA, IOL = 8mA (2.7V～4.5V) Pull-up resistor control Digital input Standby mode control Analog output 36 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your FUJITSU SEMICONDUCTOR semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-2Ea DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 37 r1.0 MB9B560L Series  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.  Precautions Related to Usage of Devices FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under FUJITSU SEMICONDUCTOR's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions. 38 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU SEMICONDUCTOR recommended conditions for baking. Condition: 125°C/24 h  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 39 r1.0 MB9B560L Series 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://edevice.fujitsu.com/fj/handling-e.pdf 40 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  HANDLING DEVICES  Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device.  Power supply pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply.  Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board.  Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. • Surface mount type Size : More than 3.2 mm × 1.5 mm Load capacitance : Approximately 6 pF to 7 pF • Lead type Load capacitance : Approximately 6 pF to 7 pF DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 41 r1.0 MB9B560L Series  Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.  Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. X1(PE3), X1A (P47) Set as External clock input  Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.  C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND  Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. 42 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VBAT → VCC → USBVCC VCC → AVCC → AVRH Turning off : USBVCC → VCC → VBAT AVRH → AVCC → VCC  Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data.  Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.  Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.  Handling when using debug pins When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 43 r1.0 MB9B560L Series  BLOCK DIAGRAM MB9BF564K/L, F565K/L, F566K/L TRSTX,TCK, TDI,TMS TDO SRAM0 16/24/32 Kbytes SWJ-DP ROM Table SRAM1 8/12/16 Kbytes Cortex-M4F　Core I @160 MHz(Max) MPU NVIC Multi-layer AHB (Max 160 MHz) D FPU Sys AHB-APB Bridge: APB0(Max 80 MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) SRAM2 8/12/16 Kbytes MainFlash I/F MainFlash 512 Kbytes/ 384 Kbytes/ 256 Kbytes Trace Buffer (16 Kbytes) Security WorkFlash 32 Kbytes WorkFlash I/F USB2.0 (Host/ Func) CSV PHY USBVCC UDP0,UDM0 UHCONX0 DMAC 8ch. CLK DSTC X0A X1A Main Osc PLL VBAT Domain Sub Osc AHB-AHB Bridge Source Clock X0 X1 CR 100 kHz CR 4 MHz TIOAx TIOBx AINx BINx ZINx CAN Prescaler Unit 1 USB Clock Ctrl Base Timer 16-bit 16ch./ 32-bit 8ch. QPRC 1ch. A/D Activation Compare 6ch. ICxx FRCKx 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. DTTIxX RTOxx GPIO P0x, P1x, PLL . . . PEx Power-On Reset LVD Ctrl LVD IRQ-Monitor Regulator C CRC Accelerator AHB-APB Bridge : APB2 (Max 80 MHz) ADTGx 12-bit A/D Converter Unit 0 AHB-APB Bridge : APB1 (Max 160 MHz) ANxx TX0, RX0 PIN-FunctionCtrl CROUT AVCC, AVSS, AVRH CAN Watch Counter Deep Standby Ctrl Peripheral Clock Gating Low-speed CR Prescaler VBAT Domain Real-Time Clock Port Ctrl. Multi-function Timer × 2 44 FUJITSU SEMICONDUCTOR CONFIDENTIAL VWAKEUP VREGCTL RTCCO, SUBOUT External Interrupt Controller 16pin + NMI INTxx NMIX MODE-Ctrl MD0, MD1 Multi-function Serial I/F 6ch. HW flow control(ch.4) SCKx SINx SOTx CTS4 RTS4 12-bit D/A Converter 2units DAx Waveform Generator 3ch. 16-bit PPG 3ch. WKUPx DS709-00005-1v0-E r1.0 MB9B560L Series  MEMORY SIZE See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.  MEMORY MAP  Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4007_0000 0x4006_F000 GPIO Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M4F Private Peripherals 0x4006_3000 0x4006_2000 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 External Device Area 0x6000_0000 Reserved 0x4400_0000 0x4200_0000 32 Mbytes Bit band alias Peripherals 0x4000_0000 Reserved 0x2400_0000 0x2200_0000 32 Mbytes Bit band alias Reserved 0x2010_0000 0x200E_0000 0x200C_0000 See "Memory Map (2)" for the memory size details. 0x2004_4000 0x2004_0000 0x2003_C000 0x2000_0000 0x1FFF_8000 0x0050_0000 0x0040_0000 WorkFlash I/F WorkFlash Reserved SRAM2 SRAM1 Reserved SRAM0 Reserved Security/CR Trim MainFlash 0x0000_0000 FUJITSU SEMICONDUCTOR CONFIDENTIAL Reserved USB ch.0 Reserved 0x4003_C800 0x4003_C100 Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4003_8000 MFS 0x4003_7000 CAN prescaler 0x4003_6000 USB Clock ctrl 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4003_3000 D/AC Reserved 0x4003_2000 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x4002_F000 Reserved 0x4002_E000 CR Trim 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_2000 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 DS709-00005-1v0-E CAN ch.0 DSTC DMAC Reserved A/DC QPRC Base Timer PPG Reserved MFT Unit1 MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved MainFlash I/F 45 r1.0 MB9B560L Series  Memory Map (2) MB9BF566K/L 0x2008_0000 MB9BF565K/L 0x2008_0000 Reserved 0x200C_8000 0x200C_0000 0x2008_0000 Reserved 0x200C_8000 WorkFlash 32 Kbytes MB9BF564K/L 0x200C_0000 Reserved Reserved 0x200C_8000 WorkFlash 32 Kbytes 0x200C_0000 Reserved 0x2004_4000 WorkFlash 32 Kbytes Reserved 0x2004_3000 SRAM2 16 Kbytes 0x2004_0000 0x2004_0000 SRAM1 16 Kbytes 0x2003_D000 SRAM2 12 Kbytes SRAM1 12 Kbytes 0x2004_2000 0x2004_0000 0x2003_E000 SRAM2 8 Kbytes SRAM1 8 Kbytes 0x2003_C000 0x2000_0000 0x2000_0000 SRAM0 32 Kbytes Reserved Reserved Reserved 0x1FFF_A000 0x2000_0000 SRAM0 24 Kbytes 0x1FFF_C000 SRAM0 16 Kbytes 0x1FFF_8000 0x0050_0000 0x0040_2000 0x0040_0000 0x0050_0000 CR trimming Security Reserved Reserved Reserved 0x0040_2000 0x0040_0000 0x0050_0000 CR trimming Security 0x0040_2000 0x0040_0000 CR trimming Security Reserved Reserved 0x0008_0000 Reserved 0x0006_0000 MainFlash 512 Kbytes 0x0000_0000 0x0004_0000 MainFlash 384 Kbytes 0x0000_0000 46 FUJITSU SEMICONDUCTOR CONFIDENTIAL MainFlash 256 Kbytes 0x0000_0000 DS709-00005-1v0-E r1.0 MB9B560L Series  Peripheral Address Map Start address End address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_5800 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_C100 0x4003_C800 0x4004_0000 0x4005_0000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_3000 0x4006_F000 0x4006_7000 0x200E_0000 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_0FFF 0x4002_1FFF 0x4003_FFFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_4FFF 0x4003_3FFF 0x4003_4FFF 0x4003_57FF 0x4003_5FFF 0x4003_6FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_C0FF 0x4003_C7FF 0x4003_FFFF 0x4004_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_1FFF 0x4006_2FFF 0x4006_EFFF 0x4006_FFFF 0x41FF_FFFF 0x200E_FFFF Bus AHB APB0 APB1 APB2 AHB DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Peripherals MainFlash I/F register Reserved Clock/Reset Control Hardware Watchdog timer Software Watchdog timer Reserved Dual-Timer Reserved Multi-function timer unit0 Multi-function timer unit1 Reserved PPG Base Timer Quadrature Position/Revolution Counter A/D Converter Reserved Internal CR trimming Reserved External Interrupt Controller Interrupt Request Batch-Read Function Reserved D/A Converter Reserved Low Voltage Detector Deep standby mode Controller USB clock generator CAN prescaler Multi-function serial Interface CRC Watch Counter RTC/Port Ctrl Low-speed CR Prescaler Peripheral Clock Gating Reserved USB ch.0 Reserved DMAC register DSTC register CAN ch.0 Reserved GPIO Reserved WorkFlash I/F register 47 r1.0 MB9B560L Series  PIN STATUS IN EACH CPU STATE The terms used for pin status have the following meanings. ・ INITX=0 This is the period when the INITX pin is the "L" level. ・ INITX=1 This is the period when the INITX pin is the "H" level. ・ SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0". ・ SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1". ・ Input enabled Indicates that the input function can be used. ・ Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L". ・ Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. ・ Setting disabled Indicates that the setting is disabled. ・ Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. ・ Analog input is enabled Indicates that the analog input is enabled. ・ Trace output Indicates that the trace function can be used. ・ GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. ・ Setting prohibition Prohibition of a setting by specification limitation. 48 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r2.1 MB9B560L Series Pin status type ・ List of Pin Status A Function group Power-on reset or low-voltage detection state Power supply unstable ‐ ‐ INITX input state Device internal reset state Power supply stable INITX=0 INITX=1 ‐ ‐ Run mode or SLEEP mode state Power supply stable INITX=1 ‐ GPIO selected Setting disabled Setting Setting disabled disabled Maintain previous state Main crystal oscillator input pin/ External main clock input selected Input enabled Input Input enabled enabled Input enabled TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Maintain previous state Input enabled GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Input enabled Input enabled GPIO Hi-Z / selected Setting Internal Internal disabled input fixed input fixed at "0" at "0" Hi-Z / Maintain Maintain Maintain Setting Internal previous previous previous disabled input fixed state state state at "0" Maintain Maintain Maintain Maintain previous previous previous previous Hi-Z / state/When state/When state/When state/When Internal oscillation oscillation oscillation oscillation input stops*1, stops*1, stops*1, stops*1, fixed Hi-Z / Hi-Z / Hi-Z / Hi-Z / at "0" Internal Internal Internal Internal input fixed input fixed input fixed input fixed at "0" at "0" at "0" at "0" Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Input Input Input Input Input enabled enabled enabled enabled enabled Maintain previous state Maintain previous state Return from Deep standby mode state Power supply stable INITX=1 - GPIO selected Input enabled Input enabled Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected Setting disabled Setting disabled External main clock input selected Setting disabled Setting disabled Main crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at "0" C INITX input pin Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input Input enabled enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input Input enabled enabled Setting Setting disabled disabled Input enabled Hi-Z / Input enabled Input enabled Hi-Z / Input enabled Input enabled Setting disabled Input enabled Maintain previous state Input enabled GPIO selected Input enabled Maintain previous state B E DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL GPIO selected Hi-Z / Maintain Internal previous input fixed state at "0" Maintain Maintain previous previous state/When state/When oscillation oscillation stops*1, stops*1, Hi-Z / Hi-Z / Internal Internal input fixed input fixed at "0" at "0" Pull-up / Pull-up / Input Input enabled enabled GPIO selected 49 r1.0 Pin status type MB9B560L Series Function group NMIX selected F Resource other than above selected Power-on reset or low-voltage detection state Device internal reset state Power supply unstable ‐ ‐ INITX=0 INITX=1 ‐ ‐ Setting disabled Setting Setting disabled disabled Hi-Z GPIO selected JTAG selected INITX input state Hi-Z Power supply stable Hi-Z / Hi-Z / Input Input enabled enabled Pull-up / Pull-up / Input Input enabled enabled G GPIO selected J K Analog output selected External interrupt enabled selected Resource other than above selected GPIO selected External interrupt enabled selected Resource other than above selected GPIO selected Setting disabled Setting Setting disabled disabled Run mode or SLEEP mode state Power supply stable INITX=1 ‐ TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state *2 Setting disabled Setting Setting disabled disabled Maintain previous state Hi-Z Hi-Z / Hi-Z / Input Input enabled enabled Setting disabled Setting Setting disabled disabled Hi-Z Hi-Z / Hi-Z / Input Input enabled enabled Hi-Z / Internal input fixed at "0" Maintain previous state 50 FUJITSU SEMICONDUCTOR CONFIDENTIAL Maintain previous state Power supply stable INITX=1 - GPIO selected Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected *3 Hi-Z / Internal input fixed at "0" Maintain previous state Maintain previous state Hi-Z / WKUP input enabled GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Maintain previous state Maintain previous state WKUP input enabled Return from Deep standby mode state Hi-Z / Internal input fixed at "0" GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" GPIO selected GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" GPIO selected DS709-00005-1v0-E r2.1 Pin status type MB9B560L Series Power-on reset or lowvoltage detection Function group Power supply ‐ Hi-Z L Resource other than above selected GPIO selected Analog input selected M External interrupt enabled selected Resource other than above selected GPIO selected state Device internal reset state Run mode or SLEEP mode state TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply Power supply Power supply stable stable INITX=1 INITX=1 Return from Deep standby mode state state unstable ‐ Analog input selected INITX input Setting disabled Hi-Z Power supply stable INITX=0 INITX=1 ‐ ‐ stable INITX=1 ‐ SPL=0 SPL=1 stable SPL=1 INITX=1 - Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal Internal input input input fixed input fixed input fixed input fixed input fixed input fixed fixed fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog Analog input input input input input input input input enabled enabled enabled enabled enabled enabled enabled enabled Setting Setting disabled disabled Maintain previous state Maintain previous state GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" GPIO selected Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal Internal input input input fixed input fixed input fixed input fixed input fixed input fixed fixed fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog Analog input input input input input input input input enabled enabled enabled enabled enabled enabled enabled enabled Maintain previous state Setting disabled SPL=0 Power supply Setting Setting disabled disabled Maintain previous state DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Maintain previous state Hi-Z / Internal input fixed at "0" GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" GPIO selected 51 r1.0 Pin status type MB9B560L Series Function group Power-on reset or lowvoltage detection state Power supply unstable ‐ ‐ Analog input selected O WKUP enabled External interrupt enabled selected Resource other than above selected GPIO selected Analog input selected P Hi-Z Setting disabled Device internal reset state Power supply stable INITX=0 INITX=1 ‐ ‐ Run mode or SLEEP mode state Power supply stable INITX=1 ‐ Hi-Z Hi-Z Setting disabled Deep standby RTC TIMER mode, RTC mode, or STOP mode state mode or Deep standby STOP mode state Power supply Power supply stable stable INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 Return from Deep standby mode state Power supply stable INITX=1 - Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal Internal input input input fixed input fixed input fixed input fixed input fixed input fixed fixed fixed at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / Analog Analog Analog Analog Analog Analog Analog Analog input input input input input input input input enabled enabled enabled enabled enabled enabled enabled enabled WKUP WKUP input input Maintain enabled enabled Setting Setting previous disabled disabled state Maintain previous state WKUP enabled Resource other than above selected GPIO selected INITX input state Hi-Z Hi-Z Input Input enabled enabled Maintain previous state Hi-Z / Internal input fixed at "0" GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" GPIO selected Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal Internal Internal input input input fixed input fixed input fixed input fixed input fixed input fixed fixedat fixedat at "0" / at "0" / at "0" / at "0" / at "0" / at "0" / "0" / "0" / Analog Analog Analog Analog Analog Analog Analog Analog input input input input input input input input enabled enabled enabled enabled enabled enabled enabled enabled Hi-Z / Maintain WKUP WKUP previous input input state enabled enabled Maintain Maintain Setting Setting GPIO previous previous GPIO disabled disabled selected Hi-Z / Hi-Z / state state selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" 52 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r2.1 Pin status type MB9B560L Series Function group Power-on reset or lowvoltage detection state Power supply unstable ‐ ‐ INITX input state Device internal reset state Power supply stable INITX=0 INITX=1 ‐ ‐ Run mode or SLEEP mode state Power supply stable INITX=1 ‐ mode or Deep standby STOP mode state Power supply Power supply stable stable INITX=1 SPL=0 WKUP enabled Setting disabled Q External interrupt enabled selected Resource other than above selected GPIO selected GPIO selected Hi-Z Hi-Z Hi-Z / Hi-Z / Input Input enabled enabled Maintain previous state USB I/O pin Setting disabled Setting Setting disabled disabled INITX=1 SPL=0 SPL=1 WKUP input enabled Hi-Z / WKUP input enabled Maintain previous state Return from Deep standby mode state Power supply stable INITX=1 - GPIO selected Hi-Z / Internal input fixed at "0" Hi-Z / Hi-Z / Input Input enabled enabled R SPL=1 Maintain previous state Setting Setting disabled disabled Maintain previous state Deep standby RTC TIMER mode, RTC mode, or STOP mode state GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" GPIO Hi-Z / selected Internal Hi-Z / Internal Maintain input fixed Internal input fixed previous at "0" input fixed at "0" state Hi-Z / at "0" Hi-Z / Input Input enabled enabled Hi-Z at Hi-Z at transtransmission/ mission/ Input Input Hi-Z / Hi-Z / enabled/ enabled/ Input Input Internal Internal enabled enabled input fixed input fixed at "0" at at "0" at reception reception GPIO selected Hi-Z / Input enabled *1 : Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep standby STOP mode. *2 : Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode. *3 : Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 53 r1.0 MB9B560L Series VBAT pin status type ・ List of VBAT Domain Pin Status S VBAT Power-on reset INITX input state Function group Device Run mode internal or SLEEP reset mode state state Power Power supply Power supply stable supply unstable stable ‐ INITX=0 INITX=1 INITX=1 ‐ ‐ ‐ ‐ TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX=1 SPL=0 SPL=1 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state External sub clock input selected Setting disabled Setting disabled Setting disabled Sub crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable T Resource selected Hi-Z U GPIO selected Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" INITX=1 SPL=0 SPL=1 GPIO Hi-Z / Hi-Z / selected Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Input enabled Input enabled GPIO Hi-Z / selected Internal Internal input fixed input fixed at "0" at "0" Hi-Z / Maintain Maintain Maintain Internal previous previous previous input fixed state state state at "0" Maintain Maintain Maintain previous previous previous state/When state/When state/When Maintain oscillation oscillation oscillation previous stops*, stops*, stops*, state Hi-Z / Hi-Z / Hi-Z/ Internal Internal Internal input fixed input fixed input fixed at "0" at "0" at "0" Maintain Maintain Maintain previous previous previous state state state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Return Return from from VBAT Deep VBAT RTC standby RTC mode state mode mode state state Power Power Power supply supply stable supply stable stable INITX=1 GPIO selected Input enabled Input enabled Hi-Z / Internal input fixed at "0" GPIO selected Hi-Z / Internal input fixed at "0" Maintain previous state/When oscillation stops*, Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state Setting prohibition Maintain Maintain previous previous state state Setting prohibition FUJITSU SEMICONDUCTOR CONFIDENTIAL - Maintain Maintain previous previous state state Maintain previous state/When oscillation Maintain Maintain stops*, previous previous Hi-Z/ state state Internal input fixed at "0" Maintain previous state Maintain Maintain previous previous state state *: Oscillation is stopped at STOP mode and Deep standby STOP mode. 54 - DS709-00005-1v0-E r2.1 MB9B560L Series  ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage *1, *2 Power supply voltage (for USB)*1, * 3 Power supply voltage (VBAT) *1 ,*4 Analog power supply voltage *1 ,*5 Analog reference voltage *1 ,*5 Symbol VCC USBVCC VBAT AVCC AVRH Rating Min Max Unit Remarks VSS + 6.5 V VSS + 6.5 V VSS + 6.5 V VSS + 6.5 V VSS + 6.5 V VCC + 0.5 Except for USB VSS - 0.5 V (≤ 6.5V) pin 1 USBV + 0.5 Input voltage * VI CC VSS - 0.5 V USB pin (≤ 6.5V) VSS - 0.5 VSS + 6.5 V 5V tolerant AVCC + 0.5 1 Analog pin input voltage * VIA VSS - 0.5 V (≤ 6.5V) VCC + 0.5 Output voltage *1 VO VSS - 0.5 V (≤ 6.5V) 10 mA 4mA type 20 mA 8mA type "L" level maximum output current *6 IOL 20 mA 12mA type 22.4 mA I2C Fm+ 4 mA 4mA type 8 mA 8mA type 7 "L" level average output current * IOLAV 12 mA 12mA type 20 mA I2C Fm+ "L" level total maximum output current ∑IOL 100 mA "L" level total maximum output current *8 ∑IOLAV 50 mA - 10 mA 4mA type "H" level maximum output current *6 IOH - 20 mA 8mA type - 20 mA 12mA type -4 mA 4mA type "H" level average output current *7 IOHAV -8 mA 8mA type - 12 mA 12mA type "H" level total maximum output current ∑IOH - 100 mA "H" level total average output current *8 ∑IOHAV - 50 mA Storage temperature TSTG - 55 + 150 °C *1 : These parameters are based on the condition that VSS = AVSS = 0.0V. *2 : VCC must not drop below VSS - 0.5V. *3 : USBVCC must not drop below VSS - 0.5V. *4 : VBAT must not drop below VSS - 0.5V. *5 : Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on. *6 : The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *7 : The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100ms period. *8 : The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 55 r1.0 MB9B560L Series Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. 56 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series 2. Recommended Operating Conditions Parameter Power supply voltage Symbol Conditions VCC - Min 2.7 3.0 Power supply voltage (for USB) USBVCC 2.7 Value Max 5.5 3.6 (≤ VCC) 5.5 (≤ VCC) 5.5 5.5 AVCC + 125 *4 Unit Remarks V *1 V *2 Power supply voltage (VBAT) VBAT 2.7 V Analog power supply voltage AVCC 2.7 V AVCC=VCC Analog reference voltage AVRH *3 V Junction temperature Tj - 40 °C Operating temperature Ambient temperature Ta - 40 °C *1 : When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *2 : When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *3 : The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See "5. 12-bit A/D Converter" for the details. *4 : The maximum temperature of the ambient temperature (Ta) can guarantee a range that does not exceed the junction temperature (Tj). The calculation formula of the ambient temperature (Ta) is shown below. Ta(Max) = Tj(Max) - Pd(Max) × θja Pd : Power dissipation (W) θja : Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL IOH VOL VOH : "L" level output current : "H" level output current : "L" level output voltage : "H" level output voltage Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices.  Table for package thermal resistance and maximum permissible power Thermal Maximum permissible power resistance θja (mW) Package Printed circuit board (°C/W) Ta=+85°C Ta=+105°C FPT-48P-M49 (0.5mm pitch) LCC-48P-M73 (0.5mm pitch) FPT-64P-M38 (0.5mm pitch) FPT-64P-M39 (0.65mm pitch) LCC-64P-M24 (0.5mm pitch) Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 87 53 30 24 70 45 61 40 24 21 460 755 1333 1667 571 889 656 1000 1667 1905 230 377 667 833 286 444 328 500 833 952 57 r1.0 MB9B560L Series The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.  Calculation method of power dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL IOH VOL VOH : "L" level output current : "H" level output current : "L" level output voltage : "H" level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT) : Current consumed in internal logic and memory, etc. through regulator ΣICC(IO) : Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT : Pin internal load capacitance CEXT : External load capacitance of output pin fSW : Pin switching frequency Parameter Pin internal load capacitance Symbol CINT Conditions Capacitance value 4mA type 1.93pF 8mA type 3.45pF 12mA type 3.42pF Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself. (1) Measure current value ICC (Typ) at normal temperature (+25°C). (2) Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Maximum leak current at operating Symbol Conditions Current value ICC(leak_max) Tj = +125°C Tj = +105°C Tj = +85°C 28mA 17mA 13mA 58 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series  Current explanation diagram Pd = VCC×ICC + Σ(IOL×VOL) + Σ((VCC-VOH)×(-IOH)) ICC = ICC(INT) + ΣICC(IO) VCC A ICC Chip ICC(INT) ΣICC(IO) A IOL Regulator V VOL ・・・ Flash VOH V IOH ・・・ Logic A RAM ICC(IO) CEXT ・・・ DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 59 r1.0 MB9B560L Series 3. DC Characteristics (1) Current Rating Parameter Symbol Power supply current ICC Parameter Symbol Power supply current ICC Pin name VCC Pin name VCC Conditions Frequency*4 Normal operation*5,*6 (PLL) 160MHz 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz 160MHz 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz Conditions Frequency*7 Normal operation*8 (PLL) 160MHz 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz 160MHz 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz Value Unit Typ*1 Max*2 44 40 34 29 23 18 13 7.7 4.6 3.6 30 27 23 20 16 13 9 5.7 3.7 3 72 67 60 55 48 42 37 31 27 26 58 54 49 46 41 38 33 30 27 26 mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF Value Unit Typ*1 Max*2 64 60 52 46 39 32 25 15 7.8 5.2 47 43 39 35 30 25 20 13 6.7 4.6 101 96 88 81 73 65 58 47 39 36 80 75 71 66 61 55 50 42 36 34 Remarks Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF *1: Ta=+25°C, VCC=3.3V *2: Tj=+125°C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) 60 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series Parameter Symbol Power supply current ICC Pin name VCC Conditions Normal operation*5 (PLL) Value Frequency*4 Unit (MHz) Typ*1 Max*2 72MHz 60MHz 48MHz 36MHz 24MHz 12MHz 8MHz 4MHz 72MHz 60MHz 48MHz 36MHz 24MHz 12MHz 8MHz 4MHz 41 36 31 25 18 11 8.1 5.4 32 28 24 20 15 9.1 6.9 4.6 75 69 64 57 50 42 39 37 63 58 54 50 45 38 36 34 Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF *1: Ta=+25°C, VCC=3.3V *2: Tj=+125°C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00) Parameter Symbol Pin name Conditions Normal operation*5 (built-in high-speed CR) Power supply current ICC VCC Normal operation*5 (sub oscillation) Normal operation*5 (built-in low-speed CR) Frequency*4 Value Typ*1 Max*2 Unit 3.3 29 mA 2.8 29 mA 0.51 27 mA 0.50 27 mA 0.54 27 mA 0.52 27 mA 4MHz 32kHz 100kHz Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *1: Ta=+25°C, VCC=3.3V *2: Tj=+125°C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait- cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 61 r1.0 MB9B560L Series Parameter Symbol Power supply current ICCS Parameter Symbol Power supply current ICCS Value Pin Conditions Frequency*4 name Typ*1 Max*2 VCC SLEEP operation (PLL) Pin Conditions name VCC 160MHz 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz 160MHz 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz Frequency*5 SLEEP operation (PLL) 72MHz 60MHz 48MHz 36MHz 24MHz 12MHz 8MHz 4MHz 72MHz 60MHz 48MHz 36MHz 24MHz 12MHz 8MHz 4MHz 28 25 21 18 15 12 8.8 5.6 3.8 3.2 14 13 11 9.7 8.1 6.7 5.2 3.7 2.9 2.6 58 55 50 46 43 39 36 32 30 29 44 43 40 38 36 34 32 30 29 29 Value Typ*1 Max*2 19 16 13 10 7.8 5.2 4.3 3.5 8.8 7.7 6.6 5.5 4.4 3.4 3 2.7 47 43 40 37 34 31 30 29 36 35 34 32 31 30 29 29 Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF *1: Ta=+25°C, VCC=3.3V *2: Tj=+125°C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK 62 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series Parameter Symbol Pin name Conditions SLEEP operation (built-in high-speed CR) Power supply current ICCS VCC SLEEP operation (sub oscillation) SLEEP operation (built-in low-speed CR) Frequency*4 Value Unit Typ*1 Max*2 1.3 27 mA 0.91 27 mA 0.49 27 mA 0.48 27 mA 0.51 27 mA 0.49 27 mA 4MHz 32kHz 100kHz Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *1: Ta=+25°C, VCC=3.3V *2: Tj=+125°C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 63 r1.0 MB9B560L Series Parameter Symbol Pin name ICCH Conditions STOP mode TIMER mode (built-in high-speed CR) Power supply current ICCT VCC TIMER mode (sub oscillation) TIMER mode (built-in low-speed CR) ICCR RTC mode (sub oscillation) Frequency - 4MHz 32kHz 100kHz 32kHz Value Unit Typ*1 Max*2 0.25 1.0 mA - 11 mA - 14 mA 0.54 1.54 mA - 12 mA - 15 mA 0.25 1.0 mA - 11 mA - 14 mA 0.26 1.0 mA - 11 mA - 14 mA 0.25 1.0 mA - 11 mA - 14 mA Remarks *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *1: VCC=3.3V *2: VCC=5.5V *3: When all ports are fixed. *4: When LVD is OFF 64 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series Parameter Symbol Pin name Conditions Frequency Deep standby STOP mode (When RAM is OFF) ICCHD Value Typ*1 Max*2 Unit 27 140 μA - 590 μA - 770 μA 32 180 μA - 870 μA - 1200 μA 27 140 μA - 590 μA - 770 μA 32 180 μA - 870 μA - 1200 μA 0.015 0.14 μA - 4.0 μA - 9.4 μA 1.3 2.4 μA - 6.2 μA - 12 μA Deep standby STOP mode (When RAM is ON) VCC Power supply current Deep standby RTC mode (When RAM is OFF) ICCRD 32kHz Deep standby RTC mode (When RAM is ON) RTC stop ICCVBAT VBAT RTC operation Remarks *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *3, *4, *5 Ta=+25°C *3, *4, *5 Ta=+85°C *3, *4, *5 Ta=+105°C *3, *4 Ta=+25°C *3, *4 Ta=+85°C *3, *4 Ta=+105°C *1: VCC=3.3V *2: VCC=5.5V *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 65 r1.0 MB9B560L Series Parameter Low-voltage detection circuit (LVD) power supply current Symbol Pin name Conditions ICCLVD Main flash memory write/erase current ICCFLASH Work flash memory write/erase current ICCWFLASH VCC  Peripheral current dissipation Clock Peripheral system HCLK PCLK1 PCLK2 Min Value Typ Max Remarks For occurrence of interrupt At operation - 4 7 μA At Write/Erase - 13.4 15.9 mA At Write/Erase - 11.5 13.6 mA Unit Frequency (MHz) 40 80 160 GPIO All ports 0.21 0.43 0.92 DMAC - 0.71 1.43 2.74 DSTC - 0.36 0.72 1.46 CAN 1ch. 0.03 0.06 0.11 USB 1ch. 0.42 0.80 1.60 Base timer 4ch. 0.18 0.36 0.70 1unit/4ch. 0.57 1.13 2.24 1unit 0.04 0.08 0.16 A/DC 1unit 0.21 0.40 0.79 Muli-function serial 1ch. 0.33 0.67 - Multi-functional timer/PPG Quadrature position/Revolution counter Unit Unit Remarks mA mA 66 FUJITSU SEMICONDUCTOR CONFIDENTIAL mA DS709-00005-1v0-E r1.0 MB9B560L Series (2) Pin Characteristics (VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin name "H" level input voltage (hysteresis input) "L" level input voltage (hysteresis input) VIHS VILS CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I2C Fm+ CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I2C Fm+ 4mA type 8mA type "H" level output voltage VOH 12mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ Min Value Typ Max - VCC×0.8 - VCC + 0.3 V - VCC×0.8 - VSS + 5.5 V - VCC×0.7 - VSS + 5.5 V - VSS - 0.3 - VCC×0.2 V - VSS - 0.3 - VCC×0.2 V - VSS - VCC×0.3 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC - 0.5 - VCC V USBVCC 0.4 - USBVCC V VCC - 0.5 - VCC V Conditions VCC ≥ 4.5 V, IOH = - 4mA VCC < 4.5 V, IOH = - 2mA VCC ≥ 4.5 V, IOH = - 8mA VCC < 4.5 V, IOH = - 4mA VCC ≥ 4.5 V, IOH = - 12mA VCC < 4.5 V, IOH = - 8mA USBVCC ≥ 4.5 V, IOH = - 20.5mA USBVCC < 4.5 V, IOH = - 13.0mA VCC ≥ 4.5 V, IOH = - 4mA VCC < 4.5 V, IOH = - 3mA DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Unit Remarks At GPIO 67 r1.0 MB9B560L Series Parameter Symbol Pin name 4mA type 8mA type "L" level output voltage VOL 12mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ Input leak current Pull-up resistor value Input capacitance Conditions VCC ≥ 4.5 V, IOL = 4mA VCC < 4.5 V, IOL = 2mA VCC ≥ 4.5 V, IOH = 8mA VCC < 4.5 V, IOH = 4mA VCC ≥ 4.5 V, IOL = 12mA VCC < 4.5 V, IOL = 8mA USBVCC ≥ 4.5 V, IOL = 18.5mA USBVCC < 4.5 V, IOL = 10.5mA VCC ≥ 4.5 V, IOH = 4mA VCC < 4.5 V, IOH = 3mA VCC ≤ 5.5 V, IOH = 20mA Min Value Typ Max VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 Unit Remarks V At I2C Fm+ IIL - - -5 - +5 μA RPU Pull-up pin VCC ≥ 4.5 V VCC < 4.5 V 25 30 50 80 100 200 kΩ CIN Other than VCC, USBVCC, VBAT, VSS, AVCC, AVSS, AVRH - - 5 15 pF 68 FUJITSU SEMICONDUCTOR CONFIDENTIAL At GPIO DS709-00005-1v0-E r1.0 MB9B560L Series 4. AC Characteristics (1) Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time Pin Conditions name FCH tCYLH X0, X1 tCF, tCR Value Min Max Unit VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V PWH/tCYLH, PWL/tCYLH 4 4 4 4 20.83 50 48 20 48 20 250 250 45 55 % - - 5 ns MHz MHz ns Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock When using external clock Base clock (HCLK/FCLK) Internal operating FCP0 80 MHz APB0 bus clock*2 clock*1 frequency FCP1 160 MHz APB1 bus clock*2 FCP2 80 MHz APB2 bus clock*2 Base clock tCYCC 6.25 ns (HCLK/FCLK) Internal operating t 12.5 ns APB0 bus clock*2 CYCP0 clock*1 cycle time tCYCP1 6.25 ns APB1 bus clock*2 tCYCP2 12.5 ns APB2 bus clock*2 *1: For more information about each internal operating clock, see "Chapter:Clock" in "FM4 Family PERIPHERAL MANUAL". *2: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data sheet. FCC - - - 160 MHz X0 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 69 r1.0 MB9B560L Series (2) Sub Clock Input Characteristics (VBAT = 2.7V to 5.5V, VSS = 0V) Parameter Pin Conditions name Min Value Typ Max - - 32.768 - kHz - 32 - 100 kHz tCYLL - 10 - 31.25 μs - PWH/tCYLL, PWL/tCYLL 45 - 55 % Symbol 1/ tCYLL Input frequency X0A, X1A Input clock cycle Input clock pulse width 0.8 × VBAT Unit VBAT X0A Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock VBAT VBAT VBAT (3) Built-in CR Oscillation Characteristics ・ Built-in High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Min Typ Max Ta = - 20°C to + 105°C 3.92 4 4.08 Ta = - 40°C to + 125°C 3.88 4 4.12 Unit Remarks When trimming* Clock frequency FCRH MHz When not trimming *: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. Ta = - 40°C to + 125°C 3 4 5 ・ Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Clock frequency Symbol Condition FCRL - 70 FUJITSU SEMICONDUCTOR CONFIDENTIAL Value Min Typ Max 50 100 150 Unit Remarks kHz DS709-00005-1v0-E r1.0 MB9B560L Series (4-1) Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 200 μs (LOCK UP time) PLL input clock frequency FPLLI 4 16 MHz PLL multiplication rate 13 80 multiplier PLL macro oscillation clock frequency FPLLO 200 320 MHz Main PLL clock frequency*2 FCLKPLL 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM4 Family PERIPHERAL MANUAL". (4-2) Operating Conditions of USB PLL (In the case of using main clock for input clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency USB clock frequency*2 Value Unit Min Typ Max tLOCK 100 - - μs FPLLI FPLLO 4 13 200 - 16 80 320 MHz multiplier MHz FCLKSPLL - - 48 MHz Remarks After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about USB clock, see "Chapter: USB Clock Generation" in "FM4 Family PERIPHERAL MANUAL Communication Macro Part". (4-3) Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 200 Μs (LOCK UP time) PLL input clock frequency FPLLI 3.8 4 4.2 MHz PLL multiplication rate 50 75 multiplier PLL macro oscillation clock frequency FPLLO 190 320 MHz 2 Main PLL clock frequency* FCLKPLL 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM4 Family PERIPHERAL MANUAL". Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed. (5) Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Reset input time Symbol Pin name Condition tINITX INITX - DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Value Min Max 500 - Unit Remarks ns 71 r1.0 MB9B560L Series (6) Power-on Reset Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Power supply rising time Power supply shut down time Time until releasing Power-on reset Value Pin name Tr Toff VCC Tprt Unit Min Max 0 - ms 1 - ms 0.33 0.60 ms Remarks VCC_minimum VCC VDL_minimum 0.2V 0.2V 0.2V Tr Tprt Internal RST Toff RST Active Release CPU Operation start Glossary ・ VCC_minimum : Minimum VCC of recommended operating conditions. ・ VDL_minimum : Minimum detection voltage of Low-Voltage detection reset. See "8. Low-Voltage Detection Characteristics". (7) GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Symbol Pin name Conditions tPCYCLE Pxx* VCC ≥ 4.5 V VCC < 4.5 V Value Min Max - 50 32 Unit MHz MHz *: GPIO is a target. Pxx tPCYCLE 72 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series (8) Base Timer Input Timing ・ Timer input timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS ・ Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see " BLOCK DIAGRAM" in this data sheet. DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 73 r1.0 MB9B560L Series (9) UART Timing ・ Synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Pin Symbol Conditions name Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time Notes: tF tR SCKx SCKx, SOTx Internal shift SCKx, clock operation SINx SCKx, SINx VCC < 4.5V Min Max VCC ≥ 4.5V Unit Min Max 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tCYCP 10 tCYCP + 10 SCKx, External shift SOTx clock SCKx, operation SINx SCKx, SINx SCKx SCKx - 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. 74 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL VIH VIL SIN MS bit = 0 tSLSH SCK VIH tF SOT SIN tSHSL VIL VIL VIH VIH tR tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 75 r1.0 MB9B560L Series ・ Synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time Notes: tF tR Conditions SCKx SCKx, SOTx Internal shift SCKx, clock operation SINx SCKx, SINx SCKx, SOTx External shift SCKx, clock operation SINx SCKx, SINx SCKx SCKx VCC < 4.5V Min Max VCC ≥ 4.5V Unit Min Max 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tCYCP 10 tCYCP + 10 - 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. 76 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK VIL tR SOT tSLSH VIH VIH VIL VIL tF tSHOVE VOH VOL tIVSLE VIH VIL SIN tSLIXE VIH VIL MS bit = 1 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 77 r1.0 MB9B560L Series ・ Synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Conditions name VCC < 4.5V Min Max VCC ≥ 4.5V Unit Min Max SCKx SCKx, SOTx SCKx, Internal shift SINx clock operation SCKx, SINx SCKx, SOTx 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns - ns Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time Notes: tF tR SCKx, SOTx External shift SCKx, clock operation SINx SCKx, SINx SCKx SCKx 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. 78 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK SOT VOL tSOVLI VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI VIH VIL MS bit = 0 tSLSH SCK VIH tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN VIH VIL tF * SOT VIL tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 79 r1.0 MB9B560L Series ・ Synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCKx SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time Notes: tF tR Conditions SCKx SCKx, SOTx SCKx, Internal shift SINx clock operation SCKx, SINx SCKx, SOTx SCKx, SOTx External shift SCKx, clock operation SINx SCKx, SINx SCKx SCKx VCC < 4.5V Min Max VCC ≥ Min 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns - ns 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 4.5V Unit Max - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. 80 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIH VIL tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 81 r1.0 MB9B560L Series ・ High-speed synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Symbol Pin name Serial clock cycle time tSCYC SCKx SCK↓→SOT delay time tSLOVI SCKx, SOTx SIN→SCK↑ setup time tIVSHI SCKx, SINx SCK↑→SIN hold time tSHIXI SCKx, SINx tSLSH SCKx tSHSL SCKx SCK↓→SOT delay time tSLOVE SCKx, SOTx SIN→SCK↑ setup time tIVSHE SCKx, SINx SCK↑→SIN hold time tSHIXE Parameter Serial clock "L" pulse width Serial clock "H" pulse width SCK falling time SCK rising time Notes: tF tR Conditions Internal shift clock operation VCC < 4.5V Min Max SCKx, SINx SCKx SCKx Unit 4tCYCP - 4tCYCP - ns - 10 + 10 - 10 + 10 ns 14 12.5* - 12.5 - ns 5 - 5 - ns - ns - ns 2tCYCP –5 tCYCP + 10 External shift clock operation VCC ≥ 4.5V Min Max - 2tCYCP –5 tCYCP + 10 - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the following pins.  No chip select : SIN0_1, SOT0_1, SCK0_1   Chip select : SIN6_0, SOT6_0, SCK6_0, SCS6_0  When the external load capacitance CL = 30pF. (For *, when CL = 10pF) 82 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL VIH VIL SIN MS bit = 0 tSLSH SCK VIH tF SOT SIN tSHSL VIL VIL VIH VIH tR tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 83 r1.0 MB9B560L Series ・ High-speed synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Symbol Pin name Serial clock cycle time tSCYC SCKx SCK↑→SOT delay time tSHOVI SCKx, SOTx SIN→SCK↓ setup time tIVSLI SCKx, SINx SCK↓→SIN hold time tSLIXI Serial clock "L" pulse width Parameter Conditions VCC < 4.5V Min Max VCC ≥ 4.5V Min Max Unit 4tCYCP - 4tCYCP - ns - 10 + 10 - 10 + 10 ns 14 12.5* - 12.5 - ns SCKx, SINx 5 - 5 - ns tSLSH SCKx 2tCYCP –5 - 2tCYCP –5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns tF tR SCKx SCKx - 5 5 - 5 5 ns ns SCK falling time SCK rising time Notes: Internal shift clock operation External shift clock operation  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the following pins.  No chip select : SIN0_1, SOT0_1, SCK0_1   Chip select : SIN6_0, SOT6_0, SCK6_0, SCS6_0  When the external load capacitance CL = 30pF. (For *, when CL = 10pF) 84 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK VIL tR SOT tSLSH VIH VIH VIL VIL tF tSHOVE VOH VOL tIVSLE VIH VIL SIN tSLIXE VIH VIL MS bit = 1 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 85 r1.0 MB9B560L Series ・ High-speed synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V Min Max VCC ≥ 4.5V Min Max Symbol Pin name Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 10 + 10 - 10 + 10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 14 12.5* - 12.5 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx 2tCYCP –5 - 2tCYCP –5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns tF tR SCKx SCKx - 5 5 - 5 5 ns ns Parameter SCK falling time SCK rising time Notes: Conditions Internal shift clock operation External shift clock operation Unit  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the following pins.  No chip select : SIN0_1, SOT0_1, SCK0_1   Chip select : SIN6_0, SOT6_0, SCK6_0, SCS6_0  When the external load capacitance CL = 30pF. (For *, when CL = 10pF) 86 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK SOT VOL tSOVLI VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI VIH VIL MS bit = 0 tSLSH SCK VIH tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN VIH VIL tF * SOT VIL tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 87 r1.0 MB9B560L Series ・ High-speed synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V Min Max VCC ≥ 4.5V Min Max Symbol Pin name Internal shift clock operation tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 10 + 10 - 10 + 10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 14 12.5* - 12.5 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx 2tCYCP –5 - 2tCYCP –5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns tF tR SCKx SCKx - 5 5 - 5 5 ns ns Parameter SCK falling time SCK rising time Notes: Conditions Internal shift clock operation External shift clock operation Unit  The above characteristics apply to CLK synchronous mode.  tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet.  These characteristics only guarantee the following pins.  No chip select : SIN0_1, SOT0_1, SCK0_1   Chip select : SIN6_0, SOT6_0, SCK6_0, SCS6_0  When the external load capacitance CL = 30pF. (For *, when CL = 10pF) 88 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIH VIL tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 89 r1.0 MB9B560L Series ・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓setup time SCK↑→SCS↑ hold time tCSSI tCSHI SCS deselect time tCSDI SCS↓→SCK↓setup time SCK↑→SCS↑ hold time SCS deselect time SCS↓→SOT delay time SCS↑→SOT delay time tCSSE tCSHE tCSDE tDSE tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V Min Max VCC ≥ 4.5V Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 (*2)+0 (*2)+20 (*2)+0 (*2)+20 (*3)-20 (*3)+20 (*3)-20 (*3)+20 +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15 3tCYCP+15 0 0 3tCYCP+15 3tCYCP+15 25 25 0 0 - Unit ns ns ns ns ns ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes:  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family PERIPHERAL MANUAL". When the external load capacitance CL = 30pF. 90 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series SCS output tCSDI tCSSI tCSHI tCSSE tCSHE SCK output SOT (SPI=0) SOT (SPI=1) SCS input tCSDE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 91 r1.0 MB9B560L Series ・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions SCS↓→SCK↑setup time SCK↓→SCS↑ hold time tCSSI tCSHI SCS deselect time tCSDI SCS↓→SCK↑setup time SCK↓→SCS↑ hold time SCS deselect time SCS↓→SOT delay time SCS↑→SOT delay time tCSSE tCSHE tCSDE tDSE tDEE Internal shift clock operation External shift clock operation VCC < 4.5V Min Max VCC ≥ 4.5V Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 (*2)+0 (*2)+20 (*2)+0 (*2)+20 (*3)-20 (*3)+20 (*3)-20 (*3)+20 +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15 3tCYCP+15 0 0 3tCYCP+15 3tCYCP+15 25 25 0 0 - Unit ns ns ns ns ns ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes:  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family PERIPHERAL MANUAL". When the external load capacitance CL = 30pF. 92 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series SCS output tCSDI tCSSI tCSHI SCK output SOT (SPI=0) SOT (SPI=1) SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 93 r1.0 MB9B560L Series ・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↓setup time SCK↑→SCS↓ hold time tCSSI tCSHI SCS deselect time tCSDI SCS↑→SCK↓setup time SCK↑→SCS↓ hold time SCS deselect time SCS↑→SOT delay time SCS↓→SOT delay time tCSSE tCSHE tCSDE tDSE tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V Min Max VCC ≥ 4.5V Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 (*2)+0 (*2)+20 (*2)+0 (*2)+20 (*3)-20 (*3)+20 (*3)-20 (*3)+20 +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15 3tCYCP+15 0 0 3tCYCP+15 3tCYCP+15 25 25 0 0 - Unit ns ns ns ns ns ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes:  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family PERIPHERAL MANUAL". When the external load capacitance CL = 30pF. 94 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tCSDI SCS output tCSSI tCSHI SCK output SOT (SPI=0) SOT (SPI=1) tCSDE SCS input tCSSE tCSHE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 95 r1.0 MB9B560L Series ・ When using high-speed synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions SCS↑→SCK↑setup time SCK↓→SCS↓ hold time tCSSI tCSHI SCS deselect time tCSDI SCS↑→SCK↑setup time SCK↓→SCS↓ hold time SCS deselect time SCS↑→SOT delay time SCS↓→SOT delay time tCSSE tCSHE tCSDE tDSE tDEE Internal shift clock operation External shift clock operation VCC < 4.5V Min Max VCC ≥ 4.5V Min Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 (*2)+0 (*2)+20 (*2)+0 (*2)+20 (*3)-20 (*3)+20 (*3)-20 (*3)+20 +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15 3tCYCP+15 0 0 3tCYCP+15 3tCYCP+15 25 25 0 0 - Unit ns ns ns ns ns ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes:  tCYCP indicates the APB bus clock cycle time.   About the APB bus number which UART is connected to, see "BLOCK DIAGRAM" in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family PERIPHERAL MANUAL". When the external load capacitance CL = 30pF. 96 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS709-00005-1v0-E r1.0 MB9B560L Series tCSDI SCS output tCSSI tCSHI SCK output SOT (SPI=0) SOT (SPI=1) SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 97 r1.0 MB9B560L Series ・ External clock (EXT = 1) : when in asynchronous mode only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock "L" pulse width Serial clock "H" pulse width SCK falling time SCK rising time tSLSH tSHSL tF tR tR SCK VIL Condition CL = 30pF Value Min Max tCYCP + 10 tCYCP + 10 - tSHSL VIH 98 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5 5 VIL Remarks ns ns ns ns tF tSLSH VIH Unit VIL VIH DS709-00005-1v0-E r1.0 MB9B560L Series (10) External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions Value Unit Min Max Remarks A/D converter trigger input 2tCYCP*1 ns Free-run timer input FRCKx clock Input pulse tINH, ICxx Input capture width tINL DTTIxX 2tCYCP*1 ns Waveform generator 2tCYCP + 100*1 ns INT00 to INT31, External interrupt, NMIX NMI 500*2 ns WKUPx 500*3 ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "BLOCK DIAGRAM" in this data sheet. *2: When in STOP mode, in timer mode. *3: When in deep standby RTC mode, in deep standby STOP mode. ADTG DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 99 r1.0 MB9B560L Series (11) Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Conditions Min Max AIN pin "H" width tAHL AIN pin "L" width tALL BIN pin "H" width tBHL BIN pin "L" width tBLL BIN rising time from PC_Mode2 or tAUBU AIN pin "H" level PC_Mode3 AIN falling time from PC_Mode2 or tBUAD BIN pin "H" level PC_Mode3 BIN falling time from PC_Mode2 or tADBD AIN pin "L" level PC_Mode3 AIN rising time from PC_Mode2 or tBDAU BIN pin "L" level PC_Mode3 AIN rising time from PC_Mode2 or tBUAU BIN pin "H" level PC_Mode3 2tCYCP* BIN falling time from PC_Mode2 or tAUBD AIN pin "H" level PC_Mode3 AIN falling time from PC_Mode2 or tBDAD BIN pin "L" level PC_Mode3 BIN rising time from PC_Mode2 or tADBU AIN pin "L" level PC_Mode3 ZIN pin "H" width tZHL QCR:CGSC="0" ZIN pin "L" width tZLL QCR:CGSC="0" AIN/BIN rising and falling time from determined ZIN tZABE QCR:CGSC="1" level Determined ZIN level from AIN/BIN rising and falling tABEZ QCR:CGSC="1" time * : tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "BLOCK DIAGRAM" in this data sheet. Unit ns tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL 100 FUJITSU SEMICONDUCTOR CONFIDENTIAL tBLL DS709-00005-1v0-E r1.0 MB9B560L Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN DS709-00005-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 101 r1.0 MB9B560L Series 2 (12) I C Timing ・Typical mode, high-speed mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock "L" width SCL clock "H" width (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between "STOP condition" and "START condition" Symbol Conditions Typical mode High-speed mode Min Max Unit Remarks Min Max FSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs tSUSTA 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs tHDDAT CL = 30pF, R = (Vp/IOL)*1 2MHz ≤ 2tCYCP*4 2tCYCP*4 ns tCYCP