The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
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4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9B560R Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the MB9B560R Series are highly integrated 32-bit microcontrollers with high performance and competitive cost.
®
®
This series is based on the ARM Cortex -M4F Processor with on-chip Flash memory and SRAM. The series has peripheral
2
functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN).
Features
®
®
32-bit ARM Cortex -M4F Core
[SRAM]
Processor version: r0p1
FPU built-in
This is composed of three independent SRAMs (SRAM0,
SRAM1, and SRAM2). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
Support DSP instruction
SRAM0: Up to 64 Kbytes
Memory Protection Unit (MPU): improves the reliability of an
SRAM1: Up to 32 Kbytes
Up to 160 MHz Frequency Operation
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
SRAM2: Up to 32 Kbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash, and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-bit Data width
Up to 25-bit Address bit
On-chip Memories
Maximum Access size: 256M byte
[Flash memory]
Supports Address/Data multiplex
These series are based on two independent on-chip Flash
memories.
MainFlash memory
to 1024 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
The read access to Flash memory can be achieved without
wait-cycle up to operation frequency of 72 MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
Supports external RDY function
Supports scramble function
Possible
to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
Up
WorkFlash memory
32
Kbytes
Read cycle:
• 6wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
• 4wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
Cypress Semiconductor Corporation
Document Number: 002-04864 Rev. *D
•
USB Interface
USB interface is composed of Device and Host.
[USB device]
USB2.0 Full-Speed supported
Max 6 Endpoint supported
198 Champion Court
Endpoint
0 is control transfer
1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
Endpoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
Endpoint 1 to 5 comprise Double Buffer
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64 bytes
• Endpoint 1: 256 bytes
Endpoint
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 25, 2017
MB9B560R Series
[USB host]
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
I2 C
Standard-mode
(Max 100 kbps) / Fast-mode (Max 400
kbps) supported
Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A
and ch.7=ch.B) supported
USB Device connected/dis-connected automatically detect
DMA Controller (Eight channels)
IN/OUT token handshake packet automatically
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
Max 256-byte packet-length supported
Wake-up function supported
CAN Interface (Max two channels)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Built-in 32 message buffer
Transfer data type: bytes/half-word/word
Multi-function Serial Interface (Max eight channels)
Transfer block count: 1 to 16
64 bytes with FIFO (the FIFO step numbers are variable
Number of transfers: 1 to 65536
depending on the settings of the communication mode or bit
length.)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
I C
UART
Full-duplex
double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
CSIO
Full-duplex
double buffer
dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 and ch.7 only)
Supports high-speed SPI (ch.4 and ch.6 only)
Data length 5 to 16-bit
Built-in
LIN
LIN
protocol Rev.2.1 supported
double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit
length)
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Full-duplex
Document Number: 002-04864 Rev. *D
DSTC (Descriptor System data Transfer Controller)
(128 channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor which has
already been constructed on the memory, can access directly
the memory /peripheral device and performs the data transfer
operation.
It supports the software activation, the hardware activation and
the chain activation functions.
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 3 units
Conversion time: 0.5 μs @ 5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4steps)
D/A Converter (Max two channels)
R-2R type
12-bit resolution
Page 2 of 170
MB9B560R Series
Base Timer (Max eight channels)
Real-time clock (RTC)
Operation mode is selectable from the followings for each
channel.
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
General Purpose I/O Port
Capable of rewriting the time with continuing the time count.
This series can use its pins as general purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated.
Leap year automatic count is available.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 100 high-speed general-purpose I/O ports @ 120 pin
Package
Some pin is 5 V tolerant I/O.
See 4. Pin Description and 5. I/O Circuit Type for the
corresponding pins.
Multi-function Timer (Max two units)
The Multi-function timer is composed of the following blocks.
Minimum resolution: 6.25 ns
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 6 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
PWM signal output function
Quadrature Position/Revolution Counter (QPRC)
(Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins AIN,
BIN, and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP.
Document Number: 002-04864 Rev. *D
Page 3 of 170
MB9B560R Series
CRC (Cyclic Redundancy Check) Accelerator
Low-power Consumption Mode
The CRC accelerator helps a verify data transmission or
storage integrity.
Six low-power consumption modes are supported.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
1-bit or 4-bit data bus
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
Clock and Reset
RTC
Clocks
32 kHz oscillation circuit
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main clock:
4 MHz to 48 MHz
Sub Clock:
32.768 kHz
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
Power-on circuit
Resets
Reset
requests from INITX pin
on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Power
Back up register: 32 bytes
Port circuit
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Clock Super Visor (CSV)
Three Power Supplies
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Wide range voltage:
External OSC clock failure (clock stop) is detected, reset is
Power supply for USB I/O:
asserted.
VCC
USBVCC = 3.0 V to 3.6 V (when USB is used)
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for VBAT:
VBAT
= 2.7 V to 5.5 V
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-04864 Rev. *D
Page 4 of 170
MB9B560R Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Description ................................................................................................................................................................ 15
4.1
List of Pin Numbers ..................................................................................................................................................... 15
4.2
List of Pin Functions .................................................................................................................................................... 28
5. I/O Circuit Type................................................................................................................................................................ 44
6. Handling Precautions ..................................................................................................................................................... 51
6.1
Precautions for Product Design ................................................................................................................................... 51
6.2
Precautions for Package Mounting .............................................................................................................................. 52
6.3
Precautions for Use Environment ................................................................................................................................ 53
7. Handling Devices ............................................................................................................................................................ 54
8. Block Diagram ................................................................................................................................................................. 57
9. Memory Size .................................................................................................................................................................... 58
10. Memory Map .................................................................................................................................................................... 58
11. Pin Status in Each CPU State ........................................................................................................................................ 61
12. Electrical Characteristics ............................................................................................................................................... 69
12.1 Absolute Maximum Ratings ......................................................................................................................................... 69
12.2 Recommended Operating Conditions.......................................................................................................................... 70
12.3 DC Characteristics....................................................................................................................................................... 74
12.3.1 Current Rating .............................................................................................................................................................. 74
12.3.2 Pin Characteristics ....................................................................................................................................................... 81
12.4 AC Characteristics ....................................................................................................................................................... 83
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 83
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 84
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 84
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 85
12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 85
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) 85
12.4.7 Reset Input Characteristics .......................................................................................................................................... 86
12.4.8 Power-on Reset Timing................................................................................................................................................ 86
12.4.9 GPIO Output Characteristics ........................................................................................................................................ 87
12.4.10 External Bus Timing.................................................................................................................................................. 87
12.4.11 Base Timer Input Timing......................................................................................................................................... 100
12.4.12 CSIO/UART Timing ................................................................................................................................................ 101
12.4.13 External Input Timing .............................................................................................................................................. 134
12.4.14 Quadrature Position/Revolution Counter Timing .................................................................................................... 135
2
12.4.15 I C Timing ............................................................................................................................................................... 137
12.4.16 SD Card Interface Timing ....................................................................................................................................... 139
12.4.17 ETM Timing ............................................................................................................................................................ 142
12.4.18 JTAG Timing ........................................................................................................................................................... 143
12.5 12-bit A/D Converter .................................................................................................................................................. 144
12.6 12-bit D/A Converter .................................................................................................................................................. 147
12.7 USB Characteristics .................................................................................................................................................. 148
12.8 Low-Voltage Detection Characteristics ...................................................................................................................... 152
12.8.1 Low-Voltage Detection Reset ..................................................................................................................................... 152
Document Number: 002-04864 Rev. *D
Page 5 of 170
MB9B560R Series
12.8.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 152
12.9 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 153
12.10 WorkFlash Memory Write/Erase Characteristics ....................................................................................................... 153
12.11 Standby Recovery Time ............................................................................................................................................ 154
12.11.1 Recovery cause: Interrupt/WKUP ........................................................................................................................... 154
12.11.2 Recovery Cause: Reset .......................................................................................................................................... 156
13. Ordering Information .................................................................................................................................................... 158
14. Package Dimensions .................................................................................................................................................... 159
15. Major Changes .............................................................................................................................................................. 166
Document History ............................................................................................................................................................... 168
Sales, Solutions, and Legal Information ........................................................................................................................... 170
Document Number: 002-04864 Rev. *D
Page 6 of 170
MB9B560R Series
1. Product Lineup
Memory Size
Product name
MainFlash memory
WorkFlash memory
On-chip SRAM
SRAM0
SRAM1
SRAM1
MB9BF566M/N/R
512 Kbytes
32 Kbytes
64 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
MB9BF567M/N/R
768 Kbytes
32 Kbytes
96 Kbytes
48 Kbytes
24 Kbytes
24 Kbytes
MB9BF568M/N/R
1024 Kbytes
32 Kbytes
128 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
Function
MB9BF566M
MB9BF567M
MB9BF568M
Product name
Pin count
80
100/112
Cortex-M4F, MPU, NVIC 128ch.
160 MHz
2.7 V to 5.5 V
1ch.
2ch. (Max)
8ch.
128ch.
Addr:25-bit (Max),
Addr:19-bit (Max),
R/W data: 8-/16-bit (Max),
R/W data: 8-bit (Max),
CS:9 (Max),
CS:5 (Max),
SRAM,
SRAM,
NOR Flash,
NOR Flash
SDRAM
CPU
Freq.
Power supply voltage range
USB2.0 (Device/Host)
CAN
DMAC
DSTC
External Bus Interface
MF Timer
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation compare
Input capture
Free-run timer
Output compare
Waveform generator
PPG
SD Card Interface
QPRC
Dual Timer
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog Timer
External Interrupts
I/O Ports
MB9BF566N
MB9BF567N
MB9BF568N
MB9BF566R
MB9BF567R
MB9BF568R
120/144
Addr:25-bit (Max),
R/W data: 8-/16-bit (Max),
CS:9 (Max),
SRAM,
NOR Flash,
NAND Flash, SDRAM
8ch. (Max)
8ch. (Max)
6ch.
4ch.
3ch.
6ch.
3ch.
3ch.
2 units (Max)
1 unit
2ch. (Max)
1 unit
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
16 pins (Max) + NMI × 1
63 pins (Max)
80 pins (Max)
12-bit A/D Converter
16ch. (3 units)
24ch. (3 units)
12-bit D/A Converter
2 units (Max)
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
Yes
2ch.
4 MHz
100 kHz
SWJ-DP/ETM
Yes
100 pins (Max)
Notes:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
−
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-04864 Rev. *D
Page 7 of 170
MB9B560R Series
2. Packages
Product Name
Package
LQFP: LQH080 (0.5 mm pitch)
LQFP: LQJ080 (0.65 mm pitch)
QFP: PQH100 (0.65 mm pitch)
LQFP: LQI100 (0.5 mm pitch)
LQFP: LQM120 (0.5 mm pitch)
BGA: LDC112 (0.5 mm pitch)
BGA: LDC144 (0.5 mm pitch)
MB9BF566M
MB9BF567M
MB9BF568M
MB9BF566N
MB9BF567N
MB9BF568N
-
-
MB9BF566R
MB9BF567R
MB9BF568R
: Supported
Note:
−
See 14. Package Dimensions for detailed information on each package.
Document Number: 002-04864 Rev. *D
Page 8 of 170
MB9B560R Series
3. Pin Assignment
LQH080/LQJ080
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P09/AN19/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
59
P21/AN17/SIN0_0/INT06_1
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
58
P22/CROUT_0/AN16/TIOB7_1/SOT0_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
57
P23/AN15/TIOA7_1/SCK0_0/RTO00_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
56
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
55
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
54
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
53
P18/AN08/SCK2_2/MAD15_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
9
52
AVRH
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
10
51
AVRL
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
11
50
AVSS
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
12
49
AVCC
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
13
48
P17/AN07/SOT2_2/WKUP3/MAD14_0
P3A/TIOA0_1/AIN0_0/RTO00_0
14
47
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3B/TIOA1_1/BIN0_0/RTO01_0
15
46
P15/AN05/SCK0_1/MAD12_0
P3C/TIOA2_1/ZIN0_0/RTO02_0
16
45
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3D/TIOA3_1/RTO03_0/MAD00_0
17
44
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3E/TIOA4_1/RTO04_0/MAD01_0
18
43
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3F/TIOA5_1/RTO05_0/MAD02_0
19
42
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
VSS
20
41
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/TIOA4_0/RTO14_1/DA0
P45/TIOB0_0/RTO15_1/DA1
INITX
P46/X0A
P47/X1A
P48/VREGCTL
P49/VWAKEUP
VBAT
C
VSS
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 80
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04864 Rev. *D
Page 9 of 170
MB9B560R Series
LQI100
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
74
P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
73
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
72
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
71
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
70
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
69
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
68
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
9
67
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
10
66
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
11
65
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
12
64
P18/AN08/SCK2_2/MAD15_0
P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0
13
63
AVRH
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0
14
62
AVRL
LQFP - 100
47
48
49
50
PE3/X1
VSS
46
PE0/MD1
MD0
45
PE2/X0
44
43
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
42
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
41
40
VSS
VCC
39
P4B/TIOB1_0/SCS7_1/MAD03_0
38
C
VCC
VBAT
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
51
37
52
25
P49/VWAKEUP
24
VSS
36
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
P3F/TIOA5_1/RTO05_0/MAD02_0
35
53
P47/X1A
23
P48/VREGCTL
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3E/TIOA4_1/RTO04_0/MAD01_0
34
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
54
P46/X0A
55
22
33
21
P3D/TIOA3_1/RTO03_0/MAD00_0
32
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
INITX
56
P45/TIOB0_0/RTO15_1/DA1
20
31
P15/AN05/SCK0_1/MAD12_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
P44/TIOA4_0/RTO14_1/DA0
P16/AN06/SIN2_2/INT14_1/MAD13_0
57
30
58
19
29
18
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
P42/TIOA2_0/RTO12_1/MSDWEX_0
P17/AN07/SOT2_2/WKUP3/MAD14_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
59
28
17
27
AVCC
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0
26
AVSS
60
VCC
61
16
P41/TIOA1_0/RTO11_1/INT13_1
15
P40/TIOA0_0/RTO10_1/INT12_1
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04864 Rev. *D
Page 10 of 170
MB9B560R Series
LQM120
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
93
92
91
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
96
95
94
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
98
99
97
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
101
100
P03/TMS/SWDIO
P04/TDO/SWO
103
102
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
106
105
104
P67/TIOA7_2/SOT3_0
P68/TIOB7_2/SCK3_0/INT00_2
VSS
109
108
107
P65/TIOB7_0/SCK5_1
P66/ADTG_8/SIN3_0/INT11_2
111
110
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/SIN5_1/INT03_0/S_CD_0/MWEX_0
P64/TIOA7_0/SOT5_1/INT10_2
114
113
112
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
117
116
115
VSS
P81/UDP0
P80/UDM0
120
119
118
(TOP VIEW)
VCC
1
90
VSS
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
2
89
P20/AN18/AIN1_1/INT05_0/MAD24_0
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
3
88
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
4
87
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
5
86
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
6
85
P24/RX1_0/SIN2_1/RTO01_1/INT01_2
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
7
84
P25/TX1_0/TIOA5_0/SOT2_1/RTO02_1
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
8
83
P26/TIOB5_0/SCK2_1/RTO03_1
P57/SCK6_0/MADATA07_0
9
82
P27/TIOA6_2/RTO04_1/INT02_2
P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0
10
81
P1F/ADTG_4/TIOB6_2/RTO05_1
P59/RX1_1/SOT4_2/BIN1_0/INT07_1/MADATA09_0
11
80
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P5A/TX1_1/SCK4_2/ZIN1_0/MADATA10_0
12
79
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P5B/CTS4_2/MADATA11_0
13
78
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0
14
77
P1B/AN11/SCK4_1/IC02_1/MAD18_0
76
P1A/AN10/SOT4_1/IC01_1/MAD17_0
75
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0
15
P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0
16
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0
17
74
P18/AN08/SCK2_2/MAD15_0
P34/TX0_1/TIOB4_1/FRCK0_0/MNALE_0
18
73
AVRH
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MNCLE_0
19
72
AVRL
LQFP - 120
58
59
60
VSS
MD0
PE2/X0
PE0/MD1
PE3/X1
55
56
57
P74/SCK2_0/DTTI1X_1
53
54
P73/TIOB6_0/SOT2_0/IC10_1/INT03_2
P70/TX0_0/TIOA4_2/AIN0_1/IC13_1
P71/RX0_0/TIOB4_2/BIN0_1/IC12_1/INT15_1
P72/TIOA6_0/SIN2_0/ZIN0_1/IC11_1/INT14_2
50
51
52
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
48
49
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
45
46
47
VSS
VCC
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
61
42
30
43
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
VSS
44
62
C
29
VBAT
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
P3F/TIOA5_1/RTO05_0/MAD02_0
P49/VWAKEUP
63
40
28
41
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
P3E/TIOA4_1/RTO04_0/MAD01_0
P47/X1A
64
P48/VREGCTL
27
37
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3D/TIOA3_1/RTO03_0/MAD00_0
38
P14/AN04/SOT0_1/IC03_2/MAD11_0
65
39
66
26
INITX
25
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
P46/X0A
P15/AN05/SCK0_1/MAD12_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
P45/TIOB0_0/RTO15_1/DA1
67
34
24
35
P16/AN06/SIN2_2/INT14_1/MAD13_0
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
36
68
P44/TIOA4_0/RTO14_1/DA0
23
P42/TIOA2_0/RTO12_1/MSDWEX_0
P17/AN07/SOT2_2/WKUP3/MAD14_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
69
31
22
32
AVCC
P38/SCK5_2/IC00_0/INT06_2
33
AVSS
70
VCC
71
21
P40/TIOA0_0/RTO10_1/INT12_1
20
P41/TIOA1_0/RTO11_1/INT13_1
P36/SIN5_2/IC02_0/INT09_1/MNWEX_0
P37/SOT5_2/IC01_0/INT05_2/MNREX_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04864 Rev. *D
Page 11 of 170
MB9B560R Series
PQH100
P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0
VCC
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0
P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0
P62/ADTG_3/TX0_2/SIN5_0/INT04_1/S_WP_0/MOEX_0
P63/CROUT_1/RX0_2/INT03_0/S_CD_0/MWEX_0
VSS
P00/TRSTX/MCSX7_0
P01/TCK/SWCLK
P02/TDI/MCSX6_0
P03/TMS/SWDIO
P04/TDO/SWO
P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0
P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0
P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0
P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0
P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0
P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0
P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0
P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0
P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0
P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0
VCC
VSS
P20/AN18/AIN1_1/INT05_0/MAD24_0
P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0
81
50
P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1
P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0
82
49
P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0
P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0
83
48
P1E/AN14/ADTG_5/FRCK0_1/MAD21_0
P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0
84
47
P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0
P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0
85
46
P1C/AN12/CTS4_1/IC03_1/MAD19_0
P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0
86
45
P1B/AN11/SCK4_1/IC02_1/MAD18_0
P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0
87
44
P1A/AN10/SOT4_1/IC01_1/MAD17_0
P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0
88
43
P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0
P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0
89
42
P18/AN08/SCK2_2/MAD15_0
P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0
90
41
AVRH
P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0
91
40
AVRL
P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0
92
39
AVSS
QFP - 100
20
21
22
23
24
25
26
27
28
29
30
P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0
P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0
19
VCC
P4B/TIOB1_0/SCS7_1/MAD03_0
18
P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0
17
16
VBAT
C
15
VSS
14
13
P47/X1A
P48/VREGCTL
12
P49/VWAKEUP
11
INITX
P46/X0A
10
P45/TIOB0_0/RTO15_1/DA1
P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0
9
P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0
31
8
32
P44/TIOA4_0/RTO14_1/DA0
99
P3D/TIOA3_1/RTO03_0/MAD00_0 100
7
P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0
P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0
P42/TIOA2_0/RTO12_1/MSDWEX_0
33
P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0
98
6
P14/AN04/SOT0_1/IC03_2/MAD11_0
P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0
P41/TIOA1_0/RTO11_1/INT13_1
P15/AN05/SCK0_1/MAD12_0
34
5
35
97
4
96
P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0
VCC
P16/AN06/SIN2_2/INT14_1/MAD13_0
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0
P40/TIOA0_0/RTO10_1/INT12_1
36
3
95
2
P17/AN07/SOT2_2/WKUP3/MAD14_0
P38/SCK5_2/IC00_0/INT06_2/MADATA15_0
1
AVCC
37
VSS
38
94
P3F/TIOA5_1/RTO05_0/MAD02_0
93
P3E/TIOA4_1/RTO04_0/MAD01_0
P36/SIN5_2/IC02_0/INT09_1/MADATA13_0
P37/SOT5_2/IC01_0/INT05_2/MADATA14_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04864 Rev. *D
Page 12 of 170
MB9B560R Series
LDC112
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
UDP0
UDM0
USBVCC
VSS
TCK/
SWCLK
VSS
AN21
P0A
P0B
VSS
P0E
VSS
B
VCC
VSS
P60
P61
P62
TRSTX SWDIO
AN22
AN19
P0C
P0D
VSS
VCC
C
P50
P51
P52
AN23
AN20
VSS
AN18
AN17
D
P53
P54
AN16
AN15
E
P55
P56
P30
AN14
AN13
AVRH
F
P31
P32
P33
AN12
AN11
AVRL
G
P34
P35
P36
AN10
AN09
AVSS
H
VSS
P37
P38
AN08
AN07
AVCC
J
P39
P3A
P3B
AN06
AN05
AN04
K
P3C
P3D
AN03
AN02
L
P3E
P3F
P43
VSS
AN01
AN00
M
VCC
VSS
P42
N
VSS
P40
P41
P63
TMS/
TDI
TDO/
SWO
index
P45
P48
P4B
P4C
P4E
P44
VSS
INITX
P49
VCC
P4D
MD1
MD0
VSS
VCC
VSS
X0A
X1A
VSS
VBAT
C
VSS
X0
X1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04864 Rev. *D
Page 13 of 170
MB9B560R Series
LDC144
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
UDP0
UDM0
USBVCC
VSS
P66
VSS
VSS
AN21
VSS
P0C
VCC
VSS
B
VCC
VSS
P60
P61
P63
P67
TCK/
SWCLK
TDO/
SWO
AN20
P0B
VSS
VSS
P0E
C
P50
P51
VSS
P62
P64
P68
TDI
AN23
AN19
P0D
VSS
AN18
VSS
D
P52
P53
P54
VSS
P65
AN22
P0A
VSS
AN17
AN16
AN15
E
P55
P56
P57
P58
index
P24
P25
P26
P27
F
P59
P5A
P5B
P30
P1F
AN14
AN13
AN12
G
P31
P32
P33
P34
AN11
AN10
AN09
AVRH
H
P35
P36
P37
P38
AN08
AN07
AN06
AVRL
J
P39
P3A
P3B
P3C
AN05
AN04
AN03
AVSS
K
VSS
P3D
P3E
VSS
P45
P49
P4C
P70
P72
VSS
AN02
AN01
AVCC
L
P3F
P41
VSS
P44
VSS
P48
P4B
P4E
P71
P74
VSS
AN00
VSS
M
VCC
VSS
P43
VSS
X1A
VSS
VSS
P4D
VCC
P73
MD0
VSS
VCC
N
VSS
P40
P42
INITX
X0A
VSS
VBAT
C
VSS
MD1
X0
X1
VSS
TMS/
TRSTX SWDIO
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04864 Rev. *D
Page 14 of 170
MB9B560R Series
4. Pin Description
4.1
List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
I/O
Circuit
Type
Pin No
LQFP120
1
LQFP100
1
LQFP80
1
QFP100
BGA112
BGA144
79
B1
B1
Pin Name
VCC
-
Pin State
Type
-
P50
CTS4_0
AIN0_2
2
2
2
80
C1
C1
RTO10_0
(PPG10_0)
E
K
E
K
E
I
E
I
E
K
INT00_0
MADATA00_0
P51
RTS4_0
BIN0_2
3
3
3
81
C2
C2
RTO11_0
(PPG10_0)
INT01_0
MADATA01_0
P52
SCK4_0
(SCL4_0)
4
4
4
82
C3
D1
ZIN0_2
RTO12_0
(PPG12_0)
MADATA02_0
P53
TIOA1_2
5
5
5
83
D1
D2
SOT4_0
(SDA4_0)
RTO13_0
(PPG12_0)
MADATA03_0
P54
TIOB1_2
SIN4_0
6
6
6
84
D2
D3
RTO14_0
(PPG14_0)
INT02_0
MADATA04_0
Document Number: 002-04864 Rev. *D
Page 15 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
E
K
E
K
E
I
E
K
E
K
E
I
E
I
E
Q
P55
ADTG_1
SIN6_0
7
7
7
85
E1
E1
RTO15_0
(PPG14_0)
INT07_2
MADATA05_0
P56
8
8
8
86
E2
E2
SOT6_0
(SDA6_0)
DTTI1X_0
INT08_2
MADATA06_0
P57
9
-
-
-
-
E3
SCK6_0
(SCL6_0)
MADATA07_0
P58
SIN4_2
10
-
-
-
-
E4
AIN1_0
INT04_2
MADATA08_0
P59
RX1_1
11
-
-
-
-
F1
SOT4_2
(SDA4_2)
BIN1_0
INT07_1
MADATA09_0
P5A
TX1_1
12
-
-
-
-
F2
SCK4_2
(SCL4_2)
ZIN1_0
MADATA10_0
P5B
13
-
-
-
-
F3
CTS4_2
MADATA11_0
P30
TIOB0_1
14
9
9
87
E3
F4
RTS4_2
INT15_2
14
-
-
Document Number: 002-04864 Rev. *D
-
-
F4
WKUP1
MADATA07_0
MADATA12_0
Page 16 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
I
K
N
K
N
K
E
I
E
K
E
K
E
K
P31
15
10
10
88
F1
G1
TIOB1_1
SIN3_1
INT09_2
15
-
-
-
-
-
MADATA08_0
G1
MADATA13_0
P32
TIOB2_1
16
16
11
-
11
-
89
-
F2
-
G2
G2
SOT3_1
(SDA3_1)
INT10_1
MADATA09_0
MADATA14_0
P33
ADTG_6
17
17
18
18
12
12
90
F3
-
-
-
-
13
-
91
G1
-
-
-
-
G3
TIOB3_1
SCK3_1
(SCL3_1)
G3
G4
G4
INT04_0
MADATA10_0
MADATA15_0
P34
TX0_1
TIOB4_1
FRCK0_0
MADATA11_0
MNALE_0
P35
RX0_1
19
14
-
92
G2
H1
TIOB5_1
IC03_0
19
20
20
21
-
-
-
-
15
-
93
G3
-
16
-
-
-
94
-
H2
H1
H2
H2
H3
INT08_1
MADATA12_0
MNCLE_0
P36
SIN5_2
IC02_0
INT09_1
MADATA13_0
MNWEX_0
P37
SOT5_2
(SDA5_2)
IC01_0
21
-
-
Document Number: 002-04864 Rev. *D
-
-
H3
INT05_2
MADATA14_0
MNREX_0
Page 17 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
E
K
L
I
G
I
G
I
G
I
G
I
G
I
G
I
-
-
P38
22
17
-
95
H3
H4
SCK5_2
(SCL5_2)
IC00_0
-
-
INT06_2
MADATA15_0
P39
ADTG_2
23
18
13
96
J1
J1
DTTI0X_0
RTCCO_2
SUBOUT_2
-
MSDCLK_0
P3A
TIOA0_1
24
19
14
97
J2
J2
AIN0_0
RTO00_0
(PPG00_0)
-
MSDCKE_0
P3B
TIOA1_1
25
20
15
98
J3
J3
BIN0_0
RTO01_0
(PPG00_0)
-
MRASX_0
P3C
TIOA2_1
26
21
16
99
K1
J4
ZIN0_0
RTO02_0
(PPG02_0)
-
MCASX_0
P3D
TIOA3_1
27
22
17
100
K2
K2
RTO03_0
(PPG02_0)
MAD00_0
P3E
TIOA4_1
28
23
18
1
L1
K3
RTO04_0
(PPG04_0)
MAD01_0
P3F
TIOA5_1
29
24
19
2
L2
L1
30
25
20
3
N1
N1
VSS
31
26
-
4
M1
M1
VCC
RTO05_0
(PPG04_0)
MAD02_0
Document Number: 002-04864 Rev. *D
Page 18 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
G
K
G
K
G
I
G
I
R
J
R
J
B
C
P
S
Q
T
O
U
O
U
-
-
E
I
P40
TIOA0_0
32
27
-
5
N2
N2
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
33
28
-
6
N3
L2
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
34
29
-
7
M3
N3
RTO12_1
(PPG12_1)
MSDWEX_0
P43
ADTG_7
35
30
-
8
L3
M3
TIOA3_0
RTO13_1
(PPG12_1)
MCSX8_0
P44
TIOA4_0
36
31
21
9
M4
L4
RTO14_1
(PPG14_1)
DA0
P45
TIOB0_0
37
32
22
10
L5
K5
38
33
23
11
M6
N4
RTO15_1
(PPG14_1)
DA1
INITX
P46
39
34
24
12
N5
N5
40
35
25
13
N6
M5
41
36
26
14
L6
L6
42
37
27
15
M7
K6
43
38
28
16
N8
N7
VBAT
44
39
29
17
N9
N8
C
45
40
30
18
N10
N9
VSS
46
41
31
19
M8
M9
VCC
X0A
P47
X1A
P48
VREGCTL
P49
VWAKEUP
P4B
47
42
32
20
L7
L7
TIOB1_0
SCS7_1
MAD03_0
Document Number: 002-04864 Rev. *D
Page 19 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
N
I
N
K
I
Q
E
I
E
K
E
K
E
K
E
I
P4C
TIOB2_0
48
43
33
21
L8
K7
SCK7_1
(SCL7_1)
AIN1_2
MAD04_0
P4D
TIOB3_0
49
44
34
22
M9
M8
SOT7_1
(SDA7_1)
BIN1_2
INT13_2
MAD05_0
P4E
TIOB4_0
SIN7_1
50
45
35
23
L9
L8
ZIN1_2
FRCK1_1
INT11_1
WKUP2
MAD06_0
P70
TX0_0
51
-
-
-
-
K8
TIOA4_2
AIN0_1
IC13_1
P71
RX0_0
52
-
-
-
-
L9
TIOB4_2
BIN0_1
IC12_1
INT15_1
P72
TIOA6_0
53
-
-
-
-
K9
SIN2_0
ZIN0_1
IC11_1
INT14_2
P73
TIOB6_0
54
-
-
-
-
M10
SOT2_0
(SDA2_0)
IC10_1
INT03_2
P74
55
-
-
-
-
L10
SCK2_0
(SCL2_0)
DTTI1X_1
Document Number: 002-04864 Rev. *D
Page 20 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
56
46
36
24
M10
N10
57
47
37
25
M11
M11
Pin Name
PE0
MD1
MD0
PE2
58
48
38
26
N11
N11
59
49
39
27
N12
N12
60
50
40
28
N13
N13
VSS
61
51
-
29
M13
M13
VCC
X0
PE3
X1
I/O
Circuit
Type
Pin State
Type
C
E
J
D
A
A
A
B
-
-
F
M
F
L
F
L
F
M
F
L
F
L
P10
AN00
RX1_2
62
52
41
30
L13
L12
SIN1_1
FRCK0_2
INT02_1
MAD07_0
P11
AN01
TX1_2
63
53
42
31
L12
K12
SOT1_1
(SDA1_1)
IC00_2
MAD08_0
P12
AN02
SCK1_1
(SCL1_1)
64
54
43
32
K13
K11
IC01_2
RTCCO_1
SUBOUT_1
MAD09_0
P13
AN03
65
55
44
33
K12
J12
SIN0_1
IC02_2
INT03_1
MAD10_0
P14
AN04
66
56
45
34
J13
J11
SOT0_1
(SDA0_1)
IC03_2
MAD11_0
P15
AN05
67
57
46
35
J12
J10
SCK0_1
(SCL0_1)
MAD12_0
Document Number: 002-04864 Rev. *D
Page 21 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
F
M
F
P
-
-
F
L
F
M
M
L
M
L
F
L
F
L
P16
AN06
68
58
47
36
J11
H12
SIN2_2
INT14_1
MAD13_0
P17
AN07
69
59
48
37
H12
H11
SOT2_2
(SDA2_2)
WKUP3
MAD14_0
70
60
49
38
H13
K13
AVCC
71
61
50
39
G13
J13
AVSS
72
62
51
40
F13
H13
AVRL
73
63
52
41
E13
G13
AVRH
P18
AN08
74
64
53
42
H11
H10
SCK2_2
(SCL2_2)
MAD15_0
P19
AN09
75
65
54
43
G12
G12
SIN4_1
IC00_1
INT05_1
MAD16_0
P1A
AN10
76
66
55
44
G11
G11
SOT4_1
(SDA4_1)
IC01_1
MAD17_0
P1B
AN11
77
67
56
45
F12
G10
SCK4_1
(SCL4_1)
IC02_1
MAD18_0
P1C
AN12
78
68
-
46
F11
F13
CTS4_1
IC03_1
MAD19_0
P1D
AN13
79
69
-
47
E12
F12
RTS4_1
DTTI0X_1
MAD20_0
Document Number: 002-04864 Rev. *D
Page 22 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
F
L
E
I
E
K
E
I
E
I
E
K
F
L
P1E
AN14
80
70
-
48
E11
F11
ADTG_5
FRCK0_1
MAD21_0
P1F
ADTG_4
81
-
-
-
-
F10
TIOB6_2
RTO05_1
(PPG04_1)
P27
TIOA6_2
82
-
-
-
-
E13
RTO04_1
(PPG04_1)
INT02_2
P26
TIOB5_0
83
-
-
-
-
E12
SCK2_1
(SCL2_1)
RTO03_1
(PPG02_1)
P25
TX1_0
TIOA5_0
84
-
-
-
-
E11
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
P24
RX1_0
85
-
-
-
-
E10
SIN2_1
RTO01_1
(PPG00_1)
INT01_2
P23
AN15
TIOA7_1
86
71
57
49
D13
D13
SCK0_0
(SCL0_0)
RTO00_1
(PPG00_1)
-
Document Number: 002-04864 Rev. *D
MAD22_0
Page 23 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
F
L
F
M
F
M
-
-
L
I
L
I
L
I
L
K
P22
CROUT_0
87
72
58
AN16
50
D12
D12
TIOB7_1
SOT0_0
(SDA0_0)
-
ZIN1_1
P21
59
88
73
-
AN17
51
C13
D11
SIN0_0
BIN1_1
59
INT06_1
-
MAD23_0
P20
AN18
89
74
-
52
C12
C12
AIN1_1
INT05_0
MAD24_0
90
75
60
53
A13
A13
VSS
91
76
61
54
B13
A12
VCC
P0E
TIOB5_2
92
77
62
55
A12
B13
SCS6_1
IC13_0
S_CLK_0
MDQM1_0
P0D
TIOA5_2
93
78
63
56
B11
C10
SCK6_1
(SCL6_1)
IC12_0
S_CMD_0
MDQM0_0
P0C
TIOA6_1
94
79
64
57
B10
A11
SOT6_1
(SDA6_1)
IC11_0
S_DATA1_0
MALE_0
P0B
TIOB6_1
SIN6_1
95
80
65
58
A10
B10
IC10_0
INT00_1
S_DATA0_0
MCSX0_0
Document Number: 002-04864 Rev. *D
Page 24 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
L
K
M
N
F
N
F
N
F
N
F
O
E
G
E
G
P0A
SIN1_0
96
81
66
59
A9
D9
FRCK1_0
INT12_2
S_DATA3_0
MCSX1_0
P09
67
AN19
97
82
TRACED0
60
B9
C9
TIOA3_2
SOT1_0
(SDA1_0)
67
S_DATA2_0
MCSX5_0
P08
AN20
TRACED1
98
83
-
61
C9
B9
TIOB3_2
SCK1_0
(SCL1_0)
MCSX4_0
P07
AN21
TRACED2
99
84
-
62
A8
A9
TIOA0_2
SCK7_0
(SCL7_0)
MCLKOUT_0
P06
AN22
TRACED3
100
85
-
63
B8
D8
TIOB0_2
SOT7_0
(SDA7_0)
MCSX3_0
P05
AN23
ADTG_0
101
86
-
64
C8
C8
TRACECLK
SIN7_0
INT01_1
MCSX2_0
P04
102
87
68
65
C7
B8
TDO
SWO
P03
103
88
69
66
B7
D7
TMS
SWDIO
Document Number: 002-04864 Rev. *D
Page 25 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
BGA144
89
70
67
C6
C7
Pin Name
I/O
Circuit
Type
Pin State
Type
E
H
E
G
E
H
-
-
E
K
E
I
E
K
E
I
E
K
E
K
I
K
P02
104
TDI
MCSX6_0
P01
105
90
71
68
A6
B7
TCK
SWCLK
P00
106
91
72
69
B6
D6
TRSTX
MCSX7_0
107
92
-
70
A5
A7
VSS
P68
TIOB7_2
108
-
-
-
-
C6
SCK3_0
(SCL3_0)
INT00_2
P67
109
-
-
-
-
B6
TIOA7_2
SOT3_0
(SDA3_0)
P66
110
-
-
-
-
A6
ADTG_8
SIN3_0
INT11_2
P65
111
-
-
-
-
D5
TIOB7_0
SCK5_1
(SCL5_1)
P64
TIOA7_0
112
-
-
-
-
C5
SOT5_1
(SDA5_1)
INT10_2
P63
93
73
71
C5
-
-
-
-
CROUT_1
RX0_2
113
B5
SIN5_1
INT03_0
93
73
71
C5
S_CD_0
MWEX_0
P62
ADTG_3
TX0_2
114
94
74
72
B5
C4
SIN5_0
INT04_1
S_WP_0
MOEX_0
Document Number: 002-04864 Rev. *D
Page 26 of 170
MB9B560R Series
Pin No
LQFP120
LQFP100
LQFP80
QFP100
BGA112
Pin Name
BGA144
I/O
Circuit
Type
Pin State
Type
E
I
I
F
-
-
H
R
H
R
-
-
P61
UHCONX0
TIOB2_2
115
95
75
73
B4
B4
SOT5_0
(SDA5_0)
RTCCO_0
SUBOUT_0
P60
TIOA2_2
116
96
76
74
B3
B3
SCK5_0
(SCL5_0)
NMIX
WKUP0
MRDY_0
117
97
77
75
A4
A4
118
98
78
76
A3
A3
119
99
79
77
A2
A2
120
100
80
78
A1
A1
-
-
-
-
A7
A5
-
-
-
-
B2
A8
-
-
-
-
B12
A10
-
-
-
-
C11
B2
-
-
-
-
H1
B11
-
-
-
-
N4
B12
-
-
-
-
M5
C3
-
-
-
-
N7
C11
-
-
-
-
L11
C13
-
-
-
-
A11
D4
-
-
-
-
M12
D10
-
-
-
-
M2
K1
-
-
-
-
-
K4
-
-
-
-
-
K10
-
-
-
-
-
L3
-
-
-
-
-
L5
-
-
-
-
-
L11
-
-
-
-
-
L13
-
-
-
-
-
M2
-
-
-
-
-
M4
-
-
-
-
-
M6
-
-
-
-
-
M7
-
-
-
-
-
M12
-
-
-
-
-
N6
Document Number: 002-04864 Rev. *D
USBVCC
P80
UDM0
P81
UDP0
VSS
VSS
Page 27 of 170
MB9B560R Series
4.2
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Pin
Function
ADC
Base Timer
0
Pin Name
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
Function Description
A/D converter external trigger input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Document Number: 002-04864 Rev. *D
LQFP
120
101
7
23
114
81
80
17
35
110
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
86
87
88
89
97
98
99
100
101
32
24
99
37
14
100
LQFP
100
LQFP
80
86
7
18
94
70
12
30
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
86
27
19
84
32
9
85
7
13
74
12
41
42
43
44
45
46
47
48
53
54
55
56
57
58
59
67
14
22
9
-
QFP
100
64
85
96
72
48
90
8
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
49
50
51
52
60
61
62
63
64
5
97
62
10
87
63
BGA
112
C8
E1
J1
B5
E11
F3
L3
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
D13
D12
C13
C12
B9
C9
A8
B8
C8
N2
J2
A8
L5
E3
B8
BGA
144
C8
E1
J1
C4
F10
F11
G3
M3
A6
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
D13
D12
D11
C12
C9
B9
A9
D8
C8
N2
J2
A9
K5
F4
D8
Page 28 of 170
MB9B560R Series
Pin
Function
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base Timer
5
Base Timer
6
Base Timer
7
CAN 0
CAN 1
Pin Name
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
TX0_0
TX0_1
TX0_2
RX0_0
RX0_1
RX0_2
TX1_0
TX1_1
TX1_2
RX1_0
RX1_1
RX1_2
Function Description
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
CAN interface ch.0 TX output pin
CAN interface ch.0 RX output pin
CAN interface ch.1 TX output pin
CAN interface ch.1 RX output pin
Document Number: 002-04864 Rev. *D
LQFP
120
33
25
5
47
15
6
34
26
116
48
16
115
35
27
97
49
17
98
36
28
51
50
18
52
84
29
93
83
19
92
53
94
82
54
95
81
112
86
109
111
87
108
51
18
114
52
19
113
84
12
63
85
11
62
LQFP
100
28
20
5
42
10
6
29
21
96
43
11
95
30
22
82
44
12
83
31
23
45
13
24
78
14
77
79
80
71
72
13
94
14
93
53
52
Pin No
LQFP
QFP
80
100
BGA
112
15
5
32
10
6
16
76
33
11
75
17
67
34
12
21
18
35
19
63
62
64
65
57
58
74
73
42
41
N3
J3
D1
L7
F1
D2
M3
K1
B3
L8
F2
B4
L3
K2
B9
M9
F3
C9
M4
L1
L9
G1
L2
B11
G2
A12
B10
A10
D13
D12
G1
B5
G2
C5
L12
L13
6
98
83
20
88
84
7
99
74
21
89
73
8
100
60
22
90
61
9
1
23
91
2
56
92
55
57
58
49
50
91
72
92
71
31
30
BGA
144
L2
J3
D2
L7
G1
D3
N3
J4
B3
K7
G2
B4
M3
K2
C9
M8
G3
B9
L4
K3
K8
L8
G4
L9
E11
L1
C10
E12
H1
B13
K9
A11
E13
M10
B10
F10
C5
D13
B6
D5
D12
C6
K8
G4
C4
L9
H1
B5
E11
F2
K12
E10
F1
L12
Page 29 of 170
MB9B560R Series
Pin
Function
Pin Name
SWCLK
SWDIO
Debugger
External
Bus
SWO
TCK
TDI
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
Function Description
Serial wire debug interface clock input
pin
Serial wire debug interface data input /
output pin
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
Trace CLK output pin of ETM
Trace data output pin of ETM
JTAG test reset input pin
External bus interface address bus
Document Number: 002-04864 Rev. *D
LQFP
120
LQFP
100
Pin No
LQFP
QFP
80
100
BGA
112
BGA
144
105
90
71
68
A6
B7
103
88
69
66
B7
D7
102
105
104
102
103
101
97
98
99
100
106
27
28
29
47
48
49
50
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
86
88
89
87
90
89
87
88
86
82
83
84
85
91
22
23
24
42
43
44
45
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
71
73
74
68
71
70
68
69
72
17
18
19
32
33
34
35
41
42
43
44
45
46
47
48
53
54
55
56
-
65
68
67
65
66
64
60
61
62
63
69
100
1
2
20
21
22
23
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
49
51
52
C7
A6
C6
C7
B7
C8
B9
C9
A8
B8
B6
K2
L1
L2
L7
L8
M9
L9
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
D13
C13
C12
B8
B7
C7
B8
D7
C8
C9
B9
A9
D8
D6
K2
K3
L1
L7
K7
M8
L8
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
D13
D11
C12
Page 30 of 170
MB9B560R Series
Pin
Function
External
Bus
Pin Name
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MCSX8_0
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MDQM0_0
MDQM1_0
MALE_0
MRDY_0
MCLKOUT_0
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
MWEX_0
Function Description
External bus interface chip select
output pin
External bus interface data bus
(Address / data multiplex bus)
External bus interface byte mask signal
output pin
External bus interface Address Latch
enable output signal for multiplex
External bus interface external RDY
input signal
External bus interface external clock
output pin
External bus interface ALE signal to
control NAND Flash output pin
External bus interface CLE signal to
control NAND Flash output pin
External bus interface read enable
signal to control NAND Flash
External bus interface write enable
signal to control NAND Flash
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
Document Number: 002-04864 Rev. *D
LQFP
120
LQFP
100
Pin No
LQFP QFP
80
100
BGA
112
BGA
144
95
96
101
100
98
97
104
106
35
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
93
92
80
81
86
85
83
82
89
91
30
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
78
77
65
66
67
70
72
2
3
4
5
6
7
8
9
10
11
12
63
62
58
59
64
63
61
60
67
69
8
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
56
55
A10
A9
C8
B8
C9
B9
C6
B6
L3
C1
C2
C3
D1
D2
E1
E2
E3
F1
F2
F3
G1
G2
G3
H2
H3
B11
A12
B10
D9
C8
D8
B9
C9
C7
D6
M3
C1
C2
D1
D2
D3
E1
E2
E3
E4
F1
F2
F3
F4
G1
G2
G3
C10
B13
94
79
64
57
B10
A11
116
96
76
74
B3
B3
99
84
-
62
A8
A9
18
-
-
-
-
G4
19
-
-
-
-
H1
21
-
-
-
-
H3
20
-
-
-
-
H2
114
94
74
72
B5
C4
113
93
73
71
C5
B5
Page 31 of 170
MB9B560R Series
Pin
Function
Pin Name
MSDCLK_0
MSDCKE_0
External
Bus
MRASX_0
MCASX_0
MSDWEX_0
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_1
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
Function Description
SDRAM interface
SDRAM clock output pin
SDRAM interface
SDRAM clock enable pin
SDRAM interface
SDRAM row address strobe pin
SDRAM interface
SDRAM column address strobe pin
SDRAM interface
SDRAM write enable pin
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
Document Number: 002-04864 Rev. *D
LQFP
100
Pin No
LQFP
QFP
80
100
23
18
-
96
J1
J1
24
19
-
97
J2
J2
25
20
-
98
J3
J3
26
21
-
99
K1
J4
34
29
-
7
M3
N3
2
95
108
3
101
85
6
62
82
113
65
54
17
114
10
89
75
21
88
22
11
7
19
8
20
15
16
112
50
110
32
96
33
49
68
53
52
14
2
80
3
86
6
52
93
55
12
94
74
65
16
73
17
7
14
8
15
10
11
45
27
81
28
44
58
9
2
65
3
6
41
73
44
12
74
54
59
7
8
10
11
35
66
34
47
9
80
58
81
64
84
30
71
33
90
72
52
43
94
51
95
85
92
86
93
88
89
23
5
59
6
22
36
87
C1
A10
C2
C8
D2
L13
C5
K12
F3
B5
C12
G12
H2
C13
H3
E1
G2
E2
G3
F1
F2
L9
N2
A9
N3
M9
J11
E3
C1
B10
C6
C2
C8
E10
D3
L12
E13
B5
J12
M10
G3
C4
E4
C12
G12
H3
D11
H4
F1
E1
H1
E2
H2
G1
G2
C5
L8
A6
N2
D9
L2
M8
H12
K9
L9
F4
LQFP
120
BGA
112
BGA
144
Page 32 of 170
MB9B560R Series
Pin
Function
Pin Name
External
Interrupt
NMIX
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
Function Description
Non-Maskable Interrupt input pin
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Document Number: 002-04864 Rev. *D
LQFP
100
Pin No
LQFP
QFP
80
100
BGA
112
BGA
144
116
96
76
74
B3
B3
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
62
63
64
65
66
67
68
69
74
75
76
77
78
79
80
81
89
88
87
86
85
84
83
82
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
74
73
72
71
-
72
71
70
69
68
67
66
65
64
63
62
41
42
43
44
45
46
47
48
53
54
55
56
59
58
57
-
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
52
51
50
49
-
B6
A6
C6
B7
C7
C8
B8
A8
C9
B9
A9
A10
B10
B11
A12
L13
L12
K13
K12
J13
J12
J11
H12
H11
G12
G11
F12
F11
E12
E11
C12
C13
D12
D13
-
D6
B7
C7
D7
B8
C8
D8
A9
B9
C9
D9
B10
A11
C10
B13
L12
K12
K11
J12
J11
J10
H12
H11
H10
G12
G11
G10
F13
F12
F11
F10
C12
D11
D12
D13
E10
E11
E12
E13
LQFP
120
Page 33 of 170
MB9B560R Series
Pin
Function
GPIO
Pin Name
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
Function Description
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
Document Number: 002-04864 Rev. *D
LQFP
120
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
39
40
41
42
47
48
49
50
2
3
4
5
6
7
8
9
10
11
12
13
LQFP
100
Pin No
LQFP
QFP
80
100
BGA
112
BGA
144
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
34
35
36
37
42
43
44
45
2
3
4
5
6
7
8
-
9
10
11
12
13
14
15
16
17
18
19
21
22
24
25
26
27
32
33
34
35
2
3
4
5
6
7
8
-
E3
F1
F2
F3
G1
G2
G3
H2
H3
J1
J2
J3
K1
K2
L1
L2
N2
N3
M3
L3
M4
L5
N5
N6
L6
M7
L7
L8
M9
L9
C1
C2
C3
D1
D2
E1
E2
-
F4
G1
G2
G3
G4
H1
H2
H3
H4
J1
J2
J3
J4
K2
K3
L1
N2
L2
N3
M3
L4
K5
N5
M5
L6
K6
L7
K7
M8
L8
C1
C2
D1
D2
D3
E1
E2
E3
E4
F1
F2
F3
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
12
13
14
15
20
21
22
23
80
81
82
83
84
85
86
-
Page 34 of 170
MB9B560R Series
Pin
Function
GPIO
Pin Name
P60
P61
P62
P63
P64
P65
P66
P67
P68
P70
P71
P72
P73
P74
P80
P81
PE0
PE2
PE3
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
Multifunction
Serial
0
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
SIN1_0
SIN1_1
SOT1_0
(SDA1_0)
Multifunction
Serial
1
SOT1_1
(SDA1_1)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
Function Description
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port E
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when it is used
in a UART/CSIO/LIN (operation modes 0 to
3) and as SDA0 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used
in a UART/CSIO/LIN (operation modes 0 to
3) and as SCL0 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output
pin.
This pin operates as SOT1 when it is used
in a UART/CSIO/LIN (operation modes 0 to
3) and as SDA1 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.1 clock I/O
pin.
This pin operates as SCK1 when it is used
in a CSIO (operation modes 4) and as
SCL1 when it is used in an I2C (operation
mode 4).
Document Number: 002-04864 Rev. *D
LQFP
120
LQFP
100
Pin No
LQFP
QFP
80
100
BGA
112
BGA
144
116
115
114
113
112
111
110
109
108
51
52
53
54
55
118
119
56
58
59
88
65
96
95
94
93
98
99
46
48
49
73
55
76
75
74
73
78
79
36
38
39
59
44
74
73
72
71
76
77
24
26
27
51
33
B3
B4
B5
C5
A3
A2
M10
N11
N12
C13
K12
B3
B4
C4
B5
C5
D5
A6
B6
C6
K8
L9
K9
M10
L10
A3
A2
N10
N11
N12
D11
J12
87
72
58
50
D12
D12
66
56
45
34
J13
J11
86
71
57
49
D13
D13
67
57
46
35
J12
J10
96
62
81
52
66
41
59
30
A9
L13
D9
L12
97
82
67
60
B9
C9
63
53
42
31
L12
K12
98
83
-
61
C9
B9
64
54
43
32
K13
K11
Page 35 of 170
MB9B560R Series
Pin
Function
Multifunction
Serial
2
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
SIN3_1
SOT3_0
(SDA3_0)
Multifunction
Serial
3
LQFP
100
Pin No
LQFP
QFP
80
100
53
85
68
58
47
36
J11
K9
E10
H12
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA2 when it is used in an I2C
(operation mode 4).
54
-
-
-
-
M10
84
-
-
-
-
E11
69
59
48
37
H12
H11
Multi-function serial interface ch.2 clock I/O
pin.
This pin operates as SCK2 when it is used in
a CSIO (operation modes 2) and as SCL2
when it is used in an I2C (operation mode 4).
55
-
-
-
-
L10
83
-
-
-
-
E12
74
64
53
42
H11
H10
110
15
10
10
88
F1
A6
G1
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA3 when it is used in an I2C
(operation mode 4).
109
-
-
-
-
B6
16
11
11
89
F2
G2
Multi-function serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in
a CSIO (operation modes 2) and as SCL3
when it is used in an I2C (operation mode 4).
108
-
-
-
-
C6
17
12
12
90
F3
G3
Pin Name
SOT3_1
(SDA3_1)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
Function Description
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.3 input pin
Document Number: 002-04864 Rev. *D
LQFP
120
BGA
112
BGA
144
Page 36 of 170
MB9B560R Series
Pin
Function
Multifunction
Serial
4
Multifunction
Serial
5
Pin Name
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
CTS4_0
CTS4_1
CTS4_2
RTS4_0
RTS4_1
RTS4_2
SIN5_0
SIN5_1
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
LQFP
100
Pin No
LQFP
QFP
80
100
BGA
112
6
75
10
6
65
-
6
54
-
84
43
-
D2
G12
-
D3
G12
E4
5
5
5
83
D1
D2
76
66
55
44
G11
G11
11
-
-
-
-
F1
4
4
4
82
C3
D1
77
67
56
45
F12
G10
12
-
-
-
-
F2
2
78
13
3
79
14
114
113
20
2
68
3
69
9
94
15
2
3
9
74
-
80
46
81
47
87
72
93
C1
F11
C2
E12
E3
B5
G3
C1
F13
F3
C2
F12
F4
C4
B5
H2
115
95
75
73
B4
B4
112
-
-
-
-
C5
21
16
-
94
H2
H3
116
96
76
74
B3
B3
111
-
-
-
-
D5
22
17
-
95
H3
H4
Function Description
Multi-function serial interface ch.4 input pin
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA4 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
CSIO (operation modes 2) and as SCL4 when it
is used in an I2C (operation mode 4).
Multi-function serial interface ch.4 CTS input pin
Multi-function serial interface ch.4 RTS output
pin
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA5 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
CSIO (operation modes 2) and as SCL5 when it
is used in an I2C (operation mode 4).
Document Number: 002-04864 Rev. *D
LQFP
120
BGA
144
Page 37 of 170
MB9B560R Series
Pin
Function
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
Multifunction
Serial
6
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
LQFP
100
Pin No
LQFP QFP
80
100
BGA
112
7
95
7
80
7
65
85
58
E1
A10
E1
B10
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA6 when it is used in an I2C (operation
mode 4).
8
8
8
86
E2
E2
94
79
64
57
B10
A11
Multi-function serial interface ch.6 clock I/O
pin.
This pin operates as SCK6 when it is used in a
CSIO (operation modes 2) and as SCL6 when
it is used in an I2C (operation mode 4).
9
-
-
-
-
E3
93
78
63
56
B11
C10
Function Description
Multi-function serial interface ch.6 input pin
BGA
144
SCS6_1
Multi-function serial interface ch.6 serial chip
select pin
92
77
62
55
A12
B13
SIN7_0
SIN7_1
Multi-function serial interface ch.7 input pin
101
50
86
45
35
64
23
C8
L9
C8
L8
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA7 when it is used in an I2C (operation
mode 4).
100
85
-
63
B8
D8
49
44
34
22
M9
M8
Multi-function serial interface ch.7 clock I/O
pin.
This pin operates as SCK7 when it is used in a
CSIO (operation modes 2) and as SCL7 when
it is used in an I2C (operation mode 4).
99
84
-
62
A8
A9
48
43
33
21
L8
K7
47
42
32
20
L7
L7
SOT7_0
(SDA7_0)
Multifunction
Serial
7
LQFP
120
Pin Name
SOT7_1
(SDA7_1)
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
SCS7_1
Multi-function serial interface ch.7 serial chip
select pin
Document Number: 002-04864 Rev. *D
Page 38 of 170
MB9B560R Series
Pin
Function
Pin Name
DTTI0X_0
DTTI0X_1
Multifunction
Timer
0
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
Function Description
Input signal controlling wave form generator
outputs RTO00 to RTO05 of Multi-function
timer 0.
16-bit free-run timer ch.0 external clock input
pin
16-bit input capture ch.0 input pin of
Multi-function timer 0.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Document Number: 002-04864 Rev. *D
LQFP
120
LQFP
100
Pin No
LQFP QFP
80
100
BGA
112
23
18
13
96
J1
J1
79
69
-
47
E12
F12
18
80
62
22
75
63
21
76
64
20
77
65
19
78
66
13
70
52
17
65
53
16
66
54
15
67
55
14
68
56
41
54
42
55
43
56
44
45
91
48
30
95
43
31
94
44
32
93
45
33
92
46
34
G1
E11
L13
H3
G12
L12
H2
G11
K13
G3
F12
K12
G2
F11
J13
G4
F11
L12
H4
G12
K12
H3
G11
K11
H2
G10
J12
H1
F13
J11
24
19
14
97
J2
J2
86
71
57
49
D13
D13
25
20
15
98
J3
J3
85
-
-
-
-
E10
26
21
16
99
K1
J4
84
-
-
-
-
E11
27
22
17
100
K2
K2
83
-
-
-
-
E12
28
23
18
1
L1
K3
82
-
-
-
-
E13
29
24
19
2
L2
L1
81
-
-
-
-
F10
BGA
144
Page 39 of 170
MB9B560R Series
Pin
Function
DTTI1X_0
DTTI1X_1
Multifunction
Timer
1
LQFP
120
LQFP
100
Pin No
LQFP QFP
80
100
BGA
112
Input signal controlling wave form generator
outputs RTO10 to RTO15 of Multi-function
timer 1.
8
8
8
86
E2
E2
55
-
-
-
-
L10
16-bit free-run timer ch.1 external clock input
pin
96
50
95
54
94
53
93
52
92
51
81
45
80
79
78
77
-
66
35
65
64
63
62
-
59
23
58
57
56
55
-
A9
L9
A10
B10
B11
A12
-
D9
L8
B10
M10
A11
K9
C10
L9
B13
K8
2
2
2
80
C1
C1
32
27
-
5
N2
N2
3
3
3
81
C2
C2
33
28
-
6
N3
L2
4
4
4
82
C3
D1
34
29
-
7
M3
N3
5
5
5
83
D1
D2
35
30
-
8
L3
M3
6
6
6
84
D2
D3
36
31
21
9
M4
L4
7
7
7
85
E1
E1
37
32
22
10
L5
K5
Pin Name
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Function Description
16-bit input capture ch.1 input pin of
Multi-function timer 1.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
Document Number: 002-04864 Rev. *D
BGA
144
Page 40 of 170
MB9B560R Series
Pin
Function
Quadrature
Position/
Revolution
Counter
0
Quadrature
Position/
Revolution
Counter
1
Real-time
clock
USB
Low-Power
Consumption
Mode
DAC
VBAT
Pin Name
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
ZIN1_1
ZIN1_2
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
UDM0
UDP0
UHCONX0
WKUP0
WKUP1
WKUP2
WKUP3
DA0
DA1
VREGCTL
VWAKEUP
S_CLK_0
S_CMD_0
SD I/F
S_DATA1_0
S_DATA0_0
S_DATA3_0
S_DATA2_0
S_CD_0
S_WP_0
Function Description
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
0.5 seconds pulse output pin of Real-time
clock
Sub clock output pin
USB device/host D – pin
USB device/host D + pin
USB external pull-up control pin
Deep standby mode return signal input pin 0
Deep standby mode return signal input pin 1
Deep standby mode return signal input pin 2
Deep standby mode return signal input pin 3
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
On-board regulator control pin
The return signal input pin from a hibernation
state
SD memory card interface
SD memory card clock output pin
SD memory card interface
SD memory card command output
SD memory card interface
SD memory card data bus
SD memory card interface
SD memory card detection pin
SD memory card interface
SD memory card write protection
Document Number: 002-04864 Rev. *D
LQFP
120
LQFP
100
Pin No
LQFP QFP
80
100
BGA
112
BGA
144
24
51
2
25
52
3
26
53
4
10
89
48
11
88
49
12
87
50
115
64
23
115
64
23
118
119
115
116
14
50
69
36
37
41
19
2
20
3
21
4
74
43
73
44
72
45
95
54
18
95
54
18
98
99
95
96
9
45
59
31
32
36
14
2
15
3
16
4
33
34
35
75
43
13
75
43
13
78
79
75
76
9
35
48
21
22
26
97
80
98
81
99
82
52
21
51
22
50
23
73
32
96
73
32
96
76
77
73
74
87
23
37
9
10
14
J2
C1
J3
C2
K1
C3
C12
L8
C13
M9
D12
L9
B4
K13
J1
B4
K13
J1
A3
A2
B4
B3
E3
L9
H12
M4
L5
L6
J2
K8
C1
J3
L9
C2
J4
K9
D1
E4
C12
K7
F1
D11
M8
F2
D12
L8
B4
K11
J1
B4
K11
J1
A3
A2
B4
B3
F4
L8
H11
L4
K5
L6
42
37
27
15
M7
K6
92
77
62
55
A12
B13
93
78
63
56
B11
C10
94
95
96
97
79
80
81
82
64
65
66
67
57
58
59
60
B10
A10
A9
B9
A11
B10
D9
C9
113
93
73
71
C5
B5
114
94
74
72
B5
C4
Page 41 of 170
MB9B560R Series
Pin
Function
Reset
Pin Name
INITX
MD1
Mode
MD0
Power
GND
Function Description
External Reset Input pin.
A reset is valid when INITX="L".
Mode 1 pin.
During serial programming to Flash memory,
MD1="L" must be input.
Mode 0 pin.
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
VCC
Power supply Pin
USBVCC
3.3 V Power supply port for USB I/O
VSS
GND Pin
Document Number: 002-04864 Rev. *D
LQFP
120
LQFP
100
Pin No
LQFP QFP
80
100
38
33
23
11
M6
N4
56
46
36
24
M10
N10
57
47
37
25
M11
M11
1
31
46
61
91
117
107
30
45
60
90
120
-
1
26
41
51
76
97
92
25
40
50
75
100
-
1
31
61
77
20
30
40
60
80
-
79
4
19
29
54
75
70
3
18
28
53
78
-
B1
M1
M8
M13
B13
A4
A5
N1
N10
N13
A13
A1
A7
B2
B12
C11
H1
N4
M5
N7
L11
A11
M12
M2
-
B1
M1
M9
M13
A12
A4
A7
N1
N9
N13
A13
A1
A5
A8
A10
B2
B11
B12
C3
C11
C13
D4
D10
K1
K4
K10
L3
L5
L11
L13
M2
M4
M6
M7
M12
N6
BGA
112
BGA
144
Page 42 of 170
MB9B560R Series
Pin
Function
Clock
Pin Name
X0
X1
X0A
X1A
CROUT_0
CROUT_1
AVCC
ADC
Power
AVRL
AVRH
VBAT
Power
ADC
GND
C pin
VBAT
AVSS
C
Function Description
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock output port
A/D converter and D/A converter
analog power supply pin
A/D converter analog reference voltage input
pin
A/D converter analog reference voltage input
pin
VBAT power supply pin.
Backup power supply (battery etc.) and system
power supply.
A/D converter and D/A converter
GND pin
Power supply stabilization capacity pin
LQFP
120
LQFP
100
Pin No
LQFP QFP
80
100
58
59
39
40
87
113
48
49
34
35
72
93
38
39
24
25
58
73
26
27
12
13
50
71
N11
N12
N5
N6
D12
C5
N11
N12
N5
M5
D12
B5
70
60
49
38
H13
K13
72
62
51
40
F13
H13
73
63
52
41
E13
G13
43
38
28
16
N8
N7
71
61
50
39
G13
J13
44
39
29
17
N9
N8
BGA
112
BGA
144
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04864 Rev. *D
Page 43 of 170
MB9B560R Series
5. I/O Circuit Type
Type
Circuit
Remarks
Pull-up
resistor
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
It is possible to select the main
oscillation / GPIO function
Pull-up resistor control
Digital input
Standby mode control
Clock input
When the main oscillation is
selected.
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
Feedback
A
When the GPIO is selected.
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
•
•
•
•
•
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-04864 Rev. *D
Page 44 of 170
MB9B560R Series
Type
Circuit
Remarks
Digital input
C
Digital output
N-ch
P-ch
P-ch
Digital output
E
N-ch
• Open drain output
• CMOS level hysteresis input
Digital output
R
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
P-ch
P-ch
N-ch
Digital output
Digital output
F
Pull-up resistor control
R
Digital input
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Standby mode control
Analog input
Input control
Document Number: 002-04864 Rev. *D
Page 45 of 170
MB9B560R Series
Type
Circuit
P-ch
P-ch
Remarks
Digital output
G
N-ch
Digital output
R
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -12 mA, IOL = 12 mA
Pull-up resistor
control
Digital input
Standby mode
control
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
UDP/Pxx
It is possible to select the USB
I/O / GPIO function.
USB Full-speed/Low-speed control
UDP input
When the USB I/O is selected.
• Full-speed, Low-speed control
H
Differential
UDM/Pxx
Differential input
USB/GPIO select
UDM input
UDM output
When the GPIO is selected.
•
•
•
•
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH = -20.5 mA, IOL = 18.5 mA
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-04864 Rev. *D
Page 46 of 170
MB9B560R Series
Type
Circuit
P-ch
P-ch
Remarks
Digital output
I
N-ch
Digital output
R
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
5 V tolerant
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• Available to control of PZR
registers.
Pull-up resistor
control
Digital input
Standby mode control
J
Mode input
P-ch
L
P-ch
N-ch
R
CMOS level hysteresis input
Digital output
Digital output
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -8 mA, IOL = 8 mA
Pull-up resistor
control
Digital input
Standby mode
control
Document Number: 002-04864 Rev. *D
Page 47 of 170
MB9B560R Series
Type
Circuit
P-ch
P-ch
N-ch
Remarks
Digital output
Digital output
M
Pull-up resistor
control
Digital input
R
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -8 mA, IOL = 8 mA
Standby mode
control
Analog input
Input control
Pull-up resistor
control
P-ch
P-ch
N
N-ch
R
N-ch
Digital output
Digital output
Fast mode
control
Digital input
Standby mode
control
Document Number: 002-04864 Rev. *D
・ CMOS level output
・ CMOS level hysteresis input
・ 5V tolerant
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA (GPIO)
・ IOL = 20mA (Fast mode Plus)
・ Available to control of PZR
register (pseudo-open drain
control)
・ For PZR registers, refer to GPIO
in the FM4 Family Peripheral
Manual Main Part (002-04856).
・ When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off.
Page 48 of 170
MB9B560R Series
Type
Circuit
Remarks
Pull-up resistor
control
P-ch
P-ch
Digital output
O
N-ch
Digital output
R
Digital input
P-ch
P-ch
X0A
N-ch
P
Pull-up resistor
control
Digital output
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ 5 V tolerant
・ Pull-up resistor control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
・ Available to control of PZR
register (pseudo-open drain
control)
・ For PZR registers, refer to GPIO
in the FM4 Family Peripheral
Manual Main Part (002-04856).
・ For I/O setting, refer to VBAT
Domain in the FM4 Family
Peripheral Manual Main Part
(002-04856).
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
R
Digital input
Standby mode
control
OSC
Document Number: 002-04864 Rev. *D
Page 49 of 170
MB9B560R Series
Type
Circuit
Pull-up resistor
control
Digital output
P-ch
P-ch
X1A
Remarks
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is selected.
Digital output
N-ch
Q
R
Digital input
Standby mode
control
OSC
RX
• Oscillation feedback resistor
: Approximately 10 MΩ
• With Standby mode control
•
•
•
•
•
•
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
Standby mode
control
Clock input
P-ch
P-ch
N-ch
Pull-up resistor
control
Digital output
Digital output
R
R
Digital input
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
Analog output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -12 mA, IOL = 12 mA
(4.5 V to 5.5 V)
• IOH = -8 mA, IOL = 8 mA
(2.7 V to 4.5 V)
Standby mode
control
Analog output
Document Number: 002-04864 Rev. *D
Page 50 of 170
MB9B560R Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the
design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04864 Rev. *D
Page 51 of 170
MB9B560R Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and have established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04864 Rev. *D
Page 52 of 170
MB9B560R Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, yo1u must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of
1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04864 Rev. *D
Page 53 of 170
MB9B560R Series
7. Handling Devices
Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this
device.
Power Supply Pins
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power
supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
• Surface mount type
Size:
Load capacitance:
• Lead type
Load capacitance:
More than 3.2 mm × 1.5 mm
Approximately 6 pF to 7 pF
Approximately 6 pF to 7 pF
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1 (PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as External
clock input
Can be used as
general-purpose
I/O ports.
Document Number: 002-04864 Rev. *D
X1(PE3), X1A (P47)
Page 54 of 170
MB9B560R Series
2
Handling when Using Multi-function Serial Pin as I C Pin
2
If it is using the multi-function serial pin as I C pins, P-ch transistor of digital output is always disabled.
2
2
However, I C pins need to keep the electrical characteristic like other pins and not to connect to the external I C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on Power-on
Turn power on/off in the following order or at the same time. The device operates normally after all power on.
VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns
Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(A) in FM4 Family Peripheral Manual Main Part(002-04856).
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on:
Turning off:
VBAT → VCC → USBVCC
VCC → AVCC → AVRH
AVRH → AVCC → VCC
USBVCC → VCC → VBAT
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in Features among the Products with Different Memory Sizes and between Flash Products and
MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Document Number: 002-04864 Rev. *D
Page 55 of 170
MB9B560R Series
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of pull-up function use of 5V tolerant I/O.
Adjoining Wiring on Circuit Board
If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility
that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as
possible between both wirings and insert the ground pattern between them in order to avoid this possibility.
Device
P46/
X0A
P47/
X1A
P48/
P49/
VREGCTL VWAKEUP
Not allowed to run
both wirings in parallel
Ground
Insert the ground pattern
Handling when Using Debug Pins
When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set
them as output, do not set them as input.
Document Number: 002-04864 Rev. *D
Page 56 of 170
MB9B560R Series
8. Block Diagram
MB9BF566M/N/R, F567M/N/R, F568M/N/R
TRSTX,TCK,
TDI,TMS
TDO
TRACEDx,
TRACECLK
SWJ-DP
ETM*
TPIU*
ROM
Table
SRAM0
32/48/64 Kbytes
SRAM1
16/24/32 Kbytes
Cortex-M4 Core I
@160 MHz(Max)
D
MPU NVIC
Multi-layer AHB (Max 160 MHz)
FPU
Sys
AHB-APB Bridge:
APB0(Max 80 MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
CSV
SRAM2
16/24/32 Kbytes
MainFlash I/F
MainFlash
1 Mbytes/
768 Kbytes/
512 Kbytes
Trace Buffer
(16 Kbytes)
Security
WorkFlash
32 Kbytes
WorkFlash I/F
USB2.0
(Host/
Func)
PHY
USBVCC
UDP0,UDM0
UHCONX0
DMAC
8ch.
CLK
DSTC
SD-CARD I/F
CAN
X0A
X1A
Main
Osc
PLL
VBAT Domain
Sub
Osc
AHB-AHB Bridge
Source Clock
X0
X1
CR
100 kHz
CR
4 MHz
CAN
GPIO
PIN-Function-Ctrl
CROUT
S_CLK,S_CMD
S_DATAx
S_CD,S_WP
TX0,
RX0
TX1,
RX1
P0x,
P1x,
.
.
.
PEx
MADx
AVCC,
AVSS,
AVRH
ANxx
ADTGx
External Bus I/F
Unit 1
CAN Prescaler
QPRC
2ch.
A/D Activation Compare
6ch.
IC0x
FRCK0
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output Compare
6ch.
DTTI0X
RTO0x
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-function Timer × 2
AHB-APB Bridge : APB2 (Max 80 MHz)
AINx
BINx
ZINx
Base Timer
16-bit 16ch./
32-bit 8ch.
AHB-APB Bridge : APB1 (Max 160 MHz)
TIOBx
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT,MSDWEX,
MSDCLK,MSDCKE,
MRASX,MCASX
Unit 2
USB Clock Ctrl
TIOAx
MADATAx
12-bit A/D Converter
Unit 0
PLL
Power-On
Reset
LVD Ctrl
LVD
IRQ-Monitor
Regulator
C
CRC Accelerator
Watch Counter
Deep Standby Ctrl
WKUPx
Peripheral Clock Gating
Low-speed CR Prescaler
VBAT Domain
Real-Time Clock
Port Ctrl.
VWAKEUP
VREGCTL
RTCCO,
SUBOUT
External Interrupt
Controller
16pin + NMI
INTx
NMIX
MODE-Ctrl
MD0,
MD1
Multi-function Serial I/F
8ch.
HW flow control(ch.4)
SCKx
SINx
SOTx
CTS4
RTS4
12-bit D/A Converter
2units
DAx
*: For the MB9BF566M, MB9BF567M and MB9BF568M, ETM is not available.
Document Number: 002-04864 Rev. *D
Page 57 of 170
MB9B560R Series
9. Memory Size
See Memory size in 1. Product Lineup to confirm the memory size.
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_4000
0xFFFF_FFFF
0x4006_3000
Reserved
0xE010_0000
0xE000_0000
0x4006_2000
0x4006_1000
Cortex-M4 Private
Peripherals
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
External Device
Area
0x4003_C800
0x4003_C100
GPIO
SD-Card I/F
Reserved
CAN ch.1
CAN ch.0
DSTC
DMAC
Reserved
USB ch.0
EXT-bus I/F
Reserved
Peripheral Clock Gating
0x4003_C000 Low Speed CR Prescaler
0x6000_0000
0x4003_7000
RTC/Port Ctrl
Watch Counter
CRC
MFS
CAN prescaler
0x4003_6000
USB Clock ctrl
0x4003_5000
0x4003_4000
LVD/DS mode
0x4003_B000
0x4003_A000
Reserved
0x4400_0000
0x4200_0000
0x4003_8000
32 Mbytes
Bit band alias
Peripherals
0x4000_0000
Reserved
0x2400_0000
0x2200_0000
0x200C_0000
0x2004_8000
0x2004_0000
0x2003_8000
See "lMemory Map (2)"
for the memory size
details.
0x2000_0000
0x1FFF_0000
0x0050_0000
0x0040_0000
Reserved
0x4003_1000
Int-Req.Read
EXTI
Reserved
CR Trim
0x4002_E000
Reserved
0x4002_8000
0x4002_F000
0x4002_7000
Reserved
SRAM2
SRAM1
Reserved
SRAM0
Reserved
Security/CR Trim
MainFlash
0x0000_0000
D/AC
0x4003_2000
32 Mbytes
Bit band alias
WorkFlash I/F
WorkFlash
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_2000
0x4002_1000
0x4002_0000
0x4001_6000
0x4001_5000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
Document Number: 002-04864 Rev. *D
Reserved
0x4003_3000
0x4003_0000
0x2010_0000
0x200E_0000
0x4003_9000
Reserved
A/DC
QPRC
Base Timer
PPG
Reserved
MFT Unit1
MFT Unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
MainFlash I/F
Page 58 of 170
MB9B560R Series
Memory Map (2)
MB9BF568M/N/R
0x2008_0000
MB9BF567M/N/R
0x2008_0000
Reserved
0x200C_8000
0x200C_0000
0x2008_0000
Reserved
0x200C_8000
WorkFlash
32 Kbytes
MB9BF566M/N/R
0x200C_0000
Reserved
Reserved
0x200C_8000
WorkFlash
32 Kbytes
0x200C_0000
Reserved
0x2004_8000
WorkFlash
32 Kbytes
Reserved
0x2004_6000
SRAM2
32 Kbytes
0x2004_0000
0x2004_0000
SRAM1
32 Kbytes
0x2003_A000
SRAM2
24 Kbytes
SRAM1
24 Kbytes
0x2004_4000
0x2004_0000
0x2003_C000
SRAM2
16 Kbytes
SRAM1
16 Kbytes
0x2003_8000
0x2000_0000
0x2000_0000
SRAM0
64 Kbytes
Reserved
Reserved
Reserved
0x1FFF_4000
0x2000_0000
SRAM0
48 Kbytes
0x1FFF_8000
SRAM0
32 Kbytes
0x1FFF_0000
0x0050_0000
0x0040_2000
0x0040_0000
0x0050_0000
CR trimming
Security
Reserved
Reserved
Reserved
0x0040_2000
0x0040_0000
0x0050_0000
CR trimming
Security
0x0040_2000
0x0040_0000
CR trimming
Security
Reserved
Reserved
0x0010_0000
Reserved
0x000C_0000
MainFlash
1 Mbytes
0x0000_0000
Document Number: 002-04864 Rev. *D
0x0008_0000
MainFlash
768 Kbytes
0x0000_0000
MainFlash
512 Kbytes
0x0000_0000
Page 59 of 170
MB9B560R Series
Peripheral Address Map
Start address
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_C100
0x4003_C800
0x4003_F000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4006_E000
0x4006_F000
0x4006_7000
0x200E_0000
End address
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4003_FFFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_4FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_C0FF
0x4003_C7FF
0x4003_EFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x4006_DFFF
0x4006_EFFF
0x4006_FFFF
0x41FF_FFFF
0x200E_FFFF
Document Number: 002-04864 Rev. *D
Bus
AHB
APB0
APB1
APB2
AHB
Peripherals
MainFlash I/F register
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Internal CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
D/A Converter
Reserved
Low Voltage Detector
Deep standby mode Controller
USB clock generator
CAN prescaler
Multi-function serial Interface
CRC
Watch Counter
RTC/Port Ctrl
Low-speed CR Prescaler
Peripheral Clock Gating
Reserved
External Memory interface
USB ch.0
Reserved
DMAC register
DSTC register
CAN ch.0
CAN ch.1
Reserved
SD-Card I/F
GPIO
Reserved
WorkFlash I/F register
Page 60 of 170
MB9B560R Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Setting prohibition
Prohibition of a setting by specification limitation.
Document Number: 002-04864 Rev. *D
Page 61 of 170
MB9B560R Series
Pin status Type
List of Pin Status
A
B
Function
Group
Power-on
Reset or
Low-voltage
Detection
State
Power
Supply
Unstable
‐
‐
INITX
Input
State
Device
Internal
Reset
State
Power Supply
Stable
INITX=0
‐
INITX=1
‐
Run
Mode
or Sleep
Mode
State
Power
Supply
Stable
INITX=1
‐
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Power Supply
Stable
Power Supply
Stable
INITX=1
SPL=0
SPL=1
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Internal input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Hi-Z /
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Internal input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Main crystal
oscillator
input pin/
External
main clock
input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
External
main clock
input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0"/
or Input
enable
Hi-Z /
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
Main crystal
oscillator
output pin
Power
Supply
Stable
INITX=1
-
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
INITX=1
SPL=0
SPL=1
Return
from
Deep
Standby
Mode
State
Maintain
previous
state
GPIO
selected
Maintain
previous
state
Maintain previous state /
When oscillation stops*1, Hi-Z /
Internal input fixed at 0
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Document Number: 002-04864 Rev. *D
Page 62 of 170
Pin status Type
MB9B560R Series
E
F
Function
Group
Power-on
Reset or
Low-voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Power
Supply
Unstable
‐
‐
INITX=0
‐
INITX=1
‐
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
NMIX
selected
Setting
disabled
Setting
disabled
Setting
disabled
Resource
other than
above
selected
Hi-Z
GPIO
selected
JTAG
selected
Hi-Z
Power Supply
Stable
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
G
H
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Resource
other than
above
selected
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Resource
selected
I
GPIO
selected
Document Number: 002-04864 Rev. *D
Run Mode
or SLEEP
Mode
State
TIMER Mode,
RTC Mode, or
STOP Mode State
Deep Standby RTC
Mode or Deep Standby
STOP Mode State
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=1
‐
SPL=0
Input
enabled
Maintain
previous
state
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
INITX=1
SPL=1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
INITX=1
SPL=0
SPL=1
Input
enabled
GPIO
selected
WKUP
input
enabled
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
WKUP
input
enabled
Return
from
Deep
Standby
Mode
State
Power
Supply
Stable
INITX=1
-
Input
enabled
GPIO
selected
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input
fixed
at 0
GPIO
selected
Internal
input
fixed
at 0
Page 63 of 170
Pin status Type
MB9B560R Series
Function
Group
Analog
output
selected
J
K
Resource
other than
above
selected
GPIO
selected
External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
Analog input
selected
Power-on
Reset or
Low-voltage
Detection
State
Power
Supply
Unstable
‐
‐
INITX=0
‐
INITX=1
‐
Setting
disabled
Setting
disabled
Setting
disabled
Power Supply
Stable
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Run
Mode
or Sleep
Mode
State
Power
Supply
Stable
INITX=1
‐
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Power Supply
Stable
Power Supply
Stable
SPL=0
INITX=1
SPL=1
*2
Maintain
previous
state
Maintain
previous
state
*3
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
L
Resource
other than
above
selected
GPIO
selected
INITX
Input
State
Device
Internal
Reset
State
Document Number: 002-04864 Rev. *D
INITX=1
SPL=0
SPL=1
Return
from
Deep
Standby
Mode
State
Power
Supply
Stable
INITX=1
-
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
GPIO
selected
Internal
input
fixed
at 0
Page 64 of 170
Pin status Type
MB9B560R Series
Function
Group
Analog input
selected
M External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
Analog input
selected
N
Trace
selected
Resource
other than
above
selected
GPIO
selected
Power-on
Reset or
Low-voltage
Detection
State
Power
Supply
Unstable
‐
‐
Hi-Z
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
INITX=0
‐
INITX=1
‐
Power
Supply
Stable
INITX=1
‐
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Power Supply
Stable
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Power Supply
Stable
Power Supply
Stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Trace
output
Setting
disabled
Setting
disabled
Document Number: 002-04864 Rev. *D
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Return
from Deep
Standby
Mode State
Power
Supply
Stable
INITX=1
-
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Page 65 of 170
Pin status Type
MB9B560R Series
Function
Group
Analog input
selected
O
Power-on
Reset or
Low-voltage
Detection
State
Power
Supply
Unstable
‐
‐
Hi-Z
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
INITX=0
‐
INITX=1
‐
Power
Supply
Stable
INITX=1
‐
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Power Supply
Stable
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Power Supply
Stable
Power Supply
Stable
SPL=0
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
INITX=1
SPL=1
Trace
selected
Trace
output
External
interrupt
enabled
selected
Maintain
previous
state
Resource
other than
above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
GPIO
selected
Analog input
selected
P
Hi-Z /
Internal input
fixed
at 0 /
Analog
input
enabled
Hi-Z
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
0/
Analog
input
enabled
WKUP
enabled
Resource
other than
above
selected
Setting
disabled
Setting
disabled
GPIO
selected
Document Number: 002-04864 Rev. *D
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal input
fixed
at 0
INITX=1
SPL=0
SPL=1
Return
from
Deep
Standby
Mode
State
Power
Supply
Stable
INITX=1
-
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Hi-Z /
Internal input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
Internal input
fixed
at 0
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
WKUP
input
enabled
Hi-Z /
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
GPIO
selected
Page 66 of 170
Pin status Type
MB9B560R Series
Function
Group
Power-on
Reset or
Low-voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Power
Supply
Unstable
‐
INITX=0
INITX=1
Power
Supply
Stable
INITX=1
‐
‐
‐
‐
Power Supply
Stable
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Power Supply
Stable
Power Supply
Stable
INITX=1
SPL=0
WKUP
enabled
External
interrupt
enabled
Q
selected
Resource
other than
above
selected
GPIO
selected
GPIO
selected
Setting
disabled
Setting
disabled
Maintain
previous
state
Setting
disabled
Maintain
previous
state
Hi-Z
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
SPL=1
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
-
GPIO
selected
Hi-Z /
Internal input
fixed
at 0
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Internal input
fixed
at 0
GPIO
selected
Internal
input
fixed
at 0
Hi-Z /
Internal
input
fixed
at 0
GPIO
selected
Setting
disabled
Hi-Z at
transmission/
Input
enabled
/
Internal
input
fixed
at 0 at
receptio
n
Hi-Z at
transmission/
Input
enabled/
Internal input
fixed
at 0 at
reception
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Setting
disabled
Maintain
previous
state
INITX=1
SPL=0
Hi-Z /
Input
enabled
R
USB I/O pin
SPL=1
Return
from
Deep
Standby
Mode
State
Power
Supply
Stable
INITX=1
*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep
Standby Stop mode.
*2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode.
*3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.
Document Number: 002-04864 Rev. *D
Page 67 of 170
MB9B560R Series
VBAT Pin Status Type
List of VBAT Domain Pin Status
S
T
Power-on
Reset*1
INITX
Input
State
Function
Group
Power
Supply
Unstable
‐
‐
Device
Internal
Reset
State
Run
Mode or
Sleep
Mode
State
INITX=0
‐
INITX=1
‐
Power
Supply
Stable
INITX=1
‐
Power Supply Stable
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby
RTC Mode or Deep
Standby Stop Mode
State
Power Supply Stable
Power Supply Stable
INITX=1
SPL=0
SPL=1
INITX=1
SPL=0
SPL=1
Return
from
Deep
Standby
Mode
State
VBAT
RTC
Mode
State
Return
from
VBAT
RTC
Mode
State
Power
Supply
Stable
INITX=1
-
Power
Supply
Stable
-
Power
Supply
Stable
-
GPIO
selected
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
prohibiti
on
-
Sub crystal
oscillator
input pin /
External
sub clock
input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
prohibiti
on
-
External
sub clock
input
selected
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state/
When
oscillation
stops,
Hi-Z*2
Maintain
previous
state/
When
oscillation
stops,
Hi-Z*2
Maintain
previous
state/
When
oscillation
stops,
Hi-Z*2
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Sub crystal
oscillator
output pin
Hi-Z /
Internal
input
fixed at 0/
or Input
enable
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state/
When
oscillation
stops,
Hi-Z*2
Hi-Z
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Resource
selected
U
GPIO
selected
*1: When VBAT and VCC power on.
*2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous
state. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby
Stop mode
Document Number: 002-04864 Rev. *D
Page 68 of 170
MB9B560R Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
1,
Rating
Symbol
2
Power supply voltage * *
1,
Power supply voltage (for USB) * *
3
1, 4
Power supply voltage (VBAT) * *
1, 5
Analog power supply voltage * *
1, 5
Analog reference voltage * *
Min
VCC
VSS - 0.5
VSS + 6.5
V
USBVCC
VSS - 0.5
VSS + 6.5
V
VBAT
VSS - 0.5
VSS + 6.5
V
AVCC
VSS - 0.5
VSS + 6.5
V
AVRH
VSS - 0.5
VSS + 6.5
V
VSS - 0.5
1
Input voltage *
VI
VSS - 0.5
VSS - 0.5
1
Analog pin input voltage *
1
Output voltage *
"L" level maximum output current *
6
VIA
VSS - 0.5
VO
VSS - 0.5
IOL
-
"L" level average output current *
IOLAV
-
"L" level total maximum output current
8
"L" level total maximum output current *
∑IOL
∑IOLAV
-
IOH
-
"H" level average output current *
IOHAV
-
"H" level total maximum output current
8
"H" level total average output current *
Storage temperature
∑IOH
∑IOHAV
TSTG
- 55
7
"H" level maximum output current *
6
7
Unit
Max
VCC + 0.5
(≤ 6.5V)
USBVCC + 0.5
(≤ 6.5V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
10
20
20
22.4
4
8
12
20
100
50
- 10
20
- 20
-4
8
- 12
- 100
- 50
+ 150
Remarks
V
Except for USB pin
V
USB pin
V
5 V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
4 mA type
8 mA type
12 mA type
I2C Fm+
4 mA type
8 mA type
12 mA type
I2C Fm+
4 mA type
8 mA type
12 mA type
4 mA type
8 mA type
12 mA type
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: VBAT must not drop below VSS - 0.5 V.
*5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100ms period.
*8: The total average output current is defined as the average current value flowing through all of corresponding pins for a period of
100 ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04864 Rev. *D
Page 69 of 170
MB9B560R Series
12.2 Recommended Operating Conditions
Parameter
Power supply voltage
Power supply voltage (for USB)
Power supply voltage (VBAT)
Analog power supply voltage
Analog reference voltage
Junction temperature
Operating
temperature
Ambient temperature
Symbol
VCC
USBVCC
VBAT
AVCC
AVRH
Tj
Ta
Value
Conditions
-
Min
5
Max
2.7*
5.5
3.0
3.6
(≤ VCC)
2.7
5.5
(≤ VCC)
2.7
2.7
*4
- 40
- 40
5.5
5.5
AVCC
+ 125
*3
-
-
Unit
Remarks
V
*1
V
*2
V
V
V
°C
°C
AVCC=VCC
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: The maximum temperature of the ambient temperature (Ta) can guarantee a range that does not exceed
the junction temperature (Tj).
The calculation formula of the ambient temperature (Ta) is shown below.
Ta(Max) = Tj(Max) - Pd(Max) × θja
Pd: Power dissipation (W)
θja: Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL: L level output current
IOH: H level output current
VOL: L level output voltage
VOH: H level output voltage
*4: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck).
See "12.5. 12-bit A/D Converter" for the details.
*5: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
Document Number: 002-04864 Rev. *D
Page 70 of 170
MB9B560R Series
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for Package Thermal Resistance and Maximum Permissible Power
Package
LQH080
(0.5 mm pitch)
LQJ080
(0.65 mm pitch)
LQI100
(0.5 mm pitch)
PQH100
(0.65 mm pitch)
LQM120
(0.5 mm pitch)
LDC112
(0.5 mm pitch)
LDC144
(0.5 mm pitch)
Printed Circuit Board
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Maximum Permissible Power
(mW)
Ta=+85 °C
Ta=+105 °C
Thermal Resistance
θja (°C/W)
60
39
58
38
57
38
48
34
62
43
60
40
55
40
667
1026
690
1053
702
1053
833
1177
645
930
667
1000
727
1000
333
513
335
526
351
526
417
588
323
465
333
500
364
500
WARNING:
−
The recommended operating conditions are required to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04864 Rev. *D
Page 71 of 170
MB9B560R Series
Calculation Method of Power Dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL: "L" level output current
IOH: "H" level output current
VOL: "L" level output voltage
VOH: "H" level output voltage
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT): Current consumed in internal logic and memory, etc. through regulator
ΣICC(IO): Sum of current (I/O switching current) consumed in output pin
For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include ICC (IO) for a
value at pin fixed).
For Icc (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC(IO) = (CINT + CEXT) × VCC × fsw
CINT: Pin internal load capacitance
CEXT: External load capacitance of output pin
fSW: Pin switching frequency
Parameter
Pin internal load capacitance
Symbol
CINT
Conditions
Capacitance Value
4 mA type
1.93 pF
8 mA type
3.45 pF
12 mA type
3.42 pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated.
1. Measure current value ICC (Typ) at normal temperature (+25°C).
2. Add maximum leak current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Maximum leak current at operating
Document Number: 002-04864 Rev. *D
Symbol
ICC(leak_max)
Conditions
Tj = +125 °C
Tj = +105 °C
Tj = +85 °C
Current Value
45.5 mA
26.8 mA
16.2 mA
Page 72 of 170
MB9B560R Series
Current Explanation Diagram
Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC = ICC(INT)＋ΣICC(IO)
VCC
A
ICC
Chip
ICC(INT)
ΣICC(IO)
A
Regulator
VOL
V
A
・・・
V
IOL
Flash
VOH
・・・
Logic
IOH
RAM
ICC(IO)
CEXT
・・・
Document Number: 002-04864 Rev. *D
Page 73 of 170
MB9B560R Series
12.3 DC Characteristics
12.3.1 Current Rating
Table 12-1. Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory (Flash
accelerator mode and trace buffer function enabled)
Parameter
Power
supply
current
Symbol
ICC
Pin
Name
VCC
Frequency*4
Conditions
Normal operation
(PLL)
*5, *6
1
160 MHz
Typ*
54
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
4 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
4 MHz
49
41
35
28
22
16
8.9
5.1
3.8
34
31
26
22
18
14
10
6.2
3.8
3.1
Value
2
Max*
103
98
90
84
77
71
64
58
54
53
83
80
75
71
67
63
59
55
53
52
Unit
Remarks
mA
*3
When all peripheral
clocks are ON
mA
*3
When all peripheral
clocks are OFF
Table 12-2. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from
Flash memory (Flash accelerator mode and trace buffer function disabled)
Parameter
Power
supply
current
Symbol
ICC
Pin
Name
VCC
Conditions
Normal
operation
(PLL)
Document Number: 002-04864 Rev. *D
*8
Frequency*7
Value
1
Typ*
2
Max*
160 MHz
74
126
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
4 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
4MHz
68
59
52
44
36
27
17
8.3
5.4
51
47
42
37
33
28
21
13
6.9
4.6
120
112
104
97
89
79
67
58
55
103
100
94
90
85
80
73
64
56
54
Unit
Remarks
mA
*3
When all peripheral
clocks are ON
mA
*3
When all peripheral
clocks are OFF
Page 74 of 170
MB9B560R Series
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to MainFlash memory
*7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK
*8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
Table 12-3. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from
Flash memory (flash 0 wait-cycle mode and read access 0 wait)
Parameter
Power
supply
current
Symbol
ICC
Pin
Name
VCC
Conditions
Normal
operation
(PLL)
*5
Frequency*4
(MHz)
72 MHz
Typ*
46
Max*
98
60 MHz
40
92
48 MHz
33
85
36 MHz
27
78
24 MHz
19
70
12 MHz
8 MHz
4 MHz
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
11
8.5
5.5
33
29
25
20
15
61
58
55
85
81
76
71
65
12 MHz
9.2
59
8 MHz
4 MHz
6.9
4.6
56
54
Value
1
2
Unit
Remarks
mA
*3
When all peripheral
clocks are ON
mA
*3
When all peripheral
clocks are OFF
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)
Document Number: 002-04864 Rev. *D
Page 75 of 170
MB9B560R Series
Table 12-4. Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing
running from Flash memory (flash 0 wait-cycle mode and read access 0 wait
Parameter
Symbol
Pin
Name
Frequency*4
Conditions
Value
2
Max*
Unit
1
Typ*
Remarks
3
Normal operation
(built-in
high-speed CR)
Power
supply
current
ICC
VCC
Normal operation
(sub oscillation)
Normal operation
(built-in
low-speed CR)
*5
*5
*5
3.3
51
mA
2.8
51
mA
4 MHz
*
When all peripheral
clocks are ON
*3
When all peripheral
clocks are OFF
0.64
48
mA
*3
When all peripheral
clocks are ON
0.56
48
mA
*3
When all peripheral
clocks are OFF
0.64
48
mA
*3
When all peripheral
clocks are ON
mA
*3
When all peripheral
clocks are OFF
32 kHz
100 kHz
0.58
48
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)
Table 12-5. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2
Parameter
Power
supply
current
Symbol
ICCS
Pin
Name
VCC
Conditions
SLEEP
operation
(PLL)
Document Number: 002-04864 Rev. *D
Frequency*4
Value
1
2
160 MHz
Typ*
35
Max*
84
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
4 MHz
160 MHz
144 MHz
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
4 MHz
32
27
23
19
15
11
6.5
4.1
3.3
16
14
12
11
9.0
7.4
5.6
3.9
2.9
2.6
81
76
72
68
64
60
55
53
52
65
63
61
60
58
56
54
53
52
51
Unit
Remarks
mA
*3
When all peripheral
clocks are ON
mA
*3
When all peripheral
clocks are OFF
Page 76 of 170
MB9B560R Series
Table 12-6. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK
Parameter
Power
supply
current
Pin
Name
Symbol
ICCS
VCC
Frequency*5
Conditions
SLEEP
operation
(PLL)
Value
1
2
72 MHz
Typ*
22
Max*
71
60 MHz
19
68
48 MHz
16
64
36 MHz
12
61
24 MHz
9.0
58
12 MHz
8 MHz
4 MHz
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
5.8
4.6
3.6
9.5
8.3
7.1
5.8
4.6
55
54
52
58
57
56
55
53
12 MHz
3.5
52
8 MHz
4 MHz
3.0
2.7
52
51
Unit
Remarks
mA
*3
When all peripheral
clocks are ON
mA
*3
When all peripheral
clocks are OFF
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
Table 12-7. Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 = PCLK2
= HCLK/2
Parameter
Symbol
Pin Name
Conditions
SLEEP
operation
(built-in
high-speed CR)
Power
supply
current
ICCS
VCC
SLEEP
operation
(sub oscillation)
SLEEP
operation
(built-in
low-speed CR)
Frequency*4
Value
1
Typ*
1.5
2
Max*
49
Unit
mA
4 MHz
1.0
49
mA
0.59
48
mA
0.51
48
mA
32 kHz
Remarks
*3
When all peripheral
clocks are ON
*3
When all peripheral
clocks are OFF
*3
When all peripheral
clocks are ON
*3
When all peripheral
clocks are OFF
0.61
48
mA
*3
When all peripheral
clocks are ON
0.53
48
mA
*3
When all peripheral
clocks are OFF
100 kHz
*1: Ta=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are fixed.
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
Document Number: 002-04864 Rev. *D
Page 77 of 170
MB9B560R Series
Table 12-8. Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode
Parameter
Symbol
Pin Name
ICCH
Conditions
STOP mode
TIMER mode
(built-in
high-speed CR)
Power supply
current
ICCT
VCC
TIMER mode
(sub oscillation)
TIMER mode
(built-in
low-speed CR)
ICCR
RTC mode
(sub oscillation)
Frequency
-
4 MHz
32 kHz
100 kHz
32 kHz
Value
2
Max*
1
Typ*
Unit
Remarks
*3, *4
Ta=+25°C
0.33
1.8
mA
-
15
mA
-
22
mA
0.70
2.2
mA
-
16
mA
-
22
mA
0.33
1.8
mA
*3, *4
Ta=+25°C
-
15
mA
*3, *4
Ta=+85°C
-
22
mA
0.34
1.8
mA
-
15
mA
-
22
mA
0.33
1.8
mA
-
15
mA
-
22
mA
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are fixed.
*4: When LVD is OFF
Document Number: 002-04864 Rev. *D
Page 78 of 170
MB9B560R Series
Table 12-9. Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT
Parameter
Pin
Name
Symbol
Conditions
Frequency
1
Typ*
Value
2
Max*
Unit
Remarks
3
Deep standby
STOP mode
(When RAM is
OFF)
ICCHD
29
140
µA
-
644
µA
-
1011
µA
48
273
µA
-
2676
µA
-
4162
µA
29
140
µA
-
644
µA
-
1011
µA
48
273
µA
-
2676
µA
-
4162
µA
0.015
0.29
µA
-
5.77
µA
-
10.6
µA
1.53
22.6
µA
-
35.2
µA
-
41.8
µA
Deep standby
STOP mode
(When RAM is
ON)
VCC
Power
supply
current
Deep standby
RTC mode
(When RAM is
OFF)
ICCRD
32 kHz
Deep standby
RTC mode
(When RAM is
ON)
RTC stop*6
ICCVBAT
VBAT
RTC
operation*6
4
*,*
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*3, *4, *5
Ta=+25°C
*3, *4, *5
Ta=+85°C
*3, *4, *5
Ta=+105°C
*3, *4
Ta=+25°C
*3, *4
Ta=+85°C
*3, *4
Ta=+105°C
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are fixed.
*4: When LVD is OFF
*5: When sub oscillation is OFF
*6: In the case of setting RTC after VCC power on
Document Number: 002-04864 Rev. *D
Page 79 of 170
MB9B560R Series
Table 12-10. Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase
Value
Parameter
Symbol
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
Main flash
memory
write/erase
current
ICCFLASH
Work flash
memory
write/erase
current
ICCWFLASH
Pin Name
VCC
Conditions
Min
Typ
Max
Unit
At operation
-
4
7
μA
At Write/Erase
-
13.4
15.9
mA
At Write/Erase
-
11.5
13.6
mA
Remarks
For occurrence of
interrupt
Peripheral current dissipation
Clock
System
HCLK
PCLK1
PCLK2
Peripheral
Unit
40
Frequency (MHz)
80
160
GPIO
All ports
0.22
0.43
0.85
DMAC
-
0.74
1.48
2.88
DSTC
-
0.32
0.61
1.17
External bus I/F
-
0.14
0.27
0.55
SD card I/F
-
0.93
1.81
3.63
CAN
1ch.
0.02
0.06
0.11
USB
1ch.
0.34
0.67
1.33
Base timer
4ch.
0.16
0.34
0.66
1 unit/4ch.
0.55
1.09
2.17
1 unit
0.04
0.09
0.17
A/DC
1 unit
0.20
0.39
0.78
Multi-function serial
1ch.
0.31
0.62
-
Multi-functional
timer/PPG
Quadrature
position/Revolution
counter
Document Number: 002-04864 Rev. *D
Unit
Remarks
mA
mA
mA
Page 80 of 170
MB9B560R Series
12.3.2 Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin Name
Value
Conditions
Min
"H" level input
voltage
(hysteresis
input)
"L" level input
voltage
(hysteresis
input)
VIHS
VILS
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
Input pin
doubled as I2C
Fm+
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
Input pin
doubled as I2C
Fm+
4mA type
8mA type
"H" level output
voltage
VOH
12mA type
The pin
doubled as
USB I/O
The pin
doubled as I2C
Fm+
Document Number: 002-04864 Rev. *D
Unit
Typ
-
VCC×0.8
-
VCC + 0.3
V
-
VCC×0.8
-
VSS + 5.5
V
-
VCC×0.7
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC×0.2
V
-
VSS - 0.3
-
VCC×0.2
V
-
VSS
-
VCC×0.3
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
USBVCC - 0.4
-
USBVCC
V
VCC - 0.5
-
VCC
V
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 8 mA
VCC < 4.5 V,
IOH = - 4 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
IOH = - 20.5 mA
USBVCC < 4.5 V,
IOH = - 13.0 mA
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 3 mA
Remarks
Max
At GPIO
Page 81 of 170
MB9B560R Series
Value
Parameter
Symbol
Pin Name
Conditions
Min
Typ
Unit
Max
Remarks
VCC ≥ 4.5 V,
IOL = 4 mA
4 mA type
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOH = 8 mA
8 mA type
VCC < 4.5 V,
IOH = 4 mA
VCC ≥ 4.5 V,
IOL = 12 mA
12 mA type
"L" level output
voltage
VCC < 4.5 V,
IOL = 8 mA
VOL
The pin
doubled as
USB I/O
USBVCC ≥ 4.5 V,
IOL = 18.5 mA
USBVCC < 4.5 V,
IOL = 10.5 mA
VCC ≥ 4.5 V,
IOH = 4 mA
The pin
doubled as I2C
Fm+
At GPIO
VCC < 4.5 V,
IOH = 3 mA
VCC ≤ 5.5 V,
IOH = 20 mA
Input leak
current
IIL
-
Pull-up resistor
value
RPU
Pull-up pin
CIN
Other than
VCC,
USBVCC,
VBAT,
VSS,
AVCC,
AVSS, AVRH
Input
capacitance
Document Number: 002-04864 Rev. *D
At I2C Fm+
-
-5
-
+5
VCC ≥ 4.5 V
25
50
100
VCC < 4.5 V
30
80
200
-
-
5
15
μA
kΩ
pF
Page 82 of 170
MB9B560R Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Input frequency
Pin Name
fCH
Input clock cycle
tCYLH
Input clock pulse
width
Input clock rising time
and falling time
Internal operating
1
clock* frequency
Internal operating
1
clock* cycle time
X0,
X1
tCF,
tCR
Value
Conditions
Min
Unit
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
PWH/tCYLH,
PWL/tCYLH
4
4
4
4
20.83
50
48
20
48
20
250
250
45
-
Remarks
MHz
When crystal oscillator is connected
MHz
When using external clock
ns
When using external clock
55
%
When using external clock
-
5
ns
When using external clock
fCC
-
-
-
160
MHz
Base clock (HCLK/FCLK)
fCP0
fCP1
-
-
-
80
160
MHz
MHz
APB0 bus clock*
2
APB1 bus clock*
fCP2
-
-
-
80
MHz
APB2 bus clock*
tCYCC
-
-
6.25
-
ns
Base clock (HCLK/FCLK)
tCYCP0
tCYCP1
-
-
12.5
6.25
-
ns
ns
APB0 bus clock*
2
APB1 bus clock*
tCYCP2
-
-
12.5
-
ns
APB2 bus clock*
2
2
2
2
*1: For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part
(002-04856).
*2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this data sheet.
X0
Document Number: 002-04864 Rev. *D
Page 83 of 170
MB9B560R Series
12.4.2 Sub Clock Input Characteristics
(VBAT = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Input frequency
1/ tCYLL
Input clock cycle
tCYLL
Input clock pulse width
-
Pin
Name
X0A,
X1A
Value
Conditions
Min
Typ
Unit
Max
Remarks
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
-
10
-
31.25
μs
When using external clock
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external clock
0.8 × VBAT
VBAT
VBAT
VBAT
VBAT
X0A
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
TJ = -20°C to +105°C
Clock frequency
Value
Conditions
Min
3.92
Typ
4
Max
Unit
Remarks
4.08
When trimming*1
fCRH
TJ = - 40°C to +125°C
3.88
4
4.12
Clock frequency
fCRH
TJ = - 40°C to +125°C
3
4
5
Frequency
stabilization
time
tCRWT
-
-
-
30
MHz
When not trimming
*2
μs
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.
This period is able to use high-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Clock frequency
Symbol
fCRL
Condition
-
Document Number: 002-04864 Rev. *D
Value
Min
50
Typ
100
Max
150
Unit
Remarks
kHz
Page 84 of 170
MB9B560R Series
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
Value
Symbol
Min
Typ
Unit
Max
tLOCK
200
-
-
μs
fPLLI
fPLLO
fCLKPLL
4
13
200
-
-
16
80
320
160
MHz
multiplier
MHz
MHz
Remarks
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4 Family Peripheral Manual Main part
(002-04856).
12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Min
Typ
Unit
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
4
-
16
MHz
PLL multiplication rate
-
13
-
80
multiplier
PLL macro oscillation clock frequency
fPLLO
200
-
320
MHz
fCLKSPLL
-
-
48
MHz
USB clock frequency*
2
Remarks
After the M frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM4 Family Peripheral Manual
Communication Macro part (002-04856).
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
Symbol
Value
Min
Typ
Unit
Max
tLOCK
200
-
-
μs
fPLLI
fPLLO
fCLKPLL
3.8
50
190
-
4
-
4.2
75
320
160
MHz
multiplier
MHz
MHz
Remarks
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part
(002-04856).
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has
been trimmed.
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MB9B560R Series
12.4.7 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Reset input time
tINITX
Pin
Name
Value
Condition
INITX
-
Min
Unit
Max
500
-
Remarks
ns
12.4.8 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Power supply shut down time
Time until releasing Power-on reset
Value
Conditions
VCC
Unit
Min
Typ
Max
-
50
-
-
VCC: 0.2V to 2.70V
1.3
-
1000
-
0.33
-
0.60
tOFF
dV/dt
Power ramp rate
Pin
Name
tPRT
ms
Remarks
*1
mV/µs *2
ms
*1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50ms).
Note:
− If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 7.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.8. Low-Voltage Detection Characteristics”.
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MB9B560R Series
12.4.9 GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Output frequency
Symbol
tPCYCLE
Pin Name
Pxx*
Value
Conditions
Min
Unit
Max
VCC ≥ 4.5 V
-
50
MHz
VCC < 4.5 V
-
32
MHz
*: GPIO is a target.
Pxx
tPCYCLE
12.4.10 External Bus Timing
External Bus Clock Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Output frequency
Symbol
tCYCLE
Pin Name
1
MCLKOUT*
Value
Conditions
Min
Unit
Max
2
MHz
3
MHz
VCC ≥ 4.5 V
-
50*
VCC < 4.5 V
-
32*
*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see CHAPTER 14: External Bus Interface in FM4 Family Peripheral Manual
Main part (002-04856).
*2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100 MHz.
*3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64 MHz.
0.8 × Vcc
0.8 × Vcc
MCLK
tCYCLE
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MB9B560R Series
External Bus Signal Input/output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
VIH
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
Remarks
Signal input characteristics
VIL
Signal output characteristics
Signal input
VIH
VIL
VIH
VIL
Signal output
VOH
VOL
VOH
VOL
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MB9B560R Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
MOEX
Mininum pulse width
MCSX↓→Address output
delay time
MOEX↑→Address hold time
MCSX↓→
MOEX↓ delay time
MOEX↑→
MCSX↑ time
MCSX↓→MDQM↓
delay time
Data set up→MOEX↑ time
MOEX↑→
Data hold time
MWEX
Mininum pulse width
MWEX↑→Address output
delay time
Symbol
tOEW
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
tDH - OE
MOEX
MCSX[7:0],
MAD[24:0]
MOEX,
MAD[24:0]
MOEX,
MCSX[7:0]
MCSX,
MDQM[1:0]
MOEX,
MADATA[15:0]
MOEX,
MADATA[15:0]
tWEW
MWEX
tWEH - AX
MWEX,
MAD[24:0]
MCSX↓→MWEX↓ delay time
tCSL - WEL
MWEX↑→MCSX↑ delay time
tWEH - CSH
MCSX↓→MDQM↓ delay time
tCSL-WDQML
MWEX↓→
Data output time
MWEX↑→
Data hold time
Pin Name
tCSL-DX
tWEH - DX
MWEX,
MCSX[7:0]
MCSX,
MDQM[1:0]
MCSX,
MADATA[15:0]
MWEX,
MADATA[15:0]
Value
Conditions
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
VCC ≥ 4.5V
VCC < 4.5V
Min
Max
Unit
MCLK×n-3
-
-9
-12
MCLK×m-9
MCLK×m-12
20
38
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
0
-
ns
MCLK×n-3
-
ns
0
MCLK×m-9
MCLK×m-12
0
0
MCLK×n-9
MCLK×n-12
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCLK-12
0
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
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MB9B560R Series
tCYCLE
MCLK
tOEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
MOEX
tWEH-CSH
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
tCSL-WEL
MDQM[1:0]
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DX
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MB9B560R Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Address delay time
Symbol
tAV
tCSL
MCSX delay time
Pin Name
MCLK,
MAD[24:0]
tCSH
tREL
MOEX delay time
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK,
MCSX[7:0]
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK,
MOEX
tREH
Value
Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Min
1
1
1
1
1
Data set up
→MCLK↑ time
tDS
MCLK,
MADATA[15:0]
VCC ≥ 4.5 V
19
VCC < 4.5 V
37
MCLK↑→
Data hold time
tDH
MCLK,
MADATA[15:0]
VCC ≥ 4.5 V
tWEL
MWEX delay time
VCC ≥ 4.5 V
MCLK,
MWEX
tWEH
MDQM[1:0]
delay time
tDQML
VCC < 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK,
MDQM[1:0]
tDQMH
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
MCLK↑→
Data output time
tODS
MCLK,
MADATA[15:0]
VCC ≥ 4.5 V
MCLK↑→
Data hold time
tOD
MCLK,
MADATA[15:0]
VCC ≥ 4.5 V
VCC < 4.5 V
VCC < 4.5 V
0
1
1
1
1
MCLK+1
1
Unit
Max
9
12
9
12
9
12
9
12
9
12
ns
ns
ns
ns
ns
-
ns
-
ns
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance CL = 30 pF
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MB9B560R Series
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
MAD[24:0]
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
tDS
tDH
RD
tOD
WD
Invalid
MADATA[15:0]
tODS
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MB9B560R Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Multiplexed address delay time
tALE-CHMADV
Pin Name
VCC ≥ 4.5 V
MALE,
MADATA[15:0]
Multiplexed address hold time
tCHMADH
Value
Conditions
VCC < 4.5 V
Min
0
Unit
Max
10
20
VCC ≥ 4.5 V
MCLK×n+0
MCLK×n+10
VCC < 4.5 V
MCLK×n+0
MCLK×n+20
ns
ns
Note:
−
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
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MB9B560R Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK↑→
Multiplexed address delay time
Pin Name
MCLK,
ALE
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Min
Max
Unit
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Remarks
VCC ≥ 4.5 V
tCHMADV
MCLK,
MADATA[15:0]
MCLK↑→
Multiplexed data output time
Value
VCC < 4.5 V
VCC ≥ 4.5 V
tCHMADX
VCC < 4.5 V
Note:
−
When the external load capacitance CL = 30 pF
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
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MB9B560R Series
NAND Flash Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
MNREX
Min pulse width
Data set up
→MNREX↑ time
MNREX↑→
Data hold time
MNALE↑→
MNWEX delay time
MNALE↓→
MNWEX delay time
MNCLE↑→
MNWEX delay time
MNWEX↑→
MNCLE delay time
MNWEX
Min pulse width
MNWEX↓→
Data output time
MNWEX↑→
Data hold time
Symbol
tNREW
tDS – NRE
tDH – NRE
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
tNWEL – DV
tNWEH – DX
Pin Name
MNREX
MNREX,
MADATA[15:0]
MNREX,
MADATA[15:0]
MNALE,
MNWEX
MNALE,
MNWEX
MNCLE,
MNWEX
MNCLE,
MNWEX
MNWEX
MNWEX,
MADATA[15:0]
MNWEX,
MADATA[15:0]
Value
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Min
Max
Unit
MCLK×n-3
-
ns
20
38
-
ns
0
-
ns
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
0
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
0
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
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MB9B560R Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
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Page 96 of 170
MB9B560R Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
MCLK↑
MRDY input
setup time
tRDYI
Pin Name
MCLK,
MRDY
Value
Conditions
Min
VCC ≥ 4.5 V
19
VCC < 4.5 V
37
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycle
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
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MB9B560R Series
SDRAM Mode
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Value
Pin Name
Min
Unit
Max
Output frequency
tCYCSD
MSDCLK
-
32
MHz
Address delay time
tAOSD
MSDCLK,
MAD[15:0]
2
12
ns
MSDCLK↑→Data output delay time
tDOSD
MSDCLK,
MADATA[31:0]
2
12
ns
MSDCLK↑→Data output
Hi-Z time
tDOZSD
MSDCLK,
MADATA[31:0]
2
20
ns
MDQM[1:0] delay time
tWROSD
MSDCLK,
MDQM[1:0]
1
12
ns
MCSX delay time
tMCSSD
MSDCLK,
MCSX8
2
12
ns
MRASX delay time
tRASSD
MSDCLK,
MRASX
2
12
ns
MCASX delay time
tCASSD
MSDCLK,
MCASX
2
12
ns
MSDWEX delay time
tMWESD
MSDCLK,
MSDWEX
2
12
ns
MSDCKE delay time
tCKESD
MSDCLK,
MSDCKE
2
12
ns
Data set up time
tDSSD
MSDCLK,
MADATA[31:0]
23
-
ns
Data hold time
tDHSD
MSDCLK,
MADATA[31:0]
0
-
ns
Note:
−
When the external load capacitance CL = 30 pF
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MB9B560R Series
SDRAM Access
tCYCSD
MSDCLK
tAOSD
MAD[24:0]
MDQM[1:0]
MCSX
MRASX
MCASX
MSDWEX
MSDCKE
Address
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDSSD
MADATA[15:0]
tDOSD
MADATA[15:0]
Document Number: 002-04864 Rev. *D
tDHSD
RD
tDOZSD
WD
Page 99 of 170
MB9B560R Series
12.4.11 Base Timer Input Timing
Timer Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
tTIWH,
tTIWL
Input pulse width
Pin Name
Conditions
TIOAn/TIOBn
(when using as
ECK, TIN)
-
Value
Min
2tCYCP
tTIWH
Unit
Max
-
Remarks
ns
tTIWL
ECK
VIHS
VIHS
VILS
TIN
VILS
Trigger Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
tTRGH,
tTRGL
Input pulse width
Pin Name
Conditions
TIOAn/TIOBn
(when using as
TGIN)
-
2tCYCP
tTRGH
TGIN
VIHS
Value
Min
Unit
Max
-
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet.
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MB9B560R Series
12.4.12 CSIO/UART Timing
Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Baud rate
Serial clock cycle time
tSCYC
-
SCK↓→SOT delay time
tSLOVI
SIN→SCK↑
setup time
tIVSHI
SCK↑→SIN hold time
tSHIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK↓→SOT delay time
tSLOVE
SIN→SCK↑
setup time
tIVSHE
SCK↑→SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
Pin
Name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
-
Internal shift
clock operation
External shift
clock
operation
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
Conditions
-
8
-
8
Unit
4tCYCP
-
4tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
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MB9B560R Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
VIH
SCK
tF
VIL
tSHSL
VIL
SIN
VIH
tR
tSLOVE
SOT
VIH
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 102 of 170
MB9B560R Series
Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Baud rate
Serial clock cycle time
tSCYC
-
SCK↑→SOT delay time
tSHOVI
SIN→SCK↓
setup time
tIVSLI
SCK↓→SIN hold time
tSLIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK↑→SOT delay time
tSHOVE
SIN→SCK↓
setup time
tIVSLE
SCK↓→SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
Pin
Name
Conditions
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
-
Internal shift
clock operation
External shift
clock operation
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
-
8
-
8
Unit
4tCYCP
-
4tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 103 of 170
MB9B560R Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
SCK
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 104 of 170
MB9B560R Series
Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Baud rate
Serial clock cycle time
tSCYC
-
SCK↑→SOT delay time
tSHOVI
SIN→SCK↓
setup time
tIVSLI
SCK↓→SIN hold time
tSLIXI
SOT→SCK↓ delay time
tSOVLI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK↑→SOT delay time
tSHOVE
SIN→SCK↓
setup time
tIVSLE
SCK↓→SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
Pin
Name
SCKx
Conditions
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
-
8
-
8
Unit
4tCYCP
-
4tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 105 of 170
MB9B560R Series
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
MS bit = 0
tSLSH
VIH
VIL
tSHSL
VIH
VIL
SCK
tF
*
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SOT
SIN
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04864 Rev. *D
Page 106 of 170
MB9B560R Series
Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Baud rate
Serial clock cycle time
tSCYC
-
SCK↓→SOT delay time
tSLOVI
SIN→SCK↑
setup time
tIVSHI
SCK↑→SIN hold time
tSHIXI
SOT→SCK↑ delay time
tSOVHI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK↓→SOT delay time
tSLOVE
SIN→SCK↑
setup time
tIVSHE
SCK↑→SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
Pin
Name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
-
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
Conditions
-
8
-
8
Unit
4tCYCP
-
4tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 107 of 170
MB9B560R Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIL
VIH
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 108 of 170
MB9B560R Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
Symbol
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↓setup time
tCSSE
SCK↑→SCS↑ hold time
tCSHE
SCS deselect time
tCSDE
SCS↓→SUT delay time
tDSE
SCS↑→SUT delay time
tDEE
Min
(*1)-50
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
(* )+0
3
Max
(*1)+0
2
(* )+50
3
Min
(*1)-50
2
(* )+0
3
Max
Unit
(*1)+0
ns
(*2)+50
ns
3
(* )-50
+5tCYCP
(* )+50
+5tCYCP
(* )-50
+5tCYCP
(* )+50
+5tCYCP
ns
3tCYCP+30
-
3tCYCP+30
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 109 of 170
MB9B560R Series
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS input
tCSDE
tCSSE
tCSHE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 110 of 170
MB9B560R Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
Symbol
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↑setup time
tCSSE
SCK↓→SCS↑ hold time
tCSHE
SCS deselect time
tCSDE
SCS↓→SOT delay time
tDSE
SCS↑→SOT delay time
tDEE
Min
(*1)-50
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
Max
(*1)+0
2
Min
(*1)-50
2
Max
(*1)+0
2
Unit
ns
(* )+0
(* )+50
(* )+0
(* )+50
ns
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
3tCYCP+30
-
3tCYCP+30
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 111 of 170
MB9B560R Series
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 112 of 170
MB9B560R Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
Symbol
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↓setup time
tCSSE
SCK↑→SCS↓ hold time
tCSHE
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
SCS↓→SOT delay time
tDEE
Min
(*1)-50
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
Max
(*1)+0
2
Min
(*1)-50
2
Max
(*1)+0
2
Unit
ns
(* )+0
(* )+50
(* )+0
(* )+50
ns
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
3tCYCP+30
-
3tCYCP+30
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 113 of 170
MB9B560R Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 114 of 170
MB9B560R Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
Symbol
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↑setup time
tCSSE
SCK↓→SCS↓ hold time
tCSHE
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
SCS↓→SOT delay time
tDEE
Min
(*1)-50
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
Max
(*1)+0
2
Min
(*1)-50
2
Max
(*1)+0
2
Unit
ns
(* )+0
(* )+50
(* )+0
(* )+50
ns
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
3tCYCP+30
-
3tCYCP+30
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 115 of 170
MB9B560R Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 116 of 170
MB9B560R Series
High-speed Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
Name
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Min
Max
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
-
12.5
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
5
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
5
-
5
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Internal shift
clock operation
14
12.5*
External shift
clock operation
SCKx,
SINx
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins.
No chip select:
Chip select:
−
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04864 Rev. *D
Page 117 of 170
MB9B560R Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tF
VIL
tSHSL
VIL
SIN
VIH
tR
tSLOVE
SOT
VIH
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 118 of 170
MB9B560R Series
High-speed Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
Name
Serial clock cycle time
tSCYC
SCKx
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
Internal shift
clock operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
Min
Max
Min
Max
Unit
4tCYCP
-
4tCYCP
-
ns
-10
+10
-10
+10
ns
-
12.5
-
ns
14
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
5
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
5
-
5
-
ns
12.5*
External shift
clock operation
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins.
No chip select:
Chip select:
−
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04864 Rev. *D
Page 119 of 170
MB9B560R Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 120 of 170
MB9B560R Series
High-speed Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin
Name
Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Min
Min
Max
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
-
12.5
-
ns
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP – 10
-
2tCYCP – 10
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
5
-
5
-
ns
Internal shift
clock operation
14
12.5*
External shift
clock operation
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins.
No chip select:
Chip select:
−
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04864 Rev. *D
Page 121 of 170
MB9B560R Series
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
MS bit = 0
tSLSH
VIH
SCK
VIH
VIL
tF
*
SOT
VIL
tSHSL
tR
VIH
tSHOVE
VOH
VOL
SIN
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04864 Rev. *D
Page 122 of 170
MB9B560R Series
High-speed Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Min
Min
Symbol
Pin Name
Internal shift clock operation
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
-10
+10
-10
+10
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
-
12.5
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP – 10
-
2tCYCP – 10
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
5
-
ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Internal shift
clock
operation
External shift
clock
operation
Max
Max
Unit
14
12.5*
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins.
No chip select:
Chip select:
−
SIN4_1, SOT4_1, SCK4_1
SIN6_1, SOT6_1, SCK6_1, SCS6_1
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04864 Rev. *D
Page 123 of 170
MB9B560R Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIL
VIH
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 124 of 170
MB9B560R Series
When Using High-speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
Symbol
tCSHI
Min
(*1)-20
tCSSI
Internal shift
clock operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
(* )+0
3
Max
(*1)+0
2
(* )+20
3
Min
(*1)-20
2
(* )+0
3
Max
Unit
(*1)+0
ns
(*2)+20
ns
3
SCS deselect time
tCSDI
(* )-20
+5tCYCP
(* )+20
+5tCYCP
(* )-20
+5tCYCP
(* )+20
+5tCYCP
ns
SCS↓→SCK↓setup time
tCSSE
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
External shift
clock operation
SCS deselect time
tCSDE
3tCYCP+15
-
3tCYCP+15
-
ns
SCS↓→SOT delay time
tDSE
-
25
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual.
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 125 of 170
MB9B560R Series
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS input
tCSDE
tCSSE
tCSHE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 126 of 170
MB9B560R Series
When Using High-speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
Symbol
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↑setup time
tCSSE
SCK↓→SCS↑ hold time
tCSHE
SCS deselect time
tCSDE
SCS↓→SOT delay time
tDSE
SCS↑→SOT delay time
tDEE
Min
(*1)-20
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
(* )+0
3
Max
(*1)+0
2
(* )+20
3
Min
(*1)-20
2
(* )+0
3
Max
Unit
(*1)+0
ns
(*2)+20
ns
3
(* )-20
+5tCYCP
(* )+20
+5tCYCP
(* )-20
+5tCYCP
(* )+20
+5tCYCP
ns
3tCYCP+15
-
3tCYCP+15
-
ns
0
-
0
-
ns
3tCYCP+15
-
3tCYCP+15
-
ns
-
25
-
25
ns
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 127 of 170
MB9B560R Series
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS input
tCSDE
tCSHE
tCSSE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 128 of 170
MB9B560R Series
When Using High-speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
Symbol
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↓setup time
tCSSE
SCK↑→SCS↓ hold time
tCSHE
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
SCS↓→SOT delay time
tDEE
Min
(*1)-20
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
Max
(*1)+0
2
Min
(*1)-20
2
Max
(*1)+0
2
Unit
ns
(* )+0
(* )+20
(* )+0
(* )+20
ns
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
3tCYCP+15
-
3tCYCP+15
-
ns
0
-
0
-
ns
3tCYCP+15
-
3tCYCP+15
-
ns
-
25
-
25
ns
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 129 of 170
MB9B560R Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 130 of 170
MB9B560R Series
When Using High-speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
Symbol
tCSSI
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↑setup time
tCSSE
SCK↓→SCS↓ hold time
tCSHE
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
SCS↓→SOT delay time
tDEE
Min
(*1)-20
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5 V
VCC < 4.5 V
Conditions
2
Max
(*1)+0
2
Min
(*1)-20
2
Max
(*1)+0
2
Unit
ns
(* )+0
(* )+20
(* )+0
(* )+20
ns
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
3tCYCP+15
-
3tCYCP+15
-
ns
0
-
0
-
ns
3tCYCP+15
-
3tCYCP+15
-
ns
-
25
-
25
ns
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 002-04864 Rev. *D
Page 131 of 170
MB9B560R Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04864 Rev. *D
Page 132 of 170
MB9B560R Series
External Clock (EXT = 1): when in Asynchronous Mode Only
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
Condition
SCK
Document Number: 002-04864 Rev. *D
VIL
Min
tCYCP + 10
tCYCP + 10
-
CL = 30 pF
tR
Value
5
5
tSHSL
VIH
Unit
Max
ns
ns
ns
ns
tF
tSLSH
VIH
VIL
Remarks
VIL
VIH
Page 133 of 170
MB9B560R Series
12.4.13 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Min
Max
Unit
ADTG
Input pulse
width
tINH,
tINL
FRCKx
ICxx
DTTIxX
INT00 to INT31,
NMIX
WKUPx
Remarks
A/D converter trigger input
1
-
2tCYCP*
-
2tCYCP*
1
2tCYCP + 100 *
2
500 *
3
500 *
-
1
-
ns
-
ns
ns
ns
ns
Free-run timer input clock
Input capture
Waveform generator
External interrupt,
NMI
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode.
About the APB bus number which the A/D converter, multi-function timer, external interrupt are connected to, see 8. Block
Diagram in this data sheet.
*2: When in Stop mode, in timer mode.
*3: When in deep standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-04864 Rev. *D
Page 134 of 170
MB9B560R Series
12.4.14 Quadrature Position/Revolution Counter Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
AIN pin H width
AIN pin L width
BIN pin H width
BIN pin L width
BIN rising time from
AIN pin H level
AIN falling time from
BIN pin H level
BIN falling time from
AIN pin L level
AIN rising time from
BIN pin L level
AIN rising time from
BIN pin H level
BIN falling time from
AIN pin H level
AIN falling time from
BIN pin L level
BIN rising time from
AIN pin L level
ZIN pin H width
ZIN pin L width
AIN/BIN rising and falling time from
determined ZIN level
Determined ZIN level from AIN/BIN rising
and falling time
Value
Conditions
Min
tAHL
tALL
tBHL
tBLL
-
tAUBU
PC_Mode2 or PC_Mode3
tBUAD
PC_Mode2 or PC_Mode3
tADBD
PC_Mode2 or PC_Mode3
tBDAU
PC_Mode2 or PC_Mode3
tBUAU
PC_Mode2 or PC_Mode3
tAUBD
PC_Mode2 or PC_Mode3
tBDAD
PC_Mode2 or PC_Mode3
tADBU
PC_Mode2 or PC_Mode3
tZHL
tZLL
QCR:CGSC = 0
QCR:CGSC = 0
tZABE
QCR:CGSC = 1
tABEZ
QCR:CGSC = 1
2tCYCP*
Max
-
Unit
ns
*: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8. Block Diagram in this data
sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-04864 Rev. *D
tBLL
Page 135 of 170
MB9B560R Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-04864 Rev. *D
Page 136 of 170
MB9B560R Series
2
12.4.15 I C Timing
Standard-mode, Fast-mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
SCL clock "L" width
SCL clock "H" width
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Noise filter
Symbo
l
Standard-mode
Min
Max
Conditions
Fast-mode
Min
Max
Unit
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*
0
0.9*
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
4
-
2tCYCP*
4
-
ns
4
-
4tCYCP*
4
-
ns
4
-
6tCYCP*
4
-
ns
4
-
8tCYCP*
4
-
ns
-
10tCYCP*
-
ns
-
12tCYCP*
-
ns
4
-
14tCYCP*
4
-
ns
4
-
16tCYCP*
4
-
ns
tSUSTA
tHDDAT
tSP
CL = 30 pF,
1
R = (Vp/IOL)*
2 MHz ≤
tCYCP LDC144
Changed the mode name of I2C as follows (Page 2, 137-138)
Typical mode -> Standard-mode, High-speed mode -> Fast-mode
Modified from “Analog port input current” to “Analog port input leak current” in “12.5
12-bit A/D Converter” (Page 144)
Modified according to the Datasheet Errata as below
Modified the “sampling time” and “State transition time to operation permission” spec
values in “12.5 12-bit A/D Converter” (Page 144)
Deleted descriptions about Voice function(Page 4)
Removed "MB9BF568F" in the document(Page 7,8)
Document Number: 002-04864 Rev. *D
Page 168 of 170
MB9B560R Series
Deleted MPN below from “13. Ordering Information” (Page 158)
MB9BF568FBGL-000GE1
MB9BF566RBGL-GE1, MB9BF567RBGL-GE1, MB9BF568RBGL-GE1
Added MPNs below to “13. Ordering Information” (Page 158)
MB9BF566RBGL-GK7E1, MB9BF567RBGL-GK7E1, MB9BF568RBGL-GK7E1
Change the name from “USB Function” to “USB Device” (Page 1, 7, 41)
Updated IO circuit (type A, N, O) (Page 44)
Modified the expression of the “Reference power supply current” “12.5 12-bit A/D
Converter” (Page 144)
Modified the expression of the “Built-in CR” and add Note in the “1. Product
Lineup”(Page 7)
Modified typo(SCLKx_0 -> SCKx_0)(Page 101, 103, 105, 107)
Updated Package Dimensions:
*C
5727772
HARA
05/05/2017
spec 002-11500 – Changed revision from ** to *A.
Updated to new template.
*D
5873294
HUAL
Document Number: 002-04864 Rev. *D
09/25/2017
Fix minor issues listed in CDT 270742:
x
1.new note format had been updated from *x to *
2.change “FM4 Family Peripheral Manual Main Part (002-04857)” to “FM4
Family Peripheral Manual Main Part (002-04856)”.
3.change “(MN709-00001)” to “(002-04856)”.
Page 169 of 170
MB9B560R Series
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OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It
is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this informati on and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the
failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress
from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs,
damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04864 Rev. *D
September 25, 2017
Page 170 of 170
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