Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY9BD10T Series
32-bit Arm® Cortex®-M3
FM3 Microcontroller
The CY9BD10T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
competitive cost.
These series are based on the Arm® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN, Ethernet-MAC).
The products which are described in this datasheet are placed into TYPE 2 product categories in "FM3 Family Peripheral Manual".
Features
[USB device]
◼ USB2.0 Full-Speed supported
◼ Max 6 EndPoint supported
32-bit Arm® Cortex®-M3 Core
◼ Processor version: r2p1
◼ Up to 144 MHz Frequency Operation
EndPoint
◼ Memory Protection Unit (MPU): improves the reliability of an
embedded system
◼ Integrated Nested Vectored Interrupt Controller (NVIC):
1 NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
◼ 24-bit System timer (Sys Tick): System timer for OS task
management
0 is control transfer
1, 2 can be selected Bulk-transfer, Interrupttransfer or Isochronous-transfer
EndPoint 3 to 5 can be selected Bulk-transfer or Interrupttransfer
EndPoint 1 to 5 is comprised Double Buffers
• Endpoint 0, 2 to 5: 64 bytes
• Endpoint 1: 256 bytes
EndPoint
[USB host]
◼ USB2.0 Full/Low-speed supported
◼ Bulk-transfer, interrupt-transfer and Isochronous-transfer
On-chip Memories
[Flash memory]
support
◼ Up to 1 MB
◼ Built-in Flash Accelerator System with 16 KB trace buffer
memory
The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at the
operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
◼ Security function for code protection
◼ USB Device connected/dis-connected automatically detect
◼ IN/OUT token handshake packet automatically
◼ Max 256-byte packet-length supported
◼ Wake-up function supported
CAN Interface (Max 2 channels)
◼ Compatible with CAN Specification 2.0A/B
◼ Maximum transfer rate: 1 Mbps
[SRAM]
This Series contain a total of up to 128 KB on-chip SRAM.
This is composed of two independent SRAM (SRAM0,
SRAM1). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M3 core. SRAM1 is connected to System bus.
◼ SRAM0: Up to 64 KB
◼ SRAM1: Up to 64 KB
◼ Built-in 32 message buffer
Ethernet - MAC (Max 2 channels)
◼ Compliant with IEEE802.3 specification
◼ 10 Mbps / 100 Mbps data transfer rates supported
◼ MII/RMII for external PHY device supported.
MII:
USB Interface (Max 2 channels)
USB interface is composed of Device and Host.
PLL for USB/Ethernet is built-in, USB clock or Ethernet clock
can be generated by multiplication of Main clock.
Max 1 channel
Max 2 channels
RMII:
◼ Full-Duplex and Half-Duplex mode supported.
◼ Wake-ON-LAN supported
◼ Built-in dedicated descriptor-system DMAC
◼ Built-in 2 KB Transmit FIFO and 2 KB Receive FIFO.
◼ Compliant IEEE1588-2008 (PTP)
PLL for USB/Ethernet is built-in, USB clock or Ethernet clock
can be generated by multiplication of Main clock.
Cypress Semiconductor Corporation
2600
Document Number: 002-05629 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-
Revised May 27, 2020
CY9BD10T Series
Multi-function Serial Interface (Max 8 channels)
DMA Controller (8 channels)
◼ 4 channels with 16 steps × 9-bit FIFO (ch.4 to ch.7),
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
4 channels without FIFO (ch.0 to ch.3)
◼ Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I2 C
[UART]
◼ Full duplex double buffer
◼ Selection with or without parity supported
◼ Built-in dedicated baud rate generator
◼ 8 independently configured and operated channels
◼ Transfer can be started by software or request from the builtin peripherals
◼ Transfer address area: 32-bit (4 GB)
◼ Transfer mode: Block transfer/Burst transfer/Demand
transfer
◼ Transfer data type: byte/half-word/word
◼ Transfer block count: 1 to 16
◼ Number of transfers: 1 to 65536
◼ External clock available as a serial clock
A/D Converter (Max 32 channels)
◼ Hardware Flow control: Automatically control the
[12-bit A/D Converter]
transmission by CTS/RTS (only ch.4)
◼ Various error detect functions available (parity errors,
framing errors, and overrun errors)
◼ Successive Approximation Register type
◼ Built-in 3 unit
[CSIO]
◼ Conversion time: 1.0 μs @ 5 V
◼ Full duplex double buffer
◼ Priority conversion available (priority at 2 levels)
◼ Built-in dedicated baud rate generator
◼ Scanning conversion mode
◼ Overrun error detect function available
◼ Built-in FIFO for conversion data storage (for SCAN
[LIN]
◼ LIN protocol Rev.2.1 supported
◼ Full duplex double buffer
◼ Master/Slave mode supported
◼ LIN break field generate (can be changed 13 to 16-bit
length)
◼ LIN break delimiter generate (can be changed 1 to 4-bit
length)
◼ Various error detect functions available (parity errors,
conversion: 16 steps, for Priority conversion:
4 steps)
Base Timer (Max 16 channels)
Operation mode is selectable from the followings for each
channel.
◼ 16-bit PWM timer
◼ 16-bit PPG timer
◼ 16-/32-bit reload timer
◼ 16-/32-bit PWC timer
framing errors, and overrun errors)
Multi-function Timer (Max 3 units)
2
[I C]
The Multi-function timer is composed of the following blocks.
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
◼ 16-bit free-run timer × 3ch./unit
External Bus Interface
◼ Output compare × 6ch./unit
◼ Supports SRAM, NOR and NAND Flash device
◼ A/D activation compare × 3ch./unit
◼ Up to 8 chip selects
◼ Waveform generator × 3ch./unit
◼ 8-/16-bit Data width
◼ 16-bit PPG timer × 3ch./unit
◼ Input capture × 4ch./unit
◼ Up to 25-bit Address bit
◼ Maximum area size: Up to 256 MB
◼ Supports Address/Data multiplex
◼ Supports external RDY input
Document Number: 002-05629 Rev. *H
Page 2 of 133
CY9BD10T Series
The following function can be used to achieve the motor
control.
General Purpose I/O Port
◼ DC chopper waveform output function
This series can use its pins as General Purpose I/O ports
when they are not used for external bus or peripherals.
Moreover, the port relocate function is built in. It can set which
I/O port the peripheral function can be allocated.
◼ Dead time function
◼ Capable of pull-up control per pin
◼ Input capture function
◼ Capable of reading pin level directly
◼ A/D convertor activate function
◼ Built-in the port relocate function
◼ DTIF (Motor emergency stop) interrupt function
◼ Up 154 fast General Purpose I/O Ports @ 176 pin Package
Quadrature Position/Revolution Counter (QPRC)
(Max 3 channels)
◼ Some pin is 5 V tolerant I/O.
◼ PWM signal output function
See "Pin Description" to confirm the corresponding pins.
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
External Interrupt Controller Unit
◼ The detection edge of the three external event input pins
◼ Include one non-maskable interrupt (NMI)
◼ 16-bit position counter
CRC (Cyclic Redundancy Check) Accelerator
◼ Up to 32 external interrupt input pin
AIN, BIN and ZIN is configurable.
◼ 16-bit revolution counter
The CRC accelerator helps a verify data transmission or
storage integrity.
◼ Two 16-bit compare registers
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Dual Timer (32-/16-bit Down Counter)
◼ CCITT CRC16 Generator Polynomial: 0x1021
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
◼ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
◼ Free-running
◼ Periodic (=Reload)
Five clock sources (2 external oscillator, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
◼ One-shot
◼ Main Clock:
4 MHz to 50 MHz
◼ Sub Clock:
32.768 kHz
◼ High-speed internal CR Clock:
4 MHz
◼ Low-speed internal CR Clock:
100 kHz
Watch Counter
The Watch counter is used for wake up from Low Power
Consumption mode.
Clock and Reset
[Clocks]
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
◼ Main PLL Clock
Watchdog Timer (2 channels)
[Resets]
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP mode.
◼ Reset requests from INITX pin
◼ Power on reset
◼ Software reset
◼ Watchdog timers reset
◼ Low-voltage detector reset
◼ Clock supervisor reset
Document Number: 002-05629 Rev. *H
Page 3 of 133
CY9BD10T Series
Clock Super Visor (CSV)
Debug
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
◼ Serial Wire JTAG Debug Port (SWJ-DP)
◼ External OSC clock failure (clock stop) is detected, reset is
◼ Embedded Trace Macrocells (ETM) provide comprehensive
◼ External OSC frequency anomaly is detected, interrupt or
Power Supply
asserted.
reset is asserted.
debug and trace facilities.
Four Power Supplies
Low-Voltage Detector (LVD)
◼ Wide range voltage:
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
◼ I/O voltage for USB ch.0: USBVCC0
= 3.0 V to 3.6 V
(when USB ch.0 is
used)
= 2.7 V to 5.5 V
(when GPIO is
used)
◼ I/O voltage for USB ch.1: USBVCC1
= 3.0 V to 3.6 V
(when USB ch.1 is
used)
= 2.7 V to 5.5 V
(when GPIO is
used)
◼ I/O voltage for Ethernet: ETHVCC
= 3.0 V to 5.5 V
(when Ethernet is
used)
= 2.7 V to 5.5 V
(when GPIO is
used)
VCC
◼ LVD1: error reporting via interrupt
◼ LVD2: auto-reset operation
Low Power Mode
Three Low Power Consumption modes supported.
◼ SLEEP
◼ TIMER
◼ STOP
Document Number: 002-05629 Rev. *H
= 2.7 V to 5.5 V
Page 4 of 133
CY9BD10T Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type ............................................................................................................................................................... 51
6. Handling Precautions ..................................................................................................................................................... 57
6.1
Precautions for Product Design ................................................................................................................................... 57
6.2
Precautions for Package Mounting .............................................................................................................................. 58
6.3
Precautions for Use Environment ................................................................................................................................ 59
7. Handling Devices ............................................................................................................................................................ 60
8. Block Diagram ................................................................................................................................................................. 63
9. Memory Size .................................................................................................................................................................... 64
10. Memory Map .................................................................................................................................................................... 64
11. Pin Status in Each CPU State ........................................................................................................................................ 67
12. Electrical Characteristics ............................................................................................................................................... 71
12.1 Absolute Maximum Ratings ......................................................................................................................................... 71
12.2 Recommended Operating Conditions ......................................................................................................................... 73
12.3 DC Characteristics ...................................................................................................................................................... 75
12.3.1 Current Rating .............................................................................................................................................................. 75
12.3.2 Pin Characteristics ....................................................................................................................................................... 77
12.4 AC Characteristics ....................................................................................................................................................... 79
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 79
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 80
12.4.3 Internal CR Oscillation Characteristics ......................................................................................................................... 81
12.4.4 Operating Conditions of Main and USB/Ethernet PLL (In the case of using main clock for input of PLL) .................... 82
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed internal CR) ............................................ 82
12.4.6 Reset Input Characteristics .......................................................................................................................................... 83
12.4.7 Power-on Reset Timing ................................................................................................................................................ 83
12.4.8 External Bus Timing ..................................................................................................................................................... 84
12.4.9 Base Timer Input Timing .............................................................................................................................................. 93
12.4.10 CSIO/UART Timing .................................................................................................................................................. 94
12.4.11 External Input Timing .............................................................................................................................................. 102
12.4.12 Quadrature Position/Revolution Counter timing ...................................................................................................... 103
12.4.13 I2C Timing ............................................................................................................................................................... 105
12.4.14 ETM Timing ............................................................................................................................................................ 106
12.4.15 JTAG Timing........................................................................................................................................................... 107
12.4.16 Ethernet-MAC Timing ............................................................................................................................................. 108
12.5 12-bit A/D Converter .................................................................................................................................................. 113
12.6 USB characteristics ................................................................................................................................................... 116
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 120
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 120
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 120
12.8 Flash Memory Write/Erase Characteristics ............................................................................................................... 121
12.8.1 Write / Erase time....................................................................................................................................................... 121
12.8.2 Write cycles and data hold time ................................................................................................................................. 121
12.9 Return Time from Low-Power Consumption Mode .................................................................................................... 122
12.9.1 Return Factor: Interrupt .............................................................................................................................................. 122
Document Number: 002-05629 Rev. *H
Page 5 of 133
CY9BD10T Series
12.9.2 Return Factor: Reset .................................................................................................................................................. 124
13. Ordering Information .................................................................................................................................................... 126
14. Package Dimensions .................................................................................................................................................... 127
15. Major Changes .............................................................................................................................................................. 130
Document History ............................................................................................................................................................... 132
Sales, Solutions, and Legal Information ........................................................................................................................... 133
Document Number: 002-05629 Rev. *H
Page 6 of 133
CY9BD10T Series
1. Product Lineup
Memory Size
CY9BFD16S
CY9BFD16T
Product name
On-chip Flash memory
On-chip RAM
512 KB
64 KB
CY9BFD17S
CY9BFD17T
CY9BFD18S
CY9BFD18T
768 KB
96 KB
1 MB
128 KB
Function
CY9BFD16S
CY9BFD17S
CY9BFD18S
Product name
Pin count
CPU
144
Cortex-M3
144 MHz
VCC: 2.7 V to 5.5 V
(USBVCC0: 3.0 V to 3.6 V)
(USBVCC1: 3.0 V to 3.6 V)
(ETHVCC: 3.0 V to 5.5 V)
2ch. (Max)
2ch. (Max)
2ch. (Max) MII: 1ch. / RMII: 2ch.(Max)
8ch.
Addr: 19-bit (Max)
R/Wdata: 8-/16-bit (Max)
CS: 8 (Max)
Support: SRAM, NOR & NAND Flash
8ch. (Max)
ch.4 to ch.7: FIFO (16 steps × 9-bit)
ch.0 to ch.3: No FIFO
Freq.
Power supply voltage range
USB2.0 (Device/Host)
CAN
Ethernet-MAC
DMAC
External Bus Interface
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
MFTimer
176/192
Addr: 25-bit (Max)
R/Wdata :8-/16-bit (Max)
CS: 8 (Max)
Support: SRAM, NOR & NAND Flash
16ch. (Max)
A/D activation compare
3ch.
Input capture
Free-run timer
Output compare
Waveform generator
PPG
4ch.
3ch.
6ch.
3ch.
3ch.
QPRC
Dual Timer
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
CY9BFD16T
CY9BFD17T
CY9BFD18T
3 units (Max)
3ch. (Max)
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
32 pins (Max)+ NMI × 1
122 pins (Max)
24ch. (3 units)
Yes
2ch.
4 MHz
100 kHz
SWJ-DP/ETM
154 pins (Max)
32ch. (3 units)
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Internal CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-05629 Rev. *H
Page 7 of 133
CY9BD10T Series
2. Packages
Package
Product name
CY9BFD16S
CY9BFD17S
CY9BFD18S
CY9BFD16T
CY9BFD17T
CY9BFD18T
LQFP: LQS144 (0.5mm pitch)
-
LQFP: LQP176 (0.5mm pitch)
-
BGA: LBE192 (0.8mm pitch)
-
: Supported
Note:
−
See “14. Package Dimensions” for detailed information on each package.
Document Number: 002-05629 Rev. *H
Page 8 of 133
CY9BD10T Series
3. Pin Assignment
LQP176
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
P90/TIOB08_0/RTO20_1/INT30_0/MAD19_0
P91/TIOB09_0/RTO21_1/INT31_0/MAD20_0
P92/TIOB10_0/RTO22_1/SIN5_1/MAD21_0
P93/TIOB11_0/RTO23_1/SOT5_1/MAD22_0
P94/TIOB12_0/RTO24_1/SCK5_1/INT26_0/MAD23_0
P95/TIOB13_0/RTO25_1/INT27_0/MAD24_0
PC0/E_RXER0_RXDV1
PC1/E_RX03_RX11
PC2/E_RX02_RX10
PC3/E_RX01/TIOA06_1
PC4/E_RX00/TIOA08_2
PC5/E_RXDV0/TIOA10_2
PC6/E_MDIO0/TIOA14_0
PC7/E_MDC0/CROUT_1
PC8/E_RXCK0_REFCK
PC9/E_COL0
PCA/E_CRS0
ETHVCC
VSS
PCB/E_COUT
PCC/E_MDIO1
PCD/E_TCK0_MDC1
PCE/E_TXER0_TXEN1/RTS4_0/TIOB06_1
PCF/E_TX03_TX11/CTS4_0/TIOB08_2
PD0/E_TX02_TX10/SCK4_0/TIOB10_2/INT30_1
PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1
PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2
PD3/E_TXEN0/TIOB03_2
P62/E_PPS0_PPS1/SCK5_0/ADTG_3
P61/SOT5_0/TIOB02_2/UHCONX0
P60/SIN5_0/TIOA02_2/INT15_1
PF3/TIOA06_0/SIN6_2/INT06_0/AIN2_1
PF4/TIOB06_0/SOT6_2/INT07_0/BIN2_1
PF5/SCK6_2/INT08_0/ZIN2_1
USBVCC0
P80/UDM0
P81/UDP0
VCC
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VSS
(TOP VIEW)
VCC
1
132
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
131
P83/UDP1
PA1/RTO21_0/TIOA09_0/IC10_0
3
130
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
129
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
128
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0
6
127
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2
7
126
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
125
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
124
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
123
P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
122
P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
121
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
120
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
119
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
118
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
117
PB7/AN23/TIOB12_1/INT23_0/ZIN2_2
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
116
PB6/AN22/TIOA12_1/SCK0_2/INT22_0/BIN2_2
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
115
PB5/AN21/TIOB11_1/SOT0_2/INT21_0/AIN2_2
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
114
PB4/AN20/TIOA11_1/SIN0_2/INT20_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
113
PB3/AN19/TIOB10_1/INT19_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
112
PB2/AN18/TIOA10_1/SCK7_2/INT18_0
P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0
22
111
PB1/AN17/TIOB09_1/SOT7_2/INT17_0
P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0
23
110
PB0/AN16/TIOA09_1/SIN7_2/INT16_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
109
VSS
P5C/TIOA06_2/INT28_0/IC20_1
25
108
AVSS
P5D/TIOB06_2/INT29_0/DTTI2X_1
26
107
AVRH
VSS
27
106
AVCC
P30/AIN0_0/TIOB00_1/INT03_2
28
105
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P31/BIN0_0/TIOB01_1/SCK6_1/INT04_2
29
104
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P32/ZIN0_0/TIOB02_1/SOT6_1/INT05_2
30
103
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P33/INT04_0/TIOB03_1/SIN6_1/ADTG_6
31
102
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P34/FRCK0_0/TIOB04_1/TX0_1
32
101
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P35/IC03_0/TIOB05_1/RX0_1/INT08_1
33
100
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
34
99
P19/AN09/SCK2_2/INT22_1/MAD05_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
35
98
P18/AN08/SOT2_2/INT21_1/MAD04_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
36
97
P17/AN07/SIN2_2/INT04_1/MAD03_0
P39/DTTI0X_0/ADTG_2
37
96
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
38
95
P15/AN05/SOT0_1/IC03_2/MAD01_0
P3B/RTO01_0/TIOA01_1
39
94
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P3C/RTO02_0/TIOA02_1
40
93
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
41
92
P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0
P3E/RTO04_0/TIOA04_1
42
91
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0
P3F/RTO05_0/TIOA05_1
43
90
P10/AN00/MCSX7_0
VSS
44
89
VCC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VCC
P40/TIOA00_0/RTO10_1/INT12_1
P41/TIOA01_0/RTO11_1/INT13_1
P42/TIOA02_0/RTO12_1
P43/TIOA03_0/RTO13_1/ADTG_7
P44/TIOA04_0/RTO14_1
P45/TIOA05_0/RTO15_1
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P70/TX0_0/TIOA04_2/MADATA05_0
P71/RX0_0/INT13_2/TIOB04_2/MADATA06_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
P74/SCK2_0/ZIN2_0/MADATA09_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P7A/ZIN1_0/INT24_1/MADATA15_0
P7B/TIOB07_0/INT10_0
P7C/TIOA07_0/INT11_0
P7D/TIOA14_1/FRCK2_1/INT12_0
P7E/TIOB14_1/IC21_1/INT24_0
P7F/TIOA15_1/IC22_1/INT25_0
PF0/TIOB15_1/SIN1_2/INT13_0/IC23_1
PF1/TIOA08_1/SOT1_2/INT14_0
PF2/TIOB08_1/SCK1_2/INT15_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 176
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O mode 1 (timer
full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-05629 Rev. *H
Page 9 of 133
CY9BD10T Series
LQS144
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
PC0/E_RXER0_RXDV1
PC1/E_RX03_RX11
PC2/E_RX02_RX10
PC3/E_RX01/TIOA06_1
PC4/E_RX00/TIOA08_2
PC5/E_RXDV0/TIOA10_2
PC6/E_MDIO0/TIOA14_0
PC7/E_MDC0/CROUT_1
PC8/E_RXCK0_REFCK
PC9/E_COL0
PCA/E_CRS0
ETHVCC
VSS
PCB/E_COUT
PCC/E_MDIO1
PCD/E_TCK0_MDC1
PCE/E_TXER0_TXEN1/RTS4_0/TIOB06_1
PCF/E_TX03_TX11/CTS4_0/TIOB08_2
PD0/E_TX02_TX10/SCK4_0/TIOB10_2/INT30_1
PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1
PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2
PD3/E_TXEN0/TIOB03_2
P62/E_PPS0_PPS1/SCK5_0/ADTG_3
P61/SOT5_0/TIOB02_2/UHCONX0
P60/SIN5_0/TIOA02_2/INT15_1
PF5/SCK6_2/INT08_0/ZIN2_1
USBVCC0
P80/UDM0
P81/UDP0
VCC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
(TOP VIEW)
VCC
1
108
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
107
P83/UDP1
PA1/RTO21_0/TIOA09_0/IC10_0
3
106
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
105
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
104
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0
6
103
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2
7
102
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
101
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
100
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
99
P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
98
P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
97
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
96
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
95
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
94
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
93
VSS
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
92
AVSS
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
91
AVRH
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
90
AVCC
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
89
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
88
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
LQFP - 144
P10/AN00/MCSX7_0
73
VCC
VSS
PE3/X1
PE2/X0
MD0
PE0/MD1
P7A/ZIN1_0/INT24_1/MADATA15_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P74/SCK2_0/ZIN2_0/MADATA09_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
P71/RX0_0/INT13_2/TIOB04_2/MADATA06_0
P70/TX0_0/TIOA04_2/MADATA05_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
P48/DTTI1X_1/INT14_1/SIN3_2
INITX
P47/X1A
VCC
P46/X0A
VSS
C
P45/TIOA05_0/RTO15_1
P44/TIOA04_0/RTO14_1
P43/TIOA03_0/RTO13_1/ADTG_7
P42/TIOA02_0/RTO12_1
VCC
P41/TIOA01_0/RTO11_1/INT13_1
P40/TIOA00_0/RTO10_1/INT12_1
72
74
36
71
35
VSS
70
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0
P3F/RTO05_0/TIOA05_1
69
75
68
34
67
P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0
P3E/RTO04_0/TIOA04_1
66
76
65
33
64
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
63
77
62
32
61
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P3C/RTO02_0/TIOA02_1
60
P15/AN05/SOT0_1/IC03_2/MAD01_0
78
59
79
31
58
30
P3B/RTO01_0/TIOA01_1
57
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
56
80
55
29
54
P17/AN07/SIN2_2/INT04_1/MAD03_0
P39/DTTI0X_0/ADTG_2
53
P18/AN08/SOT2_2/INT21_1/MAD04_0
81
52
82
28
51
27
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
50
P19/AN09/SCK2_2/INT22_1/MAD05_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
49
83
48
26
47
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
46
84
45
25
44
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
VSS
43
85
42
24
41
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
40
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
86
39
87
23
38
22
37
P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR to select the pin.
TIOA09_0 and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O mode 1 (timer full mode) of
the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-05629 Rev. *H
Page 10 of 133
CY9BD10T Series
LBE192
(TOP VIEW)
1
A
2
3
UDP0 UDM0
4
5
6
7
8
9
USB
ETH
VSS PCD PCB VSS VCC
VCC0
10
11
12
13
14
PC8 VSS TCK VCC
B
VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS
C
VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90
D
PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20 UDM1
E
VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 VCC1
F
P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 VSS
G
VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVSS
H
P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVRH
J
VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC
K
P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17
L
P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS
M
VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC
N
VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS
P
TRSTX
VSS
TDI PF6 UDP1
USB
C
VSS VCC X0A X1A VSS P75 P77 P7C VSS
X0
X1
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O mode 1 (timer
full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-05629 Rev. *H
Page 11 of 133
CY9BD10T Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
LQFP-176
1
Pin No
LQFP-144
1
BGA-192
C1
Pin Name
I/O circuit
type
Pin state
type
-
VCC
PA0
2
2
B2
RTO20_0
TIOA08_0
G
I
G
I
G
I
G
I
G
H
G
H
E
F
E
F
FRCK1_0
PA1
3
3
C2
RTO21_0
TIOA09_0
IC10_0
PA2
4
4
C3
RTO22_0
TIOA10_0
IC11_0
PA3
5
5
D5
RTO23_0
TIOA11_0
IC12_0
PA4
RTO24_0
6
6
D2
TIOA12_0
RX0_2
IC13_0
INT03_0
PA5
RTO25_0
7
7
D1
TX0_2
TIOA13_0
INT10_2
P05
TRACED0
8
8
D3
TIOA05_2
SIN4_2
INT00_1
P06
TRACED1
9
9
D4
TIOB05_2
SOT4_2
INT01_1
Document Number: 002-05629 Rev. *H
Page 12 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin Name
BGA-192
I/O circuit
type
Pin state
type
E
G
E
G
E
G
E
H
E
H
E
H
E
H
P07
10
10
E2
TRACED2
ADTG_0
SCK4_2
P08
11
11
E3
TRACED3
TIOA00_2
CTS4_2
P09
TRACECLK
12
12
E4
TIOB00_2
RTS4_2
DTTI2X_0
P50
INT00_0
AIN0_2
13
13
E5
SIN3_1
RTO10_0
IC20_0
MOEX_0
P51
INT01_0
BIN0_2
14
14
F1
SOT3_1
RTO11_0
IC21_0
MWEX_0
P52
INT02_0
ZIN0_2
15
15
F2
SCK3_1
RTO12_0
IC22_0
MDQM0_0
P53
SIN6_0
TIOA01_2
16
16
F3
INT07_2
RTO13_0
IC23_0
MDQM1_0
Document Number: 002-05629 Rev. *H
Page 13 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin Name
BGA-192
I/O circuit
type
Pin State
type
E
I
E
I
E
H
E
H
E
H
E
H
E
H
E
H
P54
SOT6_0
17
17
F4
TIOB01_2
RTO14_0
MALE_0
P55
SCK6_0
18
18
F5
ADTG_1
RTO15_0
MRDY_0
P56
SIN1_0
19
19
F6
INT08_2
TIOA09_2
DTTI1X_0
MNALE_0
P57
SOT1_0
20
20
G2
TIOB09_2
INT16_1
MNCLE_0
P58
SCK1_0
21
21
G3
TIOA11_2
INT17_1
MNWEX_0
P59
SIN7_0
22
22
G4
RX1_1
TIOB11_2
INT09_2
MNREX_0
P5A
SOT7_0
23
23
G5
TX1_1
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
24
24
G6
TIOB13_1
INT19_1
MCSX1_0
Document Number: 002-05629 Rev. *H
Page 14 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
E
H
E
H
P5C
25
-
H1
TIOA06_2
INT28_0
IC20_1
P5D
26
-
H2
27
25
J1
TIOB06_2
INT29_0
DTTI2X_1
-
VSS
P30
28
-
H3
AIN0_0
TIOB00_1
E
H
E
H
E
H
E
H
E
I
E
H
E
H
INT03_2
P31
BIN0_0
29
-
H4
TIOB01_1
SCK6_1
INT04_2
P32
ZIN0_0
30
-
H5
TIOB02_1
SOT6_1
INT05_2
P33
INT04_0
31
-
H6
TIOB03_1
SIN6_1
ADTG_6
P34
32
-
J5
FRCK0_0
TX0_1
TIOB04_1
P35
IC03_0
33
-
J4
RX0_1
TIOB05_1
INT08_1
P36
IC02_0
34
26
J3
SIN5_2
INT09_1
TIOA12_2
MCSX2_0
Document Number: 002-05629 Rev. *H
Page 15 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
E
H
E
H
E
I
G
I
G
I
G
I
G
I
G
I
G
I
P37
IC01_0
35
27
J2
SOT5_2
INT10_1
TIOB12_2
MCSX3_0
P38
IC00_0
36
28
K1
SCK5_2
INT11_1
MCLKOUT_0
P39
37
29
K2
DTTI0X_0
ADTG_2
P3A
38
30
K3
RTO00_0
TIOA00_1
P3B
39
31
K4
RTO01_0
TIOA01_1
P3C
40
32
L1
RTO02_0
TIOA02_1
P3D
41
33
L2
RTO03_0
TIOA03_1
P3E
42
34
L3
RTO04_0
TIOA04_1
P3F
43
35
M2
RTO05_0
TIOA05_1
44
45
36
37
M1
N1
-
VSS
VCC
P40
46
38
N2
TIOA00_0
RTO10_1
G
H
G
H
INT12_1
P41
47
39
N3
TIOA01_0
RTO11_1
INT13_1
Document Number: 002-05629 Rev. *H
Page 16 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
BGA-192
48
40
M3
Pin name
I/O circuit
type
Pin state
type
G
I
G
I
G
I
G
I
P42
TIOA02_0
RTO12_1
P43
49
41
L4
TIOA03_0
RTO13_1
ADTG_7
P44
50
42
M4
TIOA04_0
RTO14_1
P45
51
43
N4
TIOA05_0
RTO15_1
52
53
54
44
45
46
P2
P3
P4
55
47
P5
56
48
P6
57
49
N5
-
C
VSS
VCC
P46
X0A
P47
X1A
INITX
D
M
D
N
B
C
E
H
E
I
E
I
E
I
P48
58
50
M5
DTTI1X_1
INT14_1
SIN3_2
P49
TIOB00_0
59
51
L5
IC10_1
AIN0_1
SOT3_2
P4A
TIOB01_0
60
52
K5
IC11_1
BIN0_1
SCK3_2
MADATA00_0
P4B
TIOB02_0
61
53
N6
IC12_1
ZIN0_1
MADATA01_0
Document Number: 002-05629 Rev. *H
Page 17 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
E
I
E
I
E
H
E
I
E
H
E
H
E
H
E
I
E
H
P4C
TIOB03_0
62
54
M6
IC13_1
SCK7_1
AIN1_2
MADATA02_0
P4D
TIOB04_0
63
55
L6
FRCK1_1
SOT7_1
BIN1_2
MADATA03_0
P4E
TIOB05_0
64
56
K6
INT06_2
SIN7_1
ZIN1_2
MADATA04_0
P70
65
57
J6
TIOA04_2
TX0_0
MADATA05_0
P71
INT13_2
66
58
N8
TIOB04_2
RX0_0
MADATA06_0
P72
SIN2_0
67
59
M8
INT14_2
AIN2_0
MADATA07_0
P73
SOT2_0
68
60
L8
INT15_2
BIN2_0
MADATA08_0
P74
69
61
K8
SCK2_0
ZIN2_0
MADATA09_0
P75
SIN3_0
70
62
P8
ADTG_8
INT07_1
MADATA10_0
Document Number: 002-05629 Rev. *H
Page 18 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
E
H
E
H
E
I
E
H
P76
SOT3_0
71
63
J8
TIOA07_2
INT11_2
MADATA11_0
P77
SCK3_0
72
64
P9
TIOB07_2
INT12_2
MADATA12_0
P78
73
65
N9
AIN1_0
TIOA15_0
MADATA13_0
P79
BIN1_0
74
66
M9
TIOB15_0
INT23_1
MADATA14_0
-
-
E1
G1
-
VSS
VSS
P7A
75
67
L9
ZIN1_0
INT24_1
E
H
E
H
E
H
E
H
E
H
E
H
MADATA15_0
P7B
76
-
K9
TIOB07_0
INT10_0
P7C
77
-
P10
TIOA07_0
INT11_0
P7D
78
-
N10
TIOA14_1
FRCK2_1
INT12_0
P7E
79
-
L10
TIOB14_1
IC21_1
INT24_0
P7F
80
-
K10
TIOA15_1
IC22_1
INT25_0
Document Number: 002-05629 Rev. *H
Page 19 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
I[1]
H
I[1]
H
I[1]
H
C
P
J
D
A
A
A
B
PF0
TIOB15_1
81
-
M10
SIN1_2
INT13_0
IC23_1
PF1
82
-
N11
TIOA08_1
SOT1_2
INT14_0
PF2
83
-
M11
TIOB08_1
SCK1_2
INT15_0
84
68
N13
85
69
N12
86
70
P12
87
71
P13
88
89
-
72
73
-
N14
M14
L7
K7
90
74
M13
PE0
MD1
MD0
PE2
X0
PE3
X1
-
VSS
VCC
VSS
VSS
P10
AN00
F
K
F
L
F
K
F
K
MCSX7_0
P11
AN01
SIN1_1
91
75
M12
RX1_2
INT02_1
FRCK0_2
MCSX6_0
P12
AN02
92
76
L13
SOT1_1
TX1_2
IC00_2
MCSX5_0
P13
AN03
93
77
L12
SCK1_1
IC01_2
MCSX4_0
Document Number: 002-05629 Rev. *H
Page 20 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
F
L
F
K
F
L
F
L
P14
AN04
94
78
L11
SIN0_1
INT03_1
IC02_2
MAD00_0
P15
AN05
95
79
K13
SOT0_1
IC03_2
MAD01_0
P16
AN06
96
80
K12
SCK0_1
INT20_1
MAD02_0
P17
AN07
97
81
K14
SIN2_2
INT04_1
MAD03_0
-
-
P7
P11
L14
-
VSS
VSS
VSS
P18
AN08
98
82
K11
SOT2_2
F
L
F
L
F
L
INT21_1
MAD04_0
P19
AN09
99
83
J13
SCK2_2
INT22_1
MAD05_0
P1A
AN10
SIN4_1
100
84
J12
INT05_1
TIOA13_2
IC00_1
MAD06_0
Document Number: 002-05629 Rev. *H
Page 21 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
F
L
F
L
F
L
F
L
F
L
P1B
AN11
SOT4_1
101
85
J11
INT25_1
TIOB13_2
IC01_1
MAD07_0
P1C
AN12
SCK4_1
102
86
J10
INT26_1
TIOA14_2
IC02_1
MAD08_0
P1D
AN13
CTS4_1
103
87
J9
INT27_1
TIOB14_2
IC03_1
MAD09_0
P1E
AN14
RTS4_1
104
88
H10
INT28_1
TIOA15_2
DTTI0X_1
MAD10_0
P1F
AN15
ADTG_5
105
89
H9
INT29_1
TIOB15_2
FRCK0_1
MAD11_0
106
107
108
109
90
91
92
93
J14
H14
G14
F14
-
AVCC
AVRH
AVSS
VSS
PB0
AN16
110
-
H13
TIOA09_1
F
L
SIN7_2
INT16_0
Document Number: 002-05629 Rev. *H
Page 22 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
F
L
F
L
F
L
F
L
F
L
PB1
AN17
111
-
H12
TIOB09_1
SOT7_2
INT17_0
PB2
AN18
112
-
H11
TIOA10_1
SCK7_2
INT18_0
PB3
113
-
G13
AN19
TIOB10_1
INT19_0
PB4
AN20
114
-
G12
TIOA11_1
SIN0_2
INT20_0
PB5
AN21
115
-
G11
TIOB11_1
SOT0_2
INT21_0
AIN2_2
-
-
G7
J7
-
VSS
VSS
PB6
AN22
116
-
G10
TIOA12_1
SCK0_2
F
L
F
L
F
K
INT22_0
BIN2_2
PB7
AN23
117
-
G9
TIOB12_1
INT23_0
ZIN2_2
P29
118
94
F10
AN24
MAD12_0
Document Number: 002-05629 Rev. *H
Page 23 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
F
L
F
L
F
K
F
K
F
L
F
K
F
K
E
H
P28
AN25
119
95
F11
ADTG_4
INT09_0
RTO05_1
MAD13_0
P27
AN26
120
96
F12
INT02_2
RTO04_1
MAD14_0
P26
AN27
121
97
F13
SCK2_1
RTO03_1
MAD15_0
P25
AN28
122
98
E10
SOT2_1
TX1_0
RTO02_1
MAD16_0
P24
AN29
SIN2_1
123
99
E11
RX1_0
INT01_2
RTO01_1
124
100
E12
125
101
E13
126
102
D12
Document Number: 002-05629 Rev. *H
MAD17_0
P23
AN30
SCK0_0
TIOA07_1
RTO00_1
P22
AN31
SOT0_0
TIOB07_1
ZIN1_1
P21
SIN0_0
INT06_1
BIN1_1
Page 24 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
124
100
E12
125
101
E13
126
102
D12
127
103
D13
128
104
C13
129
105
E14
130
106
D14
131
107
C14
132
133
108
109
B14
A13
134
110
B13
135
111
A12
136
112
C12
137
113
B12
138
114
B11
139
-
C11
-
-
A8
P23
AN30
SCK0_0
TIOA07_1
RTO00_1
P22
AN31
SOT0_0
TIOB07_1
ZIN1_1
P21
SIN0_0
INT06_1
BIN1_1
P20
INT05_0
CROUT_0
UHCONX1
AIN1_1
MAD18_0
PF6
FRCK2_0
NMIX
I/O circuit
type
Pin state
type
F
K
F
K
E
H
E
H
I[1]
J
-
USBVCC1
P82
UDM1
P83
UDP1
H
O
H
O
-
VSS
VCC
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
TDO
SWO
P90
TIOB08_0
RTO20_1
INT30_0
E
E
E
E
E
E
E
E
E
E
E
H
MAD19_0
Document Number: 002-05629 Rev. *H
VSS
-
Page 25 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
E
H
E
I
E
I
E
H
E
H
K
Q
K
Q
K
Q
K
Q
K
Q
K
Q
P91
TIOB09_0
140
-
D11
RTO21_1
INT31_0
MAD20_0
P92
TIOB10_0
141
-
B10
RTO22_1
SIN5_1
MAD21_0
P93
TIOB11_0
142
-
C10
RTO23_1
SOT5_1
MAD22_0
P94
TIOB12_0
143
-
D10
RTO24_1
SCK5_1
INT26_0
MAD23_0
P95
TIOB13_0
144
-
B9
RTO25_1
INT27_0
MAD24_0
145
115
C9
146
116
B8
147
117
D9
148
118
E9
PC0
E_RXER0_RXDV1
PC1
E_RX03_RX11
PC2
E_RX02_RX10
PC3
E_RX01
TIOA06_1
PC4
149
119
F9
E_RX00
TIOA08_2
PC5
150
120
C8
E_RXDV0
TIOA10_2
-
-
Document Number: 002-05629 Rev. *H
A5
VSS
-
Page 26 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
BGA-192
151
121
D8
Pin name
I/O circuit
type
Pin state
type
K
Q
L
Q
K
Q
K
Q
K
Q
PC6
E_MDIO0
TIOA14_0
PC7
152
122
E8
E_MDC0
CROUT_1
153
123
A10
154
124
F8
155
125
B7
156
157
126
127
A9
A11
158
128
A7
159
129
C7
160
130
A6
PC8
E_RXCK0_REFCK
PC9
E_COL0
PCA
E_CRS0
-
ETHVCC
VSS
PCB
E_COUT
PCC
E_MDIO1
PCD
E_TCK0_MDC1
L
Q
K
Q
K
Q
L
Q
L
Q
L
R
L
R
PCE
161
131
D7
E_TXER0_TXEN1
RTS4_0
TIOB06_1
PCF
162
132
E7
E_TX03_TX11
CTS4_0
TIOB08_2
PD0
E_TX02_TX10
163
133
F7
SCK4_0
TIOB10_2
INT30_1
PD1
E_TX01
164
134
B6
SOT4_0
TIOB14_0
INT31_1
-
-
Document Number: 002-05629 Rev. *H
N7
G8
H7
H8
VSS
VSS
VSS
VSS
-
Page 27 of 133
CY9BD10T Series
LQFP-176
Pin No
LQFP-144
Pin name
BGA-192
I/O circuit
type
Pin state
type
L
R
L
Q
E
Q
E
I
E
H
I[1]
H
I[1]
H
I[1]
H
PD2
E_TX00
165
135
C6
SIN4_0
TIOA03_2
INT00_2
PD3
166
136
D6
E_TXEN0
TIOB03_2
P62
167
137
E6
E_PPS0_PPS1
SCK5_0
ADTG_3
P61
168
138
B5
SOT5_0
TIOB02_2
UHCONX0
P60
169
139
C5
SIN5_0
TIOA02_2
INT15_1
PF3
TIOA06_0
170
-
B4
SIN6_2
INT06_0
AIN2_1
PF4
TIOB06_0
171
-
C4
SOT6_2
INT07_0
BIN2_1
PF5
172
140
B3
173
141
A4
SCK6_2
INT08_0
ZIN2_1
174
142
A3
175
143
A2
144
-
B1
M7
176
*1: 5 V tolerant I/O
Document Number: 002-05629 Rev. *H
-
USBVCC0
P80
UDM0
P81
UDP0
VSS
VSS
H
O
H
O
-
Page 28 of 133
CY9BD10T Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
Module
ADC
Pin name
Function
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
A/D converter external trigger input pin
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
Document Number: 002-05629 Rev. *H
A/D converter analog input pin
(ANxx describes ADC ch.xx)
LQFP-176
10
18
37
167
119
105
31
49
70
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
Pin No
LQFP-144
10
18
29
137
95
89
41
62
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
100
101
BGA-192
E2
F5
K2
E6
F11
H9
H6
L4
P8
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
H13
H12
H11
G13
G12
G11
G10
G9
F10
F11
F12
F13
E10
E11
E12
E13
Page 29 of 133
CY9BD10T Series
Module
Base Timer
0
Pin name
Function
TIOA0_0
TIOA0_1
Base timer ch.0 TIOA pin
TIOA0_2
TIOB0_0
TIOB0_1
Base timer ch.0 TIOB pin
TIOB0_2
Base Timer
1
TIOA1_0
TIOA1_1
Base timer ch.1 TIOA pin
TIOA1_2
TIOB1_0
TIOB1_1
Base timer ch.1 TIOB pin
TIOB1_2
Base Timer
2
TIOA2_0
TIOA2_1
Base timer ch.2 TIOA pin
TIOA2_2
TIOB2_0
TIOB2_1
Base timer ch.2 TIOB pin
TIOB2_2
Base Timer
3
TIOA3_0
TIOA3_1
Base timer ch.3 TIOA pin
TIOA3_2
TIOB3_0
TIOB3_1
Base timer ch.3 TIOB pin
TIOB3_2
Base Timer
4
TIOA4_0
TIOA4_1
Base timer ch.4 TIOA pin
TIOA4_2
TIOB4_0
TIOB4_1
Base timer ch.4 TIOB pin
TIOB4_2
Base Timer
5
TIOA5_0
TIOA5_1
Base timer ch.5 TIOA pin
TIOA5_2
TIOB5_0
TIOB5_1
Base timer ch.5 TIOB pin
TIOB5_2
Base Timer
6
TIOA6_0
TIOA6_1
Base timer ch.6 TIOA pin
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
Document Number: 002-05629 Rev. *H
Base timer ch.6 TIOB pin
LQFP-176
46
38
11
59
28
12
47
Pin No
LQFP-144
38
30
11
51
12
39
BGA-192
N2
K3
E3
L5
H3
E4
N3
39
31
K4
16
60
29
17
48
40
169
61
30
168
49
41
165
62
31
166
50
42
65
63
32
66
51
43
8
64
33
9
170
148
25
171
161
26
16
52
17
40
32
139
53
138
41
33
135
54
136
42
34
57
55
58
43
35
8
56
9
118
131
-
F3
K5
H4
F4
M3
L1
C5
N6
H5
B5
L4
L2
C6
M6
H6
D6
M4
L3
J6
L6
J5
N8
N4
M2
D3
K6
J4
D4
B4
E9
H1
C4
D7
H2
Page 30 of 133
CY9BD10T Series
Module
Base Timer
7
Pin name
Function
TIOA07_0
TIOA07_1
Base timer ch.7 TIOA pin
TIOA07_2
TIOB07_0
TIOB07_1
Base timer ch.7 TIOB pin
TIOB07_2
Base Timer
8
TIOA08_0
TIOA08_1
Base timer ch.8 TIOA pin
TIOA08_2
TIOB08_0
TIOB08_1
Base timer ch.8 TIOB pin
TIOB08_2
Base Timer
9
TIOA09_0
TIOA09_1
Base timer ch.9 TIOA pin
TIOA09_2
TIOB09_0
TIOB09_1
Base timer ch.9 TIOB pin
TIOB09_2
Base Timer
10
TIOA10_0
TIOA10_1
Base timer ch.10 TIOA pin
TIOA10_2
TIOB10_0
TIOB10_1
Base timer ch.10 TIOB pin
TIOB10_2
Base Timer
11
TIOA11_0
TIOA11_1
Base timer ch.11 TIOA pin
TIOA11_2
TIOB11_0
TIOB11_1
Base timer ch.11 TIOB pin
TIOB11_2
Base Timer
12
TIOA12_0
TIOA12_1
Base timer ch.12 TIOA pin
TIOA12_2
TIOB12_0
TIOB12_1
Base timer ch.12 TIOB pin
TIOB12_2
Base Timer
13
TIOA13_0
TIOA13_1
Base timer ch.13 TIOA pin
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
Document Number: 002-05629 Rev. *H
Base timer ch.13 TIOB pin
LQFP-176
77
124
71
76
125
72
2
Pin No
LQFP-144
100
63
101
64
2
BGA-192
P10
E12
J8
K9
E13
P9
B2
82
-
N11
149
139
83
162
3
110
19
140
111
20
4
112
150
141
113
163
5
114
21
142
115
22
6
116
34
143
117
35
7
23
100
144
24
101
119
132
3
19
20
4
120
133
5
21
22
6
26
27
7
23
84
24
85
F9
C11
M11
E7
C2
H13
F6
D11
H12
G2
C3
H11
C8
B10
G13
F7
D5
G12
G3
C10
G11
G4
D2
G10
J3
D10
G9
J2
D1
G5
J12
B9
G6
J11
Page 31 of 133
CY9BD10T Series
Module
Base Timer
14
Pin name
Function
TIOA14_0
TIOA14_1
Base timer ch.14 TIOA pin
TIOA14_2
TIOB14_0
TIOB14_1
Base timer ch.14 TIOB pin
TIOB14_2
Base Timer
15
TIOA15_0
TIOA15_1
Base timer ch.15 TIOA pin
TIOA15_2
TIOB15_0
TIOB15_1
Base timer ch.15 TIOB pin
TIOB15_2
CAN 0
TX0_0
TX0_1
CAN interface ch.0 TX output pin
TX0_2
RX0_0
RX0_1
CAN interface ch.0 RX output pin
RX0_2
CAN 1
TX1_0
TX1_1
CAN interface ch.1 TX output pin
TX1_2
RX1_0
RX1_1
CAN interface ch.1 RX output pin
RX1_2
Debugger
SWCLK
Serial wire debug interface clock input pin
SWDIO
Serial wire debug interface data input / output pin
SWO
Serial wire viewer output pin
TCK
JTAG test clock input pin
TDI
JTAG test data input pin
TDO
JTAG debug data output pin
TMS
JTAG test mode state input/output pin
TRACECLK
Trace CLK output pin of ETM
TRACED0
TRACED1
TRACED2
Trace data output pin of ETM
TRACED3
TRSTX
Document Number: 002-05629 Rev. *H
JTAG test reset input pin
LQFP-176
151
78
102
164
79
103
73
Pin No
LQFP-144
121
86
134
87
65
BGA-192
D8
N10
J10
B6
L10
J9
N9
80
-
K10
104
74
81
105
65
32
7
66
33
6
122
23
92
123
22
91
135
137
138
135
136
138
137
12
8
9
10
11
134
88
66
89
57
7
58
6
98
23
76
99
22
75
111
113
114
111
112
114
113
12
8
9
10
11
110
H10
M9
M10
H9
J6
J5
D1
N8
J4
D2
E10
G5
L13
E11
G4
M12
A12
B12
B11
A12
C12
B11
B12
E4
D3
D4
E2
E3
B13
Page 32 of 133
CY9BD10T Series
Module
External
Bus
Pin name
Function
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
External bus interface address bus
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
External bus interface chip select output pin
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
MOEX_0
MWEX_0
Document Number: 002-05629 Rev. *H
External bus interface byte mask signal output pin
External bus interface read enable signal for
SRAM
External bus interface write enable signal for
SRAM
LQFP-176
94
95
96
97
98
99
100
101
102
103
104
105
118
119
120
121
122
123
127
139
140
141
142
143
144
23
24
34
35
93
92
91
90
15
16
Pin No
LQFP-144
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
103
23
24
26
27
77
76
75
74
15
16
BGA-192
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
F10
F11
F12
F13
E10
E11
D13
C11
D11
B10
C10
D10
B9
G5
G6
J3
J2
L12
L13
M12
M13
F2
F3
13
13
E5
14
14
F1
Page 33 of 133
CY9BD10T Series
Module
External
Bus
LQFP-176
Pin No
LQFP-144
BGA-192
19
19
F6
20
20
G2
22
22
G4
21
21
G3
MADATA00_0
60
52
K5
MADATA01_0
61
53
N6
MADATA02_0
62
63
64
65
66
67
68
69
70
71
72
73
74
75
54
55
56
57
58
59
60
61
62
63
64
65
66
67
M6
L6
K6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
17
17
F4
18
36
18
28
F5
K1
Pin name
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
Function
External bus interface ALE signal to control NAND
Flash output pin
External bus interface CLE signal to control NAND
Flash output pin
External bus interface read enable signal to
control NAND Flash
External bus interface write enable signal to
control NAND Flash
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
External bus interface data bus
(Address / data multiplex bus)
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MALE_0
External bus interface Address Latch enable
output signal for multiplex
MRDY_0
External bus interface external RDY input signal
MCLKOUT_0
External bus interface external clock output pin
Document Number: 002-05629 Rev. *H
Page 34 of 133
CY9BD10T Series
Module
External
Interrupt
Pin name
Function
INT00_0
INT00_1
External interrupt request 00 input pin
INT00_2
INT01_0
INT01_1
External interrupt request 01 input pin
INT01_2
INT02_0
INT02_1
External interrupt request 02 input pin
INT02_2
INT03_0
INT03_1
External interrupt request 03 input pin
INT03_2
INT04_0
INT04_1
External interrupt request 04 input pin
INT04_2
INT05_0
INT05_1
External interrupt request 05 input pin
INT05_2
INT06_0
INT06_1
External interrupt request 06 input pin
INT06_2
INT07_0
INT07_1
External interrupt request 07 input pin
INT07_2
INT08_0
INT08_1
External interrupt request 08 input pin
INT08_2
INT09_0
INT09_1
External interrupt request 09 input pin
INT09_2
INT10_0
INT10_1
External interrupt request 10 input pin
INT10_2
INT11_0
INT11_1
External interrupt request 11 input pin
INT11_2
INT12_0
INT12_1
External interrupt request 12 input pin
INT12_2
INT13_0
INT13_1
External interrupt request 13 input pin
INT13_2
INT14_0
INT14_1
INT14_2
Document Number: 002-05629 Rev. *H
External interrupt request 14 input pin
LQFP-176
13
8
165
14
9
123
15
91
120
6
94
28
31
97
29
127
100
30
170
126
64
171
70
16
172
33
19
119
34
22
76
35
7
77
36
71
78
46
72
81
47
66
82
58
67
Pin No
LQFP-144
13
8
135
14
9
99
15
75
96
6
78
81
103
84
102
56
62
16
140
19
95
26
22
27
7
28
63
38
64
39
58
50
59
BGA-192
E5
D3
C6
F1
D4
E11
F2
M12
F12
D2
L11
H3
H6
K14
H4
D13
J12
H5
B4
D12
K6
C4
P8
F3
B3
J4
F6
F11
J3
G4
K9
J2
D1
P10
K1
J8
N10
N2
P9
M10
N3
N8
N11
M5
M8
Page 35 of 133
CY9BD10T Series
Module
External
Interrupt
Pin name
Function
INT15_0
INT15_1
External interrupt request 15 input pin
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
Document Number: 002-05629 Rev. *H
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
External interrupt request 23 input pin
External interrupt request 24 input pin
External interrupt request 25 input pin
External interrupt request 26 input pin
External interrupt request 27 input pin
External interrupt request 28 input pin
External interrupt request 29 input pin
External interrupt request 30 input pin
External interrupt request 31 input pin
Non-Maskable Interrupt input pin
LQFP-176
83
169
68
110
20
111
21
112
23
113
24
114
96
115
98
116
99
117
74
79
75
80
101
143
102
144
103
25
104
26
105
139
163
140
164
128
Pin No
LQFP-144
139
60
20
21
23
24
80
82
83
66
67
85
86
87
88
89
133
134
104
BGA-192
M11
C5
L8
H13
G2
H12
G3
H11
G5
G13
G6
G12
K12
G11
K11
G10
J13
G9
M9
L10
L9
K10
J11
D10
J10
B9
J9
H1
H10
H2
H9
C11
F7
D11
B6
C13
Page 36 of 133
CY9BD10T Series
Module
GPIO
Pin name
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
Document Number: 002-05629 Rev. *H
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
LQFP-176
134
135
136
137
138
8
9
10
11
12
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
127
126
125
124
123
122
121
120
119
118
Pin No
LQFP-144
110
111
112
113
114
8
9
10
11
12
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
103
102
101
100
99
98
97
96
95
94
BGA-192
B13
A12
C12
B12
B11
D3
D4
E2
E3
E4
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
Page 37 of 133
CY9BD10T Series
Module
GPIO
Pin name
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
Document Number: 002-05629 Rev. *H
Function
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
LQFP-176
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
48
49
50
51
55
56
58
59
60
61
62
63
64
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Pin No
LQFP-144
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
13
14
15
16
17
18
19
20
21
22
23
24
-
BGA-192
H3
H4
H5
H6
J5
J4
J3
J2
K1
K2
K3
K4
L1
L2
L3
M2
N2
N3
M3
L4
M4
N4
P5
P6
M5
L5
K5
N6
M6
L6
K6
E5
F1
F2
F3
F4
F5
F6
G2
G3
G4
G5
G6
H1
H2
Page 38 of 133
CY9BD10T Series
Module
GPIO
Pin name
P60
P61
P62
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P7F
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Document Number: 002-05629 Rev. *H
Function
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port 9
General-purpose I/O port A
General-purpose I/O port B
LQFP-176
169
168
167
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
174
175
130
131
139
140
141
142
143
144
2
3
4
5
6
7
110
111
112
113
114
115
116
117
Pin No
LQFP-144
139
138
137
57
58
59
60
61
62
63
64
65
66
67
142
143
106
107
2
3
4
5
6
7
-
BGA-192
C5
B5
E6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
K9
P10
N10
L10
K10
A3
A2
D14
C14
C11
D11
B10
C10
D10
B9
B2
C2
C3
D5
D2
D1
H13
H12
H11
G13
G12
G11
G10
G9
Page 39 of 133
CY9BD10T Series
Module
GPIO
Pin name
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PD3
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
Document Number: 002-05629 Rev. *H
Function
General-purpose I/O port C
General-purpose I/O port D
General-purpose I/O port E
General-purpose I/O port F *1
LQFP-176
145
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
84
86
87
81
82
83
170
171
172
128
Pin no
LQFP-144
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
68
70
71
140
104
BGA-192
C9
B8
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
C6
D6
N13
P12
P13
M10
N11
M11
B4
C4
B3
C13
Page 40 of 133
CY9BD10T Series
Module
Multifunction Serial
0
Pin name
Function
SIN0_0
SIN0_1
Multi-function serial interface ch.0 input pin
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA0 when it is used in an I2C (operation mode
4).
SOT0_2
(SDA0_2)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
CSIO (operation mode 2) and as SCL0 when it is
used in an I2C (operation mode 4).
SCK0_2
(SCL0_2)
Multifunction Serial
1
SIN1_0
SIN1_1
Multi-function serial interface ch.1 input pin
SIN1_2
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
SOT1_2
(SDA1_2)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA1 when it is used in an I2C (operation mode
4).
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
SCK1_2
(SCL1_2)
Document Number: 002-05629 Rev. *H
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
CSIO (operation mode 2) and as SCL1 when it is
used in an I2C (operation mode 4).
LQFP-176
126
94
114
Pin No.
LQFP-144
102
78
-
BGA-192
D12
L11
G12
125
101
E13
95
79
K13
115
-
G11
124
100
E12
96
80
K12
116
-
G10
19
91
81
19
75
-
F6
M12
M10
20
20
G2
92
76
L13
82
-
N11
21
21
G3
93
77
L12
83
-
M11
Page 41 of 133
CY9BD10T Series
Module
Multifunction Serial
2
LQFP-176
67
123
97
Pin No.
LQFP-144
59
99
81
BGA-192
M8
E11
K14
68
60
L8
122
98
E10
98
82
K11
69
61
K8
121
97
F13
99
83
J13
SIN3_0
70
62
P8
SIN3_1
13
13
E5
58
50
M5
71
63
J8
14
14
F1
59
51
L5
72
64
P9
15
15
F2
60
52
K5
Pin name
SIN2_0
SIN2_1
Multi-function serial interface ch.2 input pin
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
Multifunction Serial
3
Function
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA2 when it is used in an I2C (operation mode
4).
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
CSIO (operation mode 2) and as SCL2 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.3 input pin
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Document Number: 002-05629 Rev. *H
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA3 when it is used in an I2C (operation mode
4).
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
CSIO (operation mode 2) and as SCL3 when it is
used in an I2C (operation mode 4).
Page 42 of 133
CY9BD10T Series
Module
Multifunction Serial
4
LQFP-176
165
100
8
Pin No
LQFP-144
135
84
8
BGA-192
C6
J12
D3
164
134
B6
101
85
J11
9
9
D4
163
133
F7
102
86
J10
10
10
E2
161
104
12
162
103
11
169
141
34
131
88
12
132
87
11
139
26
D7
H10
E4
E7
J9
E3
C5
B10
J3
168
138
B5
142
-
C10
SOT5_2
(SDA5_2)
35
27
J2
SCK5_0
(SCL5_0)
167
137
E6
143
-
D10
36
28
K1
Pin name
Function
SIN4_0
SIN4_1
Multi-function serial interface ch.4 input pin
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA4 when it is used in an I2C (operation mode
4).
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
CSIO (operation mode 2) and as SCL4 when it is
used in an I2C (operation mode 4).
RTS4_0
RTS4_1
Multi-function serial interface ch.4 RTS output pin
RTS4_2
CTS4_0
CTS4_1
Multi-function serial interface ch.4 CTS input pin
CTS4_2
Multifunction Serial
5
SIN5_0
SIN5_1
Multi-function serial interface ch.5 input pin
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Document Number: 002-05629 Rev. *H
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA5 when it is used in an I2C (operation mode
4).
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
CSIO (operation mode 2) and as SCL5 when it is
used in an I2C (operation mode 4).
Page 43 of 133
CY9BD10T Series
Module
Multifunction Serial
6
LQFP-176
16
31
170
Pin No
LQFP-144
16
-
BGA-192
F3
H6
B4
17
17
F4
30
-
H5
171
-
C4
18
18
F5
29
-
H4
172
140
B3
22
64
110
22
56
-
G4
K6
H13
23
23
G5
63
55
L6
SOT7_2
(SDA7_2)
111
-
H12
SCK7_0
(SCL7_0)
24
24
G6
62
54
M6
112
-
H11
Pin name
SIN6_0
SIN6_1
Multi-function serial interface ch.6 input pin
SIN6_2
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SOT6_2
(SDA6_2)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SCK6_2
(SCL6_2)
Multifunction Serial
7
Function
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA6 when it is used in an I2C (operation mode
4).
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
CSIO (operation mode 2) and as SCL6 when it is
used in an I2C (operation mode 4).
SIN7_0
SIN7_1
Multi-function serial interface ch.7 input pin
SIN7_2
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
Document Number: 002-05629 Rev. *H
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA7 when it is used in an I2C (operation mode
4).
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
CSIO (operation mode 2) and as SCL7 when it is
used in an I2C (operation mode 4).
Page 44 of 133
CY9BD10T Series
Module
Multifunction Timer
0
Pin name
DTTI0X_0
DTTI0X_1
Function
Input signal controlling wave form generator
outputs RTO00 to RTO05 of multi-function timer
0.
FRCK0_0
FRCK0_1
16-bit free-run timer ch.0 external clock input pin
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
16-bit input capture ch.0 input pin of multi-function
timer 0.
(ICxx describes channel number)
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
Wave form generator output pin of multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
Wave form generator output pin of multi-function
timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
Wave form generator output pin of multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Document Number: 002-05629 Rev. *H
Wave form generator output pin of multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of multi-function
timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of multi-function
timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Pin No
LQFP-176
LQFP-144
BGA-192
37
29
K2
104
32
105
91
36
100
92
35
101
93
34
102
94
33
103
95
88
89
75
28
84
76
27
85
77
26
86
78
87
79
H10
J5
H9
M12
K1
J12
L13
J2
J11
L12
J3
J10
L11
J4
J9
K13
38
30
K3
124
100
E12
39
31
K4
123
99
E11
40
32
L1
122
98
E10
41
33
L2
121
97
F13
42
34
L3
120
96
F12
43
35
M2
119
95
F11
Page 45 of 133
CY9BD10T Series
Module
Multifunction Timer
1
Pin name
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
LQFP-176
Pin No
LQFP-144
BGA-192
19
19
F6
58
50
M5
2
63
3
59
4
60
5
61
6
62
2
55
3
51
4
52
5
53
6
54
B2
L6
C2
L5
C3
K5
D5
N6
D2
M6
Wave form generator output pin of multi-function
timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
13
13
E5
46
38
N2
Wave form generator output pin of multi-function
timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
14
14
F1
47
39
N3
Wave form generator output pin of multi-function
timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
15
15
F2
48
40
M3
Wave form generator output pin of multi-function
timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
16
16
F3
49
41
L4
17
17
F4
50
42
M4
18
18
F5
51
43
N4
Function
Input signal controlling wave form generator
outputs RTO10 to RTO15 of multi-function timer
1.
16-bit free-run timer ch.1 external clock input pin
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
16-bit input capture ch.1 input pin of multi-function
timer 1.
(ICxx describes channel number)
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
Wave form generator output pin of multi-function
timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Wave form generator output pin of multi-function
timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
Document Number: 002-05629 Rev. *H
Page 46 of 133
CY9BD10T Series
Module
Multifunction Timer
2
Pin name
DTTI2X_0
DTTI2X_1
FRCK2_0
FRCK2_1
Function
Input signal controlling wave form generator
outputs RTO20 to RTO25 of multi-function timer
2.
16-bit free-run timer ch.2 external clock input pin
IC20_0
IC20_1
IC21_0
IC21_1
IC22_0
IC22_1
16-bit input capture ch.2 input pin of multi-function
timer 2.
(ICxx describes channel number)
IC23_0
IC23_1
RTO20_0
(PPG20_0)
RTO20_1
(PPG20_1)
RTO21_0
(PPG20_0)
RTO21_1
(PPG20_1)
RTO22_0
(PPG22_0)
RTO22_1
(PPG22_1)
RTO23_0
(PPG22_0)
RTO23_1
(PPG22_1)
RTO24_0
(PPG24_0)
RTO24_1
(PPG24_1)
RTO25_0
(PPG24_0)
RTO25_1
(PPG24_1)
Document Number: 002-05629 Rev. *H
Wave form generator output pin of multi-function
timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output pin of multi-function
timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output pin of multi-function
timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
Wave form generator output pin of multi-function
timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
Wave form generator output pin of multi-function
timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
Wave form generator output pin of multi-function
timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
Pin No
LQFP-176
LQFP-144
BGA-192
12
12
E4
26
-
H2
128
78
13
25
14
79
15
80
16
81
104
13
14
15
16
-
C13
N10
E5
H1
F1
L10
F2
K10
F3
M10
2
2
B2
139
-
C11
3
3
C2
140
-
D11
4
4
C3
141
-
B10
5
5
D5
142
-
C10
6
6
D2
143
-
D10
7
7
D1
144
-
B9
Page 47 of 133
CY9BD10T Series
Module
Quadrature
Position/
Revolution
Counter
0
Pin name
Function
AIN0_0
AIN0_1
QPRC ch.0 AIN input pin
AIN0_2
BIN0_0
BIN0_1
QPRC ch.0 BIN input pin
BIN0_2
ZIN0_0
ZIN0_1
QPRC ch.0 ZIN input pin
ZIN0_2
Quadrature
Position/
Revolution
Counter
1
AIN1_0
AIN1_1
QPRC ch.1 AIN input pin
AIN1_2
BIN1_0
BIN1_1
QPRC ch.1 BIN input pin
BIN1_2
ZIN1_0
ZIN1_1
QPRC ch.1 ZIN input pin
ZIN1_2
Quadrature
Position/
Revolution
Counter
2
AIN2_0
AIN2_1
QPRC ch.2 AIN input pin
AIN2_2
BIN2_0
BIN2_1
QPRC ch.2 BIN input pin
BIN2_2
ZIN2_0
ZIN2_1
QPRC ch.2 ZIN input pin
ZIN2_2
USB0
USB1
LQFP-176
28
59
13
29
60
14
30
61
15
73
127
62
74
126
63
75
125
64
67
170
115
68
171
116
69
172
117
174
175
Pin No
LQFP-144
51
13
52
14
53
15
65
103
54
66
102
55
67
101
56
59
60
61
140
142
143
BGA-192
H3
L5
E5
H4
K5
F1
H5
N6
F2
N9
D13
M6
M9
D12
L6
L9
E13
K6
M8
B4
G11
L8
C4
G10
K8
B3
G9
A3
A2
UDM0
USB ch.0 device/host D – pin
UDP0
USB ch.0 device/host D + pin
UHCONX0
USB ch.0.
USB external pull-up control pin
168
138
B5
UDM1
USB ch.1 device/host D – pin
UDP1
USB ch.1 device/host D + pin
130
131
106
107
D14
C14
UHCONX1
USB ch.1.
USB external pull-up control pin
127
103
D13
Document Number: 002-05629 Rev. *H
Page 48 of 133
CY9BD10T Series
Module
Ethernet
Reset
Pin name
Function
LQFP-176
154
158
155
152
151
159
Pin No
LQFP-144
124
128
125
122
121
129
BGA-192
F8
A7
B7
E8
D8
C7
167
137
E6
149
148
119
118
F9
E9
E_COL0
Ch.0 collision detection
E_COUT
Clock output pin for EtherPHY
E_CRS0
Ch.0 carrier detection
E_MDC0
Ch.0 management clock
E_MDIO0
Ch.0 management data input/output
E_MDIO1
Ch.1 management data input/output
E_PPS0_PPS1
Ch.0 PTP counter monitor/
Ch.1 PTP counter monitor
E_RX00
Ch.0 received data0
E_RX01
Ch.0 received data1
E_RX02_RX10
Ch.0 received data2/
Ch.1 received data0
147
117
D9
E_RX03_RX11
Ch.0 received data3/
Ch.1 received data1
146
116
B8
E_RXCK0_REFCK
Ch.0 received clock input/
reference clock
153
123
A10
E_RXDV0
Ch.0 received data enable
150
120
C8
E_RXER0_RXDV1
Ch.0 received data error detection/
Ch.1 received data enable
145
115
C9
E_TCK0_MDC1
Ch.0 transition clock input/
Ch.1 management clock
160
130
A6
E_TX00
Ch.0 transition data0
E_TX01
Ch.0 transition data1
165
164
135
134
C6
B6
E_TX02_TX10
Ch.0 transition data2/
Ch.1 transition data0
163
133
F7
E_TX03_TX11
Ch.0 transition data3/
Ch.1 transition data1
162
132
E7
E_TXEN0
Ch.0 transition data enable
166
136
D6
E_TXER0_TXEN1
Ch.0 transition data error detection/
Ch.1 transition data enable
161
131
D7
INITX
External Reset Input pin.
A reset is valid when INITX="L".
57
49
N5
MD0
Mode 0 pin.
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
85
69
N12
MD1
Mode 1 pin.
During serial programming to Flash memory,
MD1="L" must be input.
84
68
N13
Mode
Document Number: 002-05629 Rev. *H
Page 49 of 133
CY9BD10T Series
Module
Power
Pin name
Function
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
VCC
Power supply Pin
133
109
A13
173
141
A4
129
105
E14
USBVCC1
Clock
3.3V Power supply port for USB I/O
ETHVCC
Power supply pin for Ethernet I/O
156
126
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
27
44
53
88
109
132
157
176
86
25
36
45
72
93
108
127
144
70
J1
M1
P3
N14
F14
B14
A11
B1
E1
G1
P7
P11
L14
A8
A5
N7
M7
L7
K7
J7
G7
H7
H8
G8
P12
X0A
Sub clock (oscillation) input pin
55
47
P5
X1
Main clock (oscillation) I/O pin
87
71
P13
X1A
Sub clock (oscillation) I/O pin
56
48
P6
127
103
D13
152
122
E8
CROUT_0
CROUT_1
Analog
Power
BGA-192
C1
N1
P4
M14
VCC
VCC
VCC
VCC
USBVCC0
GND
Pin No
LQFP-144
1
37
46
73
LQFP-176
1
45
54
89
Bulit-in high-speed CR-osc clock output port
AVCC
A/D converter analog power supply pin
106
90
J14
AVRH
A/D converter analog reference voltage input pin
107
91
H14
Analog
GND
AVSS
A/D converter GND pin
108
92
G14
C pin
C
Power stabilization capacity pin
52
44
P2
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05629 Rev. *H
Page 50 of 133
CY9BD10T Series
5. I/O Circuit Type
Type
A
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
P-ch
When the main oscillation is
selected.
P-ch
Digital output
X1
−
Oscillation feedback resistor
: Approximately 1 MΩ
−
N-ch
Digital output
With Standby mode control
When the GPIO is selected.
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
Pull-up resistor control
−
With standby mode control
Digital input
−
Pull-up resistor
Standby mode control
−
IOH = -4 mA, IOL = 4 mA
−
CMOS level hysteresis input
−
Pull-up resistor
R
: Approximately 50 kΩ
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
B
: Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-05629 Rev. *H
Page 51 of 133
CY9BD10T Series
Type
C
Circuit
Remarks
Digital input
−
Open drain output
−
CMOS level hysteresis input
Control pin
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
When the sub oscillation is selected.
P-ch
Digital output
−
Oscillation feedback resistor
: Approximately 5 MΩ
X1A
−
With Standby mode control
When the GPIO is selected.
N-ch
Digital output
R
Pull-up resistor control
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
Digital input
−
IOH = -4 mA, IOL = 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
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Page 52 of 133
CY9BD10T Series
Type
E
Circuit
P-ch
P-ch
Remarks
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
When this pin is used as an I2C pin,
the digital output P-ch transistor is
N-ch
always off
Digital output
R
−
+B input is available
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
P-ch
Digital output
: Approximately 50 kΩ
N-ch
Digital output
−
IOH = -4 mA, IOL = 4 mA
−
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
−
R
+B input is available
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
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Page 53 of 133
CY9BD10T Series
Type
G
Circuit
P-ch
Remarks
Digital output
P-ch
N-ch
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -12 mA, IOL = 12 mA
−
+B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
H
GPIO Digital output
It is possible to select the USB I/O /
GPIO function.
GPIO Digital input/output direction
GPIO Digital input
When the USB I/O is selected.
GPIO Digital input circuit control
−
UDP (+) output
EBP
USB Full-speed/Low-speed control
UDP (+) input
Differential
EBM
Differential input
Full-speed, Low-speed control
When the GPIO is selected.
−
CMOS level output
−
CMOS level hysteresis input
−
With standby mode control
−
IOH = -20.5 mA, IOL = 18.5 mA
USB/GPIO select
UDM (-) input
UDM (-) output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
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Page 54 of 133
CY9BD10T Series
Type
I
Circuit
P-ch
Remarks
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
5 V tolerant
−
With standby mode control
−
IOH = -4 mA, IOL = 4 mA
−
Available to control of PZR registers.
−
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
N-ch
Digital output
R
Digital input
Standby mode control
J
−
CMOS level hysteresis input
Mode input
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Page 55 of 133
CY9BD10T Series
Type
K
Circuit
P-ch
P-ch
N-ch
Remarks
Digital output
−
CMOS level output
−
TTL level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
L
P-ch
P-ch
Digital output
: Approximately 50 kΩ
−
IOH = -8 mA, IOL = 8 mA
−
When this pin is used as an I2C pin,
the digital output
N-ch
P-ch transistor is always off
Digital output
−
R
+B input is available
Pull-up resistor control
Digital input
Standby mode control
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Page 56 of 133
CY9BD10T Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess
of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
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CY9BD10T Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising
from such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress Inc. recommends the solder reflow method, and has established a
ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of
recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
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CY9BD10T Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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CY9BD10T Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins
and GND pins, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0,X0A pin only and the X1,X1A pin should be kept open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
Handling when using Multi-function serial pin as I2C pin
If it is using multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep
the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF.
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CY9BD10T Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation
(F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to
use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
Cs
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on: VCC → USBVCC0
VCC → USBVCC1
VCC → ETHVCC
VCC → AVCC → AVRH
Turning off: AVRH → AVCC → VCC
ETHVCC → VCC
USBVCC1 → VCC
USBVCC0 → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
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CY9BD10T Series
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Base Timer
In the case of using ch.8 and ch.9 at I/O mode 1 (timer full mode), the TIOA09 pin cannot be used for external startup trigger input
(TGIN).
Be sure to use the pin with making ESG1 and ESG2 bits of the Timer Control Register (Ch.9-TMCR) in the Base Timer to be
"0b00" in order to disable trigger input.
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CY9BD10T Series
8. Block Diagram
MB9BFD16/D17/D18
TRACED[3:0],
TRACECLK
SWJ-DP
ETM
TPIU
ROM
Table
Cortex-M3 Core
144MHz(Max)
SRAM0
32/48/64Kbyte
I
Multi-layer AHB (Max 144MHz)
TRSTX,TCK,
TDI,TMS
TDO
D
MPU NVIC
Sys
AHB-APB Bridge:
APB0(Max 72MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
On-chip Flash
512Kbyte/
768Kbyte/
1024Kbyte
Flash I/F
Security
Trace Buffer
(16Kbyte)
SRAM1
32/48/64Kbyte
USBVCC0
USB 2.0
(Host/
Func)
PHY
USB 2.0
(Host/
Func)
PHY
UDP0,UDM0
UHCONX0
USBVCC1
UDP1,UDM1
UHCONX1
CSV
DMAC
8ch.
X0A
X1A
CROUT
AVCC,
AVSS,AVRH
Main
Osc
Sub
Osc
PLL
Source Clock
CR
4MHz
AHB-AHB
Bridge
(Slave)
X1
CR
100kHz
12-bit A/D Converter
AHB-AHB
Bridge
(Master)
X0
Unit 0
AN[31:00]
Unit 1
ADTG[8:0]
CAN
TX0,
RX0
CAN
TX1,
RX1
EthernetMAC0
MII/
RMII
EthernetMAC1
RMII
Selector
CLK
E_TXx,
E_RXx,
E_MDx
Unit 2
MAD[24:00]
AIN[2:0]
BIN[2:0]
QPRC
3ch.
ZIN[2:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
IC2[3:0]
FRCK[2:0]
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare
6ch.
DTTI[2:0]X
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
USB-Ethernet Clk Ctrl
AHB-APB Bridge : APB2 (Max 72MHz)
TIOB[15:00]
External Bus I/F
Base Timer
16-bit 16ch./
32-bit 8ch.
AHB-APB Bridge : APB1 (Max 72MHz)
TIOA[15:00]
CAN Prescaler
LVD Ctrl
IRQ-Monitor
MADATA[15:00]
PLL
Power On
Reset
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MALE
MRDY
MCLKOUT
LVD
Regulator
C
CRC
Accelerator
Watch Counter
External Interrupt
Controller
32-pin + NMI
Waveform Generator
3ch.
MODE-Ctrl
16-bit PPG
3ch.
GPIO
Multi-function Timer ×3
Multi-Function
Serial I/F 8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)
INT[31:00]
NMIX
MD[1:0]
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
PFx
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
Note:
−
The following items vary depending on the package.
•
•
Number of external bus interface pin
Number of 12-bit A/D converter channel
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CY9BD10T Series
9. Memory Size
See “Memory size” in “1. Product Lineup” to confirm the memory size.
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4006_9000
0x4006_7000
0xFFFF_FFFF
0x4006_6000
Reserved
0x4006_4000
0x4006_3000
Cortex-M3 Private
Peripherals
0x4006_2000
0x4006_1000
0xE010_0000
0xE000_0000
0x4006_0000
Ethernet-MAC1
Ethernet-Control-Reg.
Ethernet-MAC0
CAN ch.1
CAN ch.0
Reserved
DMAC
USB ch.1
0x4005_0000
Reserved
USB ch.0
0x4004_0000
0x4003_F000
0x7000_0000
0x6000_0000
0x4200_0000
0x4000_0000
Reserved
External Device
Area
0x4003_B000
Reserved
0x4003_8000
0x4003_7000
32Mbyte
Bit band alias
0x4003_6000
0x4003_5000
0x4400_0000
Peripherals
0x4003_A000
0x4003_9000
0x4003_4000
0x4003_3000
0x4003_2000
Reserved
0x4003_1000
0x4003_0000
32Mbyte
Bit band alias
0x4002_F000
0x4002_E000
Reserved
0x4002_8000
0x2400_0000
0x2200_0000
0x2008_0000
0x2000_0000
0x1FFF_0000
0x0010_2000
See the next page
“●Memory Map (2)” for
the memory size details.
0x0010_0000
SRAM1
SRAM0
Reserved
Security/CR Trim
Watch Counter
CRC
MFS
CAN Prescaler
USB-Ethernet Clk Ctrl
LVD Ctrl
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4002_1000
0x4002_0000
On-chip Flash
EXT-bus I/F
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
A/DC
QPRC
Base Timer
PPG
Reserved
MFT unit2
MFT unit1
MFT unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
Document Number: 002-05629 Rev. *H
Flash I/F
Page 64 of 133
CY9BD10T Series
Memory Map (2)
MB9BFD18S/T
MB9BFD17S/T
0x2008_0000
MB9BFD16S/T
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2001_0000
Reserved
0x2001_C000
SRAM1
64Kbyte
0x2000_8000
SRAM1
48Kbyte
0x2000_0000
SRAM1
32Kbyte
0x2000_0000
0x2000_0000
SRAM0
32Kbyte
SRAM0
48Kbyte
SRAM0
64Kbyte
0x1FFF_8000
0x1FFF_4000
Reserved
0x1FFF_0000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
0x000C_0000
Reserved
SA10-19(64KBx10)
0x0000_0000
SA4-7(8KBx4)
0x0008_0000
SA10-15(64KBx6)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
Flash 512Kbyte
SA8-9(48KBx2)
Flash 768Kbyte
Flash 1Mbyte
SA10-23(64KBx14)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
See "CY9BD10T/610T/510T/410T/310T/210T/110T Series Flash Programming Manual" for sector structure of Flash.
Document Number: 002-05629 Rev. *H
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CY9BD10T Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4002_3FFF
Multi-function timer unit2
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_5FFF
Low-Voltage Detector
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
CAN Prescaler
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External bus I/F
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
USB ch.1
0x4006_0000
0x4006_0FFF
DMAC register
0x4006_1000
0x4006_1FFF
Reserved
0x4006_2000
0x4006_2FFF
0x4006_3000
0x4006_3FFF
0x4006_4000
0x4006_5FFF
Ethernet-MAC ch.0
0x4006_6000
0x4006_6FFF
Ethernet-MAC setting Register
0x4006_7000
0x4006_8FFF
Ethernet-MAC ch.1
0x4006_9000
0x41FF_FFFF
Reserved
Document Number: 002-05629 Rev. *H
AHB
APB0
APB1
APB2
AHB
Flash memory I/F register
Reserved
Software Watchdog timer
Reserved
Base Timer
Quadrature Position/Revolution Counter (QPRC)
USB-Ethernet clock generator
CAN ch.0
CAN ch.1
Page 66 of 133
CY9BD10T Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
◼ INITX=0
This is the period when the INITX pin is the "L" level.
◼ INITX=1
This is the period when the INITX pin is the "H" level.
◼ SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".
◼ SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".
◼ Input enabled
Indicates that the input function can be used.
◼ Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
◼ Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
◼ Setting disabled
Indicates that the setting is disabled.
◼ Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
◼ Analog input is enabled
Indicates that the analog input is enabled.
◼ Trace output
Indicates that the trace function can be used.
Document Number: 002-05629 Rev. *H
Page 67 of 133
CY9BD10T Series
List of Pin Status
Pin
Status
type
Function group
Power-on
reset or lowvoltage
detection
state
Power supply
unstable
-
INITX input
state
Device
internal
reset state
Power supply stable
INITX=0
-
INITX=1
-
Run mode
or sleep
mode state
Power
supply
stable
INITX=1
-
SPL=1
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Main crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state/
Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
Main crystal
oscillator output pin
C
INITX input pin
D
Mode input pin
JTAG
selected
G
INITX=1
SPL=0
GPIO selected
B
F
Power supply stable
Hi-Z/ Internal
input fixed at
"0"
A
E
Timer mode or sleep mode
state
GPIO
selected
Trace selected
External interrupt
enabled selected
GPIO
selected, or resource
other than above
selected
Trace selected
GPIO selected, or
resource other than
above selected
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Input enabled
Pull-up/ Input
enabled
Input enabled
Pull-up/ Input
enabled
Input enabled
Input enabled
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Input enabled
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Trace output
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
or Input enable
Pull-up/
Input
enabled
Input enabled
Hi-Z
Hi-Z
Setting
disabled
Hi-Z
Document Number: 002-05629 Rev. *H
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Setting
disabled
Hi-Z/
Input enabled
Setting
disabled
Hi-Z/
Input enabled
Hi-Z/
Internal input
fixed at "0"
Trace output
Hi-Z/
Internal input
fixed at "0"
Page 68 of 133
CY9BD10T Series
Pin
Status
type
H
I
J
Function group
External interrupt
enabled selected
GPIO selected, or
resource other than
above selected
Power-on
reset or lowvoltage
detection
state
Power
supply
unstable
-
Device
internal
reset state
Power supply stable
INITX=0
-
INITX=1
-
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
GPIO selected,
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
NMIX selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Setting
disabled
GPIO selected, or
resource other than
above selected
Analog input
selected
K
GPIO selected, or
resource other than
above selected
External interrupt
enabled selected
L
INITX input
state
Run mode
or sleep
mode state
Power
supply
stable
INITX=1
-
Timer mode or sleep mode
state
Power supply stable
INITX=1
SPL=0
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Setting
disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
SPL=1
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"
Analog input
selected
Hi-Z
GPIO selected, or
resource other than
above selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Sub crystal oscillator
input pin
Input
enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
M
Document Number: 002-05629 Rev. *H
Page 69 of 133
CY9BD10T Series
Pin
status
type
Function group
GPIO selected
Power-on
reset or lowvoltage
detection
state
Power
supply
unstable
Setting
disabled
INITX input
state
Device
internal
reset state
Power supply stable
INITX=0
Setting
disabled
INITX=1
Setting
disabled
Run mode or
sleep mode
state
Power
supply
stable
INITX=1
-
INITX=1
SPL=0
Maintain
previous state
Maintain
previous state
Sub crystal oscillator
output pin
Hi-Z/
Internal input
fixed at "0"/
or Input enable
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
GPIO selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
Maintain
previous state
O
USB I/O pin
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Mode input pin
Input
enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Ethernet input or
output selected*3
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
P
R
Power supply stable
Maintain
previous state/
Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
N
Q
Timer mode or sleep mode
state
GPIO selected, or
resource other than
above selected
Ethernet input or
output pin selected*3
External interrupt
enabled selected
GPIO selected, or
resource other than
above selected
Maintain
previous state
Maintain
previous state
Hi-Z at
transmission/
Input enabled/
Internal input
fixed at "0" at
reception
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
SPL=1
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state/
Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Hi-Z at
transmission/
Input enabled/
Internal input
fixed at "0" at
reception
Input
enabled
Hi-Z/
Input enabled
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
*1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, and STOP mode.
*2: Oscillation is stopped at STOP mode.
*3: When selected by EPFR14.E_SPLC register.
Document Number: 002-05629 Rev. *H
Page 70 of 133
CY9BD10T Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
Min
Max
Unit
Remarks
Power supply voltage*1, *2
Power supply voltage (for USB ch.0)*1, *3
Vcc
USBVcc0
Vss - 0.5
Vss - 0.5
Vss + 6.5
Vss + 6.5
V
V
Power supply voltage (for USB ch.1)*1, *3
USBVcc1
Vss - 0.5
Vss + 6.5
V
Power supply voltage (for Ethernet)*1, *4
Analog power supply voltage*1, *5
Analog reference voltage*1, *5
ETHVcc
AVcc
AVRH
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss + 6.5
Vss + 6.5
Vss + 6.5
Vcc + 0.5
(≤ 6.5 V)
USBVcc0 + 0.5
(≤ 6.5 V)
USBVcc1 + 0.5
(≤ 6.5 V)
ETHVcc + 0.5
(≤ 6.5 V)
Vss + 6.5
AVcc + 0.5
(≤ 6.5 V)
Vcc + 0.5
(≤ 6.5 V)
+2
V
V
V
mA
*9
+20
mA
*9
10
mA
4 mA type
20
mA
8 mA type
20
39
4
8
12
18.5
100
50
- 10
mA
mA
mA
mA
mA
mA
mA
mA
mA
12 mA type
P80,P81,P82,P83
4 mA type
8 mA type
12 mA type
P80,P81,P82,P83
- 20
- 20
- 39
-4
-8
- 12
- 20.5
- 100
- 50
1000
+ 150
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
8 mA type
12 mA type
P80,P81,P82,P83
4 mA type
8 mA type
12 mA type
P80,P81,P82,P83
Vss - 0.5
Vss - 0.5
Input voltage
*1
VI
Vss - 0.5
Vss - 0.5
Vss - 0.5
Analog pin input voltage
*1
VIA
Vss - 0.5
Output voltage*1
VO
Vss - 0.5
Clamp maximum current
ICLAMP
-2
Clamp total maximum current
Σ[ICLAMP]
"L" level maximum output current
*6
IOL
-
"L" level average output current *7
IOLAV
-
"L" level total maximum output current
"L" level total average output current *8
∑IOL
∑IOLAV
-
"H" level maximum output current
*6
IOH
-
"H" level average output current *7
IOHAV
-
"H" level total maximum output current
"H" level total average output current *8
Power consumption
Storage temperature
∑IOH
∑IOHAV
PD
TSTG
- 55
V
Except for USB pin and
Ethernet-MAC pin
V
USB ch.0 pin
V
USB ch.1 pin
V
Ethernet-MAC pin
V
5 V tolerant
V
V
4 mA type
*1: These parameters are based on the condition that Vss = AVss = 0.0 V.
*2: Vcc must not drop below Vss - 0.5 V.
*3: USBVcc0 and USBVcc1 must not drop below Vss - 0.5 V.
*4: ETHVcc must not drop below Vss - 0.5 V.
*5: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*6: The maximum output current is the peak value for a single pin.
Document Number: 002-05629 Rev. *H
Page 71 of 133
CY9BD10T Series
*7: The average output is the average current for a single pin over a period of 100 ms.
*8: The total average output current is the average current for all pins over a period of 100 ms.
*9:
•
•
•
•
•
•
•
•
See "4. List of Pin Functions" and "5. I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin
does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
VCC
Protection Diode
VCC
P-ch
Limiting
resistor
+B input (0V to 16V)
Digital output
N-ch
Digital input
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess
of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-05629 Rev. *H
Page 72 of 133
CY9BD10T Series
12.2 Recommended Operating Conditions
(Vss = AVss = 0.0 V)
Parameter
Power supply voltage
Symbol
Vcc
Conditions
-
Value
Min
2.7[8]
USBVcc0
Power supply voltage
(3V power supply) for
USB ch.1
USBVcc1
V
2.7
2.7
1
- 40
+ 85
°C
2.7
3.0
2.7
3.0
Power supply voltage for Ethernet
ETHVcc
-
4.5
2.7
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
LQS144,
Operating
LQP176,
temperature
LBE192
AVcc
AVRH
CS
TA
When mounted
on four-layer
PCB
Unit
5.5
3.6
(≤ Vcc)
5.5
(≤ Vcc)
3.6
(≤ Vcc)
5.5
(≤ Vcc)
3.6
(≤ Vcc)
5.5
(≤ Vcc)
5.5
(≤ Vcc)
5.5
AVcc
10
3.0
Power supply voltage
(3V power supply) for
USB ch.0
Max
Remarks
*1
V
*2
*3
V
*4
*5
V
*5
*6
V
V
μF
AVcc = Vcc
for built-in regulator *7
*1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80).
*3: When P83/UDP1 and P82/UDM1 pin are used as USB (UDP1, UDM1).
*4: When P83/UDP1 and P82/UDM1 pin are used as GPIO (P83, P82).
*5: When the pins in "Ethernet-MAC pins" except P62/E_PPS0_PPS1/SCK5_0/ADTG_3 pin are used as Ethernet-MAC pin.
*6: When the pins in "Ethernet-MAC pins" except P62/E_PPS0_PPS1/SCK5_0/ADTG_3 pin are used as function pins other than
Ethernet-MAC pin.
*7: See "C pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*8: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges
may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating
conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are
advised to contact their representatives beforehand.
Document Number: 002-05629 Rev. *H
Page 73 of 133
CY9BD10T Series
Ethernet-MAC pins
Pin Name
Ethernet-MAC function
Except for Ethernet-MAC
function
P62/E_PPS0_PPS1/SCK5_0/ADTG_3
E_PPS0_PPS1*1
P62 /SCK5_0/ADTG_3
PC0/E_RXER0_RXDV1
E_RXER0_RXDV1
PC0
PC1/E_RX03_RX11
E_RX03_RX11
PC1
PC2/E_RX02_RX10
E_RX02_RX10
PC2
PC3/E_RX01/TIOA06_1
E_RX01
PC3/TIOA06_1
PC4/E_RX00/TIOA08_2
E_RX00
PC4/TIOA08_2
PC5/E_RXDV0/TIOA10_2
E_RXDV0
PC5/TIOA10_2
PC6/E_MDIO0/TIOA14_0
E_MDIO0
PC6/TIOA14_0
PC7/E_MDC0/CROUT_1
E_MDC0
PC7/CROUT_1
PC8/E_RXCK0_REFCK
E_RXCK0_REFCK
PC8
PC9/E_COL0
E_COL0
PC9
PCA/E_CRS0
E_CRS0
PCA
PCB/E_COUT
E_COUT
PCB
PCC/E_MDIO1
E_MDIO1
PCC
PCD/E_TCK0_MDC1
E_TCK0_MDC1
PCD
PCE/E_TXER0_TXEN1/RTS4_0/
TIOB06_1
E_TXER0_TXEN
PCE/RTS4_0/TIOB06_1
PCF/E_TX03_TX11/CTS4_0/TIOB08_2
E_TX03_TX11
PCF/CTS4_0/TIOB08_2
PD0/E_TX02_TX10/SCK4_0/TIOB10_2/
INT30_1
E_TX02_TX10
PD0/SCK4_0/TIOB10_2/
INT30_1
PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1
E_TX01
PD1/SOT4_0/TIOB14_0/
INT31_1
PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2
E_TX00
PD2/TIOA03_2/INT00_2
PD3/E_TXEN0/TIOB03_2
E_TXEN0
PD3/TIOB03_2
Power
Supply
type
Vcc
ETHVcc
*1: It is used to confirm the PTP counter cycle in Ethernet-MAC by wave forms.
Document Number: 002-05629 Rev. *H
Page 74 of 133
CY9BD10T Series
12.3 DC Characteristics
12.3.1
Current Rating
(Vcc = AVcc = USBVcc0 = USBVcc1 = ETHVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
PLL
RUN mode
RUN
mode
current
Icc
High-speed
CR
RUN mode
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
SLEEP
mode
current
Iccs
PLL
SLEEP mode
High-speed
CR
SLEEP mode
Sub
SLEEP mode
Low-speed
CR
SLEEP mode
CPU: 144 MHz,
Peripheral: 72 MHz,
Flash 2 Wait,
TraceBuffer: ON,
FRWTR.RWT = 10,
FSYNDN.SD = 000,
FBFCR.BE = 1
CPU: 72 MHz,
Peripheral: 72 MHz,
Flash 0 Wait,
TraceBuffer: OFF,
FRWTR.RWT = 00,
FSYNDN.SD = 000,
FBFCR.BE = 0
Value
Typ[3]
Max[4]
Unit
Remarks
100
180
mA
*1, *5
65
135
mA
*1, *5
6
57.8
mA
*1
1.3
51.7
mA
*1, *6
1.3
51.7
mA
*1
Peripheral: 72 MHz
30
89
mA
*1, *5
Peripheral: 4 MHz[2]
4.5
55.9
mA
*1
Peripheral: 32 kHz
1.2
51.6
mA
*1, *6
Peripheral: 100 kHz
1.2
51.6
mA
*1
CPU/ Peripheral: 4 MHz[2],
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 32 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 100 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
*1: When all ports are fixed, Ethernet is stopped.
*2: When setting it to 4 MHz by trimming.
*3: TA = +25°C, VCC = 5.5 V
*4: TA = +85°C, VCC = 5.5 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05629 Rev. *H
Page 75 of 133
CY9BD10T Series
(Vcc = AVcc = USBVcc0 = USBVcc1 = ETHVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, TA = - 40°C to + 85°C)
Parameter
TIMER
mode
current
Pin
name
Symbol
Main
TIMER
mode
ICCT
VCC
STOP
mode
current
ICCH
Value
Typ*2
Max*2
Conditions
Sub
TIMER
mode
STOP mode
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
Unit
Remarks
4
10
mA
*1, *3
-
55
mA
*1, *3
1.1
5
mA
*1, *4
-
50
mA
*1, *4
1
5
mA
*1
-
50
mA
*1
*1: When all ports are fixed.
*2: VCC = 5.5 V
*3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C)
Parameter
Low-voltage detection
circuit (LVD) power
supply current
Symbol
ICCLVD
Pin
name
VCC
Value
Conditions
At operation
for interrupt
Typ
4
Max
7
Unit
μA
Remarks
At not detect
Flash Memory Current
(VCC = 2.7 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C)
Parameter
Flash memory
write/erase
current
Symbol
ICCFLASH
Pin
name
VCC
Value
Conditions
At Write/Erase
Typ
12
Max
14
Unit
Remarks
mA
A/D Converter Current
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = AVRL = 0 V, TA = - 40°C to + 85°C)
Parameter
Power supply current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Document Number: 002-05629 Rev. *H
Pin
name
Value
Conditions
Typ
Max
Unit
At 1 unit operation
0.57
0.72
mA
At stop
0.06
35
μA
At 1unit operation
AVRH=5.5 V
1.1
1.96
mA
At stop
0.06
4
μA
Remarks
AVCC
AVRH
Page 76 of 133
CY9BD10T Series
12.3.2
Pin Characteristics
(Vcc = USBVcc0 = USBVcc1 = ETHVcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, TA = - 40°C to + 85°C)
Parameter
"H" level input
voltage
(hysteresis
input)
"L" level input
voltage
(hysteresis
input)
Symbol
VIHS
VILS
Pin name
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
TTL Schmitt
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
TTL Schmitt
input pin
4 mA type
8 mA type
"H" level
output voltage
VOH
12 mA type
P80, P81,
P82, P83
Document Number: 002-05629 Rev. *H
Conditions
-
Min
Vcc
(ETHVcc) × 0.8
Value
Typ
Max
Unit
Remarks
*1
-
Vcc
(ETHVcc) + 0.3
V
-
Vcc × 0.8
-
Vss + 5.5
V
-
2.0
-
ETHVcc + 0.3
V
-
Vss - 0.3
-
Vcc
(ETHVcc) × 0.2
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
0.8
V
Vcc
(ETHVcc) - 0.5
-
Vcc
(ETHVcc)
V
*1
ETHVcc - 0.5
-
ETHVcc
V
*1
Vcc - 0.5
-
Vcc
V
USBVcc - 0.4
-
USBVcc
V
Vcc (ETHVcc) ≥ 4.5 V,
IOH = - 4 mA
Vcc (ETHVcc) < 4.5 V,
IOH = - 2 mA
ETHVcc ≥ 4.5 V,
IOH = - 8 mA
ETHVcc < 4.5 V,
IOH = - 4 mA
Vcc ≥ 4.5 V,
IOH = - 12 mA
Vcc < 4.5 V,
IOH = - 8 mA
USBVcc ≥ 4.5 V,
IOH = - 20.5 mA
USBVcc < 4.5 V,
IOH = - 13.0 mA
*1
*2
Page 77 of 133
CY9BD10T Series
Parameter
Symbol
Pin name
4 mA type
8 mA type
"L" level
output voltage
VOL
12 mA type
P80, P81,
P82, P83
Input leak current
Pull-up resistance
value
Input capacitance
IIL
-
RPU
Pull-up pin
CIN
Other than
VCC,
USBVCC0,
USBVCC1,
ETHVCC,
VSS,
AVCC,
AVSS, AVRH
Value
Conditions
Vcc (ETHVcc) ≥ 4.5 V,
IOL = 4 mA
Vcc (ETHVcc) < 4.5 V,
IOL = 2 mA
ETHVcc ≥ 4.5 V,
IOL = 8 mA
ETHVcc < 4.5 V,
IOL = 4 mA
Vcc ≥ 4.5 V,
IOL = 12 mA
Vcc < 4.5 V,
IOL = 8 mA
USBVcc ≥ 4.5 V,
IOL = 18.5 mA
USBVcc < 4.5 V,
IOL = 10.5 mA
-
Min
Typ
Max
Unit
Remarks
Vss
-
0.4
V
*1
Vss
-
0.4
V
*1
Vss
-
0.4
V
Vss
-
0.4
V
μA
-5
-
+5
Vcc ≥ 4.5 V
25
50
100
Vcc < 4.5 V
30
80
200
-
-
5
15
*2
kΩ
pF
*1: The power supply type varies depending on the pin position.
For example, power supply A (power supply B) shows that either of power supply A or power supply B becomes a power supply
voltage.
*2: USBVcc0 and USBVcc1 are described as USBVcc.
Document Number: 002-05629 Rev. *H
Page 78 of 133
CY9BD10T Series
12.4 AC Characteristics
12.4.1
Main Clock Input Characteristics
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Input frequency
FCH
Input clock cycle
tCYLH
Input clock pulse width
-
Input clock rise time and
fall time
tCF,
tCR
Internal operating
Clock[1] frequency
Internal operating
Clock*1 cycle time
Pin
name
Symbol
X0,
X1
Value
Conditions
Min
Max
Unit
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
PWH/tCYLH,
PWL/tCYLH
4
4
4
4
20
50
50
20
50
20
250
250
45
55
%
-
-
5
ns
Remarks
MHz
When crystal oscillator is
connected
MHz
When using external
clock
ns
When using external
clock
When using external
clock
When using external
clock
FCM
-
-
-
144
MHz
Master clock
FCC
-
-
-
144
MHz
Base clock (HCLK/FCLK)
FCP0
FCP1
-
-
-
72
72
MHz
MHz
APB0 bus clock*2
APB1 bus clock*2
FCP2
-
-
-
72
MHz
APB2 bus clock*2
tCYCC
-
-
6.94
-
ns
Base clock (HCLK/FCLK)
tCYCP0
tCYCP1
-
-
13.8
13.8
-
ns
ns
APB0 bus clock*2
APB1 bus clock*2
tCYCP2
-
-
13.8
-
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this datasheet.
X0
Document Number: 002-05629 Rev. *H
Page 79 of 133
CY9BD10T Series
12.4.2
Sub Clock Input Characteristics
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Input frequency
1/tCYLL
Input clock cycle
tCYLL
Input clock pulse width
-
Pin
name
X0A,
X1A
Value
Conditions
Min
Typ
Max
Unit
Remarks
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
-
10
-
31.25
μs
When using external clock
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external clock
X0A
Document Number: 002-05629 Rev. *H
Page 80 of 133
CY9BD10T Series
12.4.3
Internal CR Oscillation Characteristics
High-speed internal CR
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Frequency stability time
Symbol
FCRH
tCRWT
Value
Conditions
Min
Typ
Max
TA = + 25°C
3.96
4
4.04
TA = 0°C to + 70°C
3.84
4
4.16
TA = - 40°C to + 85°C
3.8
4
4.2
TA = - 40°C to + 85°C
3
4
5
-
-
-
90
Unit
Remarks
When trimming*1
MHz
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the
trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.
Low-speed internal CR
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
FCRL
Document Number: 002-05629 Rev. *H
Conditions
-
Value
Min
50
Typ
100
Max
150
Unit
Remarks
kHz
Page 81 of 133
CY9BD10T Series
12.4.4
Operating Conditions of Main and USB/Ethernet PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
USB/Ethernet clock frequency*3
FPLLI
FPLLO
FCLKPLL
FCLKSPLL
4
13
200
-
-
16
75
300
144
50
MHz
multiple
MHz
MHz
MHz
Remarks
After the M frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*3: For more information about USB/Ethernet clock, see "Chapter 2-3: USB/Ethernet Clock Generation" in "FM3 Family Peripheral
Manual Communication Macro Part".
12.4.5
Operating Conditions of Main PLL (In the case of using built-in high-speed internal CR)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLI
FPLLO
FCLKPLL
3.8
50
190
-
4
-
4.2
71
300
144
MHz
multiple
MHz
MHz
Remarks
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
PLL input
K
clock
divider
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-05629 Rev. *H
Page 82 of 133
CY9BD10T Series
USB/Ethernet PLL connection
Main clock (CLKMO)
K
divider
PLL input
clock
PLL macro
oscillation clock
USB/Ethernet
PLL
USB/Ethernet
clock
M
divider
N
divider
12.4.6
Reset Input Characteristics
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Reset input time
12.4.7
tINITX
Pin name
INITX
Value
Conditions
Min
-
Unit
Max
500
-
Remarks
ns
Power-on Reset Timing
(Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Power supply shut down time
tOFF
Power ramp rate
dV/dt
Time until releasing Power-on reset
tPRT
Pin name
VCC
Value
Conditions
Unit
Remarks
Min
Typ
Max
-
50
-
-
ms
*1
Vcc:0.2 V to 2.70
V
0.9
-
1000
mV/μs
*2
-
0.46
-
0.76
ms
*1: VCC must be held below 0.2V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary:
VDH: detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics”
Document Number: 002-05629 Rev. *H
Page 83 of 133
CY9BD10T Series
12.4.8
External Bus Timing
External bus clock output characteristics
(Vcc = 2.7 V to 5.5V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Output frequency
Symbol
Pin name
MCLKOUT*1
tCYCLE
Value
Conditions
Min
Unit
Max
Vcc ≥ 4.5 V
-
50*2
MHz
Vcc < 4.5 V
-
32*3
MHz
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "Chapter 12: External Bus Interface" in "FM3 Family Peripheral
Manual".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100 MHz, the divider setting for MCLKOUT must be more than 4.
*3: When AHB bus clock frequency is more than 64 MHz, the divider setting for MCLKOUT must be more than 4.
MCLKOUT
External bus signal input/output characteristics
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Signal input characteristics
Signal output characteristics
Symbol
Conditions
VIH
VIL
-
VOH
VOL
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Document Number: 002-05629 Rev. *H
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
Page 84 of 133
CY9BD10T Series
Separate bus access asynchronous SRAM mode
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
MOEX
Min pulse width
MCSX ↓ → Address output
delay time
MOEX ↑ →
Address hold time
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MCSX ↑ time
MCSX ↓ →
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑ →
Data hold time
MWEX
Min pulse width
MWEX ↑ → Address output
delay time
MCSX ↓ →
MWEX ↓ delay time
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓ →
MDQM ↓ delay time
MCSX ↓ →
Data output time
MWEX ↑ →
Data hold time
Symbol
tOEW
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
tDH - OE
Pin name
MOEX
MCSX[7:0],
MAD[24:0]
MOEX,
MAD[24:0]
MOEX,
MCSX[7:0]
MCSX,
MDQM[1:0]
MOEX,
MADATA[15:0]
MOEX,
MADATA[15:0]
tWEW
MWEX
tWEH - AX
MWEX,
MAD[24:0]
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
MWEX,
MCSX[7:0]
MCSX,
MDQM[1:0]
MCSX,
MADATA[15:0]
MWEX,
MADATA[15:0]
Value
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Min
Max
Unit
MCLK×n-3
-
-9
-12
MCLK×m-9
MCLK×m-12
20
38
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
0
-
ns
MCLK×n-3
-
ns
0
MCLK×m-9
MCLK×m-12
0
0
MCLK×n-9
MCLK×n-12
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCLK-12
0
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Document Number: 002-05629 Rev. *H
Page 85 of 133
CY9BD10T Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
Document Number: 002-05629 Rev. *H
Page 86 of 133
CY9BD10T Series
Separate bus access synchronous SRAM mode
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Address delay time
Symbol
tCSL
MCLK,
MCSX[7:0]
tCSH
tREL
MCLK,
MOEX
MOEX delay time
tREH
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
tDS
tDH
tWEL
MCLK,
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
MCLK ↑ →
Data output time
MCLK ↑ →
Data hold time
tDQML
MCLK,
MDQM[1:0]
tDQMH
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
tOD
tOD
Value
Conditions
Min
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK,
MAD[24:0]
tAV
MCSX delay time
Data set up →
MCLK ↑ time
MCLK ↑ →
Data hold time
Pin name
Max
9
12
9
12
9
12
9
12
9
12
1
1
1
1
1
Unit
ns
ns
ns
ns
ns
19
37
-
ns
0
-
ns
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
1
1
1
1
MCLK+1
1
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance = 30 pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
MAD[24:0]
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
Document Number: 002-05629 Rev. *H
Page 87 of 133
CY9BD10T Series
Multiplexed bus access asynchronous SRAM mode
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Multiplexed
address delay time
Multiplexed
address hold time
Symbol
tALE-CHMADV
tCHMADH
Pin name
MALE,
MADATA[15:0]
Value
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Min
0
MCLK×n+0
MCLK×n+0
Max
10
20
MCLK×n+10
MCLK×n+20
Unit
ns
ns
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05629 Rev. *H
Page 88 of 133
CY9BD10T Series
Multiplexed bus access synchronous SRAM mode
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK ↑ →
Multiplexed
Address delay time
tCHMADV
MCLK ↑ →
Multiplexed
Data output time
tCHMADX
Pin name
MCLK,
ALE
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
MCLK,
MADATA[15:0]
Value
Conditions
Min
Max
Unit
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Remarks
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Note:
−
When the external load capacitance = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05629 Rev. *H
Page 89 of 133
CY9BD10T Series
NAND flash mode
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
MNREX
Min pulse width
Data setup →
MNREX↑time
MNREX↑→
Data hold time
MNALE↑→
MNWEX delay time
MNALE↓→
MNWEX delay time
MNCLE↑→
MNWEX delay time
MNWEX↑→
MNCLE delay time
MNWEX
Min pulse width
MNWEX↓→
Data output time
MNWEX↑→
Data hold time
Symbol
tNREW
tDS – NRE
tDH – NRE
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
tNWEL – DV
tNWEH – DX
Pin name
MNREX
MNREX,
MADATA[15:0]
MNREX,
MADATA[15:0]
MNALE,
MNWEX
MNALE,
MNWEX
MNCLE,
MNWEX
MNCLE,
MNWEX
MNWEX
MNWEX,
MADATA[15:0]
MNWEX,
MADATA[15:0]
Value
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Min
Max
Unit
MCLK×n-3
-
ns
20
38
-
ns
0
-
ns
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
0
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
0
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Document Number: 002-05629 Rev. *H
Read
Page 90 of 133
CY9BD10T Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Document Number: 002-05629 Rev. *H
Write
Page 91 of 133
CY9BD10T Series
External ready input timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
MCLK ↑
MRDY input
setup time
tRDYI
Pin name
MCLK,
MRDY
Value
Conditions
Min
Vcc ≥ 4.5 V
19
Vcc < 4.5 V
37
Unit
Max
-
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
MRDY
Document Number: 002-05629 Rev. *H
tRDYI
0.5×VCC
Page 92 of 133
CY9BD10T Series
12.4.9
Base Timer Input Timing
Timer input timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
TIOAn/TIOBn
(when using as ECK,
TIN)
tTIWH,
tTIWL
-
tTIWH
ECK
VIHS
TIN
Value
Min
2tCYCP
Unit
Max
-
Remarks
ns
tTIWL
VIHS
VILS
VILS
Trigger input timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin name
Conditions
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
2tCYCP
Max
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Notes:
−
tCYCP indicates the APB bus clock cycle time.
−
About the APB bus number which Base Timer is connected to, see "8. Block Diagram" in this datasheet.
Document Number: 002-05629 Rev. *H
Page 93 of 133
CY9BD10T Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Pin
name
Symbol
Baud rate
-
-
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
Vcc < 4.5 V
Min
Max
Conditions
-
Master mode
Slave mode
Vcc ≥ 4.5 V
Min
Max
Unit
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
−
−
tCYCP indicates the APB bus clock cycle time.
−
When the external load capacitance = 30 pF.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this datasheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed
Document Number: 002-05629 Rev. *H
Page 94 of 133
CY9BD10T Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
SIN
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05629 Rev. *H
Page 95 of 133
CY9BD10T Series
CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Baud rate
Serial clock cycle time
tSCYC
SCKx
SCK ↑ → SOT delay time
tSHOVI
SCKx,
SOTx
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Vcc < 4.5 V
Min
Max
Conditions
-
Master mode
Slave mode
Vcc ≥ 4.5 V
Min
Max
Unit
4tCYCP
8
-
4tCYCP
8
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-05629 Rev. *H
Page 96 of 133
CY9BD10T Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05629 Rev. *H
Page 97 of 133
CY9BD10T Series
CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Baud rate
Serial clock cycle time
tSCYC
SCKx
SCK ↑ → SOT delay time
tSHOVI
SCKx,
SOTx
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Vcc < 4.5 V
Min
Max
Conditions
-
Master mode
Slave mode
Vcc ≥ 4.5 V
Min
Max
Unit
4tCYCP
8
-
4tCYCP
8
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-05629 Rev. *H
Page 98 of 133
CY9BD10T Series
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05629 Rev. *H
Page 99 of 133
CY9BD10T Series
CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Baud rate
Serial clock cycle time
tSCYC
SCKx
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Vcc < 4.5 V
Min
Max
Conditions
-
Master mode
Slave mode
Vcc ≥ 4.5 V
Min
Max
Unit
4tCYCP
8
-
4tCYCP
8
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-05629 Rev. *H
Page 100 of 133
CY9BD10T Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tSHSL
tR
SCK
tSLSH
VIH
VIH
VIL
tF
VIL
VIL
VIH
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
SCK rise time
Symbol
tSLSH
tSHSL
tF
tR
VIL
Document Number: 002-05629 Rev. *H
Min
tSHSL
VIH
5
5
VIL
Remarks
ns
ns
ns
ns
tF
tSLSH
VIH
Unit
Max
tCYCP + 10
tCYCP + 10
-
CL = 30 pF
tR
SCK
Value
Conditions
VIL
VIH
Page 101 of 133
CY9BD10T Series
12.4.11 External Input Timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Value
Min
Conditions
Max
Unit
ADTG
Input pulse width
tINH,
tINL
FRCKx
ICxx
DTTIxX
INTxx,
NMIX
Remarks
A/D converter trigger input
-
2tCYCP*1
-
ns
Except
Timer mode,
Stop mode
Timer mode,
Stop mode
2tCYCP*1
-
ns
2tCYCP + 100*1
-
ns
500
-
ns
Free-run timer input clock
Input capture
Wave form generator
External interrupt
NMI
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "8. Block
Diagram" in this datasheet.
Document Number: 002-05629 Rev. *H
Page 102 of 133
CY9BD10T Series
12.4.12 Quadrature Position/Revolution Counter timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and fall time from
determined ZIN level
Determined ZIN level from AIN/BIN
rise and fall time
Value
Conditions
tAHL
tALL
tBHL
tBLL
-
tAUBU
PC_Mode2 or PC_Mode3
tBUAD
PC_Mode2 or PC_Mode3
tADBD
PC_Mode2 or PC_Mode3
tBDAU
PC_Mode2 or PC_Mode3
tBUAU
PC_Mode2 or PC_Mode3
tAUBD
PC_Mode2 or PC_Mode3
tBDAD
PC_Mode2 or PC_Mode3
tADBU
PC_Mode2 or PC_Mode3
tZHL
tZLL
QCR:CGSC="0"
QCR:CGSC="0"
tZABE
QCR:CGSC="1"
tABEZ
QCR:CGSC="1"
Min
Unit
Max
2tCYCP*1
-
ns
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "8. Block Diagram" in this
datasheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-05629 Rev. *H
tBLL
Page 103 of 133
CY9BD10T Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05629 Rev. *H
Page 104 of 133
CY9BD10T Series
12.4.13 I2C Timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
SCL clock frequency
(Repeated) START condition hold time
SDA ↓ → SCL ↓
SCLclock "L" width
SCLclock "H" width
(Repeated) START setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Noise filter
Symbol
Standard-mode
Min
Max
Conditions
Fast-mode
Min
Max
Unit
Remarks
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 tCYCP*4
-
2 tCYCP*4
-
ns
*5
3 tCYCP*4
-
3 tCYCP*4
-
ns
*5
4 tCYCP*4
-
4 tCYCP*4
-
ns
*5
tSUSTA
tHDDAT
tSP
CL = 30 pF,
R = (Vp/IOL)*1
8 MHz ≤
tCYCP ≤ 40 MHz
40 MHz <
tCYCP ≤ 60 MHz
60 MHz <
tCYCP ≤ 72 MHz
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement
of "tSUDAT ≥ 250 ns"
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number which I2C is connected to, see "8. Block Diagram" in this datasheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
*5: The number of steps of the noise filter can be changed with register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
SDA
SCL
Document Number: 002-05629 Rev. *H
Page 105 of 133
CY9BD10T Series
12.4.14 ETM Timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Data hold
tETMH
TRACECLK
frequency
1/ tTRACE
Pin name
TRACECLK,
TRACED[3:0]
TRACECLK
TRACECLK
cycle time
tTRACE
Value
Min
Max
Conditions
Unit
Vcc ≥ 4.5 V
2
9
Vcc < 4.5 V
2
15
Vcc ≥ 4.5 V
-
50
MHz
Vcc < 4.5 V
-
32
MHz
Vcc ≥ 4.5 V
20
-
ns
Vcc < 4.5 V
31.25
-
ns
Remarks
ns
Note:
−
When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05629 Rev. *H
Page 106 of 133
CY9BD10T Series
12.4.15 JTAG Timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
Vcc ≥ 4.5 V
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
Vcc ≥ 4.5 V
TDO delay time
tJTAGD
TCK,
TDO
Min
Value
Max
Unit
15
-
ns
15
-
ns
Vcc ≥ 4.5 V
-
25
Vcc < 4.5 V
-
45
Vcc < 4.5 V
Vcc < 4.5 V
Remarks
ns
Note:
−
When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05629 Rev. *H
Page 107 of 133
CY9BD10T Series
12.4.16 Ethernet-MAC Timing
RMII transmission (100 Mbps/10 Mbps)
(ETHVcc = 3.0 V to 3.6 V, 4.5 V to 5.5 V *1)
(Vss = 0 V, TA = - 40°C to + 85°C, CL=25 pF)
Parameter
Reference Clock
Cycle time*2
Reference Clock
High pulse width duty
Reference Clock
Low pulse width duty
Symbol
tREFCYC
E_RXCK0_REFCK
tREFCYCH
E_RXCK0_REFCK
tREFCYCL
E_RXCK0_REFCK
tRMIITX
E_TX01,
E_TX00,
E_TXEN0
E_TX03_TX11,
E_TX02_TX10,
E_TXER0_TXEN1
REFCK ↑ → Transmitted data
Delay time (ch.0)
REFCK ↑ → Transmitted data
Delay time (ch.1)
Pin name
Conditions
20 ns (typical)
tREFCYCH /
tREFCYC
tREFCYCL /
tREFCYC
-
Min
Value
Max
Unit
-
-
ns
35
65
%
35
65
%
-
12
ns
*1: When ETHV = 4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the output current.
*2: The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device
specifications.
tREFCYC
E_RXCK0_REFCK
VIHS
tREFCYCH
E_TX03_TX11
E_TX02_TX10
E_TX01
E_TX00
E_TXEN0
E_TXER0_TXEN1
Document Number: 002-05629 Rev. *H
VIHS
VILS
tREFCYCL
VOH
VOL
tRMIITX
Page 108 of 133
CY9BD10T Series
RMII receiving (100 Mbps/10 Mbps)
(ETHVcc = 3.0 V to 3.6 V, 4.5 V to 5.5 V)
(Vss = 0 V, TA = - 40°C to + 85°C, CL=25 pF)
Parameter
Reference Clock
Cycle time*1
Reference Clock
High pulse width duty
Reference Clock
Low pulse width duty
Symbol
tREFCYC
E_RXCK0_REFCK
tREFCYCH
E_RXCK0_REFCK
tREFCYCL
E_RXCK0_REFCK
Received data → REFCK↑
Setup time(ch.0)
tRMIIRXS
Received data → REFCK↑
Setup time(ch.1)
REFCK ↑ → Received data
Hold time(ch.0)
tRMIIRXH
REFCK ↑ → Received data
Hold time (ch.1)
Pin name
Value
Conditions
20 ns (typical)
Max
Unit
-
-
ns
35
65
%
35
65
%
-
4
-
ns
-
2
-
ns
tREFCYCH /
tREFCYC
tREFCYCL /
tREFCYC
E_RX01,
E_RX00,
E_RXDV0
E_RX03_RX11,
E_RX02_RX10,
E_RXER0_RXDV1
E_RX01,
E_RX00,
E_RXDV0
E_RX03_RX11,
E_RX02_RX10,
E_RXER0_RXDV1
Min
*1: The reference clock is fixed to 50 MHz in the RMII specifications.
The clock accuracy should meet the PHY-device specifications.
tREFCYC
E_RXCK0_REFCK
VIHS
E_RX03_RX11
E_RX02_RX10
E_RX01
E_RX00
E_RXDV0
E_RXER0_RXDV1
Document Number: 002-05629 Rev. *H
tREFCYCH
VIHS
VILS
tRMIIRXS
VIHS
VILS
tREFCYCL
VIHS
VILS
tRMIIRXH
Page 109 of 133
CY9BD10T Series
Management interface
(ETHVcc = 3.0 V to 3.6 V, 4.5 V to 5.5 V)
(Vss = 0 V, TA = - 40°C to + 85°C, CL=25 pF)
Parameter
Management Clock
Cycle time*1 (ch.0)
Management Clock
Cycle time*1 (ch.1)
Management Clock
High pulse width duty (ch.0)
Management Clock
High pulse width duty (ch.1)
Management Clock
Low pulse width duty (ch.0)
Management Clock
Low pulse width duty (ch.1)
MDC ↓ → MDIO
Delay time (ch.0)
MDC ↓ → MDIO
Delay time (ch.1)
MDIO → MDC ↑
Setup time (ch.0)
MDIO → MDC ↑
Setup time (ch.1)
MDC ↑ → MDIO
Hold time (ch.0)
MDC ↑ → MDIO
Hold time (ch.1)
Symbol
Pin name
Value
Conditions
Min
Max
Unit
E_MDC0
tMDCYC
-
400
-
ns
tMDCYCH /
tMDCYC
45
55
%
tMDCYCL /
tMDCYC
45
55
%
-
-
60
ns
-
20
-
ns
-
0
-
ns
E_TCK0_MDC1
E_MDC0
tMDCYCH
E_TCK0_MDC1
E_MDC0
tMDCYCL
E_TCK0_MDC1
E_MDIO0
tMDO
E_MDIO1
E_MDIO0
tMDIS
E_MDIO1
E_MDIO0
tMDIH
E_MDIO1
*1: The clock time should be set to a value greater than the minimum value by setting the Ether-MAC setting register.
tMDCYC
E_MDC0 (output)
E_TCK0_MDC1 (output)
VOH
VOL
tMDCYCH
E_MDIO0 (input)
E_MDIO1 (input)
Document Number: 002-05629 Rev. *H
tMDCYCL
VIHS
VILS
VIHS
VILS
VIHS
VILS
VIHS
VILS
tMDIS
tMDIH
tMDIS
tMDIH
tMDO
tMDO
E_MDIO0 (output)
E_MDIO1 (output)
VOH
VOL
VOH
VOL
VOH
VOL
Page 110 of 133
CY9BD10T Series
MII transmission (100 Mbps/10 Mbps)
(ETHVcc = 3.0 V to 3.6 V, 4.5V to 5.5 V *1)
(Vss = 0 V, TA = - 40°C to + 85°C, CL=25 pF)
Parameter
Transmission Clock
Cycle time*2
Transmission Clock
High pulse width duty
Transmission Clock
Low pulse width duty
TXCK ↑ → Transmitted data
Delay time
Symbol
tTXCYC
Pin name
100 Mbps,
40 ns (typical)
10 Mbps,
400 ns (typical)
tTXCYCH /
tTXCYC
tTXCYCL /
tTXCYC
E_TCK0_MDC1
tTXCYCH
E_TCK0_MDC1
tTXCYCL
E_TCK0_MDC1
tMIITX
E_TX03_TX11,
E_TX02_TX10,
E_TX01,
E_TX00,
E_TXEN0,
E_TXER0_TXEN1
Value
Conditions
-
Min
Max
Unit
-
-
ns
-
-
ns
35
65
%
35
65
%
-
24
ns
*1: When ETHV = 4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the output current.
*2: The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications.
The clock accuracy should meet the PHY-device specifications.
tTXCYC
E_TCK0_MDC1
VIHS
E_TX03_TX11
E_TX02_TX10
E_TX01
E_TX00
E_TXEN0
E_TXER0_TXEN1
Document Number: 002-05629 Rev. *H
VIHS
VILS
tTXCYCH
tTXCYCL
VOH
VOL
tMIITX
Page 111 of 133
CY9BD10T Series
MII receiving (100 Mbps/10 Mbps)
(ETHVcc = 3.0 V to 3.6 V, 4.5 V to 5.5 V)
(Vss = 0 V, TA = - 40°C to + 85°C, CL=25 pF)
Parameter
Receiving Clock
Cycle time*1
Receiving Clock
High pulse width duty
Receiving Clock
Low pulse width duty
Symbol
Pin name
tRXCYC
E_RXCK0_REFCK
tRXCYCL
E_RXCK0_REFCK
tMIIRXS
REFCK ↑ → Received data
Hold time
tMIIRXH
100 Mbps,
40 ns (typical)
10 Mbps,
400 ns (typical)
tRXCYCH /
tRXCYC
tRXCYCL /
tRXCYC
E_RXCK0_REFCK
tRXCYCH
Received data → REFCK ↑
Setup time
Conditions
E_RX03_RX11,
E_RX02_RX10,
E_RX01,
E_RX00,
E_RXDV0,
E_RXER0_RXDV1
E_RX03_RX11,
E_RX02_RX10,
E_RX01,
E_RX00,
E_RXDV0,
E_RXER0_RXDV1
Min
Value
Max
Unit
-
-
ns
-
-
ns
35
65
%
35
65
%
-
5
-
ns
-
2
-
ns
*1: The receiving clock 100 Mbps is fixed to 25 MHz or 2.5 MHz in the MII specifications.
The clock accuracy should meet the PHY-device specifications.
tRXCYC
E_RXCK0_REFCK
VIHS
E_RX03_RX11
E_RX02_RX10
E_RX01
E_RX00
E_RXDV0
E_RXER0_RXDV1
Document Number: 002-05629 Rev. *H
VIHS
tRXCYCH
VIHS
VILS
tMIIRXS
VILS
tRXCYCL
VIHS
VILS
tMIIRXH
Page 112 of 133
CY9BD10T Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
Parameter
(Vcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, TA = - 40°C to + 85°C)
Value
Unit
Remarks
Min
Typ
Max
Pin
name
Symbol
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
VZT
VFST
ANxx
ANxx
Conversion time
-
-
-
-
12
± 4.5
± 2.5
± 15
AVRH ± 15
1.0*1
-
-
1.2*1
-
-
*2
-
-
*2
-
-
bit
LSB
LSB
mV
mV
μs
Sampling time
Ts
-
Compare clock cycle*3
Tcck
-
50
-
2000
ns
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistance
RAIN
-
-
-
Interchannel disparity
Analog port input leak current
-
ANxx
-
-
3.8
4
5
Analog input voltage
-
ANxx
AVSS
-
AVRH
V
Reference voltage
-
AVRH
2.7
-
AVCC
V
2
ns
kΩ
AVRH = 2.7 V to 5.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
LSB
μA
*1: The Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5 V, HCLK=120 MHz
AVcc < 4.5 V, HCLK=120 MHz
sampling time: 300 ns
sampling time: 500 ns
compare time: 700 ns
compare time: 700 ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral Manual
Analog Macro Part".
The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this datasheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
Document Number: 002-05629 Rev. *H
Page 113 of 133
CY9BD10T Series
Analog
signal source
Rext
ANxx
Analog input pin
Comparator
RAIN
CAIN
(Equation 1) Ts ≥ (RAIN + Rext) × CAIN × 9
Ts:
Sampling time
RAIN: Input resistance of A/D = 2 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistance of A/D = 3.8 kΩ at 2.7 V ≤ AVCC < 4.5 V
CAIN: Input capacity of A/D = 12.9 pF at 2.7 V ≤ AVCC ≤ 5.5 V
Rext: Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck: Compare clock cycle
Document Number: 002-05629 Rev. *H
Page 114 of 133
CY9BD10T Series
Definition of 12-bit A/D converter terms
◼ Resolution:
Analog variation that is recognized by an A/D converter.
◼ Integral Nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
◼ Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
Digital output
Digital output
0xFFD
Differential Nonlinearity
(Actually-measured
value)
0x003
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
0xN
Ideal characteristics
VNT
Actual conversion characteristics
AVRH
AVss
Analog input
Integral Nonlinearity of digital output N =
N:
VZT:
VFST:
VNT:
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Differential Nonlinearity of digital output N =
1LSB =
(Actually-measured
value)
(Actually-measured
value)
0x(N-2)
VZT (Actually-measured value)
AVss
V(N+1)T
0x(N-1)
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05629 Rev. *H
Page 115 of 133
CY9BD10T Series
12.6 USB characteristics
The USB characteristics of ch.0 and those of ch.1 are the same.
USBVcc0 and USBVcc1 are described as USBVcc below.
(Vcc = 2.7 V to 5.5 V, USBVcc = 3.0 V to 3.6 V, Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Input
characteristics
Output
characteristics
Symbol
Pin
name
Value
Conditions
Min
Max
Unit
Remarks
Input "H" level voltage
VIH
-
2.0
USBVcc + 0.3
V
*1
Input "L" level voltage
VIL
-
Vss - 0.3
0.8
V
*1
Differential input sensitivity
VDI
-
0.2
-
V
*2
Different common mode range
VCM
-
0.8
2.5
V
*2
2.8
3.6
V
*3
0.0
0.3
V
*3
1.3
4
4
90
28
75
75
80
2.0
20
20
111.11
44
300
300
125
V
ns
ns
%
Ω
ns
ns
%
*4
*5
*5
*5
*6
*7
*7
*7
Output "H" level voltage
VOH
Output "L" level voltage
VOL
Crossover voltage
Rise time
Fall time
Rise/ fall time matching
Output impedance
Rise time
Fall time
Rise/ fall time matching
VCRS
tFR
tFF
tFRFM
ZDRV
tLR
tLF
tLRFM
UDP0,
UDM0
External pull-down
resistance = 15 kΩ
External pull-up
resistance = 1.5 kΩ
Full-Speed
Full-Speed
Full-Speed
Full-Speed
Low-Speed
Low-Speed
Low-Speed
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
Minimum differential input
sensitivity [V]
*2: Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V
to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
Document Number: 002-05629 Rev. *H
Page 116 of 133
CY9BD10T Series
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above
(to ground and 1.5 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
*5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
Document Number: 002-05629 Rev. *H
Falling time
Page 117 of 133
CY9BD10T Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential
Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series
resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25 Ω to 30 Ω
Series resistor of 27 Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See Figure "Low-speed load (compliance load)" for conditions of external load.
Document Number: 002-05629 Rev. *H
Page 118 of 133
CY9BD10T Series
Low-speed load (upstream port load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
Low-speed load (downstream port load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
Low-speed load (compliance load)
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-05629 Rev. *H
Page 119 of 133
CY9BD10T Series
12.7 Low-Voltage Detection Characteristics
12.7.1
Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Parameter
Detected voltage
Released voltage
12.7.2
Symbol
Conditions
VDL
VDH
-
Value
Typ
Min
2.25
2.30
Max
2.45
2.50
2.65
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Parameter
Symbol
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait time
TLVDW
Conditions
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Value
Typ
Min
Max
Unit
Remarks
2.58
2.67
2.76
2.8
2.9
3.0
3.02
3.13
3.24
V
V
V
When voltage drops
When voltage rises
When voltage drops
2.85
3.1
3.34
V
When voltage rises
2.94
3.2
3.45
V
When voltage drops
3.04
3.3
3.56
V
When voltage rises
3.31
3.6
3.88
V
When voltage drops
3.40
3.7
3.99
V
When voltage rises
3.40
3.7
3.99
V
When voltage drops
3.50
3.8
4.10
V
When voltage rises
3.68
4.0
4.32
V
When voltage drops
3.77
4.1
4.42
V
When voltage rises
3.77
4.1
4.42
V
When voltage drops
3.86
4.2
4.53
V
When voltage rises
3.86
4.2
4.53
V
When voltage drops
3.96
4.3
4.64
V
When voltage rises
-
-
4032 × tCYCP*1
μs
*1: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05629 Rev. *H
Page 120 of 133
CY9BD10T Series
12.8 Flash Memory Write/Erase Characteristics
Write / Erase time
12.8.1
(Vcc = 2.7 V to 5.5 V, TA = - 40°C to + 85°C)
Value
Parameter
Typ*1
Unit
Max*1
Large Sector
0.7
3.7
Small Sector
0.3
1.1
Half word (16-bit)
write time
12
Chip erase time
13.6
Sector erase time
Remarks
s
Includes write time prior to internal erase
384
μs
Not including system-level overhead time.
68
s
Includes write time prior to internal erase
*1: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
Write cycles and data hold time
12.8.2
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*1
10,000
10*1
100,000
5*1
Remarks
*1: At average + 85°C
Document Number: 002-05629 Rev. *H
Page 121 of 133
CY9BD10T Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return count time
(VCC = 2.7 V to 5.5 V, TA = - 40°C to + 85°C)
Parameter
Value
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Unit
Max*1
Typ
tCYCC
ns
40
80
μs
453
737
μs
Sub TIMER mode
453
737
μs
STOP mode
453
737
μs
Low-speed CR TIMER mode
Ticnt
Remarks
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*1)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*1: External interrupt is set to detecting fall edge.
Document Number: 002-05629 Rev. *H
Page 122 of 133
CY9BD10T Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*1)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*1: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual
about the return factor from Low-Power consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".
Document Number: 002-05629 Rev. *H
Page 123 of 133
CY9BD10T Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return count time
(VCC = 2.7 V to 5.5 V, TA = - 40°C to + 85°C)
Parameter
Value
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Unit
Max*1
Typ
321
461
μs
321
461
μs
441
701
μs
Sub TIMER mode
441
701
μs
STOP mode
441
701
μs
Low-speed CR TIMER mode
Trcnt
Remarks
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Document Number: 002-05629 Rev. *H
Start
Page 124 of 133
CY9BD10T Series
Operation example of return from low power consumption mode (by internal resource reset*1)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*1: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral
Manual"
−
The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.7. Power-on Reset Timing in 12.4. AC
Characteristics 12. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05629 Rev. *H
Page 125 of 133
CY9BD10T Series
13. Ordering Information
Part number
On-chip
Flash
memory
On-chip
SRAM
CY9BFD16TBGL-GK7E1
512 KB
64 KB
CY9BFD17TBGL-GK7E1
768 KB
96 KB
CY9BFD18TBGL-GK7E1
1 MB
128 KB
Document Number: 002-05629 Rev. *H
Package
Plastic · PFBGA 192-pin
(0.8 mm pitch), (LBE192)
Packing
Tray
Page 126 of 133
CY9BD10T Series
14. Package Dimensions
Package Type
Package Code
LQFP 176
LQP176
D
D1
132
4
5 7
89
133
89
88
132
133
88
E1
E
5
7
4
3
6
176
45
1
176
45
44
44
1
2 5 7
e
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.08
C A-B
D
8
TOP VIEW
2
A
A
A'
0.08 C
SIDE VIEW
SYM BOL
NOM . M AX.
0.05
0.15
L1
0.25
A1
10
L
c
b
SECTION A-A'
1.70
b
0.17
c
0.09
0.22
26.00 BSC
D1
24.00 BSC
e
0.50 BSC
E
26.00 BSC
E1
0.27
0.20
D
24.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
θ
SEA TIN G
PLAN E
DIM ENSIONS
M IN.
A
A1
9
θ
0°
8°
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 M M LQP176 REV**
Document Number: 002-05629 Rev. *H
002-15150 **
Page 127 of 133
CY9BD10T Series
Package Type
Package Code
LQFP 144
LQS144
4
D
D1
10 8
4
5 7
7 5
73
10 9
73
72
D
D1
108
10 9
72
E1
E
5
7
E
4
4
E1
5
7
3
3
6
14 4
37
1
14 4
37
36
1
36
BOTTOM VIEW
2 5 7
e
3
0.1 0 C A-B D
0.2 0 C A-B D
b
0.0 8
TOP VIEW
C A-B
D
8
2
A
9 c
A
A'
0.0 8 C
SEATING
PLAN E
L1
0.25
L
A1
10
b
SECTION A-A'
SIDE VIEW
SYMBOL
DIM ENSIONS
M IN. NOM. M AX.
1.70
A
A1
0.05
b
0.17
c
0.09
0.15
0.22
0.27
0.20
D
22.00 BSC
D1
20.00 BSC
e
0.50 BSC
E
22.00 BSC
20.00 BSC
E1
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 M M LQS144 REV*A
Document Number: 002-05629 Rev. *H
002-13015 *A
Page 128 of 133
CY9BD10T Series
Package Type
Package Code
FBGA 192
LBE192
002-13493 *A
Document Number: 002-05629 Rev. *H
Page 129 of 133
CY9BD10T Series
15. Major Changes
Spansion Publication Number: DS706-00031
Page
Revision 1.0
1
3
7
9 to 11
55
Section
DESCRIPTION
FEATURES
Multi-function Serial Interface
(Max 8channels)
PRODUCT LINEUP
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
PIN ASSIGNMENT
I/O CIRCUIT TYPE
HANDLING DEVICES
62 to 64
BLOCK DIAGRAM
65
77
80
83
85
113
ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
3. DC Characteristics
(1) Current Rating
4. AC Characteristics
(1) Main Clock Input Characteristics
(4-1) Operating Conditions of Main and USB/Ethernet
PLL (In the case of using main clock for input of PLL)
(4-2) Operating Conditions of Main PLL (In the case of
using high-speed internal CR)
Management Interface
5. 12-bit A/D Converter
Electrical characteristics for the A/D converter
116
119
123
124
6. USB Characteristics
7. Low-voltage Detection Characteristics
(2) Interrupt of Low-Voltage Detection
8. Flash Memory Write/Erase Characteristics
Erase/write cycles and data hold time
Document Number: 002-05629 Rev. *H
Change Results
Preliminary → Datasheet
Corrected the description.
Revised the following description.
"4 channels with 16-byte FIFO"
→"4 channels with 16steps×9-bit FIFO"
Added the following description.
"ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO"
Added the description of "Note".
Added the following description to "Type H".
IOH = -20.5mA, IOL = 18.5mA
Revised the description of "Power supply pins".
Revised the description of "C pin".
Added the description of "Base Timer".
Corrected the figure.
TIOA: input → input/output
TIOB: output → input
Corrected the value of "Analog reference voltage (AVRH)".
Min: AVSS → 2.7V
Added the "Smoothing capacitor (CS)".
Added the footnote.
Revised the value of "TBD".
Revised the unit.
Deleted "and estimated values."
Added "Internal operating clock frequency (FCM): Master clock".
Added "Main PLL clock frequency (FCLKPLL)".
Added "USB/Ethernet clock frequency (FCLKSPLL)".
Revised the value of "MDC ↑ → MDIO Hold time".
Min: 20 → 0
Deleted "(Preliminary value)".
Added the Symbol.
Revised the value of "TBD".
Revised the maximum value of "Power supply current (analog +
digital)":
A/D 1unit operation: Typ: 0.47 → 0.57
When A/D stops: Typ: 0.01 → 0.06
Revised the value of "Reference power supply current (between AVRH
to AVSS)"
When A/D stops: Typ: 0.01 → 0.06
Deleted the following Pin name.
- "Sampling time"
- "Compare clock cycle"
- "State transition time to operation permission"
- "Analog input capacity"
- "Analog input resistance"
Corrected the value of "Compare clock cycle (Tcck)".
Max: 10000 → 2000
Corrected the condition of "Output L level voltage".
External pull-down → External pull-up
Corrected the value of "LVD stabilization wait time (TLVDW)".
Max: 2240 × tcyc → 4032 × tCYCP
Deleted "(targeted value)".
Page 130 of 133
CY9BD10T Series
Page
Revision 1.1
Revision 2.0
Section
-
9, 10
Features
USB Interface
Ethernet-MAC
Features
USB Interface
Features
External Bus Interface
Pin Assignment
52 to 57
I/O Circuit Type
62
Handling Devices
62
Handling Devices
Crystal oscillator circuit
2
2
3
63
65
67
68
Handling Devices
C Pin
Block Diagram
Memory Map
Memory map(1)
Memory Map
Memory map(2)
75, 76
Electrical Characteristics
1. Absolute Maximum Ratings
77
Electrical Characteristics
2. Recommended Operation Conditions
79, 80
Electrical Characteristics
3. DC Characteristics
(1) Current rating
84
86
88 to 90
97 to 104
116
125 to 128
129
Electrical Characteristics
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) External Bus Timing
Electrical Characteristics
4. AC Characteristics
(9) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
9. Return Time from Low-Power Consumption Mode
Ordering Information
Change Results
Company name and layout design change
Added the description of PLL for USB and Ethernet
Added the size of each EndPoint
Added the description of Maximum area size
Added SWCLK and SWDIO and SWO
Added the description of I2C to the type of E, F, I, L
Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount
board."
Changed the description
Modified the block diagram
Modified the area of "External Device Area"
Added the summary of Flash memory sector and the note
Added the Clamp maximum current
Added the output current of P80, P81, P82, P83
Added about +B input
Modified the minimum value of Analog reference voltage
Added Smoothing capacitor
Added the note about less than the minimum power supply voltage
Changed the table format
Added Main TIMER mode current
Added Flash Memory Current
Moved A/D Converter Current
Added Frequency stability time at Built-in high-speed CR
Added Time until releasing Power-on reset
Changed the figure of timing
Modified Data output time
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
Added Conversion time at AVcc < 4.5 V
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage
Added Return Time from Low-Power Consumption Mode
Change to full part number
Note: Please see “Document History” about later revised information.
Document Number: 002-05629 Rev. *H
Page 131 of 133
CY9BD10T Series
Document History
Document Title: CY9BD10T Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05629
Submission
Revision
ECN
**
–
02/10/2015
*A
5208926
04/06/2016
Description of Change
Date
Migrated to Cypress and assigned document number 002-05639.
No change to document contents or format.
Updated to Cypress format.
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply rising
time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments (Page 83)
Added Notes for JTAG (Page 50), Changed “J-TAG” to” JTAG” in “4 List of Pin Functions”
(Page 32)
Updated Package code and dimensions as follows (Page 8-11, 73, 126-129)
FPT-144P-M08 -> LQS144, FPT-176P-M07 -> LQP176, BGA-192P-M06 -> LBE192
Change the name from “USB Function” to “USB Device” (Page 1, 7, 48)
Corrected the following statement
Analog port input current → Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 113)
*B
5560212
03/09/2017
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 94, 96, 98, 100)
Deleted MPNs below from “13. Ordering Information” (Page 126)
MB9BFD16SPMC-GE1, MB9BFD16TBGL-GE1, MB9BFD16TPMC-GE1, MB9BFD17SPMCGE1, MB9BFD17TBGL-GE1, MB9BFD17TPMC-GE1, MB9BFD18SPMC-GE1,
MB9BFD18TBGL-GE1, MB9BFD18TPMC-GE1
Added MPNs below to “13. Ordering Information” (Page 126)
MB9BFD16SPMC-GK7E1, MB9BFD16TBGL-GK7E1, MB9BFD16TPMC-GK7E1,
MB9BFD17SPMC-GK7E1, MB9BFD17TBGL-GK7E1, MB9BFD17TPMC-GK7E1,
MB9BFD18SPMC-GK7E1, MB9BFD18TBGL-GK7E1, MB9BFD18TPMC-GK7E1
Adapted new Cypress logo
*C
5797507
07/11/2017
*D
6013737
01/15/2018
*E
6054039
02/01/2018
Update Ethernet- MAC error from IEEE1558-2008 (PTP) to IEEE1588-2008 (PTP)
*F
6268602
08/01/2018
Obsoleted
*G
6351925
10/16/2018
Updated Arm trademark and the last page
Updated the figure of LBE192 in 14. Package Dimensions
Reactivate document.
No change.
Updated Ordering Information and removed the following Part numbers from the Table:
CY9BFD16SPMC-GK7MJE1, CY9BFD17SPMC-GK7MJE1, CY9BFD18SPMC-GK7MJE1
*H
6881610
05/13/2020
CY9BFD16TPMC-GK7MJE1, CY9BFD17TPMC-GK7MJE1, CY9BFD18TPMC-GK7MJE1
Updated Part Numbers across the document.
Document Number: 002-05629 Rev. *H
Page 132 of 133
CY9BD10T Series
Sales, Solutions, and Legal Information
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All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2012-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
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reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
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It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
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use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless
from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a
Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent
that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05629 Rev. *H
May 27, 2020
Page 133 of 133
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