MB9DF125PMC-GSK5E2

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9DF125 - Atlas-L CY9DF125 Series General Description CY9DF125 series is based on Cypress’s advanced ARM architecture (32-bit with instruction pipeline for RISC-like performance). Improvements compared to the previous generation include significantly improved performance at higher frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 128 MHz operation frequency from an external resonator. Note: ARM, Cortex, Thumb and CoreSight are the trademarks of ARM Limited in the EU and other countries. Features High-Performance/High Memory Content Low Power ARM Cortex R4, 8KB D-Cache, 8KB I-Cache ■ 32-Bit ARMv7 architecture ■ 205 DMIPS ■ 1MB Internal Flash ■ 48KB Internal EEFlash (Data Flash) ■ 128KB Internal RAM with ECC ■ Connectivity ■ ■ 2x CAN, 2 x LIN-USART, 3 x SPI, 1 x I2C, 2 x I2S Up to six Stepper Motor Control (SMC) outputs ■ HS-SPI (memory mapped access) Characteristics ■ ■ Safety Features/Security Features ■ Multiple Memory Production Units (MPU) ■ Peripheral Protection Units (PPU) ■ Timing Protection Unit (TPU) ■ Cyclic Redundancy Checks (CRC of Flash, Cache and RAM) ■ Watchdog ■ Flash-, Debug- and Test-Security ■ Secure Hardware Extension (SHE) ❐ Self-contained secure area ❐ Random Number generator ❐ Secure repository for cryptographic keys ❐ AES encryption/decryption block Applications ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Switchable Power Domains 16KB Retention RAM Flexible Clock Control Debugging/Testing ARM Coresight Debug and Trace Debugging via JTAG Interface Boundary Scan 5V capable IOs Ta: 40 °C to +105 °C Package: LQFP-176 Classical Automotive Instruments Cluster with pointers Vehicle Controller for Virtual Cluster and Head Units in cards Other Features Up/Down Counters ■ Programmable Pulse Generators ■ Analog-to-Digital Converters - 50 channels ■ Sound Generator ■ Free Running/Reload Timers ■ Real Time Clock (RTC) ■ Input Capture Units, Output Compare units ■ 32 external Interrupts ■ Errata: For information on silicon errata, see Errata on page 390. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation Document Number: 002-05677 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 28, 2019 CY9DF125 - Atlas-L Block Diagram Controlgroup EIC EIC0_INT00.... EIC0_INT31 NMI EIC0_NMI EBI0_MDATA00i......EBI0_MDATA15i EBI0_RDY Memories RTC RTC_WOT SYSC SYSC_CKOT SYSC_CKOTX TPU IRQ Control Power Control RetRAM 16K EEFlash 48K option CLK_MEM_E_PD3 Watchdog EBI_MDATA00o...EBI_MDATA15o EBI_MAD00...EBI_MAD23 EBI_MDQM0, EBI_MDQM1 EBI_MWEX EBI_MOEX EBI_MCLK EBI_MCASX EBI_MRASX EBI_MDWEX EBI_MCKE EBI_MNALE EBI_MNCLE EBI_MNWEX EBI_MNREX EBI_MCSX0...EBI_MCSX3 EBI_MCSX8 CLK_CFG_PD4 BootROM 12K HS−SPI (1 ch) TCMRAM 64K EBI CLK_MEM_E_PD3 ECC TCFlash 1M CLK_HPM_PD2 SRAM 48K Memory Map CLK_DBG_PD2 CLK_TRACE_PD2 Trace I−Cache 8K 128 MHz D−Cache 8K MPU 12 ch Oscillators PLL’s SHE CSV/CLK−out CLK_SYS_PD3 High Performance Matrix (HPM) GPIO0_00o˘GPIO0_52o GPIO0_62o,GPIO0_63o GPIO1_00o˘GPIO1_59o GPIO2_00o˘GPIO2_25o PPU CRC I2S (2 ch) Peripheral Bus Bridge 0 Peripheral Bus Bridge 1 SPIn_CLKi SPIn_DATA0i˘. SPIn_DATA3i SPIn_SSi SPIn_CLKo SPIn_DATA[0]o˘. SPIn_DATA[3]o SPIn_SSo SPIn_SSO[1]˘. SPIn_SSO[3] CLK_HPM_PD2 PERI5_AHB BUS DMA (8 ch) SG_SGA SG_SGO SG (1 ch) 10−bit ADC I2Sn_ECLK I2Sn_SCKi I2Sn_SDi I2Sn_WSi CANn_RX CANn_TX CAN (2 ch) I2Sn_SDo I2Sn_WSo I2Sn_SCKo USART6_SCKi USART6_SIN USART6_SCKo USART6_SOT I/O Timer (4 ch) FRT 0/1/2/3 ICU 2/3 OCU 0/1 FRTn_FRCK ICUn_IN0, ICUn_IN1 OTDn,OTDn_I,OTDn_G,OTDn_GI PPG_ETRG0˘.. PPG_ETRG3 PPGA PPGB (50 ch) USART (1 ch) I/O Timer (4 ch) FRT 16/17/18/19 ICU 18/19 OCU 16/17 PERI0_RBUS GPIO0_00i˘... GPIO0_52i GPIO0_62i,GPIO0_63i GPIO1_00i˘...GPIO1_59i GPIO2_00i˘... GPIO2_25i SPI (3 ch) DMA0_DEOP_ACK0, DMA0_DEOP_ACK1 DMA0_DREQ0, DMA0_DREQ1 DMA0_DSTP0, DMA0_DSTP1 DMA0_DREQ_ACK0, DMA0_DREQ_ACK1 DMA0_DSTP_ACK0, DMA0_DSTP_ACK1 DMA0_DEOP0, DMA0_DEOP1 PERI1_RBUS GPIO (141 pins) UDC0_AIN0, UDC0_AIN1 UDC0_BIN0, UDC0_BIN1 UDC0_ZIN0, UDC0_ZIN1 UDC0_UDOT0 UDC0_UDOT1 PERI4_SLAVE AHB BUS UDC (1 ch) RLTn_TIN RLTn_TOUT CLK_PERI4_PD2 RLT (10 ch) Peripheral Bus Bridge 4 16−bit PPG (8 ch) CLK_PERI0_PD2 Peripheral Bus Bridge 3 CLK_HPM_PD2 CLK_DMA_PD2 CLK_HPM_PD2 CLK_PERI1_PD2 CLK_HPM_PD2 PERI3_eRBUS Clock group Cortex R4 On−chip Debug CLK_CFG_PD1 CLK_PERI3_PD2 X0 X1 MODE X0A X1A RSTX DBG0_CTL DBG0_CLK DBG0_TRACE0.... DBG0_TRACE7 USART (1 ch) AVDD5 AVSS5 AVRH ADC0_AN0..... ADC0_AN31 ADC0_EDGI FRTn_FRCK ICUn_IN0, ICUn_IN1 OTDn,OTDn_I,OTDn_G,OTDn_GI USART0_SCKi USART0_SIN USART0_SCKo USART0_SOT I2C (1 ch) I2C0_SCLi I2C0_SDAi I2C0_SCLo I2C0_SDAo SMC (6 ch) SMCn_M1 SMCn_P1 SMCn_M2 SMCn_P2 16−bit PPG (16 ch) PPG_ETRG0˘.. PPG_ETRG3 PPGn_PPGA PPGn_PPGB Power Domain Power Domain Modules PD1 Clockgroup (Osc, PLL, CSV), Controlgroup (EIC, NMI, RTC, SYSC, WDG, TPU, IRQ Control, Power Control) PD2 Peripheral bus 0 (ADC, FRT, ICU, OCU, USART, I2C, SMC, PPG), Peripheral bus 1 (SG, CAN, USART, FRT, ICU, OCU, PPG), Peripheral bus 3 (RLT, UDC, GPIO, PPU), Peripheral bus 4 (SPI, I2S), On-Chip Debug, Trace, SRAM, CRC PD3 Cortex R4, SHE, MPU, I-Cache, D-Cache, TCM, TCFlash, EEFlash, TPU, BootROM, HS-SPI, EBI PD4 RetRAM Document Number: 002-05677 Rev. *C Page 2 of 423 CY9DF125 - Atlas-L Contents CY9DF125 Features.......................................................... 4 Resource Distribution for Non-modulated Clock ....... 16 Lock/Unlock Values for Protection Units ................... 16 ID-Values for Module Identification Registers ........... 17 Package and Pin Assignment ....................................... 18 Package .................................................................... 18 I/O Pins and Functions .............................................. 22 I/O Pin Types............................................................. 64 IO Circuit Types......................................................... 70 Package Diagram............................................................ 75 Interrupt/DMA.................................................................. 76 NMI............................................................................ 86 DMA Overview .......................................................... 87 PPU ........................................................................... 92 Master ID................................................................... 93 I/O Map............................................................................. 94 Electrical Characteristics............................................. 335 Absolute Maximum Ratings..................................... 335 Recommended Operating Conditions ..................... 338 DC Characteristics .................................................. 339 AC Characteristics................................................... 346 Analog Digital Converter ......................................... 366 FLASH Memory Program/Erase Characteristics for TCFLASH and EEFLASH................................... 368 RC Oscillator Frequency ......................................... 369 ESD Structure between Power Domains ................ 370 Procedures.................................................................... 373 Boundary Scan........................................................ 373 Document Number: 002-05677 Rev. *C Flash Parallel Programming .................................... Debug and Trace..................................................... Handling Devices.......................................................... Preventing Latch-up ................................................ Handling of Unused Input Pins................................ Power Supply Pins .................................................. Power on Sequence ................................................ Pin State During Active External Reset................... Crystal Oscillator Circuit .......................................... Notes on Using External Clock................................ Unused Sub Clock Signal........................................ Errata ............................................................................. Ordering Information.................................................... Appendix ....................................................................... Workaround for IRQ Unit Register Read Timing Issue ................ Workaround for Flash Erase Suspend Internal ............................ Workaround for IUNIT Interrupt Handling Problem ...................... Document History Page ............................................... Sales, Solutions, and Legal Information .................... Worldwide Sales and Design Support..................... Products .................................................................. PSoC® Solutions .................................................... Cypress Developer Community............................... Technical Support ................................................... 375 385 387 387 387 387 387 388 388 389 389 390 409 410 410 417 418 420 423 423 423 423 423 423 Page 3 of 423 CY9DF125 - Atlas-L CY9DF125 Features Table 1. Overview Feature ATLAS-L / QFP-176 Max. Core frequency 128 MHz DMA 8 channels TCFlash 1 MB EEFlash 48 KB AXI RAM (with ECC) 48 KB TCM RAM (with ECC) 64 KB RetRAM 16 KB Core has 4-way-associative cache I/D each 8KB SHE yes Boot-ROM 16 KB IRQ Ctrl 256 RTC (with auto calibration) 1 channel Source clock timer 4 RLT (Reload Timer) (32 bit) 10 channels FRT 8 channels ICU 8 channels OCU 8 channels PPG 24 channels SG (Sound Generator) 1 channel UDC (UpDown Counter) 2 channels CAN 2 channels USART (LIN-USART) 2 channels SPI 3 channels I2C 1 channel I2S 2 channels Quad - SPI 1 channel External bus 24-bit address/16-bit data EIC (External Interrupts) 32 channels NMI (intern / extern) 32/1 SMC 6 channels ADC (10-bit) 50 channels (including 24 channels shared with SMC) Debug Trace Standard 5-pin JTAG interface 4-bit and 8-bit trace data shared with resources. CRC 1 channel Package QFP-176 Document Number: 002-05677 Rev. *C Page 4 of 423 CY9DF125 - Atlas-L Table 2. Features Feature Technology Processor Subsystem Debug and Trace Clocks Clock Supervisor Resets Description ■ 90nm CMOS with embedded flash ■ Cortex R4 CPU core ■ 32-bit ARM architecture, dual-issue superscalar eight stage pipeline ■ ARMv7 and Thumb-2 instruction set compliant ■ Memory Protection Unit (MPU) with 12 regions ■ Two Tightly Coupled Memory (TCM) ports. 64-bit AXI slave port for access to TCMs ■ 64-bit AXI master port ■ Vectored Interrupt Controller (VIC) port for faster interrupt processing ■ Single error correction, double error detection (SECDED) Error Correction Coding (ECC) for memory error detection and correction ■ Instruction cache: 8KB 4-way set-associative ■ Data cache: 8KB 4-way set-associative ■ Up to 8 break-points and 8 watchpoints ■ ARM Coresight technology ■ Standard 5-pin JTAG interface ■ 4-bit, 8-bit and 16-bit trace data width supported depending on package ■ Secure entry supported for debugger ■ External main clock of 4MHz (up to 8MHz under evaluation) ■ External sub clock (typical 32.768 kHz) ■ Embedded RC oscillator (typical 8/12 MHz, configurable) ■ Embedded Slow RC oscillator (typical 100 kHz) ■ On-chip Phase Locked Loop (PLL) clock multiplier for main clock, Spread Spectrum Clock Generation (SSCG) ■ Stabilization timers for all source clocks ■ Clock supervision for all source clocks and PLL outputs ■ Reset generation for out-of-bound clock frequencies on input source clocks, or PLL output clocks ■ External Reset ■ Software triggered hard reset ■ Clock supervision resets ■ Watchdog ■ Low Voltage Detection reset ■ Software reset Document Number: 002-05677 Rev. *C Page 5 of 423 CY9DF125 - Atlas-L Table 2. Features (Continued) Feature Watchdog Timer DMA Interrupts External Interrupts Timing Protection Description ■ 32-bit counter ■ Supports selection of four clock sources (Main clock, Sub clock, RC clock or Slow RC clock) ■ Support for window watchdog functionality ■ Reset or NMI generation support on watchdog errors ■ Support for preemptive warning interrupt before watchdog reset or NMI generation ■ Additional safety provision through three times redundancy and error correction logic for important configuration bits ■ Option to halt watchdog counter in case of core reaching break-point ■ 64-bit AHB Master Interface ■ 32-bit AHB Slave Interface ■ Block, burst and demand transfer modes ■ Fixed and incremental addressing for source as well as destination ■ 132 clients ■ 8 channels to handle independent data flows ■ Fixed priority, dynamic priority, and round robin arbitration ■ Interrupt Request (IRQ) and Fast Interrupt Request (FIQ) capability ■ NMI sources can generate FIQ ■ Supports 32 Non Maskable Interrupt (NMI) source for FIQ generation ■ Supports 512 Normal Interrupt sources for IRQ generation ■ Supports request for low power mode entry ■ Programmable 32-level priority controller for normal IRQ sources. Also, supports programmable priority level masking ■ Programmable 16-level priority controller for NMI interrupt sources ■ Software interrupt generation ■ Privileged mode support for restricted access ■ Up to 32 pins can be used as external interrupts ■ Optional 25ns (typical) noise filters on all lines ■ DMA support ■ NMI support ■ Five polarity support (‘H’, ‘L’, rising edge, falling edge, and, any edge) ■ Event capture support for all 32 external interrupt pins ■ Software enabled monitoring of external events, with sampling frequency of 500Hz to 16MHz ■ Up to eight identical 24-bit timers for execution time protection, locking time protection, inter-arrival time protection or deadline protection ■ Normal and overflow mode support ■ Global linear prescaler (1 to 64) to scale down clock frequency ■ Additional, individual timer prescaler to support 4 different software programmable frequencies (1,1/2, 1/4, and 1/16) ■ Start, stop, and continue options per timer controllable by software Document Number: 002-05677 Rev. *C Page 6 of 423 CY9DF125 - Atlas-L Table 2. Features (Continued) Feature Memory Protection Peripheral Protection CAN USART/LIN I2C Stepper Motor Control Description ■ Memory protection unit for all bus masters ■ AXI interface support ■ 8 programmable memory regions, and one background region which covers entire 4GB address space ■ Unauthorized access generates NMI ■ Protection to all peripherals and General Purpose IOs (GPIO) ■ Individual protection setting for up to 512 peripherals, and 512 GPIO channels ■ DMA access support for faster register configuration ■ Supports CAN protocol version 2.0 part A and B ■ Bit rates up to 1 Mbps ■ 64 message objects ■ Each message object has its own identifier mask ■ Programmable FIFO mode (concatenation of message objects) ■ Maskable interrupt ■ Disabled automatic retransmission mode for time triggered CAN applications ■ Programmable loop-back mode for self-test operation ■ Programmable LIN or USART function ■ Full-duplex support ■ Clock synchronous (start-stop synchronization and start-stop-bit option),and Clock asynchronous (using start-, stop-bits) transfer modes ■ Dedicated baud rate generator. Mechanism for automatic baud rate adjust available in LIN mode ■ Support for data length of 7-bits (not in synchronous or LIN mode) and 8-bits ■ Support for signal modes Non-Return to Zero (NRZ) and Non-Return to Zero Inverted (NRZI) ■ Reception error detection for framing, overrun, parity, checksum, sync field timeout, and frame-ID (only in LIN mode) errors ■ Interrupt capability for transmission, reception, and errors ■ DMA support ■ Master/slave transmitting and receiving functions ■ 7-bit addressing as master and slave ■ 10-bit addressing as master and slave ■ Acknowledge disable option upon slave address reception (master-only operation) ■ Address mirroring to give interface several slave addresses ■ Up to 400 kbit transfer rate ■ Optional noise filters for SDA and SCL ■ Interrupt capability on transmission and bus error events ■ PWM duty cycle programmable from 0% to 100% ■ Programmable setting to select ‘L’, ‘H’, ‘PWM’ and ‘HighZ’ output ■ High current output pins Document Number: 002-05677 Rev. *C Page 7 of 423 CY9DF125 - Atlas-L Table 2. Features (Continued) Feature A/D Converter I2S Sound Generator Up Down Counter Description ■ 50 channels ■ Conversion time: 1us per channel ■ RC type Successive Approximation (SAR) with sample and hold circuit ■ 10-bit or 8-bit resolution ■ Program selection analog input from 32 channels ■ Single conversion, continuous conversion, and scan conversion options ■ Interrupt capability ■ DMA support ■ 4 range comparator channels for comparing conversion output with thresholds ■ Programmable master/slave operations ■ Supports transmission only, reception only and simultaneous transmission/reception operations ■ Support for 1 sub frame and 2 sub frame constructions ■ Up to 32 channels supported in each sub frame ■ Support for individual configuration of channel number, channel length, word length in each sub frame ■ Word length support from 7-bits to 32-bits ■ Programmable frequency, polarity, and phase of frame synchronous signal ■ Programmable sampling point of received data (center or at the end of received data) ■ Support for frequency division from 1 to 126 in multiples of 2 ■ DMA support ■ Interrupt capability ■ Produces sound/melody with varying frequency and amplitude ■ Square wave sound output with frequency of 100Hz – 6kHz (resolution 20Hz) ■ Programmable Pulse Width Modulated (PWM) cycle width of 255 or 511 clocks. PWM duty cycle programmable from 0% to 100% ■ Two 2-bit prescaler with programmable clock division of 1, 1/2, 1/3, and 1/4 ■ Automatic linear or exponential amplitude increment or decrement ■ Start, stop, resume functionality ■ DMA support ■ Automatic sound output stop when amplitude becomes 0 ■ 16-bit ■ Three count modes (timer mode, up/down count mode, and phase difference count mode) supported ■ Multiply by 2 or multiply by 4 in phase difference count mode ■ Count source can be internal clock or external trigger ■ Counting range: any value between 0 and 232-1 can be set ■ 4 interrupt options (Compare-match interrupt, Underflow interrupt, Overflow interrupt, and Count direction change interrupt) Document Number: 002-05677 Rev. *C Page 8 of 423 CY9DF125 - Atlas-L Table 2. Features (Continued) Feature Reload Timers Free Running Timers Input Capture Units Output Compare Units Programmable Pulse Generator Description ■ 32-bit reload counter ■ External and Internal clock/event source ■ Trigger signal programmable as rising/falling edge or both ■ Gated count function ■ One-shot or reload counter mode ■ Counter state can be made visible at external pin ■ Prescaler with six different settings for the internal clock and two settings for the external clock ■ Several Reload Timers can be cascaded to form a longer Reload Timer ■ DMA support ■ Signals an interrupt on overflow, match with Compare registers, zero-detection, or match with Compare Clear Register ■ Option to mask zero detection, compare clear match interrupt, or both to allow for interrupt generation only after multiple events ■ Programmable timer period up to 1 sec ■ Support for 11 counter clocks. Prescaler with 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of peripheral clock frequency ■ DMA support ■ Consists of 2 independent input channels ■ 16-bit wide capture registers per channel ■ Signals an interrupt upon external event ■ Rising edge, falling edge or rising & falling edge sensitive ■ DMA support ■ Consists of 2 independent channels ■ 16-bit wide ■ Signals an interrupt when a match with 16-bit I/O Timer occurs ■ A pair of compare registers can be used to generate an output signal ■ Interrupt capability ■ 16-bit down counter, cycle and duty setting registers ■ Interrupt at trigger, counter borrow and/or duty match ■ PWM operation and one-shot operation ■ Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer underflow as clock input ■ Can be triggered by software or reload timer Document Number: 002-05677 Rev. *C Page 9 of 423 CY9DF125 - Atlas-L Table 2. Features (Continued) Feature Real Time Clock Internal Memories- TCMRAM Internal Memories- System RAM Internal Memories- Retention RAM Tightly Coupled Flash Memory EEPROM Emulation Flash Memory Description ■ Can be clocked from main clock, sub clock or RC clock ■ Automatic calibration support even when device is in low power state ■ Interrupt capability on half-second, 1 second, 1 minute, 1 hour, and 1 day duration ■ Additional capability for interrupt generation on calibration failure detection and calibration done event ■ Auto calibration of Sub clock or RC clock with respect to Main clock ■ Separate clock selector for calibration ■ Configurable calibration duration ■ Auto/manual trigger for calibration ■ 64 KB ■ 64-bit interface ■ Single error correction, double error detection (SECDED) ECC support ■ 64-bit AXI interface ■ 48 KB ■ Single error correction, double error detection (SECDED) ECC support ■ Parallel read/write capability for 2 different banks ■ 16 KB ■ 4 banks ■ 32-bit AHB ■ Low leakage RAMs for low power consumption ■ 1 MB ■ Parallel Programming support ■ Mapped to TCM address space as well as Cacheable address space through AXI interface ■ Single error correction, double error detection (SECDED) ECC support ■ TCM address space supports only read access ■ Cacheable AXI address space supports write and read access ■ Detection of hang-up 1 state ■ 16 large sectors of 64KB each ■ 8 small sectors of 8KB each ■ Sector-wise access protection for write and read accesses ■ 48 KB ■ Single error correction, double error detection (SECDED) ECC support ■ Support for sector erase ■ EEPROM emulation mode support ■ Support for mirroring of memory in 3 diverse memory-mapped regions ■ 6 sectors of 8KB each ■ Sector-wise access protection for write and read accesses Document Number: 002-05677 Rev. *C Page 10 of 423 CY9DF125 - Atlas-L Table 2. Features (Continued) Feature Quad SPI Error Collection Low Voltage Detect I/O Ports EBI Description ■ Supports legacy as well as the dual-bit and quad-bit modes of SPI operation ■ Supports up to four slave devices in master mode ■ Programmable transfer rate, active-level of slave-select signal, polarity, and phase of the serial clock per slave select ■ Support for memory mapped operation of external serial flash and serial SRAM devices in command sequencer mode ■ Additional direct mode support for standard SPI operation through FIFO interface ■ Error collection on all peripherals ■ Optional Non-Maskable Interrupt (NMI) generation capability ■ Low voltage detection for 5V, 3.3V, and 1.2V ■ Programmable thresholds ■ Reset generation capability on low voltage events ■ All functional pins can be used as GPIO ■ Programmable analog or digital functionality selection ■ Programmable input levels (Automotive, CMOS, and TTL) ■ Programmable pull-up/pull-down and output drive ■ Endianess configuration support for all SRAM interfaces based on chip select ■ PPU Protection for EBI Configuration register range ■ Only 32-bit write access support supported by EBI Configuration registers ■ Lock/Unlock register for write protection for EBI Configuration registers ■ SHE CRC Implements all commands defined by the functional specification of SHE (chapter 7) ■ Provides AES-128 encryption and decryption operations ■ Electronic cipher book (ECB) and cipher block chaining (CBC) modes ■ Supports generation of the cipher-based message authentication code (CMAC) ■ Implements Miyaguchi-Preneel compression function. ■ Provides random number generation function ■ Supports secure booting ■ Measurement during / before application start-up ■ Secure boot mode, start address and length of the bootloader are configurable by the user ■ Secure key storage implemented in EEFLASH ■ Programmable 8, 16, 24 or 32 bit input data width ■ Programmable polynomial value (Polynomial degree from 2 to 32) ■ Programmable initial seed value ■ Programmable final checksum XOR value ■ Interrupt and DMA trigger capability ■ Configurable input/output bit reflection and byte swapping ■ Supports PPU ■ Supports block/multiple data transfers (more than 32-bit) Document Number: 002-05677 Rev. *C Page 11 of 423 CY9DF125 - Atlas-L Table 2. Features (Continued) Feature Packages Description ■ QFP-176 Table 3. Memory Map Start Address Table 3. Memory Map (Continued) Module Start Address Module FFFF2000 Reserved 01100000 Reserved FFFF0000 BOOTROM 01000000 AXI_FLASH_MEMORY_LARGE_SECTORS FFFEF000 EXCFG 00FF0000 TCM_FLASH_SMALL_SECTORS B0D01000 Reserved 00900000 Reserved B0D00000 SYSTEM_RAM_CONFIG 00800000 TCM_FLASH_LARGE_SECTORS B0C00000 PERI5_AHB 00010000 Reserved B0B00000 PERI4_SLAVE 00000000 TCM_RAM B0A00000 PERI3_ERBUS B0900000 Reserved B0800000 PERI1_RBUS B0700000 PERI0_RBUS B0600000 MCU_CONFIG B0500000 DEBUG_BUS B0400000 MEMORY_CONFIG B0200000 Reserved B0180000 EBI B0080000 Reserved B0000000 HSSPI0 90000000 Reserved 80000000 HSSPI0_MEMORY 28000000 Reserved 20000000 EBI_MEMORY1 10000000 EBI_MEMORY0 06000000 Reserved 05FF0000 AXI_SLAVE_CORE0_TCM_FLASH_SMALL_ SECTORS 05900000 Reserved 05800000 AXI_SLAVE_CORE0_TCM_FLASH_LARGE_ SECTORS 05010000 Reserved 05000000 AXI_SLAVE_CORE0_TCM_RAM 04800000 AXI_SLAVE_CORE0_DCACHE 04000000 AXI_SLAVE_CORE0_ICACHE 01A0C000 Reserved 01A00000 SYSTEM_RAM 01800000 Reserved 017F0000 AXI_FLASH_MEMORY_SMALL_SECTORS Document Number: 002-05677 Rev. *C Page 12 of 423 CY9DF125 - Atlas-L Table 4. PERI0_RBUS Memory Map (Continued) Table 4. PERI0_RBUS Memory Map Start Address Module B07FFC00 B07FA800 B07F8000 B07F0400 B07F0000 B07EC000 B07E8000 B075A000 B074C000 B074BC00 B0748C00 B0748800 B0748400 B0748000 B0747C00 B073BC00 B073B800 B073B400 B073B000 B073AC00 B073A800 B073A400 B073A000 B0739C00 B0739800 B0739400 B0739000 B0738C00 B0738800 B0738400 B0738000 B0732000 B0731800 B0731400 B0731000 B0730C00 B0730800 B0730400 B0730000 B0729800 B0728000 B0720C00 B0720000 B071C000 B0718400 BSU0 Reserved RICFG0 Reserved BECU0 Reserved PPC Reserved PPGGLC0 Reserved PPGGRP3 PPGGRP2 PPGGRP1 PPGGRP0 Reserved PPG15 PPG14 PPG13 PPG12 PPG11 PPG10 PPG9 PPG8 PPG7 PPG6 PPG5 PPG4 PPG3 PPG2 PPG1 PPG0 Reserved SMCTG0 SMC5 SMC4 SMC3 SMC2 SMC1 SMC0 Reserved USART0 Reserved I2C0 Reserved OCU1 Document Number: 002-05677 Rev. *C Start Address Module B0718000 B0714000 B0710C00 B0710800 B0710400 B0708C00 B0708800 B0708400 B0708000 B0700400 B0700000 OCU0 Reserved ICU3 ICU2 Reserved FRT3 FRT2 FRT1 FRT0 Reserved ADC0 Table 5. PERI1_RBUS Memory Map Start Address Module B08FFC00 B08FB000 B08F8000 B08F0000 B0868000 B085C000 B085BC00 B0858400 B0858000 B0857C00 B0849C00 B0849800 B0849400 B0849000 B0848C00 B0848800 B0848400 B0848000 B0842000 B0838000 B0830C00 B0828400 B0828000 B0824000 B0820C00 B0820800 B0820400 B0818C00 B0818800 B0818400 B0818000 BSU1 Reserved RICFG1 BECU1 Reserved PPGGLC1 Reserved PPGGRP17 PPGGRP16 Reserved PPG71 PPG70 PPG69 PPG68 PPG67 PPG66 PPG65 PPG64 Reserved USART6 Reserved OCU17 OCU16 Reserved ICU19 ICU18 Reserved FRT19 FRT18 FRT17 FRT16 Page 13 of 423 CY9DF125 - Atlas-L Table 5. PERI1_RBUS Memory Map (Continued) Start Address Module B0810400 B0808800 B0808400 B0808000 B0800400 B0800000 Reserved Reserved CAN1 CAN0 Reserved SG0 Table 6. PERI3_eRBUS Memory Map Table 7. PERI4_SLAVE AHB Bus Memory Map Start Address Module B0BFFC00 BSU4 B0BFA400 Reserved B0BF8000 RICFG4 B0B40400 Reserved B0B40000 Reserved B0B3B000 Reserved B0B38800 SPI2 Start Address Module B0B38400 SPI1 B0AFFC00 BSU3 B0B38000 SPI0 B0AF9400 Reserved B0B30800 Reserved B0AF8000 RICFG3 B0B30000 CRC0 B0AF0000 BECU3 B0B29000 Reserved B0A28000 Reserved B0B20400 I2S1 B0A20000 UDC0 B0B20000 I2S0 B0A18000 Reserved B0B00000 Reserved B0A12400 RLT9 B0A12000 RLT8 B0A11C00 RLT7 B0A11800 RLT6 B0A11400 RLT5 B0A11000 RLT4 B0A10C00 RLT3 B0A10800 RLT2 B0A10400 RLT1 B0A10000 RLT0 B0A09000 Reserved Table 8. PERI5_AHB Bus Memory Map Start Address Module B0CFFC00 BSU5 B0CFF800 Reserved B0C08000 MPUXDMA0 B0C04000 Reserved B0C00000 DMA0 Table 9. Memory and Config (MEMORY_CONFIG) AHB Bus Memory Map B0A08000 GPIO B0A00400 Reserved Start Address Module PPU0 B04C0000 EEFLASH_NOECC_MIR B0480000 EEFLASH_TABLE_MIR B0440000 EEFLASH_ECC_MIR B0420400 Reserved B0414400 Reserved B0418000 BSU6 B0414400 Reserved B0414000 MPUSHE B0A00000 Document Number: 002-05677 Rev. *C Page 14 of 423 CY9DF125 - Atlas-L Table 9. Memory and Config (MEMORY_CONFIG) AHB Bus Memory Map (Continued) Table 11. HSSPI0 Memory Map Start Address Module Start Address Module B0413400 Reserved B007FC00 BSU8 B0413000 SHECFG B0078400 Reserved B0078000 RICFG8 B0000000 HSSPI0 B0412400 Reserved B0412000 EEFCFG B0411400 Reserved B0411000 TCFCFG Start Address Module B0410400 Reserved B01FFC00 BSU10 B0410000 TRCFG B0180080 Reserved B040B400 Reserved B0180000 EBI B0408000 TPU0 B0401000 Reserved B0400000 IRQ0 Table 12. EBI CFG AHB Bus Memory Map Table 10. MCU_CONFIG AHB Bus Memory Map Start Address Module B06FFC00 BSU7 B06F9400 Reserved B06F8000 RICFG7 B0648000 Reserved B063B000 RETRAMBANK3 B063A000 RETRAMBANK2 B0639000 RETRAMBANK1 B0638000 RETRAMBANK0 B0630000 Reserved B0628000 EICU0 B0620400 Reserved B0620000 EIC0 B0618400 Reserved B0618000 RTC B0610400 Reserved B0610000 RRCFG B0608400 Reserved B0608000 WDG B0601000 Reserved B0600000 SYSC Document Number: 002-05677 Rev. *C Page 15 of 423 CY9DF125 - Atlas-L Resource Distribution for Non-modulated Clock Lock/Unlock Values for Protection Units Some of the resources are available with modulated and non-modulated clock. Find below the distribution: For various protection and system relevant units, registers must be unlocked before configuring and can be locked for protection. For the details about functionality, see the FCR4 Hardware Manual. Table 13. Resource Distribution for Non-modulated Clock Module Non-modulated Modulation Possible CAN 2 - SG 1 - Module Unlock value Lock value ICU/OCU/FRT 4 4 TPU0 ACC5A110 B10CACC5 Table 14. Lock/unlock Values for FCR4 Protection Module Instances PPG 8 16 PPU0 ACC5BB01 BB0B10C1 USART/LIN 1 1 MPUXDMA0 ACCABB56 112ABB56 I2C 1 - TRCFG ACC55ECC 5ECCB10C SMC - 6 EXCFG ACC5B007 B007ECF6 Document Number: 002-05677 Rev. *C IRQ0 17ACC911 17B10C11 RRCFG ACC5DECC DECCB10C SCCFG 5ECACCE5 A135331A SRCFG 5ECC551F 551FB10C TCFCFG CF61F1A5 EEFCFG CF6DF1A5 WDG EDACCE55 SYSC 5CACCE55 EBI EB1410CE 10CE0EB1 MPUXSHE EA1221AE 15EDDE51 Page 16 of 423 CY9DF125 - Atlas-L ID-Values for Module Identification Registers For several peripheral and system related modules, the hardware contains Module Identification Registers that hold read-only values which contain information about the module number, the version and possible patches. Table 15. List of Module ID Module ID-Register ID Value System Controller SYSC_SYSIDR 0x00031101 Security Checker SCCFG_MODID 0x00020400 SRAM Interface SRCFG_MID 0x00040300 TC-Flash Interface TCFCFG_FMIDR 0x000E0300 EE-Flash Interface EEFCFG_MIR 0x00090700 Interrupt Controller 0 IRQ0_MID 0x000B0100 DMA Controller 0 DMA0_ID 0x00010300 Timing Protection Unit 0 TPU0_MID 0x00050200 Memory Protection Unit for AXI MPUXDMA0_MID 0x000D0200 Memory Protection Unit for AXI MPUXSHE_MID 0x000D0200 Bus Error Collection Unit 0 BECU0_MIDH / BECU0_MIDL 0x0008 / 0x0200 Bus Error Collection Unit 1 BECU1_MIDH / BECU1_MIDL 0x0008 / 0x0200 Bus Error Collection Unit 3 BECU3_MIDH / BECU3_MIDL 0x0008 / 0x0200 High Speed SPI Interface 0 HSSPI0_MID 0x00060300 SPI Interface 0 SPI0_MID 0x00070300 SPI Interface 1 SPI1_MID 0x00070300 SPI Interface 2 SPI2_MID 0x00070300 Inter IC Sound 0 I2S0_MIDREG 0x000A0300 Inter IC Sound 1 I2S1_MIDREG 0x000A0300 SHE SHE_MID 0x000F0200 Document Number: 002-05677 Rev. *C Page 17 of 423 CY9DF125 - Atlas-L Package and Pin Assignment Package A QFP-176 package will be used for ATLAS-L. The package code is LQP176. 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VDP5 RSTX MODE X1A X0A VSS X0 X1 VSS VDP5 P0_28 P0_27 VSS VDP3 P0_26 P0_15 P0_14 P0_13 P0_12 P0_11 P0_10 P0_09 P0_08 VDP3 VSS P1_29 P1_28 P1_27 P1_26 P3_32 P3_31 P3_30 P3_29 P3_28 P3_27 P3_26 P3_25 VSS VDP3 P3_24 P3_23 P3_22 VSS VDD Figure 1. QFP-176 Pin Assignment VDP5 / 3V-5V-IO VDP3 / 3V-IO VDP3 / 3V-I 3V-IO 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 69 170 171 172 173 174 175 176 VDP5 / 3V 3V-5V-IO VSS VDD VSS P0 40 P0 41 P0 42 P0 43 P0 44 P0 45 P0 46 P0 47 P0 48 P0 49 P0 50 P0 51 P0 62 P0 63 P2 32 P2 33 VDP5 VSS P2 34 P2 35 P2 36 P2 37 P2 38 P2 39 P2 40 P2 41 P2 42 P2 43 P2 44 P2 45 P2 46 P2 47 VSS VDP5 5 JTAG TDO JTAG TDI JTAG TCK VSS VDD JTAG TMS JTAG NTRST ` DVCC / 3V-5V-IO ` ` P3 21 P3 20 P3 19 P3 18 P3 17 P3 16 P3 15 P3 14 P3 13 VSS VDP3 P3 42 P3 41 P3 40 P3 39 P3 38 P3 37 P3 36 P3 35 P3 34 P3 33 P1 25 P1 24 VDP3 VSS P3 12 P3 11 P3 10 P3 09 P3 08 P3 07 P3 06 P3 05 P3 04 P3 03 P3 02 P3 01 3 0 VSS VDP3 P3 00 P1 33 P1 32 P1 31 P1 30 VDP3 / 3V-IO AVSS5 AVRH5 AVDD5 DVCC DVSS P1_00 P1_01 P1_02 P1_03 P1_04 P1_05 P1_06 P1_07 DVSS DVCC P1_08 P1_09 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 DVSS DVCC P1_16 P1_17 P1_18 P1_19 P1_20 P1_21 P1_22 P1_23 DVSS DVCC VDP3 VSS P1_34 P1_35 P1_36 P1_37 P1_38 VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Analog ` 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5 51 50 49 48 47 46 45 Document Number: 002-05677 Rev. *C Page 18 of 423 CY9DF125 - Atlas-L Table 16. QFP-176 Package Pinout (Continued) Table 16. QFP-176 Package Pinout Pin Number Pin Name 1 AVSS5 2 AVRH5 3 AVDD5 4 DVCC 5 DVSS 6 P1_00 7 P1_01 8 P1_02 9 P1_03 10 P1_04 11 P1_05 12 P1_06 13 P1_07 14 DVSS 15 DVCC 16 P1_08 17 P1_09 18 P1_10 19 P1_11 20 P1_12 21 P1_13 22 P1_14 23 P1_15 24 DVSS 25 DVCC 26 P1_16 27 P1_17 28 P1_18 29 P1_19 30 P1_20 31 P1_21 32 P1_22 33 P1_23 34 DVSS 35 DVCC 36 VDP3 37 VSS 38 P1_34 39 P1_35 40 P1_36 Document Number: 002-05677 Rev. *C Pin Number Pin Name 41 P1_37 42 P1_38 43 VDD 44 VSS 45 P1_30 46 P1_31 47 P1_32 48 P1_33 49 P3_00 50 VDP3 51 VSS 52 P3_01 53 P3_02 54 P3_03 55 P3_04 56 P3_05 57 P3_06 58 P3_07 59 P3_08 60 P3_09 61 P3_10 62 P3_11 63 P3_12 64 VSS 65 VDP3 66 P1_24 67 P1_25 68 P3_33 69 P3_34 70 P3_35 71 P3_36 72 P3_37 73 P3_38 74 P3_39 75 P3_40 76 P3_41 77 P3_42 78 VDP3 79 VSS 80 P3_13 Page 19 of 423 CY9DF125 - Atlas-L Table 16. QFP-176 Package Pinout (Continued) Table 16. QFP-176 Package Pinout (Continued) Pin Number Pin Name Pin Number Pin Name 81 P3_14 121 P0_27 82 P3_15 122 P0_28 83 P3_16 123 VDP5 84 P3_17 124 VSS 85 P3_18 125 X1 86 P3_19 126 X0 87 P3_20 127 VSS5 88 P3_21 128 X0A 89 VDD 129 X1A 90 VSS 130 MODE 91 P3_22 131 RSTX 92 P3_23 132 VDP5 93 P3_24 133 VSS 94 VDP3 134 VDD 95 VSS 135 VSS 96 P3_25 136 P0_40 97 P3_26 137 P0_41 98 P3_27 138 P0_42 99 P3_28 139 P0_43 100 P3_29 140 P0_44 101 P3_30 141 P0_45 102 P3_31 142 P0_46 103 P3_32 143 P0_47 104 P1_26 144 P0_48 105 P1_27 145 P0_49 106 P1_28 146 P0_50 107 P1_29 147 P0_51 108 VSS 148 P0_62 109 VDP3 149 P0_63 110 P0_08 150 P2_32 111 P0_09 151 P2_33 112 P0_10 152 VDP5 113 P0_11 153 VSS 114 P0_12 154 P2_34 115 P0_13 155 P2_35 116 P0_14 156 P2_36 117 P0_15 157 P2_37 118 P0_26 158 P2_38 119 VDP3 159 P2_39 120 VSS 160 P2_40 Document Number: 002-05677 Rev. *C Page 20 of 423 CY9DF125 - Atlas-L Table 16. QFP-176 Package Pinout (Continued) Pin Number Pin Name 161 P2_41 162 P2_42 163 P2_43 164 P2_44 165 P2_45 166 P2_46 167 P2_47 168 VSS 169 VDP5 170 JTAG_TDO 171 JTAG_TDI 172 JTAG_TCK 173 VSS 174 VDD 175 JTAG_TMS 176 JTAG_NTRST Document Number: 002-05677 Rev. *C Page 21 of 423 CY9DF125 - Atlas-L I/O Pins and Functions IO pin configuration needs to be done by writing into Port Pin Multiplexing registers and Resource Input Configuration registers which are described in Table 17 and Table 18. GPIO_PPERn register must be enabled before starting IO Pin configuration, since GPIO_PPERn enables corresponding pin of the device. Note: Since writing GPIO PPERn registers are required for both Portmux and resource-mux registers. Port Pin Multiplexing Table 17. Port Pin Multiplexing Resource functional output Register (offset) PCFGR008 (0x0010) PCFGR009 (0x0012) PCFGR010 (0x0014) PCFGR011 (0x0016) PCFGR012 (0x0018) PCFGR013 (0x001A) PCFGR014 (0x001C) PCFGR015 (0x001E) Port P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 P0_14 P0_15 POF=0 GPIO0_08 GPIO0_09 GPIO0_10 GPIO0_11 POF=1 SPI2_SS GPIO0_14 GPIO0_15 PPG66_PPGB SPI2_CLK UDC0_UD PPG67_PPGB OT0 SPI0_SSO1 I2S0_WS I2S0_SCK Document Number: 002-05677 Rev. *C POF=4 PPG65_PPGB SPI2_DATA0 I2S0_SD POF=3 PPG64_PPGB SPI2_DATA1 GPIO0_12 GPIO0_13 POF=2 SPI0_SSO2 SPI0_SSO3 SPI1_SSO1 POF=5 OCU0_OTD0 POF=6 RLT9_TOT OCU0_OTD1 OCU1_OTD0 RLT2_TOT OCU1_OTD1 PPG68_PPGB OCU16_OTD0 RLT7_TOT SPI0_DATA PPG69_PPGB OCU16_OTD1 2 SPI0_DATA PPG70_PPGB OCU17_OTD0 3 UDC0_UD PPG71_PPGB OCU17_OTD1 OT1 RLT8_TOT POF=7 Possible Resource Function Input PPG8_PPGA GPIO0_08, EIC0_INT05, EIC0_INT03, SPI2_SS, SPI0_SS, UDC0_AIN0, ICU2_IN0, PPG9_PPGA GPIO0_09, EIC0_INT19, SPI2_DATA1, SPI0_DATA1, UDC0_BIN0, ICU2_IN1, RLT9_TIN, PPG10_PPGA GPIO0_10, EIC0_INT20, SPI2_DATA0, SPI0_DATA0, UDC0_ZIN0, ICU3_IN0, PPG11_PPGA GPIO0_11, EIC0_INT21, SPI2_CLK, SPI0_CLK, ICU3_IN1, RLT2_TIN, PPG12_PPGA GPIO0_12, EIC0_INT22, I2S0_ECLK, I2S1_ECLK, UDC0_AIN1, ICU18_IN0, PPG13_PPGA GPIO0_13, EIC0_INT23, SPI0_DATA2, I2S0_SD, I2S1_SD, UDC0_BIN1, ICU18_IN1, RLT7_TIN, PPG14_PPGA GPIO0_14, EIC0_INT06, EIC0_INT07, SPI0_DATA3, I2S0_WS, I2S1_WS, UDC0_ZIN1, ICU19_IN0, PPG15_PPGA GPIO0_15, EIC0_INT24, I2S0_SCK, I2S1_SCK, ICU19_IN1, RLT8_TIN, Page 22 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR026 (0x0034) Port P0_26 POF=0 POF=1 P0_27 GPIO0_27 USART0_SC K PCFGR028 (0x0038) P0_28 GPIO0_28 USART0_SO T PCFGR041 (0x0052) PCFGR042 (0x0054) PCFGR043 (0x0056) PCFGR044 (0x0058) P0_40 P0_41 P0_42 P0_43 P0_44 GPIO0_40 GPIO0_41 GPIO0_42 GPIO0_43 GPIO0_44 POF=3 OCU1_OTD 0_GI GPIO0_26 PCFGR027 (0x0036) PCFGR040 (0x0050) POF=2 SPI2_SS POF=4 PPG10_PPGB POF=5 OCU1_OTD0 OCU1_OTD 1_GI PPG11_PPGB OCU16_OT D0_GI PPG12_PPGB OCU16_OTD0 RTC_WOT PPG64_PPGB POF=6 OCU1_OTD1 RLT5_TOT OCU16_OTD0_ G OCU16_OTD1_ SPI2_DATA1 SYSC_CKO USART6_S PPG65_PPGB G T CK SPI2_DATA0 SYSC_CKO USART6_S OCU17_OTD0_ RLT2_TOT PPG66_PPGB TX OT G SPI2_CLK SPI0_SS Document Number: 002-05677 Rev. *C WDG_OBS ERVE CAN0_TX PPG67_PPGB OCU17_OTD1_ G SPI2_SSO2 SPI2_DATA OCU0_OTD0_ PPG68_PPGB 2 G RLT3_TOT POF=7 Possible Resource Function Input PPG2_PPGA GPIO0_26, EIC0_INT11, EIC0_INT12, USART0_SIN, USART6_SIN, ICU3_IN0, RLT3_TIN PPG3_PPGA GPIO0_27, EIC0_INT29, USART0_SCK, USART6_SCK, ICU3_IN1, RLT4_TIN PPG4_PPGA GPIO0_28, EIC0_INT12, USART6_SIN, ICU18_IN0I PPG8_PPGA GPIO0_40, EIC0_INT05, EIC0_INT12, EIC0_INT11, SPI2_SS, USART6_SIN, USART0_SIN, FRT0_FRCK, RLT5_TIN, ADC0_AN15 PPG9_PPGA GPIO0_41, EIC0_INT15, SPI2_DATA1, USART6_SCK, USART0_SCK, FRT1_FRCK, RLT6_TIN,, ICU2_IN0, ICU18_IN1, ADC0_AN16 PPG10_PPGA GPIO0_42, EIC0_INT08, EIC0_INT10, EIC0_INT11, SPI2_DATA0, CAN0_RX,, FRT2_FRCK, CAN1_RX,, ICU2_IN1, ICU19_IN0, USART0_SIN, ADC0_AN17 PPG11_PPGA GPIO0_43, EIC0_INT09, SPI2_CLK, CAN1_RX, FRT3_FRCK, RLT2_TIN, ADC0_AN18 PPG12_PPGA GPIO0_44, EIC0_INT03, SPI2_DATA2, SPI0_SS, FRT16_FRCK, UDC0_AIN0, ADC0_AN19 Page 23 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR045 (0x005A) PCFGR046 (0x005C) PCFGR046 (0x005C) PCFGR047 (0x005E) PCFGR048 (0x0060) Port P0_45 P0_46 P0_46 P0_47 P0_48 POF=0 GPIO0_45 GPIO0_46 GPIO0_46 GPIO0_47 GPIO0_48 POF=1 POF=2 POF=3 POF=4 POF=5 POF=6 OCU0_OTD1_ SPI0_DATA1 SPI2_SSO3 SPI2_DATA PPG69_PPGB G 3 SPI0_DATA0 SPI2_SSO1 USART0_S OCU1_OTD0_ PPG70_PPGB CK G ARH0_AIC1_ TDA1 SPI0_DATA0 SPI2_SSO1 USART0_S OCU1_OTD0_ PPG70_PPGB CK G SPI0_CLK SPI1_SS Document Number: 002-05677 Rev. *C OCU1_OTD1_ UDC0_UDO USART0_S PPG71_PPGB G T0 OT SPI0_SSO2 SPI0_DATA 2 PPG0_PPGB OCU0_OTD0 RLT4_TOT POF=7 Possible Resource Function Input PPG13_PPGA GPIO0_45, EIC0_INT11, EIC0_INT12, FRT16_FRCK, FRT18_FRCK, SPI2_DATA3, SPI0_DATA1, USART0_SIN, USART6_SIN, FRT17_FRCK, RLT3_TIN, FRT19_FRCK, UDC0_BIN0, ADC0_AN20 PPG14_PPGA GPIO0_46, EIC0_INT16, SPI0_DATA0, USART0_SCK, USART6_SCK, FRT18_FRCK, RLT4_TIN, UDC0_ZIN0, ICU18_IN0, ADC0_AN21 PPG14_PPGA GPIO0_46, EIC0_INT16, SPI0_DATA0, USART0_SCK, USART6_SCK, FRT18_FRCK, RLT4_TIN, UDC0_ZIN0, ICU18_IN0, ADC0_AN21 PPG15_PPGA GPIO0_47, FRT0_FRCK, FRT1_FRCK, FRT2_FRCK, EIC0_INT17, FRT3_FRCK, SPI0_CLK, FRT16_FRCK, FRT17_FRCK, FRT19_FRCK, RLT0_TIN, FRT18_FRCK, EIC0_INT12, ICU18_IN1, USART6_SIN, ADC0_AN22 PPG64_PPGA GPIO0_48, EIC0_INT04, EIC0_INT09, EIC0_INT08, SPI0_DATA2, SPI1_SS, CAN1_RX, CAN0_RX, ICU2_IN0, UDC0_AIN1, ADC0_AN23 Page 24 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR049 (0x0062) PCFGR050 (0x0064) Port P0_49 P0_50 POF=0 GPIO0_49 GPIO0_50 POF=1 POF=2 POF=3 SPI1_DATA1 SPI0_SSO1 CAN1_TX SPI1_DATA0 SPI0_SSO3 SPI0_DATA 3 POF=4 PPG1_PPGB PPG2_PPGB POF=5 OCU0_OTD1 OCU1_OTD0 POF=6 RLT0_TOT RLT1_TOT POF=7 Possible Resource Function Input PPG65_PPGA GPIO0_49, EIC0_INT10, SPI1_DATA1, ICU2_IN1, CAN0_RX, UDC0_BIN1, ADC0_AN24 PPG66_PPGA GPIO0_50, EIC0_INT10, EIC0_INT09, SPI0_DATA3, SPI1_DATA0, CAN1_RX, ICU3_IN0, UDC0_ZIN1, ADC0_AN25 PPG67_PPGA GPIO0_51, EIC0_INT08, SPI1_CLK, CAN0_RX, ICU3_IN1, RLT1_TIN, ADC0_EDGI PCFGR051 (0x0066) P0_51 GPIO0_51 SPI1_CLK PCFGR062 (0x007C) P0_62 GPIO0_62 I2C0_SCL GPIO0_62, EIC0_INT24, I2C0_SCL PCFGR063 (0x007E) P0_63 GPIO0_63 I2C0_SDA GPIO0_63, EIC0_INT00, I2C0_SDA PPG0_PPGA GPIO1_00, CAN0_RX, EIC0_INT08, EIC0_INT25, ADC0_AN26 PPG1_PPGA GPIO1_01, EIC0_INT26, ADC0_AN26 PPG2_PPGA GPIO1_02, EIC0_INT13, CAN1_RX, EIC0_INT09, ADC0_AN26 PPG3_PPGA GPIO1_03, EIC0_INT27, ADC0_AN26 PPG4_PPGA GPIO1_04, EIC0_INT28, ADC0_AN27 PPG5_PPGA GPIO1_05, EIC0_INT29, ADC0_AN27 PPG6_PPGA GPIO1_06, EIC0_INT30, ADC0_AN27 PPG7_PPGA GPIO1_07, EIC0_INT31, ADC0_AN27 PCFGR100 (0x0080) P1_00 GPIO1_00 SMC0_M2 PCFGR101 (0x0082) P1_01 GPIO1_01 SMC0_P2 PCFGR102 (0x0084) P1_02 GPIO1_02 SMC0_M1 PCFGR103 (0x0086) P1_03 GPIO1_03 SMC0_P1 PCFGR104 (0x0088) P1_04 GPIO1_04 SMC1_M2 PCFGR105 (0x008A) P1_05 GPIO1_05 SMC1_P2 PCFGR106 (0x008C) P1_06 GPIO1_06 SMC1_M1 PCFGR107 (0x008E) P1_07 GPIO1_07 SMC1_P1 Document Number: 002-05677 Rev. *C UDC0_UDO T1 PPG3_PPGB OCU1_OTD1 PPG64_PPGB PPG65_PPGB CAN0_TX PPG66_PPGB PPG67_PPGB PPG68_PPGB PPG69_PPGB PPG70_PPGB PPG71_PPGB CAN1_TX Page 25 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR108 (0x0090) PCFGR109 (0x0092) PCFGR110 (0x0094) PCFGR111 (0x0096) PCFGR112 (0x0098) PCFGR113 (0x009A) PCFGR114 (0x009C) PCFGR115 (0x009E) Port P1_08 P1_09 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 POF=0 GPIO1_08 GPIO1_09 GPIO1_10 GPIO1_11 GPIO1_12 GPIO1_13 GPIO1_14 GPIO1_15 POF=1 POF=2 SMC2_M2 POF=3 POF=4 PPG0_PPGB SMC2_P2 PPG1_PPGB SMC2_M1 PPG2_PPGB SMC2_P1 PPG3_PPGB SMC3_M2 PPG4_PPGB SMC3_P2 PPG5_PPGB SMC3_M1 PPG6_PPGB SMC3_P1 PPG7_PPGB POF=5 POF=6 SPI0_SS SPI0_DATA1 SPI0_DATA0 USART0_SC K USART0_SO T SPI0_CLK SPI1_SS SPI1_DATA1 SPI1_DATA0 USART6_SC K USART6_SO T SPI1_CLK POF=7 Possible Resource Function Input PPG8_PPGA GPIO1_08, USART0_SIN, RLT3_TIN, EIC0_INT00, SPI0_SS, ADC0_AN28, EIC0_INT03, EIC0_INT11 PPG9_PPGA GPIO1_09, USART0_SCK, RLT4_TIN, EIC0_INT01, SPI0_DATA1, ICU2_IN1, ADC0_AN28 PPG10_PPGA GPIO1_10, EIC0_INT02, SPI0_DATA0, ICU2_IN0, ADC0_AN28 PPG11_PPGA GPIO1_11, EIC0_INT03, SPI0_CLK, RLT0_TIN, ADC0_AN28 PPG12_PPGA GPIO1_12, USART6_SIN, RLT5_TIN, EIC0_INT04, SPI1_SS, ADC0_AN29, EIC0_INT12 PPG13_PPGA GPIO1_13, USART6_SCK, RLT6_TIN, EIC0_INT05, SPI1_DATA1, ICU18_IN0, ADC0_AN29 PPG14_PPGA GPIO1_14, EIC0_INT06,, SPI1_DATA0, ICU19_IN1, ADC0_AN29 PPG15_PPGA GPIO1_15, EIC0_INT07, SPI1_CLK, RLT1_TIN, ADC0_AN29 PCFGR116 (0x00A0) P1_16 GPIO1_16 SMC4_M2 PPG8_PPGB SPI2_SS SPI1_SSO2 PPG64_PPGA GPIO1_16, EIC0_INT10, EIC0_INT13, SPI2_SS, ADC0_AN30, EIC0_INT05 PCFGR117 (0x00A2) P1_17 GPIO1_17 SMC4_P2 PPG9_PPGB SPI2_DATA1 SPI1_SSO1 PPG65_PPGA GPIO1_17, EIC0_INT14, SPI2_DATA1, ADC0_AN30 PPG66_PPGA GPIO1_18, EIC0_INT15, SPI2_DATA0, ICU18_IN0, ADC0_AN30 PCFGR118 (0x00A4) P1_18 GPIO1_18 SMC4_M1 Document Number: 002-05677 Rev. *C SG0_SGA SPI2_DATA0 DMA0_DRE PPG10_PPGB Q_ACK1 SPI1_SSO3 Page 26 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) Port POF=0 POF=1 PCFGR119 (0x00A6) P1_19 GPIO1_19 SMC4_P1 PCFGR120 (0x00A8) P1_20 GPIO1_20 SMC5_M2 PCFGR121 (0x00AA) P1_21 GPIO1_21 SMC5_P2 PCFGR122 (0x00AC) P1_22 GPIO1_22 SMC5_M1 PCFGR123 (0x00AE) P1_23 GPIO1_23 POF=2 SG0_SGO POF=4 DMA0_DST PPG11_PPGB P_ACK1 DMA0_DE OP1 POF=5 POF=6 SPI2_CLK PPG12_PPGB PPG13_PPGB PPG14_PPGB SMC5_P1 PPG15_PPGB PCFGR124 (0x00B0) P1_24 GPIO1_24 DBG0_TRAC DMA0_DRE E6 Q_ACK0 PCFGR125 (0x00B2) P1_25 GPIO1_25 DBG0_TRAC DMA0_DST E7 P_ACK0 PCFGR126 (0x00B4) P1_26 GPIO1_26 PCFGR127 (0x00B6) P1_27 PCFGR128 (0x00B8) PCFGR129 (0x00BA) PCFGR130 (0x00BC) POF=3 POF=7 Possible Resource Function Input PPG67_PPGA GPIO1_19, EIC0_INT16, SPI2_CLK, ICU19_IN1, RLT2_TIN, ADC0_AN30 PPG68_PPGA GPIO1_20, EIC0_INT17, ADC0_AN31 PPG69_PPGA GPIO1_21, EIC0_INT18, DMA0_DREQ1, ADC0_AN31 PPG70_PPGA GPIO1_22, EIC0_INT19, DMA0_DSTP1, ADC0_AN31 PPG71_PPGA GPIO1_23, EIC0_INT20, DMA0_DEOP_ ACK1, ADC0_AN31 PPG69_PPGA GPIO1_24, EIC0_INT19, I2S0_ECLK, I2S1_ECLK,, ICU18_IN1 PPG70_PPGA GPIO1_25, EIC0_INT20, I2S1_SD, ICU19_IN0, PPG71_PPGA GPIO1_26, EIC0_INT07, I2S1_WS, ICU19_IN1, PPG5_PPGB OCU16_OTD1 I2S1_SD PPG6_PPGB OCU17_OTD0 DBG0_TRAC DMA0_DEO E0 P0 I2S1_WS PPG7_PPGB OCU17_OTD1 GPIO1_27 DBG0_TRAC E1 I2S1_SCK P1_28 GPIO1_28 DBG0_CTL RLT3_TOT GPIO1_28, EIC0_INT22, DMA0_DSTP0 P1_29 GPIO1_29 DBG0_CLK RLT4_TOT GPIO1_29, EIC0_INT23, DMA0_DEOP_ ACK0 P1_30 GPIO1_30 HSSPI0_SS O3 OCU0_OTD 0 EBI0_MAD13 EBI0_MAD14 GPIO1_27, EIC0_INT21, DMA0_DREQ0, I2S1_SCK DBG0_TRAC E2 EBI0_MAD15 GPIO1_30, EIC0_INT11, PPG_ETRG2, USART0_SIN, RLT3_TIN, ADC0_EDGI PCFGR131 (0x00BE) P1_31 GPIO1_31 HSSPI0_SS O2 OCU0_OTD USART0_S DBG0_TRAC 1 CK E3 EBI0_MAD16 GPIO1_31, EIC0_INT24, USART0_SCK, ICU3_IN1, RLT4_TIN PCFGR132 (0x00C0) P1_32 GPIO1_32 HSSPI0_SS O1 OCU1_OTD USART0_S DBG0_TRAC 0 OT E4 EBI0_MAD17 GPIO1_32, EIC0_INT25, ICU3_IN0 Document Number: 002-05677 Rev. *C Page 27 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR133 (0x00C2) PCFGR134 (0x00C4) PCFGR135 (0x00C6) Port P1_33 P1_34 P1_35 POF=0 GPIO1_33 GPIO1_34 GPIO1_35 POF=1 POF=2 HSSPI0_SS OCU1_OTD 1 HSSPI0_DAT A2 GPIO1_36 HSSPI0_DAT A1 PCFGR137 (0x00CA) P1_37 GPIO1_37 HSSPI0_DAT UDC0_UDO A0 T0 PCFGR138 (0x00CC) P1_38 GPIO1_38 PCFGR233 (0x0142) PCFGR234 (0x0144) P2_33 P2_34 GPIO2_32 GPIO2_33 GPIO2_34 POF=5 POF=6 HSSPI0_CLK SPI2_SS UDC0_UDO SPI1_DATA T0 2 SPI2_DATA1 I2S0_SD SPI2_DATA0 I2S0_WS Document Number: 002-05677 Rev. *C SPI1_DATA 3 PPG8_PPGB PPG9_PPGB PPG10_PPGB OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 POF=7 EBI0_MAD18 GPIO1_33, EIC0_INT01, HSSPI0_SS EBI0_MAD19 GPIO1_34, EIC0_INT08, HSSPI0_DATA 3, CAN0_RX, UDC0_AIN0 EBI0_MAD20 GPIO1_35, EIC0_INT26, HSSPI0_DATA 2, ICU2_IN0, UDC0_BIN0 EBI0_MAD21 GPIO1_36, EIC0_INT09, HSSPI0_DATA 1, CAN1_RX, ICU2_IN1, UDC0_ZIN0 RLT5_TOT EBI0_MAD22 GPIO1_37, EIC0_INT13, HSSPI0_DATA 0, ICU3_IN0 RLT6_TOT EBI0_MAD23 GPIO1_38, EIC0_INT10, HSSPI0_CLK, ICU3_IN1 PPG0_PPGA GPIO2_32, I2S0_ECLK, I2S1_ECLK, SPI1_DATA2, SPI2_SS, SPI0_SS, ICU2_IN0, EIC0_INT05, EIC0_INT03, ADC0_EDGI PPG1_PPGA GPIO2_33, I2S0_SD, I2S1_SD, SPI1_DATA3, UDC0_AIN0, SPI2_DATA1, SPI0_DATA1, ICU2_IN1, EIC0_INT26, ADC0_AN0 PPG2_PPGA GPIO2_34, I2S0_WS, I2S1_WS, UDC0_BIN0, SPI2_DATA0, SPI0_DATA0, ICU3_IN0, EIC0_INT06, EIC0_INT07, ADC0_AN1 DBG0_TRAC E5 CAN1_TX P1_36 P2_32 CAN0_TX POF=4 HSSPI0_DAT A3 PCFGR136 (0x00C8) PCFGR232 (0x0140) POF=3 Possible Resource Function Input RLT9_TOT RLT8_TOT RLT7_TOT Page 28 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR235 (0x0146) PCFGR236 (0x0148) PCFGR237 (0x014A) PCFGR238 (0x014C) PCFGR239 (0x014E) PCFGR240 (0x0150) Port P2_35 P2_36 P2_37 P2_38 P2_39 P2_40 POF=0 GPIO2_35 GPIO2_36 GPIO2_37 GPIO2_38 GPIO2_39 GPIO2_40 POF=1 SPI2_CLK SPI1_SS POF=2 I2S0_SCK UDC0_UDO T1 SPI1_DATA1 I2S1_SD SPI1_DATA0 I2S1_WS SPI1_CLK SPI0_SS Document Number: 002-05677 Rev. *C I2S1_SCK CAN0_TX POF=3 POF=4 PPG11_PPGB PPG12_PPGB PPG13_PPGB PPG14_PPGB PPG15_PPGB PPG64_PPGB POF=5 POF=6 OCU1_OTD1 OCU16_OTD0 OCU16_OTD1 OCU17_OTD0 OCU17_OTD1 OCU0_OTD1_I RLT8_TOT POF=7 Possible Resource Function Input PPG3_PPGA GPIO2_35, I2S0_SCK, I2S1_SCK, UDC0_ZIN0, SPI2_CLK, SPI0_CLK, RLT2_TIN, ICU3_IN1, EIC0_INT29, ADC0_AN2 PPG4_PPGA GPIO2_36, I2S1_ECLK, I2S0_ECLK, SPI1_SS, SPI2_SS, RLT9_TIN, ICU18_IN0, EIC0_INT04, EIC0_INT05, ADC0_AN3 PPG5_PPGA GPIO2_37, I2S1_SD, I2S0_SD, UDC0_AIN1, SPI1_DATA1, SPI2_DATA1, RLT8_TIN, ICU18_IN1, EIC0_INT30, ADC0_AN4 PPG6_PPGA GPIO2_38, I2S1_WS, I2S0_WS, PPG_ETRG0, UDC0_BIN1, SPI1_DATA0, SPI2_DATA0, RLT7_TIN, ICU19_IN0, EIC0_INT06, EIC0_INT07, ADC0_AN5 PPG7_PPGA GPIO2_39, I2S1_SCK, I2S0_SCK, PPG_ETRG1, UDC0_ZIN1, SPI1_CLK, SPI2_CLK, RLT1_TIN, ICU19_IN1, EIC0_INT31, ADC0_AN6 PPG8_PPGA GPIO2_40, I2S0_ECLK, SPI0_SS, SPI1_SS, ICU2_IN0, FRT16_FRCK, CAN1_RX, EIC0_INT03, EIC0_INT04, EIC0_INT10, ADC0_AN7 Page 29 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR241 (0x0152) PCFGR242 (0x0154) PCFGR243 (0x0156) PCFGR244 (0x0158) PCFGR245 (0x015A) PCFGR246 (0x015C) Port P2_41 P2_42 P2_43 P2_44 P2_45 P2_46 POF=0 GPIO2_41 GPIO2_42 GPIO2_43 POF=1 POF=2 POF=3 SPI0_DATA1 I2S0_SD SPI0_DATA0 I2S0_WS SPI0_CLK GPIO2_44 GPIO2_45 GPIO2_46 Document Number: 002-05677 Rev. *C I2S0_SCK PPG65_PPGB SG0_SGA SG0_SGO CAN1_TX PPG66_PPGB PPG67_PPGB PPG68_PPGB I2S1_SD I2S1_WS POF=4 PPG69_PPGB SG0_SGA PPG70_PPGB POF=5 POF=6 OCU0_OTD0_I RLT9_TOT OCU0_OTD1_ GI OCU0_OTD0_ GI OCU16_OTD1_ RLT7_TOT I OCU16_OTD0_ I OCU16_OTD1_ RLT5_TOT GI POF=7 Possible Resource Function Input PPG9_PPGA GPIO2_41, I2S0_SD, CAN0_RX, CAN1_RX, SPI0_DATA1, SPI1_DATA1, RLT8_TIN, ICU2_IN1, FRT17_FRCK, EIC0_INT08, EIC0_INT09, ADC0_AN8 PPG10_PPGA GPIO2_42, I2S0_WS, SPI0_DATA0, SPI1_DATA0, RLT9_TIN, ICU3_IN0, FRT18_FRCK, EIC0_INT06, ADC0_AN9 PPG11_PPGA GPIO2_43, I2S0_SCK, EIC0_NMI, SPI0_CLK, SPI1_CLK, RLT0_TIN, ICU3_IN1, FRT19_FRCK, ADC0_AN10 PPG12_PPGA GPIO2_44, I2S1_ECLK, CAN0_RX, ICU18_IN0, FRT0_FRCK, EIC0_INT08, ADC0_AN11 PPG13_PPGA GPIO2_45, I2S1_SD, CAN1_RX, FRT0_FRCK, RLT7_TIN, ICU18_IN1, FRT1_FRCK, FRT2_FRCK, FRT3_FRCK, CAN0_RX, EIC0_INT09, EIC0_INT10, ADC0_AN12 PPG14_PPGA GPIO2_46, I2S1_WS, CAN0_RX, ICU19_IN0, FRT2_FRCK, EIC0_INT07, EIC0_INT10, EIC0_INT08, ADC0_AN13 Page 30 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) PCFGR247 (0x015E) PCFGR300 (0x0180) PCFGR301 (0x0182) Port P2_47 P3_00 P3_01 POF=0 GPIO2_47 GPIO3_01 P3_02 GPIO3_02 PCFGR303 (0x0186) P3_03 GPIO3_03 PCFGR305 (0x018A) P3_04 P3_05 PCFGR306 (0x018C) P3_06 GPIO3_06 PCFGR307 (0x018E) P3_07 GPIO3_07 PCFGR308 (0x0190) P3_08 GPIO3_08 POF=3 SG0_SGO POF=4 PPG71_PPGB POF=5 POF=6 PPG15_PPGA EBI0_MAD00 GPIO3_00, EIC0_INT12, EIC0_INT11, USART6_SIN, RLT5_TIN, USART0_SIN EBI0_MAD01 GPIO3_01, EIC0_INT27, PPG_ETRG3, USART6_SCK, ICU3_IN1, RLT6_TIN, ADC0_EDGI, USART0_SCK RLT3_TOT EBI0_MAD02 GPIO3_02, EIC0_INT11, EIC0_INT28, ICU3_IN0, USART0_SIN RLT4_TOT EBI0_MAD03 GPIO3_03, EIC0_INT02 EBI0_MAD04 GPIO3_04, EIC0_INT11, EIC0_INT12, USART0_SIN, ICU18_IN0, RLT3_TIN, UDC0_AIN1, USART6_SIN EBI0_MAD05 GPIO3_05, EIC0_INT29, USART0_SCK, ICU18_IN1, RLT4_TIN, UDC0_BIN1, USART6_SCK EBI0_MAD06 GPIO3_06, EIC0_INT12, EIC0_INT30, ICU19_IN0, UDC0_ZIN1, USART6_SIN OCU16_OTD0_ RLT6_TOT GI USART6_SC OCU16_OT K D1 USART6_SO OCU17_OT T D0 OCU17_OT PPG6_PPG PPG70_PPGB D1 A PPG7_PPG PPG71_PPGB A USART0_SC K USART0_SO T SPI0_SSO3 Document Number: 002-05677 Rev. *C PPG8_PPG PPG0_PPGB A PPG9_PPG PPG1_PPGB A POF=7 GPIO2_47, I2S1_SCK, FRT2_FRCK, CAN1_RX, FRT16_FRCK, FRT17_FRCK, FRT18_FRCK, ICU19_IN1, FRT3_FRCK, FRT19_FRCK, FRT0_FRCK, FRT1_FRCK, EIC0_INT09, ADC0_AN14 OCU16_OT D0 GPIO3_04 GPIO3_05 POF=2 I2S1_SCK GPIO3_00 PCFGR302 (0x0184) PCFGR304 (0x0188) POF=1 Possible Resource Function Input UDC0_UDO PPG10_PP T1 GA PPG2_PPGB EBI0_MAD07 GPIO3_07, EIC0_INT31, ICU19_IN1 PPG11_PP GA PPG3_PPGB EBI0_MAD08 GPIO3_08, EIC0_INT00 Page 31 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Possible Resource Function Input Resource functional output Register (offset) Port POF=0 POF=1 POF=2 POF=3 POF=4 POF=5 POF=6 POF=7 PCFGR309 (0x0192) P3_09 GPIO3_09 SPI2_SS OCU0_OTD PPG12_PP 1_I GA PPG4_PPGB EBI0_MAD09 GPIO3_09, SPI2_SS, EIC0_INT05 PCFGR310 (0x0194) P3_10 GPIO3_10 SPI2_DATA1 OCU0_OTD PPG13_PP 0_I GA PPG5_PPGB EBI0_MAD10 GPIO3_10, EIC0_INT02, SPI2_DATA1 PCFGR311 (0x0196) P3_11 GPIO3_11 SPI2_DATA0 OCU0_OTD PPG14_PP 1_GI GA PPG6_PPGB EBI0_MAD11 GPIO3_11, EIC0_INT14, SPI2_DATA0 PCFGR312 (0x0198) P3_12 GPIO3_12 SPI2_CLK OCU0_OTD PPG15_PP 0_GI GA PPG7_PPGB EBI0_MAD12 GPIO3_12, EIC0_INT15, SPI2_CLK, RLT2_TIN PCFGR313 (0x019A) P3_13 GPIO3_13 SPI2_DATA2 UDC0_UDO PPG64_PP T0 GA PPG8_PPGB EBI0_MCSX0 GPIO3_13, EIC0_INT16, SPI2_DATA2, ICU2_IN0 EBI0_MCSX1 GPIO3_14, EIC0_INT17, SPI2_DATA3, ICU2_IN1, UDC0_AIN0 EBI0_MCSX2 GPIO3_15, EIC0_INT18, ICU3_IN0, UDC0_BIN0 EBI0_MCSX3 GPIO3_16, EIC0_INT19, ICU3_IN1, UDC0_ZIN0 EBI0_MDATA00 GPIO3_17, EBI0_MDATA0 0, EIC0_INT20, ICU18_IN0 PCFGR314 (0x019C) P3_14 GPIO3_14 SPI2_DATA3 PPG65_PP GA PCFGR315 (0x019E) P3_15 GPIO3_15 SPI0_SSO1 PPG66_PP PPG10_PPGB GA PCFGR316 (0x01A0) P3_16 GPIO3_16 SPI0_SSO2 PPG67_PP PPG11_PPGB GA PCFGR317 (0x01A2) P3_17 GPIO3_17 SPI2_SSO2 UDC0_UDO PPG68_PP PPG12_PPGB T1 GA PCFGR318 (0x01A4) PCFGR319 (0x01A6) P3_18 P3_19 GPIO3_18 GPIO3_19 SPI2_SSO1 PPG9_PPGB PPG69_PP PPG13_PPGB GA SPI1_DATA2 EBI0_MCSX 8 PPG70_PP PPG14_PPGB GA EBI0_MDQM 1 GPIO3_18, EBI0_MDATA0 EBI0_MDATA01 1, EIC0_INT21, ICU18_IN1, UDC0_AIN1 GPIO3_19, EBI0_MDATA0 2, EIC0_INT22, EBI0_MDATA02 SPI1_DATA2, ICU19_IN0, UDC0_BIN1 GPIO3_20, EBI0_MDATA0 3, EIC0_INT23, EBI0_MDATA03 SPI1_DATA3, ICU19_IN1, UDC0_ZIN1 PCFGR320 (0x01A8) P3_20 GPIO3_20 SPI1_DATA3 PCFGR321 (0x01AA) P3_21 GPIO3_21 SPI1_SS OCU17_OT D0 EBI0_MDATA04 GPIO3_21, EBI0_MDATA0 4, SPI1_SS, EIC0_INT04 PCFGR322 (0x01AC) P3_22 GPIO3_22 SPI1_DATA1 OCU17_OT D1 EBI0_MDATA05 GPIO3_22, EBI0_MDATA0 5, EIC0_INT20, SPI1_DATA1 Document Number: 002-05677 Rev. *C PPG71_PP PPG15_PPGB GA Page 32 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Possible Resource Function Input Resource functional output Register (offset) PCFGR323 (0x01AE) Port P3_23 POF=0 GPIO3_23 POF=1 POF=2 POF=3 POF=4 POF=5 SPI1_DATA0 POF=6 RLT0_TOT POF=7 EBI0_MDATA06 GPIO3_23, EBI0_MDATA0 6, EIC0_INT21, SPI1_DATA0 GPIO3_24, EBI0_MDATA0 EBI0_MDATA07 7, EIC0_INT22, SPI1_CLK, RLT1_TIN PCFGR324 (0x01B0) P3_24 GPIO3_24 SPI1_CLK PCFGR325 (0x01B2) P3_25 GPIO3_25 SPI0_SS OCU0_OTD PPG64_PP 0 GB PPG0_PPGA RLT1_TOT EBI0_MDATA08 GPIO3_25, EBI0_MDATA0 8, SPI0_SS, EIC0_INT03 PCFGR326 (0x01B4) P3_26 GPIO3_26 SPI0_DATA1 OCU0_OTD PPG65_PP 1 GB PPG1_PPGA RLT2_TOT EBI0_MDATA09 GPIO3_26, EBI0_MDATA0 9, EIC0_INT24, SPI0_DATA1 PCFGR327 (0x01B6) P3_27 GPIO3_27 SPI0_DATA0 OCU1_OTD PPG66_PP 0 GB PPG2_PPGA RLT5_TOT EBI0_MDATA10 GPIO3_27, EBI0_MDATA1 0, EIC0_INT25, SPI0_DATA0 PCFGR328 (0x01B8) P3_28 GPIO3_28 SPI0_CLK OCU1_OTD PPG67_PP 1 GB PPG3_PPGA EBI0_MDATA11 GPIO3_28, EBI0_MDATA11 , EIC0_INT26, SPI0_CLK, RLT0_TIN PCFGR329 (0x01BA) P3_29 GPIO3_29 SPI0_DATA2 OCU16_OT PPG68_PP D0 GB PPG4_PPGA EBI0_MDATA12 GPIO3_29, EBI0_MDATA1 2, EIC0_INT27, SPI0_DATA2 PPG5_PPGA GPIO3_30, EBI0_MDATA1 EBI0_MDATA13 3, EIC0_INT28, SPI0_DATA3, RLT5_TIN PCFGR330 (0x01BC) P3_30 GPIO3_30 SPI0_DATA3 OCU16_OT PPG69_PP D1 GB PCFGR331 (0x01BE) P3_31 GPIO3_31 SPI1_SSO1 OCU1_OTD 1_I SG0_SGO EBI0_MDATA14 GPIO3_31, EBI0_MDATA1 4, EIC0_INT27, ICU19_IN0 PCFGR332 (0x01C0) P3_32 GPIO3_32 SPI1_SSO2 OCU1_OTD 0_I SG0_SGA EBI0_MDATA15 GPIO3_32, EBI0_MDATA1 5, EIC0_INT28, ICU19_IN1 PCFGR333 (0x01C2) P3_33 GPIO3_33 OCU1_OTD UDC0_UD 1_GI OT0 EBI0_MAD18 EBI0_MNAL E EBI0_MCASX GPIO3_33, I2S0_ECLK, EIC0_INT01 PCFGR334 (0x01C4) P3_34 GPIO3_34 OCU1_OTD 0_GI I2S0_SD EBI0_MAD19 EBI0_MNCL E EBI0_MRASX GPIO3_34, I2S0_SD, EIC0_INT14, UDC0_AIN0 PCFGR335 (0x01C6) P3_35 GPIO3_35 OCU16_OT D1_I I2S0_WS EBI0_MAD20 EBI0_MNWE X EBI0_MDWEX GPIO3_35, I2S0_WS, UDC0_BIN0, EIC0_INT06 PCFGR336 (0x01C8) P3_36 GPIO3_36 OCU16_OT D0_I I2S0_SCK EBI0_MAD21 EBI0_MNRE X EBI0_MCKE GPIO3_36, I2S0_SCK, EIC0_INT18, UDC0_ZIN0 PCFGR337 (0x01CA) P3_37 GPIO3_37 OCU16_OT UDC0_UD D1_GI OT1 EBI0_MAD18 EBI0_MCAS X EBI0_MDQM0 GPIO3_37, I2S1_ECLK, EIC0_INT19 Document Number: 002-05677 Rev. *C Page 33 of 423 CY9DF125 - Atlas-L Table 17. Port Pin Multiplexing (Continued) Resource functional output Register (offset) Port POF=0 POF=1 POF=2 POF=3 POF=4 POF=5 POF=6 POF=7 Possible Resource Function Input PCFGR338 (0x01CC) P3_38 GPIO3_38 OCU16_OT D0_GI I2S1_SD EBI0_MAD19 EBI0_MRAS X EBI0_MDQM1 GPIO3_38, I2S1_SD, EIC0_INT23, UDC0_AIN1 PCFGR339 (0x01CE) P3_39 GPIO3_39 OCU17_OT D1_I I2S1_WS EBI0_MAD20 EBI0_MDWE X EBI0_MWEX GPIO3_39, I2S1_WS, UDC0_BIN1, EIC0_INT07 PCFGR340 (0x01D0) P3_40 GPIO3_40 OCU17_OT D0_I I2S1_SCK EBI0_MAD21 EBI0_MCKE EBI0_MOEX GPIO3_40, I2S1_SCK, EIC0_INT29, UDC0_ZIN1 PCFGR341 (0x01D2) P3_41 GPIO3_41 SPI1_SSO3 OCU17_OT D1_GI EBI0_MCLK GPIO3_41, EIC0_INT30, ADC0_EDGI PCFGR342 (0x01D4) P3_42 GPIO3_42 SPI2_SSO3 OCU17_OT D0_GI Document Number: 002-05677 Rev. *C EBI0_MAD22 EBI0_MDQM 0 GPIO3_42, EBI0_RDY, EIC0_INT31 Page 34 of 423 CY9DF125 - Atlas-L Resource Input Source RICFG0_ADC Table 18. Resource Input Source Table for ADC Configurations Register (offset) Resource input ADC0EDGIL ADC0EDGI (0x000C) Source for resource input Register Field Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 PORTPIN OCU - - - - - - reserved reserved reserved reserved reserved reserved - - - - - - reserved reserved reserved reserved reserved reserved OCU10 OCU11 - - - - reserved reserved reserved reserved All the signals that are enabled Ports selectby the ed by ADC0EDGIOCU ADC0EDGI_ n registers ANDPORTSEL ed together. register. If they are not enabled, they are masked to '1'. PORTSEL ADC0_EDGI ADC0EDGIH 0010: P1_30 is selected 0100: P0_51 is selected 0101: P2_32 is selected 0110: P3_01 is selected 0111: P3_41 is selected OCU00 ADC0EDGIO ADC0_EDGI CU0 (0x000E) 0: ADC0EDGIO OCU0_OTD0 is disabled CU0L 1: OCU0_OTD0 is enabled - ADC0EDGIO ADC0_EDGI CU1 (0x0010) - ADC0EDGIO ADC0_EDGI CU2 (0x0012) - ADC0EDGIO ADC0_EDGI CU3 (0x0014) - Document Number: 002-05677 Rev. *C OCU01 0: OCU0_OTD1 is disabled 1: OCU0_OTD1 is enabled 0: 0: OCU1_OTD0 OCU1_OTD1 is disabled is disabled 1: 1: OCU1_OTD0 OCU1_OTD1 is enabled is enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Page 35 of 423 CY9DF125 - Atlas-L Table 18. Resource Input Source Table for ADC Configurations (Continued) Register (offset) Resource input ADC0EDGIO ADC0_EDGI CU4 (0x0016) Source for resource input Register Field Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 OCU160 OCU161 OCU170 OCU171 - - - - reserved reserved reserved reserved 0: 0: 0: ADC0EDGIO OCU16_OTD 0: OCU16_OTD1 OCU17_OTD OCU17_OTD 0 is disabled is disabled 0 is disabled 1 is disabled CU4L 1: 1: OCU16_OTD1 1: 1: OCU16_OTD is enabled OCU17_OTD OCU17_OTD 0 is enabled 0 is enabled 1 is enabled - ADC0EDGIO ADC0_EDGI CU5 (0x0018) - ADC0EDGIO ADC0_EDGI CU6 (0x001A) - ADC0EDGIO CU7 (0x001C) ADC0_EDGI - ADC0TIMIL ADC0TIMI (0x001E) ADC0_TIMI ADC0TIMIRL TL ADC0_TIMI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RLT PPGL PPGH - - - - - reserved reserved reserved reserved reserved UFSET outADTRGH and put of RLT ADTRGH and ADTRGL sigthat is select- ADTRGL signals nals of ed by of PPG0 to PPG64 to RICFGRADC PPG63 ORed toPPG127 0_TIMIRLT gether ORed togethbits [3:0] er - - - - - - - - - - - - - - - - RLT - - - - 0000: RLT0_UFSE T 0001: RLT1_UFSE T ... 1001: RLT9_UFSE T 1010 - 1111: clipped to GND (reserved in spec) - - - - - ADC0TIMIRL T (0x0020) - - Document Number: 002-05677 Rev. *C - - - - - - - - - - - - - - - - Page 36 of 423 CY9DF125 - Atlas-L Table 18. Resource Input Source Table for ADC Configurations (Continued) Register (offset) Resource input Source for resource input Register Field Bit 0 Bit 1 Bit 2 Bit 3 ZPDEN ADC0ZPDEN (0x003E) ADC0_ZPD ADC0ZPDEN Bit 4 Bit 5 Bit 6 Bit 7 - - - - 0: ZPD disable 1: ZPD enable RICFG0 Table 19. Resource Input Source Table (RICFG0) Register (offset) Resource Input Source for resource input RESSEL[3:0]/PO RTSEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - - - - - - - - - - - - - - - - P1_00 (6) P1_01 (7) P1_02 (8) P1_03 (9) P1_00 (6)/ P1_01 (7) P1_01 (7)/ P1_00 (6) P1_02 (8)/ P1_03 (9) P1_03 (9)/ P1_02 (8) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P1_05 (11)/ P1_04 (10) P1_06 (12)/ P1_07 (13) P1_07 (13)/ P1_06 (12) RESSEL ADC0AN26 (0x0000) ADC0_AN26 PORTSEL RESSEL ADC0AN27 (0x0002) ADC0_AN27 PORTSEL P1_04 (10) P1_05 (11) P1_06 (12) P1_07 (13) P1_04 (10)/ P1_05 (11) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P1_08 (16) P1_09 (17) P1_10 (18) P1_11 (19) P1_08 (16)/ P1_09 (17) P1_09 (17)/ P1_08 (16) P1_10 (18)/ P1_11 (19) P1_11 (19)/ P1_10 (18) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P1_13 (21)/ P1_12 (20) P1_14 (22)/ P1_15 (23) P1_15 (23)/ P1_14 (22) RESSEL ADC0AN28 (0x0004) ADC0_AN28 PORTSEL RESSEL ADC0AN29 (0x0006) ADC0_AN29 PORTSEL P1_12 (20) P1_13 (21) P1_14 (22) P1_15 (23) P1_12 (20)/ P1_13 (21) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P1_16 (26) P1_17 (27) P1_18 (28) P1_19 (29) P1_16 (26)/ P1_17 (27) P1_17 (27)/ P1_16 (26) P1_18 (28)/ P1_19 (29) P1_19 (29)/ P1_18 (28) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P1_21 (31)/ P1_20 (30) P1_22 (32)/ P1_23 (33) P1_23 (33)/ P1_22 (32) reserved reserved reserved RESSEL ADC0AN30 (0x0008) ADC0_AN30 PORTSEL RESSEL ADC0AN31 (0x000A) ADC0_AN31 PORTSEL P1_20 (30) P1_21 (31) P1_22 (32) P1_23 (33) P1_20 (30)/ P1_21 (31) reserved reserved reserved reserved reserved Document Number: 002-05677 Rev. *C Page 37 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input RESSEL FRT0TEXT (0x0400) RESSEL RESSEL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Port Sel RLT2_TOT RLT3_TOT RLT0_TOT PPG10_PPG B reserved reserved reserved - - - - - - - - reserved reserved reserved P0_40 (136) P0_47 (143) P2_44 (164) P2_45 (165) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved RLT1_TOT PPG11_PPG B reserved reserved reserved Port Sel RESSEL - - - - - - - reserved P0_41 (137) P0_47 (143) P2_45 (165) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Port Sel RLT2_TOT RLT3_TOT RLT4_TOT PPG12_PPG B reserved reserved reserved - - - - - - - - reserved reserved reserved P0_42 (138) P0_47 (143) P2_45 (165) P2_46 (166) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved RLT5_TOT PPG13_PPG B reserved reserved reserved Port Sel ICU2_IN0 PORTSEL ICU2_IN1 PORTSEL ICU2FRTSEL ICU2_FRTSE (0x0844) L - - - - - - - reserved P0_43 (139) P0_47 (143) P2_45 (165) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_08(110) reserved reserved reserved P0_48 (144) P1_35 (39) reserved P0_41 (137) P1_10 (18) P2_32 (150) P2_40 (160) P3_13 (80) reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_09(111) reserved reserved reserved P0_49 (145) P1_36 (40) reserved P0_42 (138) P1_09 (17) P2_33 (151) P2_41 (161) P3_14 (81) reserved reserved reserved FRT2 FRT0 reserved reserved reserved reserved reserved reserved RESSEL PORTSEL RESSEL ICU3IN0 (0x0860) ICU3_IN0 PORTSEL ICU3_IN1 PORTSEL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - reserved P0_10(112) reserved P0_26(118) P0_50 (146) P1_37 (41) reserved P1_32 (47) P2_34 (154) P2_42 (162) P3_02 (53) P3_15 (82) reserved reserved reserved reserved - - - - - - - - - - - - - - - - RESSEL ICU3IN1 (0x0862) RLT3_TOT - RESSEL ICU2IN1 (0x0842) RLT2_TOT reserved RESSEL ICU2IN0 (0x0840) RLT3_TOT - FRT3_TEXT PORTSEL RLT2_TOT reserved FRT2_TEXT PORTSEL FRT3TEXT (0x0460) 1 FRT1_TEXT PORTSEL FRT2TEXT (0x0440) 0 FRT0_TEXT PORTSEL FRT1TEXT (0x0420) Source for resource input RESSEL[3:0]/PO RTSEL[3:0] reserved P0_11(113) reserved P0_27(121) P0_51 (147) P1_38 (42) reserved P1_31 (46) P2_35 (155) P2_43 (163) P3_01 (52) P3_16 (83) reserved reserved reserved reserved Document Number: 002-05677 Rev. *C Page 38 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input ICU3FRTSEL ICU3_FRTSE (0x0864) L Source for resource input RESSEL[3:0]/PO RTSEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FRT3 FRT1 ICU2_TOUT0 [15:0] reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - RLT4_TOT RLT0_TOT reserved reserved - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved RESSEL PORTSEL OCU0OTD0 GATE (0x0C00) OCU0_OTD0 Gate RESSEL PORTSEL OCU0OTD0 OCU0_OTD0 GM (0x0C02) GateMode RESSEL - - - - - - - - - - - - - - - - RLT4_TOT RLT1_TOT reserved reserved - - - - PORTSEL OCU0OTD1 GATE (0x0C04) OCU0_OTD1 Gate RESSEL PORTSEL OCU0OTD1 OCU0_OTD1 GM (0x0C06) GateMode RESSEL PORTSEL OCU1CMP0 OCU1_CMP0 EXT EXT (0x0C20) RESSEL OCU1_OTD0 Gate OCU1_OTD1 Gate OCU1OTD1 OCU1_OTD1 GM (0x0C2A) GateMode - - - - - - - Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - RLT4_TOT RLT2_TOT reserved reserved - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - RLT4_TOT RLT3_TOT reserved reserved - - - - PPG5_PPGA PPG9_PPGA OCU0_OTD0 OCU0_OTD1 - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - P0_27(121) reserved P0_41 (137) P0_46 (142) P1_31 (46) reserved P1_09 (17) P3_01 (52) P3_05 (56) reserved reserved reserved reserved reserved reserved reserved RESSEL PORTSEL RESSEL PORTSEL PPG5_PPGA PPG8_PPGA OCU0_OTD0 OCU0_OTD1 - PORTSEL USART0SCK USART0_SC I (0x1400) KI - RESSEL RESSEL - FRT0 PORTSEL OCU1OTD1 GATE (0x0C28) - - PORTSEL OCU1OTD0 OCU1_OTD0 GM (0x0C26) GateMode - FRT1 RESSEL RESSEL - - - PORTSEL OCU1OTD0 GATE (0x0C24) PPG5_PPGA PPG7_PPGA OCU1_OTD0 OCU1_OTD1 Async OCU1_MTR OCU0_CMP0 G OUT PORTSEL OCU1FRTSE OCU1_FRTS L (0x0C22) EL PPG5_PPGA PPG6_PPGA OCU1_OTD0 OCU1_OTD1 Document Number: 002-05677 Rev. *C Page 39 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input Source for resource input RESSEL[3:0]/PO RTSEL[3:0] RESSEL USART0SIN USART0_SIN (0x1402) PORTSEL PPG0PPGA GATE (0x1C00) PPG0_PPGA Gate PPG0_PPGB Gate PPG1_PPGA Gate PPG1_PPGB Gate PPG2_PPGA Gate PPG2_PPGB Gate 10 11 12 13 14 15 - - - - - - - - - - - - P1_30 (45) reserved P0_42 (138) P1_08 (16) P3_00 (49) P3_02 (53) P3_04 (55) reserved reserved reserved reserved 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RESSEL RESSEL RESSEL RESSEL RESSEL RESSEL RESSEL RESSEL RESSEL RESSEL PORTSEL PPG2PPGB GATE (0x1C44) 9 P0_45 (141) PORTSEL PPG2PPGA PPG2_PPGA GM (0x1C42) GateMode 8 - PORTSEL PPG2PPGA GATE (0x1C40) 7 P0_40 (136) PORTSEL PPG1PPGB PPG1_PPGB GM (0x1C26) GateMode 6 - PORTSEL PPG1PPGB GATE (0x1C24) 5 reserved PORTSEL PPG1PPGA PPG1_PPGA GM (0x1C22) GateMode 4 - PORTSEL PPG1PPGA GATE (0x1C20) 3 reserved PORTSEL PPG0PPGB PPG0_PPGB GM (0x1C06) GateMode 2 - PORTSEL PPG0PPGB GATE (0x1C04) 1 P0_26(118) PORTSEL PPG0PPGA PPG0_PPGA GM (0x1C02) GateMode 0 RESSEL PORTSEL Document Number: 002-05677 Rev. *C - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 40 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input PPG2PPGB PPG2_PPGB GM (0x1C46) GateMode RESSEL[3:0]/PO RTSEL[3:0] RESSEL PORTSEL PPG3PPGA GATE (0x1C60) PPG3_PPGA Gate RESSEL PORTSEL PPG3PPGA PPG3_PPGA GM (0x1C62) GateMode RESSEL PORTSEL PPG3PPGB GATE (0x1C64) PPG3_PPGB Gate RESSEL PORTSEL PPG3PPGB PPG3_PPGB GM (0x1C66) GateMode RESSEL PORTSEL PPG4PPGA GATE (0x1C80) PPG4_PPGA Gate RESSEL PORTSEL PPG4PPGA PPG4_PPGA GM (0x1C82) GateMode RESSEL PORTSEL PPG4PPGB GATE (0x1C84) PPG4_PPGB Gate RESSEL PORTSEL PPG4PPGB PPG4_PPGB GM (0x1C86) GateMode RESSEL PORTSEL PPG5PPGA GATE (0x1CA0) PPG5_PPGA Gate RESSEL PORTSEL PPG5PPGA PPG5_PPGA GM (0x1CA2) GateMode RESSEL PORTSEL PPG5PPGB GATE (0x1CA4) PPG5_PPGB Gate RESSEL PORTSEL Document Number: 002-05677 Rev. *C Source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 41 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input PPG5PPGB PPG5_PPGB GM (0x1CA6) GateMode RESSEL[3:0]/PO RTSEL[3:0] RESSEL PORTSEL PPG6PPGA GATE (0x1CC0) PPG6_PPGA Gate RESSEL PORTSEL PPG6PPGA PPG6_PPGA GM (0x1CC2) GateMode RESSEL PORTSEL PPG6PPGB GATE (0x1CC4) PPG6_PPGB Gate RESSEL PORTSEL PPG6PPGB PPG6_PPGB GM (0x1CC6) GateMode RESSEL PORTSEL PPG7PPGA GATE (0x1CE0) PPG7_PPGA Gate RESSEL PORTSEL PPG7PPGA PPG7_PPGA GM (0x1CE2) GateMode RESSEL PORTSEL PPG7PPGB GATE (0x1CE4) PPG7_PPGB Gate RESSEL PORTSEL PPG7PPGB PPG7_PPGB GM (0x1CE6) GateMode RESSEL PORTSEL PPG8PPGA GATE (0x1D00) PPG8_PPGA Gate RESSEL PORTSEL PPG8PPGA PPG8_PPGA GM (0x1D02) GateMode RESSEL PORTSEL PPG8PPGB GATE (0x1D04) PPG8_PPGB Gate RESSEL PORTSEL Document Number: 002-05677 Rev. *C Source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 42 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input PPG8PPGB PPG8_PPGB GM (0x1D06) GateMode RESSEL[3:0]/PO RTSEL[3:0] RESSEL PORTSEL PPG9PPGA GATE (0x1D20) PPG9_PPGA Gate RESSEL PORTSEL PPG9PPGA PPG9_PPGA GM (0x1D22) GateMode RESSEL PORTSEL PPG9PPGB GATE (0x1D24) PPG9_PPGB Gate PPG9PPGB PPG9_PPGB GM (0x1D26) GateMode RESSEL PORTSEL RESSEL PORTSEL PPG10PPGA PPG10_PPG GATE A Gate (0x1D40) PPG10PPGA PPG10_PPG GM (0x1D42) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG10PPGB PPG10_PPG GATE B Gate (0x1D44) PPG10PPGB PPG10_PPG GM (0x1D46) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG11PPGA PPG11_PPG GATE A Gate (0x1D60) PPG11PPGA PPG11_PPG GM (0x1D62) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG11PPGB PPG11_PPG GATE B Gate (0x1D64) RESSEL PORTSEL Document Number: 002-05677 Rev. *C Source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 43 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input PPG11PPGB PPG11_PPG GM (0x1D66) B GateMode RESSEL[3:0]/PO RTSEL[3:0] RESSEL PORTSEL PPG12PPGA PPG12_PPG GATE A Gate (0x1D80) PPG12PPGA PPG12_PPG GM (0x1D82) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG12PPGB PPG12_PPG GATE B Gate (0x1D84) PPG12PPGB PPG12_PPG GM (0x1D86) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG13PPGA PPG13_PPG GATE A Gate (0x1DA0) PPG13PPGA PPG13_PPG GM (0x1DA2) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG13PPGB PPG13_PPG GATE B Gate (0x1DA4) PPG13PPGB PPG13_PPG GM (0x1DA6) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG14PPGA PPG14_PPG GATE A Gate (0x1DC0) PPG14PPGA PPG14_PPG GM (0x1DC2) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG14PPGB PPG14_PPG GATE B Gate (0x1DC4) RESSEL PORTSEL Document Number: 002-05677 Rev. *C Source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 44 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input PPG14PPGB PPG14_PPG GM (0x1DC6) B GateMode Source for resource input RESSEL[3:0]/PO RTSEL[3:0] RESSEL PORTSEL PPG15PPGA PPG15_PPG GATE A Gate (0x1DE0) PPG15PPGA PPG15_PPG GM (0x1DE2) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG15PPGB PPG15_PPG GATE B Gate (0x1DE4) PPG15PPGB PPG15_PPG GM (0x1DE6) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPGGRP0ET PPGGRP0_E RG0 (0x2400) TRG0 RESSEL PORTSEL PPGGRP0ET PPGGRP0_E RG1 (0x2402) TRG1 RESSEL PORTSEL PPGGRP0ET PPGGRP0_E RG2 (0x2404) TRG2 RESSEL RESSEL PORTSEL PPGGRP0RL PPGGRP0_R TTRG1 LTTRG1 (0x2408) PPGGRP1ET PPGGRP1_E RG0 (0x2420) TRG0 RESSEL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved reserved - - - Port Sel P2_38 Port Sel P2_39 Port Sel P1_30 Port Sel RESSEL RESSEL PORTSEL OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - - - - - - OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - reserved reserved reserved - - - - - - - - - - - - - - reserved reserved reserved OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - - - - - - - reserved reserved reserved OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - P3_01 - - - - - - - RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RLT8_TOT - - - - - - - - - - - - PORTSEL PORTSEL PPGGRP1ET PPGGRP1_E RG1 (0x2422) TRG1 1 PORTSEL PPGGRP0ET PPGGRP0_E RG3 (0x2406) TRG3 0 Port Sel OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - reserved reserved reserved - - - - - - - - P2_38 - - - - - - - Port Sel reserved reserved reserved - - - - - - - - P2_39 - - - - - - - Document Number: 002-05677 Rev. *C OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 Page 45 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input PPGGRP1ET PPGGRP1_E RG2 (0x2424) TRG2 RESSEL RESSEL PPGGRP2ET PPGGRP2_E RG0 (0x2440) TRG0 RESSEL RESSEL RESSEL 7 8 9 10 11 12 13 14 15 reserved reserved reserved Port Sel OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - - - - - - - reserved reserved reserved - - - OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - P3_01 - - - - - - - RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RLT8_TOT - - - - - - - - - - - - - - - - Port Sel reserved reserved reserved - - - - - - - - P2_38 - - - - - - - reserved reserved reserved Port Sel OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - - - - - - - - - - - - RESSEL Port Sel reserved reserved reserved RESSEL RESSEL RESSEL RESSEL RESSEL PORTSEL OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - P1_30 - - - - - - - reserved reserved reserved Port Sel OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - P3_01 - - - - - - - RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RLT8_TOT - - - - - - - - - - - - - - - - reserved reserved reserved PORTSEL PORTSEL PPGGRP3ET PPGGRP3_E RG2 (0x2464) TRG2 6 - PORTSEL PPGGRP3ET PPGGRP3_E RG1 (0x2462) TRG1 5 P2_39 PORTSEL PPGGRP3ET PPGGRP3_E RG0 (0x2460) TRG0 4 PORTSEL PORTSEL PPGGRP2RL PPGGRP2_R TTRG1 LTTRG1 (0x2448) 3 P1_30 PPGGRP2ET PPGGRP2_E RG2 (0x2444) TRG2 PPGGRP2ET PPGGRP2_E RG3 (0x2446) TRG3 2 Port Sel PORTSEL PORTSEL PPGGRP2ET PPGGRP2_E RG1 (0x2442) TRG1 1 PORTSEL PPGGRP1RL PPGGRP1_R TTRG1 LTTRG1 (0x2428) 0 PORTSEL PPGGRP1ET PPGGRP1_E RG3 (0x2426) TRG3 Source for resource input RESSEL[3:0]/PO RTSEL[3:0] Port Sel OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - - - - - - P2_38 - - - - - - - reserved reserved reserved Port Sel P2_39 Port Sel OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - - - - - - - - - - - - reserved reserved reserved OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - P1_30 - - - - - - - Document Number: 002-05677 Rev. *C Page 46 of 423 CY9DF125 - Atlas-L Table 19. Resource Input Source Table (RICFG0) (Continued) Register (offset) Resource Input PPGGRP3ET PPGGRP3_E RG3 (0x2466) TRG3 RESSEL PORTSEL PPGGRP3RL PPGGRP3_R TTRG1 LTTRG1 (0x2468) Source for resource input RESSEL[3:0]/PO RTSEL[3:0] RESSEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved reserved reserved Port Sel OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - P3_01 - - - - - - - RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RLT8_TOT - - - - - - - - - - - - - - - - PORTSEL RICFG1 Table 20. Resource Input Source Table (RICFG1) Source for resource input Register (offset) Resource Input PPGGRP16E PPGGRP16_ TRG0 ETRG0 (0x2C00) PPGGRP16E PPGGRP16_ TRG1 ETRG1 (0x2C02) PPGGRP16E PPGGRP16_ TRG2 ETRG2 (0x2C04) RESSEL[3:0]/ PORTSEL[3:0] PPGGRP17E PPGGRP17_ TRG0 ETRG0 (0x2C20) PPGGRP17E PPGGRP17_ TRG1 ETRG1 (0x2C22) PPGGRP17E PPGGRP17_ TRG2 ETRG2 (0x2C24) 2 3 4 5 6 7 9 10 11 12 13 14 15 reserved reserved reserved - - - - PORTSEL P2_38 Port Sel RESSEL - PORTSEL P2_39 Port Sel RESSEL P1_30 Port Sel RESSEL RESSEL OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - - - - - - OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - reserved reserved reserved - - - - - - - - - - - - - - reserved reserved reserved OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - - - - - - - reserved reserved reserved OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - P3_01 - - - - - - - RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RLT8_TOT - - - - - - - - - - - - PORTSEL PPGGRP16R PPGGRP16_ LTTRG1 RLTTRG1 (0x2C08) 1 8 Port Sel RESSEL PORTSEL PPGGRP16E PPGGRP16_ TRG3 ETRG3 (0x2C06) 0 PORTSEL RESSEL PORTSEL Port Sel OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 - - - reserved reserved reserved - - - - - - - - P2_38 - - - - - - - reserved reserved reserved - - - - - - - - PORTSEL P2_39 - - - - - - - RESSEL Port Sel reserved reserved reserved RESSEL PORTSEL Document Number: 002-05677 Rev. *C Port Sel OCU0_OTD0 OCU0_OTD1 OCU1_OTD0 OCU1_OTD1 OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 - - - - - - - - P1_30 - - - - - - - Page 47 of 423 CY9DF125 - Atlas-L Table 20. Resource Input Source Table (RICFG1) (Continued) Source for resource input Register (offset) Resource Input PPGGRP17E PPGGRP17_ TRG3 ETRG3 (0x2C26) RESSEL[3:0]/ PORTSEL[3:0] RESSEL CAN0RX (0x0400) RESSEL CAN1RX (0x0420) 10 11 12 13 14 15 reserved reserved reserved OCU16_OTD OCU16_OTD OCU17_OTD OCU17_OTD 0 1 0 1 P3_01 - - - - - - - RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RLT8_TOT - - - - - - - - - - - - - - - - CAN0_RX reserved reserved reserved reserved reserved reserved reserved - - - - - - - - reserved reserved reserved P0_42 (138) P0_48 (144) P0_51 (147) P1_34 (38) P1_00 (6) P2_41 (161) P2_44 (164) P2_46 (166) reserved reserved reserved reserved reserved CAN1_RX reserved reserved reserved reserved reserved reserved reserved - - - - - - - - reserved reserved reserved P0_43 (139) P0_48 (144) P0_50 (146) P1_36 (40) P1_02 (8) P2_41 (161) P2_45 (165) P2_47 (167) reserved reserved reserved reserved reserved Port Sel RLT2_TOT RLT3_TOT RLT6_TOT PPG64_PPG B reserved reserved reserved - - - - - - - - reserved reserved P0_44 (140) P0_45 (141) P0_47 (143) P2_40 (160) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT7_TOT PPG65_PPG B reserved reserved reserved FRT16_TEXT Port Sel FRT17_TEXT FRT18_TEXT PORTSEL FRT19_TEXT PORTSEL RESSEL RLT2_TOT RLT3_TOT - - - - - - - - reserved reserved P0_45 (141) P0_47 (143) P2_41 (161) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Port Sel RLT2_TOT RLT3_TOT RLT8_TOT PPG66_PPG B reserved reserved reserved - - - - - - - - reserved reserved P0_45 (141) P0_46 (142) P0_47 (143) P2_42 (162) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT9_TOT PPG67_PPG B reserved reserved reserved Port Sel RESSEL RLT2_TOT RLT3_TOT - - - - - - - - reserved reserved P0_45 (141) P0_47 (143) P2_43 (163) P2_47 (167) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_12(114) reserved P0_28(122) reserved reserved reserved P0_46 (142) P1_13 (21) P1_18 (28) P2_36 (156) P2_44 (164) P3_04 (55) P3_17 (84) reserved reserved ICU18_IN0 PORTSEL 9 - RESSEL ICU18IN0 (0x1040) 8 - PORTSEL FRT19TEXT (0x0C60) 7 - RESSEL FRT18TEXT (0x0C40) 6 - PORTSEL FRT17TEXT (0x0C20) 5 - RESSEL FRT16TEXT (0x0C00) 4 - CAN1_RX PORTSEL 3 - CAN0_RX PORTSEL 2 - PORTSEL RESSEL 1 Port Sel RESSEL PORTSEL PPGGRP17R PPGGRP17_ LTTRG1 RLTTRG1 (0x2C28) 0 Document Number: 002-05677 Rev. *C Page 48 of 423 CY9DF125 - Atlas-L Table 20. Resource Input Source Table (RICFG1) (Continued) Source for resource input Register (offset) Resource Input RESSEL[3:0]/ PORTSEL[3:0] RESSEL ICU18IN1 (0x1042) ICU18FRTSE ICU18_FRTS L (0x1044) EL - - - - - - - - P0_47 (143) P2_37 (157) P2_45 (165) P3_05 (56) P3_18 (85) reserved reserved reserved FRT18 FRT16 reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - reserved P0_14(116) reserved reserved P1_25 (67) reserved reserved P0_42 (138) P2_38 (158) P2_46 (166) P3_06 (57) P3_19 (86) P3_31 (102) reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_15(117) reserved reserved P1_26 (104) reserved reserved P1_14 (22) P1_19 (29) P2_39 (159) P2_47 (167) P3_07 (58) P3_20 (87) P3_32 (103) reserved reserved FRT19 FRT17 ICU18_TOUT 0[15:0] reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - RLT4_TOT RLT5_TOT reserved reserved - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - RLT4_TOT RLT6_TOT reserved reserved - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved reserved reserved reserved reserved OCU17_MTR OCU16_CMP G 0OUT PORTSEL OCU17_FRT SEL 15 P0_41 (137) PORTSEL OCU17FRTS EL (0x1422) 14 - RESSEL RESSEL 13 reserved PORTSEL OCU17CMP0 OCU17_CMP EXT (0x1420) 0EXT 12 - PORTSEL OCU16OTD1 OCU16_OTD GM (0x1406) 1 GateMode 11 reserved RESSEL RESSEL 10 - PORTSEL OCU16OTD1 OCU16_OTD GATE 1 Gate (0x1404) 9 P1_24 (66) PORTSEL OCU16OTD0 OCU16_OTD GM (0x1402) 0 GateMode 8 - RESSEL RESSEL 7 reserved ICU19_IN1 OCU16OTD0 OCU16_OTD GATE 0 Gate (0x1400) 6 - RESSEL ICU19FRTSE ICU19_FRTS L (0x1064) EL 5 reserved ICU19_IN0 PORTSEL 4 - RESSEL ICU19IN1 (0x1062) 3 P0_13(115) RESSEL PORTSEL 2 - PORTSEL ICU19IN0 (0x1060) 1 reserved ICU18_IN1 PORTSEL 0 RESSEL PORTSEL Document Number: 002-05677 Rev. *C PPG64_PPG PPG65_PPG OCU17_OTD OCU17_OTD B B 0 1 PPG64_PPG PPG66_PPG OCU17_OTD OCU17_OTD B B 0 1 - - - - - - - - - - - - - - - - FRT17 FRT16 reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - Page 49 of 423 CY9DF125 - Atlas-L Table 20. Resource Input Source Table (RICFG1) (Continued) Source for resource input Register (offset) Resource Input OCU17OTD0 OCU17_OTD GATE 0 Gate (0x1424) RESSEL[3:0]/ PORTSEL[3:0] RESSEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RLT4_TOT RLT7_TOT reserved reserved - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - RLT4_TOT RLT8_TOT reserved reserved - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - - - - - - - - - PORTSEL OCU17OTD0 OCU17_OTD GM (0x1426) 0 GateMode RESSEL PORTSEL OCU17OTD1 OCU17_OTD GATE 1 Gate (0x1428) RESSEL PORTSEL OCU17OTD1 OCU17_OTD GM (0x142A) 1 GateMode RESSEL PORTSEL RESSEL USART6SCKI USART6_SC (0x1C00) KI PORTSEL USART6_SIN PORTSEL PPG64PPGA PPG64_PPG GATE A Gate (0x2400) PPG64PPGA PPG64_PPG GM (0x2402) A GateMode - - - - - - - - reserved P0_41 (137) P0_46 (142) reserved P1_13 (21) P3_01 (52) P3_05 (56) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_26(118) P0_28(122) reserved P0_40 (136) P0_45 (141) reserved P0_47 (143) P1_12 (20) P3_00 (49) P3_04 (55) P3_06 (57) reserved reserved reserved reserved reserved 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT RESSEL PORTSEL RESSEL PORTSEL PPG64PPGB PPG64_PPG GATE B Gate (0x2404) PPG64PPGB PPG64_PPG GM (0x2406) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG65PPGA PPG65_PPG GATE A Gate (0x2420) PPG64_PPG PPG68_PPG OCU16_OTD OCU16_OTD B B 0 1 P0_27(121) RESSEL USART6SIN (0x1C02) PPG64_PPG PPG67_PPG OCU16_OTD OCU16_OTD B B 0 1 RESSEL PORTSEL Document Number: 002-05677 Rev. *C - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 50 of 423 CY9DF125 - Atlas-L Table 20. Resource Input Source Table (RICFG1) (Continued) Source for resource input Register (offset) Resource Input PPG65PPGA PPG65_PPG GM (0x2422) A GateMode RESSEL[3:0]/ PORTSEL[3:0] RESSEL PORTSEL PPG65PPGB PPG65_PPG GATE B Gate (0x2424) PPG65PPGB PPG65_PPG GM (0x2426) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG66PPGA PPG66_PPG GATE A Gate (0x2440) PPG66PPGA PPG66_PPG GM (0x2442) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG66PPGB PPG66_PPG GATE B Gate (0x2444) PPG66PPGB PPG66_PPG GM (0x2446) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG67PPGA PPG67_PPG GATE A Gate (0x2460) PPG67PPGA PPG67_PPG GM (0x2462) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG67PPGB PPG67_PPG GATE B Gate (0x2464) PPG67PPGB PPG67_PPG GM (0x2466) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG68PPGA PPG68_PPG GATE A Gate (0x2480) RESSEL PORTSEL Document Number: 002-05677 Rev. *C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 51 of 423 CY9DF125 - Atlas-L Table 20. Resource Input Source Table (RICFG1) (Continued) Source for resource input Register (offset) Resource Input PPG68PPGA PPG68_PPG GM (0x2482) A GateMode RESSEL[3:0]/ PORTSEL[3:0] RESSEL PORTSEL PPG68PPGB PPG68_PPG GATE B Gate (0x2484) PPG68PPGB PPG68_PPG GM (0x2486) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG69PPGA PPG69_PPG GATE A Gate (0x24A0) PPG69PPGA PPG69_PPG GM (0x24A2) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG69PPGB PPG69_PPG GATE B Gate (0x24A4) PPG69PPGB PPG69_PPG GM (0x24A6) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG70PPGA PPG70_PPG GATE A Gate (0x24C0) PPG70PPGA PPG70_PPG GM (0x24C2) A GateMode RESSEL PORTSEL RESSEL PORTSEL PPG70PPGB PPG70_PPG GATE B Gate (0x24C4) PPG70PPGB PPG70_PPG GM (0x24C6) B GateMode RESSEL PORTSEL RESSEL PORTSEL PPG71PPGA PPG71_PPG GATE A Gate (0x24E0) RESSEL PORTSEL Document Number: 002-05677 Rev. *C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Page 52 of 423 CY9DF125 - Atlas-L Table 20. Resource Input Source Table (RICFG1) (Continued) Source for resource input Register (offset) Resource Input PPG71PPGA PPG71_PPG GM (0x24E2) A GateMode RESSEL[3:0]/ PORTSEL[3:0] RESSEL PORTSEL PPG71PPGB PPG71_PPG GATE B Gate (0x24E4) PPG71PPGB PPG71_PPG GM (0x24E6) B GateMode RESSEL PORTSEL RESSEL PORTSEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 1 RLT1_TOT RLT2_TOT RLT3_TOT RLT4_TOT RLT5_TOT RLT6_TOT RLT7_TOT - - - - - - - - - - - - - - - - Async Sync reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Port Sel RLT9_TOT RLT9_UFSE T RLT1_TOT PPG0_PPGA MCLKDIV4 RCCLKDIV4 reserved - - - - - - - - reserved P0_47 (143) reserved P1_11 (19) P2_43 (163) P3_28 (99) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT0_TOT RLT0_UFSE T RLT2_TOT PPG1_PPGA MCLKDIV4 RCCLKDIV4 reserved RICFG3 Table 21. Resource Input Source Table (RICFG3) Source for resource input Register (offset) Resource Input RESSEL[3:0]/P ORTSEL[3:0] RESSEL RLT0TIN (0x0800) RLT0_TIN PORTSEL Port Sel RESSEL RLT1TIN (0x0820) - - - - - - - - reserved P0_51 (147) reserved P1_15 (23) P2_39 (159) P3_24 (93) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Port Sel RLT1_TOT RLT1_UFSE T RLT3_TOT PPG2_PPGA MCLKDIV4 RCCLKDIV4 reserved - - - - - - - - P0_11(113) P0_43 (139) reserved P1_19 (29) P2_35 (155) P3_12 (63) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT2_TOT RLT2_UFSE T RLT4_TOT PPG3_PPGA MCLKDIV4 RCCLKDIV4 reserved RLT1_TIN PORTSEL RESSEL RLT2TIN (0x0840) RLT2_TIN PORTSEL Port Sel RESSEL RLT3TIN (0x0860) - - - - - - - - P0_26(122) P0_45 (141) P1_30 (45) reserved P1_08 (16) P3_04 (55) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Port Sel RLT3_TOT RLT3_UFSE T RLT5_TOT PPG4_PPGA - - - - - - - - P0_27(121) P0_46 (142) P1_31 (46) reserved P1_09 (17) P3_05 (56) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT3_TIN PORTSEL RESSEL RLT4TIN (0x0880) RLT4_TIN PORTSEL Document Number: 002-05677 Rev. *C USART0_SO USART6_SO T T reserved Page 53 of 423 CY9DF125 - Atlas-L Table 21. Resource Input Source Table (RICFG3) (Continued) Source for resource input Register (offset) Resource Input RESSEL[3:0]/P ORTSEL[3:0] RESSEL RLT5TIN (0x08A0) RLT5_TIN PORTSEL RLT6_TIN PORTSEL RESSEL RLT7TIN (0x08E0) RLT7_TIN PORTSEL RLT8_TIN PORTSEL RESSEL RLT9TIN (0x0920) RLT9_TIN PORTSEL UDC0_AIN1 PORTSEL UDC0_BIN0 PORTSEL 6 7 8 9 10 11 12 13 14 15 Port Sel RLT4_TOT RLT4_UFSE T RLT6_TOT PPG5_PPGA - - - - - - - - reserved P0_40 (136) reserved reserved P1_12 (20) P3_00 (49) P3_30 (101) reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT5_TOT RLT5_UFSE T RLT7_TOT USART0_SO USART6_SO T T UDC0_UDOT UDC0_UDOT PPG6_PPGA 0 1 reserved reserved - - - - - - - - reserved P0_41 (137) reserved P1_13 (21) P3_01 (52) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Port Sel RLT6_TOT RLT6_UFSE T RLT8_TOT PPG7_PPGA - - - - - - - - reserved reserved reserved P2_38 (158) P2_45 (165) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT7_TOT RLT7_UFSE T RLT9_TOT UDC0_UDOT UDC0_UDOT 0 1 UDC0_UDOT UDC0_UDOT PPG8_PPGA 0 1 reserved reserved - - - - - - - - reserved reserved reserved P2_37 (157) P2_41 (161) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Port Sel RLT8_TOT RLT8_UFSE T RLT0_TOT PPG9_PPGA - - - - - - - - reserved reserved reserved P2_36 (156) P2_42 (162) reserved reserved reserved UDC0_UDOT UDC0_UDOT 0 1 reserved reserved reserved reserved reserved reserved reserved reserved RLT3_TOT RLT7_TOT reserved reserved reserved reserved - - - - - - - - reserved reserved P1_34 (38) reserved P0_44 (140) P2_33 (151) P3_14 (81) P3_34 (69) P0_08(110) reserved reserved reserved reserved reserved reserved reserved Port Sel RLT1_TOT RLT4_TOT RLT7_TOT reserved reserved reserved reserved - - - - - - - - P0_12(114) reserved reserved reserved P0_48 (144) P2_37 (157) P3_04 (55) P3_18 (85) P3_38 (73) reserved reserved reserved reserved reserved reserved reserved Port Sel RLT1_TOT RLT4_TOT RLT8_TOT reserved reserved reserved reserved - - - - - - - - P0_09(111) reserved P1_35 (39) reserved P0_45 (141) P2_34 (154) P3_15 (82) P3_35 (70) reserved reserved reserved reserved reserved reserved reserved reserved RESSEL UDC0BIN0 (0x1008) 5 RLT0_TOT RESSEL UDC0AIN1 (0x1004) 4 Port Sel UDC0_AIN0 PORTSEL 3 P0_09(111) RESSEL UDC0AIN0 (0x1000) 2 Port Sel RESSEL RLT8TIN (0x0900) 1 Port Sel RESSEL RLT6TIN (0x08C0) 0 Document Number: 002-05677 Rev. *C Page 54 of 423 CY9DF125 - Atlas-L Table 21. Resource Input Source Table (RICFG3) (Continued) Source for resource input Register (offset) Resource Input RESSEL[3:0]/P ORTSEL[3:0] RESSEL UDC0BIN1 (0x100C) UDC0_BIN1 PORTSEL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Port Sel RLT2_TOT RLT5_TOT RLT8_TOT reserved reserved reserved reserved - - - - - - - - reserved reserved reserved P0_49 (145) P2_38 (158) P3_05 (56) P3_19 (86) P3_39 (74) reserved reserved reserved reserved reserved reserved reserved Port Sel RLT2_TOT RLT5_TOT RLT9_TOT - - - - - - - - P0_10(112) reserved P1_36 (40) reserved P0_46 (142) P2_35 (155) P3_16 (83) P3_36 (71) reserved reserved reserved reserved reserved reserved reserved reserved UDC0_ZIN0 PORTSEL Port Sel RESSEL UDC0ZIN1 (0x1014) 1 P0_13(115) RESSEL UDC0ZIN0 (0x1010) 0 RLT6_TOT RLT9_TOT PPG3_PPG A PPG3_PPG PPG0_PPGA PPG1_PPGA PPG2_PPGA A - - - - - - - - P0_14(116) reserved reserved reserved P0_50 (146) P2_39 (159) P3_06 (57) P3_20 (87) P3_40 (75) reserved reserved reserved reserved reserved reserved reserved UDC0_ZIN1 PORTSEL RLT3_TOT PPG0_PPGA PPG1_PPGA PPG2_PPGA RICFG4 Table 22. Resource Input Source Table (RICFG4) Register (offset) Resource Input RESSEL I2S0ECLK (0x1000) Source for resource input RESSEL[3:0] /PORTSEL[3: 0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Port Sel SPECIAL0_C LK_PERI1 reserved reserved reserved reserved reserved reserved - - - - - - - - P0_12(114) reserved reserved P1_24 (66) P2_32 (150) P2_36 (156) P2_40 (160) P3_33 (68) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_15(117) reserved reserved P2_35 (155) P2_39 (159) P2_43 (163) P3_36 (71) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_13(115) reserved reserved P2_33 (151) P2_37 (157) P2_41 (161) P3_34 (69) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_14(116) reserved reserved P2_34 (154) P2_38 (158) P2_42 (162) P3_35 (70) reserved reserved reserved reserved reserved reserved reserved reserved reserved I2S0_ECLK PORTSEL RESSEL I2S0SCKI (0x1004) I2S0_SCKI PORTSEL RESSEL I2S0SDI (0x1008) I2S0_SDI PORTSEL RESSEL I2S0WSI (0x100C) I2S0_WSI PORTSEL Document Number: 002-05677 Rev. *C Page 55 of 423 CY9DF125 - Atlas-L Table 22. Resource Input Source Table (RICFG4) (Continued) Register (offset) Resource Input RESSEL I2S1ECLK (0x1020) Source for resource input RESSEL[3:0] /PORTSEL[3: 0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Port Sel SPECIAL0_C LK_PERI1 reserved reserved reserved reserved reserved reserved - - - - - - - - P0_12(114) reserved reserved P1_24 (66) P2_32 (150) P2_36 (156) P2_44 (164) P3_37 (72) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_15(117) reserved P1_27 (105) P2_35 (155) P2_39 (159) P2_47 (167) P3_40 (75) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_13(115) reserved P1_25 (67) P2_33 (151) P2_37 (157) P2_45 (165) P3_38 (73) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_14(116) reserved P1_26 (104) P2_34 (154) P2_38 (158) P2_46 (166) P3_39 (74) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_11(113) P0_47 (143) P1_11 (19) P2_35 (155) P2_43 (163) P3_28 (99) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_10(112) P0_46 (142) P1_10 (18) P2_34 (154) P2_42 (162) P3_27 (98) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P09(111) P0_45 (141) P1_09 (17) P2_33 (151) P2_41 (161) P3_26 (97) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_13(114) P0_48 (144) P3_29 (100) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_14(115) P0_50 (146) P3_30 (101) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved I2S1_ECLK PORTSEL RESSEL I2S1SCKI (0x1024) I2S1_SCKI PORTSEL RESSEL I2S1SDI (0x1028) I2S1_SDI PORTSEL RESSEL I2S1WSI (0x102C) I2S1_WSI PORTSEL RESSEL SPI0CLKI (0x1C00) SPI0_CLKI PORTSEL RESSEL SPI0DATA0I SPI0_DATA0I (0x1C04) PORTSEL RESSEL SPI0DATA1I SPI0_DATA1I (0x1C08) PORTSEL RESSEL SPI0DATA2I SPI0_DATA2I (0x1C0C) PORTSEL RESSEL SPI0DATA3I SPI0_DATA3I (0x1C10) PORTSEL Document Number: 002-05677 Rev. *C Page 56 of 423 CY9DF125 - Atlas-L Table 22. Resource Input Source Table (RICFG4) (Continued) Register (offset) Resource Input SPI0MSTART SPI0_MSTAR (0x1C14) T Source for resource input RESSEL[3:0] /PORTSEL[3: 0] RESSEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RLT0_TOT RLT3_TOT RLT6_TOT RLT9_TOT reserved reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - reserved P0_08(110) P0_44 (140) P1_08 (16) P2_32 (150) P2_40 (160) P3_25 (96) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P0_51 (147) P1_15 (23) P2_39 (159) P2_43 (163) P3_24 (93) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P0_50 (146) P1_14 (22) P2_38 (158) P2_42 (162) P3_23 (92) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P0_49 (145) P1_13 (21) P2_37 (157) P2_41 (161) P3_22 (91) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P2_32 (150) P3_19 (86) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P2_33 (151) P3_20 (87) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved PORTSEL RESSEL SPI0SSI (0x1C18) SPI0_SSI PORTSEL RESSEL SPI1CLKI (0x1C20) SPI1_CLKI PORTSEL RESSEL SPI1DATA0I SPI1_DATA0I (0x1C24) PORTSEL RESSEL SPI1DATA1I SPI1_DATA1I (0x1C28) PORTSEL RESSEL SPI1DATA2I SPI1_DATA2I (0x1C2C) PORTSEL RESSEL SPI1DATA3I SPI1_DATA3I (0x1C30) PORTSEL SPI1MSTART SPI1_MSTAR (0x1C34) T RESSEL RLT3_TOT RLT6_TOT RLT9_TOT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - reserved reserved P0_48 (144) P1_12 (20) P2_36 (156) P2_40 (160) P3_21 (88) reserved reserved reserved reserved reserved reserved reserved reserved reserved RESSEL SPI1_SSI PORTSEL PPG64_PPG OCU16_OTD B 0 RLT0_TOT PORTSEL SPI1SSI (0x1C38) PPG64_PPG OCU16_OTD B 0 Document Number: 002-05677 Rev. *C Page 57 of 423 CY9DF125 - Atlas-L Table 22. Resource Input Source Table (RICFG4) (Continued) Register (offset) Resource Input Source for resource input RESSEL[3:0] /PORTSEL[3: 0] RESSEL SPI2CLKI (0x1C40) SPI2_CLKI PORTSEL PORTSEL PORTSEL PORTSEL PORTSEL SPI2MSTART SPI2_MSTAR (0x1C54) T RESSEL PORTSEL 6 7 8 9 10 11 12 13 14 15 - - - - - - - - - - - - - - P1_19 (29) P2_35 (155) P2_39 (159) P3_12 (63) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_10(112) P0_42 (138) P1_18 (28) P2_34 (154) P2_38 (158) P3_11 (62) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_09(111) P0_41 (137) P1_17 (27) P2_33 (151) P2_37 (157) P3_10 (61) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_44 (140) P3_13 (80) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_45 (141) P3_14 (81) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved RLT0_TOT RLT3_TOT RLT6_TOT RLT9_TOT reserved reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - reserved P0_08(110) P0_40 (136) P1_16 (26) P2_32 (150) P2_36 (156) P3_09 (60) reserved reserved reserved reserved reserved reserved reserved reserved reserved RESSEL SPI2SSI 5 P0_43 (139) PORTSEL SPI2SSI (0x1C58) 4 - RESSEL SPI2DATA3I SPI2_DATA3I (0x1C50) 3 P0_11(113) RESSEL SPI2DATA2I SPI2_DATA2I (0x1C4C) 2 - RESSEL SPI2DATA1I SPI2_DATA1I (0x1C48) 1 reserved RESSEL SPI2DATA0I SPI2_DATA0I (0x1C44) 0 Document Number: 002-05677 Rev. *C PPG64_PPG OCU16_OTD B 0 Page 58 of 423 CY9DF125 - Atlas-L RICFG7 Table 23. Resource Input Source Table (RICFG7) Register (offset) Resource Input Source for resource input RESSEL[3:0] /PORTSEL [3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - - - - - - - - - - - - - - - - reserved reserved P0_63 (149) P1_08 (16) P3_08 (59) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P1_33 (48) reserved P1_09 (17) P3_33 (68) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved reserved P1_10 (18) P3_03 (54) P3_10 (61) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_08(110) P0_44 (140) P1_11 (19) P1_08 (16) P2_32 (150) P2_40 (160) P3_25 (96) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P0_48 (144) P1_12 (20) P2_36 (156) P2_40 (160) P3_21 (88) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_08(110) P0_40 (136) P1_13 (21) P1_16 (26) P2_32 (150) P2_36 (156) P3_09 (60) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_14(116) reserved reserved P1_14 (22) P2_34 (154) P2_38 (158) P2_42 (162) P3_35 (70) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_14(116) reserved P1_26 (104) P1_15 (23) P2_34 (154) P2_38 (158) P2_46 (166) P3_39 (74) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved reserved P0_42 (138) P0_48 (144) P0_51 (147) P1_34 (38) P1_00 (6) P2_41 (161) P2_44 (164) P2_46 (166) reserved reserved reserved reserved reserved RESSEL EIC0INT00 (0x1000) EIC0_INT00 PORTSEL RESSEL EIC0INT01 (0x1004) EIC0_INT01 PORTSEL RESSEL EIC0INT02 (0x1008) EIC0_INT02 PORTSEL RESSEL EIC0INT03 (0x100C) EIC0_INT03 PORTSEL RESSEL EIC0INT04 (0x1010) EIC0_INT04 PORTSEL RESSEL EIC0INT05 (0x1014) EIC0_INT05 PORTSEL RESSEL EIC0INT06 (0x1018) EIC0_INT06 PORTSEL RESSEL EIC0INT07 (0x101C) EIC0_INT07 PORTSEL RESSEL EIC0INT08 (0x1020) EIC0_INT08 PORTSEL Document Number: 002-05677 Rev. *C Page 59 of 423 CY9DF125 - Atlas-L Table 23. Resource Input Source Table (RICFG7) (Continued) Register (offset) Resource Input Source for resource input RESSEL[3:0] /PORTSEL [3:0] RESSEL EIC0INT09 (0x1024) EIC0_INT09 PORTSEL EIC0_INT10 PORTSEL EIC0_INT11 PORTSEL EIC0_INT12 PORTSEL EIC0_INT13 PORTSEL EIC0_INT14 PORTSEL EIC0_INT15 PORTSEL EIC0_INT16 PORTSEL EIC0_INT17 PORTSEL 8 9 10 11 12 13 14 15 - - - - - - - - - - - - - P0_48 (144) P0_50 (146) P1_36 (40) P1_02 (8) P2_41 (161) P2_45 (165) P2_47 (167) reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved reserved P0_42 (138) P0_49 (145) P0_50 (146) P1_38 (42) P1_16 (26) P2_40 (160) P2_45 (165) P2_46 (166) reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_26(118) reserved reserved P0_40 (136) P0_45 (141) P1_30 (45) reserved P0_42 (138) P1_08 (16) P3_00 (49) P3_02 (53) P3_04 (55) reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_26(118) P0_28(122) reserved P0_40 (136) P0_45 (141) reserved P0_47 (143) P1_12 (20) P3_00 (49) P3_04 (55) P3_06 (57) reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P1_37 (41) P1_02 (8) P1_16 (26) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved reserved P1_17 (27) reserved P3_11 (62) P3_34 (69) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_41 (137) reserved P1_18 (28) reserved P3_12 (63) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P0_46 (142) reserved P1_19 (29) reserved P3_13 (80) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - RESSEL EIC0INT17 (0x1044) 7 P0_43 (139) RESSEL EIC0INT16 (0x1040) 6 - RESSEL EIC0INT15 (0x103C) 5 reserved RESSEL EIC0INT14 (0x1038) 4 - RESSEL EIC0INT13 (0x1034) 3 reserved RESSEL EIC0INT12 (0x1030) 2 - RESSEL EIC0INT11 (0x102C) 1 reserved RESSEL EIC0INT10 (0x1028) 0 - - - - - - - - reserved P0_47 (143) reserved P1_20 (30) reserved P3_14 (81) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Document Number: 002-05677 Rev. *C Page 60 of 423 CY9DF125 - Atlas-L Table 23. Resource Input Source Table (RICFG7) (Continued) Register (offset) Resource Input Source for resource input RESSEL[3:0] /PORTSEL [3:0] RESSEL EIC0INT18 (0x1048) EIC0_INT18 PORTSEL EIC0_INT19 PORTSEL EIC0_INT20 PORTSEL EIC0_INT21 PORTSEL EIC0_INT22 PORTSEL EIC0_INT23 PORTSEL EIC0_INT24 PORTSEL EIC0_INT25 PORTSEL EIC0_INT26 PORTSEL 8 9 10 11 12 13 14 15 - - - - - - - - - - - - - reserved P3_15 (82) P3_36 (71) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_09(111) P1_24 (66) reserved P1_22 (32) reserved P3_16 (83) P3_37 (72) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_10(112) P1_25 (67) reserved P1_23 (33) reserved P3_17 (84) P3_22 (91) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_11(113) P1_27 (105) reserved reserved reserved P3_18 (85) P3_23 (92) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_12(114) P1_28 (106) reserved reserved reserved P3_19 (86) P3_24 (93) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_13(115) P1_29 (107) reserved reserved reserved P3_20 (87) P3_38 (73) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_15(117) P1_31 (46) P0_62 (148) reserved reserved P3_26 (97) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved P1_32 (47) P1_00 (6) reserved reserved P3_27 (98) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - RESSEL EIC0INT26 (0x1068) 7 P1_21 (31) RESSEL EIC0INT25 (0x1064) 6 - RESSEL EIC0INT24 (0x1060) 5 reserved RESSEL EIC0INT23 (0x105C) 4 - RESSEL EIC0INT22 (0x1058) 3 reserved RESSEL EIC0INT21 (0x1054) 2 - RESSEL EIC0INT20 (0x1050) 1 reserved RESSEL EIC0INT19 (0x104C) 0 - - - - - - - - reserved P1_35 (39) P1_01 (7) reserved reserved P2_33 (151) P3_28 (99) reserved reserved reserved reserved reserved reserved reserved reserved reserved Document Number: 002-05677 Rev. *C Page 61 of 423 CY9DF125 - Atlas-L Table 23. Resource Input Source Table (RICFG7) (Continued) Register (offset) Resource Input Source for resource input RESSEL[3:0] /PORTSEL [3:0] RESSEL EIC0INT27 (0x106C) EIC0_INT27 PORTSEL EIC0_INT28 PORTSEL EIC0_INT29 PORTSEL EIC0_INT30 PORTSEL EIC0_INT31 PORTSEL EIC0_NMI PORTSEL 5 6 7 8 9 10 11 12 13 14 15 - - - - - - - - - - - - - - P1_03 (9) reserved reserved P3_01 (52) P3_29 (100) P3_31 (102) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P1_04 (10) reserved reserved P3_02 (53) P3_30 (101) P3_32 (103) reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - P0_27(121) reserved P1_05 (11) reserved P2_35 (155) P3_05 (56) P3_40 (75) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P1_06 (12) reserved P2_37 (157) P3_06 (57) P3_41 (76) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - - - - - - - - - reserved reserved P1_07 (13) reserved P2_39 (159) P3_07 (58) P3_42 (77) reserved reserved reserved reserved reserved reserved reserved reserved reserved - - - - - - - - RESSEL EIC0NMI (0x1080) 4 - RESSEL EIC0INT31 (0x107C) 3 reserved RESSEL EIC0INT30 (0x1078) 2 - RESSEL EIC0INT29 (0x1074) 1 reserved RESSEL EIC0INT28 (0x1070) 0 - - - - - - - - reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Document Number: 002-05677 Rev. *C Page 62 of 423 CY9DF125 - Atlas-L RICFG8 Table 24. Resource Input Source Table (RICFG8) Source for resource input Register (offset) HSSPI0MSTART (0x0000) Resource Input HSSPI0_MSTAR T RESSEL[3:0]/ PORTSEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RLT0_TOT RLT3_TOT RLT6_TOT RLT9_TOT PPG64_PPGB OCU16_OTD0 reserved reserved - - - - - - - - - - - - - - - - RESSEL PORTSEL Document Number: 002-05677 Rev. *C Page 63 of 423 CY9DF125 - Atlas-L I/O Pin Types Table 25. Pin Circuit type of QPF-240 (Continued) Table 25. Pin Circuit type of QPF-240 Pin Number IO_TYPE SMC_IO Pin Number IO_TYPE 39 1 supply 40 supply 2 supply 41 supply 3 supply 42 supply 4 supply 43 supply 5 supply 44 supply 6 SMC_IO 45 supply 7 SMC_IO 46 supply 8 SMC_IO 47 supply 9 SMC_IO 48 BIDI33_IO 10 SMC_IO 49 BIDI33_IO 11 SMC_IO 50 BIDI33_IO 12 SMC_IO 51 BIDI33_IO 13 SMC_IO 52 BIDI33_IO 14 SMC_IO 53 BIDI33_IO 15 SMC_IO 54 BIDI33_IO 16 supply 55 BIDI33_IO 17 supply 56 BIDI33_IO 18 supply 57 supply 19 supply 58 supply 20 SMC_IO 59 supply 21 SMC_IO 60 supply 22 SMC_IO 61 NA 23 SMC_IO 62 BIDI33_IO 24 SMC_IO 63 BIDI33_IO 25 SMC_IO 64 BIDI33_IO 26 SMC_IO 65 BIDI33_IO 27 SMC_IO 66 BIDI33_IO 28 supply 67 BIDI33_IO 29 supply 68 BIDI33_IO 30 supply 69 supply 31 supply 70 supply 32 SMC_IO 71 supply 33 SMC_IO 72 supply 34 SMC_IO 73 BIDI33_IO 35 SMC_IO 74 BIDI33_IO 36 SMC_IO 75 BIDI33_IO 37 SMC_IO 76 BIDI33_IO 38 SMC_IO 77 BIDI33_IO Document Number: 002-05677 Rev. *C Page 64 of 423 CY9DF125 - Atlas-L Table 25. Pin Circuit type of QPF-240 (Continued) Table 25. Pin Circuit type of QPF-240 (Continued) Pin Number IO_TYPE Pin Number IO_TYPE 78 BIDI33_IO 116 BIDI33_IO 79 BIDI33_IO 117 BIDI33_IO 80 BIDI33_IO 118 BIDI33_IO 81 BIDI33_IO 119 BIDI33_IO 82 BIDI33_IO 120 NA 83 BIDI33_IO 121 supply 84 BIDI33_IO 122 supply 85 supply 123 BIDI33_IO 86 supply 124 BIDI33_IO 87 supply 125 BIDI33_IO 88 supply 126 BIDI33_IO 89 BIDI33_IO 127 supply 90 BIDI33_IO 128 BIDI33_IO 91 BIDI33_IO 129 supply 92 BIDI33_IO 130 BIDI33_IO 93 BIDI33_IO 131 BIDI33_IO 94 BIDI33_IO 132 BIDI33_IO 95 BIDI33_IO 133 BIDI33_IO 96 BIDI33_IO 134 BIDI33_IO 96 BIDI33_IO 135 BIDI33_IO 97 BIDI33_IO 136 BIDI33_IO 98 BIDI33_IO 137 supply 99 BIDI33_IO 138 supply 100 BIDI33_IO 139 BIDI33_IO 101 supply 140 BIDI33_IO 102 supply 141 BIDI33_IO 103 BIDI33_IO 142 BIDI33_IO 104 BIDI33_IO 143 BIDI33_IO 105 BIDI33_IO 144 BIDI33_IO 106 BIDI33_IO 145 BIDI33_IO 107 BIDI33_IO 146 supply 108 BIDI33_IO 147 supply 109 BIDI33_IO 148 BIDI33_IO 110 BIDI33_IO 149 BIDI33_IO 111 BIDI33_IO 150 BIDI33_IO 112 BIDI33_IO 151 BIDI33_IO 113 supply 152 BIDI33_IO 114 supply 153 BIDI33_IO 115 BIDI33_IO 154 BIDI33_IO Document Number: 002-05677 Rev. *C Page 65 of 423 CY9DF125 - Atlas-L Table 25. Pin Circuit type of QPF-240 (Continued) Table 25. Pin Circuit type of QPF-240 (Continued) Pin Number IO_TYPE Pin Number IO_TYPE 155 BIDI33_IO 194 BIDI50_IO 156 BIDI33_IO 195 BIDI50_IO 157 BIDI33_IO 196 BIDI50_IO 158 supply 197 BIDI50_IO 159 supply 198 BIDI50_IO 160 supply 199 BIDI50_IO 161 BIDI33_IO 200 BIDI50_IO 162 BIDI33_IO 201 BIDI50_IO 163 BIDI33_IO 202 I2C_IO 164 supply 203 I2C_IO 165 NA 204 BIDI50_IO 166 supply 205 BIDI50_IO 167 X1_IO 206 NA 168 X0_IO 207 supply 169 supply 208 supply 170 supply 209 supply 171 X0A_IO 210 supply 172 X1A_IO 211 BIDI50_IO 173 MODE_IO 212 BIDI50_IO 174 NA 213 BIDI50_IO 175 MODE_IO 214 BIDI50_IO 176 supply 215 BIDI50_IO 177 supply 216 NA 178 NA 217 BIDI50_IO 179 NA 218 BIDI50_IO 180 NA 219 BIDI50_IO 181 NA 220 BIDI50_IO 182 NA 221 BIDI50_IO 183 NA 222 BIDI50_IO 184 supply 223 BIDI50_IO 185 supply 242 BIDI50_IO 186 supply 225 BIDI50_IO 187 supply 226 supply 188 supply 227 supply 189 supply 228 supply 190 BIDI50_IO 229 supply 191 BIDI50_IO 230 JTAGO 192 BIDI50_IO 231 JTAGIUP 193 BIDI50_IO 232 JTAGIUP Document Number: 002-05677 Rev. *C Page 66 of 423 CY9DF125 - Atlas-L Table 25. Pin Circuit type of QPF-240 (Continued) Table 26. Pin Circuit type of QFP-176 (Continued) Pin Number IO_TYPE Pin Number IO_TYPE 233 supply 29 SMC_IO 234 supply 30 SMC_IO 235 supply 31 SMC_IO 236 supply 32 SMC_IO 237 JTAGIUP 33 SMC_IO 238 JTAGIDN 34 supply 239 NA 35 supply 240 NA 36 supply 37 supply 38 BIDI33_IO 39 BIDI33_IO 40 BIDI33_IO 41 BIDI33_IO 42 BIDI33_IO 43 supply Table 26. Pin Circuit type of QFP-176 Pin Number IO_TYPE 1 supply 2 supply 3 supply 4 supply 5 supply 6 SMC_IO 7 SMC_IO 8 SMC_IO 9 SMC_IO 10 SMC_IO 11 SMC_IO 12 SMC_IO 13 SMC_IO 14 supply 15 supply 16 SMC_IO 17 SMC_IO 18 SMC_IO 19 SMC_IO 20 SMC_IO 21 SMC_IO 22 SMC_IO 23 SMC_IO 24 supply 25 supply 26 SMC_IO 27 SMC_IO 28 SMC_IO Document Number: 002-05677 Rev. *C 44 supply 45 BIDI33_IO 46 BIDI33_IO 47 BIDI33_IO 48 BIDI33_IO 49 BIDI33_IO 50 supply 51 supply 52 BIDI33_IO 53 BIDI33_IO 54 BIDI33_IO 55 BIDI33_IO 56 BIDI33_IO 57 BIDI33_IO 58 BIDI33_IO 59 BIDI33_IO 60 BIDI33_IO 61 BIDI33_IO 62 BIDI33_IO 63 BIDI33_IO 64 supply 65 supply 66 BIDI33_IO 67 BIDI33_IO Page 67 of 423 CY9DF125 - Atlas-L Table 26. Pin Circuit type of QFP-176 (Continued) Table 26. Pin Circuit type of QFP-176 (Continued) Pin Number IO_TYPE Pin Number IO_TYPE 68 BIDI33_IO 107 BIDI33_IO 69 BIDI33_IO 108 supply 70 BIDI33_IO 109 supply 71 BIDI33_IO 110 BIDI33_IO 72 BIDI33_IO 111 BIDI33_IO 73 BIDI33_IO 112 BIDI33_IO 74 BIDI33_IO 113 BIDI33_IO 75 BIDI33_IO 114 BIDI33_IO 76 BIDI33_IO 115 BIDI33_IO 77 BIDI33_IO 116 BIDI33_IO 78 supply 117 BIDI33_IO 79 supply 118 BIDI33_IO 80 BIDI33_IO 119 supply 81 BIDI33_IO 120 supply 82 BIDI33_IO 121 BIDI33_IO 83 BIDI33_IO 122 BIDI33_IO 84 BIDI33_IO 123 supply 85 BIDI33_IO 124 supply 86 BIDI33_IO 125 X1_IO 87 BIDI33_IO 126 X0_IO 88 BIDI33_IO 127 supply 89 supply 128 X0A_IO 90 supply 129 X1A_IO 91 BIDI33_IO 130 MODE_IO 92 BIDI33_IO 131 MODE_IO 93 BIDI33_IO 132 supply 94 supply 133 supply 95 supply 134 supply 96 BIDI33_IO 135 supply 97 BIDI33_IO 136 BIDI50_IO 98 BIDI33_IO 137 BIDI50_IO 99 BIDI33_IO 138 BIDI50_IO 100 BIDI33_IO 139 BIDI50_IO 101 BIDI33_IO 140 BIDI50_IO 102 BIDI33_IO 141 BIDI50_IO 103 BIDI33_IO 142 BIDI50_IO 104 BIDI33_IO 143 BIDI50_IO 105 BIDI33_IO 144 BIDI50_IO 106 BIDI33_IO 145 BIDI50_IO Document Number: 002-05677 Rev. *C Page 68 of 423 CY9DF125 - Atlas-L Table 26. Pin Circuit type of QFP-176 (Continued) Pin Number IO_TYPE 146 BIDI50_IO 147 BIDI50_IO 148 I2C_IO 149 I2C_IO 150 BIDI50A_IO 151 BIDI50A_IO 152 supply 153 supply 154 BIDI50A_IO 155 BIDI50A_IO 156 BIDI50A_IO 157 BIDI50A_IO 158 BIDI50A_IO 159 BIDI50A_IO 160 BIDI50_IO 161 BIDI50_IO 162 BIDI50_IO 163 BIDI50_IO 164 BIDI50_IO 165 BIDI50_IO 166 BIDI50_IO 167 BIDI50_IO 168 supply 169 supply 170 BIDI50_IO 171 BIDI50_IO 172 BIDI50_IO 173 supply 174 supply 175 BIDI50_IO 176 BIDI50_IO Document Number: 002-05677 Rev. *C Page 69 of 423 CY9DF125 - Atlas-L IO Circuit Types Table 27. IO Circuit Type Type Circuit Remarks High-speed oscillation circuit: Programmable between oscillation mode (external crystal or resonator connected to X0/X1pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin X1 MAINOSC 0 R Xout 1 FCI X0 Note The built-in feedback resistor 'R' (1MOhm typical) is located between X0 and X1 and will be disabled in the Fast External Clock Input Mode (FCI). FCI or osc disable X1A SUBOSC Xout Low-speed oscillation circuit R X0A osc disable R JTAGIDN Hysteresis inputs Pull−down Resistor JTAGIUP Pull−up Resistor R Document Number: 002-05677 Rev. *C ■ TTL level input pin ■ Pull-down resistor value: approx. 50 k ■ TTL level input pin ■ Pull-up resistor value: approx. 50 k Hysteresis inputs Page 70 of 423 CY9DF125 - Atlas-L Table 27. IO Circuit Type (Continued) Type Circuit Remarks Pout JTAGO CMOS level output Nout AVRH5 MODE Document Number: 002-05677 Rev. *C ■ A/D converter ref+ (AVRH5) power supply input pin with protection circuit ■ Flash devices do not have a protection circuit against VDP5 for pins AVRH5 CMOS Hysteresis input pin Page 71 of 423 CY9DF125 - Atlas-L Table 27. IO Circuit Type (Continued) Type Circuit Remarks Pull−up control ■ Pout Nout Pull−down control R BIDI50 Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input ODR[1:0] IOL IOH 00 +1 mA -1 mA 01 +2 mA -2 mA 10 +5 mA -5 mA 11 +2 mA -2 mA ■ Hysteresis input with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown function ■ CMOS input with input shutdown function Automotive input TTL input CMOS input CMOS level output (programmable) PIL[1:0] Input Buffer Levels 00 Hysteresis 20% / 80% 01 Automotive 50% / 80% 10 TTL 0.7V / 2V 11 CMOS 20% / 80% ■ Programmable pull-up and pull-down resistor; 50 k approx. ■ Analog input ■ CMOS level output Analog input BIDI33 IOL IOH  +1 mA -12 mA ■ Hysteresis input with input shutdown function ■ TTL input with input shutdown function ■ Document Number: 002-05677 Rev. *C ODR[1:0] PIL[1:0] Input Buffer Levels 00 Hysteresis 20% / 80% 10 TTL 0.8V / 2V Programmable pull-up and pull-down resistor; 33 k approx. Page 72 of 423 CY9DF125 - Atlas-L Table 27. IO Circuit Type (Continued) Type Circuit Remarks ■ TTL33 CMOS level output (programmable) ODR[1:0] IOL IOH 00 +2 mA -2 mA 01 +5 mA -5 mA 10 +10 mA -10 mA 11 +20 mA -20 mA ■ Hysteresis input with input shutdown function ■ TTL input with input shutdown function PIL[1:0] Input Buffer Levels 00 Hysteresis 20% / 80% 10 TTL 0.8V / 2V ■ Programmable pull-up and pull-down resistor; 33 k approx. ■ CMOS level output (programmable) Pull−up control Pout Nout Pull−down control R SMC Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input IOL IOH 00 +1 mA -1 mA 01 +2 mA -2 mA 10 +30 mA -30 mA 11 +5 mA -5 mA ■ Hysteresis input with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown function ■ CMOS input with input shutdown function Automotive input TTL input CMOS input ODR[1:0] ■ PIL[1:0] Input Buffer Levels 00 Hysteresis 20% / 80% 01 Automotive 50% / 80% 10 TTL 0.8V / 2V 11 CMOS 20% / 80% Programmable pull-up and pull-down resistor; 50 k approx. Analog input Document Number: 002-05677 Rev. *C Page 73 of 423 CY9DF125 - Atlas-L Table 27. IO Circuit Type (Continued) Type Circuit Remarks ■ CMOS level output (programmable) ODR[1:0] I2C_enable I2C IOL IOH 00 0 +1 mA -1 mA 01 0 +2 mA -2 mA 10 0 +5 mA -5 mA 11 0 +2 mA -2 mA * 1 +3 mA Pseudo Open Drain[1] ■ Hysteresis input with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown function ■ CMOS input with input shutdown function ■ I2C_enable is high, when the corresponding PCFGRxxx_POF value is set to I2C function and the I2C interface module is enabled. Note 1. For Pseudo Open Drain output logic value “1”, Push/Pull CMOS driver is switched to HIZ state. ■ Document Number: 002-05677 Rev. *C PIL[1:0] Input Buffer Levels 00 Hysteresis 30% / 70% 01 Automotive 50% / 80% 10 TTL 0.8V / 2V 11 CMOS 30% / 70% Programmable pull-up and pull-down resistor; 50 k approx. Page 74 of 423 CY9DF125 - Atlas-L Package Diagram D % $ $  / , $ 7 ( '  ( ( 6  &  ( 1 $ / 3  * 1 , 7 $ ( 6  7 $  ' ( 1 , 0 5 ( 7 ( '  ( %  2 7    ' ( 1 , 0 5 ( 7 (  ' 1  2 ( , 5 6 $ 8  5 ' 7 1 2 $  5 + 3 &  7 ' $ /( 2'0 6 0, 6, ( 0 (  '5' 83/ /2 &P0 1P , (  7 ' 2 8 1/ 6& , 2 1 '1, 2 ,   ( (6  8' ' 51+ 17  $( $2  1   '5'$ / 3 6 6 ( 3 1 1/  0 2%2 ,8 ,$6 6 7 1:1$ (2(' 0/0 / ,7 ,$ '$ '           c 0.09 D1 24.00 BSC 0.50 BSC E 26.00 BSC 0.45 0.60 0.75 L1 0.30 0.50 0.70 ș 0° 5 $E1 % 2 0' $( ' '(( &7 ( ;$ +( & 7 2 2  / 7 1 2( ,+% 7 6  7 8' ,2 5: 1 7 2' 1 5$$ 3(& / 5 5  ( $ (+ %7 %7 0 0 2 $($2 '6') 8   (  ' $ ' P$ & P ( 8 / /7  &2 ( 11+ ,7 / 1  7 /  2$$5 + 2 1+7  6( 6 6 (58 , 262' ' 0$ 1 5 E 2 • if tSCYCI = (2*k+1)*tCLK_DBG_PD2, then N = k+1, where k is an integer > 1 Document Number: 002-05677 Rev. *C Page 351 of 423 CY9DF125 - Atlas-L Table 56. Examples tSCYCI N 4*tCLK_PERI0_PD 2 5*tCLK_PERI0_PD, 6*tCLK_PERI0_PD 3 7*tCLK_PERI0_PD, 8*tCLK_PERI0_PD 4 …. …. I2C Timing (TA = -40C to 105C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 4.5V to 5.5V[20], DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V) Table 57. I2C Timing Parameter Standard-mode Symbol Fast-mode Unit Min Max Min Max fSCL 0 100 0 400 kHz tHDSTA 4.0 – 0.6 – s “L” width of the SCL clock tLOW 4.7 – 1.3 – s “H” width of the SCL clock tHIGH 4.0 – 0.6 – s Set-up time for a repeated START condition SCLSDA tSUSTA 4.7 – 0.6 – s Data hold time SCLSDA tHDDAT 0 3.45 0 0.9 s Data set-up time SDA---SCL¦¦- tSUDAT 250 – 100 – ns Set-up time for STOP condition SCL--SDA- tSUSTO 4 – 0.6 – s tBUS 4.7 – 1.3 – s 20 + 0.1*Cb [18] 250 20 + 0.1*Cb [18] 250 ns SCL clock frequency Hold time (repeated) START condition SDASCL Bus free time between a STOP and START condition Output fall time from 0.7*VDP5 to 0.3*VDP5 with a bus capacitance from 10pF to 400pF tof Capacitive load for each bus line Cb – 400 – 50 pF Pulse width of spikes which will be suppressed by input noise filter tSP n/a n/a 0 1*tCLK_DBG_PD2[19] ns Notes 17. For use at over 100 kHz, set the CLK_DBG_PD2 to at least 6 MHz. 18. Cb = capacitance of one bus line in pF. 19. tCLK_DBG_PD2 is the cycle time of the peripheral clock CLK_DBG_PD2 20. I2C spec only guaranteed at VDP5 = 4.5V to 5.5V. Document Number: 002-05677 Rev. *C Page 352 of 423 CY9DF125 - Atlas-L Figure 12. I2C Timing HSSPI Timing (TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V) Table 58. HSSPI Interface Timing (Master Mode) Parameter Symbol HSSPI clock frequency Input setup time (HSSPIn_DATAi) TIS,DATA Value Min Typ Max Units – – 64 MHz 12.1 – – ns no clock retiming 5.6 – – ns with clock retiming 0 – – ns no clock retiming 1.5 – – ns with clock retiming Input hold time (HSSPIn_DATAi) TIH,DATA Output delay time (HSSPIn_DATAo) TOD,DATA – – 3.8 ns Output hold time (HSSPIn_DATAo) TOH,DATA 5 – – ns Output delay time (HSSPIn_SSELo) TOD,SSEL – – 5.05 ns Output hold time (HSSPIn_SSELo) TOH,SSEL 0 – – ns Document Number: 002-05677 Rev. *C Remarks Page 353 of 423 CY9DF125 - Atlas-L Figure 13. HSSPI Interface Timing Table 59. HSSPI Interface Timing (Slave Mode, No clock Retiming) Parameter Symbol HSSPI clock frequency Value Units Min Typ Max – – 25 MHz Input setup time (HSSPIn_DATAi) TIS,DATA 5 – – ns Input hold time (HSSPIn_DATAi) TIH,DATA 0 – – ns Input setup time (HSSPIn_SSELi) TIS,SSEL 8.2 – – ns Output hold time (HSSPIn_SSELi) TIH,SSEL 2 – – ns Output delay time (HSSPIn_DATAo) TOD,DATA – – 15.5 ns Output hold time (HSSPIn_SSELo) TOH,DATA 0 – – ns Document Number: 002-05677 Rev. *C Remarks Page 354 of 423 CY9DF125 - Atlas-L SPI Timing (TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V) For each SPI module, several combinations of I/O pins can be chosen for each SPI signal. The timing depends on the actual combination and is given below as separate values for each possible type of I/O-cell. When I/O/cells of different types are mixed, the worst case table, called “OVERALL SPI Interface timing” must be used. In Master Mode, using the clock retiming function improves the setup and hold times for input data. The usable maximum clock frequency depends on the transmission mode (Master to Slave / Slave to Master, using clock-retiming or not). An example for calculation is given below each table. Table 60. OVERALL SPI Interface Timing Parameter Symbol Input setup (SPIn_DATAi) time Input hold (SPIn_DATAi) time Output delay (SPIn_DATAo) time Output hold (SPIn_DATAo) time Input setup (SPIn_SSELi) time Input hold (SPIn_SSELi) time Output delay (SPIn_SSELo) time Output hold (SPIn_SSELo) time Master Mode, Master Mode, non-retimed clock retimed clock Slave Mode Unit Min Max Min Max Min Max TIS,DATA 25.3 – 8.2 – 8.1 – ns TIH,DATA -3.8[21] – 9.4 – 9.8 – ns TOD,DATA – 12.9 – 12.9 – 32.8 ns TOH,DATA -8.1[21] – -8.1[21] – 3.8 – ns TIS,SSEL – – – – 9.2 – ns TIH,SSEL – – – – 8.4 – ns TOD,SSEL – 12.9 – 12.9 – – ns TOH,SSEL -8.0[21] – -8.0[21] – – – ns Table 61. Example for Calculation of Maximum Frequencies for Communication of Master (Retimed Mode) and Slave Transmission Half Period Time Max. Frequency Unit From Master to Slave T/2 = TOD,DATA (Master) + TIS,DATA (Slave) 22.6 MHz From Slave to Master T/2 = TOD,DATA (Slave) + TIS,DATA (Master) 12.1 MHz Note 21. A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a sampling point that is outside the time interval given by Output hold time and Output delay time. Document Number: 002-05677 Rev. *C Page 355 of 423 CY9DF125 - Atlas-L Table 62. SPI Interface Timing for All Cells of Type BIDI33 Parameter Symbol Master Mode, Master Mode, Non-retimed Clock Retimed Clock Min Max Min Max Slave Mode Min Unit Max Input setup time (SPIn_DATAi) TIS,DATA 19.2 – 4.1 – 4.0 – ns Input hold time (SPIn_DATAi) TIH,DATA -3.8[22] – 4.5 – 4.7 – ns Output delay time (SPIn_DATAo) TOD,DATA – 7.9 – 7.9 – 22.7 ns Output hold time (SPIn_DATAo) [22] [22] TOH,DATA -3.6 – -3.6 – 3.8 – ns Input setup time (SPIn_SSELi) TIS,SSEL – – – – 4.2 – ns Input hold time (SPIn_SSELi) TIH,SSEL – – – – 2.7 – ns Output delay time (SPIn_SSELo) TOD,SSEL – 6.0 – 6.0 – – ns TOH,SSEL 1.3[22] – 1.3[22] – – – ns Output hold time (SPIn_SSELo) Table 63. Example for Calculation of Maximum Frequencies for Communication of Master (Retimed Mode) and Slave Half Period Time Max. Frequency Unit From Master to Slave Transmission T/2 = TOD,DATA (Master) + TIS,DATA (Slave) 42.0 MHz From Slave to Master T/2 = TOD,DATA (Slave) + TIS,DATA (Master) 18.6 MHz Note 22. A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a sampling point that is outside the time interval given by Output hold time and Output delay time. Document Number: 002-05677 Rev. *C Page 356 of 423 CY9DF125 - Atlas-L Table 64. SPI Interface Timing for All Cells of Type BIDI50 Parameter Symbol Master Mode, Master Mode, non-retimed clock retimed clock Slave Mode Min Max Min Max Min Max Unit Input setup time (SPIn_DATAi) TIS,DATA 24.7 – 5.0 – 5.0 – ns Input hold time (SPIn_DATAi) TIH,DATA -6.6[23] – 6.4 – 6.7 – ns Output delay time (SPIn_DATAo) TOD,DATA – 11.1 – 11.1 – 32.8 ns Output hold time (SPIn_DATAo) TOH,DATA -2.3[23] – -2.3[23] – 7.3 – ns Input setup time (SPIn_SSELi) TIS,SSEL – – – – 6.6 – ns Input hold time (SPIn_SSELi) TIH,SSEL – – – – 5.5 – ns Output delay time (SPIn_SSELo) TOD,SSEL – 10.0 – 10.0 – – ns Output hold time (SPIn_SSELo) TOH,SSEL 1.8 – 1.8 – – – ns Table 65. Example for Calculation of Maximum Frequencies for Communication of Master (Retimed Mode) and Slave Transmission Half Period Time Max. Frequency Unit From Master to Slave T/2 = TOD,DATA (Master) + TIS,DATA (Slave) 30.1 MHz From Slave to Master T/2 = TOD,DATA (Slave) + TIS,DATA (Master) 13.2 MHz Note 23. A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a sampling point that is outside the time interval given by Output hold time and Output delay time. Document Number: 002-05677 Rev. *C Page 357 of 423 CY9DF125 - Atlas-L Table 66. SPI Interface Timing for All Cells of Type SMC Parameter Input setup time (SPIn_DATAi) Symbol TIS,DATA Master Mode, non-retimed clock Master Mode, retimed clock Slave Mode Min Max Min Max Min Max 25.3 – 5.7 – 5.6 – [24] Unit ns Input hold time (SPIn_DATAi) TIH,DATA -6.2 – 4.3 – 4.2 – ns Output delay time (SPIn_DATAo) TOD,DATA – 7.1 – 7.1 – 26.6 ns Output hold time (SPIn_DATAo) TOH,DATA -4.3[24] – -4.3[24] – 6.8 – ns Input setup time (SPIn_SSELi) TIS,SSEL – – – – 4.8 – ns Input hold time (SPIn_SSELi) TIH,SSEL – – – – 2.6 – ns Output delay time (SPIn_SSELo) TOD,SSEL – 4.2 – 4.2 – – ns Output hold time (SPIn_SSELo) TOH,SSEL 2.1 – 2.1 – – – ns Table 67. Example for Calculation of Maximum Frequencies for Communication of Master (Retimed Mode) and Slave Transmission Half Period Time Max. Frequency Unit From Master to Slave T/2 = TOD,DATA (Master) + TIS,DATA (Slave) 39.3 MHz From Slave to Master T/2 = TOD,DATA (Slave) + TIS,DATA (Master) 15.4 MHz Note 24. A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a sampling point that is outside the time interval given by Output hold time and Output delay time. Document Number: 002-05677 Rev. *C Page 358 of 423 CY9DF125 - Atlas-L Figure 14. SPI Interface Timing Document Number: 002-05677 Rev. *C Page 359 of 423 CY9DF125 - Atlas-L External Bus Interface Timing (TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 4.5V to 5.5V, DVCC = 4.5V to 5.5V, VSS = AVSS5 = DVSS = 0V, CLoad = 20 pF) ■ General Timing Table 68. General Timing Parameters Parameter Symbol Pin names MCSX0~MCSX7 Tcso Address delay time Value Unit Min Max EBI0_MCLK, EBI0_MCSX0 ~ EBI0_MCSX7 – 7 ns Tao EBI0_MCLK, EBI0_MAD[23:0] – 11 ns Data output delay time Tdo EBI0_MCLK, EBI0_MDATA[31:0] – 9 ns Data output HiZ time Tdoz EBI0_MCLK, EBI0_MDATA[31:0] – 10 ns RDY setup time Tdsr EBI0_RDY – 8 ns RDY hold time Tdhr EBI0_RDY 0 – ns Document Number: 002-05677 Rev. *C Note Page 360 of 423 CY9DF125 - Atlas-L ■ SRAM Read Timing Table 69. SRAM Read Timing Parameters Parameter Symbol Pin names SRAM data setup time Tdsr SRAM data hold time MOEX delay time Value Unit Min Max EBI0_MOEX, EBI0_MDATA[31:0] 15 – ns Tdhr EBI0_MOEX, EBI0_MDATA[31:0] 0 – ns Trdo EBI0_MCLK, EBI0_MOEX – 8 ns Note Figure 15. SRAM Read Timing Document Number: 002-05677 Rev. *C Page 361 of 423 CY9DF125 - Atlas-L ■ SRAM Write Timing Table 70. SRAM Write Timing Parameters Parameter Symbol Pin names SRAM WE delay time Tweo MDQM[3:0] delay time Twro Value Unit Min Max EBI0_MCLK, EBI0_MWEX – 7 ns EBI0_MCLK, EBI0_MDQM[3:0] – 7 ns Note Figure 16. SRAM Write Timing Document Number: 002-05677 Rev. *C Page 362 of 423 CY9DF125 - Atlas-L ■ SDRAM Access Timing Table 71. SDRAM Access Timing Parameters Parameter Symbol Pin names Tmcs SDRAM RAS delay time SDRAM CAS delay time SDRAM WE delay time Value Unit Min Max EBI0_MCLK, EBI0_MCSX0 – 7 ns Tras EBI0_MCLK, EBI0_MRASX – 6 ns Tcas EBI0_MCLK, EBI0_MCASX – 6.5 ns Tmwe EBI0_MCLK, EBI0_MDWEX – 7 ns SDRAM CKE delay time Tcke EBI0_MCLK, EBI0_MCKE – 7.5 ns SDRAM data setup time Tdssd EBI0_MCLK, EBI0_MDATA[31:0] 8.5 – ns SDRAM data hold time Tdhsd EBI0_MCLK, EBI0_MDATA[31:0] 0 – ns SDRAM CS delay time Note Figure 17. SDRAM Access Timing Document Number: 002-05677 Rev. *C Page 363 of 423 CY9DF125 - Atlas-L ■ NAND Flash Read Timing Table 72. NAND Flash Read Timing Parameters Parameter Symbol Pin names Treno NAND data setup time NAND data hold time NAND Read Enable delay time Value Unit Min Max EBI0_MCLK, EBI0_MNREX – 7.5 Tdsn EBI0_MCLK, EBI0_MDATA[31:0] 14.5 – ns Tdhn EBI0_MCLK, EBI0_MDATA[31:0] 0 – ns Note ns Figure 18. NAND Flash Read Timing Document Number: 002-05677 Rev. *C Page 364 of 423 CY9DF125 - Atlas-L ■ NAND Flash Write Timing Table 73. NAND Flash Write Timing Parameters Parameter Symbol Pin names Taleo NAND Command Latch Enable delay time NAND Write Enable delay time NAND Address Latch Enable delay time Value Unit Min Max EBI0_MCLK, EBI0_MNALE – 6 ns Tcleo EBI0_MCLK, EBI0_MNCLE – 4.5 ns Tweno EBI0_MCLK, BI0_MNWEX – 6.5 ns Note Figure 19. NAND Flash Write Timing Document Number: 002-05677 Rev. *C Page 365 of 423 CY9DF125 - Atlas-L Analog Digital Converter (TA = -40C to +105C, 3.0V - AVRH5, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V) Table 74. Analog Digital Converter Parameter Symbol Pin Resolution – Total error Value Unit Remarks Min Typ Max – - – 10 bit – – -3 – +3 LSB Nonlinearity error – – -2.5 – +2.5 LSB Differential nonlinearity error – – -1.9 – +1.9 LSB Full scale transition voltage VFST ANi AVRH5 3.5 LSB AVRH5 - 1.5 LSB AVRH5 + 0.5 LSB V Zero Transition Voltage VFST ANi Typ - 20 AVSS5 + 0.5 LSB Typ + 20 mV TS pi_jj(ANIN) 353 – 1186 KS/s 646.8 – – ns Fclk=17MHz, Tclk=58.8ns * 11 clocks – – 2750 ns AVDD5 = 4.5V...5.5V, Fclk=4MHz, Tclk=250ns * 11 clocks – – 1837 ns AVDD5 = 3.0V...4.5V, Fclk=6MHz, Tclk=167ns * 11 clocks -1 – +1 A TA  25C, AVSS5 < VI < AVDD5, AVRH5 -3 – +3 A TA  105C, AVSS5 < VI < AVDD5, AVRH5 Conversion Rate Comparison Time TCOMP – Between 0 and 1 Analog input leakage current (during conversion) IAIN Analog input voltage range VAIN ANn AVSS5 – AVRH5 V AVRH5 AVRH5 AVDD5 0.5 – AVDD5 V IA AVDD5 – 2 3.4 mA A/D Converter active IAH AVDD5 – – 6 A 25°C, A/D Converter not operated – – 11 A 105°C, A/D Converter not operated Reference voltage range Power supply current Reference voltage current Offset between input channels ANn IR AVRH5 – 0.6 1 mA A/D Converter active IRH AVRH5 – – 0.6 A A/D Converter not operated – ANn – – 4 LSB Note 25. The accuracy gets worse as |AVRH5 | becomes smaller. Document Number: 002-05677 Rev. *C Page 366 of 423 CY9DF125 - Atlas-L Minimum Sampling Time The minimum sampling time can be calculated from the following formula: For pins ADC0_AN0..25: Tsamp [min] = 7.63 x [ Rext x ( Cext + 16pF ) + ( Rext + 1.78kOhm ) x 19pF ] For Pins ADC0_AN26..31: Tsamp [min] = 7.63 x [ Rext x ( Cext + 16pF ) + ( Rext + 1.78kOhm ) x 2pF + ( Rext + 3.55 kOhm ) x 19pF ] Definition of A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and linear error. Nonlinearity error: Deviation between a line across zero-transition line (00 0000 0000 00 0000 0001) and full-scale transition line (11 1111 1110 11 1111 1111) and actual conversion characteristics. Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Figure 20. Total Error of Digital Output Document Number: 002-05677 Rev. *C Page 367 of 423 CY9DF125 - Atlas-L FLASH Memory Program/Erase Characteristics for TCFLASH and EEFLASH (TA = -40°C to 105°C, VDD = 1.1V to 1.3V, VDP3 = 3.0V to 3.6V, VDP5 = AVDD5 = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS5 = DVSS = 0V) Table 75. Program/erase time Value Parameter Sector Erase Time Macro Erase Time Unit Min Typ[26] Max Small Sector – 0.3 1.1 s Large Sector – 0.7 3.7 s TCFLASH – 13.6 68 s EEFLASH – 2.4 8.8 s – 12 384 s Word Programming Time Remarks The internal programming time before the erase procedure starts is included. Note 26. Typical definition: TA=25°C / VDD=1.2V / Program/Erase cycle = Immediately after shipment. Table 76. Program/Erase cycle and Data Retention time[27] Program/Erase cycle at each sector Data Retention time Min Value Unit Min Value Unit 1000 cycles 20 years 10000 cycles 10 years 100000 cycles 5 years Note 27. These values were converted from the technology qualification using Arrhenius equation to translate high temperature measurements into normalized values at + 85°C. Table 77. Execution Time Limit Parameter Program Execution Time limit [28] Macro Erase Execution Time limit [29] Sector Erase Execution Time limit Value Unit 1.3 ms TCFLASH 187.2 s EEFLASH 63 s 7.8 s Notes 28. This is the time it takes for the macro to detect a Hang up 1 error when 1 is to be programmed to a memory cell whose memory value is either 0 or X. 29. See the Hardware Manual for an explanation about Flash Timing Limit Exceeded Flags. The time during Sector Erase Suspend (period from Suspend Command Write Cycle to Resume Command Write Cycle) is not included. Document Number: 002-05677 Rev. *C Page 368 of 423 CY9DF125 - Atlas-L RC Oscillator Frequency This chapter provides reference values for the RC Configuration Register (SYSC_RCCFGR) settings. The corresponding oscillator is commonly referred to as the “12 MHz RC Oscillator”, because its typical frequency at the central setting is about 12 MHz, with the SYSC_RCCFGR:SFREQ bit set to “1”. When the SYSC_RCCFGR:SFREQ bit is set to “0”, the central setting corresponds to about 8 MHz. The default value of SYSC_RCCFGR:SFREQ is “1” and the default value of SYSC_RCCFGR:TRM[7:0] is “0xFF”, so the default frequency setting is 16.9 MHz (typical value). Figure 21. RC Oscillator Frequency at SYSC_RCCFGR:SFREQ = 0 Note 30. The provided function values are not guaranteed and can serve for reference, only. Guaranteed values are listed in Table 50 on page 346. Document Number: 002-05677 Rev. *C Page 369 of 423 CY9DF125 - Atlas-L Figure 22. RC Oscillator Frequency at SYSC_RCCFGR:SFREQ = 1 Note 31. The provided function values are not guaranteed and can serve for reference, only. Guaranteed values are listed in Table 50 on page 346. ESD Structure between Power Domains Figure 23. ESD Diodes between VDP3, VDD and VSS VDP3 (3.3V typ) VDD (1.2V typ) VSS (0V) Document Number: 002-05677 Rev. *C Page 370 of 423 CY9DF125 - Atlas-L Figure 24. ESD Diodes between VDP5, VDD and VSS   VDP5 (3.3V/5V typ)     VDD  (1.2V typ)  VSS (0V)  Figure 25. ESD Diodes between VDP5, AVSS5 and VSS VDP5 (3.3V/5V typ)  AVSS5(0V) VSS (0V) Figure 26. ESD Diodes between AVDD5 and AVSS5 AVDD5(3.3V/5V typ) AVSS5(0V) Document Number: 002-05677 Rev. *C Page 371 of 423 CY9DF125 - Atlas-L Figure 27. ESD Diodes between DVCC, DVSS and VSS DVCC (3.3V/5V typ)  DVSS(0V) VSS (0V) Figure 28. ESD Diodes between VDP5, AVDD5 and VSS VDP5 (3.3V/5V typ)  AVDD5 (3.3V/5V typ)  VSS (0V) Document Number: 002-05677 Rev. *C Page 372 of 423 CY9DF125 - Atlas-L Procedures Boundary Scan Boundary scan is supported using standard 1EEE 1149.1 JTAG interface. A 5-pin JTAG connection is available on QFP-176. Instruction register supported is 5-bits wide, and the standard instructions listed in Table 78 are supported. Any other value of instruction register is reserved, and should not be entered. Entering reserved values can result in indeterminate operation Boundary scan mode may be entered by setting pins MODE = “1” and MD[0] = “0”. Table 78. Standard Instructions Instruction Code (in binary) Instruction Accessible Data Register ‘000000’ EXTEST Boundary scan chain ‘000001’ SAMPLE Boundary scan chain ‘000010’ PRELOAD Boundary scan chain ‘000011’ IDCODE Device ID code register ‘000100’ USERCODE Device user code register ‘000101’ HIGHZ Boundary scan chain ‘000110’ CLAMP Boundary scan chain ‘010001’ IO_CNTRL Boundary scan chain ‘111111’ BYPASS Bypass register Remarks For CY9DF125 (ATLAS-L), IDCODE is 0x0F153009 For CY9DF125 (ATLAS-L), USERCODE is 32-bits long, and is 0xC4AB2012 Command must be followed by 16bit data value: 0x04pp, where “pp” is a pin control setting from Table 79. Table 79. IO Control (IO_CNTRL) Register IO_CNTRL 0 0 0 0 0 Document Number: 002-05677 Rev. *C 0 0 0 0 0 0 0 0 RW RW PITILS[1] 0 PITILS[0] 1 OUTDR[0] OUTDR[1] 2 RW RW 0 3 DCPUP DCPDN 4 RW 5 RW 6 R0W0 reserved 7 R0W0 reserved RW RW 0 8 I2C SEL 9 R0W0 reserved 10 R0W0 reserved 11 R0W0 reserved 12 R0W0 reserved 13 R0W0 reserved 14 R0W0 reserved 15 0 Page 373 of 423 CY9DF125 - Atlas-L Table 80. IO Control (IO_CNTRL) Register Bits Bit Position Bit Field Name Bit Description [15:11] reserved Reserved. Always write 0 to these bits. [10] SEL Selection of DCPDN, DCPUP, OUTDR and PITILS "0": IO_CNTRL[5:0] are disabled. Input buffers are disabled. "1": IO_CNTRL[5:0] will control IO pads [9] I2C Extends IO_CNTRL[3:2], but for I2C IO cell only (see below) "0” : set I2C cell to value selected by IO_CNTRL[3:2] "1" : set I2C cell to "pseudo open drain" [8:6] reserved Reserved. Always write 0 to these bits. DCPDN Control all pull-down resistors of the IOs Valid if bit [10] is "1" "0” : All pull-downs are disabled "1” : All pull-downs are enabled DCPUP Control all pull-up resistors of the IOs Valid if bit [10] is "1" "0” : All pull-uos are disabled "1” : All pull-ups are enabled [5] [4] Output driver strength Valid if bit 10 is "1" Bit selection depends on IO cell type (see IO Circuit Types on page 70) OUTDR[1:0] [3:2] [1:0] BIDI50 BIDI33 SMC I2C “00” 5mA± mA 5mA 5mA “01” 2mA 2mA 2mA 2mA “10” 1mA 1mA 1mA 1mA “11”   30mA  x + bit[9] = “1” - - - pseudo open drain OUTDR PITILS Pin Input Test Input Level Select Valid if bit 10 is "1" "00”: Hysteresis "01”: Automotive "10”: TTL "11”: CMOS Note 32. When Bit[10] = “0”, all input buffers are disabled in Boundary Scan mode. Then, input of data via external pins to the BSR (Boundary Scan Register) is impossible. Therefore, the minimum setting to allow input to the BSR is 0x0400. Example procedure for Configuration for Port Input 1. MODE clipped to ’1’ and MD[0] clipped to ’0’. 2. release JTAG_NRST and RSTX. 3. JTAG-Instruction IO_CNTRL (010001) 4. set IO_CNTRL-reg 10th bit: (e.g. 0000010000000000) 5. JTAG-Instruction SAMPLE. -> Port Input The serial chain starts with the I/O closest to JTAG_TDI pin, and ends with the I/O closest to the JTAG_TDO pin. Details may be obtained from BSDL files released per package Document Number: 002-05677 Rev. *C Page 374 of 423 CY9DF125 - Atlas-L Flash Parallel Programming Flash Parallel Programming (FPP) mode is supported to allow for quick programming/erase of embedded flashes. In this mode program or erase of flash is done using a flash memory programmer directly via external pins. Flash programming is done either in 8-bit or 16-bit mode through the command sequence. Refer Section 4 of Tightly Coupled Flash Chapter of HWM for details of Flash program/erase command sequence. Flash addressing in this mode is direct physical addressing, with higher order bits used for flash macro selection. In CY9DF125 (ATLAS-L) device, there is one flash macro of 1MB+64KB size and 1 flash macro of 64KB. Table 81 provides the details about flash macro sectoring. Table 81. Flash sector information Flash Macro Macro size Small Sectors (8KB/sector) Large Sectors (64KB/Sector) TCFLASH macro 0 1MB + 64KB 8 16 EEFLASH macro 64KB 8 Not Available Table 82 provides the details about mapping of flash pins to external pins. Table 82. Flash Pin Mapping to External Pins External Pin Number (QFP-176) External Pin Name Flash Macro Pin Function 93 P3_24 DFSEL Flash select signal. Refer Table 86 for additional details regarding use of DFSEL. 126 X0 FCLK Flash clock 130 MODE MODE Mode pin to enter test mode (MODE = ‘1’) 131 RSTX RSTX Device Reset pin 103 P3_32 SMD[0] Set to ‘1’ when entering FPP mode. 103 P1_26 SMD[1] Set to ‘1’ when entering FPP mode. 105 P1_27 MD[2] Set to ‘1’ when entering FPP mode. 106 P1_28 MD[1] Set to ‘1’ when entering FPP mode. 107 P1_29 MD[0] Set to ‘1’ when entering FPP mode. 98 P3_27 FRSTX External flash reset pin ‘0’ : Reset ‘1’ : Normal operation External power enable to flash macro at 5V 99 P3_28 FRSTRX ‘0’ : Reset ‘1’ : Normal operation Flash macro enable 6 P1_00 CEX ‘0’ : Macro recognizes read/write commands ‘1’ : Neither read operation nor write operation is executed Write enable 146 P0_50 WEX ‘0’ : Macro recognizes read commands ‘1’ : Macro recognizes write commands 147 P0_51 Document Number: 002-05677 Rev. *C BYTEX Byte access enable ‘0’ : 8-bit write mode ‘1’ : 16-bit write mode Page 375 of 423 CY9DF125 - Atlas-L Table 82. Flash Pin Mapping to External Pins (Continued) External Pin Number (QFP-176) External Pin Name Flash Macro Pin 68 P3_33 OEX 7 P1_01 FA[00] 8 P1_02 FA[01] 9 P1_03 FA[02] 10 P1_04 FA[03] 11 P1_05 FA[04] 12 P1_06 FA[05] 13 P1_07 FA[06] 16 P1_08 FA[07] 17 P1_09 FA[08] 18 P1_10 FA[09] 19 P1_11 FA[10] 20 P1_12 FA[11] 21 P1_13 FA[12] 22 P1_14 FA[13] 23 P1_15 FA[14] 26 P1_16 FA[15] 27 P1_17 FA[16] 28 P1_18 FA[17] 29 P1_19 FA[18] 30 P1_20 FA[19] 31 P1_21 FA[20] 32 P1_22 GND 33 P1_23 GND Document Number: 002-05677 Rev. *C Function Direction control signal for shared pins like data and ECC data ‘0’ : Shared data/ECC data pins are in output mode ‘1’ : Shared data/ECC data pins are in input mode Flash address Page 376 of 423 CY9DF125 - Atlas-L Table 82. Flash Pin Mapping to External Pins (Continued) External Pin Number (QFP-176) External Pin Name Flash Macro Pin 150 P2_32 DIN[00]/DOR[00] 151 P2_33 DIN[01]/DOR[01] 154 P2_34 DIN[02]/DOR[02] 155 P2_35 DIN[03]/DOR[03] 156 P2_36 DIN[04]/DOR[04] 157 P2_37 DIN[05]/DOR[05] 158 P2_38 DIN[06]/DOR[06] 159 P2_39 DIN[07]/DOR[07] 160 P2_40 DIN[08]/DOR[08] 161 P2_41 DIN[09]/DOR[09] 162 P2_42 DIN[10]/DOR[10] 163 P2_43 DIN[11]/DOR[11] 164 P2_44 DIN[12]/DOR[12] 165 P2_45 DIN[13]/DOR[13] 166 P2_46 DIN[14]/DOR[14] 167 P2_47 DIN[15]/DOR[15] 136 P0_40 EDIN[00]/EDOR[00] 137 P0_41 EDIN[01]/EDOR[01] 138 P0_42 EDIN[02]/EDOR[02] 139 P0_43 EDIN[03]/EDOR[03] 140 P0_44 EDIN[04]/EDOR[04] 141 P0_45 EDIN[05]/EDOR[05] 142 P0_46 EDIN[06]/EDOR[06] Function Shared data input/output Shared ECC data input/output ECC write access enable 70 P3_35 ECCA ‘0’ : ECC write disable ‘1’ : ECC write enable Internal voltage ready/busy flag at 5V 144 P0_48 RDYR ‘0’ : Busy ‘1’ : Ready 145 69 P0_49 P3_34 Document Number: 002-05677 Rev. *C RDY Flash ready/busy flag RD64 64-bit read enable 0 : 32-bit read mode 1 : 64-bit read mode Page 377 of 423 CY9DF125 - Atlas-L Timing requirements for flash signals are provided in Figure 22 and Table 83 on page 379. Figure 22. Flash Timing Parameters Document Number: 002-05677 Rev. *C Page 378 of 423 CY9DF125 - Atlas-L Table 83. Flash Timing Requirements Parameter Symbol Min. Value Unit tCY 100 ns Clock High Time tCWH 25 ns Clock Low Time tCWL 25 ns Cycle Time CEX setup tSCE 20 ns CEX hold tHCE 20 ns WEX setup tSWE 20 ns WEX hold tHWE 20 ns RD64 setup tSRD 20 ns RD64 hold tHRD 20 ns BYTEX setup tSBW 20 ns BYTEX hold tHBW 20 ns ECCA setup tSEC 20 ns ECCA hold tHEC 20 ns OEX setup tSOE 20 ns OEX hold tHOE 20 ns DFSEL setup tSDF 20 ns DFSEL hold tHDF 20 ns FA setup tSA 20 ns FA hold tHA 20 ns DIN/EDIN setup tSI 20 ns DIN/EDIN hold tHI 20 ns RDY output delay tACY 80 ns DOR/EDOR output delay tACC 80 ns tHD 5 ns DOR/EDOR hold Document Number: 002-05677 Rev. *C Page 379 of 423 CY9DF125 - Atlas-L Memory Map This flash memory consists of 0,2,4,6,8,10,12,14, or 16 sector(s) of 64k byte (large sector) and 8 sectors of 8k byte (small sector). Large sector is composed of 16k word, and small sector is composed of 2k word. 1word data width is 39bit (regular bit: 32bit + ECC parity bit: 7bit) for both large sector and small sector. Address Space & Memory Cell Select Address Assignment The select address assignment is listed below. The assignment in the large sector and that in the small sector differ. When the small sector (FA[20]=0) is selected, no matter what the values (1/0) of FA[19:16] are, the memory cell to be used is determined according to the values of FA[15:0]. ■ Large Sector (0x100000 ~ 0x1FFFFF) Table 84. Large Sector (0x100000 ~ 0x1FFFFF) In read or program mode, an address pin input is ignored as shown below. Apply a given value (1/0) to the corresponding pin. For the correspondence between data output pins and data input pins, see Section and Section . 8bit program mode (BYTEX=0): Ignore none of FA[20:0] and input 8bit selected in FA[20:0]. 16bit program mode (BYTEX=1): Ignore FA[0] and input 16bit. ❐ FPP mode can only output 8 or 16 bit. ❐ RD64 should always be kept 0. ❐ BYTEX=0: DQ[7:0] is used ❐ BYTEX=1: DQ[15:0] is used ❐ ■ Small Sector (0x0*0000 ~ 0x0*FFFF) Table 85. Small Sector (0x0*0000 ~ 0x0*FFFF) The left asterisk mark in the value indicates a given value (except an indeterminate value). When small sector is selected (FA[20]=0), input a given value (1/0) to FA[19:16] pins. In read or program mode, an address pin input is ignored as shown below. Apply a given value (1/0) to the corresponding pin. For the correspondence between data output pins and data input pins, see Section and Section . 8bit program mode (BYTEX=0): Ignore none of FA[20,15:0] and input 8bit selected in FA[20,15:0]. 16bit program mode (BYTEX=1): Ignore FA[0] and input 16bit. ❐ FPP mode can only output 8 or 16 bit. ❐ RD64 should always be kept 0. ❐ BYTEX=0: DQ[7:0] is used ❐ BYTEX=1: DQ[15:0] is used ❐ ❐ Document Number: 002-05677 Rev. *C Page 380 of 423 CY9DF125 - Atlas-L Output Data Table In 32-bit read mode, the data is output to different output pins based on the sector-selected lowest address values as shown in Table 86. Table 86. Data Output Correspondence Table in Read Bit Modes ■ FA[#] indicates the lowest bit of sector-selected address, i.e. FA[16] when the large sector is selected (FA[n]=1), and FA[13] when the small sector is selected (FA[n]=0). ■ Even Sector indicates an even-number-th sector (large sector FA[16]=0 / small sector FA[13]=0). Odd Sector indicates an odd-number-th sector (larget sector FA[16]=1 / small sector FA[13]=1). Document Number: 002-05677 Rev. *C Page 381 of 423 CY9DF125 - Atlas-L Input Data Table In 8-bit program mode, the data of the different input pins based on the FA[0] values is programmed as shown in Table 87. When ECCA=1, is input at the program data input, the data is written to ECC parity bit as well as Regular bit. When ECCA=0 is input at the program data input, the data is written only to Regular bit. In this case, EDIN[6:0] input value is “don’t care,” and regardless of the value, no value is written to ECC parity bit. In the case of erase operation, regardless of input values to ECCA, both Regular bit and ECC parity bit are erased together. Table 87. Correspondence Table of Data Input and Memory Cell Bit in Program Bit Modes ■ "Any" a value of either 1 or 0. ■ FA[#] indicates the lowest bit of sector-selected address, i.e. FA[16] when the large sector is selected (FA[n]=1), and FA[13] when the small sector is selected (FA[n]=0). When programming, in both 8bit mode and 16bit mode, program/erase operation is executed per one sector specified by the selected addresses. ■ Program Data Input means the 4th write cycle of a program command in the normal operation state and the 2nd write cycle of a program command in the Unlock-bypass state. ■ Command Data Input means the write cycles in the write command sequence other than those mentioned above in which program data is input. Document Number: 002-05677 Rev. *C Page 382 of 423 CY9DF125 - Atlas-L Flash address mapping in FPP However, device level memory map differs from actual physical address to flash macro. Hence, it is expected that the flash parallel programmer must translate CPU mode addressing to actual physical address to flash. Hence, CPU execution code must be located at physical addresses that are mapped to the CPU mode addresses. Translation of CPU mode address to actual physical address differs based on whether small or large sectors are accessed. Address translation for small sectors of TCFLASH macro 0 is as shown in Table 88. Table 88. TCFlash Small Sectors Address Translation Flash Address Bit CPU Address Bit FA[20] 0 FA[19] 0 FA[18] 0 FA[17] 0 FA[16] 0 FA[15] ADDR[15] FA[14] ADDR[14] FA[13] ADDR[02] FA[12] ADDR[13] FA[11] ADDR[12] FA[10] ADDR[11] FA[09] ADDR[10] FA[08] ADDR[09] FA[07] ADDR[08] FA[06] ADDR[07] FA[05] ADDR[06] FA[04] ADDR[05] FA[03] ADDR[04] FA[02] ADDR[03] FA[01] ADDR[01] Document Number: 002-05677 Rev. *C Table 88. TCFlash Small Sectors Address Translation Flash Address Bit CPU Address Bit FA[00] ADDR[00] Address translation for large sectors of TCFlash is shown in Table 89. Table 89. TCFlash Large Sectors Address Translation Flash Address Bit CPU Address Bit FA[20] 1 FA[19] ADDR[20] FA[18] ADDR[19] FA[17] ADDR[18] FA[16] ADDR[02] FA[15] ADDR[17] FA[14] ADDR[16] FA[13] ADDR[15] FA[12] ADDR[14] FA[11] ADDR[13] FA[10] ADDR[12] FA[09] ADDR[11] FA[08] ADDR[10] FA[07] ADDR[09] FA[06] ADDR[08] FA[05] ADDR[07] FA[04] ADDR[06] FA[03] ADDR[05] FA[02] ADDR[04] FA[01] ADDR[01] The EEFlash macro can not be programmed in FPP mode with respect to SHE security. Page 383 of 423 CY9DF125 - Atlas-L Flash Power On Sequence Prior to entering flash parallel programming mode, the sequence mentioned below must be followed: using wired-AND of the RDY outputs, to detect when slowest device becomes ready. 1. Apply following constant pin setting: MODE = 1 and MD[2:0] = 111. The pins for MD[2:0] have pull-up, thus can be left open. Failure to follow the above sequence can result in indeterminate behavior. Once the above sequence is completed, flash parallel programming mode may be entered. 2. Assert RSTX = 0 and JTAG_nTRST = 0. The pin JTAG_nTRST has pull-down, so it will be kept in reset by the device if it is left open. Asserting FRSTX = 0 and FRSTRX = 0 is optional. This is done internally at device startup. Flash parallel programming mode standard usage: 3. Ramp up the power supply (please refer to device specific datasheet for power supply sequence) and wait till all power suppliess (VDP5, VDP3 & VDD) are stable 4. Wait for at least 500ns after all power supplies are stable. 5. De-assert RSTX= 1, also deassert FRSTX = 1 and FRSTRX = 1 if those were asserted before. 6. Wait until Flash Parallel Programming mode is entered by the bootROM program (boot time). Wait time should be >=2.5 ms after RSTX release. Note that the wait time is necessary because RDY pin is High-Z before FPP mode is entered. Looking at RDY (which has pull-up) alone would cause mis-interpretation before that time is elapsed. 7. Flash access is possible after RDY pin goes to “1” . Clock supply is needed for monitoring RDY. RDY pin is pseudo open drain and thus needs a pull-up resistor. That makes it possible to program multiple devices at once by Entering FPP by releasing RSTX while keeping ■ MODE = ‘1’ ■ MD[1] = ‘1’, MD[0] = ‘1’ ■ SMD[2] = ‘1’, SMD[1] = ‘1’, SMD[0] = ‘1’ Furthermore, Flash parallel programming mode may be entered using 2 options: 1. Setting MCFG_DTAR:FPPREQ 2. Setting MCFG_TSR:MD = ’XXX111’, and MCFG_TSR:SMD = ’11111’ Once flash parallel mode is requested, the bit SYSC_MCR:FPPEN is set, which enables entry to FPP mode. However, it must be noted that FPP access must also be enabled in Security Description Record (SDR) (see HWM). The external programmer must also take care to program ECC bits for flash data contents. This also applies to flash erase, where bit flipping (XOR with 0x73) is to be performed to handle ECC checking for erased flash. Figure 23. Power On Sequence Document Number: 002-05677 Rev. *C Page 384 of 423 CY9DF125 - Atlas-L Table 90. Timing Parameters Related to Power ON Sequence Parameter Symbol Hardware Reset(FRSTX=0) period FRSTRX fall to RDYR fall access FRSTX fall to RDY reset FRSTRX rise to RDYR rise access FRSTRX rise to RDY rise access Debug and Trace ■ A standard 5-pin JTAG interface is supported for debug and trace. Conventional debug (core halted, and invasive) as well as trace debug (core not halted and non-invasive) are supported. The procedures for debug and trace rely on ARM Coresight technology. The salient features for debug are: ■ Secure mode entry for debugger Value Unit Min Max tRP 440 - ns tARYR - 16 ns tARY - 8 ns tREGRDYR - 80 ns tREGRDY - 80 ns Up to 8 breakpoints, or 8 watchpoints Tracing support is provided on both packages as shown below: ■ QFP-176: 4-bit and 8-bit trace data shared with resources. Trace port to pin mapping in QFP-176 package is shown in Table 91. Table 91. Trace Port to External Pin Mapping Shared Pin Number (QFP-176) External Pin Name Trace Port 106 P1_28 DBG0_CTL 107 P1_29 DBG0_CLK 104 P1_26 DBG0_TRACE0 105 P1_27 DBG0_TRACE1 45 P1_30 DBG0_TRACE2 46 P1_31 DBG0_TRACE3 47 P1_32 DBG0_TRACE4 48 P1_33 DBG0_TRACE5 66 P1_24 DBG0_TRACE6 67 P1_25 DBG0_TRACE7 Document Number: 002-05677 Rev. *C Page 385 of 423 CY9DF125 - Atlas-L Package QFP-176 has no dedicated trace pins. See Table 17 for relevant pins and the corresponding settings for their activation. In general, additional information regarding debug and trace methodology can be obtained from Coresight TRM provided by ARM Limited. However, an additional characteristic is the support of security feature to prevent unauthorized access through the debug port. At the time of initiating the debugger access, it is necessary to transmit a security key. The security key can only be transmitted once after reset. If a wrong key is entered, further accesses are disabled, and the only method to regain access is through application of external reset. In the device, trace support is provided for the following components/busses: 1. Embedded Trace Macro (ETM) and Instrumentation Trace Macro (ITM) for processor core 2. Independent AHB bus trace macro (HTM) for up to 8 busses. Refer Table 92 on page 386 for details Further, Cross Trigger Interface (CTI) macros are included to support cross triggering among all the above macros. Table 92. HTM Trace Sources Bus Width (bits) Source ID EBI slave 32 9 Power domain on/off status information can be obtained through debug port by accessing register on memory mapped address 0xB0509400. This provides an easy method to obtain information on current state of power domains, without the need to access device level internal registers. Refer Table 93 for details. Table 93. Power Domain Status Information for Debugger Bit Number 31:3 2 PD4 on/off status ‘0’ : Power domain is off ‘1’ : Power domain is on 1 PD3 on/off status ‘0’ : Power domain is off ‘1’ : Power domain is on Table 92. HTM Trace Sources Bus Function Reserved Width (bits) Source ID DMA Master 64 1 PERI4 master 32 2 MEMORY_CONFIG slave 64 3 MCU_CONFIG slave 32 4 PERI5 slave 32 5 PERI3 slave 64 6 PERI4 slave 32 7 HSSPI slave 32 8 Document Number: 002-05677 Rev. *C 0 PD2 on/off status ‘0’ : Power domain is off ‘1’ : Power domain is on Page 386 of 423 CY9DF125 - Atlas-L Handling Devices Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than (VDD, VDP3 or VDP5) or less than (VSS) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. Handling of Unused Input Pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2k to 10k) or enable internal pullup or pulldown resistors (PUE/PDE) before the input enable (PIE) is activated by software. The pins of circuit type MODE can be connected to VSS or VDP5 directly. Power Supply Pins In FCR4 series, devices including multiple power supply pins and ground pins are designed as follows: pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the FCR4 series must be connected to the current supply source via a low impedance. Document Number: 002-05677 Rev. *C It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between power supply pin and ground pin near this device. If DVCC is not set to the same voltage level as AVDD5, the ZPD functionality of SMC pins cannot be used. Refer to the “ADC_SMC connection” section of the Hardware Manual for more information. Power on Sequence At any time, the difference between the power supply pins belonging to the same voltage level must not exceed 0.5V. This especially applies to the power on sequence. Otherwise, the risk of latchup will increase. Figure 24 shows the power on sequence and the groups of power supply that might be used, depending on the actual application. Furthermore, VDP5 supply must be switched on before any other power supply or at least at the same time. The following conditions must be fulfilled at any moment: 1. The voltage of VDP5 must be higher or equal than the voltage on AVDD5 and AVRH5. 2. The voltage of VDP3 must be higher or equal than the voltage on VDD. In particular, VDP3 must not be switched off for saving power. 3. The supply voltage for MODE and RSTX pins must reach the minimum operational value before switching on core voltage supply. Page 387 of 423 CY9DF125 - Atlas-L Figure 24. Power on Sequence V 5.5V 5V AVRH5 = AVDD5 = DVCC = VDP5 0.5V 3.6V 3.3V VDP3 3.0V VDP5 0.5V 1.3V 1.2V VDD 1.1V 0.5V t RSTX pin Internal RSTX undefined MODE pin internal MODE undefined Pin State During Active External Reset Crystal Oscillator Circuit Table 95 shows the state of output/bidirectional pins during External Reset. For subsequent reset or power saving states, the pin state can be programmed according to the possibilities listed in HWM. Before software execution is started, however, the user must pay attention to the listed behavior. Noise in proximity to the X0/X0A and X1/X1A pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0/X0A and X1/X1A pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0/X0A and X1/X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the related characteristics of the crystal and this device. Table 95. Pin State During Active External Reset Pin Type Reset State JTAGO HIZ BIDI50 HIZ BIDI33 HIZ SMC HIZ I2C HIZ Document Number: 002-05677 Rev. *C Page 388 of 423 CY9DF125 - Atlas-L Notes on Using External Clock Single Phase Clock Supply: Fast Clock Input Mode Opposite Phase Clock Supply: Oscillation Mode When a high frequency clock needs to be fed, it is possible to directly supply a single phase clock at X0. For this mode: When using the external clock, it is possible to simultaneously supply the X0/X0A and X1/X1A pins. In the described combination X0/X0A should be supplied with a clock signal which has the opposite phase to the X1/X1A pins. However, in this case the stop mode (oscillation stop mode) must not be used (This is because the X1/X1A pin stops at ”H” output in STOP mode). ■ SYSC_SPCCFGR:FCIMEN bit must be set to “1”. ■ Input clock must have 50% duty cycle. Figure 27. Example of Using Fast Clock Input Mode With opposite phase supply at XTAL0/X0 and XTAL1/X1, a frequency up to 16 MHz is possible. Figure 25. Example of Using Opposite Phase Supply Unused Sub Clock Signal If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. Single Phase Clock Supply For lower frequencies, up to 4 MHz, it is possible to supply a single phase clock at X0. Figure 26. Example of Using Single Phase Supply Document Number: 002-05677 Rev. *C Page 389 of 423 CY9DF125 - Atlas-L Errata This section describes the errata for the Atlas-L, CY9DF125BPMC-GSE2, and CY9DF125EBPMC-GSE2. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Product Status: In Production The following table defines the errata applicability to available Atlas-L, CY9DF125BPMC-GSE2, and CY9DF125EBPMC-GSE2. An “X” indicates that the errata pertains to the selected device. Items [1]. TCFlash Programming [2]. 3V IO Domain ESD Diode Part Number Fix Status CY9DF125BPMC-GSE2 CY9DF125EBPMC-GSE2 No silicon fix planned. Use workaround. No silicon fix planned. Use workaround. [3]. IRQ Unit Register Read Timing Issue No silicon fix planned. Use workaround. [4]. Flash Erase Suspend Internal No silicon fix planned. Use workaround. [5]. IUNIT Interrupt Handling Problem No silicon fix planned. Use workaround. [6]. IUNIT Nesting Level Status Problem No silicon fix planned. Use workaround. [7]. 1.2V LVD VDP3 Supply Problem No silicon fix planned. Use workaround. [8]. SCT Compare Value Update Limitation No silicon fix planned. Use workaround. [9]. Clock Supervisor Disable-Enable Problem No silicon fix planned. Use workaround. [10]. Flash Execution Limitation No silicon fix planned, no workaround available. [11]. Automatic ADC Input Disable Problem No silicon fix planned, no workaround available. [12]. RTC Configuration Synchronisation Problem No silicon fix planned. Use workaround. [13]. PSS Wakeup Problem No silicon fix planned. Use workaround. [14]. Port Pin Output Function Select Problem No silicon fix planned. Use workaround. Document Number: 002-05677 Rev. *C Page 390 of 423 CY9DF125 - Atlas-L 1. TCFlash Programming ■ Problem Definition A problem was found in the logic of the TCFlash Interface in the CY9DF125 series.Because of this problem the behaviour of the TCFlash programming is not working as specified. This problem is called ‘TCFlash programming Problem’. ■ Parameters Affected All part numbers of the CY9DF125 series are affected. ■ Trigger Condition(s) Programming the TCFlash with ECC is not possible with 16 bit access sequences ■ Root Cause Data abort of 16-bit programming sequence. ■ Scope of Impact Not applicable ■ Workaround In order to handle ECC calculation and Flash writes, Flash write in CPU mode is restricted to 32-bit mode. ■ Fix Status There is no plan to change this behavior for CY9DF125 series. Document Number: 002-05677 Rev. *C Page 391 of 423 CY9DF125 - Atlas-L 2. 3V IO Domain ESD Diode ■ Problem Definition A problem was found in the specific use-case of switching off the VDP3 supply (3V IO domain) in the CY9DF125 series. Due to an ESD diode between VDD (core supply) and VDP3 (3V IO domain supply) the voltage on VDP3 does not reach 0V even if not supplied. External components connected to same supply as VDP3 will be supplied with a voltage around 0.55V from VDD supply, hence power saving target in standby modes may not be achieved. This problem is called '3V IO domain ESD diode'. ■ Parameters Affected All part numbers of the CY9DF125 series are affected. ■ Trigger Condition(s) The problem occurs if the supply of the 3V IO domain (VDP3) is switched off. ■ Root Cause There is an ESD diode between VDD and VDP3 in the core supply cell to protect VDD against ESD overvoltage. In case VDP3 supply is switched off then VDP3 is supplied by VDD - Uth (threshold voltage of diode) which is around 1.2V - 0.65V = 0.55V. ■ Scope of Impact Not applicable ■ Workaround ❐ Keep 3V power on in standby modes, or ❐ Switch 3V power off in standby modes, and use separated supplies of MCU and external components to avoid external components being supplied via ESD diode, or ❐ Switch 3V power off in standby modes, and use same supply of MCU and external components, but do not exceed the maximum current limit of forward-biased diode which is 4mA, i.e. current on VDP3 must not exceed 4mA in that case. ■ Fix Status There is no plan to change this behavior for CY9DF125 series. Document Number: 002-05677 Rev. *C Page 392 of 423 CY9DF125 - Atlas-L 3. IRQ Unit Register Read Timing Issue ■ Problem Definition A timing problem was found in the Interrupt Unit (aka IRQ-Unit or I-Unit) on the CY9DF125 series. Due to this problem data from I-Unit registers may be invalid when read at CLK_MEM_I_PD3 frequencies higher than 64MHz (even though CLK_MEM_I_PD3 maximum frequency is specified up to 128MHz). Not affected by this timing issue are ❐ Write accesses to Interrupt Unit ❐ IRQ vector address transfer to CPU via ARM VIC port (if enabled) This problem is called 'IRQ Unit register read timing issue'. ■ Parameters Affected All part numbers of the CY9DF125 series are affected. ■ Trigger Condition(s) ❐ The problem may occur at the following conditions: ❐ CLK_MEM_I_PD3 is set to more than 64MHz, and ❐ Data is read from I-Unit addresses (0xB0400000 - 0xB0400D57) or IRQ0_NMIVAS mirror register at address 0xFFFEFBFC Since occurrence of this timing issue is depending on logic path delays the probability of reading invalid data is increasing with: ❐ Higher temperature conditions than room temperature ❐ Lower voltage conditions on VDD supply than nominal 1.2V ❐ Wafer process slow conditions ■ Root Cause The root cause for this problem is a misinterpretation of the internal specification document, which states that one wait cycle is inserted in AHB read transactions while reading of all registers of the interrupt controller module. In the RTL design there is one additional wait cycle added on the AHB bus, but internally, there was just one pipeline register added to the register read paths. With this, the valid read data is captured after one clock cycle, and then simply delayed by another clock cycle. For creating the timing constraining of the interrupt controller module, it was wrongly assumed that the register read data actually has two clock cycles 'time' until it is being captured (and then output to the AHB bus). This assumption then led to the incorrect introduction of a multicycle_path definition in the timing constraints file, which effectively causes a frequency relaxation of a factor of 2 for all register read accesses to interrupt controller registers. ■ Scope of Impact Not applicable ■ Workaround Refer to Workaround for IRQ Unit Register Read Timing Issue on page 410. ■ Fix Status Cypress is proposing Workaround for IRQ Unit Register Read Timing Issue on page 410. Hardware redesigns are not planned. Document Number: 002-05677 Rev. *C Page 393 of 423 CY9DF125 - Atlas-L 4. Flash Erase Suspend Internal ■ Problem Definition The functional limitation was found with Flash memory implemented in the CY9DF125 series. Data may not be read correctly irrespective on the state of erase suspend after the sector erase suspend command is issued to the Flash memory during sector erase. ■ Parameters Affected All part numbers of the CY9DF125 series are affected. ■ Trigger Condition(s) The limitation may occur under the all of following conditions are met: ❐ The sector erase suspend command is issued during sector erase. ❐ After it is shifted to the sector erase suspend state, the read operation from the same Flash memory is performed. ■ Details of the Limitation Data may not be read correctly irrespective of the large sectors or small sectors if the following operations are executed in ❐ The sector erase suspend command is issued to the flash memory during sector erase. ❐ After the state of the sector erase suspend is completed, the reading operation for the flash memory (instruction read or data read) is performed. In this case the read data are undefined. After this read data will remain undefined until the sector erase resume command is issued. Combination of operating conditions for flash memories is the following table. Table 96. Combination of Operating Conditions for Flash Memories Flash memory to which the sector erase suspend command is issued Flash memory from which data Read value of data in the sector is read erase suspend state 1 TC Flash-A TC Flash-A Undefined 2 TC Flash-B TC Flash-B Undefined 3 EE Flash EE Flash Undefined 4 TC Flash-A TC Flash-B / EE Flash Normal 5 TC Flash-B TC Flash-A / EE Normal 6 EE Flash TC Flash-A / TC Flash-B Normal Causes of the Limitation The flash memory control circuit consists of the following two circuits: ❐ The circuit to control automatic algorithm execution for sector erase operation. ❐ The circuit, which receives the sector erase suspend command from the above mentioned circuit, to stop the automatic algorithm execution and to switch to the state where the read operation is enabled. In this case, the circuit to switch the state have a problem, so it cannot to be changed to the state of read operation in case of receiving the sector erase suspend command. ■ Scope of Impact Not applicable ■ Workaround Refer to Workaround for Flash Erase Suspend Internal on page 417. ■ Fix Status Cypress is proposing software workaround specified in Workaround for Flash Erase Suspend Internal on page 417. Hardware redesigns are not planned. Document Number: 002-05677 Rev. *C Page 394 of 423 CY9DF125 - Atlas-L 5. IUNIT Interrupt Handling Problem ■ Problem Definition A problem was found in the logic of the IUNIT in CY9DF125 series. Because of this problem the IUNIT is not working as specified. This problem is called 'IUNIT Interrupt Handling Problem'. ❐ IRQ Priority Level Mask: If enabled IRQ[n] is selected by the priority encoder (no other interrupt with higher priority pending and IRQ0_IRQPLn < IRQ0_IRQPLM) and IRQ0_IRQPLM is changed to IRQ0_IRQPLM ? IRQ0_IRQPLn while the interrupt unit is waiting for the CPU to read the interrupt vector address, the interrupt hold status for IRQ[n] in IRQ0_IRQHSn is not set. • If IRQ[n] is active and IRQ0_IRQPLM is set to IRQ0_IRQPLM > IRQ0_IRQPL[n] before the interrupt flag at the peripheral is cleared and no enabled interrupt with high priority was asserted then IRQ[n] will be selected again for interrupt service. • If IRQ[n]/IRQ[m] is active and IRQ0_IRQPLM is set to IRQ0_IRQPLM > IRQ0_IRQPL[m] > IRQ0_IRQPL[n] after the interrupt flag at the peripheral asserting IRQ[n] is cleared and no enabled interrupt with higher priority was asserted then IRQ[n] will be nested by IRQ[m]. ❐ IRQ/NMI Priority Level: IRQ0_IRQPL0~127, IRQ0_NMIPL0~7 are changed during interrupt priority evaluation. • Wrong IRQ/NMI interrupt number and vector (even the number and vector of a non-existing IRQ/NMI interrupt) can be handed over to the CPU. • One IRQ/NMI interrupt is executed, but the hold status bit of another IRQ/NMI interrupt (or no hold status bit or several hold status bits) may get set. ❐ IRQ/NMI Hold clear: IRQ0_IRQHC, IRQ0_NMIHC are written during interrupt priority evaluation. • Wrong IRQ/NMI interrupt number and vector (even the number and vector of a non-existing IRQ/NMI interrupt) can be handed over to the CPU. ❐ IRQ0_IRQHC byte write access: 8-bit (byte) width write access to IRQ0_IRQHC register triggers the hold clear of partly specified IRQ number. ■ Parameters Affected All part numbers of the CY9DF125 series are affected. ■ Trigger Condition(s) ❐ Enabled IRQ[n] is selected for interrupt service (no other interrupt with higher priority pending and IRQ0_IRQPLn < IRQPLM) and IRQ0_IRQPLM is changed to equal or lower value than IRQ0_IRQPLn before IRQ0_IRQHS is set (point in time when CPU reads the interrupt vector address). ❐ Priorities of active IRQ/NMI are changed during interrupt priority evaluation. ❐ IRQ/NMI Hold Bit is cleared during interrupt priority evaluation. ❐ IRQ0_IRQHC write access with 8-bit access width. ■ Root Cause ❐ Not all inputs of priority encoder are latched during interrupt processing (period from start of priority evaluation until handover to CPU), in this case priority level mask IRQ0_IRQPLM. ❐ Not all inputs of priority encoder are latched during interrupt processing (period from start of priority evaluation until handover to CPU), in this case priority level IRQ0_IRQPL0~127, resp. IRQ0_NMIPL0~7. ❐ Not all inputs of priority encoder are latched during interrupt processing (period from start of priority evaluation until handover to CPU), in this case hold status IRQ0_IRQHS0~15 cleared by IRQ0_IRQHC, resp. IRQ0_NMIHS cleared by IRQ0_NMIHC. ❐ Write strobes for the relevant 2 Bytes of IRQ0_IRQHC are evaluated by OR instead of AND which causes byte write access effects change on full 16 Bit. ■ Workaround Refer to Workaround for IUNIT Interrupt Handling Problem on page 418. ■ Fix Status Cypress is proposing above software workaround specified in Workaround for IUNIT Interrupt Handling Problem on page 418. Hardware redesigns are not planned. Document Number: 002-05677 Rev. *C Page 395 of 423 CY9DF125 - Atlas-L 6. IUNIT Nesting Level Status Problem ■ Description A problem was found in the logic of the IUNIT on CY9DF125 series. Because of this problem the IUNIT Nesting Level Status Register (IRQ0_NESTL) is not working as specified. This problem is called ‘IUNIT Nesting Level Status Register Problem’. Part numbers are listed below. ■ Problem Conditions At least one of the following conditions must occur: ❐ Handover of IRQ vector address to CPU (by VIC protocol) and clearing of IRQ Hold status (by CPU executing ISR) occurs in the same clock cycle ❐ Handover of NMI vector address to CPU (by CPU reading the IRQ0_NMIVAS register) occurs one clock cycle before clearing of NMI Hold status (by CPU executing NMI handler). ■ Affected Devices All part numbers of the CY9DF125 series are affected. ■ Root Cause IRQ0_NESTL:IRQNL: If handover of IRQ vector address to CPU (by VIC protocol) and clearing of IRQ Hold status (by CPU executing ISR) occurs in the same clock cycle, then IRQ0_NESTL:IRQNL is incremented (if it is =0) or decremented (if it is !=0), but its value should not be changed. IRQ0_NESTL:NMINL: If handover of NMI vector address to CPU (by CPU reading the IRQ0_NMIVAS register) occurs one clock cycle before clearing of NMI Hold status (by CPU executing NMI handler) then IRQ0_NESTL:NMINL is incremented (if it is =0) or decremented (if it is !=0), but its value should not be changed. ■ Workaround Do not evaluate the value returned by reading IUNIT Nesting Level Status Register (IRQ0_NESTL). If software needs information about the current nesting level, a variable counter can be implemented which is incremente/decremented in the interrupt handler entry/exit code. ■ Fix Status Cypress is proposing above software workaround. Hardware redesigns are not planned. Document Number: 002-05677 Rev. *C Page 396 of 423 CY9DF125 - Atlas-L 7. 1.2V LVD VDP3 Supply Problem ■ Description A problem was found in the CY9DF125 series in the behaviour of the 1.2V Low Voltage Detection (1.2V LVD, which is supervising the 1.2V core supply VDD) which is linked to the VDP3 supply voltage. Because of this problem the 1.2V LVD may not output power-good even if VDD supply is above set limit of LVD. This may cause prevention of system startup after power-on and reset release and/or wrong 1.2V LVD behavior (Reset/Interrupt) at RUN and PSS mode. This problem is called ‘1.2V Low Voltage Detection – VDP3 Supply problem’. Part numbers are listed below. ■ Problem Conditions The problem may occur at the following conditions: ❐ VDD is above set limits of 1.2V LVD (set by default to 0.8V lower limit at reset) ❐ 1.2V LVD is enabled (enabled by default at reset) ❐ VDP3 supply is smaller than 2.2V ■ Affected Devices All part numbers of the CY9DF125 series are affected. ■ Root Cause The band-gap reference (BGR) of 1.2V LVD (supervising 1.2V core supply VDD) is connected to VDP3 supply. If VDP3 supply is 0x0000 0x017F01BF --> 0x20DF Any code fetch (after translation) from flash address 0x0000 - 0x20DF will be prohibited, which effectively covers 0x0000 - 0x3FFF area since code fetches are always done with 64-bit width. A correct implementation would need to compare the access with two areas: 0x0000 - 0x00DF and 0x2000 - 0x20DF ■ Workaround None, but read accesses are not prohibited, hence the affected regions can be used for constants. ■ Fix Status There is no plan to change this behaviour for CY9DF125 series. Document Number: 002-05677 Rev. *C Page 401 of 423 CY9DF125 - Atlas-L 11.Automatic ADC Input Disable Problem ■ Description A problem was found in port pin multiplexing in CY9DF125 series. This problem is called “Automatic ADC Input Disable Problem”. Intended function: For pins with an ADC input, the digital input buffer is disabled irrespective of the PPC_PCFGRijj:PIE value if the corresponding ADC channel is enabled i.e. if the corresponding bit of the ADCn_ER32/ADCn_ER10 register is set to ’1’. Problem: On CY9DF125 series: Using ADC input of pin P0_40 de-activates the digital inputs of pin P0_15 and P0_40. Using ADC input of pin P2_41 de-activates the digital inputs of pin P0_08 and P2_41. Using ADC input of pin P2_42 de-activates the digital inputs of pin P0_09 and P2_42. Using ADC input of pin P2_43 de-activates the digital inputs of pin P0_10 and P2_43. Using ADC input of pin P2_44 de-activates the digital inputs of pin P0_11 and P2_44. Using ADC input of pin P2_45 de-activates the digital inputs of pin P0_12 and P2_45. Using ADC input of pin P2_46 de-activates the digital inputs of pin P0_13 and P2_46. Using ADC input of pin P2_47 de-activates the digital inputs of pin P0_14 and P2_47. ■ Affected Devices All part numbers of the CY9DF125 series are affected. Problem Conditions The problem occurs if the following conditions are met On CY9DF125 series: • Pin P0_40 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE15 to ‘1’) ■ and • Pin P0_15 is used as GPIO INPUT function or Peripheral INPUT function or • Pin P2_41 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE08 to ‘1’) and • Pin P0_08 is used as GPIO INPUT function or Peripheral INPUT function or • Pin P2_42 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE09 to ‘1’) and • Pin P0_09 is used as GPIO INPUT function or Peripheral INPUT function or • Pin P2_43 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE10 to ‘1’) and • Pin P0_10 is used as GPIO INPUT function or Peripheral INPUT function or • Pin P2_44 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE11 to ‘1’) and • Pin P0_11 is used as GPIO INPUT function or Peripheral INPUT function or Document Number: 002-05677 Rev. *C Page 402 of 423 CY9DF125 - Atlas-L • Pin P2_45 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE12 to ‘1’) and • Pin P0_12 is used as GPIO INPUT function or Peripheral INPUT function or • Pin P2_46 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE13 to ‘1’) and • Pin P0_13 is used as GPIO INPUT function or Peripheral INPUT function or • Pin P2_47 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE14 to ‘1’) and • Pin P0_14 is used as GPIO INPUT function or Peripheral INPUT function ■ Cause of Failure Misconnection of the ADC channel enable and the digital input disable of affected pins. ■ Workaround None, don’t use affected pin pairs as ADC input and as GPIO INPUT or Peripheral INPUT at same time. ■ Fix Status • There is no plan to change this behavior for CY9DF125 series. Document Number: 002-05677 Rev. *C Page 403 of 423 CY9DF125 - Atlas-L 12.RTC Configuration Synchronisation Problem ■ Description A problem was found in synchronization architecture of the RTC in CY9DF125 series. This problem is called “RTC Configuration Synchronization Problem”. In the case of two consecutive write accesses to RTC_WTCR register it could happen that the values UPCAL, SCAL[2:0], ENUP, ACAL are synchronized as random values into the CLK_MAIN clock domain or cannot be changed inside CLK_MAIN clock domain until next hard reset occurrence. In the case of two consecutive write accesses to RTC_WTCR register it could happen that the values RCKSEL[1:0], CSM are synchronized as random value into the RTC clock domain or cannot be changed inside RTC clock domain until next hard reset occurrence. That UPCAL, SCAL[2:0], ENUP, ACAL, RCKSEL[1:0], CSM cannot be changed in CLK_MAIN or RTC clock domain cannot be identified by reading back RTC_WTCR. ■ Parameters Affected All part numbers of the CY9DF125 series are affected. ■ Problem Conditions The problem could occur if the following conditions are met: Two write accesses to RTC_WTCR are performed within less than 10 times the period of slowest clock out of CLK_MAIN, previous and new CLK_S_RTC and CLK_CFG_PD1 in between. Figure 28. RTC Timer Module Diagram Document Number: 002-05677 Rev. *C Page 404 of 423 CY9DF125 - Atlas-L ■ Cause of Failure The synchronization of the random data for UPCAL, SCAL[2:0], ENUP, ACAL into the CLK_MAIN clock domain is caused if the data sampled in CLK_CFG_PD1 domain changes at sampling by CLK_MAIN. The synchronization of the random data for RCKSEL[1:0], CSM into the RTC clock domain is caused if the data sampled in CLK_CFG_PD1 domain changes at sampling by CLK_S_RTC. The locking of UPCAL, SCAL[2:0], ENUP, ACAL inside CLK_MAIN clock domain until hard reset occurrence is caused if the second write access occurs during handshake of synchronization flag. The locking of RCKSEL[1:0], CSM inside RTC clock domain until hard reset occurrence is caused if the second write access occurs during handshake of synchronization flag. The waveform in Figure 29 shows the principle of handshake interference which causes a deadlock. Figure 29. Handshake Synchronization ■ Workaround ❐ Please ensure that after a write accesses to RTC_WTCR there is no write to RTC_WTCR for 10 times the period of slowest clock out of CLK_MAIN, previous and new CLK_S_RTC and CLK_CFG_PD1. • Write RTC_WTCR • Read RTC_WTCR to ensure that first write has arrived at RTC due to CPU store buffer. • Wait 10 times the period of slowest clock out of CLK_MAIN, previous and new CLK_S_RTC and CLK_CFG_PD1 before next write access to RTC_WTCR. ■ Fix Status There is no plan to change this behaviour for CY9DF125 series. Document Number: 002-05677 Rev. *C Page 405 of 423 CY9DF125 - Atlas-L 13.PSS Wakeup Problem ■ Description A problem was found at wakeup from Power Saving State (PSS) in CY9DF125 series. This problem is called “PSS Wakeup Problem”. At wakeup from PSS, an unexpected Non-Maskable Interrupt (NMI) will appear if the PSS profile settings meet certain conditions. ■ Affected Devices All part numbers of the CY9DF125 series are affected. ■ Condition The problem will occur if the following conditions are met: The device is in PSS state and receives a wakeup event AND the RC oscillator is OFF in PSS state (SYSC_PSSCKSRER:RCOSCEN=0) AND the Low Voltage Detection (LVD) threshold settings differ between RUN and PSS profile ( (SYSC_RUNLVDCFGR:SV12[2:0] != SYSC_PSSLVDCFGR:SV12[2:0]) OR (SYSC_RUNLVDCFGR:SV33[2:0] != SYSC_PSSLVDCFGR:SV33[2:0]) OR (SYSC_RUNLVDCFGR:SV50[2:0] != SYSC_PSSLVDCFGR:SV50[2:0]) ). ■ Cause of Failure Before the transition from RUN to PSS state, the PSS profile is checked for validity. If the PSS profile is not valid, SYSC_SYSSTSR:IPPAPSS would be set and a transition to PSS would not be possible. When the profile was good and the device has entered the PSS state, following happens after a wakeup event: ❐ The fast RC oscillator is started (in case it was OFF in PSS) ❐ An unintended PSS profile check is executed, caused by a logic bug ❐ The RUN profile is checked normally as described in hardware manual Figure 30. PSS to RUN State Switching Document Number: 002-05677 Rev. *C Page 406 of 423 CY9DF125 - Atlas-L Usually, the unintended PSS profile check has no effect because of the PSS profile was already checked at the preceding RUN to PSS transition. However, at startup, the following invalid PSS profile setting rule builds an exception: After wakeup, the APP profile of LVD already holds the settings for RUN state. Now the mentioned rule compares the LVD threshold settings (APP differ from PSS?), and if the RC oscillator is disabled in PSS, the rule is fulfilled, the PSS profile error flag SYSC_SYSERRR:PSSERRIF is set and NMI is triggered. ■ Workaround ❐ Do not use the combination of settings mentioned in Condition on page 406. ❐ If the mentioned combination of settings was applied, execute and handle this particular NMI exception by ignoring it once after every wake-up. ■ Fix Status There is no plan to change this behavior for CY9DF125 series. Document Number: 002-05677 Rev. *C Page 407 of 423 CY9DF125 - Atlas-L 14.Port Pin Output Function Select Problem ■ Problem Description A problem was found in the logic of the port pin multiplexing on 32-bit FCR4 Cluster Series MCUs. Because of this problem the behaviour of the port pin multiplexing is not working as specified. This problem is called ‘Port Pin Output Function Select Problem’. ■ Problem Conditions The problem occurs if the port pin output function select value ‘010’ is programmed for port pin P2_40, P2_41, P2_42 or P2_43. ■ Cause of Failure The port pin output function select value ‘010’ for port pin P2_40, P2_41, P2_42, P2_43 does not select the specified output function. ■ Workaround Do not program pin output function select value ‘010’ for port pin P2_40, P2_41, P2_42, P2_43. To use the resources specified for port pin output function select value ‘010’ on port pin P2_40, P2_41, P2_42, P2_43 select another specified port pin location for the corresponding resource functional output. Note: The pin output function RTC_WOT, SYSC_CKOT, SYSC_CKOTX, WDG_OBSERVE specified on port pin P0_40, P0_41, P0_42, P0_43 are only supported when power domain PD2 is active. ■ Fix Status There is no plan to fix this limitation. SW workaround is available. Document Number: 002-05677 Rev. *C Page 408 of 423 CY9DF125 - Atlas-L Ordering Information Table 99. Ordering Information Part Number Package Remarks CY9DF125BPMC-GSE2 176-pin plastic LQFP LQP-176 Lead-free package 4 SMC variant CY9DF125EBPMC-GSE2 176-pin plastic LQFP LQP-176 Lead-free package 6 SMC variant Document Number: 002-05677 Rev. *C Page 409 of 423 CY9DF125 - Atlas-L Appendix Workaround for IRQ Unit Register Read Timing Issue General Considerations It is assumed that for normal operation of the MCU and most use cases it is not necessary to read back any I-Unit registers, i.e. the application software e.g. knows which vector addresses are configured, which priorities are set and which IRQ channels are enabled. Furthermore, it is assumed that for IRQ handling the application enables the ARM VIC port which is not affected by the read timing issue. It is not necessary to poll the I-Unit lock status bit (IRQ0_CSR_LST) after unlocking/locking the I-Unit. This bit does not indicate any I-Unit internal time consuming operations. Its purpose is to inform the application about the current lock state so that exceptions caused by double unlocking or locking can be avoided. This can also be implemented with software means (e.g. semaphore). For debugging during development or error logging purposes it may be useful to read certain status registers from the I-Unit (e.g. IRQ0_IRQST, IRQ0_EAN) which still can be done but it must be regarded that the gathered information may not be reliable. Considering above mentioned assumptions the only functionality that is affected by the read timing issue is the NMI handling. FCR4 MCUs by default use the ARM “high exception vectors” option with exception vector table located at address 0xFFFF0000. This area is implemented as ROM and its contents are not changeable. The instruction placed at the FIQ exception vector (Note: FIQ and NMI are used synonymously throughout the document) will read from the NMIVAS mirror register at address 0xFFFEFBFC to retrieve the branch target. Due to the read timing issue the target address is not reliable and the read must be prevented. Following two workarounds exist to overcome this situation and still provide NMI functionality. ■ Workaround #1 (MPU) on page 411 using Memory Protection Unit ' preventing the read from NMIVAS mirror ■ Workaround #2 (Low Exception) on page 414 using ARM “low exception vector” option ' allowing to replace the instruction at FIQ exception vector All described preparatory steps in these workarounds (e.g. MPU configuration) must be completed before application enables NMIs (clearing of 'F'-bit in CPU Current Program Status Register). If these workarounds are used, it is also not necessary to initialize the NMI specific I-Unit registers (NMI priorities, NMI vectors). Software samples are provided to demonstrate both workarounds: ■ Workaround #1: fcr4_nmi_mpu_mbxxxxx-vxx ■ Workaround #2: fcr4_nmi_low_exception_mbxxxxx-vxx Document Number: 002-05677 Rev. *C Page 410 of 423 CY9DF125 - Atlas-L Workaround #1 (MPU) Overview In general this workaround aims to detect the read access to the IRQ0_NMIVAS mirror register from the instruction at the FIQ exception vector. The NMIVAS mirror register is located at address 0xFFFEFBFC which will be secured by a memory protection region supported by the ARM core MPU. The flowchart below introduces the process of the workaround when the application code is interrupted by an NMI event. Figure 31. Workaround #1 Software Flow Protected area with no access permission 0xFFFEFBFC Permission fault leads to Data Abort exception NMIVAS mirror Read address of NMI Exception Handler Application code . . . NMI event Exception table 0xFFFF0010 Data Abort Exception Data Abort Exception Handler 0xFFFF001C FIQ Exception Evaluation of Data Abort cause: NMI exception in case of access to NMIVAS mirror register (0xFFFEFBFC) ... Regular data abort exception handling User Data Abort Exception Handler NMI Dispatcher Dummy read (non-mirrored) NMIVAS Evaluation of NMI cause by checking all NMI flags in relevant ressources. Branch to corresponding User NMI Handler User NMI Handler Clear corresponding NMI flag Clear all NMI Hold bits Return to application code Description 1. Each non-maskable interrupt will cause an FIQ exception and the instruction at address 0xFFFF001C is executed. The instruction reads the vector for the NMI exception handler. This vector is determined by the I-Unit and made available via NMIVAS register and because of the mentioned hardware fault in the I-Unit cannot be read reliably. In order to prevent a branch to a corrupted NMI vector address the access to NMIVAS mirror register at address 0xFFFEFBFC must be protected by an ARM MPU region. 2. When the FIQ exception instruction accesses the NMIVAS mirror register, a Data Abort exception will occur because of the MPU protection. 3. After the Data Abort handler is entered the Data Fault Status Register (DFSR) and Data Fault Address Register (DFAR) which are located in System Control coprocessor and the CPU Link Register (R14) are evaluated to determine whether the Data Abort was caused by the occurrence of an NMI. Conditions for NMI cause: • Data Fault Status Register • DFSR[10,3:0] = 0b01101 (Permission Fault) • DFSR[11] = 0 (read access) • Data Fault Address Register • DFAR = 0xFFFEFBFC (NMIVAS mirror register) • Link Register R14_abt = 0xFFFF0024 shows that an NMI caused the abort (0xFFFF001C + 0x8) Before evaluation starts all CPU registers modified by the code are pushed on Data Abort stack (R13_abt). Document Number: 002-05677 Rev. *C Page 411 of 423 CY9DF125 - Atlas-L 4. There are two cases depending on this evaluation result: a. In case not all conditions are true the Data Abort was not caused by the occurrence of an NMI. The modified registers are restored from the stack and the Data Abort handler branches to the user's Data Abort handler ("branch without link" ' Link Register is not modified). This behavior is transparent for the user's Data Abort handler which can be written assuming that the handler is directly executed from a Data Abort exception b. In case all conditions are true, the Data Abort was caused by the occurrence of an NMI. Data Fault Status and Data Fault Address register are explicitly cleared to prevent a repetitive NMI handling in case an NMI occurred shortly after a "normal" Data Abort. After that, the modified registers are restored from the stack and the CPU mode is changed from "Abort" to "FIQ". The program continues at NMI Dispatcher function where a dummy read to the NMIVAS register is done, because this read has the I-Unit internal effect of deasserting the nFIQ CPU signal and setting the NMI Hold bit of the NMI which has won I-Unit priority decision. Finally, the NMI cause must be evaluated. This is done by checking all NMI flags in the corresponding peripheral resources (availability may vary for different FCR4 derivates). As it is not possible to reliably read the I-Unit ECC Double Bit Error NMI flag (IRQ0_EEI_EENS) the software must assume that this is the NMI cause in case no other NMI is present. Once the NMI cause has been detected, the software can branch to the user's NMI handler. Before doing the "branch without link", the stack and registers should be restored (if used by NMI Dispatcher), as the user handler will directly return to the program location where the NMI occurred. 5. The user NMI handler must be changed as described in “Changes to User NMI Handler” on page 416. It will directly return to the application code. ARM MPU Configuration The MPU is a part of Cortex-R4 MCU and can be configured via System Control Coprocessor. It controls the accesses to defined memory regions with the configuration of permission rights. For protection of NMIVAS mirror register this function will be used in following way: The setup of MPU is done by defining ■ Region number ■ Region access permissions ■ Region size and enable setting ■ Region base address The region number with the highest priority ('11') must be chosen. The access permission must be set to 'No Access' in User and in Privileged Mode. The region size (bit 5..1) is set to minimum size (32 byte) which will not influence any other used memory area. Bit 0 enables the configured MPU setup. It must be ensured that the region base address is 32 byte aligned and the NMIVAS mirror address is within the given region size. In addition two more settings in the System Control Register (also located in System Control Coprocessor) must be done for activating the MPU function: ■ M (bit 0) = 1: MPU enable ■ BR (bit 17) = 1: MPU background region enable Refer to the ARM Cortex-R4 Technical Reference Manual and the provided software sample for information on how to configure and enable the MPU. Document Number: 002-05677 Rev. *C Page 412 of 423 CY9DF125 - Atlas-L Configuration Sequence Following configuration sequence for this workaround is recommended: 1. Reset (High Exception Vectors active, FIQ/NMI masked, IRQ masked). 2. Configure MPU to prohibit access to NMIVAS mirror register. 3. Enable NMI processing in CPU (clear 'F'-bit in CPSR register). 4. Configure IRQ vector table, priority levels and channel enable status in I-Unit. 5. Enable VIC port (to enable IRQ processing via not-affected VIC port). 6. Enable IRQ processing in I-Unit (IRQ0_CSR_IRQEN). 7. Enable IRQ processing in CPU (clear 'I'-bit in CPSR register). Workaround Limitations Following limitations need to be considered if this workaround is used: ■ NMI dispatcher and all called NMI handlers must not allow NMI nesting If NMIs would be re-enabled (clearing of 'F'-bit in CPU Current Program Status Register), another NMI exception could occur. In case the NMI flag of the already handled NMI is evaluated again by the new/nested NMI Dispatcher function, the same handler will be called again. Further, error scenarios are imaginable which can also result in some inconsistent state. ■ Return from a "normal" Data or Prefetch Abort may not be possible It can happen that while a “normal” Data or Prefetch Abort handler is currently executed an NMI occurs because they are not masked on Abort exception entry. As a consequence this NMI will lead to another Data Abort exception that overwrites the original SPSR_abt and R14_abt CPU register values, and the Fault Status Registers in the System Control Coprocessor. This makes it impossible for the user's Data or Prefetch Abort handler to return to application or correctly evaluate the circumstances (e.g. program location and processor state) of the original Abort. Basically, a similar behavior can occur on any ARMv7-R architecture if another precise Abort occurs while an Abort handler is executed. Document Number: 002-05677 Rev. *C Page 413 of 423 CY9DF125 - Atlas-L Workaround #2 (Low Exception) Overview The application needs to set up an exception table at the “low exception table” location at address 0x0 (inside TCMRAM) and afterwards make this the active table. With this solution the instruction at the FIQ exception vector can be chosen arbitrarily and so the read to NMIVAS register is avoided. Description Preconditions For the implementation shown in the software samples the linker settings of the application must ensure that 64 bytes starting from address 0x0 are reserved for the low exception table and corresponding handler addresses (address area 0x00 - 0x3F). Exception Table Setup The exception table in ARMv7-R architecture is defined as provided in Table 100. Table 100. ARMv7-R Exception Table Pin Signal 0x00 Reset 0x04 Undefined Instruction 0x08 Supervisor Call / (Software Interrupt) 0x0C Prefetch Abort 0x10 Data Abort 0x14 reserved 0x18 IRQ (if VIC port disabled) 0x1C FIQ Typically, a LDR PC, [PC, #+/-] instruction is placed at each of these exception vectors which will do a 32-bit read at a PC-relative location and move this value to the PC (= branch to this address). In ARM terminology the data that is read are called "literals". These literals are the addresses of the corresponding exception handler functions. In the sample software, the exception table and literals are setup in the following way: Table 101. Exception Table Setup in Sample Software Absolute Address Content 0x00 don’t care (on reset high exception table is getting active anyway) 0x04 LDR PC, [PC, #+0x18] 0x08 LDR PC, [PC, #+0x18] 0x0C LDR PC, [PC, #+0x18] 0x10 LDR PC, [PC, #+0x18] 0x14 don’t care 0x18 LDR PC, [PC, #+0x18] 0x1C LDR PC, [PC, #+0x18] 0x20 don’t care 0x24 Address of Undefined Instruction handler 0x28 Address of Supervisor Call handler 0x2C Address of Prefetch Abort handler 0x30 Address of Data Abort handler 0x34 don’t care 0x38 Address of IRQ handler (in case VIC port disabled) 0x3C Address of special NMI dispatcher function (see Description of NMI Dispatcher) Document Number: 002-05677 Rev. *C Page 414 of 423 CY9DF125 - Atlas-L The offset value in the LDR PC, [PC, #+0x18] instruction regards the fact that in ARMv7-R architecture the PC always points to the address of the currently executed instruction + 0x8 0x18 + 0x8 = 0x20 offset between instruction and corresponding literal. MPU protection of low exception table (optional) Especially when considering the probability of immature software using uninitialized NULL pointers it is recommended to protect the low exception table and related literals against accidental write accesses by setting up a read-only MPU region for that address area. Refer to the ARM Cortex-R4 Technical Reference Manual and the provided software sample for information on how to configure and enable the MPU. Switching the active exception table In order to make the low exception table active, the 'V' bit (bit 13) in the System Control Register of the System Control Coprocessor must be cleared. Description of NMI Dispatcher The same NMI Dispatcher as for Workaround #1 is also used for workaround #2. This function executes a dummy read to the NMIVAS register, because this read has the I-Unit internal effect of deasserting the nFIQ CPU signal and setting the NMI Hold bit of the NMI which has won I-Unit priority decision.Finally, the NMI cause must be evaluated. This is done by checking all NMI flags in the corresponding peripheral ressources (availability may vary for different FCR4 derivates). As it is not possible to reliably read the I-Unit ECC Double Bit Error NMI flag (IRQ0_EEI_EENS) the software must assume that this is the NMI cause in case no other NMI is present. Once the NMI cause has been detected, the software can branch to the user's NMI handler. Before doing the "branch without link", the stack and registers should be restored (if used by NMI Dispatcher), as the user handler will directly return to the program location where the NMI occurred. The user NMI handler must be changed as described in “Changes to User NMI Handler” on page 416. Configuration Sequence Following configuration sequence for this workaround is recommended: 1. Reset (High Exception Vectors active, FIQ/NMI masked, IRQ masked) 2. Create Low Exception Vector table @ 0x00000000 3. Configure MPU to protect exception vector table in TCMRAM 4. Switch to Low Exception Vector table 5. Enable NMI processing in CPU (clear 'F'-bit in CPSR register) 6. Configure IRQ vector table, priority levels and channel enable status in I-Unit 7. Enable VIC port (to enable IRQ processing via not-affected VIC port) 8. Enable IRQ processing in I-Unit (IRQ0_CSR_IRQEN) 9. Enable IRQ processing in CPU (clear 'I'-bit in CPSR register) Workaround Limitations Following limitations need to be considered if this workaround is used: ■ NMI dispatcher and all called NMI handlers must not allow NMI nesting If NMIs would be re-enabled (clearing of 'F'-bit in CPU Current Program Status Register), another NMI exception could occur. In case the NMI flag of the already handled NMI is evaluated again by the new/nested NMI Dispatcher function, the same handler will be called again. Further error scenarios are imaginable which can also result in some inconsistent state. Document Number: 002-05677 Rev. *C Page 415 of 423 CY9DF125 - Atlas-L Changes to User NMI Handler The limitation and workarounds covered by this document result in necessary changes to the user NMI handlers. A different NMI handler exit code is required for correct operation. Instead of only clearing the corresponding NMI Hold bit, all NMI Hold bits must be cleared (as currently set Hold Bit cannot be read back from I-Unit). If this is not done a problem can occur in case of multiple pending NMIs. The software NMI dispatcher may have evaluated a different “winning” NMI than the I-Unit hardware logic (in case of multiple pending NMIs), because it uses the ressource NMI flags to determine pending NMIs. Consequently, the NMI Hold bit would not be cleared by the user NMI handler and this prevents the I-Unit from asserting the nFIQ signal to CPU again for this still pending and not yet handled NMI. Ordering of NMI Flag Evaluation In the event of an NMI no information can be read from the I-Unit, hence the NMI flag(s) of all resources that can generate NMIs need to be evaluated. Following order of NMI flag evaluation is used in the provided software samples: 1. Low voltage detection NMI 2. System controller error NMI 3. External NMI pin 4. Watchdog NMI 5. Timing Protection Unit NMI 6. MPU DMA Access Violation NMI 7. MPU IRIS Access Violation NMI (if available) 8. MPU MLB0 Access Violation NMI (if available) 9. Bus Error Collection Unit BECU0 Access Violation (Peripheral group 0) 10.Bus Error Collection Unit BECU1 Access Violation (Peripheral group 1) 11.Bus Error Collection Unit BECU3 Access Violation (Peripheral group 3) 12.Iris Signature Unit NMI (if available) 13.MPU SHE Access violation (if available) 14.IRQ Double Error NMI The order may be re-arranged to decrease NMI latency for certain use cases, except "IRQ Double Error NMI", which must remain on last position as it must be determined by exclusion principle. Writing I-Unit Registers Care must be taken when writing code for the initialization of I-Unit registers. Any code that would result in RMW (Read-Modify-Write) accesses must be avoided. RMW accesses may be generated if register bit field types are used for assigning values. Example: If priority level for IRQ channel 2 shall be set to 19: C-Code: .... I RQ0_IRQPL0_IRQPL2 = 19; (wrong!) Compiler Output: ....... 32-bit read of IRQ0_IRQPL0 register .. ....... Modify bits belonging to IRQPL2 bit field 32-bit write of IRQ0_IRQPL0 register Because the read of this RMW access is affected by the limitation described in this Customer Information there is the chance that the other priority levels in the same register are getting corrupted. Document Number: 002-05677 Rev. *C Page 416 of 423 CY9DF125 - Atlas-L Workaround for Flash Erase Suspend Internal To avoid this limitation, the following workaround by software is recommended. After the flash sector erase suspend operation (issue of the suspend command + verification of DQ6/TOGG1 bit) is finished, check the hardware sequence flag DQ4 bit indicating the specific internal state which can read flash or not (see Figure 32). If the value of DQ4 bit is "1" then issue the sector erase resume command and restart the sector erase suspend operation after the waiting time. Figure 32. Workaround by Software Please note the following factors of internal circuit when using the software workaround: ■ At least 2 ms waiting time is required to restart the sector erase suspend operation after the resume command is issued by DQ4 == "1" (see *1 in Figure 32). ■ Approximately a maximum of 10 ms would be required for DQ4 to become "0" after the suspend command is issued first. Though DQ4 is an undefined bit on the hardware manual, it can be used to read the internal sequence state which can read from flash or not. If DQ4 =="0", it indicates the internal state which can read from flash. But if DQ4 =="1", internal circuit have not switch to the state of read flash. See the following table representing bit assignment of DQ4 bit for FCR4 family. Table 102. Bit Assignment of Hardware Sequence Flags (Cypress FCR4 Family) Read data bit no. 7 6 5 4 3 2 1 0 Hardware sequence flag DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 - - Read data bit no. 15 14 13 12 11 10 9 8 Hardware sequence flag DQ15 DQ14 DQ13 - DQ11 DQ10 - - The following software products (all releases) are not affected by this limitation, because they do not use erase suspend: ■ FCR4 MCAL (SW-MCAL31-DRV-FCR4-E01, SW-MCAL31-DRV-FCR4-E02, SW-MCAL40-DRV-FCR4-E01), ■ FCR4 FEE/FLS (SW-FEEFLS-DRV-FCR4-E01, SW-FEE40-DRV-FCR4-E01) Document Number: 002-05677 Rev. *C Page 417 of 423 CY9DF125 - Atlas-L Workaround for IUNIT Interrupt Handling Problem 1. To change the IRQ Priority Level Mask Register (IRQ0_IRQPLM) use the following workaround: a. Safe sequence to change IRQ0_PLM (temporarily disable interrupt processing and perform wait until IUNIT idle) SuspendAllInterrupts(); // globally disable all IRQs with // 'I'-bit in CPU CPSR IRQ0_UNLOCK = ; IRQ0_CSR = 0; // setting IRQEN bit to '0' IRQ0_CSR; // dummy read to generate wait cycles // until state machine has returned to // idle state IRQ0_IRQPLM = ; IRQ0_CSR = 1; // setting IRQEN bit to '1' IRQ0_UNLOCK = ; ResumeAllInterrupts(); // restore previous state of 'I'// bit in CPU CPSR extension for each ISR entry code (check if corresponding IRQ0_IRQPL[n] < current IRQ0_IRQPLM) Pseudocode: __interrupt void Interrupt_1_Handler(void) { // Check if priority of current IRQ is higher (means lower value) // than the currently active priority level mask if (Interrupt_1_Prio < Current_PLM_Value) { // The interrupt is "valid" and corresponding code // shall be executed // Call user callback function, which is also responsible // for clearing the interrupt flag in the peripheral .... } // Clear Hold-Bit of Interrupt_1 ... } IMPORTANT: 'Interrupt_1_Prio' must be determined indirectly by the called ISR and OS/application internal interrupt priority configuration variable(s). IRQ0_IRQPL0~127 and IRQ0_IRQST:IRQSN must not be read. (see CI707-00026-E_FCR4_IRQ_Unit_register_read_timing_issue) Current_PLM_value must be read from OS/application internal buffer variable IRQ0_IRQPLM must not be read. (see CI707-00026-E_FCR4_IRQ_Unit_register_read_timing_issue) 2. To avoid changing the priority level of an active IRQ interrupt, configure IRQ0_IRQPL0~127 only in initial phase before enabling interrupts by setting IRQ0_CSR.IRQEN=1. 3. With the software workaround explained in CI707-00026-E_FCR4_IRQ_Unit_register_read_timing_issue, it is not necessary to change IRQ0_NMIPL0~7. 4. IRQ Hold Clear - use following sequence to clear the bit: IRQ0_UNLOCK = IRQ0_CSR = 0; // setting IRQEN bit to '0' IRQ0_CSR; // dummy read to generate wait cycles // until IRQ is latched in IUNIT, resp. // state machine returned to idle state IRQ0_IRQHC = // clear Hold-bit of IRQ IRQ0_CSR = 1; // setting IRQEN bit to '1' IRQ0_UNLOCK = Document Number: 002-05677 Rev. *C Page 418 of 423 CY9DF125 - Atlas-L NMI Hold Clear - use following workaround: NMI handling shall be implemented according to workarounds in CI707-00026-E_FCR4_IRQ_Unit_register_read_timing_issue (will not use any potential wrong NMI register values, as reading is prohibited anyway). 5. Perform write access to IRQ0_IRQHC only with 16-bit or 32-bit access width. Document Number: 002-05677 Rev. *C Page 419 of 423 CY9DF125 - Atlas-L Document History Page Document Title: CY9DF125 - Atlas-L, CY9DF125 Series Document Number: 002-05677 Rev. ECN No. ** – Orig. of Change – Submission Description of Change Date 07/27/2011 Initial draft - Change bootrom size to 16K - Add 240 pin trace package - Add resource input tables - Add 240 pin I/O types - Add 240 pin trace package data sheet Update JTAG pin types in chapter 3.4 - Add I/O map chapter - Add Procedures chapter - Update memory map - Pinning of 240 pin package changed - Updated DC characteristics - Add Table 2-10: EBI CFG AHB Bus Memory Map - Naming of PCFGRxx register in chapter 5 I/O updated - Added ADC minimum sampling time - RICFG0_ADC table corrected - Added HSSPI, SPI External Bus Interface timing chapters - Added Lock/unlock values - Added Module ID’s - Update FPP mode entrance - Updated DC characteristics - Improved SPI Timing - External BUS frequency corrected - EBI RDY timing added - I/O map corrected - Updated DC characteristics - RICFG1 table corrected - Remove color from Pin Assignment figures - Extended Boundary Scan chapter - Added ADC Zero Transition Voltage - Correct typo in ordering informations - Added information about VDD3 in power on sequences - Added Pin State while Power-On-Reset table - Corrected clock in UART/I2C AC chapter - Corrected number of Cortex-R4 MPU regions - Incorporated PCN Document No. 001-53350 Rev. *B The following changes have been made in this datasheet: Page 363 / DC Characteristics Power Supply current in PSS mode Page 363 / DC Characteristics, Power supply current in Timer mode *A 5270168 GESC Document Number: 002-05677 Rev. *C 05/20/2016 Updated to Cypress look and feel (cosmetic changes only) Removed references to “VDE5” in all instances across the document. Updated MB9DF125 Features: Updated Table 2 (Updated details in “Description” column corresponding to Resets (Removed “Power on Reset (PoR)” from the list)). Updated ID-Values for Module Identification Registers: Updated Table 15 (Updated details in “ID Value” column corresponding to SYSC_SYSIDR register). Page 420 of 423 CY9DF125 - Atlas-L Document History Page (Continued) Document Title: CY9DF125 - Atlas-L, CY9DF125 Series Document Number: 002-05677 Orig. of Submission Rev. ECN No. Description of Change Change Date *A (cont.) 5270168 GESC 05/20/2016 Updated Package and Pin Assignment: Updated IO Circuit Types: Updated Table 27 (Updated details in “Remarks” column corresponding to BIDI50, BIDI33, TTL33, SMC and I2C IO cell types). Updated Handling Devices: Updated Pin State During Active External Reset: Replaced “Pin State while Power-On-Reset” with “Pin State During Active External Reset” in heading. Updated description. Updated Table 95 (Updated caption only). Added Errata. Updated Ordering Information: Updated Table 99: Updated part numbers. Added Note 33 and referred the same note in MB9DF125PMC-GSE2, MB9DF125EPMC-GSE2, MB9DF125PVFS-ESE2. Updated to Cypress template. *B 5436869 GESC 11/02/2016 Added Features. Updated MB9DF125 Features: Updated Table 1. Updated Package and Pin Assignment: Updated IO Circuit Types: Updated Table 27 (Updated details in “Remarks” column corresponding to MAINOSC (Added a Note at the end)). Updated Electrical Characteristics: Updated DC Characteristics: Updated Table 49. Added ESD Structure between Power Domains. Updated Procedures: Updated Debug and Trace: Updated Table 91. Updated Errata: Updated description; and also table below. Updated Appendix: Updated Workaround for Flash Erase Suspend Internal: Removed table “4 Bit Assignment of Hardware Sequence Flags (FR5 Family)”. Updated to new template. *C 6571343 NOFL 05/28/2019 Updated Document Title to read as “CY9DF125 - Atlas-L, CY9DF125 Series”. Replaced “MB9DF125 Series” with “CY9DF125 Series” in all instances across the document. Removed QFP-240 Package related information in all instances across the document. Updated Package Diagram: Removed existing spec “FPT-240P-M03”. Removed existing spec “FPT-176P-M07”. Added spec 002-15150 **. Document Number: 002-05677 Rev. *C Page 421 of 423 CY9DF125 - Atlas-L Document History Page (Continued) Document Title: CY9DF125 - Atlas-L, CY9DF125 Series Document Number: 002-05677 Orig. of Submission Rev. ECN No. Description of Change Change Date *C (cont.) 6571343 NOFL 05/28/2019 Updated Electrical Characteristics: Updated Absolute Maximum Ratings: Updated Table 46: Updated details corresponding to “Maximum Clamp Current” and “Total Maximum Clamp Current” parameters. Added Note 10 and referred the same note in “Remarks” column corresponding to “Maximum Clamp Current” and “Total Maximum Clamp Current” parameters. Added Figure 6. Updated FLASH Memory Program/Erase Characteristics for TCFLASH and EEFLASH: Replaced “FLASH Memory Program/Erase Characteristics” with “FLASH Memory Program/Erase Characteristics for TCFLASH and EEFLASH” in heading. Updated Procedures: Updated Debug and Trace: Updated Table 91. Updated Errata: Updated description. Updated details in table below description. Removed item “Undefined Port Pin State while Core Supply (VDD) is Unavailable” and its corresponding details. Added item “FL0011 [Port Pin Output Function Select Problem]” and its corresponding details. Updated Ordering Information: Updated Table 99: Updated part numbers. Updated details in “Package” column. Removed Note “These devices are subject to the limitation shown in “Undefined Port Pin State while Core Supply (VDD) is Unavailable” on page 410.” and its references. Updated Appendix: Removed “Limitation Details”. Updated to new template. Completing Sunset Review. Document Number: 002-05677 Rev. *C Page 422 of 423 CY9DF125 - Atlas-L Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2008–2019. 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