PALC22V10D

1P AL C2 2V 10D fax id: 6007 For new designs, please refer to the PALCE22V10. PALC22V10D Flash Erasable, Reprogrammable CMOS PAL® Device Features • Advanced second-generation PAL architecture • Low power — 90 mA max. commercial (10 ns) — 130 mA max. commercial (7.5 ns) • CMOS Flash EPROM technology for electrical erasability and reprogrammability • Variable product terms — 2 x(8 through 16) product terms • User-programmable macrocell — Output polarity control — Individually selectable for registered or combinatorial operation • Up to 22 input terms and 10 outputs • DIP, LCC, and PLCC available — 7.5 ns commercial version 5 ns tCO 5 ns tS 7.5 ns tPD 133-MHz state machine — 10 ns military and industrial versions 6 ns tCO 6 ns tS 10 ns tPD 110-MHz state machine — 15-ns commercial and military versions — 25-ns commercial and military versions • High reliability — Proven Flash EPROM technology 100% programming and functional testing vides the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as “registered” or “combinatorial.” Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through “array” configurable “output enable” for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array. PALC22V10D features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PAL C 22V10D is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. Additional features of the Cypress PALC22V10D include a synchronous preset and an asynchronous reset product term. These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up. The PALC22V10D, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity. Since each of the 10 output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to 12 inputs and 10 outputs are possible. The 10 potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is available for establishing the next result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. Along with this increase in functional density, the Cypress PALC22V10D provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. PAL is a registered trademark of Advanced Micro Devices Functional Description The Cypress PALC22V10D is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell. The PALC22V10D is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. The 22V10D can be electrically erased and reprogrammed. The programmable macrocell pro- Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 1991 – Revised October 1995 PALC22V10D Logic Block Diagram (PDIP/CDIP) VSS 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 CP/I 1 PROGRAMMABLE AND ARRAY (132 X 44) 8 10 12 14 16 16 14 12 10 8 Reset Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Preset 13 I 14 I/O9 15 I/O8 16 I/O 7 17 I/O6 18 I/O5 19 I/O4 20 I/O3 21 I/O2 22 I/O1 23 I/O0 24 VCC V10D–1 Pin Configuration LCC Top View PLCC Top View 4 3 2 1 282726 I I I NC I I I 5 6 7 8 9 10 11 12131415161718 V10D–2 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 I I I NC I I I 5 6 7 8 9 10 11 4 3 2 1 2827 26 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 V10D–3 121314 1516 1718 Configuration Table Registered/Combinatorial C1 0 0 C0 0 1 Configuration Registered/Active LOW Registered/Active HIGH Configuration Table Registered/Combinatorial C1 1 1 C0 0 1 Configuration Combinatorial/Active LOW Combinatorial/Active HIGH 2 PALC22V10D Macrocell AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AR AA AA AA AA AA AA AA OUTPUT AA AA AA AA AA SELECT AA AA AA AA MUX D Q AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA S1 S0 Q CP AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA SP AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA INPUT/ AA AA AA AA AA FEEDBACK AA AA AA MUX AA AA AA AA AA AA AA AA S1 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA MACROCELL AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A C1 C0 V10D–4 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................−65°C to +150°C Ambient Temperature with Power Applied ..................................................−55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................− 0.5V to +7.0V DC Input Voltage............................................. -0.5V to +7.0V Output Current into Outputs (LOW) ............................. 16 mA DC Programming Voltage .............................................12.5V ]] Latch-Up Current ..................................................... >200 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2001V Operating Range Range Commercial Military[1] Industrial Ambient Temperature 0°C to +75°C −55°C to +125°C −40°C to +85°C VCC 5V ±5% 5V ±10% 5V ±10% Note: 1. TA i s the “instant on” case temperature. Electrical Characteristics Over the Operating Parameter VOH VOL VIH VIL IIX IOZ ISC [2] Range[2] Test Conditions Min. Com’l Mil/Ind Com’l Mil/Ind 2.0 -0.5 -10 -40 -30 0.8 10 40 -90 V V µA µA mA Inputs[3] 0.5 V 2.4 Max. Unit V Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL IOH = -3.2 mA IOH = -2 mA IOL = 16 mA IOL = 12 mA Guaranteed Input Logical HIGH Voltage for All Inputs[3] Guaranteed Input Logical LOW Voltage for All VSS < VIN < VCC, VCC = Max. VCC = Max., VSS < VOUT < VCC 0.5V[5,6] Output Short Circuit Current VCC = Max., VOUT = 3 PALC22V10D Electrical Characteristics Over the Operating Range[2] Parameter ICC1 Description Standby Power Supply Current Test Conditions VCC = Max., 10, 15, 25 ns VIN = GND, 7.5 ns Outputs Open in Unprogrammed De- 15, 25 ns vice 10 ns VCC = Max., VIL = 0V, VIH = 3V, Output Open, Device Programmed as a 10-Bit Counter, f = 25 MHz 10, 15, 25 ns 7.5 ns 15, 25 ns 10 ns Com’l Com’l Mil/Ind Mil/Ind Com’l Com’l Mil/Ind Mil/Ind Min. Max. 90 130 120 120 110 140 130 130 Unit mA mA mA mA mA mA mA mA ICC2[6] Operating Power Supply Current Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. Capacitance[6] Parameter CIN COUT Description Input Capacitance Output Capacitance [6] Description Minimum Reprogramming Cycles Test Conditions VIN = 2.0V @ f = 1 MHz VOUT = 2.0V @ f = 1 MHz Min. Max. 10 10 Unit pF pF Endurance Characteristics Parameter N Test Conditions Normal Programming Conditions Min. 100 Max. Unit Cycles AC Test Loads and Waveforms R1238 Ω (319Ω MIL) R1238 Ω (319Ω MIL) OUTPUT CL 750Ω (1.2KΩ MIL) 5V OUTPUT 5V R2170 Ω (236Ω MIL) OUTPUT CL INCLUDING JIG AND SCOPE 5 pF INCLUDING JIG AND SCOPE R2170 Ω (236Ω MIL) (a) 3.0V 90% GND < 2 ns 10% (b) ALL INPUT PULSES 90% 10% < 2 ns (c) (d) Equivalent to: THÉ VENIN EQUIVALENT(Commercial) 99Ω OUTPUT 2.08V=V thc V10D–6 V10D–5 Equivalent to: THÉVENIN EQUIVALENT(Military) 136Ω OUTPUT 2.13V=V thm V10D–7 4 PALC22V10D Load Speed 7.5, 10, 15, 25 ns Parameter t ER (- ) t ER (+) t EA (+) t EA (- ) CL 50 pF Package PDIP, CDIP, PLCC, LCC Output W aveform Measurement Level V OH V OL VX VX 0.5V 0.5V 1.5V VX VX V10D–9 V10D–8 VX 1.5V 2.6V 0V V thc V OH V10D–10 0.5V (e) Test Waveforms V OL V10D–11 5 PALC22V10D Commercial Switching Characteristics PALC22V10D[2, 7] 22V10D-7 Parameter tPD tEA tER tCO tS1 tS2 tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tAW tAR tAP tSPR tPR Description Input to Output Propagation Delay[8, 9] Input to Output Enable Delay[10] Input to Output Disable Delay[11] Clock to Output Delay [8, 9] 22V10D-10 Min. 3 Max. 10 10 10 2 6 7 0 12 3 3 76.9 142 111 7 22V10D-15 Min. 3 Max. 15 15 15 2 10 10 0 20 6 6 55.5 83.3 68.9 8 22V10D-25 Min. 3 Max. 25 25 25 2 15 15 0 30 13 13 33.3 35.7 38.5 15 Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 13 25 25 ns ns ns 25 15 1 ns ns µs Min. 3 Max. 7.5 8 8 2 5 6 0 10 3 3 100 166 133 5 Input or Feedback Set-Up Time Synchronous Preset Set-Up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH[6] Clock Width LOW[6] External Maximum Frequency (1/(tCO + tS))[12] Data Path Maximum Frequency (1/(tWH + tWL))[6, 13] Internal Feedback Maximum Frequency (1/(tCF + tS))[6,14] Register Clock to Feedback Input[6, 15] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Delay Synchronous Preset Recovery Time Power-Up Reset Time[6,16] 2.5 8 5 12 6 1 8 1 10 6 3 15 10 13 10 1 4.5 20 Notes: 7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test Loads and Waveforms is used for tEA(+). 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. This specification is guaranteed for all device outputs changing state in a given access cycle. 10. The test load of part (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring tEA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 11. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 13. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 15. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS. 16. The registers in the PALC22V10D have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied. 6 PALC22V10D Military and Industrial Switching Characteristics PALC22V10D[2, 7] 22V10D-10 Parameter tPD tEA tER tCO tS1 tS2 tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tAW tAR tAP tSPR tPR Description Input to Output Propagation Delay[8, 9] Input to Output Enable Delay[10] Input to Output Disable Delay[11] Clock to Output Delay [8, 9] 22V10D-15 Min. 3 Max. 15 15 15 2 10 10 0 20 6 6 50.0 83.3 68.9 8 22V10D-25 Min. 3 Max. 25 25 25 2 18 18 0 33 14 14 30.3 35.7 32.2 15 Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 13 25 25 ns ns ns 25 25 1 ns ns µs Min. 3 Max. 10 10 10 2 6 7 0 12 3 3 76.9 142 111 7 Input or Feedback Set-Up Time Synchronous Preset Set-Up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH[6] Clock Width LOW[6] External Maximum Frequency (1/(tCO + tS))[12] Data Path Maximum Frequency (1/(tWH + tWL))[6, 13] Internal Feedback Maximum Frequency (1/(tCF + tS))[6,14] Register Clock to Feedback Input[6,15] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Delay Synchronous Preset Recovery Time Power-Up Reset Time[6, 16] 3 10 6 12 8 1 20 1 15 12 4.5 20 7 PALC22V10D Switching Waveform INPUTS I/O, REGISTERED FEEDBACK SYNCHRONOUS PRESET CP t SPR t AW ASYNCHRONOUS RESET REGISTERED OUTPUTS t PD COMBINATORIAL OUTPUTS V10D–12 tS tH t WH t WL tP t AR t CO t AP tER[NO TAG] tEA[NO TAG] tER[NO TAG] tEA[NO TAG] Power-Up Reset Waveform[16] POWER SUPPLY VOLTAGE REGISTERED ACTIVE L OW OUTPUTS CLOCK tPR MAX = 1 µs t WL V10D–13 10% 90% t PR VCC tS 8 PALC22V10D Functional Logic Diagram for PALC22V10D 1 0 AR OE 0 4 8 12 16 20 24 28 32 36 40 S S S 7 OE 0 Macro– cell 23 S S S 2 9 OE 0 Macro– cell 22 S S S 3 11 OE 0 Macro– cell 21 S S S 4 13 OE 0 Macro– cell 20 S S S 15 OE 0 Macro– cell 19 5 S S S 6 15 OE 0 Macro– cell 18 S S S 7 13 OE 0 Macro– cell 17 S S S 11 Macro– cell 16 8 OE 0 S S S 9 Macro– cell 15 9 OE 0 S S S 7 Macro– cell 14 10 SP 11 V10D–14 13 9 PALC22V10D Ordering Information ICC (mA) 130 90 150 150 tPD (ns) 7.5 10 10 10 tS (ns) 5 6 6 6 tCO (ns) 5 7 7 7 Ordering Code PALC22V10D-7JC PALC22V10D-7PC PALC22V10D-10JC PALC22V10D-10PC PALC22V10D-10JI PALC22V10D-10PI PALC22V10D-10DMB PALC22V10D-10KMB PALC22V10D-10LMB 90 120 120 15 15 15 7.5 7.5 7.5 10 10 10 PALC22V10D-15JC PALC22V10D-15PC PALC22V10D-15JI PALC22V10D-15PI PALC22V10D-15DMB PALC22V10D-15KMB PALC22V10D-15LMB 90 120 120 25 25 25 15 15 15 15 15 15 PALC22V10D-25JC PALC22V10D-25PC PALC22V10D-25JI PALC22V10D-25PI PALC22V10D-25DMB PALC22V10D-25KMB PALC22V10D-25LMB Package Name J64 P13 J64 P13 J64 P13 D14 K73 L64 J64 P13 J64 P13 D14 K73 L64 J64 P13 J64 P13 D14 K73 L64 Package Type 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier Military Industrial Commercial Military Industrial Commercial Military Industrial Commercial Operating Range Commercial MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tPD tCO tS tH Switching Characteristics Parameter Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Document #: 38-00185-H 10 PALC22V10D Package Diagrams 24–Lead (300–Mil) CerDIP D14 MIL-STD-1835 D-9 Config. A 28–Lead Plastic Leaded Chip Carrier J64 24–Lead Rectangular Cerpack K73 MIL-STD-1835 F-6 Config. A 28–Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 11 PALC22V10D Package Diagrams (continued) 24–Lead (300–Mil) Molded DIP P13/P13A © Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.