PALCE16V8L-25DMB

USE ULTRA37000™ FOR ALL NEW DESIGNS PALCE16V8 Flash-Erasable Reprogrammable CMOS PAL® Device Features • Active pull-up on data input pins • Low power version (16V8L) — 55 mA max. commercial (10, 15, 25 ns) — 65 mA max. industrial (10, 15, 25 ns) — 65 mA military (15 and 25 ns) • Standard version has low power — 90 mA max. commercial (10, 15, 25 ns) — 115 mA max. commercial (7 ns) — 130 mA max. military/industrial (10, 15, 25 ns) • CMOS Flash technology for electrical erasability and reprogrammability • PCI-compliant • User-programmable macrocell — Output polarity control — Individually selectable for registered or combinatorial operation • Up to 16 input terms and eight outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • 10 ns military/industrial versions 7 ns tCO 10 ns tS 10 ns tPD 62-MHz state machine • High reliability — Proven Flash technology — 100% programming and functional testing Functional Description The Cypress PALCE16V8 is a CMOS Flash Electrical Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. Logic Block Diagram (PDIP/CDIP) GND 10 I8 9 I7 8 I6 7 I5 6 I4 5 I3 4 I2 3 I1 2 CLK/I0 1 PROGRAMMABLE AND ARRAY (64 x 32) 8 8 8 8 8 8 8 8 Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell 11 OE/I9 12 I/O0 13 I/O1 14 I/O2 15 I/O3 16 I/O4 17 I/O5 18 I/O6 19 I/O7 20 VCC Pin Configurations CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 GND Cypress Semiconductor Corporation Document #: 38-03025 Rev. *A • 3901 North First Street • San Jose, CA 95134 I8 GND OE/I9 I/O0 I/O1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE/I9 I3 I4 I5 I6 I7 I2 I1 CLK/I 0 VCC I/O7 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10111213 I/O6 I/O5 I/O4 I/O3 I/O2 DIP Top View PLCC/LCC Top View • 408-943-2600 Revised April 22, 2004 USE ULTRA37000™ FOR ALL NEW DESIGNS Selection Guide tPD ns Generic Part Number PALCE16V8-5 PALCE16V8-7 PALCE16V8-10 PALCE16V8-15 PALCE16V8-25 PALCE16V8L-15 PALCE16V8L-25 Com’l/Ind 5 7.5 10 15 25 15 25 10 15 25 15 25 Mil 3 7 10 12 15 12 15 10 12 20 12 20 tS n s Com’l/Ind Mil 4 5 7 10 12 10 12 10 10 12 12 20 tCO ns Com’l/Ind Mil PALCE16V8 ICC mA Com’l 115 115 90 90 90 55 55 130 130 130 65 65 Mil/Ind Shaded areas contain preliminary information. Functional Description The PALCE16V8 is executed in a 20-pin 300-mil molded DIP, a 300-mil cerdip, a 20-lead square ceramic leadless chip carrier, and a 20-lead square plastic leaded chip carrier. The device provides up to 16 inputs and 8 outputs. The PALCE16V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 20-pin PLDs such as 16L8, 16R8, 16R6, and 16R4. The PALCE16V8 features 8 product terms per output and 32 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control or as a data product term. There are a total of 18 architecture bits in the PALCE16V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself. Power-Up Reset All registers in the PALCE16V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. Electronic Signature An electronic signature word is provided in the PALCE16V8 that consists of 64 bits of programmable memory that can contain user-defined data. Security Bit A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. Low Power The Cypress PALCE16V8 provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled. Configuration Table CG0 0 0 1 1 1 CG1 1 1 0 0 1 CL0x 0 1 0 1 1 Cell Configuration Registered Output Combinatorial I/O Combinatorial Output Input Combinatorial I/O Devices Emulated Registered Med PALs Registered Med PALs Small PALs Small PALs 16L8 only Document #: 38-03025 Rev. *A Page 2 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Macrocell PALCE16V8 11 0X 10 OE VCC 11 10 00 01 To Adjacent Macrocell CG1 CL0x 11 0X D Q Q 10 I/Ox VCC CLK CL1x 10 11 0X CG1 for pin 13 to 18 CG0 for pin 12 and 19 CL0x From Adjacent Pin Document #: 38-03025 Rev. *A Page 3 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State ............................................... –0.5V to +7.0V PALCE16V8 DC Input Voltage ............................................–0.5V to +7.0V Output Current into Outputs (LOW)............................. 24 mA DC Programming Voltage............................................. 12.5V Latch-Up Current .................................................... > 200 mA Operating Range Range Commercial Military[1] Industrial Ambient Temperature 0°C to +75°C –55°C to +125°C –40°C to +85°C VCC 5V ±5% 5V ±10% 5V ±10% Electrical Characteristics Over the Operating Range[2] Parameter VOH VOL VIH VIL[4] IIH IIL[5] ISC ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input or I/O HIGH Leakage Current Input or I/O LOW Leakage Current Operating Power Supply Current VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL Test Conditions IOH = –3.2 mA IOH = –2 mA IOL = 24 mA IOL = 12 mA Com’l Mil/Ind Com’l Mil/Ind 2.0 –0.5 0.8 10 –100 –30 Com’l –150 115 90 55 Mil/Ind Mil. Ind. 130 65 65 V V µA µA mA mA mA mA mA mA mA 0.5 V Min. 2.4 Max. Unit V Guaranteed Input Logical HIGH Voltage for All Inputs[3] Guaranteed Input Logical LOW Voltage for All Inputs[3] 3.5V < VIN < VCC 0V < VIN < VIN (Max.) Output Short Circuit Current VCC = Max., VOUT = 0.5V[6, 7] VCC = Max., VIL = 0V, VIH = 3V, Output Open, f = 15 MHz (counter) 5, 7 ns 10, 15, 25 ns 15L, 25L ns 10, 15, 25 ns 15L, 25L ns 15L, 25L ns Capacitance[7] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0V @ f = 1 MHz VOUT = 2.0V @ f = 1 MHz Typ. 5 5 Unit pF pF Endurance Characteristics[7] Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions Min. 100 Max. Unit Cycles Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to –3.0V for pulse durations less than 20 ns. 5. The leakage current is due to the internal pull-up resistor on all pins. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03025 Rev. *A Page 4 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS AC Test Loads and Waveforms ALL INPUT PULSES 3.0V 90% GND < 2 ns 10% 90% 10% < 2 ns PALCE16V8 5V S1 R1 OUTPUT R2 CL TEST POINT Commercial Specification tPD, tCO tPZX, tEA tPXZ, tER Closed Z · H: Open Z · L: Closed H · Z: Open L · Z: Closed 5 pF S1 CL 50 pF R1 200Ω R2 390Ω R1 Military R2 750Ω Measured Output Value 1.5V 1.5V H · Z: VOH – 0.5V L · Z: VOL + 0.5V 390Ω Commercial and Industrial Switching Characteristics [2] 16V8-5 Parameter tPD tPZX tPXZ tEA tER tCO tS tH tP Description Input to Output Propagation Delay[8, 9] OE to Output Enable OE to Output Disable Input to Output Enable Delay[7] Input to Output Disable Delay[7, 10] Clock to Output Delay[8, 9] Input or Feedback Set-up Time Input Hold Time External Clock Period (tCO + tS) Min. 1 1 1 1 1 1 3 0 7 Max. 5 6 5 6 5 4 2 5 0 10 16V8-7 Min. 3 Max. 7.5 6 6 9 9 5 2 7.5 0 14.5 16V8-10 Min. 3 Max. 10 10 10 10 10 7 2 12 0 22 16V8-15 Min. 3 Max. 15 15 15 15 15 10 2 15 0 27 16V8-25 Min. 3 Max. 25 20 20 25 25 12 Unit ns ns ns ns ns ns ns ns ns Shaded areas contain preliminary information. Notes: 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. This specification is guaranteed for all device outputs changing state in a given access cycle. 10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. 11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS. Document #: 38-03025 Rev. *A Page 5 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Commercial and Industrial Switching Characteristics (continued)[2] 16V8-5 Parameter tWH tWL fMAX1 fMAX2 fMAX3 Description Clock Width HIGH [7] PALCE16V8 16V8-15 Min. 8 8 45.5 62.5 50 Max. 16V8-25 Min. 12 12 37 41.6 40 Max. Unit ns ns MHz MHz MHz 16V8-7 Min. 4 4 100 125 125 Max. 16V8-10 Min. 6 6 69 83 74 Max. Min. 3 3 143 Max. Clock Width LOW[7] External Maximum Frequency (1/(tCO + tS))[7, 11] Data Path Maximum 166 Frequency (1/(tWH + tWL))[7, 12] Internal Feedback Maximum Frequency (1/(tCF + tS))[7, 13] Register Clock to Feedback Input[7, 14] Power-Up Reset Time[7] 1 166 tCF tPR 3 1 3 1 6 1 8 1 10 ns µs Military Switching Characteristics[7] 16V8-10 Parameter tPD tPZX tPXZ tEA tER tCO tS tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tPR Description Input to Output Propagation Delay[8, 9] OE to Output Enable OE to Output Disable Input to Output Enable Delay[7] Input to Output Disable Delay[7, 10] 2 10 .5 17 6 6 58 83 62.5 6 1 1 Clock to Output Delay[8, 9] Input or Feedback Set-up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH[7] Clock Width LOW[7] External Maximum Frequency (1/(tCO + tS)[7, 11] Data Path Maximum Frequency (1/(tWH + tWL))[7, 12] Internal Feedback Maximum Frequency (1/(tCF + tS))[7, 13] Register Clock to Feedback Input[7, 14] Power-Up Reset Time[7] Min. 3 Max. 10 10 10 10 10 7 2 12 .5 22 8 8 45.5 62.5 50 8 1 3 16V8-15 Min. Max. 15 15 15 15 15 10 2 15 .5 27 12 12 37 41.6 40 10 3 16V8-25 Min. Max. 25 20 20 25 25 12 Unit ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns µs Document #: 38-03025 Rev. *A Page 6 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Switching Waveform INPUTS, I/O, REGISTERED FEEDBACK tS CP t CO REGISTERED OUTPUTS t PD COMBINATORIAL OUTPUTS tPXZ, tER [10] tP tPXZ, tER [10] tH PALCE16V8 t WH t WL tEA, tPZX [10] tEA, tPZX[10] Power-Up Reset Waveform POWER SUPPLY VOLTAGE REGISTERED ACTIVE LOW OUTPUTS CLOCK tPR MAX = 1 µs t WL 10% 90% t PR VCC tS Document #: 38-03025 Rev. *A Page 7 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Functional Logic Diagram for PALCE16V8 PIN NUMBERS PRODUCT LINE FIRST CELL NUMBERS 0 00 64 128 192 3 4 78 11 12 15 16 19 20 23 24 27 28 31 INPUT LINE NUMBERS PIN NUMBERS PALCE16V8 VCC 1 20 MC7 CL1=2048 CL0=2120 PTD=2128 -2135 MC6 CL1=2049 CL0=2121 PTD=2136 -2143 MC5 CL1=2050 CL0=2122 PTD=2144 -2151 MC4 CL1=2051 CL0=2123 PTD=2152 -2159 MC3 CL1=2052 CL0=2124 PTD=2160 -2167 MC2 CL1=2053 CL0=2125 PTD=2168 -2175 MC1 CL1=2054 CL0=2126 PTD=2176 -2183 MC0 CL1=2055 CL0=2127 PTD=2184 -2191 32 96 160 224 19 2 256 320 384 448 288 352 416 480 18 3 512 576 640 704 544 608 672 736 17 4 768 832 896 960 800 864 928 992 16 5 1024 1088 1152 1216 1056 1120 1184 1248 15 6 1280 1344 1408 1312 1376 14 14721440 1504 7 1536 1600 1664 1568 1632 13 17281696 1760 8 1792 1856 1920 1824 1888 12 19841952 2016 9 10 0 34 2056 BYTE 0 78 2064 11 12 15 16 19 20 23 24 27 28 31 USER ELECTRONIC SIGNATURE ROW 2072 2080 2088 2096 2104 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 11 2112 2119 GLOBAL ARCH BITS CG0=2192 CG1=2193 BYTE 1 BYTE 7 MSB LSB MSB LSB Document #: 38-03025 Rev. *A Page 8 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Ordering Information ICC (mA) 115 115 90 130 130 90 130 tPD (ns) 5 7.5 10 10 10 15 15 tS (ns) 3 5 7.5 7.5 10 12 12 tCO (ns) 4 5 7 7 7 10 10 Ordering Code PALCE16V8-5JC PALCE16V8-7JC PALCE16V8-7PC PALCE16V8-10JC PALCE16V8-10PC PALCE16V8-10JI PALCE16V8-10PI PALCE16V8-10DMB PALCE16V8-10LMB PALCE16V8-15JC PALCE16V8-15PC PALCE16V8-15PI PALCE16V8-15DMB PALCE16V8-15LMB 90 130 25 25 15 15 12 12 PALCE16V8-25JC PALCE16V8-25PC PALCE16V8-25JI PALCE16V8-25DMB PALCE16V8-25LMB 55 65 55 65 55 65 10 10 15 15 25 25 7.5 10 12 12 15 15 7 7 10 10 12 12 PALCE16V8L-10JC PALCE16V8L-10PC PALCE16V8L-10JI PALCE16V8L-10PI PALCE16V8L-15JC PALCE16V8L-15PC PALCE16V8L-15DMB PALCE16V8L-15LMB PALCE16V8L-25JC PALCE16V8L-25PC PALCE16V8L-25DMB PALCE16V8L-25LMB Shaded areas contain preliminary information. PALCE16V8 Operating Range Commercial Commercial Package Name J61 J61 P5 J61 P5 J61 P5 D6 L61 J61 P5 P5 D6 L61 J61 P5 J61 D6 L61 J61 P5 J61 P5 J61 P5 D6 L61 J61 P5 D6 L61 Package Type 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead (300-Mil) CerDIP 20-Pin Square Leadless Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead(300Mil) Molded DIP 20-Lead (300-Mil) CerDIP 20-Pin Square Leadless Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) CerDIP 20-Pin Square Leadless Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead (300-Mil) CerDIP 20-Pin Square Leadless Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead (300-Mil) Molded DIP 20-Lead (300-Mil) CerDIP 20-Pin Square Leadless Chip Carrier Industrial Military Commercial Industrial Military Commercial Industrial Military Commercial Industrial Commercial Military Commercial Military Document #: 38-03025 Rev. *A Page 9 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Subgroups PALCE16V8 Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Switching Characteristics Parameter tPD tCO tS tH Package Diagrams 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config. A 51-80029-** Document #: 38-03025 Rev. *A Page 10 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 20-Lead Plastic Leaded Chip Carrier J61 PALCE16V8 51-85000-*A 20-Square Leadless Chip Carrier L61 51-80049-** Document #: 38-03025 Rev. *A Page 11 of 13 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 20-Lead (300-Mil) Molded DIP P5 PALCE16V8 51-85011-*A Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-03025 Rev. *A Page 12 of 13 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS Document History Page Document Title: PALCE16V8 Flash Erasable Reprogrammable CMOS PAL® Device Document Number: 38-03025 REV. ** *A ECN NO. 106370 213375 Issue Date 07/11/01 See ECN Orig. of Change SZV FSG Description of Change Change from Spec Number: 38-00364 to 38-03025 PALCE16V8 Added note to title page: “Use Ultra37000 For All New Designs” Document #: 38-03025 Rev. *A Page 13 of 13