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S25FL064P0XBHI023

S25FL064P0XBHI023

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    24-TBGA

  • 描述:

    IC FLASH 64MBIT 104MHZ 24BGA

  • 数据手册
  • 价格&库存
S25FL064P0XBHI023 数据手册
S25FL064P 64-Mbit 3.0 V SPI Flash Memory This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede S25FL064P. These are the factory-recommended migration paths. Please refer to the S25FL-L Family data sheets for specifications and ordering information. Architectural Advantages  Single power supply operation – Full voltage range: 2.7 to 3.6V read and write operations  Memory architecture – Uniform 64-kB sectors – Top or bottom parameter block (Two 64-kB sectors (top or bottom) broken down into sixteen 4-kB sub-sectors each) – 256-byte page size – Backward compatible with the S25FL064A device  Program – Page Program (up to 256 bytes) in 1.5 ms (typical) – Program operations are on a page by page basis – Accelerated programming mode via 9V W#/ACC pin – Quad Page Programming  Erase – Bulk erase function – Sector erase (SE) command (D8h) for 64-kB sectors – Sub-sector erase (P4E) command (20h) for 4-kB sectors – Sub-sector erase (P8E) command (40h) for 8-kB sectors  Cycling endurance – 100,000 cycles per sector typical  Data retention – 20 years typical  Device ID – JEDEC standard two-byte electronic signature – RES command one-byte electronic signature for backward compatibility  One time programmable (OTP) area for permanent, secure identification; can be programmed and locked at the factory or by the customer Cypress Semiconductor Corporation Document Number: 002-00649 Rev. *J •  CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices  Process technology – Manufactured on 90-nm MirrorBit® process technology  Package option – Industry Standard Pinouts – 16-pin SO package (300 mils) – 8-contact WSON package (6 × 8 mm) – 24-ball BGA package (6 × 8 mm), 5 × 5 pin configuration – 24-ball BGA package (6 × 8 mm), 6 × 4 pin configuration Performance Characteristics  Speed – Normal READ (Serial): 40 MHz clock rate – FAST_READ (Serial): 104 MHz clock rate (maximum) – DUAL I/O FAST_READ: 80 MHz clock rate or 20 MB/s effective data rate – QUAD I/O FAST_READ: 80 MHz clock rate or 40 MB/s effective data rate  Power saving standby mode – Standby Mode 80 μA (typical) – Deep Power-Down Mode 3 μA (typical) Memory Protection Features  Memory protection – W#/ACC pin works in conjunction with Status Register Bits to protect specified memory areas – Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only Software Features – SPI Bus Compatible Serial Interface 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 22, 2017 Not Recommended for New Designs Distinctive Characteristics S25FL064P General Description The S25FL064P is a 3.0 Volt (2.7V to 3.6V), single-power-supply flash memory device. The device consists of 128 uniform 64 kB sectors with the two (Top or Bottom) 64 kB sectors further split up into thirty-two 4 kB sub sectors. The S25FL064P device is fully backward compatible with the S25FL064A device. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0-volt VCC supply.  Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz  Quad Output Read using SI, SO, W#/ACC and HOLD# pins as output pins at a clock rate of up to 80 MHz  Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz  Quad I/O High Performance Read using SI, SO, W#/ACC and HOLD# pins as input and output pins at a clock rate of up to 80 MHz  Quad Page Programming using SI, SO, W#/ACC and HOLD# pins as input pins to program data at a clock rate of up to 80 MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device requires a high voltage supply to the W#/ACC pin to enable the Accelerated Programming mode. The S25FL064P device also offers a One-Time Programmable area (OTP) of up to 128-bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions. Document Number: 002-00649 Rev. *J Page 2 of 63 Not Recommended for New Designs The S25FL064P device adds the following high-performance features using 5 new instructions: S25FL064P Distinctive Characteristics .................................................. 1 11. Power-up and Power-down........................................ 48 General Description ............................................................. 2 12. Initial Delivery State.................................................... 49 1. Block Diagram.............................................................. 4 13. Program Acceleration via W#/ACC Pin..................... 49 2. Connection Diagrams.................................................. 5 3. Input/Output Descriptions........................................... 7 14. Electrical Specifications............................................. 50 14.1 Absolute Maximum Ratings .......................................... 50 4. Logic Symbol ............................................................... 7 15. Operating Ranges ....................................................... 50 5. 5.1 Ordering Information ................................................... 8 Valid Combinations ........................................................ 9 16. DC Characteristics...................................................... 51 17. Test Conditions ........................................................... 52 6. SPI Modes................................................................... 10 7. 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 Device Operations ..................................................... 11 Byte or Page Programming.......................................... 11 Quad Page Programming ............................................ 11 Dual and Quad I/O Mode ............................................. 11 Sector Erase / Bulk Erase............................................ 11 Monitoring Write Operations Using the Status Register 11 Active Power and Standby Power Modes.................... 11 Status Register ............................................................ 12 Configuration Register ................................................. 12 Data Protection Modes ................................................ 13 Hold Mode (HOLD#) .................................................... 14 Accelerated Programming Operation........................... 15 18. AC Characteristics...................................................... 53 18.1 Capacitance .................................................................. 54 8. Sector Address Table ................................................ 15 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 Command Definitions................................................ Read Data Bytes (READ) ............................................ Read Data Bytes at Higher Speed (FAST_READ) ...... Dual Output Read Mode (DOR)................................... Quad Output Read Mode (QOR) ................................. DUAL I/O High Performance Read Mode (DIOR)........ Quad I/O High Performance Read Mode (QIOR) ........ Read Identification (RDID) ........................................... Read-ID (READ_ID)..................................................... Write Enable (WREN) .................................................. Write Disable (WRDI)................................................... Read Status Register (RDSR) ..................................... Read Configuration Register (RCR) ............................ Write Registers (WRR) ................................................ Page Program (PP)...................................................... QUAD Page Program (QPP) ....................................... Parameter Sector Erase (P4E, P8E) ........................... Sector Erase (SE) ........................................................ Bulk Erase (BE) ........................................................... Deep Power-Down (DP) .............................................. Release from Deep Power-Down (RES)...................... Clear Status Register (CLSR)...................................... OTP Program (OTPP).................................................. Read OTP Data Bytes (OTPR) .................................... 18 19 20 21 22 23 24 26 30 31 31 32 33 34 36 37 38 39 40 41 42 43 44 44 10. 10.1 10.2 10.3 OTP Regions .............................................................. Programming OTP Address Space.............................. Reading OTP Data....................................................... Locking OTP Regions .................................................. 45 45 45 45 Document Number: 002-00649 Rev. *J 19. Data Integrity ............................................................... 56 19.1 Erase Endurance .......................................................... 56 19.2 Data Retention .............................................................. 56 20. Physical Dimensions .................................................. 57 20.1 SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) 57 20.2 WNF 008 — WSON 8-contact (6 x 8 mm) No-Lead Package 58 20.3 FAB024 — 24-ball Ball Grid Array (6 x 8 mm) package 59 20.4 FAC024 — 24-ball Ball Grid Array (6 x 8 mm) package 60 21. Revision History.......................................................... 61 Document History ........................................................... 61 Sales, Solutions, and Legal Information ...................... 63 Worldwide Sales and Design Support ....................... 63 Products .................................................................... 63 PSoC® Solutions ...................................................... 63 Cypress Developer Community ................................. 63 Technical Support ..................................................... 63 Page 3 of 63 Not Recommended for New Designs Contents S25FL064P 1. Block Diagram SRAM X D E C Array - L Not Recommended for New Designs PS Array - R Logic RD DATA PATH Document Number: 002-00649 Rev. *J W# / ACC / IO2 HOLD# / IO3 VCC GND SO / IO1 SI / IO0 SCK CS# IO Page 4 of 63 S25FL064P 2. Connection Diagrams HOLD#/IO3 1 16 SCK VCC 2 15 SI/IO0 DNC 3 14 DNC DNC 4 13 DNC DNC 5 12 DNC DNC 6 11 DNC CS# 7 10 GND SO/IO1 8 9 W#/ACC/IO2 Note DNC = Do Not Connect (Reserved for future use) Figure 2.2 8-contact WSON Package (6 x 8 mm) CS# 1 SO/IO1 2 8 VCC 7 HOLD#/IO3 WSON W#/ACC/IO2 3 6 SCK GND 4 5 SI/IO0 Note There is an exposed central pad on the underside of the USON package. This should not be connected to any voltage or signal line on the PCB. Connecting the central pad to GND (VSS) is possible, provided PCB routing ensures 0 mV difference between voltage at the USON GND (VSS) lead and the central exposed pad. Figure 2.3 6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration 1 2 3 4 5 NC NC NC NC NC SCK GND VCC NC NC CS# NC SO/IO1 NC NC A B C NC W#/ACC/IO2 NC D SI/IO0 HOLD#/IO3 NC E Document Number: 002-00649 Rev. *J NC NC NC Page 5 of 63 Not Recommended for New Designs Figure 2.1 16-pin Plastic Small Outline Package (SO) S25FL064P Document Number: 002-00649 Rev. *J A1 A2 A3 A4 NC NC NC NC B1 B2 B3 B4 NC SCK GND VCC C1 C2 C3 C4 NC CS# NC W#/ACC/IO2 D1 D2 D3 NC SO/IO1 E1 E2 E3 E4 NC NC NC NC Not Recommended for New Designs Figure 2.4 6x8 mm 24-ball BGA Package, 6x4 Pin Configuration D4 SI/IO0 HOLD#/IO3 F1 F2 F3 F4 NC NC NC NC Page 6 of 63 S25FL064P 3. Input/Output Descriptions I/O Description SO/IO1 I/O Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as an input pin in Dual and Quad I/O, and Quad Page Program modes. SI/IO0 I/O Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and program data on SI on the rising edge of SCK. Functions as an output pin in Dual and Quad I/O mode. SCK Input Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising edge of SCK. Triggers output on SO after the falling edge of SCK. CS# Input Chip Select: Places device in active power mode when driven low. Deselects device and places SO at high impedance when high. After power-up, device requires a falling edge on CS# before any command is written. Device is in standby mode when a program, erase, or Write Status Register operation is not in progress. HOLD#/IO3 I/O Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low. Functions as an output pin in Quad I/O mode. W#/ACC/IO2 I/O Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area. Functions as an output pin in Quad I/O mode. VCC Input Supply Voltage GND Input Ground Not Recommended for New Designs Signal 4. Logic Symbol VCC SO/IO1 SI/IO0 SCK CS# W#/ACC/IO2 HOLD#/IO3 GND Document Number: 002-00649 Rev. *J Page 7 of 63 S25FL064P 5. Ordering Information The ordering part number is formed by a valid combination of the following: S25FL 064 P 0X M F I 00 1 Packing Type 0 = Tray 1 = Tube 3 = 13” Tape and Reel Not Recommended for New Designs Model Number (Additional Ordering Options) 03 = 6 x 4 pin configuration BGA package 02 = 5 x 5 pin configuration BGA package 00 = 16-pin SO package / 8-contact WSON package Temperature Range / Grade I = Industrial (–40°C to + 85°C) V = Industrial Plus(–40°C to +105°C) A = Automotive, AEC-Q100 Grade 3 (–40°C to +85°C) B = Automotive, AEC-Q100 Grade 2 (–40°C to +105°C) Package Materials F = Lead (Pb)-free H = Low-Halogen, Lead (Pb)-free Package Type M = 16-pin SO package N = 8-contact WSON 6 x 8mm package B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch Speed 0X = 104 MHz Device Technology P = 90 nm MirrorBit® Process Technology Density 064= 64 Mbit Device Family S25FL Cypress Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory Document Number: 002-00649 Rev. *J Page 8 of 63 S25FL064P 5.1 Valid Combinations Valid Combinations — Standard Table 5.1 lists the standard valid combinations configurations planned to be supported in volume for this device. Table 5.1 S25FL064P Valid Combinations — Standard Base Ordering Part Number Speed Option Package & Temperature Model Number Packing Type 00 0, 1, 3 02, 03 0, 3 MFI,NFI S25FL064P 0X MFV, NFV BHI, BHV Package Marking FL064P + (Temp) + F Valid Combinations — Automotive Grade / AEC-Q100 Table 5.2 lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on newly released combinations. Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products. Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/ TS-16949 requirements. AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949 compliance. Table 5.2 S25FL064P Valid Combinations — Automotive Grade / AEC-Q100 S25FL064P Valid Combinations Base Ordering Part Number Speed Option Package & Temperature MFA, NFA S25FL064P 0X MFB, NFB BHA, BHB Document Number: 002-00649 Rev. *J Model Number Packing Type 00 0, 1, 3 02, 03 0, 3 Package Marking FL064P + (Temp) + F Page 9 of 63 Not Recommended for New Designs S25FL064P Valid Combinations S25FL064P 6. SPI Modes A microcontroller can use either of its two SPI modes to control SPI flash memory devices:  CPOL = 0, CPHA = 0 (Mode 0)  CPOL = 1, CPHA = 1 (Mode 3) Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.  SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)  SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3) Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SI SCK SCK SO SI SCK SO SI SCK SO SI Bus Master SPI Memory Device CS3 CS2 SPI Memory Device SPI Memory Device CS1 CS# HOLD# W#/ACC CS# HOLD# W#/ACC CS# HOLD# W#/ACC Note The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. Figure 6.2 SPI Modes Supported CS# CPOL CPHA Mode 0 0 0 SCK Mode 3 1 1 SCK SI SO Document Number: 002-00649 Rev. *J MSB MSB Page 10 of 63 Not Recommended for New Designs When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes: S25FL064P 7. Device Operations All Cypress SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device that supports an inactive clock while CS# is held low. Byte or Page Programming Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation. 7.2 Quad Page Programming The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed using 4 pins as inputs at the same time, thus effectively quadrupling the data transfer rate, compared to the Page Program (PP) instruction. The Write Enable Latch (WEL) bit must be set to a 1 using the Write Enable (WREN) command prior to issuing the QPP command. 7.3 Dual and Quad I/O Mode The S25FL064P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode and the Dual/Quad I/ O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows data to be transferred to or from the device at two to four times the rate of standard SPI devices. When operating in the Dual or Quad I/O High Performance Mode (BBh or EBh instructions), data can be read at fast speed using two or four data bits at a time, and the 3-byte address can be input two or four address bits at a time. 7.4 Sector Erase / Bulk Erase The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be individually programmed from 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level. In addition to the 64-kB Sector Erase (SE), the S25FL064P device also offers 4-kB Parameter Sector Erase (P4E) and 8-kB Parameter Sector Erase (P8E). 7.5 Monitoring Write Operations Using the Status Register The host system can determine when a Write Register, program, or erase operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the S25FL064P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure. 7.6 Active Power and Standby Power Modes The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but may still be in the Active Power mode until all program, erase, and Write Registers operations have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB. The Deep Power-Down (DP) command provides additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or erase commands, and reduces its power consumption to IDP. Document Number: 002-00649 Rev. *J Page 11 of 63 Not Recommended for New Designs 7.1 S25FL064P 7.7 Status Register  Write In Progress (WIP): Indicates whether the device is performing a Write Registers, program or erase operation.  Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.  Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected against program and erase commands.  Erase Error (E_ERR): The Erase Error Bit is used as an Erase operation success and failure check.  Program Error (P_ERR): The Program Error Bit is used as an program operation success and failure check.  Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit is set to 1 and the W#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits. 7.8 Configuration Register The Configuration Register contains the control bits that can be read or set by specific commands. These bits configure different configurations and security features of the device.  The FREEZE bit locks the BP2-0 bits in Status Register and the TBPROT and TBPARM bits in the Configuration Register. Note that once the FREEZE bit has been set to 1, then it cannot be cleared to 0 until a power-on-reset is executed. As long as the FREEZE bit is set to 0, then the other bits of the Configuration Register, including FREEZE bit, can be written to.  The QUAD bit is non-volatile and sets the pin out of the device to Quad mode; that is, W#/ACC becomes IO2 and HOLD# becomes IO3. The instructions for Serial, Dual Output, and Dual I/O reads function as normal. The W#/ACC and HOLD# functionality does not work when the device is set in Quad mode.  The TBPARM bit defines the logical location of the 4 kB parameter sectors. The parameter sectors consist of thirty two 4 kB sectors. All sectors other than the parameter sectors are defined to be 64-kB uniform in size. When TBPARM is set to a 1, the 4 kB parameter sectors starts at the top of the array. When TBPARM is set to a 0, the 4 kB parameter sectors starts at the bottom of the array. Note that once this bit is set to a 1, it cannot be changed back to 0. The desired state of TBPARM must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. TBPARM must not be programmed after programming or erasing is done in the main flash array.  The BPNV bit defines whether or not the BP2-0 bits in the Status Register are volatile or non-volatile. When BPNV is set to a 1, the BP2-0 bits in the Status Register are volatile and will be reset to binary 111 after power on reset. When BPNV is set to a 0, the BP2-0 bits in the Status Register are non-volatile. Note that once this bit is set to a 1, it cannot be changed back to 0.  The TBPROT bit defines the operation of the block protection bits BP2, BP1, and BP0 in the Status Register. When TBPROT is set to a 0, then the block protection is defined to start from the top of the array. When TBPROT is set to a 1, then the block protection is defined to start from the bottom of the array. Note that once this bit is set to a 1, it cannot be changed back to 0. The desired state of TBPROT must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. TBPROT must not be programmed after programming or erasing is done in the main flash array. Note: It is suggested that the Block Protection & Parameter sectors not be set to the same area of the array; otherwise, the user cannot utilize the Parameter sectors if they are protected. The following matrix shows the recommended settings. Table 7.1 Suggested Cross Settings TBPARM TBPROT Array Overview Parameter Sectors - Bottom 0 0 BP Protection - Top 0 1 Not recommended (Parameters & BP Protection are both Bottom) (Default) Document Number: 002-00649 Rev. *J Page 12 of 63 Not Recommended for New Designs The Status Register contains the status and control bits that can be read or set by specific commands (see Table 9.1 on page 18). These bits configure different protection configurations and supply information of operation of the device. (for details see Table 9.8, S25FL064P Status Register on page 32): S25FL064P Table 7.1 Suggested Cross Settings TBPARM TBPROT Array Overview 1 0 Not recommended (parameters & BP Protection are both Top) 1 1 Parameter Sectors - Top of Array (high address) BP Protection - Bottom of Array (low address Bit Bit Name 7 NA - Bit Function Not Used Description 6 NA - Not Used 5 TBPROT Configures start of block protection 1 = Bottom Array (low address) 0 = Top Array (high address) (Default) 4 NA - Do Not Use 3 BPNV Configures BP2-0 bits in the Status Register 1 = Volatile 0 = Non-volatile (Default) 2 TBPARM Configures Parameter sector location 1 = Top Array (high address) 0 = Bottom Array (low address) (Default) 1 QUAD Puts the device into Quad I/O mode 1 = Quad I/O 0 = Dual or Serial I/O (Default) 0 FREEZE Locks BP2-0 bits in the Status Register 1 = Enabled 0 = Disabled (Default) Note (Default) indicates the value of each Configuration Register bit set upon initial factory shipment. 7.9 Data Protection Modes Cypress SPI flash memory devices provide the following data protection methods:  The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands: – Page Program (PP) – Sector Erase (SE) – Bulk Erase (BE) – Write Disable (WRDI) – Write Register (WRR) – Parameter 4 kB Sector Erase (P4E) – Parameter 8 kB Sector Erase (P8E) – Quad Page Programming (QPP) – OTP Byte Programming (OTPP)  Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not programmed or erased. Table 7.3 and Table 7.4 shows the sizes and address ranges of protected areas that are defined by Status Register bits BP2:BP0.  Hardware Protected Mode (HPM): The Write Protect (W#/ACC) input and the Status Register Write Disable (SRWD) bit together provide write protection.  Clock Pulse Count: The device verifies that all program, erase, and Write Register commands consist of a clock pulse count that is a multiple of eight before executing them. Document Number: 002-00649 Rev. *J Page 13 of 63 Not Recommended for New Designs Table 7.2 Configuration Register Table S25FL064P Table 7.3 TBPROT = 0 (Starts Protection from TOP of Array) BP2 BP1 BP0 Memory Array Protected Address Range Protected Sectors Unprotected Address Range Unprotected Sectors Protected Portion of Total Memory Area 0 0 0 None 0 000000h-7FFFFFh SA127:SA0 0 0 0 1 7E0000h-7FFFFFh (2) SA127:SA126 000000h-7DFFFFh SA125:SA0 1/64 0 1 0 7C0000h-7FFFFFh (4) SA127:SA124 000000h-7BFFFFh SA123:SA0 1/32 0 1 1 780000h-7FFFFFh (8) SA127:SA120 000000h-77FFFFh SA119:SA0 1/16 1 0 0 700000h-7FFFFFh (16) SA127:SA112 000000h-6FFFFFh SA111:SA0 1/8 1 0 1 600000h-7FFFFFh (32) SA127:SA96 000000h-5FFFFFh SA95:SA0 1/4 1 1 0 400000h-7FFFFFh (64) SA127:SA64 000000h-3FFFFFh SA63:SA0 1/2 1 1 1 000000h-7FFFFFh (128) SA127:SA0 None None All Protected Portion of Total Memory Area Table 7.4 TBPROT=1 (Starts Protection from BOTTOM of Array) Status Register Block Memory Array Protected Sectors Unprotected Address Range Unprotected Sectors None 0 000000h-7FFFFFh SA0:SA127 0 000000h-01FFFFh (2) SA0:SA1 020000h-7FFFFFh SA2:SA127 1/64 000000h-03FFFFh (4) SA0:SA3 040000h-7FFFFFh SA4:SA127 1/32 000000h-07FFFFh (8) SA0:SA7 080000h-7FFFFFh SA8:SA127 1/16 0 000000h-0FFFFFh (16) SA0:SA15 100000h-7FFFFFh SA16:SA127 1/8 0 1 000000h-1FFFFFh (32) SA0:SA31 200000h-7FFFFFh SA32:SA127 1/4 1 1 0 000000h-3FFFFFh (64) SA0:SA63 400000h-7FFFFFh SA64:SA127 1/2 1 1 1 000000h-7FFFFFh (128) SA0:SA127 None None All BP2 BP1 BP0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 7.10 Protected Address Range Hold Mode (HOLD#) The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write Registers, program or erase operation that is currently in progress. The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, standard use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of SCK (non-standard use). The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-standard use) See Figure 7.1. The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the Hold mode. CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low. Note: The HOLD Mode feature is disabled when Quad mode is enabled, i.e., Quad bit in the Configuration register is set to 1. Document Number: 002-00649 Rev. *J Page 14 of 63 Not Recommended for New Designs Status Register Block S25FL064P Figure 7.1 Hold Mode Operation SCK Hold Condition (standard use) 7.11 Hold Condition (non-standard use) Accelerated Programming Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device uses the higher voltage on the pin to reduce the time required for program operations. Removing VHH from the W#/ACC pin returns the device to normal operation. Note that the W#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the W#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Note: The ACC function is disabled during Quad I/O Mode. 8. Sector Address Table The Sector Address tables show the size of the memory array, sectors, and pages. The device uses pages to cache the program data before the data is programmed into the memory array. Each page or byte can be individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sub-sector, sector- or device-wide basis using the P4E/P8E, SE or BE commands. Table 8.1 and Table 8.2 show the starting and ending address for each sector. The complete set of sectors comprises the memory array of the flash device. Document Number: 002-00649 Rev. *J Page 15 of 63 Not Recommended for New Designs HOLD# S25FL064P Table 8.1 S25FL064P Sector Address Table TBPARM=0 SA127 SA126 SA125 SA124 SA123 SA122 SA121 SA120 SA119 SA118 SA117 SA116 SA115 SA114 SA113 SA112 SA111 SA110 SA109 SA108 SA107 SA106 SA105 SA104 SA103 SA102 SA101 SA100 SA99 SA98 SA97 SA96 SA95 SA94 SA93 SA92 SA91 SA90 SA89 SA88 SA87 SA86 SA85 Address range Start End address Address 7F0000h 7FFFFFh 7E0000h 7EFFFFh 7D0000h 7DFFFFh 7C0000h 7CFFFFh 7B0000h 7BFFFFh 7A0000h 7AFFFFh 790000h 79FFFFh 780000h 78FFFFh 770000h 77FFFFh 760000h 76FFFFh 750000h 75FFFFh 740000h 74FFFFh 730000h 73FFFFh 720000h 72FFFFh 710000h 71FFFFh 700000h 70FFFFh 6F0000h 6FFFFFh 6E0000h 6EFFFFh 6D0000h 6DFFFFh 6C0000h 6CFFFFh 6B0000h 6BFFFFh 6A0000h 6AFFFFh 690000h 69FFFFh 680000h 68FFFFh 670000h 67FFFFh 660000h 66FFFFh 650000h 65FFFFh 640000h 64FFFFh 630000h 63FFFFh 620000h 62FFFFh 610000h 61FFFFh 600000h 60FFFFh 5F0000h 5FFFFFh 5E0000h 5EFFFFh 5D0000h 5DFFFFh 5C0000h 5CFFFFh 5B0000h 5BFFFFh 5A0000h 5AFFFFh 590000h 59FFFFh 580000h 58FFFFh 570000h 57FFFFh 560000h 56FFFFh 550000h 55FFFFh Sector SA84 SA83 SA82 SA81 SA80 SA79 SA78 SA77 SA76 SA75 SA74 SA73 SA72 SA71 SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 Address range Start End address Address 540000h 54FFFFh 530000h 53FFFFh 520000h 52FFFFh 510000h 51FFFFh 500000h 50FFFFh 4F0000h 4FFFFFh 4E0000h 4EFFFFh 4D0000h 4DFFFFh 4C0000h 4CFFFFh 4B0000h 4BFFFFh 4A0000h 4AFFFFh 490000h 49FFFFh 480000h 48FFFFh 470000h 47FFFFh 460000h 46FFFFh 450000h 45FFFFh 440000h 44FFFFh 430000h 43FFFFh 420000h 42FFFFh 410000h 41FFFFh 400000h 40FFFFh 3F0000h 3FFFFFh 3E0000h 3EFFFFh 3D0000h 3DFFFFh 3C0000h 3CFFFFh 3B0000h 3BFFFFh 3A0000h 3AFFFFh 390000h 39FFFFh 380000h 38FFFFh 370000h 37FFFFh 360000h 36FFFFh 350000h 35FFFFh 340000h 34FFFFh 330000h 33FFFFh 320000h 32FFFFh 310000h 31FFFFh 300000h 30FFFFh 2F0000h 2FFFFFh 2E0000h 2EFFFFh 2D0000h 2DFFFFh 2C0000h 2CFFFFh 2B0000h 2BFFFFh 2A0000h 2AFFFFh Sector SA41 SA40 SA39 SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Address range Start End address Address 290000h 29FFFFh 280000h 28FFFFh 270000h 27FFFFh 260000h 26FFFFh 250000h 25FFFFh 240000h 24FFFFh 230000h 23FFFFh 220000h 22FFFFh 210000h 21FFFFh 200000h 20FFFFh 1F0000h 1FFFFFh 1E0000h 1EFFFFh 1D0000h 1DFFFFh 1C0000h 1CFFFFh 1B0000h 1BFFFFh 1A0000h 1AFFFFh 190000h 19FFFFh 180000h 18FFFFh 170000h 17FFFFh 160000h 16FFFFh 150000h 15FFFFh 140000h 14FFFFh 130000h 13FFFFh 120000h 12FFFFh 110000h 11FFFFh 100000h 10FFFFh 0F0000h 0FFFFFh 0E0000h 0EFFFFh 0D0000h 0DFFFFh 0C0000h 0CFFFFh 0B0000h 0BFFFFh 0A0000h 0AFFFFh 090000h 09FFFFh 080000h 08FFFFh 070000h 07FFFFh 060000h 06FFFFh 050000h 05FFFFh 040000h 04FFFFh 030000h 03FFFFh 020000h 02FFFFh 010000h 01FFFFh 000000h 00FFFFh Sector SS31 SS30 SS29 SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 SS19 SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 Address range Start End address Address 01F000h 01E000h 01D000h 01C000h 01B000h 01A000h 019000h 018000h 017000h 016000h 015000h 014000h 013000h 012000h 011000h 010000h 00F000h 00E000h 00D000h 00C000h 00B000h 00A000h 009000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h 01FFFFh 01EFFFh 01DFFFh 01CFFFh 01BFFFh 01AFFFh 019FFFh 018FFFh 017FFFh 016FFFh 015FFFh 014FFFh 013FFFh 012FFFh 011FFFh 010FFFh 00FFFFh 00EFFFh 00DFFFh 00CFFFh 00BFFFh 00AFFFh 009FFFh 008FFFh 007FFFh 006FFFh 005FFFh 004FFFh 003FFFh 002FFFh 001FFFh 000FFFh Note Sector SA0 is split up into sub-sectors SS0 - SS15 (dark gray shading) Sector SA1 is split up into sub-sectors SS16 - SS31(light gray shading) Document Number: 002-00649 Rev. *J Page 16 of 63 Not Recommended for New Designs Sector S25FL064P Sector SS31 SS30 SS29 SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 SS19 SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 Address range Start End address Address 7FF000h 7FFFFFh 7FE000h 7FEFFFh 7FD000h 7FDFFFh 7FC000h 7FCFFFh 7FB000h 7FBFFFh 7FA000h 7FAFFFh 7F9000h 7F9FFFh 7F8000h 7F8FFFh 7F7000h 7F7FFFh 7F6000h 7F6FFFh 7F5000h 7F5FFFh 7F4000h 7F4FFFh 7F3000h 7F3FFFh 7F2000h 7F2FFFh 7F1000h 7F1FFFh 7F0000h 7F0FFFh 7EF000h 7EFFFFh 7EE000h 7EEFFFh 7ED000h 7EDFFFh 7EC000h 7ECFFFh 7EB000h 7EBFFFh 7EA000h 7EAFFFh 7E9000h 7E9FFFh 7E8000h 7E8FFFh 7E7000h 7E7FFFh 7E6000h 7E6FFFh 7E5000h 7E5FFFh 7E4000h 7E4FFFh 7E3000h 7E3FFFh 7E2000h 7E2FFFh 7E1000h 7E1FFFh 7E0000h 7E0FFFh Sector SA127 SA126 SA125 SA124 SA123 SA122 SA121 SA120 SA119 SA118 SA117 SA116 SA115 SA114 SA113 SA112 SA111 SA110 SA109 SA108 SA107 SA106 SA105 SA104 SA103 SA102 SA101 SA100 SA99 SA98 SA97 SA96 SA95 SA94 SA93 SA92 SA91 SA90 SA89 SA88 SA87 SA86 Address range Start End address Address 7F0000h 7FFFFFh 7E0000h 7EFFFFh 7D0000h 7DFFFFh 7C0000h 7CFFFFh 7B0000h 7BFFFFh 7A0000h 7AFFFFh 790000h 79FFFFh 780000h 78FFFFh 770000h 77FFFFh 760000h 76FFFFh 750000h 75FFFFh 740000h 74FFFFh 730000h 73FFFFh 720000h 72FFFFh 710000h 71FFFFh 700000h 70FFFFh 6F0000h 6FFFFFh 6E0000h 6EFFFFh 6D0000h 6DFFFFh 6C0000h 6CFFFFh 6B0000h 6BFFFFh 6A0000h 6AFFFFh 690000h 69FFFFh 680000h 68FFFFh 670000h 67FFFFh 660000h 66FFFFh 650000h 65FFFFh 640000h 64FFFFh 630000h 63FFFFh 620000h 62FFFFh 610000h 61FFFFh 600000h 60FFFFh 5F0000h 5FFFFFh 5E0000h 5EFFFFh 5D0000h 5DFFFFh 5C0000h 5CFFFFh 5B0000h 5BFFFFh 5A0000h 5AFFFFh 590000h 59FFFFh 580000h 58FFFFh 570000h 57FFFFh 560000h 56FFFFh Sector SA85 SA84 SA83 SA82 SA81 SA80 SA79 SA78 SA77 SA76 SA75 SA74 SA73 SA72 SA71 SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 Address range Start End address Address 550000h 55FFFFh 540000h 54FFFFh 530000h 53FFFFh 520000h 52FFFFh 510000h 51FFFFh 500000h 50FFFFh 4F0000h 4FFFFFh 4E0000h 4EFFFFh 4D0000h 4DFFFFh 4C0000h 4CFFFFh 4B0000h 4BFFFFh 4A0000h 4AFFFFh 490000h 49FFFFh 480000h 48FFFFh 470000h 47FFFFh 460000h 46FFFFh 450000h 45FFFFh 440000h 44FFFFh 430000h 43FFFFh 420000h 42FFFFh 410000h 41FFFFh 400000h 40FFFFh 3F0000h 3FFFFFh 3E0000h 3EFFFFh 3D0000h 3DFFFFh 3C0000h 3CFFFFh 3B0000h 3BFFFFh 3A0000h 3AFFFFh 390000h 39FFFFh 380000h 38FFFFh 370000h 37FFFFh 360000h 36FFFFh 350000h 35FFFFh 340000h 34FFFFh 330000h 33FFFFh 320000h 32FFFFh 310000h 31FFFFh 300000h 30FFFFh 2F0000h 2FFFFFh 2E0000h 2EFFFFh 2D0000h 2DFFFFh 2C0000h 2CFFFFh 2B0000h 2BFFFFh Sector SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Address range Start End address Address 2A0000h 2AFFFFh 290000h 29FFFFh 280000h 28FFFFh 270000h 27FFFFh 260000h 26FFFFh 250000h 25FFFFh 240000h 24FFFFh 230000h 23FFFFh 220000h 22FFFFh 210000h 21FFFFh 200000h 20FFFFh 1F0000h 1FFFFFh 1E0000h 1EFFFFh 1D0000h 1DFFFFh 1C0000h 1CFFFFh 1B0000h 1BFFFFh 1A0000h 1AFFFFh 190000h 19FFFFh 180000h 18FFFFh 170000h 17FFFFh 160000h 16FFFFh 150000h 15FFFFh 140000h 14FFFFh 130000h 13FFFFh 120000h 12FFFFh 110000h 11FFFFh 100000h 10FFFFh 0F0000h 0FFFFFh 0E0000h 0EFFFFh 0D0000h 0DFFFFh 0C0000h 0CFFFFh 0B0000h 0BFFFFh 0A0000h 0AFFFFh 090000h 09FFFFh 080000h 08FFFFh 070000h 07FFFFh 060000h 06FFFFh 050000h 05FFFFh 040000h 04FFFFh 030000h 03FFFFh 020000h 02FFFFh 010000h 01FFFFh 000000h 00FFFFh Note Sector SA126 is split up into sub-sectors SS0 - SS15 (dark gray shading) Sector SA127 is split up into sub-sectors SS16 - SS31 (light gray shading) Document Number: 002-00649 Rev. *J Page 17 of 63 Not Recommended for New Designs Table 8.2 S25FL064P Sector Address Table TBPARM=1 S25FL064P 9. Command Definitions The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on the rising edge of SCK. Table 9.1 lists the complete set of commands. The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Read (DOR), Quad Output Read (QOR), Dual I/O High Performance Read (DIOR), Quad I/O High Performance Read (QIOR), Read Status Register (RDSR), Read Configuration Register (RCR), Read OTP Data (OTPR), Read Manufacturer and Device ID (READ_ID), Read Identification (RDID) and Release from Deep Power-Down and Read Electronic Signature (RES) command sequences are followed by a data output sequence on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation. The Page Program (PP), Quad Page Program (QPP), 64 kB Sector Erase (SE), 4 kB Parameter Sector Erase (P4E), 8 kB Parameter Sector Erase (P8E), Bulk Erase (BE), Write Status and Configuration Registers (WRR), Program OTP space (OTPP), Write Enable (WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an exact multiple of eight. The device ignores any attempt to access the memory array during a Write Registers, program, or erase operation, and continues the operation uninterrupted. The instruction set is listed in Table 9.1. Table 9.1 Instruction Set Operation Read Write Control Erase Command Status & Configuration Register OTP Address Bytes Mode Bit Cycle Dummy Bytes Data Bytes READ (03h) 0000 0011 Read Data bytes 3 0 0 1 to ∞ (0Bh) 0000 1011 Read Data bytes at Fast Speed 3 0 1 1 to ∞ DOR (3Bh) 0011 1011 Dual Output Read 3 0 1 1 to ∞ QOR (6Bh) 0110 1011 Quad Output Read 3 0 1 1 to ∞ DIOR (BBh) 1011 1011 Dual I/O High Performance Read 3 1 0 1 to ∞ QIOR (EBh) 1110 1011 Quad I/O High Performance Read 3 1 2 1 to ∞ RDID (9Fh) 1001 1111 Read Identification 0 0 0 1 to 81 READ_ID (90h) 1001 0000 Read Manufacturer and Device Identification 3 0 0 1 to ∞ WREN (06h) 0000 0110 Write Enable 0 0 0 0 WRDI (04h) 0000 0100 Write Disable 0 0 0 0 P4E (20h) 0010 0000 4 kB Parameter Sector Erase 3 0 0 0 P8E (40h) 0100 0000 8 kB (two 4 kB) Parameter Sector Erase 3 0 0 0 (D8h) 1101 1000 64 kB Sector Erase 3 0 0 0 0 0 0 0 SE (60h) 0110 0000 or (C7h) 1100 0111 Bulk Erase 0 0 PP (02h) 0000 0010 Page Programming 3 0 0 1 to 256 QPP (32h) 0011 0010 Quad Page Programming 3 0 0 1 to 256 1 to ∞ RDSR (05h) 0000 0101 Read Status Register 0 0 0 WRR (01h) 0000 0001 Write (Status & Configuration) Registers 0 0 0 1 to 2 RCR (35h) 0011 0101 Read Configuration Register (CFG) 0 0 0 1 to ∞ CLSR (30h) 0011 0000 Reset the Erase and Program Fail Flag (SR5 and SR6) and restore normal operation) 0 0 0 0 DP Power Saving Description FAST_READ BE Program One Byte Command Code RES (B9h) 1011 1001 Deep Power-Down 0 0 0 0 (ABh) 1010 1011 Release from Deep Power-Down Mode 0 0 0 0 (ABh) 1010 1011 Release from Deep Power-Down and Read Electronic Signature 0 0 3 1 to ∞ OTPP (42h) 0100 0010 Programs one byte of data in OTP memory space 3 0 0 1 OTPR (4Bh) 0100 1011 Read data in the OTP memory space 3 0 1 1 to ∞ Document Number: 002-00649 Rev. *J Page 18 of 63 Not Recommended for New Designs Every command sequence begins with a one-byte command code. The command may be followed by address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written. S25FL064P 9.1 Read Data Bytes (READ) Figure 9.1 and Table 9.1 on page 18 detail the READ command sequence. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single READ command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The READ command is terminated by driving CS# high at any time during data output. The device rejects any READ command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.1 Read Data Bytes (READ) Command Sequence CS# Mode 3 SCK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 Command 24 Bit Address 23 22 21 SI 3 2 1 0 MSB SO Hi-Z Data Out 1 7 6 5 4 3 2 Data Out 2 1 0 7 MSB Document Number: 002-00649 Rev. *J Page 19 of 63 Not Recommended for New Designs The Read Data Bytes (READ) command reads data from the memory array at the frequency (fR) presented at the SCK input, with a maximum speed of 40 MHz. The host system must first select the device by driving CS# low. The READ command is then written to SI, followed by a 3 byte address (A23-A0). Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fR, on the falling edge of SCK. S25FL064P 9.2 Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ command sequence is shown in Figure 9.2 and Table 9.1 on page 18. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single FAST_READ command. When the highest address is reached, the address counter reverts to 000000h, allowing the read sequence to continue indefinitely. The FAST_READ command is terminated by driving CS# high at any time during data output. The device rejects any FAST_READ command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence CS# Mode 3 SCK 0 1 2 3 4 5 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 0 Command 24 Bit Address 23 22 21 SI SO 6 Hi-Z 3 2 Dummy Byte 1 0 7 6 5 4 3 2 1 0 7 MSB Document Number: 002-00649 Rev. *J 6 5 4 3 DATA OUT 1 2 1 0 7 MSB DATA OUT 2 Page 20 of 63 Not Recommended for New Designs The FAST_READ command reads data from the memory array at the frequency (fC) presented at the SCK input, with a maximum speed of 104 MHz. The host system must first select the device by driving CS# low. The FAST_READ command is then written to SI, followed by a 3 byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fC, on the falling edge of SCK. S25FL064P 9.3 Dual Output Read Mode (DOR) The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 2 bits at a time using 2 pins (SI/IO0 and SO/IO1) instead of 1 bit, at a maximum frequency of 80 MHz. The Dual Output Read mode effectively doubles the data transfer rate compared to the FAST_READ instruction. The Dual Output Read command sequence is shown in Figure 9.3 and Table 9.1 on page 18. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Dual Output Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. The Dual Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Dual Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.3 Dual Output Read Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK 24 Bit Address Instruction SI/IO0 23 22 21 * Hi-Z SO/IO1 3 Dummy Byte 2 1 0 7 6 5 4 3 2 SI Switches from Input to Output 1 0 6 4 2 0 6 4 2 0 6 7 5 3 1 7 5 3 1 7 * * Byte 1 * Byte 2 *MSB Document Number: 002-00649 Rev. *J Page 21 of 63 Not Recommended for New Designs The host system must first select the device by driving CS# low. The Dual Output Read command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through the IO0 (SI) & IO1 (SO) pins at a frequency fC on the falling edge of SCK. S25FL064P 9.4 Quad Output Read Mode (QOR) The host system must first select the device by driving CS# low. The Quad Output Read command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the address that are given, are shifted out four bits at a time through IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#) pins at a frequency fC on the falling edge of SCK. The Quad Output Read command sequence is shown in Figure 9.4 and Table 9.1 on page 18. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Quad Output Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. The Quad Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Quad Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the S25FL device. Figure 9.4 Quad Output Read Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Instruction SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 Hi-Z Hi-Z Hi-Z 24 Bit Address 23 22 21 * 3 2 1 Dummy Byte 0 7 6 5 4 3 2 1 0 * SI Switches from Input to Output 4 0 4 0 4 0 4 0 4 5 1 5 1 5 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 1 * * * * * DATA DATA DATA DATA OUT 1 OUT 2 OUT 3 OUT 4 Document Number: 002-00649 Rev. *J *MSB Page 22 of 63 Not Recommended for New Designs The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 4 bits at a time using 4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 bit, at a maximum frequency of 80 MHz. The Quad Output Read mode effectively doubles the data transfer rate compared to the Dual Output Read instruction, and is four times the data transfer rate of the FAST_READ instruction. S25FL064P 9.5 DUAL I/O High Performance Read Mode (DIOR) The Dual I/O High Performance Read instruction is similar to the Dual Output Read instruction, except that it improves throughput by allowing input of the address bits (A23-A0) using 2 bits per SCK via two input pins (SI/IO2 and SO/IO1), at a maximum frequency of 80 MHz. The DUAL I/O High Performance Read command sequence is shown in Figure 9.5 and Table 9.1 on page 18. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single DUAL I/O High Performance Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. In addition, address jumps can be done without exiting the Dual I/O High Performance Mode through the setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 9.5). This added feature removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O High Performance instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON’T CARE (“x”). If the Mode bits equal Axh, then the device remains in Dual I/O High Performance Read Mode and the next address can be entered (after CS# is raised high and then asserted low) without requiring the BBh instruction opcode, as shown in Figure 9.6, thus eliminating eight cycles for the instruction sequence. However, if the Mode bits are any value other than Axh, then the next instruction (after CS# is raised high and then asserted low) requires the instruction sequence, which is normal operation. The following sequences will release the device from Dual I/O High Performance Read mode; after which, the device can accept standard SPI instructions: 1. During the Dual I/O High Performance Instruction Sequence, if the Mode bits are any value other than Axh, then the next time CS# is raised high and then asserted low, the device will be released from Dual I/O High Performance Read mode. 2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 & IO1) are not set for a valid instruction sequence, then the device will be released from Dual I/O High Performance Read mode. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be driven high at any time during data output to terminate a read operation. Figure 9.5 DUAL I/O High Performance Read Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK 24 Bit Address Instruction SI/IO0 Hi-Z SO/IO1 IO0 & IO1 Switches from Input to Output 22 20 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 23 21 * 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 * * Mode Bits Document Number: 002-00649 Rev. *J * Byte 1 * Byte 2 *MSB Page 23 of 63 Not Recommended for New Designs The host system must first select the device by driving CS# low. The Dual I/O High Performance Read command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with two bits latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through IO0 (SI) and IO1 (SO). S25FL064P Figure 9.6 Continuous Dual I/O High Performance Read Instruction Sequence CS# 0 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK 24 Bit Address SO/IO1 22 20 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 23 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 21 * Mode Bits 9.6 * * * Byte 1 * Byte 2 *MSB Quad I/O High Performance Read Mode (QIOR) The Quad I/O High Performance Read instruction is similar to the Quad Output Read instruction, except that it further improves throughput by allowing input of the address bits (A23-A0) using 4 bits per SCK via four input pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3), at a maximum frequency of 80 MHz. The host system must first select the device by driving CS# low. The Quad I/O High Performance Read command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with four bits latched on the rising edge of SCK. Note that four dummy clocks are required prior to the data input. Then the memory contents, at the address that is given, are shifted out four bits at a time through IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#). The Quad I/O High Performance Read command sequence is shown in Figure 9.7 and Table 9.1 on page 18. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Quad I/O High Performance Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. In addition, address jumps can be done without exiting the Quad I/O High Performance Mode through the setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 9.7). This added feature the removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Quad I/O High Performance instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON'T CARE (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode and the next address can be entered (after CS# is raised high and then asserted low) without requiring the EBh instruction opcode, as shown in Figure 9.8, thus eliminating eight cycles for the instruction sequence. The following sequences will release the device from Quad I/O High Performance Read mode; after which, the device can accept standard SPI instructions: 1. During the Quad I/O High Performance Instruction Sequence, if the Mode bits are any value other than Axh, then the next time CS# is raised high and then asserted low the device will be released from Quad I/O High Performance Read mode. 2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0, IO1, IO2, & IO3) are not set for a valid instruction sequence, then the device will be released from Quad I/O High Performance Read mode. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be driven high at any time during data output to terminate a read operation. Document Number: 002-00649 Rev. *J Page 24 of 63 Not Recommended for New Designs SI/IO0 IO0 & IO1 Switches from Input to Output S25FL064P Figure 9.7 QUAD I/O High Performance Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCK 24 Bit Address SI/IO0 Hi-Z SO/IO1 IO’s Switches from Input to Output 20 16 0 4 0 4 0 4 0 4 21 17 1 5 1 5 1 5 1 5 22 18 2 6 2 6 2 6 2 6 7 3 3 7 Hi-Z W#/ACC/IO2 Hi-Z HOLD#/IO3 3 23 19 * 7 3 * Mode Bits DUMMY DUMMY 7 * * Byte 1 Byte 2 * *MSB Figure 9.8 Continuous QUAD I/O High Performance Instruction Sequence CS# 0 1 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK 24 Bit Address IO’s Switches from Input to Output SI/IO0 20 16 0 4 0 4 0 4 0 4 SO/IO1 21 17 1 5 1 5 1 5 1 5 W#/ACC/IO2 22 18 2 6 2 6 2 6 2 6 HOLD#/IO3 23 * 19 3 7 3 7 3 7 * Byte 2 * * Bits DUMMY Mode 7 DUMMY 3 * Byte 1 *MSB Document Number: 002-00649 Rev. *J Page 25 of 63 Not Recommended for New Designs Instruction S25FL064P 9.7 Read Identification (RDID) The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. The manufacturer identification is assigned by JEDEC; for Cypress devices, it is 01h. The device identification (2 bytes) and CFI bytes are assigned by the device manufacturer. The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. The system can read CFI information at the addresses given in Table 9.3. The host system must first select the device by driving CS# low. The RDID command is then written to SI, and each bit is latched on the rising edge of SCK. One byte of manufacture identification, two bytes of device identification and sixty-six bytes of extended device identification are then output from the memory array on SO at a frequency fR, on the falling edge of SCK. The maximum clock frequency for the RDID (9Fh) command is 50 MHz (Normal Read). The manufacturer ID and Device ID can be read repeatedly by applying multiples of 648 clock cycles. The manufacturer ID, Device ID and CFI table can be continuously read as long as CS# is held low with a clock input. The RDID command sequence is shown in Figure 9.9 and Table 9.1 on page 18. Driving CS# high after the device identification data has been read at least once terminates the RDID command. Driving CS# high at any time during data output (for example, while reading the extended CFI bytes), also terminates the RDID operation. The device rejects any RDID command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.9 Read Identification (RDID) Command Sequence and Data-Out Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 652 653 654 655 SCK Instruction SI Extended Device Information Manufacturer / Device Identification High Impedance SO 0 1 2 20 21 22 23 24 25 26 644 645 646 1 647 Table 9.2 Manufacturer & Device ID - RDID (JEDEC 9Fh) Device S25FL064P SPI flash Manuf. ID # Extended bytes Device Id Byte 0 Byte 1 Byte 2 Byte 3 01h 02h 16h 4Dh Notes 1. Byte 0 is Manufacturer ID of Cypress. 2. Byte 1 & 2 is Device Id. 3. Byte 3 is Extended Device Information String Length, to indicate how many Extended Device Information bytes will follow. 4. Bytes 4, 5 and 6 are Cypress reserved (do not use). 5. For Bytes 07h-0Fh and 3Dh-3Fh, the data will be read as 0xFF. 6. Bytes 10h-50h are factory programmed per JEDEC standard. Document Number: 002-00649 Rev. *J Page 26 of 63 Not Recommended for New Designs See Table 9.2 on page 26 for device ID data. S25FL064P Table 9.3 Product Group CFI Query Identification String Data 10h 51h 11h 52h 12h 59h 13h 02h 14h 00h 15h 40h 16h 00h 17h 00h 18h 00h 19h 00h 1Ah 00h Description Query Unique ASCII string “QRY” Primary OEM Command Set Not Recommended for New Designs Byte Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 9.4 Product Group CFI System Interface String Byte Data 1Bh 27h Description VCC Min. (erase/program): (D7-D4: Volt, D3-D0: 100 mV) 1Ch 36h VCC Max. (erase/program): (D7-D4: Volt, D3-D0: 100 mV) 1Dh 00h VPP Min. voltage (00h = no VPP pin present) 1Eh 00h VPP Max. voltage (00h = no VPP pin present) 1Fh 0Bh Typical timeout per single byte program 2N µs 20h 0Bh Typical timeout for Min. size Page program 2N µs (00h = not supported) 21h 09h Typical timeout per individual sector erase 2N ms 22h 10h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 01h Max. timeout for byte program 2N times typical 24h 01h Max. timeout for page program 2N times typical 25h 02h Max. timeout per individual sector erase 2N times typical 26h 01h Max. timeout for full chip erase 2N times typical (00h = not supported) Document Number: 002-00649 Rev. *J Page 27 of 63 S25FL064P Table 9.5 Product Group CFI Device Geometry Definition Byte Data 27h 17h Device Size = 2 N byte; Description 28h 05h Flash Device Interface Description; 00h = x8 only 01h = x16 only 02h = x8/x16 capable 05h 03h = x32 only Not Recommended for New Designs 29h 04h = Single I/O SPI, 3-byte address 05h = Multi I/O SPI, 3-byte address 2Ah 08h 2Bh 00h 2Ch 02h 2Dh 1Fh 2Eh 00h 2Fh 10h Max. number of bytes in multi-byte write = 2N (00 = not supported) Number of Erase Block Regions within device 1 = Uniform Device, 2 = Parameter Block Erase Block Region 1 Information (refer to CFI publication 100) 30h 00h 31h 7Dh 32h 00h 33h 00h 34h 01h 35h 00h 36h 00h 37h 00h 38h 00h 39h 00h 3Ah 00h 3Bh 00h 3Ch 00h Erase Block Region 2 Information (refer to CFI publication 100) Erase Block Region 3 Information (refer to CFI publication 100) Erase Block Region 4 Information (refer to CFI publication 100) Document Number: 002-00649 Rev. *J Page 28 of 63 S25FL064P Table 9.6 Product Group CFI Primary Vendor-Specific Extended Query Data 40h 50h 41h 52h 42h 49h Description Query-unique ASCII string “PRI” 43h 31h Major version number, ASCII 44h 33h Minor version number, ASCII 45h 15h Address Sensitive Unlock (Bits 1-0) 00b = Required, 01b = Not Required Process Technology (Bits 5-2) 0000b = 0.23 µm Floating Gate 0001b = 0.17 µm Floating Gate 0010b = 0.23 µm MirrorBit 0010b = 0.20 µm MirrorBit 0011b = 0.11 µm Floating Gate 0100b = 0.11 µm MirrorBit 0101b = 0.09 µm MirrorBit 1000b = 0.065 µm MirrorBit 46h 00h Erase Suspend 0 = Not Supported, 1 = Read Only, 2 = Read & Write 47h 02h Sector Protect 00 = Not Supported, X = Number of sectors in per smallest group 48h 00h Temporary Sector Unprotect 00 = Not Supported, 01 = Supported 49h 05h Sector Protect/Unprotect Scheme 04 = High Voltage Method 05 = Software Command Locking Method 08 = Advanced Sector Protection Method 4Ah 00h Simultaneous Operation 00 = Not Supported, X = Number of Sectors outside Bank 1 4Bh 01h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 03h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 03 = 256 Byte Page 4Dh 85h ACC (Acceleration) Supply Minimum 00 = Not Supported, (D7-D4: Volt, D3-D0: 100 mV) 4Eh 95h ACC (Acceleration) Supply Maximum 00 = Not Supported, (D7-D4: Volt, D3-D0: 100 mV) 4Fh 07h W# Protection 07 = Uniform Device with Top or Bottom Write Protect (user select) 50h 00h Program Suspend 00 = Not Supported, 01 = Supported Note CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering Information tables to obtain the VCC range for particular part numbers. Please consult the AC Characteristics on page 53 for typical timeout specifications. Document Number: 002-00649 Rev. *J Page 29 of 63 Not Recommended for New Designs Byte S25FL064P 9.8 Read-ID (READ_ID) The instruction is initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code “90h” followed by a 24bit address (which is either 00000h or 00001h). Following this, the Manufacturer ID and the Device ID are shifted out on the SO output pin starting after the falling edge of the SCK serial clock input signal. If the 24-bit address is set to 000000h, the Manufacturer ID is read out first followed by the Device ID. If the 24-bit address is set to 000001h, then the Device ID is read out first followed by the Manufacturer ID. The Manufacturer ID and the Device ID are always shifted out on the SO output pin with the MSB first, as shown in Figure 10-14. Once the device is in Read-ID mode, the Manufacturer ID and Device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition on the CS# input pin. The maximum clock frequency for the Read-ID (90h) command is at 104 MHz (FAST_READ). The Manufacturer ID & Device ID is output continuously until terminated by a low to high transition on CS# chip select input pin. Figure 9.10 Read-ID (RDID) Command Timing Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Instruction SI 24-Bit Address 23 22 21 MSB 3 2 1 0 Manufacture Identification Device Identification High Impedance 7 SO 6 5 4 3 2 1 0 Table 9.7 READ_ID Data-Out Sequence Address Uniform Manufacturer Identification 00000h 01h Device Identification 00001h 16h Document Number: 002-00649 Rev. *J Page 30 of 63 Not Recommended for New Designs The READ_ID instruction provides the S25FL064P manufacturer and device information and is provided as an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC Read Identification (RDID) commands. S25FL064P 9.9 Write Enable (WREN) The Write Enable (WREN) command (see Figure 9.11) sets the Write Enable Latch (WEL) bit to a 1, which enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Quad Page Program (QPP), Parameter Sector Erase (P4E, P8E), Erase (SE or BE), Write Registers (WRR) and OTP Program (OTPP) command. The host system must first drive CS# low, write the WREN command, and then drive CS# high. CS# Mode 3 SCK 0 1 2 3 4 5 6 7 Mode 0 Command SI Hi-Z SO 9.10 Write Disable (WRDI) The Write Disable (WRDI) command (see Figure 9.12) resets the Write Enable Latch (WEL) bit to a 0, which disables the device from accepting a Page Program (PP), Quad Page Program (QPP), Parameter Sector Erase (P4E, P8E), Erase (SE, BE), Write Registers (WRR) and OTP Program (OTPP) command. The host system must first drive CS# low, write the WRDI command, and then drive CS# high. Any of following conditions resets the WEL bit:  Power-up  Write Disable (WRDI) command completion  Write Registers (WRR) command completion  Page Program (PP) command completion  Quad Page Program (QPP) completion  Parameter Sector Erase (P4E, P8E) completion  Sector Erase (SE) command completion  Bulk Erase (BE) command completion  OTP Program (OTPP) completion Figure 9.12 Write Disable (WRDI) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command SI Hi-Z SO Document Number: 002-00649 Rev. *J Page 31 of 63 Not Recommended for New Designs Figure 9.11 Write Enable (WREN) Command Sequence S25FL064P 9.11 Read Status Register (RDSR) The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.8 shows the status register bits and their functions. The RDSR command may be written at any time, even while a program, erase, or Write Registers operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new command to the device if an operation is already in progress. Figure 9.13 shows the RDSR command sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven high. The maximum clock frequency for the RDSR command is 104 MHz. Table 9.8 S25FL064P Status Register Status Register Bit Bit Function Description 7 SRWD Status Register Write Disable 6 P_ERR Programming Error Occurred 5 E_ERR Erase Error Occurred 4 BP2 3 BP1 2 BP0 1 WEL Write Enable Latch 0 WIP Write in Progress Not Recommended for New Designs Bit 1 = Protects when W#/ACC is low 0 = No protection, even when W#/ACC is low 0 = No Error 1 = Error occurred 0 = No Error 1 = Error occurred Block Protect Protects selected Block from Program or Erase 1 = Device accepts Write Registers, program or erase commands 0 = Ignores Write Registers, program or erase commands 1 = Device Busy a Write Registers, program or erase operation is in progress 0 = Ready. Device is in standby mode and can accept commands. Figure 9.13 Read Status Register (RDSR) Command Sequence CS# Mode 3 SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Command SI SO Hi-Z 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB Status Register Out MSB Status Register Out The following describes the status and control bits of the Status Register. Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Registers, program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these operations is in progress; if WIP is 0, no such operation is in progress. This bit is a Read-only bit. Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Registers, program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the WRDI command, and is also automatically reset to 0 after the completion of a Write Registers, program, or erase operation, and after a power down/power up sequence. WEL cannot be directly set by the WRR command. Document Number: 002-00649 Rev. *J Page 32 of 63 S25FL064P Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored data. The Block Protection (BP2, BP1, BP0) bits are either volatile or non-volatile, depending on the state of the non-volatile bit BPNV in the Configuration register. The Block Protection (BP2, BP1, BP0) bits are written with the Write Registers (WRR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1’s, the relevant memory area is protected against Page Program (PP), Parameter Sector Erase (P4E, P8E), Sector Erase (SE), Quad Page Programming (QPP) and Bulk Erase (BE) instructions. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) instruction can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0’s. Erase Error bit (E_ERR): The Erase Error Bit is used as a Erase operation success and failure check. When the Erase Error bit is set to a “1”, it indicates that there was an error which occurred in the last erase operation. With the Erase Error bit set to a “1”, this bit is reset with the Clear Status Register (CLSR) command. Program Error bit (P_ERR): The Program Error Bit is used as a Program operation success and failure check. When the Program Error bit is set to a “1”, it indicates that there was an error which occurred in the last program operation. With the Program Error bit set to a “1”, this bit is reset with the Clear Status Register (CLSR) command. Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write Protect (W#/ACC) signal. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#/ACC) input pin. The Status Register Write Disable (SRWD) bit and the Write Protect (W#/ACC) signal allow the device to be put in the Hardware Protected mode. With the Status Register Write Disable (SRWD) bit set to a “1” and the W#/ACC driven to the logic low state, the device enters the Hardware Protected mode; the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) and the nonvolatile bits of the Configuration Register (TBPARM, TBPROT, BPNV and QUAD) become read-only bits and the Write Registers (WRR) instruction opcode is no longer accepted for execution. Note that the P_ERR and E_ERR bits will not be set to a 1 if the application writes to a protected memory area. 9.12 Read Configuration Register (RCR) The Read Configuration Register (RCR) instruction opcode allows the Configuration Register contents to be read out of the SO serial output pin. The Configuration Register contents may be read at any time, even while a program, erase, or write cycle is in progress. When one of these cycles is in progress, it is recommended to the user to check the Write In Progress (WIP) bit of the Status Register before issuing a new instruction opcode to the device. The Configuration Register originally shows 00h when the device is first shipped from the factory to the customer. (Refer to Section 7.8 on page 12 for more details). Figure 9.14 Read Configuration Register (RCR) Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 0 SCK In st r u ct i o n SI Configuration Register Out Configuration Register Out SO High Impedance 7 MSB Document Number: 002-00649 Rev. *J 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 7 MSB Page 33 of 63 Not Recommended for New Designs The default condition of the BP2-0 bits is binary 000 (all 0’s). S25FL064P 9.13 Write Registers (WRR) The Write Registers (WRR) command allows changing the bits in the Status and Configuration Registers. A Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to writing the WRR command. Table 9.8 shows the status register bits and their functions. The host system must drive CS# low, then write the WRR command and the appropriate data byte on SI Figure 9.15. The Status Register consists of one data byte in length; similarly, the Configuration Register is also one data byte in length. The CS# pin must be driven to the logic low state during the entire duration of the sequence. The WRR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit and W#/ACC pin together place the device in the Hardware Protected Mode (HPM). The device ignores all WRR commands once it enters the Hardware Protected Mode (HPM). Table 9.9 shows that W#/ACC must be driven low and the SRWD bit must be 1 for this to occur. The Write Registers (WRR) instruction has no effect on the P/E Error and the WIP bits of the Status & Configuration Registers. Any bit reserved for the future is always read as a 0 The CS# chip select input pin must be driven to the logic high state after the eighth (see Figure 9.15) or sixteenth (see Figure 9.16) bit of data has been latched in. If not, the Write Registers (WRR) instruction is not executed. If CS# is driven high after the eighth cycle then only the Status Register is written to; otherwise, after the sixteenth cycle both the Status and Configuration Registers are written to. As soon as the CS# chip select input pin is driven to the logic high state, the self-timed Write Registers cycle is initiated. While the Write Registers cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is a 1 during the self-timed Write Registers cycle, and is a 0 when it is completed. When the Write Registers cycle is completed, the Write Enable Latch (WEL) is set to a 0. The WRR command can operate at a maximum clock frequency of 104 MHz. Figure 9.15 Write Registers (WRR) Instruction Sequence – 8 data bits CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK In st r u ct i o n St at u s Regi st er In 7 SI 6 5 4 3 2 1 0 MSB SO Document Number: 002-00649 Rev. *J High Impedance Page 34 of 63 Not Recommended for New Designs The WRR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. S25FL064P Figure 9.16 Write Registers (WRR) Instruction Sequence – 16 data bits CS S# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK SI Status Register In 7 6 5 4 3 2 Configuration Register In 1 0 7 6 5 4 3 2 1 0 MSB MSB High Impedance SO Table 9.9 Protection Modes W#/ ACC SRWD Bit 1 1 1 0 0 0 0 1 Memory Content Mode Write Protection of Registers Protected Area Unprotected Area Software Protected (SPM) Status & Configuration Registers are Writable (if WREN instruction has set the WEL bit). The values in the SRWD, BP2, BP1, & BP0 bits & those in the Configuration Register can be changed Protected against Page Program, Parameter Sector Erase, Sector Erase, and Bulk Erase Ready to accept Page Program, Parameter Sector Erase, & Sector Erase instructions Hardware Protected (HPM) Status & Configuration Registers are Hardware Write Protected. The values in the SRWD, BP2, BP1, & BP0 bits & those in the Configuration Register cannot be changed Protected against Page Program, Parameter Sector Erase, Sector Erase, and Bulk Erase Ready to accept Page Program, Parameter Sector Erase, Sector Erase instructions Note As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.3 on page 14. Table 9.9 shows that neither W#/ACC or SRWD bit by themselves can enable HPM. The device can enter HPM either by setting the SRWD bit after driving W#/ACC low, or by driving W#/ACC low after setting the SRWD bit. However, the device disables HPM only when W#/ACC is driven high. Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM). If W#/ACC is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status Register) can be used. The Status and Configuration registers originally default to 00h, when the device is first shipped from the factory to the customer. Note: HPM is disabled when the Quad I/O Mode is enabled (Quad bit = 1 in the Configuration Register). W# becomes IO2; therefore, HPM cannot be utilized. Document Number: 002-00649 Rev. *J Page 35 of 63 Not Recommended for New Designs Instruction S25FL064P 9.14 Page Program (PP) The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN command is required prior to writing the PP command. The device programs only the last 256 data bytes sent to the device. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are programmed from the starting address of the same page (from the address whose 8 least significant bits are all zero). If fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effect on the other bytes in the same page. The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tPP. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see Table 7.3 on page 14). Figure 9.17 Page Program (PP) Command Sequence CS# 0 Mode 3 5 4 3 6 8 7 28 29 30 31 32 33 34 35 36 37 38 9 10 39 Mode 0 24 Bit Address 3 23 22 21 2 1 0 MSB 6 5 4 3 2 1 0 2078 2079 2076 55 2077 51 52 53 54 2072 MSB CS# 40 41 42 43 44 45 46 47 48 49 50 7 2075 SI Data Byte 1 2074 Command 2073 SCK 2 1 SCK Data Byte 2 SI 7 6 5 4 3 MSB Document Number: 002-00649 Rev. *J 2 Data Byte 3 1 0 7 6 MSB 5 4 3 2 Data Byte 256 1 0 7 6 5 4 3 2 1 0 MSB Page 36 of 63 Not Recommended for New Designs The host system must drive CS# low, and then write the PP command, three address bytes, and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are programmed from the starting address of the same page (from the address whose 8 least significant bits are all zero). CS# must be driven low for the entire duration of the PP sequence. The command sequence is shown in Figure 9.17 and Table 9.1 on page 18. S25FL064P 9.15 QUAD Page Program (QPP) To use QPP, the Quad Enable Bit in the Configuration Register must be set (QUAD = 1). A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL = 1). The instruction is initiated by driving the CS# pin low then shifting the instruction code “32h” followed by a 24 bit address (A23-A0) and at least one data byte, into the IO pins. The CS# pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Input Page Program are identical to standard Page Program. The QPP instruction sequence is shown below. Figure 9.18 QUAD Page Program Instruction Sequence CS# 0 1 2 4 3 5 6 7 8 9 28 10 29 30 31 32 33 34 35 36 37 38 39 2 1 0 4 0 4 0 4 0 4 0 1 5 1 5 1 SCK 24 Bit Address Instruction SI/IO0 3 21 23 22 * SO/IO1 5 1 5 W#/ACC/IO2 6 2 6 2 6 2 6 2 3 7 3 7 3 7 3 7 HOLD#/IO3 * Byte 1 * Byte 2 * Byte 3 * Byte 4 543 542 541 540 539 538 537 536 CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SI/IO0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO/IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 W#/ACC/IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 SCK HOLD#/IO3 7 3 * Byte 5 7 3 * Byte 6 7 3 * Byte 7 7 3 * Byte 8 7 3 * Byte 9 7 3 * Byte 10 7 3 * Byte 11 7 3 * Byte 12 4 0 3 3 7 3 7 3 7 * * * * Byte 253 Byte 254 Byte 255 Byte 256 7 *MSB Document Number: 002-00649 Rev. *J Page 37 of 63 Not Recommended for New Designs The Quad Page Program instruction is similar to the Page Program instruction, except that the Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#), instead of just one pin (SI) as in the case of the Page Program (PP) instruction. This effectively increases the data transfer rate by up to four times, as compared to the Page Program (PP) instruction. The QPP feature can improve performance for PROM Programmer and applications that have slow clock speeds < 5 MHz. Systems with faster clock speed will not realize much benefit for the QPP instruction since the inherent page program time is much greater than the time it take to clock-in the data. S25FL064P 9.16 Parameter Sector Erase (P4E, P8E) The Parameter Sector Erase (P4E, P8E) command sets all bits at all addresses within a specified sector to a logic 1 (FFh). A WREN command is required prior to writing the Parameter Sector Erase commands. The host system must drive CS# high after the device has latched the 24th bit of the P4E/P8E address, otherwise the device does not execute the command. The parameter sector erase operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tSE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the parameter sector erase operation is in progress. The WIP bit is 1 during the P4E/P8E operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). A Parameter Sector Erase (P4E, P8E) instruction applied to a sector that has been Write Protected through the Block Protect Bits will not be executed. The Parameter Sector Erase Command (P4E, P8E) consists of an 8-bit instruction and a 24-bit address. The Parameter sector is identified by the upper address bits (A23-A12). Any address within the Parameter sector can be used in the Parameter Sector Erase Commands. If the address is not a valid 4 kB Parameter sector address, the Parameter Sector Erase Command will be ignored, and the sector will not be erased. The P8E Parameter Sector Erase Command erases two sequential 4 kB Parameter sectors. The Parameter sector address LSB (A12) is disregarded so that the two Parameter sectors in the selected address space can be erased. If the sector address (A23A12) of Parameter sector n is an even number, Parameter sectors n and n+1 will be erased. If the sector address (A23-A12) of Parameter sector n is an odd number, Parameter sectors n and n-1 will be erased. Figure 9.19 Parameter Sector Erase (P4E, P8E) Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCK Instruction SI 24 Bit Address 23 22 21 3 2 1 0 MSB Document Number: 002-00649 Rev. *J Page 38 of 63 Not Recommended for New Designs The host system must drive CS# low, and then write the P4E or P8E command, plus three address bytes on SI. Any address within the sector (see Table 8.1 on page 16 and Table 8.2 on page 17) is a valid address for the P4E or P8E command. CS# must be driven low for the entire duration of the P4E/P8E sequence. The command sequence is shown in Figure 9.19 and Table 9.1 on page 18. S25FL064P 9.17 Sector Erase (SE) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the SE command. The host system must drive CS# high after the device has latched the 24th bit of the SE address, otherwise the device does not execute the command. The SE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tSE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a SE command for those sectors which are not protected by the Block Protect bits (BP2:BP0) (see Table 7.3 on page 14). Otherwise, the device ignores the command. A 64 kB sector erase (D8h) command issued on 4 kB or 8 kB erase sectors will erase all sectors in the specified 64 kB region. However, please note that a 4 kB sector erase (20h) or 8 kB sector erase (40h) command will not work on a 64 kB sector. Figure 9.20 Sector Erase (SE) Command Sequence CS# Mode 3 SCK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 1 0 Mode 0 Command SI 24 bit Address 23 22 21 3 2 MSB SO Hi-Z Document Number: 002-00649 Rev. *J Page 39 of 63 Not Recommended for New Designs The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any address within the sector (see Table 7.3 on page 14) is a valid address for the SE command. CS# must be driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.20 and Table 9.1 on page 18. S25FL064P 9.18 Bulk Erase (BE) The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the BE command. The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise the device does not execute the command. The BE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tBE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.3 on page 14). Otherwise, the device ignores the command. Figure 9.21 Bulk Erase (BE) Command Sequence CS# Mode 3 SCK 0 1 2 3 4 5 6 7 Mode 0 Command SI SO Hi-Z Document Number: 002-00649 Rev. *J Page 40 of 63 Not Recommended for New Designs The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the entire duration of the BE sequence. The command sequence is shown in Figure 9.21 and Table 9.1 on page 18. S25FL064P 9.19 Deep Power-Down (DP) The Deep Power-Down (DP) command provides the lowest power consumption mode of the device. It is intended for periods when the device is not in active use, and ignores all commands except for the Release from Deep Power-Down (RES) command. The DP mode therefore provides the maximum data protection against unintended write operations. The standard standby mode, which the device goes into automatically when CS# is high (and all operations in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise the device does not execute the command. After a delay of tDP, the device enters the DP mode and current reduces from ISB to IDP (see Table 16.1 on page 51). Once the device has entered the DP mode, all commands are ignored except the RES command (which releases the device from the DP mode). The RES command also provides the Electronic Signature of the device to be output on SO, if desired (see Section 9.20 and 9.20.1). DP mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.22 Deep Power-Down (DP) Command Sequence CS# tDP Mode 3 SCK 0 1 2 3 4 5 6 7 Mode 0 Command SI SO Hi-Z Standby Mode Document Number: 002-00649 Rev. *J Deep Power-down Mode Page 41 of 63 Not Recommended for New Designs The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the entire duration of the DP sequence. The command sequence is shown in Figure 9.22 and Table 9.1 on page 18. S25FL064P 9.20 Release from Deep Power-Down (RES) The device requires the Release from Deep Power-Down (RES) command to exit the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands except RES are ignored. The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire duration of the sequence. The command sequence is shown in Figure 9.23 and Table 9.1 on page 18. The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions from DP mode to the standby mode after a delay of tRES (see Figure 18.1). In the standby mode, the device can execute any read or write command. Not Recommended for New Designs Note: The RES command does not reset the Write Enable Latch (WEL) bit. Figure 9.23 Release from Deep Power-Down (RES) Command Sequence CS# Mode 3 SCK 0 1 2 3 4 5 6 7 Mode 0 Command tRES SI SO Hi-Z Deep Power-down Mode Document Number: 002-00649 Rev. *J Standby Mode Page 42 of 63 S25FL064P 9.20.1 Release from Deep Power-Down and Read Electronic Signature (RES) After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to output the Electronic Signature repeatedly. When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as previously described. The RES command always provides access to the Electronic Signature of the device and can be applied even if DP mode has not been entered. Any RES command issued while an erase, program, or Write Registers operation is in progress not executed, and the operation continues uninterrupted. Figure 9.24 Release from Deep Power-Down and RES Command Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK SI t RES 3 Dummy Bytes Instruction 23 22 21 3 2 1 0 MSB Electonic ID High Impedance SO 7 6 5 4 3 2 1 0 MSB Deep Power-Down Mode 9.21 Standby Mode Clear Status Register (CLSR) The Clear Status Register command resets bit SR5 (Erase Fail Flag) and bit SR6 (Program Fail Flag). It is not necessary to set the WEL bit before the Clear SR Fail Flags command is executed. The WEL bit will be unchanged after this command is executed. Figure 9.25 Clear Status Register (CLSR) Instruction Sequence CS S# 0 1 2 3 4 5 6 7 SCK Instruction SI Document Number: 002-00649 Rev. *J Page 43 of 63 Not Recommended for New Designs The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.24 and Table 9.1 on page 18 for the command sequence and signature value. The Electronic Signature is not to be confused with the identification data obtained using the RDID command. The device offers the Electronic Signature so that it can be used with previous devices that offered it; however, the Electronic Signature should not be used for new designs, which should read the RDID data instead. S25FL064P 9.22 OTP Program (OTPP) The OTP Program command programs data in the OTP region, which is in a different address space from the main array data. Refer to, “OTP Regions” for details on the OTP region. The protocol of the OTP Program command is the same as the Page Program command, except that the OTP Program command requires exactly one byte of data; otherwise, the command will be ignored. To program the OTP in bit granularity, the rest of the bits within the data byte can be set to “1”. Note: The Write Enable (WREN) command must precede the OTPP command before programming of the OTP can occur. Figure 9.26 OTP Program Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK 24 Bit Address Instruction 23 22 21 SI Data Byte 1 3 2 1 0 MSB 9.23 7 6 5 4 3 2 1 0 MSB Read OTP Data Bytes (OTPR) The Read OTP Data Bytes command reads data from the OTP region. Refer to “OTP Regions” for details on the OTP region. The protocol of the Read OTP Data Bytes command is the same as the Fast Read Data Bytes command except that it will not wrap to the starting address after the OTP address is at its maximum; instead, the data will be indeterminate. Figure 9.27 Read OTP Instruction Sequence CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK 24 Bit Address Instruction 23 22 21 SI 3 Dummy Byte 2 1 0 7 6 5 4 3 2 1 0 DATA OUT 1 SO High Impedance 7 MSB Document Number: 002-00649 Rev. *J 6 5 4 3 2 DATA OUT 2 1 0 7 MSB Page 44 of 63 Not Recommended for New Designs The OTP memory space can be programmed one or more times, provided that the OTP memory space is not locked (as described in “Locking OTP Regions”). Subsequent OTP programming can be performed only on the unprogrammed bits (that is, “1” data). S25FL064P 10. OTP Regions The OTP Regions are separately addressable from the main array and consists of two 8-byte (ESN), thirty 16-byte, and one 10-byte regions that can be individually locked. The two 8-byte ESN region is a special order part (please contact your local Cypress sales representative for further details). The two 8-byte regions enable permanent part identification through an Electronic Serial Number (ESN). The customer can utilize the ESN to pair a flash device with the system CPU/ASIC to prevent system cloning. The Cypress factory programs and locks the lower 8-byte ESN with a 64-bit randomly generated, unique number. The upper 8-byte ESN is left blank for customer use or, if special ordered, Cypress can program (and lock) in a unique customer ID. Standard part Special order part Lock Register ESN1 (Bit 0) Lock Register ESN2 (Bit 1) ESN1 Region Contains 1h 1h FFh FFh Unique random pattern Factory/Customer programmed pattern 0h 1h/0h ESN2 Region Contains  The thirty 16-byte and one 10-byte OTP regions are open for the customer usage.  The thirty 16-byte, one 10-byte, and upper 8-byte ESN OTP regions can be individually locked by the end user. Once locked, the data cannot changed. The locking process is permanent and cannot be undone. The following general conditions should be noted with respect to the OTP Regions:  On power-up, or following a hardware reset, or at the end of an OTPP or an OTPR command, the device reverts to sending commands to the normal address space.  Reads or Programs outside of the OTP Regions will be ignored  The OTP Region is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.  The ACC function is not available when accessing the OTP Regions.  The thirty 16-byte and one 10-byte OTP regions are left open for customer usage, but special care of the OTP locking must be maintained, or else a malevolent user can permanently lock the OTP regions. This is not a concern, if the OTP regions are not used. 10.1 Programming OTP Address Space The protocol of the OTP Program command (42h) is the same as the Page Program command. Refer to Table 9.1 for the command description and protocol. The OTP Program command can be issued multiple times to any given OTP address, but this address space can never be erased. After a given OTP region is programmed, it can be locked to prevent further programming with the OTP lock registers (refer to Section 10.3). The valid address range for OTP Program is depicted in the figure below. OTP Program operations outside the valid OTP address range will be ignored. 10.2 Reading OTP Data The protocol of the OTP Read command (4Bh) is the same as that of the Fast Read command. Refer to Table 9.1 for the command description and protocol. The valid address range for OTP Reads is depicted in the figure below. OTP Read operations outside the valid OTP address range will yield indeterminate data. 10.3 Locking OTP Regions In order to permanently lock the ESN and OTP regions, individual bits at the specified addresses can be set to 0 to lock specific regions of OTP memory, as highlighted in Figures 10.1 and 10.2. Document Number: 002-00649 Rev. *J Page 45 of 63 Not Recommended for New Designs  S25FL064P Figure 10.1 OTP Memory Map - Part 1 OT P R EGION ADDRESS 0x213h 16 bytes (OTP16) 0x204h 0x203h 16 bytes (OTP15) 0x1F4h 0x1F3h Not Recommended for New Designs 16 bytes (OTP14) 0x1E4h 0x1E3 16 bytes (OTP13) 0x1D4h 0x1D3h 16 bytes (OTP12) 0x1C4h 0x1C3h 16 bytes (OTP11) 0x1B4h 0x1B3h 16 bytes (OTP10) 0x1A4h 0x1A3h 16 bytes (OTP9) 0x194h 0x193h 16 bytes (OTP8) 0x184h 0x183h 16 bytes (OTP7) 0x174h 0x173h 16 bytes (OTP6) 0x164h 0x163h 16 bytes (OTP5) 0x154h 0x153h 16 bytes (OTP4) Address 0x112h 0x144h 0x143h 16 bytes (OTP3) 0x134h 0x133h 16 bytes (OTP2) 0x124h 0x123h 16 bytes (OTP1) 0x114h 0x113h 0x112h 0x111h 0x113h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8 bytes (ES N2) 0x10Ah 0x109h 8 bytes (ES N1) 0x102h 0x101h 0x100h 0x100h Reserved X X X X X X Bit 1 Bit 0 B it 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2- 7 Locks R egion… OTP1 OTP2 OTP3 OTP4 OTP5 OTP6 OTP7 OTP8 OTP9 OTP10 OTP11 OTP12 OTP13 OTP14 OTP15 OTP16 ESN1 ES N2 R eserved Notes 1. Bit 0 at address 0x100h locks ESN1 region. 2. Bit 1 at address 0x100h locks ESN2 region. 3. Bits 2-7 (“X”) are NOT programmable and will be ignored. Document Number: 002-00649 Rev. *J Page 46 of 63 S25FL064P Figure 10.2 OTP Memory Map - Part 2 OT P R EGION ADDRESS 0x2FFh 10 bytes (OTP31) 0x2F6h 0x2F5h 16 bytes (OTP30) 0x2E6h 0x2E5 Not Recommended for New Designs 16 bytes (OTP29) 0x2D6h 0x2D5h 16 bytes (OTP28) 0x2C6h 0x2C5h 16 bytes (OTP27) 0x2B6h 0x2B5h 16 bytes (OTP26) 0x2A6h 0x2A5h 16 bytes (OTP25) 0x296h 0x295h 16 bytes (OTP24) 0x286h 0x285h 16 bytes (OTP23) 0x276h 0x275h 16 bytes (OTP22) 0x266h 0x265h 16 bytes (OTP21) Address 0x214h 0x256h 0x255h 16 bytes (OTP20) 0x246h 0x245h 16 bytes (OTP19) 0x236h 0x235h 0x215h 16 bytes (OTP18) 0x226h 0x225h 16 bytes (OTP17) 0x216h 0x215h 0x214h X Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B it 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Locks Region… OTP17 OTP18 OTP19 OTP20 OTP21 OTP22 OTP23 OTP24 OTP25 OTP26 OTP27 OTP28 OTP29 OTP30 OTP31 R eserved Note 1. Bit 7 (“X”) at address 0x215h is NOT programmable and will be ignored. Document Number: 002-00649 Rev. *J Page 47 of 63 S25FL064P 11. Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows (see Figure 11.1 and Table 11.1 on page 49):  At power-up, VCC (min.) plus a period of tPU  At power-down, GND No Read, Write Registers, program, or erase command should be sent to the device until VCC rises to the VCC min., plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power-Down mode) and the WEL bit is reset (0). Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed. When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all operations are disabled and the device does not respond to any commands. Note that data corruption may result if a power-down occurs while a Write Registers, program, or erase operation is in progress. Figure 11.1 Power-Up Timing Diagram Vcc (max) Vcc (min) Vcc t PU Full Device Access Time Figure 11.2 Power-down and Voltage Drop Document Number: 002-00649 Rev. *J Page 48 of 63 Not Recommended for New Designs A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements. S25FL064P Table 11.1 Power-Up / Power-Down Voltage and Timing VCC(cut-off) VCC(low) Parameter Min Max Unit VCC (minimum operation voltage) 2.7 V VCC (Cut off where re-initialization is needed) 2.4 V VCC (Low voltage for initialization to occur at read/standby) VCC (Low voltage for initialization to occur at embedded) 0.2 V tPU VCC(min.) to device operation TPD VCC (low duration time) 2.3 300 µs 1.0 µs 12. Initial Delivery State The device is delivered with the memory array erased i.e. all bits are set to 1 (FFh) upon initial factory shipment. The Status Register and Configuration Register contains 00h (all bits are set to 0). 13. Program Acceleration via W#/ACC Pin The program acceleration function requires applying VHH to the W#/ACC input, and then waiting a period of tWC. Minimum tVHH rise and fall times is required for W#/ACC to change to VHH from VIL or VIH. Removing VHH from the W#/ACC pin returns the device to normal operation after a period of tWC. Figure 13.1 ACC Program Acceleration Timing Requirements VHH ACC tWC tWC VIL or VIH tVHH tVHH VIL or VIH Command OK Note Only Read Status Register (RDSR) and Page Program (PP) operation are allow when ACC is at (VHH). The W#/ACC pin is disabled during Quad I/O mode. Table 13.1 ACC Program Acceleration Specifications Symbol Min. Max VHH ACC Pin Voltage High Parameter 8.5 9.5 tVHH ACC Voltage Rise and Fall time 2.2 µs tWC ACC at VHH and VIL or VIH to First command 5 µs Document Number: 002-00649 Rev. *J Unit V Page 49 of 63 Not Recommended for New Designs Symbol VCC(min) S25FL064P 14. Electrical Specifications Absolute Maximum Ratings Description Rating Ambient Storage Temperature -65°C to +150°C -0.5V to VCC+0.5V Voltage with Respect to Ground: All Inputs and I/Os Output Short Circuit Current (Note 2) 200 mA Notes 1. Minimum DC voltage on input or I/Os is -0.5V. During voltage transitions, inputs or I/Os may undershoot GND to -2.0V for periods of up to 20 ns. See Figure 14.1. Maximum DC voltage on input or I/Os is VCC + 0.5V. During voltage transitions inputs or I/Os may overshoot to VCC + 2.0V for periods up to 20 ns. See Figure 14.2. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Figure 14.1 Maximum Negative Overshoot Waveform 20 ns 20 ns +0.8V –0.5V –2.0V 20 ns Figure 14.2 Maximum Positive Overshoot Waveform 20 ns VCC +2.0V VCC +0.5V 2.0V 20 ns 20 ns 15. Operating Ranges Table 15.1 Operating Ranges Description Ambient Operating Temperature (TA) Positive Power Supply Rating Industrial –40°C to +85°C Automotive In-Cabin –40°C to +105°C Voltage Range 2.7V to 3.6V Note Operating ranges define those limits between which functionality of the device is guaranteed. Document Number: 002-00649 Rev. *J Page 50 of 63 Not Recommended for New Designs 14.1 S25FL064P 16. DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 17.1 on page 52, when relying on the quoted parameters. Table 16.1 DC Characteristics (CMOS Compatible) Limits Parameter Test Conditions Min. VCC Supply Voltage VHH ACC Program Acceleration Voltage VIL Typ* Unit Max 2.7 3.6 V 8.5 9.5 V Input Low Voltage -0.3 0.3 x VCC V VIH Input High Voltage 0.7 x VCC VCC +0.5 V VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min. VOH Output High Voltage IOH = -0.1 mA VCC = 2.7V to 3.6V 0.4 VCC-0.6 Not Recommended for New Designs Symbol V V ILI Input Leakage Current VCC = VCC Max, VIN = VCC or GND ±2 µA ILO Output Leakage Current VCC = VCC Max, VIN = VCC or GND ±2 µA At 80 MHz (Dual or Quad) 38 ICC1 Active Power Supply Current READ (SO = Open) At 104 MHz (Serial) 26 At 40 MHz (Serial) 15 ICC2 Active Power Supply Current (Page Program) CS# = VCC 26 mA ICC3 Active Power Supply Current (WRR) CS# = VCC 15 mA ICC4 Active Power Supply Current (SE) CS# = VCC 26 mA ICC5 Active Power Supply Current (BE) CS# = VCC 26 mA ISB1 Standby Current CS# = VCC; VIN = GND or VCC 80 200 µA IPD Deep Power-down Current CS# = VCC; VIN = GND or VCC 3 10 µA mA *Typical values are at TAI = 25°C and VCC = 3V Document Number: 002-00649 Rev. *J Page 51 of 63 S25FL064P 17. Test Conditions Figure 17.1 AC Measurements I/O Waveform 0.8 VCC 0.7 VCC 0.5 VCC 0.3 VCC Input Levels Not Recommended for New Designs 0.2 VCC Input and Output Timing Reference levels Table 17.1 Test Specifications Symbol Parameter CL Load Capacitance Min Max 30 Input Rise and Fall Times Unit pF 5 ns Input Pulse Voltage 0.2 VCC to 0.8 VCC V Input Timing Reference Voltage 0.3 VCC to 0.7 VCC V Output Timing Reference Voltage 0.5 VCC V Document Number: 002-00649 Rev. *J Page 52 of 63 S25FL064P 18. AC Characteristics Figure 18.1 AC Characteristics Parameter (Notes) Min. (Notes) Typ (Notes) Max (Notes) Unit MHz SCK Clock Frequency for READ command DC 40 SCK Clock Frequency for RDID command DC 50 SCK Clock Frequency for all others: FAST_READ, PP, QPP, P4E, P8E, SE, BE, DP, RES, WREN, WRDI, RDSR, WRR, READ_ID DC 104 (serial) 80 (dual/quad) tWH, tCH (5) Clock High Time 4.5 tWL, tCL (5) Clock Low Time 4.5 ns tCRT, tCLCH Clock Rise Time (slew rate) 0.1 V/ns tCFT, tCHCL Clock Fall Time (slew rate) 0.1 V/ns tCS CS# High Time (Read Instructions) CS# High Time (Program/Erase) 10 tCSS CS# Active Setup Time (relative to SCK) 3 ns tCSH CS# Active Hold Time (relative to SCK) 3 ns tSU:DAT Data in Setup Time 3 ns tHD:DAT Data in Hold Time 2 fR fC tV ns ns 50 Clock Low to Output Valid 0 tHO Output Hold Time 2 tDIS Output Disable Time MHz ns 8 (Serial)Δ 9.5 (Dual/Quad)Δ 6.5 (Serial)∞ 8 (Dual/Quad)∞ 7 (Dual/Quad)Ω ns ns 8 ns tHLCH HOLD# Active Setup Time (relative to SCK) 3 ns tCHHH HOLD# Active Hold Time (relative to SCK) 3 ns tHHCH HOLD# Non Active Setup Time (relative to SCK) 3 ns tCHHL HOLD# Non Active Hold Time (relative to SCK) 3 ns tHZ HOLD# enable to Output Invalid 8 ns tLZ HOLD# disable to Output Valid 8 ns tWPS W#/ACC Setup Time (4) 20 tWPH W#/ACC Hold Time (4) 100 tW WRR Cycle Time tPP Page Programming (1)(2) tEP Page Programming (ACC = 9V) (1)(2)(3) tSE Sector Erase Time (64 kB) (1)(2) tPE Not Recommended for New Designs Symbol (Notes) ns ns 100 ms 1.5 3 ms 1.2 2.4 ms 0.5 2 sec Parameter Sector Erase Time(4 kB or 8 kB) (1)(2) 200 800 ms 64 tBE Bulk Erase Time (1)(2) 128 sec tRES Deep Power-down to Standby Mode 30 µs tDP Time to enter Deep Power-down Mode 10 µs tVHH ACC Voltage Rise and Fall time tWC ACC at VHH and VIL or VIH to first command 2.2 µs 5 µs Notes 1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern 2. Under worst-case conditions of 85°C; VCC = 2.7V; 100,000 cycles. 3. Acceleration mode (9V ACC) only in Program mode, not Erase. 4. Only applicable as a constraint for WRR instruction when SRWD is set to a 1. 5. tWH + tWL must be less than or equal to 1/fC. Document Number: 002-00649 Rev. *J Page 53 of 63 S25FL064P 6. Δ Full VCC range (2.7 – 3.6V) & CL = 30 pF 7. ∞ Regulated VCC range (3.0 – 3.6V) and CL = 30 pF 8. Ω Regulated VCC range (3.0 – 3.6V) and CL = 15 pF Capacitance Symbol CIN COUT Parameter Test Conditions Input Capacitance (applies to SCK, PO7-PO0, SI, CS#) Typ Max Unit VOUT = 0V 9.0 12.0 pF VIN = 0V 12.0 16.0 pF Output Capacitance (applies to PO7-PO0, SO) Min Not Recommended for New Designs 18.1 Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. 3. For more information on pin capacitance, please consult the IBIS models. Figure 18.2 SPI Mode 0 (0,0) Input Timing tCS CS# tCSH tCSS tCSH tCSS SCK tSU:DAT tHD:DAT SI tCRT tCFT MSB IN SO LSB IN Hi-Z Figure 18.3 SPI Mode 0 (0,0) Output Timing CS# tWH SCK tV tHO SO Document Number: 002-00649 Rev. *J tV tWL tDIS tHO LSB OUT Page 54 of 63 S25FL064P Figure 18.4 HOLD# Timing CS# tCHHL tHHCH tHLCH SCK tHZ Not Recommended for New Designs tCHHH tLZ SO SI HOLD# Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1 W# tWPS tWPH CS# SCK SI SO Hi-Z Document Number: 002-00649 Rev. *J Page 55 of 63 S25FL064P 19. Data Integrity 19.1 Erase Endurance Minimum Unit Program/Erase cycles per main Flash array sectors Parameter 100K PE cycle Program/Erase cycles per PPB array or non-volatile register array (1) 100K PE cycle Note: 1. Each write command to a non-volatile register causes a PE cycle on the entire non-volatile register array. OTP bits and registers internally reside in a separate array that is not cycled. 19.2 Data Retention Table 19.2 Data Retention Industrial and Industrial Plus Temperature Parameter Data Retention Time Test Conditions Minimum Time Unit 1K Program/Erase Cycles 20 Years 10K Program/Erase Cycles 2 Years 100K Program/Erase Cycles 0.2 Years Contact Cypress Sales and FAE for further information on the data integrity. An application note is available at http://www.cypress.com/appnotes. Document Number: 002-00649 Rev. *J Page 56 of 63 Not Recommended for New Designs Table 19.1 Erase Endurance Industrial and Industrial Plus Temperature S25FL064P 20. Physical Dimensions 20.1 SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) Not Recommended for New Designs 0.20 C A-B 0.10 C D 2X 0.33 C 0.25 M C A-B D 0.10 C 0.10 C DIMENSIONS SYMBOL NOTES: NOM. MAX. 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2.35 - 2.65 A1 0.10 - 0.30 A2 2.05 - 2.55 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 5. DATUMS A AND B TO BE DETERMINED AT DATUM H. 6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. A MIN. b 0.31 - 0.51 b1 c 0.27 - 0.48 0.20 - 0.33 c1 0.20 - 0.30 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 - L1 1.40 REF L2 0.25 BSC 8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT 1.27 16 N h 0.25 - 0 0° - 8° 01 5° - 15° 02 0° - - MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. 9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 0.75 CYPRESS Company Confidential TITLE THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION. Document Number: 002-00649 Rev. *J DRAWN BY PACKAGE CODE(S) SO3016 SL3016 SS3016 KOTA APPROVED BY BESY DATE 24-OCT-16 PACKAGE OUTLINE, 16 LEAD SOIC 10.30X7.50X2.65 MM SO3016/SL3016/SS3016 SPEC NO. DATE 24-OCT-16 SCALE : TO FIT REV 002-15547 *A SHEET 1 OF 2 Page 57 of 63 S25FL064P WNF 008 — WSON 8-contact (6 x 8 mm) No-Lead Package NOTES: DIMENSIONS SYMBOL MIN. e MAX. 1.27 BSC. 8 N ND L NOM. 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. 4 DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED 4 0.50 0.45 N IS THE TOTAL NUMBER OF TERMINALS. BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS 0.55 THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE b 0.35 0.40 0.45 D2 4.70 4.80 4.90 5 ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE. E2 5.70 5.80 5.90 6. 7. MAX. PACKAGE WARPAGE IS 0.05mm. 8 9 PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE. D 6.00 BSC E 8.00 BSC 0.75 0.02 0.20 MIN. 0.80 0.05 - 0.15 A A1 0.70 0.00 K L1 0.00 Not Recommended for New Designs 20.2 DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA. MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 10 A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT. CYPRESS Company Confidential TITLE THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION. Document Number: 002-00649 Rev. *J DRAWN BY PACKAGE CODE(S) WNF008 KOTA APPROVED BY LKSU DATE 23-FEB-17 PACKAGE OUTLINE, 8 LEAD DFN 6.0X8.0X0.8 MM WNF008 4.8X5.8 MM EPAD (SAWN) SPEC NO. DATE 23-FEB-17 SCALE : TO FIT REV 002-18902 ** SHEET 1 OF 2 Page 58 of 63 S25FL064P FAB024 — 24-ball Ball Grid Array (6 x 8 mm) package NOTES: DIMENSIONS SYMBOL MIN. A - A1 0.20 NOM. MAX. - 1.20 - - 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. D 8.00 BSC 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. E 6.00 BSC 4. e REPRESENTS THE SOLDER BALL GRID PITCH. D1 4.00 BSC 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. E1 4.00 BSC MD 5 ME 5 N Not Recommended for New Designs 20.3 SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE 24 b 0.40 0.35 PARALLEL TO DATUM C. 0.45 7 "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE eE 1.00 BSC eD 1.00 BSC POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. SD 0.00 BSC WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. SE 0.00 BSC WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. CYPRESS Company Confidential TITLE THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION. Document Number: 002-00649 Rev. *J DRAWN BY PACKAGE CODE(S) FAB024 KOTA APPROVED BY BESY DATE 18-JUL-16 PACKAGE OUTLINE, 24 BALL FBGA 8.0X6.0X1.2 MM FAB024 SPEC NO. DATE 18-JUL-16 SCALE : TO FIT REV 002-15534 ** SHEET 1 OF 2 Page 59 of 63 S25FL064P FAC024 — 24-ball Ball Grid Array (6 x 8 mm) package NOTES: DIMENSIONS SYMBOL MIN. NOM. MAX. 1. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 4. e 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. A - - 1.20 A1 0.25 - - D 8.00 BSC E 6.00 BSC D1 5.00 BSC E1 3.00 BSC MD 6 ME 4 N 0.35 0.40 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 24 b Not Recommended for New Designs 20.4 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 0.45 7 "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE eE 1.00 BSC eD 1.00 BSC SD 0.50 BSC WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. SE 0.50 BSC WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. "SE" = eE/2. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. CYPRESS Company Confidential TITLE THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION. Document Number: 002-00649 Rev. *J DRAWN BY PACKAGE CODE(S) FAC024 KOTA APPROVED BY BESY DATE 18-JUL-16 PACKAGE OUTLINE, 24 BALL FBGA 8.0X6.0X1.2 MM FAC024 SPEC NO. DATE 18-JUL-16 SCALE : TO FIT REV 002-15535 ** SHEET 1 OF 2 Page 60 of 63 S25FL064P 21. Revision History Document Title: S25FL064P, 64-Mbit 3.0 V SPI Flash Memory Document Number: 002-00649 Orig. of Submission Rev. ECN No. Description of Change Change Date ** – BWHA 07/18/2008 Initial release Added BGA package information Added BGA package Added Automotive In-cabin information Added BGA package information Corrected Valid Combination Table Added Suggested Cross Setting Table Updated Configuration Register Table Added note for ACC function Updated Instruction Set Table Added statement for Dual Output Read command. Added statement for Dual Output Read command Updated Read Identification description Updated figure for RDID Updated CFI table for 29h and 45h *A – BWHA 07/02/2009 Added note for P_ERR and E_ERR Updated figure for RCR Added note for HPM Updated description for P4E/P8E command Updated figure for Parameter Sector Erase Updated description for SE command Added note for RES command Updated figure for RES Updated descriptions Added ESN1 ESN2 Table Updated Power-Up / Power-Down Voltage and Timing Table Updated ICC1 and ICC3 Added Automotive In-cabin spec for fC Updated tWH, tCH and tWL, tCL Added BGA 6 x 8 mm package Changed all references to RDID clock rate from 40 to 50 MHz Added “5 x 5 pin configuration” to Figure 2.3 title Added 6 x 4 pin configuration BGA connection diagram Added note regarding exposed central pad on bottom of package to the WSON connection diagram Added 02 and 03 model numbers for BGA packages *B – BWHA 10/05/2009 Added Low-Halogen material option Changed valid BGA model number combinations to 02 and 03 Changed valid BGA material option to Low-Halogen Added Automotive In-Cabin temperature valid combination for BGA packages Removed Note 1 Added FAC024 BGA package Removed 76 MHz Automotive in-cabin spec and Note 9 Document Number: 002-00649 Rev. *J Page 61 of 63 Not Recommended for New Designs Document History S25FL064P Document Title: S25FL064P, 64-Mbit 3.0 V SPI Flash Memory Document Number: 002-00649 Orig. of Submission Rev. ECN No. Description of Change Change Date Clarified that TBPARM and TBPROT must be selected at the initial configuration of the device, before any program or erase operations In the Instruction Set table, corrected the CLSR Data Byte Cycle value from 1 to 0 Clarified proper Parameter Sector Erase command usage on different types of sectors Clarified that the device only executes a SE command for those sectors which are not protected by the Block Protection Bits *C – BWHA 04/05/2011 Clarified that a 64 kB sector erase command will work on 4 kB and 8 kB sectors Removed incomplete statement regarding internal state machine Corrected ESN1 and ESN2 Register data on a standard part from 0h to FFh Corrected Lock Register ESN1 data on a special order part from 1h to 0h Clarified that for locking OTP regions, “setting the bit” refers to changing the value from 1 to 0 Updated S03106 package outline drawing to latest revision Updated WNF008 package outline drawing to latest revision Corrected tPU *D – BWHA 11/18/2011 Modified section Added notes to table *E – BWHA 09/21/2012 Changed Output Hold Time (tHO) to 2 ns (min) Instruction Set table: Corrected the value of RES, OTPP, and OTPR commands Protection Mode table: Added Parameter Sector Erase to Memory Content col*F – BWHA 10/30/2012 umns for clarification Updated the table reference Added “Typical” values column *G – BWHA 01/29/2013 Corrected “Max” values for CIN / COUT (Input / Output Capacitance) *H 4926108 ASPA 09/18/2015 Updated to Cypress template. Added Automotive Temperature Grade related information in all instances across the document. Updated Ordering Information on page 8: *I 5406237 NFB 08/18/2016 Updated Valid Combinations on page 9: Added S25FL064P Valid Combinations — Automotive Grade / AEC-Q100 on page 9. Updated Copyright and Disclaimer. Added watermark “Not Recommended for New Designs” across the document. Added “This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede S25FL064P. These are the factory-recommended migration paths. Please refer to the S25FL-L Family data sheets for specifications and ordering information.” in page 1. Added Data Integrity on page 56. Updated Physical Dimensions on page 57: *J 5711159 ECAO 05/22/2017 Updated SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) on page 57. Updated WNF 008 — WSON 8-contact (6 x 8 mm) No-Lead Package on page 58. Updated FAB024 — 24-ball Ball Grid Array (6 x 8 mm) package on page 59. Updated FAC024 — 24-ball Ball Grid Array (6 x 8 mm) package on page 60. Updated to new template. Document Number: 002-00649 Rev. *J Page 62 of 63 Not Recommended for New Designs Document History (Continued) S25FL064P Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions ® ® ARM Cortex Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory Microcontrollers cypress.com/iot cypress.com/memory cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). 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If the Software is not acompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-00649 Rev. *J Revised May 22, 2017 Page 63 of 63 Not Recommended for New Designs Products
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