Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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S25FL256L/S25FL128L
256-Mb (32-MB)/128-Mb (16-MB),
3.0 V FL-L Flash Memory
General Description
The Cypress FL-L Family devices are Flash non-volatile memory products using:
■
Floating Gate technology
■
65 nm process lithography
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides
individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match
or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,
executing code directly (XIP), and storing re-programmable data.
Features
■
Serial Peripheral Interface (SPI) with Multi-I/O
❐ Clock polarity and phase modes 0 and 3
❐ Double Data Rate (DDR) option
❐ Quad peripheral Interface (QPI) option
❐ Extended Addressing: 24- or 32-bit address options
❐ Serial Command subset and footprint compatible with
S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI
families
❐ Multi I/O Command subset and footprint compatible with
S25FL-P, S25FL-S and S25FS-S SPI families
■
Read
❐ Commands: Normal, Fast, Dual I/O, Quad I/O, DualO,
QuadO, DDR Quad I/O.
❐ Modes: Burst Wrap, Continuous (XIP), QPI
❐ Serial Flash Discoverable Parameters (SFDP) for configuration information.
■
Program Architecture
❐ 256 Bytes Page Programming buffer
❐ 3.0 V FL-L Flash Memory
❐ Program suspend and resume
■
Erase Architecture
❐ Uniform 4 KB Sector Erase
❐ Uniform 32 KB Half Block Erase
❐ Uniform 64 KB Block Erase
❐ Chip erase
❐ Erase suspend and resume
■
100,000 Program/Erase Cycles, minimum
■
20 Year Data Retention, minimum
Cypress Semiconductor Corporation
Document Number: 002-00124 Rev. *H
•
■
Security features
❐ Status and Configuration Register Protection
❐ Four Security Regions of 256 bytes each outside the main
Flash array
❐ Legacy Block Protection: Block range
❐ Individual and Region Protection
• Individual Block Lock: Volatile individual Sector/Block
• Pointer Region: Non-Volatile Sector/Block range
• Power Supply Lock-down, Password, or Permanent protection of Security Regions 2 and 3 and Pointer Region
■
Technology
❐ 65 nm Floating Gate Technology
■
Single Supply Voltage with CMOS I/O
❐ 2.7 V to 3.6 V
■
Temperature Range / Grade
❐ Industrial (–40 °C to +85 °C)
❐ Industrial Plus (–40 °C to +105 °C)
❐ Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
❐ Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
❐ Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)
■
Packages (all Pb-free)
❐ 8-pin SOIC 208 mil (SOC008) — S25FL128L only
❐ WSON 5 6 mm (WND008) — S25FL128L only
❐ WSON 6 8 mm (WNG008) — S25FL256L only
❐ 16-pin SOIC 300 mil (SO3016)
❐ BGA-24 6 8 mm
• 5 5 ball (FAB024) footprint
• 4 6 ball (FAC024) footprint
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 11, 2018
S25FL256L/S25FL128L
Performance Summary
Maximum Read Rates SDR
Command
Clock Rate (MHz)
MBps
Read
50
6.25
Fast Read
133
16.5
Dual Read
133
33
Quad Read
133
66
Clock Rate (MHz)
MBps
66
66
Maximum Read Rates DDR
Command
DDR Quad Read
Typical Program and Erase Rates
Operation
KBps
Page Programming
854
4 KB Sector Erase
80
32 KB Half Block Erase
168
64 KB Block Erase
237
Typical Current Consumption, –40 °C to +85 °C
Operation
Typical Current
Fast Read 5 MHz
10
Fast Read 10 MHz
10
Fast Read 20 MHz
10
Fast Read 50 MHz
15
Fast Read 108 MHz
25
Fast Read 133 MHz
30
Quad I/O / QPI Read 108 MHz
25
Quad I/O / QPI Read 133 MHz
30
Quad I/O / QPI DDR Read 33 MHz
15
Quad I/O / QPI DDR Read 66 MHz
30
Program
40
Erase
40
Standby SPI
20
Standby QPI
60
Deep Power Down
2
Document Number: 002-00124 Rev. *H
Unit
mA
µA
Page 2 of 160
S25FL256L/S25FL128L
Contents
1.
1.1
Product Overview ........................................................ 4
Migration Notes.............................................................. 4
2.
2.1
2.2
2.3
2.4
Connection Diagrams..................................................
SOIC 16-Lead ................................................................
8 Connector Packages...................................................
BGA Ball Footprint .........................................................
Special Handling Instructions for FBGA Packages........
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
Signal Descriptions ..................................................... 7
Input/Output Summary................................................... 7
Multiple Input / Output (MIO).......................................... 8
Serial Clock (SCK) ......................................................... 8
Chip Select (CS#) .......................................................... 8
Serial Input (SI) / IO0 ..................................................... 8
Serial Output (SO) / IO1................................................. 8
Write Protect (WP#) / IO2 .............................................. 8
IO3 / RESET# ................................................................ 9
RESET# ......................................................................... 9
Voltage Supply (VCC)..................................................... 9
Supply and Signal Ground (VSS) ................................... 9
Not Connected (NC) ...................................................... 9
Reserved for Future Use (RFU)................................... 10
Do Not Use (DNU) ....................................................... 10
4.
4.1
Block Diagram............................................................ 11
System Block Diagrams............................................... 11
5.
5.1
5.2
5.3
5.4
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Data Protection ............................................................
6.
6.1
6.2
6.3
6.4
6.5
6.6
Address Space Maps................................................. 23
Overview ...................................................................... 23
Flash Memory Array..................................................... 23
ID Address Space ........................................................ 24
JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space.............................................................. 24
Security Regions Address Space ................................ 24
Registers...................................................................... 25
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Data Protection ..........................................................
Security Regions..........................................................
Deep Power Down .......................................................
Write Enable Commands .............................................
Write Protect Signal .....................................................
Status Register Protect (SRP1, SRP0)........................
Array Protection ...........................................................
Individual and Region Protection .................................
43
43
43
44
44
45
46
53
8.
8.1
8.2
8.3
8.4
8.5
Commands .................................................................
Command Set Summary..............................................
Identification Commands .............................................
Register Access Commands........................................
Read Memory Array Commands .................................
Program Flash Array Commands ................................
58
58
64
68
82
90
Document Number: 002-00124 Rev. *H
5
5
5
6
6
13
13
14
18
22
8.6
8.7
8.8
8.9
8.10
8.11
8.12
Erase Flash Array Commands...................................... 92
Security Regions Array Commands............................ 100
Individual Block Lock Commands ............................... 102
Pointer Region Command........................................... 107
Individual and Region Protection (IRP) Commands ... 108
Reset Commands ....................................................... 115
Deep Power Down Commands................................... 116
9.
9.1
9.2
Data Integrity ............................................................. 119
Erase Endurance ........................................................ 119
Data Retention ............................................................ 119
10. Software Interface Reference .................................. 120
10.1 JEDEC JESD216B Serial Flash Discoverable
Parameters ................................................................. 120
10.2 Device ID Address Map .............................................. 129
10.3 Initial Delivery State .................................................... 129
11.
11.1
11.2
11.3
11.4
11.5
11.6
Electrical Specifications........................................... 130
Absolute Maximum Ratings ........................................ 130
Latchup Characteristics .............................................. 130
Thermal Resistance .................................................... 130
Operating Ranges....................................................... 131
Power-Up and Power-Down ....................................... 132
DC Characteristics ...................................................... 134
12.
12.1
12.2
12.3
12.4
12.5
12.6
Timing Specifications............................................... 137
Key to Switching Waveforms ...................................... 137
AC Test Conditions ..................................................... 137
Reset .......................................................................... 138
SDR AC Characteristics ............................................. 141
DDR AC Characteristics ............................................. 144
Embedded Algorithm Performance Tables ................. 146
13. Ordering Information ................................................ 147
13.1 Ordering Part Number................................................. 147
14.
14.1
14.2
14.3
14.4
14.5
14.6
Physical Diagrams .................................................... 150
SOIC 16-Lead, 300-mil Body Width (SO3016) ........... 150
SOIC 8-Lead, 208 mil Body Width (SOC008)............. 151
WSON 8-Contact 5 x 6 mm Leadless (WND008) ....... 152
WSON 8-Contact 6 x 8 mm Leadless (WNG008)....... 153
Ball Grid Array 24-ball 6 x 8 mm (FAB024)................. 154
Ball Grid Array 24-ball 6 x 8 mm (FAC024) ................ 155
15.
15.1
15.2
15.3
15.4
Other Resources ....................................................... 156
Glossary...................................................................... 156
Link to Cypress Flash Roadmap................................. 157
Link to Software .......................................................... 157
Link to Application Notes ............................................ 157
16. Document History ..................................................... 158
Sales, Solutions, and Legal Information ......................... 160
Worldwide Sales and Design Support .......................... 160
Products ....................................................................... 160
PSoC® Solutions ......................................................... 160
Cypress Developer Community .................................... 160
Technical Support ........................................................ 160
Page 3 of 160
S25FL256L/S25FL128L
1.
Product Overview
1.1
Migration Notes
1.1.1 Features Comparison
The FL-L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families.
Table 1. Cypress SPI Families Comparison
Parameter
Technology Node
FL-L
FL-S
FL1-K
FL-P
65 nm
65 nm
90 nm
90 nm
MirrorBit Eclipse™
Floating Gate
MirrorBit®
®
Architecture
Floating Gate
Release Date
In Production
In Production
In Production
In Production
256 Mb
128 Mb - 1 Gb
4 Mb - 64 Mb
32 Mb - 256 Mb
x1, x2, x4
x1, x2, x4
x1, x2, x4
x1, x2, x4
2.7 V - 3.6 V
2.7 V - 3.6 V /
1.65 V - 3.6 V VIO
2.7 V - 3.6 V
2.7 V - 3.6 V
6 MBps (50 MHz)
6 MBps (50 MHz)
6 MBps (50 MHz)
5 MBps (40 MHz)
Density
Bus Width
Supply Voltage
Normal Read Speed
Fast Read Speed
16.5 MBps (133 MHz)
17 MBps (133 MHz)
13 MBps (108 MHz)
13 MBps (104 MHz)
Dual Read Speed
33 MBps (133 MHz)
26 MBps (104 MHz)
26 MBps (108 MHz)
20 MBps (80 MHz)
Quad Read Speed
66 MBps (133 MHz)
52 MBps (104 MHz)
52 MBps (108 MHz)
40 MBps (80 MHz)
Quad Read Speed (DDR)
66 MBps (66 MHz)
80 MBps (80 MHz)
–
–
Program Buffer Size
256B
256B / 512B
256B
256B
4 KB / 32 KB / 64 KB
64 KB / 256 KB
4 KB / 64 KB
64 KB / 256 KB
-
4 KB (option)
–
4 KB
Sector / Block Erase Rate (typ.)
80 KBps (4 KB)
168 KBps (32 KB
237 KBps (64 KB)
500 KBps
136 KBps (4 KB)
437 KBps (64 KB)
130 KBps
Page Programming Rate (typ.)
854 KBps (256B)
1.2 MBps (256B)
1.5 MBps (512B)
365 KBps
170 KBps
1024B
1024B
768B (3 256B)
506B
Erase Sector/Block Size
Parameter Sector Size
Security Region / OTP
Individual and Region Protection
or Advanced Sector Protection
No
Yes
Erase Suspend/Resume
Yes
Program Suspend/Resume
Operating Temperature
No
Yes
–40 °C to +85 °C
–40 °C to +105 °C
–40 °C to +125 °C
–40 °C to +85 °C
–40 °C to +105 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +105 °C
Note
1. Refer to individual datasheets for further details.
Document Number: 002-00124 Rev. *H
Page 4 of 160
S25FL256L/S25FL128L
2.
Connection Diagrams
2.1
SOIC 16-Lead
Figure 1. 16-Lead SOIC Package (SO3016), Top View
IO3 / RESET#
1
16
SCK
VCC
2
15
SI / IO0
RESET#
3
14
RFU
NC
4
13
DNU
SOIC 16
NC
5
12
DNU
RFU
6
11
DNU
CS#
7
10
VSS
SO / IO1
8
9
WP# / IO2
Note
2. The RESET# and IO3 / RESET# inputs have an internal pull-up and may be left unconnected in the system if quad mode, mode and hardware reset are not in use.
2.2
8 Connector Packages
Figure 2. 8-Pin Plastic Small Outline Package (SOIC8)
CS#
1
8
V CC
SO / IO 1
2
7
IO 3 / RESET#
SO IC
W P# / IO 2
3
6
SCK
V SS
4
5
SI / IO 0
Figure 3. 8-Connector Package (WSON 6 x 8) (WSON 5 x 6), Top View
C S#
1
8
VCC
S O / IO 1
2
7
IO 3 / R ES ET#
W P # / IO 2
3
6
SC K
VSS
4
5
S I / IO 0
W SO N
Note
3. The RESET# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use.
Document Number: 002-00124 Rev. *H
Page 5 of 160
S25FL256L/S25FL128L
2.3
BGA Ball Footprint
Figure 4. 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View
1
2
3
4
5
A
NC
NC
RESET#
NC
DNU
SCK
VSS
VCC
NC
DNU
CS#
RFU
WP#/IO2
NC
DNU
SO/IO1
NC
NC
B
C
D
SI/IO0 IO3/RESET#
NC
E
NC
RFU
NC
Notes
4. Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use either package.
5. The RESET# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use.
Figure 5. 24-Ball BGA, 4 x 6 Ball Footprint (FAC024), Top View
1
2
3
4
NC
NC
NC
RESET#
DNU
SCK
VSS
VCC
DNU
CS#
RFU
WP#/IO2
DNU
SO/IO1
NC
NC
NC
RFU
NC
NC
NC
NC
A
B
C
D
SI/IO0 IO3/RESET#
E
F
Note
6. The RESET# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use.
2.4
Special Handling Instructions for FBGA Packages
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Document Number: 002-00124 Rev. *H
Page 6 of 160
S25FL256L/S25FL128L
3.
Signal Descriptions
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large
number of signal connections and larger package size. The large number of connections increase power consumption due to so
many signals switching and the larger package increases cost.
The FL-L family reduces the number of signals for connection to the host system by serially transferring all control, address, and
data information over 6 signals. This reduces the cost of the memory package, reduces signal switching power, and either reduces
the host connection count or frees host connectors for use in providing other features.
The FL-L family uses the industry standard single bit SPI and also supports optional extension commands for two bit (Dual) and four
bit (Quad) wide serial transfers. This multiple width interface is called SPI Multi-I/O or SPI-MIO.
3.1
Input/Output Summary
Table 2. Signal List
Signal Name
Type
Description
RESET#
Input
Hardware Reset: Low = device resets and returns to standby state, ready to receive a command. The signal has an
internal pull-up resistor and may be left unconnected in the host system if not used.
SCK
Input
Serial Clock.
CS#
Input
SI / IO0
I/O
SO / IO1
I/O
Chip Select.
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
Write Protect when not in Quad mode (CR1V[1] = 0 and SR1NV[7] = 1).
IO2 when in Quad mode (CR1V[1] = 1).
WP# / IO2
I/O
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad
commands or write protection. If write protection is enabled by SR1NV[7] = 1 and CR1V[1] = 0, the host system is
required to drive WP# high or low during a WRR or WRAR command.
IO3 in Quad-I/O mode, when Configuration Register 1 QUAD bit, CR1V[1] =1, or in QPI mode, when Configuration
Register 2 QPI bit, CR2V[3] =1 and CS# is low.
IO3 / RESET#
I/O
RESET# when enabled by CR2V[7]=1 and not in Quad-I/O mode, CR1V[1] = 0, or when enabled in quad mode,
CR1V[1] = 1 and CS# is high.
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad
commands or RESET#.
VCC
Supply
Power Supply.
VSS
Supply
Ground.
NC
Unused
Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use
the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board
(PCB). However, any signal connected to an NC must not have voltage levels higher than VCC.
RFU
Reserved for Future Use. No device internal signal is currently connected to the package connector but there is
Reserved potential future use of the connector for a signal. It is recommended to not use RFU connectors for PCB routing
channels so that the PCB may take advantage of future enhanced features in compatible footprint devices.
DNU
Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by
Cypress for test or other purposes and is not intended for connection to any host system signal. Any DNU signal
Reserved related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels.
Do not connect any host system signal to this connection.
Note
7. Inputs with internal pull-ups or pull-downs drive less than 2 A. Only during power-up is the current larger at 150 A for 4 S. Resistance of pull-ups or pull-down
resistors with the typical process at Vcc = 3.3 V at –40°C is ~4.5 M and at 90°C is ~6.6 M.
Document Number: 002-00124 Rev. *H
Page 7 of 160
S25FL256L/S25FL128L
3.2
Multiple Input / Output (MIO)
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the Serial Input (SI)
signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI/IO0 signal. Address or data is sent from
the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host
similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
QPI mode transfers all instructions, addresses, and data from the host to the memory as four bit (nibble) groups on IO0, IO1, IO2,
and IO3. Data is returned to the host similarly as four bit (nibble) groups on IO0, IO1, IO2, and IO3.
3.3
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on
the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR commands.
3.4
Chip Select (CS#)
The chip select signal indicates when a command is transferring information to or from the device and the other signals are relevant
for the memory device.
When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are
high impedance. The device will be in the Standby Power mode, unless an internal embedded operation is in progress. An
embedded operation is indicated by the Status Register 1 Write-In-Progress bit (SR1V[0]) set to 1, until the operation is completed.
Some example embedded operations are: Program, Erase, or Write Registers (WRR) operations.
Driving the CS# input to the logic low state enables the device, placing it in the Active Power mode. After Power-up, a falling edge on
CS# is required prior to the start of any command.
3.5
Serial Input (SI) / IO0
This input signals used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed.
Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 - an input and output during Dual and Quad
commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock
signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
3.6
Serial Output (SO) / IO1
This output signals used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock
signal. SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be
programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK in
SDR commands, and on every edge of SCK, in DDR commands).
3.7
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), when the Status Register Protect 0 (SRP0_NV) or (SRP0) bit of Status Register 1 (SR1NV[7]) or
(SR1V[7]) is set to a 1, it is not possible to write to Status Registers, Configuration Registers or DLR registers. In this situation, the
command selecting SR1NV, SR1V, CR1NV,CR1V, CR2NV, CR2V, CR3NV, DLRNV and DLRV is ignored, and no error is set.
This prevents any alteration of the Legacy Block Protection settings. As a consequence, all the data bytes in the memory area that
are protected by the Legacy Block Protection feature are also hardware protected against data modification if WP# is Low during
commands changing Status Registers, Configuration Registers or DLR registers, with SRP0_NV set to 1. Similarly, the Security
Region Lock Bits (LB3-LB0) are protected against programming.
The WP# function is not available when the Quad mode is enabled (CR1V[1]=1) or QPI mode is enabled (CR2V[3]=1). The WP#
function is replaced by IO2 for input and output during Quad mode or QPI mode is enabled (CR2V[3]=1) for receiving addresses,
and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data on the falling edge of
SCK, in SDR commands, and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host system if not
used for Quad mode or QPI mode or protection.
Document Number: 002-00124 Rev. *H
Page 8 of 160
S25FL256L/S25FL128L
3.8
IO3 / RESET#
IO3 is used for input and output during Quad mode (CR1V[1]=1) or QPI mode is enabled (CR2V[3]=1) for receiving addresses, and
data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK,
in SDR commands, and on every edge of SCK, in DDR commands).
The IO3 / RESET# input may also be used to initiate the hardware reset function when the IO3 / RESET# feature is enabled by
writing Configuration Register 2 non-volatile bit 7 (CR2NV[7]=1). The input is only treated as RESET# when the device is not in
Quad modes (114,144,444), CR1V[1] = 0, or when CS# is high. When Quad modes are in use, CR1V[1]=1or QPI mode is enabled
(CR2V[3]=1), and the device is selected with CS# low, the IO3 / RESET# is used only as IO3 for information transfer. When CS# is
high, the IO3 / RESET# is not in use for information transfer and is used as the reset input. By conditioning the reset operation on
CS# high during Quad modes (114,144,444), the reset function remains available during Quad modes (114,144,444).
When the system enters a reset condition, the CS# signal must be driven high as part of the reset process and the IO3 / RESET#
signal is driven low. When CS# goes high the IO3 / RESET# input transitions from being IO3 to being the reset input. The reset
condition is then detected when CS# remains high and the IO3 / RESET# signal remains low for tRP. If a reset is not intended, the
system is required to actively drive IO3 / RESET# to high along with CS# being driven high at the end of a transfer of data to the
memory. Following transfers of data to the host system, the memory will drive IO3 high during tCS. This will ensure that IO3 /
RESET# is not left floating or being pulled slowly to high by the internal or an external passive pull-up. Thus, an unintended reset is
not triggered by the IO3 / RESET# not being recognized as high before the end of tRP.
The IO3 / RESET# input reset feature is disabled when (CR2V[7]=0).
The IO3 / RESET# input has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode
or the reset function. The internal pull-up will hold IO3 / RESET# high after the host system has actively driven the signal high and
then stops driving the signal.
Note that IO3 / RESET# input cannot be shared by more than one SPI-MIO memory if any of them are operating in Quad I/O mode
as IO3 being driven to or from one selected memory may look like a reset signal to a second non-selected memory sharing the same
IO3 / RESET# signal.
3.9
RESET#
The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a command. When
RESET# is driven to logic low (VIL) for at least a period of tRP, the device starts the hardware reset process.
RESET# causes the same initialization process as is performed when power comes up and requires tPU time.
RESET# may be asserted low at any time. To ensure data integrity any operation that was interrupted by a hardware reset should
be reinitiated once the device is ready to accept a command sequence.
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used. The internal pull-up will hold
Reset high after the host system has actively driven the signal high and then stops driving the signal.
The RESET# input is not available on all packages options. When not available the RESET# input of the device is tied to the inactive
state.
3.10 Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read,
program, and erase.
3.11 Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.
3.12 Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The
connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).
Document Number: 002-00124 Rev. *H
Page 9 of 160
S25FL256L/S25FL128L
3.13 Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but there is potential future use of the connector. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced
features in compatible footprint devices.
3.14 Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other
purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the
signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.
Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
Document Number: 002-00124 Rev. *H
Page 10 of 160
S25FL256L/S25FL128L
4.
Block Diagram
Figure 6. Logic Block Diagram
X Decoders
CS#
SCK
SI/IO0
SO/IO1
Memory Array
Y Decoders
I/O
Data Latch
WP#/IO2
Control
Logic
RESET#/IO3
Data Path
RESET#
4.1
System Block Diagrams
Figure 7. Bus Master and Memory Devices on the SPI Bus — Single Bit Data Path
RESET#
WP#
RESET#
WP#
SI
SO
SCK
SI
SO
SCK
CS2#
CS1#
CS#
CS#
SPI
Bus Master
SPI Flash
SPI Flash
Figure 8. Bus Master and Memory Devices on the SPI Bus — Dual Bit Data Path
RESET#
WP#
RESET#
WP#
IO1
IO0
SCK
IO1
IO0
SCK
CS2#
CS1#
SPI
Bus Master
Document Number: 002-00124 Rev. *H
CS#
CS#
SPI Flash
SPI Flash
Page 11 of 160
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Figure 9. Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path — Separate RESET#
RESET#
IO3
IO2
IO1
IO0
SCK
RESET#
IO3
IO2
IO1
IO0
SCK
CS2#
CS1#
SPI
Bus Master
CS#
CS#
SPI Flash
SPI Flash
Figure 10. Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path — I/O3 / RESET#
IO3 / RESET#
IO2
IO1
IO0
SCK
CS#
SPI
Bus Master
Document Number: 002-00124 Rev. *H
IO3 / RESET#
IO2
IO1
IO0
SCK
CS#
SPI Flash
Page 12 of 160
S25FL256L/S25FL128L
5.
5.1
Signal Protocols
SPI Clock Modes
5.1.1 Single Data Rate (SDR)
The FL-L family can be driven by an embedded micro-controller (bus master) in either of the two following clocking modes.
■
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
■
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is
always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data.
■
SCK will stay at logic low state with CPOL = 0, CPHA = 0
■
SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 11. SPI SDR Modes Supported
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
SI_IO0
MSb
SO_IO1
MSb
Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by showing SCK as both
high and low at the fall of CS#. In some cases a timing diagram may show only mode 0 with SCK low at the fall of CS#. In such a
case, mode 3 timing simply means clock is high at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of
CS# is needed for mode 3.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode 0 the beginning of the
first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low
at the beginning of a command.
5.1.2 Double Data Rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always latched on the rising
edge of clock, the same as in SDR commands. However, the address and input data that follow the instruction are latched on both
the rising and falling edges of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end
of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the next falling edge of
SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge
of SCK because SCK is already low at the beginning of a command.
Figure 12. SPI DDR Modes Supported
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
Transfer_Phase
IO0
Instruction
Inst. 0
Mode
Dummy / DLP
A28 A24
A0 M4 M0
DLP.
DLP.
D0 D1
IO1
A29 A25
A1 M5 M1
DLP.
DLP.
D0 D1
IO2
A30 A26
A2 M6 M2
DLP.
DLP.
D0 D1
IO3
A31 A27
A3 M7 M3
DLP.
DLP.
D0 D1
Document Number: 002-00124 Rev. *H
Inst. 7
Address
Page 13 of 160
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5.2
Command Protocol
All communication between the host system and FL-L family memory devices is in the form of units called commands. See
Section 8. Commands on page 58 for definition and details for all commands.
All commands begin with an 8-bit instruction that selects the type of information transfer or device operation to be performed.
Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the
memory. All instruction, address, and data information is transferred sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three
command phases:
■
instruction;
■
address and instruction modifier (continuous read mode bits);
■
data.
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI signal. Data may be
sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol for single bit width instruction, single
bit width address and modifier, single bit data.
Dual-O or Quad-O commands provide an address sent from the host as serial on SI (IO0) then followed by dummy cycles. Data is
returned to the host as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-1-2 for
Dual-O and 1-1-4 for Quad-O command protocols.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)
groups on IO0, IO1, IO2, and IO3 then followed by dummy cycles. Data is returned to the host similarly as bit pairs on IO0 and IO1
or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command
protocols.
The FL-L family also supports a QPI mode in which all information is transferred in 4-bit width, including the instruction, address,
modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
■
Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host driving
the Chip Select (CS#) signal low throughout a command.
■
The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
■
Each command begins with an eight bit (byte) instruction. The instruction selects the type of information transfer or device operation
to be performed. The instruction transfers occur on SCK rising edges. However, some read commands are modified by a prior read
command, such that the instruction is implied from the earlier command. This is called Continuous Read Mode. When the device
is in continuous read mode, the instruction bits are not transmitted at the beginning of the command because the instruction is the
same as the read command that initiated the Continuous Read Mode. In Continuous Read mode the command will begin with the
read address. Thus, Continuous Read Mode removes eight instruction bits from each read command in a series of same type read
commands.
■
The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in
the device. The instruction determines the address space used. The address may be either a 24-bit or a 32-bit, byte boundary,
address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
■
In legacy SPI mode, the width of all transfers following the instruction are determined by the instruction sent. Following transfers
may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per (dual)
transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per (quad) transfer on the IO0-IO3 signals. Within the dual
or quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher numbered IO
signal. Single bits or parallel bit groups are transferred in most to LSb order.
■
In QPI mode, the width of all transfers is a 4-bit wide (quad) transfer on the IO0-IO3 signals.
■
Dual and Quad I/O read instructions send an instruction modifier called Continuous Read mode bits, following the address, to indicate
whether the next command will be of the same type with an implied, rather than an explicit, instruction. These mode bits initiate or
end the continuous read mode. In continuous read mode, the next command thus does not provide an instruction byte, only a new
address and mode bits. This reduces the time needed to send each command when the same command type is repeated in a
sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR
commands.
Document Number: 002-00124 Rev. *H
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S25FL256L/S25FL128L
■
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read
data is returned to the host.
■
Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
■
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles (also referred to
as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on SCK falling edge at
the end of the last read latency cycle. The first read data bits are considered transferred to the host on the following SCK rising
edge. Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
■
If the command returns read data to the host, the device continues sending data transfers until the host takes the CS# signal high.
The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the command.
■
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go high after the eighth
bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be driven high when
the number of bits after the CS# signal was driven low is an exact multiple of eight bits. If the CS# signal does not go high exactly
at the eight bit boundary of the instruction or write data, the command is rejected and not executed.
■
All instruction, address, and mode bits are shifted into the device with the MSb first. The data bits are shifted in and out of the device
MSb first. All data is transferred in byte units with the lowest address byte sent first. Following bytes of data are sent in lowest to
highest byte address order i.e. the byte address increments.
■
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The
embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded
operation. These are discussed in the individual command descriptions.
■
Depending on the command, the time for execution varies. A command to read status information from an executing command is
available to determine when the command completes execution and whether the command was successful.
5.2.1 Command Sequence Examples
Figure 13. Stand Alone Instruction Command
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1-IO3
Phase
Instruction
Figure 14. Single Bit Wide Input Command
CS#
SCLK
SO_IO1-IO3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
Figure 15. Single Bit Wide Output Command without Latency
CS#
SCLK
SI
7
6
5
4
3
SO
Phase
2
1
0
7
Instruction
Document Number: 002-00124 Rev. *H
6
5
4
3
Data 1
2
1
0
7
6
5
4
3
2
1
0
Data 2
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S25FL256L/S25FL128L
Figure 16. Single Bit Wide I/O Command with Latency
CS#
SCLK
SI
7
6
5
4
3
2
1
0 31
1
0
SO
7
Phase
Instruction
Address
6
5
Dummy Cycles
4
3
2
1
0
Data 1
Figure 17. Dual Output Read Command
CS#
SCK
IO0
7
6
5
4
3
2
1
0
31
1
0
IO1
Phase
Instruction
Address
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
Dummy Cycles
Data 1
Data 2
Figure 18. Quad Output Read Command
CS#
SCK
IO0
4 0
4
0 4
0
4 0
4
0 4
IO1
7
6
5 4
5 1
5
1 5
1
5 1
5
1
5
IO2
6 2
6
2 6
2
6 2
6
2
6
IO3
7 3
7
3 7
3
7 3
7
3
7
Phase
3
2 1
0 31
Instruction
1
0
Address
Dummy
D1
D2
D3
D4
D5
Figure 19. Dual I/O Command
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
Phase
0
30
2
0
6
4
2
0
6
4
2
0
6
4
2
0
31
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Instruction
Address
Mode
Dum
Data 1
Data 2
Figure 20. Quad I/O Command
CS#
SCLK
IO0
0 28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
7
6
5
4
3
Instruction
2
1
Address Mode
Dummy
D1
D2
D3
D4
Note
8. The gray bits are optional, the host does not have to drive bits during that cycle.
Document Number: 002-00124 Rev. *H
Page 16 of 160
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Figure 21. Quad I/O Read Command in QPI Mode
CS#
SCLK
IO0
4
0
28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Note
9. The gray bits are optional, the host does not have to drive bits during that cycle.
Figure 22. DDR Quad I/O Read Command
CS#
SCK
IO0
7
6
5
A-3
8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
A-2
9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
A-1
2 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
A
3 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1
D2
Figure 23. DDR Quad I/O Read Command QPI Mode
CS#
SCLK
IO0
4
0
A-3
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
5
1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
6
2
A-1
2
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
7
3
A
3
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
DLP
D1
D2
Additional sequence diagrams, specific to each command, are provided in Section 8. Commands on page 58.
Document Number: 002-00124 Rev. *H
Page 17 of 160
S25FL256L/S25FL128L
5.3
Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3. Interface States Summary
Interface State
VCC
SCK
CS#
RESET#
IO3 /
RESET#
WP# /
IO2
SO /
IO1
SI / IO0
Power-Off
50 MHz), an LC that provides 1 or more dummy cycles should be
selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict.
When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to allow 1
cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP.
Each read command ends when CS# is returned High at any point during data return. CS# must not be returned High during the
mode or dummy cycles before data returns as this may cause mode bits to be captured incorrectly; making it indeterminate as to
whether the device remains in continuous read mode.
Document Number: 002-00124 Rev. *H
Page 82 of 160
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8.4.1 Read (Read 03h or 4READ 13h)
The instruction
03h (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
03h (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
13h is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, are shifted out on SO/IO1.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 65. Read Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
Phase
Instruction
Address
6
5
4
3
2
1
0
7
6
5
Data 1
4
3
2 1
0
Data N
Note
31. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 13h.
8.4.2 Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)
The instruction
0Bh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
0Bh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR3V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on SO/IO1 is “don’t care” and may be high impedance. Then the memory contents, at the address given, are shifted out on
SO/IO1.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 66. Fast Read (FAST_READ) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
6
5
4
3
2
1
0
IO2-IO3
Phase
Instruction
Address
Dummy Cycles
Data 1
Note
32. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 0Ch.
Document Number: 002-00124 Rev. *H
Page 83 of 160
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8.4.3 Dual Output Read (DOR 3Bh or 4DOR 3Ch)
The instruction
3Bh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
3Bh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
3Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR3V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on IO0 (SI) and IO1 (S0) is “don’t care” and may be high impedance.
Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO). Two bits are shifted
out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
For Dual Output Read commands, there are dummy cycles required after the last address bit is shifted into IO0 (SI) before data
begins shifting out of IO0 and IO1.
Figure 67. Dual Output Read Command Sequence
CS#
SCK
IO0
7
6
5
4
3
2
1
0
A
1
0
IO1
Phase
Instruction
Address
Dummy Cycles
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
Data 1
Data 2
Note
33. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 3Ch.
8.4.4 Quad Output Read (QOR 6Bh or 4QOR 6Ch)
The instruction
6Bh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
6Bh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
6Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR3V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on IO0 - IO3 is “don’t care” and may be high impedance.
Then the memory contents, at the address given, is shifted out four bits at a time through IO0 - IO3. Each nibble (4 bits) is shifted out
at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
For Quad Output Read commands, there are dummy cycles required after the last address bit is shifted into IO0 before data begins
shifting out of IO0 - IO3.
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Figure 68. Quad Output Read Command Sequence
CS#
SCK
IO0
4 0
4 0
4 0
4 0
4 0 4
IO1
5 1
5 1
5 1
5 1
5 1
5
IO2
6 2
6 2
6 2
6 2
6 2
6
IO3
7 3
7 3
7 3
7 3
7 3
7
D1
D2
D3
D4
D5
Phase
7
6 5
4 3
2 1
Instruction
0 A
1 0
Address
Dummy
Note
34. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 6Ch.
8.4.5 Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
BBh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
BBh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This command takes input of the
address and returns read data two bits per SCK rising edge. In some applications, the reduced address input and data output time
might allow for code execution in place (XIP) i.e. directly from the memory device.
The Dual I/O Read command has continuous read mode bits that follow the address so, a series of Dual I/O Read commands may
eliminate the 8 bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the following
command will also be a Dual I/O Read command. The first Dual I/O Read command in a series starts with the 8 bit instruction,
followed by address, followed by four cycles of mode bits, followed by an optional latency period. If the mode bit pattern is Axh the
next command is assumed to be an additional Dual I/O Read command that does not provide instruction bits. That command starts
with address, followed by mode bits, followed by optional latency.
Variable latency may be added after the mode bits are shifted into SI and SO before data begins shifting out of IO0 and IO1. This
latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the
dummy cycles, the data value on SI and SO are “don’t care” and may be high impedance. The number of dummy cycles is
determined by the frequency of SCK. The latency is configured in CR3V[3:0].
The continuous read feature removes the need for the instruction bits in a sequence of read accesses and greatly improves code
execution (XIP) performance. The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read command
through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”)
and may be high impedance. If the Mode bits equal Axh, then the device remains in Dual I/O Continuous Read Mode and the next
address can be entered (after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in Figure 70;
thus, eliminating eight cycles of the command sequence. The following sequences will release the device from Dual I/O Continuous
Read mode; after which, the device can accept standard SPI commands:
1. During the Dual I/O continuous read command sequence, if the Mode bits are any value other than Axh, then the next time CS#
is raised high the device will be released from Dual I/O conti nous read mode.
2. Send the Mode Reset command.
Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial address after the last
address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock
speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is
allowed and may be helpful in preventing I/O signal contention, for the host system to turn off the I/O signal outputs (make them high
impedance) during the last two “don’t care” mode cycles or during any dummy cycles.
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Following the latency period the memory content, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1
(SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Figure 69. Dual I/O Read Command Sequence
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
0 A-1
A
Phase
Instruction
2
0
6
4
2
0
6
4
2
0
6
4
2
0
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Address
Mode
Dum
Data 1
Data 2
Notes
35. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command BCh.
36. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these cycles to increase bus turn
around time between Mode bits from host and returning data from the memory.
Figure 70. Dual I/O Continuous Read Command Sequence
CS#
SCK
IO0
6
4
2
0
A-1
2
0
6
4
2
0
6
4
2
0
6
4
2
0
IO1
7
5
3
1
A
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Phase
Data N
Address
Mode
Dum
Data 1
Data 2
Note
37. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command BCh.
8.4.6 Quad I/O Read (QIOR EBh or 4QIOR ECh)
The instruction,
EBh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
EBh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals IO0-IO3. It allows input of the address bits four bits per
serial SCK clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from FL-L
family devices. The QUAD bit of the Configuration Register 1 must be set (CR1V[1]=1) or the QPI bit of Configuration Register 2
must be set (CR2V[1]=1 to enable the Quad capability of FL-L family devices.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data begins shifting out of
IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to access data at the initial
address. During latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. The number of dummy
cycles is determined by the frequency of SCK. The latency is configured in CR3V[3:0].
Following the latency period, the memory contents at the address given, is shifted out four bits at a time through IO0-IO3. Each
nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
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Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through the setting of the
Mode bits (after the address sequence, as shown in Figure 71 on page 87. This added feature removes the need for the instruction
sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next
Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits
are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode and the next
address can be entered (after CS# is raised high and then asserted low) without requiring the EBh or ECh instruction, as shown in
Figure 73 on page 88; thus, eliminating eight cycles for the command sequence. The following sequences will release the device
from Quad I/O High Performance Read mode; after which, the device can accept standard SPI commands:
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is
raised high the device will be released from Quad I/O High Performance Read mode.
2. Send the Mode Reset command.
Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal circuitry latency
time to access the initial address after the last address cycle that is clocked into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data out clock. At higher
clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished.
It is allowed and may be helpful in preventing IO0-IO3 signal contention, for the host system to turn off the IO0-IO3 signal outputs
(make them high impedance) during the last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
In QPI mode (CR2V[3]=1) the Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the command protocol is
identical to the Quad I/O commands.
Figure 71. Quad I/O Read Initial Access Command Sequence
CS#
SCLK
IO0
7
6
0 A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
A
7
3
7
3
7
3
7
3
7
3
7
3
Phase
5
4
3
2
1
Instruction
Address Mode
Dummy
D1
D2
D3
D4
Note
38. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command ECh.
Figure 72. Quad I/O Read Initial Access Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Note
39. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command ECh.
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Figure 73. Continuous Quad I/O Read Command Sequence
CS#
SCK
IO0
4
0
4
0
A-3
4
0
4
0
4
0
4
0
6
4
2
0
IO1
5
1
5
1
A-2
5
1
5
1
5
1
5
1
7
5
3
1
IO2
6
2
6
2
A-1
6
2
6
2
6
2
6
1
7
5
3
1
IO3
7
3
7
3
A
7
3
7
3
3
7
1
7
5
3
Phase
DN-1
DN
Address
Mode
7
Dummy
D1
D2
D3
1
D4
Notes
40. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command ECh.
41. The same sequence is used in QPI mode.
8.4.7 DDR Quad I/O Read (EDh, EEh)
The DDR Quad I/O Read command improves throughput with four I/O signals IO0-IO3. It is similar to the Quad I/O Read command
but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might
allow for code execution (XIP) directly from FL-L Family devices. The QUAD bit of the Configuration Register 1 must be set
(CR1V[1]=1) or the QPI bit of Configuration Register 2 must be set (CR2V[1]=1 to enable the Quad capability of FL-L family devices.
The instruction
EDh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
EDh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
EEh is followed by a 4-byte address (A31-A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four
bits at a time on each clock edge through IO0-IO3.
The maximum operating clock frequency for DDR Quad I/O Read command is 66 MHz.
For DDR Quad I/O Read, there is a latency required after the last address and mode bits are shifted into the IO0-IO3 signals before
data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access
the initial address. During these latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. When the
Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must
be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR3V[3:0].
Mode bits allow a series of Quad I/O DDR commands to eliminate the 8 bit instruction after the first command sends a
complementary mode bit pattern. This feature removes the need for the eight bit SDR instruction sequence and dramatically reduces
initial access times (improves XIP performance). The Mode bits control the length of the next DDR Quad I/O Read operation through
the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are
complementary (i.e. 5h and Ah) the device transitions to Continuous DDR Quad I/O Read Mode and the next address can be
entered (after CS# is raised high and then asserted low) without requiring the EDh or EEh instruction, thus eliminating eight cycles
from the command sequence. The following sequences will release the device from Continuous DDR Quad I/O Read mode; after
which, the device can accept standard SPI commands:
1. During the DDR Quad I/O Read Command Sequence, if the Mode bits are not complementary the next time CS# is raised high
and then asserted low the device will be released from DDR Quad I/O Read mode.
2. Send the Mode Reset command.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. Note that the memory
devices may drive the IOs with a preamble prior to the first data value. The preamble is a Data Learning Pattern (DLP) that is used
by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus for the four clock cycles
immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts
outputting the preamble.
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The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to
when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the
preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read
operation. The optimized capture point will be determined during the preamble period of every read operation. This optimization
strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h
(or 00110100) will be driven on each of the active outputs (i.e. all four IOs). This pattern was chosen to cover both “DC” and “AC”
data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks) followed by a
high going transition (001) and the complementary low going transition (110). The two AC transition scenarios include data low for a
short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). The
DC transitions will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully settled
to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC
transitions will bound the ending of the data valid period. These transitions will allow the host controller to identify the beginning and
ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be chosen. In QPI mode
(CR2V[3]=1) the DDR Quad I/O instructions are sent 4 bits at SCK rising edge. The remainder of the command protocol is identical
to the DDR Quad I/O commands.
Figure 74. DDR Quad I/O Read Initial Access
CS#
SCK
IO0
7
6
5
4
A-3
8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
A-2
9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
A-1
10 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
A
11 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
Phase
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1
D2
Notes
42. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command EEh
43. Example DLP of 34h (or 00110100)
Figure 75. DDR Quad I/O Read Initial Access QPI Mode
CS#
SCLK
IO0
4
0
A-3
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
5
1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
6
2
A-1
10
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
7
3
A
11
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
DLP
D1
D2
Notes
44. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command EEh.
45. Example DLP of 34h (or 00110100).
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Figure 76. Continuous DDR Quad I/O Read Subsequent Access
CS#
SCK
IO0
A-3
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
A-1
10
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
A
11
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Address
Mode
Dummy
DLP
D1
D2
Notes
46. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command EEh.
47. The same sequence is used in QPI mode.
48. Example DLP of 34h (or 00110100).
8.5
Program Flash Array Commands
8.5.1 Program Granularity
8.5.1.1
Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move
data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single
programming command. Page Programming allows up to a page size 256bytes to be programmed in one operation. The page is
aligned on the page size address boundary. It is possible to program from one bit up to a page size in each Page programming
operation. For the very best performance, programming should be done in full pages of 256bytes aligned on 256byte boundaries
with each Page being programmed only once.
8.5.1.2
Single Byte Programming
Single Byte Programming allows full backward compatibility to the legacy standard SPI Page Programming (PP) command by
allowing a single byte to be programmed anywhere in the memory array.
8.5.2 Page Program (PP 02h or 4PP 12H)
The Page Program (PP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). Before the Page
Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the
device. After the Write Enable (WREN) command has been decoded successfully, the device sets the Write Enable Latch (WEL) in
the Status Register to enable any write operations.
The instruction
02h (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
02h (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
12h is followed by a 4-byte address (A31-A0)
and at least one data byte on SI/IO0. Up to a page can be provided on SI/IO0 after the 3-byte address with instruction 02h or 4-byte
address with instruction 12h has been provided. As with the write and erase commands, the CS# pin must be driven high after the
eighth bit of the last byte has been latched. If this is not done the Page Program command will not be executed. After CS# is driven
high, the self-timed Page Program command will commence for a time duration of tPP.
Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall programming time
versus loading less than a page into the program buffer.
The programming process is managed by the Flash memory device internal control logic. After a programming command is issued,
the programming operation status can be checked using the Read Status Register 1 command. The WIP bit (SR1V[0]) will indicate
when the programming operation is completed. The P_ERR bit (SR2V[5]) will indicate if an error occurs in the programming
operation that prevents successful completion of programming. This includes attempted programming of a protected area.
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Figure 77. Page Program (PP 02h or 4PP 12h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Address
Input Data 1
Input Data 2
Note
49. A = MSb of address = A23 for PP 02h with CR2V[0]=0, or A31 for PP 02h with CR2V[0] = 1, or for 4PP 12h.
This command is also supported in QPI mode. In QPI mode, the instruction, address and data is shifted in on IO0-IO3.
Figure 78. Page Program (PP 02h or 4PP 12h) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Input D1
Input D2
Input D3
Input D4
Note
50. A = MSb of address = A23 for PP 02h with CR2V[0]=0, or A31 for PP 02h with CR2V[0] = 1, or for 4PP 12h.
8.5.3 Quad Page Program (QPP 32h or 4QPP 34h)
The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). The
Quad-input Page Program (QPP) command allows up to a page of data to be loaded into the Page Buffer using four signals: IO0IO3. QPP can improve performance for PROM Programmer and applications that have slower clock speeds (< 12 MHz) by loading 4
bits of data per clock cycle. Systems with faster clock speeds do not realize as much benefit for the QPP command since the
inherent page program time becomes greater than the time it takes to clock-in the data. The maximum frequency for the QPP
command is 133MHz.
To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD=1). A Write Enable command
must be executed before the device will accept the QPP command (Status Register 1, WEL=1).
The instruction
32h (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
32h (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
34h is followed by a 4-byte address (A31-A0)
and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory locations.
All other functions of QPP are identical to Page Program. The QPP command sequence is shown in the figure below.
Document Number: 002-00124 Rev. *H
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Figure 79. Quad Page Program Command Sequence
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
IO1
7
6
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
Phase
5
4
3
2
1
0
A
Instruction
1
0
Address
Data 1
Data 2
Data 3
Data 4
Data 5
...
Note
51. A = MSb of address = A23 for QPP 32h with CR2V[0]=0, or A31 for QPP 32h with CR2V[0]=1, or for 4QPP 34h.
8.6
Erase Flash Array Commands
8.6.1 Sector Erase (SE 20h or 4SE 21h)
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the Sector Erase (SE)
command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
20h [CR2V[0]=0] is followed by a 3-byte address (A23-A0), or
20h [CR2V[0]=1] is followed by a 4-byte address (A31-A0), or
21h is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of the address has been latched in on SI/IO0.
This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the chosen sector of the
flash memory array. If CS# is not driven high after the last bit of address, the sector erase operation will not be executed.
As soon as CS# is driven high, the internal erase cycle will be initiated. With the internal erase cycle in progress, the user can read
the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a “1”.
when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A SE or 4SE command applied to a sector that has been write protected through the Legacy Block Protection, Individual Block Lock
or Pointer Region Protection will not be executed and will set the E_ERR status.
Figure 80. Sector Erase (SE 20h or 4SE 21h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
52. A = MSb of address = A23 for SE 20h with CR2V[0]=0, or A31 for SE 20h with CR2V[0]=1 or for 4SE 21h.
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0-IO3.
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Figure 81. Sector Erase (SE 20h or 4SE 21h) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
53. A = MSb of address = A23 for SE 20h with CR2V[0]=0, or A31 for SE 20h with CR2V[0]=1 or for 4SE 21h.
8.6.2 Half Block Erase (HBE 52h or 4HBE 53h)
The Half Block Erase (HBE) command sets all bits in the addressed half block to 1 (all bytes are FFh). Before the Half Block Erase
(HBE) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device,
which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
52h [CR2V[0]=0] is followed by a 3-byte address (A23-A0), or
52h [CR2V[0]=1] is followed by a 4-byte address (A31-A0), or
53h is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been latched in on SI/IO0. This
will initiate the erase cycle, which involves the pre-programming and erase of each sector of the chose block. If CS# is not driven
high after the last bit of address, the half block erase operation will not be executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal erase cycle in progress,
the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate
a “1” when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A Half Block Erase (HBE) command applied to a Block that has been Write Protected through the Legacy Block Protection,
Individual Block Lock or Pointer Region Protection will not be executed and will set the E_ERR status.
If a half block erase command is applied and if any region, sector or block in the half block erase area is protected the erase will not
be executed on the 32 KB range and will set the E_ERR status.
Figure 82. Half Block Erase (HBE 52h or 4HBE 53h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Notes
54. A = MSb of address = A23 for HBE 52h with CR2V[0]=0, or A31 for HBE 52h with CR2V[0]=1 or 4HBE 53h.
55. When A[15]=0 the sectors 0-7 of Block are erased and A[15]=1 then sectors 8-15 of Block are erased.
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0-IO3.
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S25FL256L/S25FL128L
Figure 83. Half Block Erase (HBE 52h or 4HBE 53h) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Notes
56. A = MSb of address = A23 for HBE 52h with CR2V[0]=0, or A31 for HBE 52h with CR2V[0]=1 or 4HBE 53h.
57. When A[15]=0 the sectors 0-7 of Block are erased and A[15]=1 then sectors 8-15 of Block are erased.
8.6.3 Block Erase (BE D8h or 4BE DCh)
The Block Erase (BE) command sets all bits in the addressed block to 1 (all bytes are FFh). Before the Block Erase (BE) command
can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
D8h [CR2V[0]=0] is followed by a 3-byte address (A23-A0), or
D8h [CR2V[0]=1] is followed by a 4-byte address (A31-A0), or
DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been latched in on SI/IO0. This
will initiate the erase cycle, which involves the pre-programming and erase of each sector of the chosen block. If CS# is not driven
high after the last bit of address, the block erase operation will not be executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal erase cycle in progress,
the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate
a “1” when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A Block Erase (BE) command applied to a Block that has been Write Protected through the Legacy Block Protection, Individual
Block Lock or Pointer Region Protection will not be executed and will set the E_ERR status.
If a block erase command is applied and if any region or sector area is protected the erase will not be executed on the 64 KB range
and will set the E_ERR status.
Figure 84. Block Erase (BE D8h or 4BE DCh) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
58. A = MSb of address = A23 for BE D8h with CR2V[0]=0, or A31 for BE D8h with CR2V[0]=1 or 4BE DCh.
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0-IO3.
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S25FL256L/S25FL128L
Figure 85. Block Erase (BE D8h or 4BE DCh) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
59. A = MSb of address = A23 for BE D8h with CR2V[0]=0, or A31 for BE D8h with CR2V[0]=1 or 4BE DCh.
8.6.4 Chip Erase (CE 60h or C7h)
The Chip Erase (CE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the CE command
can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0. This will initiate
the erase cycle, which involves the pre-programming and erase of the entire flash memory array. If CS# is not driven high after the
last bit of instruction, the CE operation will not be executed.
As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in progress, the user can
read the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a
“1” when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A CE command will not be executed when the Legacy Block Protection, Individual Block Lock or Pointer Region Protection set to
protect any sector or block and this will set the E_ERR status bit.
Figure 86. Chip Erase Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 87. Chip Erase Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *H
Instruction
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8.6.5 Program or Erase Suspend (PES 75h)
The PES command allows the system to interrupt a programming or erase operation and then read from any other non-erasesuspended sector or non-program-suspended-page. Program or Erase Suspend is valid only during a programming or sector erase,
half block erase or block erase operation. A Chip Erase operation cannot be suspended.
The Write in Progress (WIP) bit in Status Register 1 (SR1V[0]) must be checked to know when the programming or erase operation
has stopped. The Program Suspend Status bit in the Status Register 2 (SR2[0]) can be used to determine if a programming
operation has been suspended or was completed at the time WIP changes to 0. The Erase Suspend Status bit in the Status Register
2 (SR2[1]) can be used to determine if an erase operation has been suspended or was completed at the time WIP changes to 0. The
time required for the suspend operation to complete is tSL, see Table 65 on page 146.
An Erase can be suspended to allow a program operation or a read operation. During an erase suspend, the IBL array may be read
to examine sector protection and written to remove or restore protection on a sector to be programmed. The protection bits will not
be rechecked when the operation is resumed so any changes made will not impact current in progress operation.
A program operation may be suspended to allow a read operation.
A new suspend operation is not allowed with-in an already suspended erase or program operation. The suspend command is
ignored in this situation.
Table 44. Commands Allowed During Program or Erase Suspend
Instruction
Name
Instruction
Code
(Hex)
Allowed
During
Erase
Suspend
Allowed
During
Program
Suspend
READ
03
X
X
All array reads allowed in suspend
RDSR1
05
X
X
Needed to read WIP to determine end of suspend process
RDAR
65
X
X
Alternate way to read WIP to determine end of suspend process
RDSR2
07
X
X
Needed to read suspend status to determine whether the operation is
suspended or complete.
RDCR1
35
X
X
Needed to read Configuration Register 1
RDCR2
15
X
X
Needed to read Configuration Register 2
RDCR3
33
X
X
Needed to read Configuration Register 3
RUID
4B
X
X
Needed to read Unique Id
RDID
9F
X
X
Needed to read Device Id
Comment
RDQID
AF
X
X
Needed to read Quad Device Id
RSFDP
5A
X
X
Needed to read SFDP
SBL
77
X
X
Needed to set Burst Length
WREN
06
X
X
Required for program command within erase suspend
WRDI
04
X
X
Required for program command within erase suspend
PP
4PP
QPP
02
12
32
X
Required for array program during erase suspend. Only allowed if there is no
other program suspended program operation (SR2V[0]=0). A program
command will be ignored while there is a suspended program. If a program
command is sent for a location within an erase suspended sector the program
operation will fail with the P_ERR bit set.
X
Required for array program during erase suspend. Only allowed if there is no
other program suspended program operation (SR2V[0]=0). A program
command will be ignored while there is a suspended program. If a program
command is sent for a location within an erase suspended sector the program
operation will fail with the P_ERR bit set.
X
Required for array program during erase suspend. Only allowed if there is no
other program suspended program operation (SR2V[0]=0). A program
command will be ignored while there is a suspended program. If a program
command is sent for a location within an erase suspended sector the program
operation will fail with the P_ERR bit set.
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Table 44. Commands Allowed During Program or Erase Suspend (Continued)
Instruction
Name
Instruction
Code
(Hex)
Allowed
During
Erase
Suspend
Allowed
During
Program
Suspend
Comment
Required for array program during erase suspend. Only allowed if there is no
other program suspended program operation (SR2V[0]=0). A program
command will be ignored while there is a suspended program. If a program
command is sent for a location within an erase suspended sector the program
operation will fail with the P_ERR bit set.
4QPP
34
X
4READ
13
X
X
All array reads allowed in suspend
CLSR
30
X
X
Clear status may be used if a program operation fails during erase suspend.
EPR
7A
X
X
Required to resume from erase or program suspend.
RSTEN
66
X
X
Reset allowed anytime
RST
99
X
X
Reset allowed anytime
FAST_READ
0B
X
X
All array reads allowed in suspend
4FAST_READ
0C
X
X
All array reads allowed in suspend
DOR
3B
X
X
All array reads allowed in suspend
4DOR
3C
X
X
All array reads allowed in suspend
DIOR
BB
X
X
All array reads allowed in suspend
4DIOR
BC
X
X
All array reads allowed in suspend
IBLRD
3D
X
X
It may be necessary to remove and restore Individual Block Lock during erase
suspend to allow programming during erase suspend.
4IBLRD
E0
X
X
It may be necessary to remove and restore Individual Block Lock during erase
suspend to allow programming during erase suspend.
IBL
36
X
X
It may be necessary to restore Individual Block Lock during erase suspend to
allow programming during erase suspend.
4IBL
E1
X
X
It may be necessary to restore Individual Block Lock during erase suspend to
allow programming during erase suspend.
IBUL
39
X
X
It may be necessary to remove Individual Block Lock during erase suspend to
allow programming during erase suspend.
4IBUL
E2
X
X
It may be necessary to remove Individual Block Lock during erase suspend to
allow programming during erase suspend.
QOR
6B
X
X
Read Quad Output (3 or 4 Byte Address)[60]
4QOR
6C
X
X
Read Quad Output (4 Byte Address)[60]
QIOR
EB
X
X
All array reads allowed in suspend[60]
4QIOR
EC
X
X
All array reads allowed in suspend[60]
DDRQIOR
ED
X
X
All array reads allowed in suspend[60]
DDR4QIOR
ED
X
X
All array reads allowed in suspend[60]
X
May need to reset a read operation during suspend
MBR
FF
X
SECRP
42
X
SECRR
48
X
All Security Regions program allowed in erase suspend
X
All Security Regions reads allowed in suspend
Note
60. For all Quad commands the Quad Enable CR1V[1] bit (SeeTable 13 on page 31) needs to be set to “1” before initial program or erase, since the WRR/WRAR commands
are not allowed inside of the suspend state.
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All command not included in Table 44 on page 96 are not allowed during Erase or Program Suspend. The WRR, WRAR, or SPRP
commands are not allowed during Erase or Program Suspend, it is therefore not possible to alter the Legacy Block Protection bits or
Pointer Region Protection during Erase Suspend.
Reading at any address within an erase-suspended sector or program-suspended page produces undetermined data.
After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The system can
determine the status of the program operation by reading the WIP bit in the Status Register, just as in the standard program
operation.
Figure 88. Program or Erase Suspend Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 89. Program or Erase Suspend Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Instruction
Figure 90. Program or Erase Suspend Command with Continuing Instruction Commands Sequence
tSL
CS#
SCK
SI_IO0
7 6 5 4 3 2 1 0
SO
Phase
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Suspend Instruction
Phase
Document Number: 002-00124 Rev. *H
Read Status Instruction
Status
Instr. During Suspend
Repeat Status Read Until Suspended
Page 98 of 160
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8.6.6 Erase or Program Resume (EPR 7Ah)
After program or read operations are completed during a program or erase suspend the Erase or Program Resume command is
sent to continue the suspended operation.
After an Erase or Program Resume command is issued, the WIP bit in the Status Register 1 will be set to a 1 and the suspended
operation will resume if one is suspended. If there is no suspended program or erase operation the resume command is ignored.
Program or erase operations may be interrupted as often as necessary e.g. a program suspend command could immediately follow
a program resume command but, but in order for a program or erase operation to progress to completion there must be some
periods of time between resume and the next suspend command greater than or equal to tRNS. See Table 65 on page 146.
The Program Suspend Status bit in the Status Register 2 (SR2[0]) can be used to determine if a programming operation has been
suspended or was completed at the time WIP changes to 0. The Erase Suspend Status bit in the Status Register 2 (SR2[1]) can be
used to determine if an erase operation has been suspended or was completed at the time WIP changes to 0.
See Section 6.6.2 Status Register 2 Volatile (SR2V) on page 29.
An Erase or Program Resume command must be written to resume a suspended operation.
Figure 91. Erase or Program Resume command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 92. Erase or Program Resume command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *H
Instruction
Page 99 of 160
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8.7
Security Regions Array Commands
The Security Regions commands select which region to use by address A15 to A8 as shown below.
Security Region 0: A23-16 = 00h; A15-8 = 00h; A7-0 = byte address
Security Region 1: A23-16 = 00h; A15-8 = 01h; A7-0 = byte address
Security Region 2: A23-16 = 00h; A15-8 = 02h; A7-0 = byte address
Security Region 3: A23-16 = 00h; A15-8 = 03h; A7-0 = byte address
8.7.1 Security Region Erase (SECRE 44h)
The Security Region Erase command erases data in the Security Region, which is in a different address space from the main array
data. The Security Region is 1024 bytes so, the address bits for S25FL128L (A23 to A10) and S25FL256L (A24 to A10) must be
zero for this command. Each region can be individually erased. Refer to Section 6.5 Security Regions Address Space on page 24
for details on the Security Region.
Before the Security Region Erase command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit
in SR1V may be checked to determine when the operation is completed. The E_ERR bit in SR2V may be checked to determine if
any error occurred during the operation.
The Security Region Lock Bits (CR1NV[2-5]) in the Configuration Register 1 can be used to protect the Security Regions for erase.
Once a lock bit is set to 1, the corresponding Security Region will be permanently locked, Attempting to erase a region that is locked
will fail with the E_ERR bit in SR2V[6] set to “1”.
When the Protection Register NVLOCK Bit = “0”, Security Regions 2 and 3 are protected from program or erase. Attempting to erase
in a region that locked will fail with the E_ERR bits in SR2V[6] set to “1”. See Section 7.7.2.1 NVLOCK Bit (PR[0]) on page 56.
The Password Protection Mode Lock Bit (IRP[2]) allows regions 2 and 3 to be protected from erase operations until the correct
password is provided to enable erasing of these Security Regions. Attempting to erase in a region that is password locked will fail
with the E_ERR bit in SR2V[6] set to “1”. Section 7.7.4 Security Region Read Password Protection on page 57.
The protocol of the Security Region Erase command is the same as the Sector Erase command. See Section 8.6.1 Sector Erase
(SE 20h or 4SE 21h) on page 92 for the command sequence. QPI Mode is supported.
8.7.2 Security Region Program (SECRP 42h)
The Security Region Program command programs data in the Security Region, which is in a different address space from the main
array data. The Security Region is 1024 bytes so, the address bits for S25FL128L (A23 to A10) and S25FL256L (A24 to A10) must
be zero for this command. Refer to Section 6.5 Security Regions Address Space on page 24 for details on the Security Region.
Before the Security Region Program command can be accepted by the device, a Write Enable (WREN) command must be issued
and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP
bit in SR1V may be checked to determine when the operation is completed. The P_ERR bit in SR2V may be checked to determine if
any error occurred during the operation.
To program the Security Region array in bit granularity, the rest of the bits within a data byte can be set to “1”.
Each region in the Security Region memory space can be programmed one or more times, provided that the region is not locked.
However, for the best data integrity, it is recommended that one or more 16 byte length and aligned groups of bytes be programed
together and programmed only once between erase operations within each region.
The Security Region Lock Bits (CR1NV[2-5]) in the Configuration Register 1 can be used to protect the Security Regions for
Programming. Once a lock bit is set to 1, the corresponding Security Region will be permanently locked. Attempting to program
zeros or ones in a region that is locked (protected) will fail with the P_ERR bit in SR2V[5] set to “1”. Programming ones in a unprotected area does not cause an error and does not set P_ERR. (see Section 6.6.3 Configuration Register 1 on page 30 for detail
descriptions).
When the Protection Register NVLOCK Bit = “0”, Security Regions 2 and 3 are protected from program or erase. Attempting to
program in a region that locked will fail with the P_ERR bit in SR2V[5] set to “1”. See Section 7.7.2.1 NVLOCK Bit (PR[0])
on page 56.
Document Number: 002-00124 Rev. *H
Page 100 of 160
S25FL256L/S25FL128L
The Password Protection Mode Lock Bit (IRP[2]) allows regions 2 and 3 to be protected from programming operations until the
correct password is provided to enable programming of these Security Regions 2 and 3. Attempting to program in a region that is
password locked will fail with the P_ERR bit in SR2V[5] set to “1”. See Section 7.7.3 Password Protection Mode on page 56.
The protocol of the Security Region Program command is the same as the Page Program command. See Section 8.5.1.1 Page
Programming on page 90 for the command sequence. QPI Mode is supported.
8.7.3 Security Regions Read (SECRR 48h)
The Security Region Read (SECRR) command provides a way to read data from the Security Regions. The Security Region is 1024
bytes so, the address bits for S25FL128L (A23 to A10) and S25FL256L (A24 to A10) must be zero for this command. Refer to
Section 6.5 Security Regions Address Space on page 24 for details on the Security Regions.
The instruction is followed by a 3 or 4 Byte address (depending on the address length configuration CR2V[0], followed by a number
of latency (dummy) cycles set by CR3V[3:0]. Then the selected register data are returned. The protocol of the Security Region Read
command will not wrap to the starting address after the Security Region address is at its maximum; instead, the data beyond the
maximum address will be undefined. The Security Region Read command read latency is set by the latency value in CR3V[3:0].
The Security Region Read Password Mode Enable Bit (IRP[6]) allows regions 3 to be protected from read operations until the
correct password is provided to enable reading of this Security Region. Attempting to read in region 3 that is password locked will
return invalid and undefined data. See Section 7.7.4 Security Region Read Password Protection on page 57.
Figure 93. Security Regions Read Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
Phase
Instruction
Address
6
5
4
Dummy Cycles
3
2
1
0
Data 1
Note
61. A = MSb of address = 23 for Address length CR2V[0] = 0, or 31 for CR2V[0]=1.
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in and returning data out on IO0IO3.
Figure 94. Security Regions Read Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
Note
62. A = MSb of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1.
Document Number: 002-00124 Rev. *H
Page 101 of 160
S25FL256L/S25FL128L
8.8
Individual Block Lock Commands
In order to use Individual Block Lock, the IBL protection scheme must be selected by the WPS bit in Configuration Register 2
CR2V[2]=1. If if IBL protection scheme is not selected CR2V[2]=0 the IBL commands are ignored.
Individual Block Lock Bits (IBL) are volatile, with one for each sector / block, and can be individually modified. By issuing the IBL or
GBL commands, a IBL bit is set to “0” protecting each related sector / block. By issuing the IBUL or GUL commands, a IBL bit is
cleared to “1” unprotecting each related sector or block. By issuing the IBLRD command the state of each IBL bit protection can be
read.
8.8.1 IBL Read (IBLRD 3Dh or 4IBLRD E0h)
The IBLRD/4IBLRD command allows reading the state of each IBL bit protection.
The instruction is latched into SI by the rising edge of the SCK signal. The instruction is followed by the 24- or 32-Bit address,
depending on the address length configuration CR2V[0], selecting location zero within the desired sector.
Then the 8-bit IBL access register contents are shifted out on the serial output SO/IO1. Each bit is shifted out at the SCK frequency
by the falling edge of the SCK signal. It is possible to read the same IBL access register continuously by providing multiples of eight
clock cycles. The address of the IBL register does not increment so this is not a means to read the entire IBL array. Each location
must be read with a separate IBL Read command.
Figure 95. IBLRD Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
Phase
Instruction
Address
6
Dummy Cycles
5
4
3
2
1 0
Output IBL
Notes
63. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 3Dh.
64. A = MSb of address = 31 with command E0h.
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in and returning data out on IO0IO3.
Figure 96. IBLRD Command Sequence QPI
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
IBL
Repeat IBL
Notes
65. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 3Dh.
66. A = MSb of address = 31 with command E0h.
Document Number: 002-00124 Rev. *H
Page 102 of 160
S25FL256L/S25FL128L
8.8.2 IBL Lock (IBL 36h or 4IBL E1h)
The IBL/4IBL commands sets the selected IBL bit to “0” protecting each related sector / block.
The IBL command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24- or 32-Bit address,
depending on the address length configuration CR2V[0]. The IBL command affects the WIP bits of the Status and Configuration
Registers in the same manner as any other programming operation.
CS# must be driven to the logic high state after the 24- or 32-Bit address (depending on the address length configuration CR2V[0])
has been latched in. As soon as CS# is driven to the logic high state, the self-timed IBL operation is initiated. While the IBL operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed IBL operation, and is a “0” when it is completed.
Figure 97. IBL Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Notes
67. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 36h.
68. A = MSb of address = 31 with command E1h
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0-IO3.
Figure 98. IBL Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Notes
69. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 36h.
70. A = MSb of address = 31 with command E1h.
Document Number: 002-00124 Rev. *H
Page 103 of 160
S25FL256L/S25FL128L
8.8.3 IBL Unlock (IBUL 39h or 4IBUL E2h)
The IBUL/4IBULcommands clears the selected IBL bit to “1” unprotecting each related sector / block.
The IBUL command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24- or 32-Bit
address, depending on the address length configuration CR2V[0]. The IBUL command affects the WIP bits of the Status and
Configuration Registers in the same manner as any other programming operation.
CS# must be driven to the logic high state after the 24- or 32-Bit address (depending on the address length configuration CR2V[0])
has been latched in. As soon as CS# is driven to the logic high state, the self-timed IBL operation is initiated. While the IBUL
operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In
Progress (WIP) bit is a “1” during the self-timed IBUL operation, and is a “0” when it is completed.
Figure 99. IBUL Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Notes
71. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 39h.
72. A = MSb of address = 31 with command E2h.
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0-IO3.
Figure 100. IBUL Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Notes
73. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 39h.
74. A = MSb of address = 31 with command E2h.
Document Number: 002-00124 Rev. *H
Page 104 of 160
S25FL256L/S25FL128L
8.8.4 Global IBL Lock (GBL 7Eh)
The GBL commands sets all the IBL bits to “0” protecting all sectors / blocks.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
GBL. If CS# is not driven high after the last bit of instruction, the GBL operation will not be executed.
As soon as CS# is driven into the logic high state, the GBL will be initiated. With the GBL in progress, the user can read the value of
the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a “1” when the GBL
is in progress and a “0” when the GBL has been completed.
Figure 101. Global IBL Lock (GBL) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 102. Global IBL Lock (GBL) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *H
Instruction
Page 105 of 160
S25FL256L/S25FL128L
8.8.5 Global IBL Unlock (GBUL 98h)
The GBUL commands clears all the IBL bits to “1” unprotecting all sectors / blocks.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
GBUL If CS# is not driven high after the last bit of instruction, the GBUL operation will not be executed.
As soon as CS# is driven into the logic high state, the GBL will be initiated. With the GBL in progress, the user can read the value of
the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a “1” when the GBUL
is in progress and a “0” when the GBUL has been completed.
Figure 103. Global IBL Unlock (GBUL) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 104. Global IBL Unlock (GBUL) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *H
Instruction
Page 106 of 160
S25FL256L/S25FL128L
8.9
Pointer Region Command
8.9.1 Set Pointer Region Protection (SPRP FBh or 4SPRP E3h)
The SPRP or 4SPRP command is ignored during a suspend operation because the pointer value cannot be erased and reprogrammed during a suspend.
The SPRP or 4SPRP command is ignored if default Power Supply Lock-down protection NVLOCK PR[0] = 0 or Power Supply Lockdown protection enabled IRP[1] = 0 or Password Protection enabled IRP[2] = 0 and NVLOCK PR[0] = 0.
The S25FL256L device must have 4 Byte addressing enabled (CR2V[0] = 1) to set the Pointer Region Protection register PRPR
(see Section 6.6.10 Pointer Region Protection Register (PRPR) on page 41) this ensures that A24 and A25 are set correctly. The
S25FL128L device can have 4 Byte addressing enabled (CR2V[0] = 1) or 3 Byte addressing enabled (CR2V[0] = 0).
Before the SPRP or 4SPRP command can be accepted by the device, a Write Enable (WREN) command must be issued. After the
Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to
enable any write operations.
The SPRP or 4SPRP command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24- or
32-Bit address, depending on the address length configuration CR2V[0], see Section 7.6.3 Pointer Region Protection (PRP)
on page 52 for details on address values to select protection options.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the SPRP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed SPRP operation is initiated. While the SPRP operation is in
progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
“1” during the self-timed SPRP operation, and is a “0” when it is completed. When the SPRP operation is completed, the Write
Enable Latch (WEL) is set to a “0”. The SPRP or 4SPRP command will set the P_ERR or E_ERR bits if there is a failure in the Set
Pointer Region Protection operation.
For details on the address pointer defining a sector boundary between protected and unprotected regions in the memory, see
Section 7.6.3 Pointer Region Protection (PRP) on page 52.
Figure 105. SPRP Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Notes
75. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command FDh.
76. A = MSb of address = 31 with command E3h.
This command is also supported in QPI mode. In QPI mode, the instruction and address is shifted in on IO0-IO3.
Figure 106. SPRP Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Notes
77. A = MSb of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command FDh.
78. A = MSb of address = 31 with command E3h.
Document Number: 002-00124 Rev. *H
Page 107 of 160
S25FL256L/S25FL128L
8.10 Individual and Region Protection (IRP) Commands
8.10.1 IRP Register Read (IRPRD 2Bh)
The IRP Register Read instruction 2Bh is shifted into SI/IO0 by the rising edge of the SCK signal followed by one dummy cycle. This
latency period allows the device’s internal circuitry enough time to access data at the initial address. During latency cycles, the data
value on IO0-IO3 are “don’t care” and may be high impedance.
Then the 16-bit IRP register contents are shifted out on the serial output S0/IO1, LSB first. Each bit is shifted out at the SCK
frequency by the falling edge of the SCK signal. It is possible to read the IRP register continuously by providing multiples of 16 clock
cycles.
Figure 107. IRPRD Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
7
Instruction
DY
6
5
4
3
2
1
0
7
Output IRP Low Byte
6
5
4
3
2
1
0
Output IRP High Byte
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in and returning data out on IO0-IO3.
Figure 108. IRPRD Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
Document Number: 002-00124 Rev. *H
Instruct.
Dummy
IRP Low Byte
IRP High Byte
Page 108 of 160
S25FL256L/S25FL128L
8.10.2 IRP Program (IRPP 2Fh)
Before the IRP Program (IRPP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to
enable any write operations.
The IRPP command is entered by driving CS# to the logic low state, followed by the instruction and two data bytes on SI, LSB first.
The IRP Register is two data bytes in length.
The IRPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other
programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the IRPP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed IRPP operation is initiated. While the IRPP operation is in
progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
“1” during the self-timed IRPP operation, and is a “0” when it is completed. When the IRPP operation is completed, the Write Enable
Latch (WEL) is set to a “0”.
Figure 109. IRP Program (IRPP) Command
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Input IRP Low Byte
Input IRP High Byte
This command is also supported in QPI mode. In QPI mode, the instruction and data is shifted in on IO0-IO3.
Figure 110. IRP Program (IRPP) Command QPI
CS#
SCLK
IO0
4
0
4
0
C
8
IO1
5
1
5
1
D
9
IO2
6
2
6
2
E
A
IO3
7
3
7
3
F
B
Phase
Document Number: 002-00124 Rev. *H
Instruct.
IRP Low Byte
IRP High Byte
Page 109 of 160
S25FL256L/S25FL128L
8.10.3 Protection Register Read (PRRD A7h)
The Protection Register Read (PRRD) command allows the Protection Register contents to be read out of SO/IO1. The Read
instruction A7h is shifted into SI by the rising edge of the SCK signal followed by one dummy cycle. This latency period allows the
device’s internal circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3 are
“don’t care” and may be high impedance.
Then the 8-bit Protection Register contents are shifted out on the serial output SO/IO1. Each bit is shifted out at the SCK frequency
by the falling edge of the SCK signal. It is possible to read the Protection register continuously by providing multiples of eight clock
cycles.
The Protection Register contents may only be read when the device is in standby state with no other operation in progress.
Figure 111. Protection Register Read (PRRD) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
7
Instruction
DY
6
5
4
3
2
1
0
7
Register Read
6
5
4
3
2
1
0
Repeat Register Read
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in and returning data out on IO0-IO3.
Figure 112. Protection Register Read (PRRD) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
Document Number: 002-00124 Rev. *H
Instruct.
Dummy
Register Read
Register Read
Page 110 of 160
S25FL256L/S25FL128L
8.10.4 Protection Register Lock (PRL A6h)
The Protection Register Lock (PRL) command clears the NVLOCK bit (PR[0]) to zero and loads the IRP[6] value in to SECRRP
(PR[6]). See Section 6.6.8 Protection Register (PR) on page 40. Before the PRL command can be accepted by the device, a Write
Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status
Register to enable any write operations.
The PRL command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the PRL command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PRL operation is initiated. While the PRL operation is in
progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed PRL operation, and is a “0” when it is completed. When the PRL operation is completed, the Write
Enable Latch (WEL) is set to a “0”.
Figure 113. Protection Register Lock (PRL) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 114. Protection Register Lock (PRL) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *H
Instruction
Page 111 of 160
S25FL256L/S25FL128L
8.10.5 Password Read (PASSRD E7h)
The correct password value may be read only after it is programmed and before the Password Mode has been selected by
programming the Password Protection Mode bit to 0 in the IRP Register (IRP[2]). After the Password Protection Mode is selected
the password is no longer readable, the PASSRD command will output undefined data.
The PASSRD command is shifted into SI followed by one dummy cycle. This latency period allows the device’s internal circuitry
enough time to access data at the initial address. During latency cycles, the data value on are “don’t care” and may be high
impedance.
Then the 64-bit Password is shifted out on the serial output, LSB first, MSb of each byte first. Each bit is shifted out at the SCK
frequency by the falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of 64 clock
cycles.
Figure 115. Password Read (PASSRD) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
IO2-IO3
Phase
Instruction
DY
Data 1
Data 8
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in and returning data out on IO0-IO3.
Figure 116. Password Read (PASSRD) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
Instruct.
Document Number: 002-00124 Rev. *H
Dummy
Data 1
Data 8
Page 112 of 160
S25FL256L/S25FL128L
8.10.6 Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device. After the Write Enable (WREN) command has been decoded, the device sets the Write Enable
Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password Mode is selected by programming the Password Protection Mode bit
to 0 in the IRP Register (IRP[2]). After the Password Protection Mode is selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI/IO0, LSB first, MSb of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PASSP operation is initiated. While the PASSP operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed PASSP cycle, and is a “0” when it is completed. The PASSP command can report a program error in the
P_ERR bit of the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a “0”.
Figure 117. Password Program (PASSP) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Password Byte 1
Password Byte 8
This command is also supported in QPI mode. In QPI mode, the instruction and data is shifted in on IO0-IO3.
Figure 118. Password Program (PASSP) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
Instruct.
Document Number: 002-00124 Rev. *H
Password Byte 1
Password Byte 8
Page 113 of 160
S25FL256L/S25FL128L
8.10.7 Password Unlock (PASSU EAh)
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI, LSB first, MSb of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSU command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PASSU operation is initiated. While the PASSU operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed PASSU cycle, and is a “0” when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register, an error is reported by
setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is necessary to use the CLSR command to
clear the status register, the software reset command (RSTEN 66h followed by RST 99h) to reset the device, or drive the RESET#
and IO3 / RESET# input to initiate a hardware reset, in order to return the P_ERR and WIP bits to 0. This returns the device to
standby state, ready for new commands such as a retry of the PASSU command.
If the password does match, the NVLOCK bit is set to “1”.
Figure 119. Password Unlock (PASSU) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Password Byte 1
Password Byte 8
This command is also supported in QPI mode. In QPI mode, the instruction and data is shifted in on IO0-IO3.
Figure 120. Password Unlock (PASSU) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
Instruct.
Document Number: 002-00124 Rev. *H
Password Byte 1
Password Byte 8
Page 114 of 160
S25FL256L/S25FL128L
8.11 Reset Commands
Software controlled Reset commands restore the device to its initial power up state, by reloading volatile registers from non-volatile
default values. If a software reset is initiated during a Erase, Program or writing of a Register operation the data in that Sector, Page
or Register is not stable, the operation that was interrupted needs to be initiated again.
However, the volatile SRP1 bit in the Configuration register CR1V[0] and the volatile NVLOCK bit in the Protection Register are not
changed by a software reset. The software reset cannot be used to circumvent the SRP1 or NVLOCK bit protection mechanisms for
the other security configuration bits.
The SRP1 bit and the NVLOCK bit will remain set at their last value prior to the software reset. To clear the SRP1 bit and set the
NVLOCK bit to its protection mode selected power on state, a full power-on-reset sequence or hardware reset must be done.
A software reset command (RSTEN 66h followed by RST 99h) is executed when CS# is brought high at the end of the instruction
and requires tRPH time to execute.
In the case of a previous Power-up Reset (POR) failure to complete, a reset command triggers a full power up sequence requiring
tPU to complete.
Figure 121. Software / Mode Bit Reset Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 122. Software Reset / Mode Bit Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Instruction
8.11.1 Software Reset Enable (RSTEN 66h)
The Reset Enable (RSTEN) command is required immediately before a software reset command (RST 99h) such that a software
reset is a sequence of the two commands. Any command other than RST following the RSTEN command, will clear the reset enable
condition and prevent a later RST command from being recognized.
8.11.2 Software Reset (RST 99h)
The Reset (RST) command immediately following a RSTEN command, initiates the software reset process. Any command other
than RST following the RSTEN command, will clear the reset enable condition and prevent a later RST command from being
recognized.
Document Number: 002-00124 Rev. *H
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S25FL256L/S25FL128L
8.11.3 Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command is used to return the device from continuous high performance read mode back to normal
standby awaiting any new command. Because the hardware RESET# input may be disabled and a device that is in a continuous
high performance read mode may not recognize any normal SPI command, a system hardware reset or software reset command
may not be recognized by the device. It is recommended to use the MBR command after a system reset when the RESET# signal is
not available or, before sending a software reset, to ensure the device is released from continuous high performance read mode.
The MBR command sends Ones on SI/IO0for eight SCK cycles. IO1-IO3 are “don’t care” during these cycles.
8.12 Deep Power Down Commands
8.12.1 Deep Power-Down (DPD B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep PowerDown command. The lower power consumption makes the Deep Power-down (DPD) command especially useful for battery
powered applications (see ICC1 and ICC2 in Section 11.6 DC Characteristics on page 134). The command is initiated by driving the
CS# pin low and shifting the instruction code “B9h”.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power-Down command will not be
executed. After CS# is driven high, the power-down state will be entered within the time duration of tDP (Table 62 on page 141).
While in the power-down state only the Release from Deep Power-Down / Device ID command, which restores the device to normal
operation, will be recognized. All other commands are ignored. This includes the Read Status Register command, which is always
available during normal operation. Ignoring all but one command also makes the Power Down state a useful condition for securing
maximum write protection.
While in the deep power-down mode the device will only accept a hardware reset which will initiate a Power on Reset that will
restore the device to normal operation. The device always powers-up in the normal operation with the standby current of ICC1.
Figure 123. Deep Power Down (DPD) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 124. Deep Power Down (DPD) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00124 Rev. *H
3
Instruction
Page 116 of 160
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8.12.2 Release from Deep Power-Down / Device ID (RES ABh)
The Release from Deep Power-Down /Device ID command is a multi-purpose command. It can be used to release the device from
the Deep Power-Down state, or obtain the devices electronic identification (ID) number.
To release the device from the Deep Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction
code “ABh” and driving CS# high. Release from Deep Power-Down will take the time duration of tRES (Table 62 on page 141) before
the device will resume normal operation and other commands are accepted. The CS# pin must remain high during the tRES time
duration.
When used only to obtain the Device ID while not in the Deep Power-Down state, the command is initiated by driving the CS# pin
low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of
CLK with MSb first. The Device ID values for the S25FL-L Family is listed in and Table 51 on page 129. Continued shifting of output
beyond the end of the defined ID address space will provide undefined data. The command is completed by driving CS# high.
When used to release the device from the Deep Power-Down state and obtain the Device ID, the command is the same as
previously described, and shown in Figure 127 and Figure 128, except that after CS# is driven high it must remain high for a time
duration of tRES. After this time duration the device will resume normal operation and other commands will be accepted. If the
Release from Deep Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when BUSY
equals 1) the command is ignored and will not have any effects on the current cycle.
Figure 125. Release from Deep Power Down (RES) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3.
Figure 126. Release from Deep Power Down (RES) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Instruction
Figure 127. Read Identification (RES) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0 23
1
SO_IO1
Phase
0
7
Instruction
Document Number: 002-00124 Rev. *H
Dummy
6
5
4
3
Dev ID
2
1
0
7
1
0
Dev ID
Page 117 of 160
S25FL256L/S25FL128L
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
Figure 128. Read Identification (RES) QPI Mode Command
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
IO3
7
Phase
4
0
4
0
4
5
5
1
5
1
5
2
6
6
2
6
2
6
3
7
7
3
7
3
7
Instruction
Document Number: 002-00124 Rev. *H
23
22
4
Dummy
0
Dev ID
Dev ID
Page 118 of 160
S25FL256L/S25FL128L
9.
9.1
Data Integrity
Erase Endurance
Table 45. Erase Endurance
Parameter
Min
Program/Erase cycles per main Flash array sectors
Unit
100K
[79]
Program/Erase cycles per Security Registers or non-volatile register array
P/E cycle
1K
Note
79. Each write command to a non-volatile register causes a P/E cycle on the entire non-volatile register array.
9.2
Data Retention
Table 46. Data Retention
Parameter
Data Retention Time
Test Conditions
Minimum
Time
10K Program/Erase Cycles
20
100K Program/Erase Cycles
2
Unit
Years
Contact Cypress Sales or an FAE representative for additional information regarding data integrity.
Document Number: 002-00124 Rev. *H
Page 119 of 160
S25FL256L/S25FL128L
10.
Software Interface Reference
10.1 JEDEC JESD216B Serial Flash Discoverable Parameters
This document defines the Serial Flash Discoverable Parameters (SFDP) revision B data structure used in the following Cypress
Serial Flash Devices:
S25FL-L Family
These data structure values are an update to the earlier revision SFDP data structure currently existing in the above devices.
The Read SFDP (RSFDP) command (5Ah) reads information from a separate Flash memory address space for device identification,
feature, and configuration information, in accord with the JEDEC JESD216B standard for Serial Flash Discoverable Parameters.
The SFDP data structure consists of a header table that identifies the revision of the JESD216 header format that is supported and
provides a revision number and pointer for each of the SFDP parameter tables that are provided. The parameter tables follow the
SFDP header. However, the parameter tables may be placed in any physical location and order within the SFDP address space. The
tables are not necessarily adjacent nor in the same order as their header table entries.
The SFDP header points to the following parameter tables:
Basic Flash
❐ This is the original SFDP table. It has a few modified fields and new additional field added at the end of the table.
4 Byte Address Instruction
❐ This is the original SFDP table. It has a few modified fields and new additional field added at the end of the table.
The physical order of the tables in the SFDP address space is: SFDP Header, Basic Flash Sector Map, 4 Byte Instruction.
The SFDP address space is programmed by Cypress and read-only for the host system.
10.1.1 Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides a pointer to
each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B standard. Optional parameter tables for 4 Byte
Address Instructions follow the Basic Flash table.
Table 47. SFDP Overview Map
Byte Address
0000h
,,,
0300h
...
Description
Location zero within JEDEC JESD216B SFDP space - start of SFDP header
Remainder of SFDP header followed by undefined space
Start of SFDP parameter
Remainder of SFDP JEDEC parameter followed by undefined space
Document Number: 002-00124 Rev. *H
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10.1.2 SFDP Header Field Definitions
Table 48. SFDP Header
SFDP Byte
Address
SFDP Dword
Name
00h
01h
02h
Data
53h
SFDP Header
1st DWORD
03h
Description
This is the entry point for Read SFDP (5Ah) command i.e. location zero within SFDP space
ASCII “S”
46h
ASCII “F”
44h
ASCII “D”
50h
ASCII “P”
06h
SFDP Minor Revision (06h = JEDEC JESD216 Revision B)
This revision is backward compatible with all prior minor revisions. SFDP reading and parsing
software will work with higher minor revision numbers than the software was designed to
handle. Software designed for a higher revisions must know how to handle earlier revisions.
Example: SFDP reading and parsing software for minor revision 0 will still work with minor
revision 6. SFDP reading and parsing software for minor revision 6 must be designed to also
read minor revision 0 or 5. Do not do a simple compare on the minor revision number, looking
only for a match with the revision number that the software is designed to handle. There is no
problem with using a higher number minor revision.
05h
01h
SFDP Major Revision
This is the original major revision. This major revision is compatible with all SFDP reading and
parsing software.
06h
01h
Number of Parameter Headers (zero based, 01h = 2 parameters)
07h
FFh
Unused
08h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
04h
SFDP Header
2nd DWORD
09h
0Ah
Parameter
Header
0
1st DWORD
0Bh
0Ch
0Dh
0Eh
Parameter
Header
0
2nd DWORD
0Fh
10h
11h
12h
Parameter
Header
1
1st DWORD
13h
14h
15h
16h
17h
Parameter
Header
1
2nd DWORD
06h
Parameter Minor Revision (06h = JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is
compatible with this major revision.
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
00h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC Basic SPI Flash parameter byte offset = 0300h address
03h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
84h
Parameter ID LSB (84h = SFDP 4 Byte Address Instructions Parameter)
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that
recognizes this parameter’s ID is compatible with this major revision.
02h
Parameter Table Length (in double words = Dwords = 4 byte units) (2h = 2 Dwords)
40h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC parameter byte offset = 0340h
03h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
Document Number: 002-00124 Rev. *H
Page 121 of 160
S25FL256L/S25FL128L
10.1.3 JEDEC SFDP Basic SPI Flash Parameter
Table 49. Basic SPI Flash Parameter, JEDEC SFDP Rev B
SFDP Parameter
Relative Byte
Address
SFDP Dword
Name
Data
Description
E5h
Start of SFDP JEDEC parameter
Bits 7:5 = unused = 111b
Bit 4:3 = 05h is volatile status register write instruction and status register is default
non-volatile= 00b
Bit 2 = Program Buffer > 64Bytes = 1
Bits 1:0 = Uniform 4KB erase is supported through out the device = 01b
20h
Bits 15:8 = Uniform 4KB erase instruction = 20h
02h
FBh
Bit 23 = Unused = 1b
Bit 22 = Supports QOR (1-1-4) Read, Yes = 1b
Bit 21 = Supports QIO (1-4-4) Read, Yes =1b
Bit 20 = Supports DIO (1-2-2) Read, Yes = 1b
Bit19 = Supports DDR, Yes = 1b
Bit 18:17 = Number of Address Bytes, 3 or 4 = 01b
Bit 16 = Supports Fast Read SIO and DIO Yes = 1b
03h
FFh
Bits 31:24 = Unused = FFh
04h
FFh
00h
01h
JEDEC Basic Flash
Parameter Dword-1
05h
06h
FFh
JEDEC Basic Flash
Parameter Dword-2
FFh
Density in bits, zero based,
128Mb = 07FFFFFFh256Mb = 0FFFFFFFh512Mb = 1FFFFFFFh
07h
07h 128Mb0Fh
256Mb1Fh
512Mb
08h
48h
Bits 7:5 = number of QIO Mode cycles = 010b
Bits 4:0 = number of Fast Read QIO Dummy cycles = 01000b for default latency code
EBh
Fast Read QIO instruction code
08h
Bits 23:21 = number of Quad Out Mode cycles = 000b
Bits 20:16 = number of Quad Out Dummy cycles = 01000b for default latency code
0Bh
6Bh
Quad Out instruction code
0Ch
08h
Bits 7:5 = number of Dual Out Mode cycles = 000b
Bits 4:0 = number of Dual Out Dummy cycles = 01000b for default latency code
3Bh
Dual Out instruction code
88 h
Bits 23:21 = number of Dual I/O Mode cycles = 100b
Bits 20:16 = number of Dual I/O Dummy cycles = 01000b for default latency code
09h
0Ah
0Dh
0Eh
JEDEC Basic Flash
Parameter Dword-3
JEDEC Basic Flash
Parameter Dword-4
0Fh
BBh
Dual I/O instruction code
FEh
Bits 7:5 RFU = 111b
Bit 4 = QPI supported = 1b
Bits 3:1 RFU = 111b
Bit 0 = Dual All not supported = 0b
FFh
Bits 15:8 = RFU = FFh
12h
FFh
Bits 23:16 = RFU = FFh
13h
FFh
Bits 31:24 = RFU = FFh
10h
11h
JEDEC Basic Flash
Parameter Dword-5
14h
FFh
Bits 7:0 = RFU = FFh
15h
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
FFh
Dual All instruction code
16h
JEDEC Basic Flash
Parameter Dword-6
17h
Document Number: 002-00124 Rev. *H
Page 122 of 160
S25FL256L/S25FL128L
Table 49. Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword
Name
Data
Description
18h
FFh
Bits 7:0 = RFU = FFh
19h
FFh
Bits 15:8 = RFU = FFh
48h
Bits 23:21 = number of QPI Mode cycles = 010b
Bits 20:16 = number of QPI Dummy cycles = 01000b for default latency code
1Ah
JEDEC Basic Flash
Parameter Dword-7
1Bh
EBh
QPI Fast Read instruction code (Same as QIO when QPI is enabled)
1Ch
0Ch
Sector type 1 size 2^N Bytes = 4KB = 0Ch (for Uniform 4KB)
20h
Sector type 1 instruction
0Fh
Sector type 2 size 2^N Bytes = 32KB = 0Fh (for Uniform 32KB)
1Dh
1Eh
JEDEC Basic Flash
Parameter Dword-8
1Fh
52h
Sector type 2 instruction
20h
10h
Sector type 3 size 2^N Bytes = 64KB = 10h (for Uniform 64KB)
D8h
Sector type 3 instruction
00h
Sector type 4 size 2^N Bytes = not supported = 00h
23h
FFh
Sector type 4 instruction = not supported = FFh
24h
21h
Bits 31:30 = Sector Type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128
ms, 11b: 1 s) = RFU = 11b
21h
22h
JEDEC Basic Flash
Parameter Dword-9
25h
5Ah
26h
C1h
Bits 29:25 = Sector Type 4 Erase, Typical time count = RFU = 1_1111b (typ erase time
= count +1 * units = RFU =11111)
Bits 24:23 = Sector Type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128
ms, 11b: 1 s) = 16ms = 01b
Bits 22:18 = Sector Type 3 Erase, Typical time count = 1_0000b (typ erase time =
count +1 * units = 17 * 16ms = 272ms)
Bits 17:16 = Sector Type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128
ms, 11b: 1 s) = 16ms = 01b
JEDEC Basic Flash
Parameter Dword10
27h
Bits 15:11 = Sector Type 2 Erase, Typical time count = 0_1011b (typ erase time = count
+1 * units = 12 * 16ms = 192ms)
FEh
Bits 10:9 = Sector Type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128
ms, 11b: 1 s) = 16ms = 01b
Bits 8:4 = Sector Type 1 Erase, Typical time count = 0_0010b (typ erase time = count
+1 * units = 3 * 16ms = 48ms)
Bits 3:0 = Count = (Max Erase time / (2 * Typical Erase time))- 1 = 0001b
Multiplier from typical erase time to maximum erase time = 4x multiplier
Max Erase time = 2 * (Count +1) * Typ Erase time
Binary Fields: 11-11111-01-10000-01-01011-01-00010-0001
Nibble Format: 1111_1110_1100_0001_0101_1010_0010_0001
Hex Format: FE_C1_5A_21
Document Number: 002-00124 Rev. *H
Page 123 of 160
S25FL256L/S25FL128L
Table 49. Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword
Name
Data
Description
28h
81h
Bits 23 = Byte Program Typical time, additional byte units (0b:1us, 1b:8us) = 1us = 0b
29h
E4h
Bits 22:19 = Byte Program Typical time, additional byte count, (count+1) * units, count
= 0101b, (typ Program time = count +1 * units = 6 * 1µs = 6µs
Bits 18 = Byte Program Typical time, first byte units (0b:1µs, 1b:8µs) = 1µs = 0b
Bits 17:14 = Byte Program Typical time, first byte count, (count+1) * units, count =
0111b, (typ Program time = count +1 * units = 8 * 1µs = 8µs
Bits 13 = Page Program Typical time units (0b:8us, 1b:64us) = 64us = 1b
Bits 12:8 = Page Program Typical time count, (count+1) * units, count = 00100b, (typ
Program time = count +1 * units = 5 * 64µs = 320µs)
2Ah
29h
Bits 7:4 = N = 1000b, Page size= 2^N = 256B page
Bits 3:0 = Count = 0001b = (Max Page Program time / (2 * Typ Page Program time))- 1
Multiplier from typical Page Program time to maximum Page Program time = 4x
multiplier
Max Page Program time = 2 * (Count +1) * Typ Page Program time
JEDEC Basic Flash
Parameter Dword11
Binary Fields: 0-0101-0-0111-1-00100-1000-0001
Nibble Format: 0010_1001_1110_0100_1000_0001
Hex Format: 29_74_81
128Mb = 1101_0001b = D1h
Bit 31 Reserved = 1b
Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64
s) = 4s = 10b
2Bh
D1h 128Mb
E2h 256Mb
Bits 28:24 = Chip Erase, Typical time count, (count+1)*units, count = 10001b, (typ
Program time = count +1 * units = 18 * 4s = 72s
256Mb = 1110_0010b = E2h
Bit 31 Reserved = 1b
Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64
s) = 64s = 11b
Bits 28:24 = Chip Erase, Typical time count, (count+1) * units, count = 00010b, (typ
Program time = count +1 * units = 3 * 64s = 192s
Document Number: 002-00124 Rev. *H
Page 124 of 160
S25FL256L/S25FL128L
Table 49. Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword
Name
Data
Description
2Ch
CCh
Bit 31 = Suspend and Resume supported = 0b
2Dh
83h
2Eh
18h
Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b:
8µs, 11b: 64µs) = 8µs = 10b
Bits 28:24 = Suspend in-progress erase max latency count = 00100b, max erase
suspend latency = count +1 * units = 5 * 8µs = 40µs
Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = count +1 *
64µs = 2 * 64µs = 128µs
Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b: 1µs,
10b: 8µs, 11b: 64µs) = 8µs = 10b
Bits 17:13 = Suspend in-progress program max latency count = 00100b, max erase
suspend latency = count +1 * units = 5 * 8µs = 40 µs
Bits 12:9 = Program resume to suspend interval count = 0001b, interval = count +1 * 64
µs = 2 * 64 µs = 128 µs
Bit 8 = RFU = 1b
JEDEC Basic Flash
Parameter Dword12
2Fh
44h
Bits 7:4 = Prohibited operations during erase suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx0xb: May not initiate a page program anywhere
+ x1xxb: May not initiate a read in the erase suspended sector size
+ 1xxxb: The erase and program restrictions in bits 5:4 are sufficient
= 1100b
Bits 3:0 = Prohibited Operations During Program Suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx0xb: May not initiate a new page program anywhere (program nesting not
permitted)
+ x1xxb: May not initiate a read in the program suspended page size
+ 1xxxb: The erase and program restrictions in bits 1:0 are sufficient
= 1100b
Binary Fields: 0-10-00100-0001-10-00100-0001-1-1100-1100
Nibble Format: 0100_0100_0001_1000_1000_0011_1100_1100
Hex Format: 44_18_83_CC
30h
31h
32h
7Ah
JEDEC Basic Flash
Parameter Dword13
75h
7Ah
Bits 31:24 = Erase Suspend Instruction = 75h
Bits 23:16 = Erase Resume Instruction = 7Ah
Bits 15:8 = Program Suspend Instruction = 75h
Bits 7:0 = Program Resume Instruction = 7Ah
33h
75h
34h
F7h
Bit 31 = Deep Power Down Supported = supported = 0
35h
A2h
Bits 30:23 = Enter Deep Power Down Instruction = B9h = 1011_1001b
36h
D5h
Bits 22:15 = Exit Deep Power Down Instruction = ABh = 1010_1011b
Bits 14:13 = Exit Deep Power Down to next operation delay units = (00b: 128ns, 01b:
1µs, 10b: 8µs, 11b: 64µs) = 1µs = 01b
Bits 12:8 = Exit Deep Power Down to next operation delay count = 00010b, Exit Deep
Power Down to next operation delay = (count+1) * units = 3 * 1µs = 3µs
JEDEC Basic Flash
Parameter Dword14
37h
Bits 7:4 = RFU = Fh
5Ch
Bit 3:2 = Status Register Polling Device Busy
= 01b: Legacy status polling supported = Use legacy polling by reading the Status
Register with 05h instruction and checking WIP bit[0] (0=ready; 1=busy).
Bits 1:0 = RFU = 11b
Binary Fields: 0-10111001-10101011-01-00010-1111-01-11
Nibble Format: 0101_1100_1101_0101_1010_0010_1111_0111
Hex Format: 5C_D5_A2_F7
Document Number: 002-00124 Rev. *H
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Table 49. Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword
Name
Data
38h
22h
39h
F6h
3Ah
5Dh
Description
Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP Disable = not supported = 0b
Bits 22:20 = Quad Enable Requirements
= 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read Status
instruction 05h. Status register 2 is read using instruction 35h. QE is set via Write
Status instruction 01h with two data bytes where bit 1 of the second byte is one. It is
cleared via Write Status with two data bytes where bit 1 of the second byte is zero.
Bits 19:16 0-4-4 Mode Entry Method
= xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode
+ x1xxb: Mode Bits[7:0] = Axh
+ 1xxxb: RFU
= 1101b
JEDEC Basic Flash
Parameter Dword15
3Bh
FFh
Bits 15:10 0-4-4 Mode Exit Method
= xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current
read operation
+ xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate the
mode prior to the next read operation.
+ 11_x1xx: RFU
= 111101
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences
= 0_0010b: issue instruction 38h
Bits 3:0 = 4-4-4 mode disable sequences
= 0010b: 4-4-4 issues F5h instruction
Binary Fields: 11111111-0-101-1101-111101-1-00010-0010
Nibble Format: 1111_1111_0101_1101_1111_0110_0010_0010
Hex Format: FF_5D_F6_22
Document Number: 002-00124 Rev. *H
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Table 49. Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword
Name
Data
Description
Bits 31:24 = Enter 4-Byte Addressing
= xxxx_xxx1b:issue instruction B7 (preceding write enable not required
= xxxx_1xxxb: 8-bit volatile bank register used to define A[30:24] bits. MSb (bit[7]) is
used to enable/disable 4-byte address mode. When MSb is set to ‘1’, 4-byte address
mode is active and A[30:24] bits are don’t care. Read with instruction 16h. Write
instruction is 17h with 1 byte of data. When MSb is cleared to ‘0’, select the active 128
Mb segment by setting the appropriate A[30:24] bits and use 3-Byte addressing.
+ xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data
sheet for the instruction set definition or look for 4 Byte Address Parameter Table.
+ 1xxx_xxxxb: Reserved
= 10100001b
3Ch
E8h
3Dh
50h
3Eh
F8h
Bits 23:14 = Exit 4-Byte Addressing
= xx_xxxx_xxx1b:issue instruction E9h to exit 4-Byte address mode (Write enable
instruction 06h is not required)
= xx_xxxx_1xxxb: 8-bit volatile bank register used to define A[30:24] bits. MSb (bit[7])
is used to enable/disable 4-byte address mode. When MSb is cleared to ‘0’, 3-byte
address mode is active and A30:A24 are used to select the active 128 Mb memory
segment. Read with instruction 16h. Write instruction is 17h, data length is 1 byte.
+ xx_xx1x_xxxxb: Hardware reset
+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)
+ xx_1xxx_xxxxb: Power cycle
+ x1_xxxx_xxxxb: Reserved
+ 1x_xxxx_xxxxb: Reserved
= 1111100001b
JEDEC Basic Flash
Parameter Dword16
3Fh
A1h
Bits 13:8 = Soft Reset and Rescue Sequence Support
= x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The
reset enable, reset sequence may be issued on 1,2, or 4 wires depending on the
device operating mode
= 010000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for Status
Register 1
= xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value in
the non-volatile status register, use instruction 06h to enable write to non-volatile status
register. Volatile status register may be activated after power-up to override the nonvolatile status register, use instruction 50h to enable write and activate the volatile
status register.
+ x1x_xxxxb: Reserved
+ 1xx_xxxxb: Reserved
= 1101000b
Binary Fields: 10100001-1111100001-010000-1-1101000
Nibble Format: 1010_0001_1111_1000_0101_0000_1110_1000
Hex Format: A1_F8_60_E8
Document Number: 002-00124 Rev. *H
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10.1.4 JEDEC SFDP 4-byte Address Instruction Table
Table 50. 4-byte Address Instruction, JEDEC SFDP Rev B
SFDP Parameter
Relative Byte
Address
SFDP Dword
Name
Data
40h
FBh
41h
8Eh
42h
F3h
43h
JEDEC 4 Byte
Address
Instructions
Parameter Dword1h
FFh
Description
Supported = 1, Not Supported = 0
Bits 31:20 = RFU = FFFh
Bit 19 = Support for non-volatile individual sector lock write command,
Instruction = E3h = 0
Bit 18 = Support for non-volatile individual sector lock read command,
Instruction = E2h = 0
Bit 17 = Support for volatile individual sector lock Write command,
Instruction = E1h = 1
Bit 16 = Support for volatile individual sector lock Read command,
Instruction = E0h = 1
Bit 15 = Support for (1-4-4) DTR_Read Command, Instruction = EEh = 1
Bit 14 = Support for (1-2-2) DTR_Read Command, Instruction = BEh = 0
Bit 13 = Support for (1-1-1) DTR_Read Command, Instruction = 0Eh = 0
Bit 12 = Support for Erase Command – Type 4 = 0
Bit 11 = Support for Erase Command – Type 3 = 1
Bit 10 = Support for Erase Command – Type 2 = 1
Bit 9 = Support for Erase Command – Type 1 = 1
Bit 8 = Support for (1-4-4) Page Program Command, Instruction = 3Eh =0
Bit 7 = Support for (1-1-4) Page Program Command, Instruction = 34h = 1
Bit 6 = Support for (1-1-1) Page Program Command, Instruction = 12h = 1
Bit 5 = Support for (1-4-4) FAST_READ Command, Instruction = ECh = 1
Bit 4 = Support for (1-1-4) FAST_READ Command, Instruction = 6Ch = 1
Bit 3 = Support for (1-2-2) FAST_READ Command, Instruction = BCh = 1
Bit 2 = Support for (1-1-2) FAST_READ Command, Instruction = 3Ch = 0
Bit 1 = Support for (1-1-1) FAST_READ Command, Instruction = 0Ch = 1
Bit 0 = Support for (1-1-1) READ Command, Instruction = 13h = 1
Nibble Format: 1111_1111_1111_0011_1000_1110_1111_1011
Hex Format: FF_F3_8E_FB
44h
45h
46h
47h
JEDEC 4 Byte
Address
Instructions
Parameter Dword2h
Document Number: 002-00124 Rev. *H
21h
52h
DCh
FFh
Bits 31:24 = FFh = Instruction for Erase Type 4: RFU
Bits 23:16 = DCh = Instruction for Erase Type 3 Block
Bits 15:8 = 52h = Instruction for Erase Type 2 Half Block
Bits 7:0 = 21h = Instruction for Erase Type 1 Sector
Page 128 of 160
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10.2 Device ID Address Map
10.2.1 Field Definitions
Table 51. Manufacturer Device Type
Byte Address
Data
00h
01h
Manufacturer ID for Cypress
Description
01h
60h
Device ID MSB - Memory Interface Type
02h
18h (128Mb)
19h (256Mb)
03h
Undefined
Device ID LSB - Density and Features
Reserved for Future Use
Table 52. Unique Device ID
Byte Address
Data
00h to 07
8 Byte Unique Device ID
Description
64-bit unique ID number, see section Section 6.3.1 Device
Unique ID on page 24.
10.3 Initial Delivery State
The device is shipped from Cypress with non-volatile bits set as follows:
The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).
The Security Region address space has all bytes erased to FFh.
The SFDP address space contains the values as defined in the description of the SFDP address space.
The ID address space contains the values as defined in the description of the ID address space.
The Status Register 1 Non-volatile contains 00h (all SR1NV bits are cleared to 0’s).
The Configuration Register 1 Non-volatile contains 00h.
The Configuration Register 2 Non-volatile contains 60h.
The Configuration Register 3 Non-volatile contains 78h.
The Password Register contains FFFFFFFF-FFFFFFFFh
The IRP Register bits are FFFDh for Standard Part and FFFFh for High Security Part.
The PRPR Register bits are FFFFFFh
Document Number: 002-00124 Rev. *H
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11. Electrical Specifications
11.1 Absolute Maximum Ratings
(Note 80)
Storage Temperature Plastic Packages.....................................................................................................................–65°C to +150°C
Ambient Temperature with Power Applied.................................................................................................................–65°C to +125°C
VCC...............................................................................................................................................................................–0.5 V to +4.0 V
Input voltage with respect to Ground (VSS) (Note 1)...........................................................................................–0.5 V to VCC + 0.5 V
Output Short Circuit Current (Note 2)...................................................................................................................................... 100 mA
Notes
80. See Section 11.4.3 Input Signal Overshoot on page 131 for allowed maximums during signal transition.
81. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
82. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
11.2 Latchup Characteristics
Table 53. Latchup Specification
Description
Input voltage with respect to VSS on all input only connections
Input voltage with respect to VSS on all I/O connections
VCC Current
Min
Max
Unit
–1.0
VCC + 1.0
V
–100
+100
mA
Note
83. Excludes power supply VCC. Test conditions: VCC = 3.0 V, one connection at a time tested, connections not being tested are at VSS.
11.3 Thermal Resistance
Table 54. Thermal Resistance
Parameter
Theta JA
Description
SO316
SOC008
WND008
WNG008
FAB024
FAC024
Unit
Thermal resistance
(junction to
ambient)
38
53.27
32
18
39
39
°C/W
Document Number: 002-00124 Rev. *H
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11.4 Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
11.4.1 Power Supply Voltages
2.7V to 3.6V
VCC
11.4.2 Temperature Ranges
Parameter
Symbol
Ambient Temperature
Devices
Min
Max
Industrial (I)
+85
Industrial Plus (V)
+105
Extended (N)
TA
Spec
Automotive, AEC-Q100 Grade 3 (A)
–40
+125
+85
Automotive, AEC-Q100 Grade 2 (B)
+105
Automotive, AEC-Q100 Grade 1 (M)
+125
Unit
°C
11.4.3 Input Signal Overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage transitions, inputs or I/Os
may overshoot VSS to –1.0 V or overshoot to VCC +1.0 V, for periods up to 20 ns.
Figure 129. Maximum Negative Overshoot Waveform
VSS to VCC
–1.0
V
< = 20 ns
Figure 130. Maximum Positive Overshoot Waveform
< = 20 ns
VCC + 1.0 V
VSS to VCC
Document Number: 002-00124 Rev. *H
Page 131 of 160
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11.5 Power-Up and Power-Down
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VCC) until VCC reaches
the correct value as follows:
VCC (min) at power-up, and then for a further delay of tPU
VSS at power-down
User is not allowed to enter any command until a valid delay of tPU has elapsed after the moment that VCC rises above the minimum
VCC threshold. See Figure 131. However, correct operation of the device is not guaranteed if VCC returns below VCC (min) during
tPU. No command should be sent to the device until the end of tPU.
The device draws IPOR during tPU. After power-up (tPU), the device is in Standby mode, draws CMOS standby current (ISB), and the
WEL bit is reset.
During power-down or if supply voltage drops below VCC(cut-off), the supply voltage must stay below VCC(low) for a period of tPD for
the part to initialize correctly on power-up. See Figure 132 on page 133. If during a voltage drop the VCC stays above VCC (cut-off)
the part will stay initialized and will work correctly when VCC is again above VCC (min). In the event Power-on Reset (POR) did not
complete correctly after power up, the assertion of the RESET# signal or receiving a software reset command (RSTEN 66h followed
by RST 99h) will restart the POR process.
If VCC drops below the VCC (Cut-off) during an embedded program or erase operation the embedded operation may be aborted and
the data in that memory area may be incorrect.
Normal precautions must be taken for supply rail decoupling to stabilize the VCC supply at the device. Each device in a system
should have the VCC rail decoupled by a suitable capacitor close to the package supply connection (this capacitor is generally of the
order of 0.1 µf).
Table 55. Power-Up / Power-Down Voltage and Timing
Symbol
Parameter
VCC (min)
VCC (cut-off)
VCC (low)
Min
Max
VCC (minimum operation voltage)
2.7
–
VCC (Cut 0ff where re-initialization is needed)
2.4
–
VCC (low voltage for initialization to occur)
1.0
–
–
300
10.0
–
tPU
VCC (min) to Read operation
tPD
VCC (low) time
Unit
V
µs
Figure 131. Power-up
VCC (Max)
VCC (Min)
tPU
Full Device Access
Time
Document Number: 002-00124 Rev. *H
Page 132 of 160
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Figure 132. Power-down and Voltage Drop
VCC (Max)
No Device Access Allowed
VCC (Min)
tPU
VCC (Cut-off)
VCC (Low)
tPD
Time
Document Number: 002-00124 Rev. *H
Page 133 of 160
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11.6 DC Characteristics
Table 56. DC Characteristics — Operating Temperature Range –40°C to +85°C
Symbol
Parameter
Test Conditions
Min
Typ[84]
Max
VIL
Input Low Voltage
–
–0.5
–
0.3 VCC
VIH
Input High Voltage
–
0.7 VCC
–
VCC+0.4
VOL
Output Low Voltage
IOL = 0.1 mA, VCC = VCC min
–
0.2
VOH
Output High Voltage
IOH = –0.1 mA
VCC - 0.2
–
–
–
±2
–
–
±2
15
15
15
20
25
30
30
35
20
25
ILI
Input Leakage Current VCC = VCC Max, VIN=VIH or VSS, CS# = VIH
ILO
Output Leakage
Current
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
ICC1
Active Power Supply
Current (READ)[85]
Serial SDR @ 5 MHz
Serial SDR @ 10 MHz
Serial SDR @ 20 MHz
Serial SDR @ 50 MHz
Serial SDR @ 108 MHz
Serial SDR @ 133 MHz
QIO/QPI SDR @ 108 MHz
QIO/QPI SDR @ 133 MHz
QIO/QPI DDR @ 30 MHz
QIO/QPI DDR @ 66 MHz
–
10
10
10
15
20
22
25
30
15
22
ICC2
Active Power Supply
Current
(Page Program)
CS# = VCC
–
40
50
ICC3
Active Power Supply
Current
(WRR or WRAR)
CS# = VCC
–
24
30
ICC4
Active Power Supply
Current (SE)
CS# = VCC
–
20
25
ICC5
Active Power Supply
Current (HBE, BE)
CS# = VCC
–
25
35
RESET#, CS# = VCC; SI, SCK = VCC or
VSS: SPI, Dual I/O and Quad I/O Modes
–
20
35
RESET#, CS# = VCC; SI, SCK = VCC or
VSS: QPI Mode
–
40
60
ISB
Standby Current
IDPD
Deep Power Down
Current
RESET#, CS# = VCC, VIN = GND or VCC
–
2
20
IPOR
Power On Reset
Current
RESET#, CS# = VCC; SI,
SCK = VCC or VSS
–
15
30
Unit
V
µA
mA
µA
mA
Notes
84. Typical values are at TAI = 25°C and VCC = 3.0 V.
85. Outputs unconnected during read data return. Output switching current is not included.
Document Number: 002-00124 Rev. *H
Page 134 of 160
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Table 57. DC Characteristics — Operating Temperature Range –40°C to +105°C
Symbol
Parameter
Test Conditions
Min
Typ[86]
Max
VIL
Input Low Voltage
–
–0.5
–
0.3 VCC
VIH
Input High Voltage
–
0.7 VCC
–
VCC+0.4
VOL
Output Low Voltage
IOL = 0.1 mA, VCC = VCC min
–
–
0.2
VOH
Output High Voltage
IOH = –0.1 mA
VCC - 0.2
–
–
ILI
V = VCC Max, VIN = VIH or VSS,
Input Leakage Current CC
CS# = VIH
–
–
±4
ILO
Output Leakage
Current
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
±4
ICC1
Active Power Supply
Current (READ)[87]
Serial SDR @ 5 MHz
Serial SDR @ 10MHz
Serial SDR @ 20 MHz
Serial SDR @ 50 MHz
Serial SDR @ 108Mhz
Serial SDR @133MHz
QIO/QPI SDR @ 108MHz
QIO/QPI SDR @ 133 MHz
QIO/QPI DDR @ 30MHz
QIO/QPI DDR @ 66 MHz
–
10
10
10
15
20
22
25
30
15
22
15
15
15
20
30
30
35
30
20
25
ICC2
Active Power Supply
Current
(Page Program)
CS# = VCC
–
40
50
ICC3
Active Power Supply
Current
(WRR or WRAR)
CS# = VCC
–
24
35
ICC4
Active Power Supply
Current (SE)
CS# = VCC
–
20
30
ICC5
Active Power Supply
Current (HBE, BE)
CS# = VCC
–
25
35
RESET#, CS# = VCC; SI, SCK = VCC or
VSS: SPI, Dual I/O and Quad I/O Modes
–
20
45
RESET#, CS# = VCC; SI, SCK = VCC or
VSS: QPI Mode
–
40
80
ISB
Standby Current
Unit
V
µA
IDPD
Deep Power Down
Current
RESET#, CS# = VCC, VIN = GND or VCC
–
2
30
IPOR
Power On Reset
Current
RESET#, CS# = VCC; SI, SCK = VCC or
VSS
–
15
30
mA
µA
mA
Notes
86. Typical values are at TAI = 25°C and VCC = 3.0 V.
87. Outputs unconnected during read data return. Output switching current is not included.
Document Number: 002-00124 Rev. *H
Page 135 of 160
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Table 58. DC Characteristics — Operating Temperature Range –40°C to +125°C
Symbol
Parameter
Test Conditions
Min
Typ[88]
Max
VIL
Input Low Voltage
–
–0.5
–
0.3 VCC
VIH
Input High Voltage
–
0.7 VCC
–
VCC+0.4
VOL
Output Low Voltage
IOL = 0.1 mA, VCC = VCC min
–
–
0.2
VOH
Output High Voltage
IOH = –0.1 mA
VCC - 0.2
–
–
Input Leakage Current
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
±4
Output Leakage Current
VCC = VCC Max, VIN = VIH or VSS,
CS# = VIH
–
–
±4
ICC1
Active Power Supply Current
(READ)[89]
Serial SDR @ 5 MHz
Serial SDR @ 10MHz
Serial SDR @ 20 MHz
Serial SDR @ 50 MHz
Serial SDR @ 108Mhz
Serial SDR @ 133MHz
QIO/QPI SDR @ 108MHz
QIO/QPI SDR @ 133 MHz
QIO/QPI DDR @ 30MHz
QIO/QPI DDR @ 66 MHz
–
10
10
10
15
20
22
25
30
15
22
15
15
15
20
30
30
35
35
20
25
ICC2
Active Power Supply Current
(Page Program)
CS# = VCC
–
40
50
ICC3
Active Power Supply Current
(WRR or WRAR)
CS# = VCC
–
24
35
ICC4
Active Power Supply Current
(SE)
CS# = VCC
–
20
30
ICC5
Active Power Supply Current
(HBE, BE)
CS# = VCC
–
25
35
–
20
70
Standby Current
RESET#, CS# = VCC; SI,
SCK = VCC or VSS: SPI, Dual I/O
and Quad I/O Modes
RESET#, CS# = VCC; SI,
SCK = VCC or VSS: QPI Mode
–
40
80
ILI
ILO
ISB
Unit
V
µA
IDPD
Deep Power Down Current
RESET#, CS# = VCC,
VIN = GND or VCC
–
2
50
IPOR
Power On Reset Current
RESET#, CS# = VCC;
SI, SCK = VCC or VSS
–
15
35
mA
µA
mA
Notes
88. Typical values are at TAI = 25°C and VCC = 1.8 V.
89. Outputs unconnected during read data return. Output switching current is not included.
11.6.1 Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but
may still be in an Active Power mode until all program, erase, and write operations have completed. The device then goes into the
Standby Power mode, and power consumption drops to ISB.
11.6.2 Deep Power Down Power Mode (DPD)
The Deep Power Down mode is enabled by inputing the command instruction code “B9h” and the power consumption drops to IDPD.
In DPD mode the device responds only to the Resume from DPD command (RES ABh) or Hardware reset (RESET# and IO3 /
RESET#). All other commands are ignored during DPD mode.
Document Number: 002-00124 Rev. *H
Page 136 of 160
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12. Timing Specifications
12.1 Key to Switching Waveforms
Figure 133. Waveform Element Meanings
Input
Valid at logic high or low
High Impedance
Any change permitted
Logic high
Logic low
Valid at logic high or low
High Impedance
Changing, state unknown
Logic high
Logic low
Symbol
Output
12.2 AC Test Conditions
Figure 134. Test Setup
Device
Under
Test
CL
Table 59. AC Measurement Conditions
Symbol
Parameter
Min
CL
Load Capacitance
–
–
Input Pulse Voltage
0.2 VCC
–
Input Timing Ref Voltage
–
Output Timing Ref
Voltage
Max
15 / 30
Unit
[90]
pF
0.8 VCC
V
0.5 VCC
Notes
90. Load Capacitance depends on the operation frequency or Mode of operation.
91. AC characteristics tables assume clock and data signals have the same slew rate (slope). See Section 62 SDR AC Characteristics on page 141 note [95] for Slew
Rates at operating frequencies.
Figure 135. Input, Output, and Timing Reference Levels
Input Levels
Output Levels
VCC + 0.4V
0.8 x VCC
0.5 x VCC
0.2 x VCC
- 0.5V
Document Number: 002-00124 Rev. *H
VCC - 0.2V
Timing Reference Level
0.2V
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12.2.1 Capacitance Characteristics
Table 60. Capacitance
Parameter
Test
Conditions
Min
Max
CIN
Input Capacitance (applies to SCK, CS#, RESET#, IO3 / RESET#)
1 MHz
–
8
COUT
Output Capacitance (applies to All I/O)
1 MHz
–
8
Unit
pF
12.3 Reset
If a Hardware Reset is initiated during a Erase, Program or writing of a Register operation the data in that Sector, Page or Register
is not stable, the operation that was interrupted needs to be initiated again. If a Hardware Reset is initiated during a Software Reset
operation, the Hardware Reset might be ignored.
12.3.1 Power-On (Cold) Reset
The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the moment that VCC rises above
the minimum VCC threshold. See Figure 131 on page 132, Table 55 on page 132. The device must not be selected (CS# to go high
with VCC) during power-up (tPU), i.e. no commands may be sent to the device until the end of tPU.
RESET# and IO3 / RESET# reset function is ignored during POR. If RESET# or IO3 / RESET# is low during POR and remains low
through and beyond the end of tPU, CS# must remain high until tRH after RESET# and IO3 / RESET# returns high. RESET# and IO3
/ RESET# must return high for greater than tRS before returning low to initiate a hardware reset.
The IO3 / RESET# input functions as the RESET# signal when CS# is high for more than tCS time or when Quad or QPI Mode is not
enabled CR1V[1]=0 or CR2V[3]=0.
Figure 136. Reset low at the end of POR
VCC
tPU
RESET#
If RESET# is low at tPU end
tRH
CS#
CS# must be high at tPU end
Figure 137. Reset high at the end of POR
VCC
tPU
RESET#
If RESET# is high at tPU end
tPU
CS#
CS# may stay high or go low at tPU end
Figure 138. POR followed by Hardware Reset
VCC
tPU
tRS
RESET#
tPU
CS#
Document Number: 002-00124 Rev. *H
Page 138 of 160
S25FL256L/S25FL128L
12.3.2 RESET # and IO3 / RESET# Input Initiated Hardware (Warm) Reset
The RESET# and IO3 / RESET# inputs can function as the RESET# signal. Both inputs can initiate the reset operation under
conditions.
The RESET# input initiates the reset operation when transitions from VIH to VIL for > tRP, the device will reset register states in the
same manner as power-on reset but, does not go through the full reset process that is performed during POR. The hardware reset
process requires a period of tRPH to complete. The RESET# input is available only on the SOIC 16 lead and BGA ball packages.
The IO3 / RESET# input initiates the reset operation under the following when CS# is high for more than tCS time or when Quad or
QPI Mode is not enabled CR1V[1]=0 or CR2V[3]=0. The IO3 / RESET# input has an internal pull-up to VCC and may be left
unconnected if Quad or QPI mode is not used. The tCS delay after CS# goes high gives the memory or host system time to drive IO3
high after its use as a Quad or QPI mode I/O signal while CS# was low. The internal pull-up to VCC will then hold IO3 / RESET# high
until the host system begins driving IO3 / RESET#. The IO3 / RESET# input is ignored while CS# remains high during tCS, to avoid
an unintended Reset operation. If CS# is driven low to start a new command, IO3 / RESET# is used as IO3.
When the device is not in Quad or QPI mode or, when CS# is high, and IO3 / RESET# transitions from VIH to VIL for > tRP, following
tCS, the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is
performed during POR.
The hardware reset process requires a period of tRPH to complete. If the POR process did not complete correctly for any reason
during power-up (tPU), RESET# going low will initiate the full POR process instead of the hardware reset process and will require tPU
to complete the POR process.
The software reset command (RSTEN 66h followed by RST 99h) is independent of the state of RESET # and IO3 / RESET#. If
RESET# and IO3 / RESET# is high or unconnected, and the software reset instructions are issued, the device will perform software
reset.
Additional notes:
If both RESET# and IO3 / RESET# input options are available use only one reset option in your system. IO3 / RESET# input reset
operation can be disable by setting CR2NV[7] = 0 (see Table 14 on page 32) setting the IO3_RESET to only operate as IO3. The
RESET# input can be disable by not connecting or tying the RESET# input to VIH. RESET# and IO3 / RESET# must be high for
tRS following tPU or tRPH, before going low again to initiate a hardware reset.
When IO3 / RESET# is driven low for at least a minimum period of time (tRP), following tCS, the device terminates any operation in
progress, makes all outputs high impedance, and ignores all read/write commands for the duration of tRPH. The device resets the
interface to standby state.
If Quad or QPI mode and the IO3 / RESET# feature are enabled, the host system should not drive IO3 low during tCS, to avoid
driver contention on IO3. Immediately following commands that transfer data to the host in Quad or QPI mode, e.g. Quad I/O
Read, the memory drives IO3 / RESET# high during t CS, to avoid an unintended Reset operation. Immediately following
commands that transfer data to the memory in Quad mode, e.g. Page Program, the host system should drive IO3 / RESET# high
during tCS, to avoid an unintended Reset operation.
If Quad or QPI mode is not enabled, and if CS# is low at the time IO3 / RESET# is asserted low, CS# must return high during tRPH
before it can be asserted low again after tRH.
Table 61. Hardware Reset Parameters
Parameter
Description
Limit
tRS
Reset Setup - Prior Reset end and RESET# high
before RESET# low
tRPH
Reset Pulse Hold - RESET# low to CS# low
tRP
RESET# Pulse Width
200
tRH
Reset Hold - RESET# high before CS# low
150
Min
Time
Unit
50
ns
100
µs
ns
Notes
92. RESET# and IO3 / RESET# Low is ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will
determine when CS# may go Low.
93. If Quad or QPI mode is enabled, IO3 / RESET# Low is ignored during tCS
94. Sum of tRP and tRH must be equal to or greater than tRPH.
Document Number: 002-00124 Rev. *H
Page 139 of 160
S25FL256L/S25FL128L
Figure 139. Hardware Reset using RESET# Input
tRP
RESET#
Any prior reset
tRH
tRH
tRPH
tRS
tRPH
CS#
Figure 140. Hardware Reset when Quad or QPI Mode is not enabled and IO3 / RESET# is Enabled
tRP
IO3_RESET#
Any prior reset
tRH
tRH
tRPH
tRS
tRPH
CS#
Figure 141. Hardware Reset when Quad or QPI Mode and IO3 / RESET# are Enabled
tDIS
IO3_RESET#
tRP
Reset Pulse
tRH
tCS
CS#
tRPH
Prior access using IO3 for data
Document Number: 002-00124 Rev. *H
Page 140 of 160
S25FL256L/S25FL128L
12.4 SDR AC Characteristics
Table 62. SDR AC Characteristics
Symbol
Parameter
Min
Max
FSCK, R
SCK Clock Frequency for READ and 4READ
instructions
DC
50
FSCK, C
SCK Clock Frequency for the following dual and quad
commands: QOR, 4QOR, DIOR, 4DIOR, QIOR,
4QIOR
DC
133
PSCK
MHz
1/ FSCK
–
tWH, tCH
Clock High Time
50% PSCK ±5%
–
tWL, tCL
Clock Low Time
50% PSCK ±5%
–
0.1
–
0.1
–
CS# High Time (Any Read Instructions)
20
–
CS# High Time (All other Non-Read instructions)
50
–
CS# Active Setup Time (relative to SCK)
3
–
tCRT, tCLCH
tCFT, tCHCL
tCS
tCSS
SCK Clock Period
Clock Rise Time (slew rate)[95]
Clock Fall Time (slew rate)
[95]
tCSH
CS# Active Hold Time (relative to SCK)
5
–
tSU
Data in Setup Time
3
–
tHD
Data in Hold Time
2
tV
tHO
Unit
ns
V/ns
–
[96]
Clock Low to Output Valid
–
8
6[97]
Output Hold Time
1
–
–
8
20[99]
[98]
–
tDIS
Output Disable Time
Output Disable Time (when Reset feature and Quad
mode are both enabled)
tWPS
WP# Setup Time[100]
20
–
tWPH
WP# Hold Time[100]
100
–
TDP
CS# High to Deep Power Down Mode
–
3
TRES
CS# High to Release from Deep Power Down Mode
–
5
tQEN
QIO or QPI Enter mode, time needed to issue next
command
–
1.5
tQEXN
QIO or QPI Exit mode, time needed to issue next
command
–
1
ns
µs
Notes
95. tCRT, tCLCH Clock Rise and fall slew rate for Fast clock (108 MHz) min is 1.5 V/ns and for Slow Clock (50 MHz) min is 1.0 V/ns.
96. Full VCC range and CL = 30 pF.
97. Full VCC range and CL = 15 pF.
98. Output HI-Z is defined as the point where data is no longer driven.
99. tDIS require additional time when the Reset feature and Quad mode are enabled (CR2V[7] = 1 and CR1V[1] = 1).
100.Only applicable as a constraint for WRR or WRAR instruction when SRP0 is set to a 1.
Document Number: 002-00124 Rev. *H
Page 141 of 160
S25FL256L/S25FL128L
12.4.1 Clock Timing
Figure 142. Clock Timing
PSCK
tCL
tCH
VIH min
VCC / 2
VIL max
tCFT
tCRT
12.4.2 Input / Output Timing
Figure 143. SPI Single Bit Input Timing
tCS
CS#
tCSH
tCSS
SCK
tSU
tHD
SI_IO0
MSb IN
LSb IN
SO
Figure 144. SPI Single Bit Output Timing
tCS
CS#
SCK
SI
tV
SO
Document Number: 002-00124 Rev. *H
tHO
MSb OUT
tDIS
LSb OUT
Page 142 of 160
S25FL256L/S25FL128L
Figure 145. SDR MIO Timing
tCS
CS#
tCSH
tCSS
SCLK
tSU
tHD
IO
MSB IN
tV
LSB IN
tHO
tV
MSB OUT.
tDIS
LSB OUT
Figure 146. WP# Input Timing
CS#
tWPS
tWPH
WP#
SCLK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
WRR or WRAR Instruction
Document Number: 002-00124 Rev. *H
Input Data
Page 143 of 160
S25FL256L/S25FL128L
12.5 DDR AC Characteristics
Table 63. DDR AC Characteristics 66 MHz operation
Symbol
Parameter
FSCK, R
SCK Clock Frequency for DDR READ instruction
PSCK, R
SCK Clock Period for DDR READ instruction
Min
Max
Unit
DC
66
MHz
1/FSCK
–
ns
tcrt
Clock Rise Time (slew rate)
1.5
–
tcft
Clock Fall Time (slew rate)
1.5
–
tWH, tCH
Clock High Time
50% PSCK -5%
–
tWL, tCL
Clock Low Time
50% PSCK -5%
–
tCS
CS# High Time (Read Instructions)
CS# High Time (Read Instructions when Reset feature
is enabled)
20
50
–
tCSS
CS# Active Setup Time (relative to SCK)
3
–
tSU
IO in Setup Time
3
–
tHD
IO in Hold Time
2
–
Clock Low to Output Valid
–
8[101]
6[102]
tHO
Output Hold Time
1
–
tDIS
Output Disable Time
Output Disable Time (when Reset feature is enabled)
–
8
20
First IO to last IO data valid time
–
600[103]
tV
tO_skew
V/ns
ns
ps
Notes
101.Full VCC range and CL = 30 pF.
102.Full VCC range and CL = 15 pF.
103.Not tested.
12.5.1 DDR Input Timing
Figure 147. SPI DDR Input Timing
tCS
CS#
tCSS
SCK
tHD
tSU
tHD
tSU
IO's
Inst. MSB
Document Number: 002-00124 Rev. *H
MSB IN
LSB IN
Page 144 of 160
S25FL256L/S25FL128L
12.5.2 DDR Output Timing
Figure 148. SPI DDR Output Timing
tCS
CS#
SCK
tHO
IO's
tV
tV
tDIS
MSB
LSB
12.5.3 DDR Data Valid Timing using DLP
Figure 149. SPI DDR Data Valid Window
p SCK
t CL
t CH
SCK
t IO_SKEW
tV
t OTT
IO Slow
Slow D1
Slow D2
tV
IO Fast
Fast D1
Fast D2
t V _min
t HO
t DV
IO_valid
D1
D2
The minimum data valid window (tDV) and tV minimum can be calculated as follows:
tDV = Minimum half clock cycle time (tCLH[104]) - tOTT[106] - tIO_SKEW[105]
tV _min = tHO + tIO_SKEW + tOTT
Example:
66 MHz clock frequency = 15 ns clock period, DDR operations and duty cycle of 45% or higher
❐ tCLH = 0.45 x PSCK = 0.45 x 15 ns = 6.75 ns
tOTT calculation[107] is bus impedance of 45 ohm and capacitance of 37 pf, with timing reference of 0.75 VCC, the rise time from 0 to
1 or fall time 1 to 0 is 1.4[110] x RC time constant (Tau)[109] = 1.4 x 1.67 ns = 2.34 ns
❐ tOTT = rise time or fall time = 2.34 ns.
Data Valid Window
❐ tDV = tCLH - tIO_SKEW - tOTT = 6.75 ns - 600 ps - 2.34 ns = 3.81 ns
tV Minimum
❐ tV _min = tHO + tIO_SKEW + tOTT = 1.0 ns + 600 ps + 2.34 ns = 3.94 ns
Notes
104.tCLH is the shorter duration of tCL or tCH.
105.tIO_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all IO signals.
106.tOTT is the maximum Output Transition Time from one valid data value to the next valid data value on each IO.
107.tOTT is dependent on system level considerations including:
a. Memory device output impedance (drive strength).
b. System level parasitics on the IOs (primarily bus capacitance).
c. Host memory controller input VIH and VIL levels at which 0 to 1 and 1 to 0 transitions are recognized.
d. tOTT is not a specification tested by Cypress, it is system dependent and must be derived by the system designer based on the above considerations.
108.tDV is the data valid window.
109.Tau = R (Output Impedance) x C (Load capacitance).
110.Multiplier of Tau time for voltage to rise to 75% of VCC.
Document Number: 002-00124 Rev. *H
Page 145 of 160
S25FL256L/S25FL128L
12.6 Embedded Algorithm Performance Tables
Table 64. Dual Quad Program and Erase Performance
Symbol
Parameter
Min
Typ (111)
Max
Unit
ms
tW
Non-volatile Register Write Time
–
145
750
tPP
Page Programming (256 Bytes)
–
300
1,200
tBP1
Byte Programming (First Byte)[113]
–
50
60
6
20
[113]
tBP2
Additional Byte Programming (After First Byte)
–
tSE
Sector Erase Time (4KB physical sectors)
–
50
250
tHBE
Half Block Erase Time (32KB physical sectors)
–
190
363
tBE
Block Erase Time (64KB physical sectors)
–
270
725
tCE
Chip Erase Time (S25FL128L)
–
70
180
tCE
Chip Erase Time (S25FL256L)
–
140
360
µs
ms
sec
Notes
111.Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V; 10,000 cycles; checkerboard data pattern.
112.The programming time for any OTP programming command is the same as tPP. This includes IRPP 2Fh, PASSP E8h and PDLRNV 43h.
113.For multiple bytes after firs byte within a page tBPN = tBP1 + tBP2 * N (typical and tBPN = tBP1 = tBP2 * N (max), where N = number of bytes programmed.
Table 65. Program or Erase Suspend AC Parameters
Parameter
Suspend Latency (tSL)
Typical
Max
–
40
100
–
Unit
µs
Resume to next Suspend (tRNS)
Document Number: 002-00124 Rev. *H
Comments
The time from Suspend command until the WIP
bit is 0.
Is the time needed to issue the next Suspend
command.
Page 146 of 160
S25FL256L/S25FL128L
13.
Ordering Information
13.1 Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S25FL
256
L
AG
M
F
I
00
1
Packing Type
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
00 = SOIC16 footprint (300 mil)
01 = SOIC8 (208 Mil) / 8-contact WSON footprint
02 = 5 5 ball BGA footprint
03 = 4 6 ball BGA footprint
Temperature Range / Grade
I = Industrial (–40°C to +85°C)
V = Industrial Plus (–40°C to +105°C)
A = Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
B = Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
M = Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
Package Materials[115]
F = Halogen-free, Lead (Pb)-free
H = Halogen free, Lead (Pb)-free
Package Type
M = 16-pin SOIC / 8-Lead SOIC
N = 8-contact WSON 6 8 mm / WSON 5 6 mm[114]
B = 24-ball BGA 6 8 mm package, 1.00 mm pitch
Speed
AG = 133 MHz
DP = 66 MHz DDR
Device Technology
L = 65 nm Floating Gate Process Technology
Density
128 = 128 Mb
256 = 256 Mb
Device Family
S25FL Cypress Memory 3.0 Volt-only, SPI Flash Memory
Note
114.WSON 6 8 mm is for S25FL256L only. WSON 5 6 mm is for S25FL128L only.
115.Halogen free definition is in accordance with IEC 61249-2-21 specification
Document Number: 002-00124 Rev. *H
Page 147 of 160
S25FL256L/S25FL128L
Valid Combinations — Standard
Valid Combinations list configurations planned to be supported in volume for this device. Contact your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Table 66. Valid Combinations — Standard
Valid Combinations — Standard
Base Ordering
Part Number
S25FL128L
S25FL256L
Speed
Option
Package and
Temperature
Model Number
Packing Type
AG
MFI, MFV
00
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
MFI, MFV
01
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
NFI, NFV
01
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
BHI, BHV
02, 03
0, 3
(Base) + A + (Temp) + H + (Model Number)
DP
MFI, MFV
00
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
MFI, MFV
01
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
NFI, NFV
01
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
BHI, BHV
02, 03
0, 3
(Base) + D + (Temp) + H + (Model Number)
AG
MFI, MFV
00
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
Package Marking
AG
NFI, NFV
01
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
BHI, BHV
02, 03
0, 3
(Base) + A + (Temp) + H + (Model Number)
DP
MFI, MFV
00
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
NFI, NFV
01
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
BHI, BHV
02, 03
0, 3
(Base) + D + (Temp) + H + (Model Number)
Document Number: 002-00124 Rev. *H
Page 148 of 160
S25FL256L/S25FL128L
Valid Combinations — Automotive Grade / AEC-Q100
Table 67 lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table
will be updated as new combinations are released. Contact your local sales representative to confirm availability of specific
combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/TS16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Table 67. Valid Combinations — Automotive Grade / AEC-Q100
Valid Combinations — Automotive Grade / AEC-Q100
Base Ordering
Part Number
S25FL128L
S25FL256L
Speed
Option
Package and
Temperature
Model Number
Packing Type
AG
MFA, MFB, MFM
00
0, 1, 3
Package Marking
(Base) + A + (Temp) + F + (Model Number)
AG
MFA, MFB, MFM
01
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
NFA, NFB, NFM
01
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
BHA, BHB, BHM
02, 03
0, 3
(Base) + A + (Temp) + H + (Model Number)
DP
MFA, MFB, MFM
00
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
MFA, MFB, MFM
01
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
NFA, NFB, NFM
01
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
BHA, BHB, BHM
02, 03
0, 3
(Base) + D + (Temp) + H + (Model Number)
AG
MFA, MFB, MFM
00
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
NFA, NFB, NFM
01
0, 1, 3
(Base) + A + (Temp) + F + (Model Number)
AG
BHA, BHB, BHM
02, 03
0, 3
(Base) + A + (Temp) + H + (Model Number)
DP
MFA, MFB, MFM
00
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
NFA, NFB, NFM
01
0, 1, 3
(Base) + D + (Temp) + F + (Model Number)
DP
BHA, BHB, BHM
02, 03
0, 3
(Base) + D + (Temp) + H + (Model Number)
Document Number: 002-00124 Rev. *H
Page 149 of 160
S25FL256L/S25FL128L
14.
Physical Diagrams
14.1 SOIC 16-Lead, 300-mil Body Width (SO3016)
0.20 C A-B
0.10 C D
2X
0.33 C
0.25 M
C A-B D
0.10 C
0.10 C
DIMENSIONS
SYMBOL
MIN.
NOTES:
NOM.
MAX.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2.65
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
A
2.35
-
A1
0.10
-
0.30
A2
2.05
-
2.55
b
0.31
-
0.51
b1
c
0.27
-
0.48
0.20
-
0.33
c1
0.20
-
0.30
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
L
1.27 BSC
0.40
-
L1
1.40 REF
L2
0.25 BSC
1.27
16
N
h
0.25
-
0
0°
-
8°
01
5°
-
15°
02
0°
-
-
Document Number: 002-00124 Rev. *H
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
0.75
Page 150 of 160
S25FL256L/S25FL128L
14.2 SOIC 8-Lead, 208 mil Body Width (SOC008)
NOTES:
DIMENSIONS
SYMBOL
NOM.
MAX.
1.75
-
2.16
A1
0.05
-
0.25
A2
1.70
-
1.90
b
0.36
-
0.48
b1
0.33
-
0.46
c
0.19
-
0.24
c1
0.15
-
0.20
A
MIN.
D
5.28 BSC
E
8.00 BSC
E1
5.28 BSC
e
1.27 BSC
L
-
0.51
L1
1.36 REF
L2
0.25 BSC
0.76
8
N
0
0°
-
8°
01
5°
-
15°
02
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
0-8° REF
Document Number: 002-00124 Rev. *H
Page 151 of 160
S25FL256L/S25FL128L
14.3 WSON 8-Contact 5 x 6 mm Leadless (WND008)
NOTES:
DIMENSIONS
SYMBOL
MIN.
e
MAX.
1.27 BSC.
8
N
ND
L
NOM.
4
0.60
0.55
1.
DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
4
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
N IS THE TOTAL NUMBER OF TERMINALS.
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
0.65
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
b
0.35
0.40
0.45
D2
3.90
4.00
4.10
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
E2
3.30
3.40
3.50
MAX. PACKAGE WARPAGE IS 0.05mm.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
D
5.00 BSC
6.
7.
E
6.00 BSC
0.75
0.02
8
9
A
A1
0.70
0.00
A3
0.20 REF
K
0.20 MIN.
Document Number: 002-00124 Rev. *H
0.80
0.05
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
SLUG AS WELL AS THE TERMINALS.
10
A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
Page 152 of 160
S25FL256L/S25FL128L
14.4 WSON 8-Contact 6 x 8 mm Leadless (WNG008)
NOTES:
DIMENSIONS
SYMBOL
MIN.
e
MAX.
1.27 BSC.
8
N
ND
L
NOM.
4
0.45
0.50
1.
DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
4
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
N IS THE TOTAL NUMBER OF TERMINALS.
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
0.55
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
b
0.35
0.40
0.45
D2
4.70
4.80
4.90
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
E2
4.55
4.65
4.75
MAX. PACKAGE WARPAGE IS 0.05mm.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
D
6.00 BSC
6.
7.
E
8.00 BSC
0.75
0.02
8
9
A
A1
0.70
0.00
A3
0.20 REF
K
0.20 MIN.
Document Number: 002-00124 Rev. *H
0.80
0.05
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
SLUG AS WELL AS THE TERMINALS.
10
A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
Page 153 of 160
S25FL256L/S25FL128L
14.5 Ball Grid Array 24-ball 6 x 8 mm (FAB024)
NOTES:
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
A
-
-
1.20
A1
0.20
-
-
1.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
D
8.00 BSC
E
6.00 BSC
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
D1
4.00 BSC
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
E1
4.00 BSC
MD
5
ME
5
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
24
b
0.35
0.40
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
PARALLEL TO DATUM C.
0.45
7
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
eE
1.00 BSC
eD
1.00 BSC
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
SD
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
SE
0.00 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
"SE" = eE/2.
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
Document Number: 002-00124 Rev. *H
Page 154 of 160
S25FL256L/S25FL128L
14.6 Ball Grid Array 24-ball 6 x 8 mm (FAC024)
NOTES:
DIMENSIONS
SYMBOL
MIN.
A
-
A1
0.25
NOM.
MAX.
1.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
-
1.20
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
-
-
3.
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
4.
e
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
8.00 BSC
D
E
6.00 BSC
D1
5.00 BSC
E1
3.00 BSC
MD
6
ME
4
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
24
b
eE
0.35
0.40
1.00 BSC
REPRESENTS THE SOLDER BALL GRID PITCH.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
PARALLEL TO DATUM C.
0.45
7
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
eD
1.00 BSC
SD
0.50 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
SE
0.50 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
"SE" = eE/2.
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
Document Number: 002-00124 Rev. *H
Page 155 of 160
S25FL256L/S25FL128L
15.
Other Resources
15.1 Glossary
BCD
Binary Coded Decimal. A value in which each 4 bit nibble represents a decimal numeral.
Command
All information transferred between the host system and memory during one period while CS# is low. This
includes the instruction (sometimes called an operation code or opcode) and any required address, mode bits,
latency cycles, or data.
DDP
Dual Die Package = Two die stacked within the same package to increase the memory capacity of a single
package. Often also referred to as a Multi-Chip Package (MCP).
DDR
Double Data Rate = When input and output are latched on every edge of SCK.
Flash
The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large blocks
of memory bits in parallel, making the erase operation much faster than early EEPROM.
High
A signal voltage level ≥ VIH or a logic level representing a binary one (“1”).
Instruction
The 8 bit code indicating the function to be performed by a command (sometimes called an operation code or
opcode). The instruction is always the first 8 bits transferred from host system to the memory in any command.
Low
A signal voltage level VIL or a logic level representing a binary zero (“0”).
LSb
Least Significant bit, with the lowest order of magnitude value, within a group of bits of a register or data value.
MSb
Most Significant bit, with the highest order of magnitude value, within a group of bits of a register or data value.
LSB
Least Significant Byte.
MSB
Most Significant Byte
N/A
Not Applicable. A value is not relevant to situation described.
Nonvolatile
No power is needed to maintain data stored in the memory.
OPN
Ordering Part Number = The alphanumeric string specifying the memory device type, density, package, factory
non-volatile configuration, etc. used to select the desired device.
QPI
Quad Peripheral Interface
Page
256 Byte length and aligned group of data.
PCB
Printed Circuit Board
Register Bit References
In the format: Register_name[bit_number] or Register_name[bit_range_MSb: bit_range_LSb]
Sector
Erase unit size; depending on device model and sector location this may be 4KBytes, 32KBytes or 64KBytes
SDR
Single Data Rate = When input is latched on the rising edge and output on the falling edge of SCK.
Write
An operation that changes data within volatile or non-volatile registers bits or non-volatile Flash memory. When
changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of
the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile
data is modified – as a single operation. The non-volatile data appears to the host system to be updated by the
single write command, without the need for separate commands for erase and reprogram of adjacent, but
unaffected data.
Document Number: 002-00124 Rev. *H
Page 156 of 160
S25FL256L/S25FL128L
15.2 Link to Cypress Flash Roadmap
www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap
15.3 Link to Software
www.cypress.com/software-and-drivers-cypress-flash-memory
15.4 Link to Application Notes
www.cypress.com/appnotes
Document Number: 002-00124 Rev. *H
Page 157 of 160
S25FL256L/S25FL128L
16. Document History
Document Title: S25FL256L/S25FL128L, 256-Mb (32-MB)/128-Mb (16-MB), 3.0 V FL-L Flash Memory
Document Number: 002-00124
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
4905743
BWHA
09/18/2015
Initial release.
02/22/2016
DC Characteristics – Industrial, Industrial Plus and Extended tables: changed ISB Max value
SDR AC Characteristics table: changed Min values for tCH and tCL
Embedded Algorithm Performance Tables: changed value for tPP Max
Registers: added sentences; When volatile register bits are written, only the volatile version of
the register has the appropriate bits updated.
When either a non-volatile or volatile register is read, the volatile version of the register is
delivered.
Basic SPI Flash Parameter, JEDEC SFDP Rev B: changed 3Dh Data from 60h to 50h
*A
5147318
BWHA
Description of Change
Restructured datasheet.
Added S25FL128L related information in all instances across the document.
Updated Section 9. Data Integrity on page 119:
Updated Section 9.1 Erase Endurance on page 119:
Updated Table 45.
*B
5322980
BWHA
06/25/2016
Updated Section 9.2 Data Retention on page 119:
Updated Table 46.
Updated Section 11. Electrical Specifications on page 130:
Added Section 11.3 Thermal Resistance on page 130.
Updated Section 15. Other Resources on page 156.
Added Section 15.2 Link to Cypress Flash Roadmap on page 157.
Changed status from Advance to Final.
Updated Features on page 1: Added Automotive Grade related information.
Updated Section 9. Data Integrity on page 119.
Updated Section 9.2 Data Retention on page 119.
Updated Table 46.
Updated Section 11. Electrical Specifications on page 130.
Updated Section 11.3 Thermal Resistance on page 130.
Updated Table 54.
Updated Section 11.4 Operating Ranges on page 131.
*C
5449210
ARVR
09/26/2016
Updated Section 11.4.2 Temperature Ranges on page 131: Added Automotive Grade related
information.
Updated Section 13. Ordering Information on page 147.
Updated Section 13.1 Ordering Part Number on page 147.
Updated details corresponding to “01” under “Model Number (Additional Ordering Options)”.
Added Automotive Grade related information.
Updated Section Valid Combinations — Standard on page 148.
Added Section Valid Combinations — Automotive Grade / AEC-Q100 on page 149.
Updated Section 14. Physical Diagrams on page 150.
WSON 8-contact 6 x 8 mm Leadless (WNH008).
Added Section 14.4 WSON 8-Contact 6 x 8 mm Leadless (WNG008) on page 153.
*D
5548451
ARVR
01/11/2017
Document Number: 002-00124 Rev. *H
Updated Sales information and Copyright.
Updated links in Section 15. Other Resources on page 156.
Page 158 of 160
S25FL256L/S25FL128L
Document Title: S25FL256L/S25FL128L, 256-Mb (32-MB)/128-Mb (16-MB), 3.0 V FL-L Flash Memory
Document Number: 002-00124
Rev.
*E
ECN No.
5677892
Orig. of
Change
ECAO
Submission
Date
05/15/2017
Description of Change
Changed VDD to VCC.
Added Table 37 on page 50
Updated SFDP parameter address byte 02h, Bit 22 description from “DOR” to “QOR” in Table 49
on page 122
Updated tSE value in Table 64 on page 146
Updated Package Material “F” option to “F = Halogen-free, Lead (Pb)-free” in Section 13.1
Ordering Part Number on page 147
Updated WSON 8-Contact 5 x 6 mm Leadless (WND008) on page 152
Updated WSON 8-Contact 6 x 8 mm Leadless (WNG008) on page 153
Updated Section Valid Combinations — Standard on page 148 for S25FL128L.
Added Section Valid Combinations — Automotive Grade / AEC-Q100 on page 149 for
S25FL128L.
Updated package diagram for Section 14.1 SOIC 16-Lead, 300-mil Body Width (SO3016)
on page 150 (spec 002-15547 Rev. ** to *A).
Updated Cypress logo, Sales page, and Copyright information.
Updated Section Features on page 1: Removed “S25FL256L”.
Updated Table 53: Corrected Latchup Max Spec.
*F
5846473
BWHA
08/07/2017
Updated Section 13.1 Ordering Part Number on page 147: Removed FL128L is not in
production.
Updated Table 66 and Table 67: Added SOIC 16 package for the FL128L.
Updated Section 12.5.3 DDR Data Valid Timing using DLP on page 145:
Updated Figure 22, Figure 23, Figure 74, Figure 75, and Figure 76.
*G
6085424
BWHA
04/03/2018
Updated Table 52 on page 129.
Updated Table 56 on page 134 - improved ICC and ISB current specifications.
Updated Table 57 on page 135 - improved ICC and ISB current specifications.
Updated Table 58 on page 136 - improved ICC and ISB current specifications.
Updated Sales page.
*H
6239780
BWHA
07/11/2018
Updated the Section 12.5.3 DDR Data Valid Timing using DLP on page 145 section.
Changed Low-halogen to Halogen free in Section 13. Ordering Information on page 147 and
added a Note” Halogen free definition is in accordance with IEC 61249-2-21 specification”.
Added to Section 6.6 Registers on page 25 section “Special attention must be given when
writing the non-volatile registers that there is a stable power supply with no disruption, this will
guarantee the correct data is written to the register. “
Updated Section 15.1 Glossary on page 148 Definition of MSb & LSb.
Document Number: 002-00124 Rev. *H
Page 159 of 160
S25FL256L/S25FL128L
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/arm
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cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
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cypress.com/mcu
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cypress.com/psoc
Power Management ICs
cypress.com/pmic
Touch Sensing
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
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USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-00124 Rev. *H
Revised July 11, 2018
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