ADVANCE
S25FL256L
256 Mbit (32 Mbyte)
3.0 V FL-L Flash Memory
Features
Serial Peripheral Interface (SPI) with Multi-I/O
20 Year Data Retention, typical
Security features
–
–
–
–
–
Clock polarity and phase modes 0 and 3
Double Data Rate (DDR) option
Quad peripheral Interface (QPI) option
Extended Addressing: 24- or 32-bit address options
Serial Command subset and footprint compatible with S25FL-A,
S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families
– Multi I/O Command subset and footprint compatible with S25FL-P,
S25FL-S and S25FS-S SPI families
–
–
–
–
Read
– Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR
Quad I/O.
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) for configuration
information.
Status and Configuration Register Protection
Four Security Regions of 256 bytes each outside the main Flash array
Legacy Block Protection: Block range
Individual and Region Protection
– Individual Block Lock: Volatile individual Sector/Block
– Pointer Region: Non-Volatile Sector/Block range
– Power Supply Lock-down, Password, or Permanent protection of
Security Regions 2 and 3 and Pointer Region
Technology
– 65 nm Floating Gate Technology
Single Supply Voltage with CMOS I/O
– 2.7 V to 3.6 V
Temperature Range
Program Architecture
– Industrial (–40°C to +85°C)
– Industrial Plus (–40°C to +105°C)
– Extended (–40°C to +125°C)
– 256 Bytes Page Programming buffer3.0 V FL-L Flash Memory
– Program suspend and resume
Erase Architecture
Packages (all Pb-free)
– Uniform 4KB Sector Erase
– Uniform 32KB Half Block Erase
– Uniform 64KB Block Erase
– Chip erase
– Erase suspend and resume
100,000 Program-Erase Cycles, min
– WSON 6 8 mm (WNH008)
– 16-pin SOIC 300 mil (SO3016)
– BGA-24 6 8 mm
– 5 5 ball (FAB024) footprint
– 4 6 ball (FAC024) footprint
Block Diagram
X Decoders
CS#
SCK
SI/IO0
SO/IO1
Memory Array
Y Decoders
I/O
Data Latch
WP#/IO2
Control
Logic
RESET#/IO3
Data Path
RESET#
Cypress Semiconductor Corporation
Document Number: 002-00124 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 22, 2016
ADVANCE
S25FL256L
Performance Summary
Maximum Read Rates SDR
Clock Rate (MHz)
MBps
Read
Command
50
6.25
Fast Read
133
16.5
Dual Read
133
33
Quad Read
133
66
Clock Rate (MHz)
MBps
66
66
Maximum Read Rates DDR
Command
DDR Quad Read
Typical Program and Erase Rates
Operation
KBytes/s
Page Programming
854
4 KBytes Sector Erase
80
32 KBytes Half Block Erase
168
64 KBytes Block Erase
237
Typical Current Consumption, –40°C to +85°C
Typical Current
Unit
Fast Read 5MHz
Operation
10
mA
Fast Read 10 MHz
10
mA
Fast Read 20 MHz
10
mA
Fast Read 50 MHz
15
mA
Fast Read 108 MHz
25
mA
Fast Read 133 MHz
30
mA
Quad I/O / QPI Read 108 MHz
25
mA
Quad I/O / QPI Read 133 MHz
30
mA
Quad I/O / QPI DDR Read 33MHz
15
mA
Quad I/O / QPI DDR Read 66MHz
30
mA
Program
40
mA
Erase
40
mA
Standby SPI
20
µA
Standby QPI
60
µA
Deep Power Down
2
µA
Document Number: 002-00124 Rev. *A
Page 2 of 145
ADVANCE
S25FL256L
Contents
Features................................................................................. 1
Block Diagram....................................................................... 1
Performance Summary ....................................................... 2
1.
1.1
1.2
FL-L Family Overview .................................................. 4
General Description ....................................................... 4
Migration Notes.............................................................. 5
Hardware Interface
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
Signal Descriptions .....................................................
Input/Output Summary...................................................
Multiple Input / Output (MIO)..........................................
Serial Clock (SCK) .........................................................
Chip Select (CS#) ..........................................................
Serial Input (SI) / IO0 .....................................................
Serial Output (SO) / IO1.................................................
Write Protect (WP#) / IO2 ..............................................
IO3 / RESET# ................................................................
RESET# .........................................................................
Voltage Supply (VDD).....................................................
Supply and Signal Ground (VSS) ...................................
Not Connected (NC) ......................................................
Reserved for Future Use (RFU).....................................
Do Not Use (DNU) .........................................................
System Block Diagrams.................................................
6
6
7
7
7
7
7
7
8
8
8
8
8
9
9
9
3.
3.1
3.2
3.3
3.4
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Data Protection ............................................................
11
11
12
17
21
4.
4.1
4.2
4.3
4.4
4.5
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Latchup Characteristics ...............................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
22
22
22
23
24
26
5.
5.1
5.2
5.3
5.4
5.5
5.6
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics ..............................................
Embedded Algorithm Performance Tables ..................
29
29
29
30
33
36
38
6.
6.1
6.2
Physical Interface ...................................................... 39
Connection Diagrams .................................................. 39
Physical Diagrams ....................................................... 42
7.4
7.5
7.6
JEDEC JESD216 Serial Flash
Discoverable Parameters (SFDP) Space ..................... 47
Security Regions Address Space ................................. 47
Registers....................................................................... 48
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Data Protection ........................................................... 62
Security Regions........................................................... 62
Deep Power Down ........................................................ 63
Write Enable Commands .............................................. 63
Write Protect Signal ...................................................... 64
Status Register Protect (SRP1, SRP0)......................... 64
Array Protection ............................................................ 65
Individual and Region Protection .................................. 70
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Commands .................................................................. 75
Command Set Summary............................................... 75
Identification Commands .............................................. 81
Register Access Commands......................................... 84
Read Memory Array Commands .................................. 97
Program Flash Array Commands ............................... 106
Erase Flash Array Commands.................................... 108
Security Regions Array Commands............................ 115
Individual Block Lock Commands ............................... 117
Pointer Region Command........................................... 121
Individual and Region Protection
(IRP) Commands ........................................................ 122
9.11 Reset Commands ....................................................... 127
9.12 Deep Power Down Commands................................... 128
10. Data Integrity ............................................................. 131
10.1 Endurance .................................................................. 131
10.2 Data Retention ............................................................ 131
11. Software Interface Reference .................................. 132
11.1 JEDEC JESD216B Serial Flash
Discoverable Parameters............................................ 132
11.2 Device ID Address Map .............................................. 140
11.3 Initial Delivery State .................................................... 140
12. Ordering Information ................................................ 141
12.1 Ordering Part Number................................................. 141
Glossary
13.
Document History..................................................... 144
Software Interface
7.
7.1
7.2
7.3
Address Space Maps.................................................
Overview ......................................................................
Flash Memory Array.....................................................
ID Address Space ........................................................
Document Number: 002-00124 Rev. *A
46
46
46
47
Page 3 of 145
ADVANCE
S25FL256L
1. FL-L Family Overview
1.1
General Description
The Cypress FL-L Family devices are Flash non-volatile memory products using:
Floating Gate technology
65 nm process lithography
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides
individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match
or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,
executing code directly (XIP), and storing re-programmable data.
Document Number: 002-00124 Rev. *A
Page 4 of 145
ADVANCE
1.2
S25FL256L
Migration Notes
1.2.1
Features Comparison
The FL-L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families.
Table 1.1 Cypress SPI Families Comparison
Parameter
FL-L
Technology Node
Architecture
65nm
90nm
90nm
MirrorBit® Eclipse™
Floating Gate
MirrorBit®
In Production
In Production
In Production
128Mb - 1Gb
4Mb - 64Mb
32Mb - 256Mb
256Mb
Bus Width
Fast Read Speed
FL-P
65nm
Density
Normal Read Speed
FL1-K
Floating Gate
Release Date
Supply Voltage
FL-S
x1, x2, x4
x1, x2, x4
x1, x2, x4
x1, x2, x4
2.7 V - 3.6 V
2.7 V - 3.6 V / 1.65 V - 3.6 V VIO
2.7 V - 3.6 V
2.7 V - 3.6 V
6MB/s (50MHz)
6MB/s (50MHz)
6MB/s (50MHz)
5MB/s (40MHz)
16.5MB/s (133MHz)
17MB/s (133MHz)
13MB/s (108MHz)
13MB/s (104MHz)
Dual Read Speed
33MB/s (133MHz)
26MB/s (104MHz)
26MB/s (108MHz)
20MB/s (80MHz)
Quad Read Speed
66MB/s (133MHz)
52MB/s (104MHz)
52MB/s (108MHz)
40MB/s (80MHz)
Quad Read Speed (DDR)
66MB/s (66MHz)
80MB/s (80MHz)
–
–
256B
256B / 512B
256B
256B
4KB / 32KB / 64KB
64KB / 256KB
4KB / 64KB
64KB / 256KB
-
4KB (option)
–
4KB
500 KB/s
136 KB/s (4KB)
437 KB/s (64KB)
130 KB/s
854KB/s (256B)
1.2 MB/s (256B)
1.5 MB/s (512B)
365 KB/s
170 KB/s
1024B
1024B
768B (3 256B)
506B
Yes
Yes
No
No
Program Buffer Size
Erase Sector/Block Size
Parameter Sector Size
80 KB/s (4KB)
Sector / Block Erase Rate (typ.)
168 KB/s (32KB
237KB/s (64KB)
Page Programming Rate (typ.)
Security Region / OTP
Individual and Region Protection or
Advanced Sector Protection
Erase Suspend/Resume
Yes
Yes
Yes
No
Program Suspend/Resume
Yes
Yes
Yes
No
–40°C to +85°C
Operating Temperature
–40°C to +105°C
40°C to +125°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
Notes:
Refer to individual data sheets for further details.
Document Number: 002-00124 Rev. *A
Page 5 of 145
ADVANCE
S25FL256L
Hardware Interface
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large
number of signal connections and larger package size. The large number of connections increase power consumption due to so
many signals switching and the larger package increases cost.
The FL-L family reduces the number of signals for connection to the host system by serially transferring all control, address, and
data information over 6 signals. This reduces the cost of the memory package, reduces signal switching power, and either reduces
the host connection count or frees host connectors for use in providing other features.
The FL-L family uses the industry standard single bit SPI and also supports optional extension commands for two bit (Dual) and four
bit (Quad) wide serial transfers. This multiple width interface is called SPI Multi-I/O or SPI-MIO.
2. Signal Descriptions
2.1
Input/Output Summary
Table 2.1 Signal List
Signal Name
Type
Description
RESET#
Input
Hardware Reset: Low = device resets and returns to standby state, ready to receive a command. The signal has an
internal pull-up resistor and may be left unconnected in the host system if not used.
SCK
Input
Serial Clock
CS#
Input
Chip Select
SI / IO0
I/O
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1
I/O
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
Write Protect when not in Quad mode (CR1V[1] = 0 and SR1NV[7] = 1).
IO2 when in Quad mode (CR1V[1] = 1).
WP# / IO2
I/O
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad
commands or write protection. If write protection is enabled by SR1NV[7] = 1 and CR1V[1] = 0, the host system is
required to drive WP# high or low during a WRR or WRAR command.
IO3 in Quad-I/O mode, when Configuration Register-1 QUAD bit, CR1V[1] =1, or in QPI mode, when Configuration
Register-2 QPI bit, CR2V[3] =1 and CS# is low.
IO3 / RESET#
I/O
RESET# when enabled by CR2V[7]=1 and not in Quad-I/O mode, CR1V[1] = 0, or when enabled in quad mode,
CR1V[1] = 1 and CS# is high.
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad
commands or RESET#.
VDD
Supply
Power Supply.
VSS
Supply
Ground.
NC
Unused
Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use
the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board
(PCB). However, any signal connected to an NC must not have voltage levels higher than VDD.
RFU
Reserved for Future Use. No device internal signal is currently connected to the package connector but there is
Reserved potential future use of the connector for a signal. It is recommended to not use RFU connectors for PCB routing
channels so that the PCB may take advantage of future enhanced features in compatible footprint devices.
DNU
Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by
Cypress for test or other purposes and is not intended for connection to any host system signal. Any DNU signal
Reserved related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels.
Do not connect any host system signal to this connection.
Notes
1. Inputs with internal pull-ups or pull-downs drive less than 2 A. Only during power-up is the current larger at 150 A for 4 S. Resistance of pull-ups or pull-down
resistors with the typical process at Vcc = 3.3 V at –40°C is ~4.5 M and at 90°C is ~6.6 M.
Document Number: 002-00124 Rev. *A
Page 6 of 145
ADVANCE
2.2
S25FL256L
Multiple Input / Output (MIO)
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the Serial Input (SI)
signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI/IO0 signal. Address or data is sent from
the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host
similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
QPI mode transfers all instructions, addresses, and data from the host to the memory as four bit (nibble) groups on IO0, IO1, IO2,
and IO3. Data is returned to the host similarly as four bit (nibble) groups on IO0, IO1, IO2, and IO3.
2.3
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on
the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR commands.
2.4
Chip Select (CS#)
The chip select signal indicates when a command is transferring information to or from the device and the other signals are relevant
for the memory device.
When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are
high impedance. The device will be in the Standby Power mode, unless an internal embedded operation is in progress. An
embedded operation is indicated by the Status Register-1 Write-In-Progress bit (SR1V[0]) set to 1, until the operation is completed.
Some example embedded operations are: Program, Erase, or Write Registers (WRR) operations.
Driving the CS# input to the logic low state enables the device, placing it in the Active Power mode. After Power-up, a falling edge on
CS# is required prior to the start of any command.
2.5
Serial Input (SI) / IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed.
Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 - an input and output during Dual and Quad
commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock
signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
2.6
Serial Output (SO) / IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock
signal. SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be
programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK in
SDR commands, and on every edge of SCK, in DDR commands).
2.7
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), when the Status Register Protect 0 (SRP0_NV) or (SRP0) bit of Status Register-1 (SR1NV[7]) or
(SR1V[7]) is set to a 1, it is not possible to write to Status Registers, Configuration Registers or DLR registers. In this situation, the
command selecting SR1NV, SR1V, CR1NV,CR1V, CR2NV, CR2V, CR3NV, DLRNV and DLRV is ignored, and no error is set.
This prevents any alteration of the Legacy Block Protection settings. As a consequence, all the data bytes in the memory area that
are protected by the Legacy Block Protection feature are also hardware protected against data modification if WP# is Low during
commands changing Status Registers, Configuration Registers or DLR registers, with SRP0_NV set to 1. Similarly, the Security
Region Lock Bits (LB3-LB0) are protected against programming.
The WP# function is not available when the Quad mode is enabled (CR1V[1]=1) or QPI mode is enabled (CR2V[3]=1). The WP#
function is replaced by IO2 for input and output during Quad mode or QPI mode is enabled (CR2V[3]=1) for receiving addresses,
and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data on the falling edge of
SCK, in SDR commands, and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host system if not
used for Quad mode or QPI mode or protection.
Document Number: 002-00124 Rev. *A
Page 7 of 145
ADVANCE
2.8
S25FL256L
IO3 / RESET#
IO3 is used for input and output during Quad mode (CR1V[1]=1) or QPI mode is enabled (CR2V[3]=1) for receiving addresses, and
data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK,
in SDR commands, and on every edge of SCK, in DDR commands).
The IO3 / RESET# input may also be used to initiate the hardware reset function when the IO3 / RESET# feature is enabled by
writing Configuration Register-2 non-volatile bit 7 (CR2NV[7]=1). The input is only treated as RESET# when the device is not in
Quad modes (114,144,444), CR1V[1] = 0, or when CS# is high. When Quad modes are in use, CR1V[1]=1or QPI mode is enabled
(CR2V[3]=1), and the device is selected with CS# low, the IO3 / RESET# is used only as IO3 for information transfer. When CS# is
high, the IO3 / RESET# is not in use for information transfer and is used as the reset input. By conditioning the reset operation on
CS# high during Quad modes (114,144,444), the reset function remains available during Quad modes (114,144,444).
When the system enters a reset condition, the CS# signal must be driven high as part of the reset process and the IO3 / RESET#
signal is driven low. When CS# goes high the IO3 / RESET# input transitions from being IO3 to being the reset input. The reset
condition is then detected when CS# remains high and the IO3 / RESET# signal remains low for tRP. If a reset is not intended, the
system is required to actively drive IO3 / RESET# to high along with CS# being driven high at the end of a transfer of data to the
memory. Following transfers of data to the host system, the memory will drive IO3 high during tCS. This will ensure that IO3 /
RESET# is not left floating or being pulled slowly to high by the internal or an external passive pull-up. Thus, an unintended reset is
not triggered by the IO3 / RESET# not being recognized as high before the end of tRP.
The IO3 / RESET# input reset feature is disabled when (CR2V[7]=0).
The IO3 / RESET# input has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode
or the reset function. The internal pull-up will hold IO3 / RESET# high after the host system has actively driven the signal high and
then stops driving the signal.
Note that IO3 / RESET# input cannot be shared by more than one SPI-MIO memory if any of them are operating in Quad I/O mode
as IO3 being driven to or from one selected memory may look like a reset signal to a second non-selected memory sharing the same
IO3 / RESET# signal.
2.9
RESET#
The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a command. When
RESET# is driven to logic low (VIL) for at least a period of tRP, the device starts the hardware reset process.
RESET# causes the same initialization process as is performed when power comes up and requires tPU time.
RESET# may be asserted low at any time. To ensure data integrity any operation that was interrupted by a hardware reset should
be reinitiated once the device is ready to accept a command sequence.
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used. The internal pull-up will hold
Reset high after the host system has actively driven the signal high and then stops driving the signal.
The RESET# input is not available on all packages options. When not available the RESET# input of the device is tied to the inactive
state.
2.10
Voltage Supply (VDD)
VDD is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read,
program, and erase.
2.11
Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.
2.12
Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The
connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).
Document Number: 002-00124 Rev. *A
Page 8 of 145
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2.13
S25FL256L
Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but there is potential future use of the connector. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced
features in compatible footprint devices.
2.14
Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other
purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the
signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.
Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
2.15
System Block Diagrams
Figure 2.1 Bus Master and Memory Devices on the SPI Bus - Single Bit Data Path
RESET#
WP#
RESET#
WP#
SI
SO
SCK
SI
SO
SCK
CS2#
CS1#
CS#
CS#
SPI
Bus Master
SPI Flash
SPI Flash
Figure 2.2 Bus Master and Memory Devices on the SPI Bus - Dual Bit Data Path
RESET#
WP#
RESET#
WP#
IO1
IO0
SCK
IO1
IO0
SCK
CS2#
CS1#
SPI
Bus Master
Document Number: 002-00124 Rev. *A
CS#
CS#
SPI Flash
SPI Flash
Page 9 of 145
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S25FL256L
Figure 2.3 Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path - Separate RESET#
RESET#
IO3
IO2
IO1
IO0
SCK
RESET#
IO3
IO2
IO1
IO0
SCK
CS2#
CS1#
SPI
Bus Master
CS#
CS#
SPI Flash
SPI Flash
Figure 2.4 Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path - I/O3 / RESET#
IO3 / RESET#
IO2
IO1
IO0
SCK
CS#
SPI
Bus Master
Document Number: 002-00124 Rev. *A
IO3 / RESET#
IO2
IO1
IO0
SCK
CS#
SPI Flash
Page 10 of 145
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3.
S25FL256L
Signal Protocols
3.1
SPI Clock Modes
3.1.1
Single Data Rate (SDR)
The FL-L family can be driven by an embedded micro-controller (bus master) in either of the two following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is
always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data.
SCK will stay at logic low state with CPOL = 0, CPHA = 0
SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 3.1 SPI SDR Modes Supported
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
SI_IO0
MSB
SO_IO1
MSB
Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by showing SCK as both
high and low at the fall of CS#. In some cases a timing diagram may show only mode 0 with SCK low at the fall of CS#. In such a
case, mode 3 timing simply means clock is high at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of
CS# is needed for mode 3.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode 0 the beginning of the
first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low
at the beginning of a command.
3.1.2
Double Data Rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always latched on the rising
edge of clock, the same as in SDR commands. However, the address and input data that follow the instruction are latched on both
the rising and falling edges of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end
of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the next falling edge of
SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge
of SCK because SCK is already low at the beginning of a command.
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S25FL256L
Figure 3.2 SPI DDR Modes Supported
CPOL=0_CPHA=0_SCLK
CPOL=1_CPHA=1_SCLK
CS#
Transfer_Phase
IO0
3.2
Instruction
Inst. 7
Address
Inst. 0
Mode
Dummy / DLP
A28 A24
A0 M4 M0
DLP.
DLP.
D0 D1
IO1
A29 A25
A1 M5 M1
DLP.
DLP.
D0 D1
IO2
A30 A26
A2 M6 M2
DLP.
DLP.
D0 D1
IO3
A31 A27
A3 M7 M3
DLP.
DLP.
D0 D1
Command Protocol
All communication between the host system and FL-L family memory devices is in the form of units called commands. See
Section 9., Commands on page 75 for definition and details for all commands.
All commands begin with an 8-bit instruction that selects the type of information transfer or device operation to be performed.
Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the
memory. All instruction, address, and data information is transferred sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three
command phases:
instruction;
address and instruction modifier (continuous read mode bits);
data.
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI signal. Data may be
sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol for single bit width instruction, single
bit width address and modifier, single bit data.
Dual-O or Quad-O commands provide an address sent from the host as serial on SI (IO0) then followed by dummy cycles. Data is
returned to the host as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-1-2 for
Dual-O and 1-1-4 for Quad-O command protocols.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)
groups on IO0, IO1, IO2, and IO3 then followed by dummy cycles. Data is returned to the host similarly as bit pairs on IO0 and IO1
or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command
protocols.
The FL-L family also supports a QPI mode in which all information is transferred in 4-bit width, including the instruction, address,
modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host
driving the Chip Select (CS#) signal low throughout a command.
The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
Each command begins with an eight bit (byte) instruction. The instruction selects the type of information transfer or device
operation to be performed. The instruction transfers occur on SCK rising edges. However, some read commands are
modified by a prior read command, such that the instruction is implied from the earlier command. This is called Continuous
Read Mode. When the device is in continuous read mode, the instruction bits are not transmitted at the beginning of the
command because the instruction is the same as the read command that initiated the Continuous Read Mode. In
Continuous Read mode the command will begin with the read address. Thus, Continuous Read Mode removes eight
instruction bits from each read command in a series of same type read commands.
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The instruction may be stand alone or may be followed by address bits to select a location within one of several address
spaces in the device. The instruction determines the address space used. The address may be either a 24 bit or a 32 bit,
byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in
DDR commands.
In legacy SPI mode, the width of all transfers following the instruction are determined by the instruction sent. Following
transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit
groups per (dual) transfer on the IO0 and IO1 signals, or they may be done in 4 bit groups per (quad) transfer on the IO0IO3 signals. Within the dual or quad groups the least significant bit is on IO0. More significant bits are placed in significance
order on each higher numbered IO signal. Single bits or parallel bit groups are transferred in most to least significant bit
order.
In QPI mode, the width of all transfers is a 4-bit wide (quad) transfer on the IO0-IO3 signals.
Dual and Quad I/O read instructions send an instruction modifier called Continuous Read mode bits, following the address,
to indicate whether the next command will be of the same type with an implied, rather than an explicit, instruction. These
mode bits initiate or end the continuous read mode. In continuous read mode, the next command thus does not provide an
instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same
command type is repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR
commands, or on every SCK edge, in DDR commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period
before read data is returned to the host.
Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles (also
referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on
SCK falling edge at the end of the last read latency cycle. The first read data bits are considered transferred to the host on
the following SCK rising edge. Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every
SCK edge, in DDR commands.
If the command returns read data to the host, the device continues sending data transfers until the host takes the CS#
signal high. The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the
command.
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go high after
the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be
driven high when the number of bits after the CS# signal was driven low is an exact multiple of eight bits. If the CS# signal
does not go high exactly at the eight bit boundary of the instruction or write data, the command is rejected and not
executed.
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first. The data bits are
shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address byte sent first.
Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored.
The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during
an embedded operation. These are discussed in the individual command descriptions.
Depending on the command, the time for execution varies. A command to read status information from an executing
command is available to determine when the command completes execution and whether the command was successful.
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3.2.1
S25FL256L
Command Sequence Examples
Figure 3.3 Stand Alone Instruction Command
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1-IO3
Phase
Instruction
Figure 3.4 Single Bit Wide Input Command
CS#
SCLK
SO_IO1-IO3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
Figure 3.5 Single Bit Wide Output Command without latency
CS#
SCLK
SI
7
6
5
4
3
2
1
0
SO
7
Phase
6
5
Instruction
4
3
2
1
0
7
6
5
4
Data 1
3
2
1
0
1
0
Data 2
Figure 3.6 Single Bit Wide I/O Command with latency
CS#
SCLK
SI
7
6
5
4
3
2
1
0 31
1
0
SO
7
Phase
Instruction
Address
6
5
Dummy Cycles
4
3
2
Data 1
Figure 3.7 Dual Output Read Command
CS#
SCK
IO0
7
6
5
4
3
2
1
0
31
1
0
IO1
Phase
Instruction
Document Number: 002-00124 Rev. *A
Address
Dummy Cycles
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
Data 1
Data 2
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Figure 3.8 Quad Output Read Command
CS#
SCK
IO0
7
6
5 4
4 0
4
0 4
0
4 0
4
0 4
IO1
5 1
5
1 5
1
5 1
5
1
5
IO2
6 2
6
2 6
2
6 2
6
2
6
IO3
7 3
7
3 7
3
7 3
7
3
7
Phase
3
2 1
0 31
Instruction
1
0
Address
Dummy
D1
D2
D3
D4
D5
Figure 3.9 Dual I/O Command
CS#
SCK
IO0
7
6
5
4
3
2
1
0
IO1
Phase
30
2
0
6
4
2
0
6
4
2
0
6
4
2
0
31
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Instruction
Address
Mode
Dum
Data 1
Data 2
Figure 3.10 Quad I/O Command
CS#
SCLK
IO0
7
6
5
0 28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
4
3
2
1
Instruction
Address Mode
Dummy
D1
D2
D3
D4
Note: The gray bits are optional, the host does not have to drive bits during that cycle.
Figure 3.11 Quad I/O Read Command in QPI Mode
CS#
SCLK
IO0
4
0
28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Note: The gray bits are optional, the host does not have to drive bits during that cycle.
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Figure 3.12 DDR Quad I/O Read Command
CS#
SCLK
IO0
7
6
5
0 2824201612 8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
2925211713 9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
302622181410 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
312723191511 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
Phase
4
3
2
1
Instruction
Address
Mode
Dummy
DLP
D1 D2
Note:
1. The gray bits are optional, the host does not have to drive bits during that cycle.
Figure 3.13 DDR Quad I/O Read Command QPI Mode
CS#
SCLK
IO0
4
0
28 24 20 16 12 8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
5
1
29 25 21 17 13 9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
6
2
30 26 22 18 14 10 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
7
3
31 27 23 19 15 11 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
Phase
Instruct.
Address
Mode
Dummy
DLP
D1
D2
Note:
1. The gray bits are optional, the host does not have to drive bits during that cycle.
Additional sequence diagrams, specific to each command, are provided in section 9., Commands on page 75.
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3.3
S25FL256L
Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3.1 Interface States Summary
Interface State
VDD
SCK
CS#
RESET#
IO3 /
RESET#
WP# /
IO2
SO / IO1
SI / IO0
Power-Off
133 MHz SDR, or 66MHz DDR is not supported by this family of devices.
2. The Dual I/O, Quad I/O, QPI, DDR Quad I/O, and DDR QPI command protocols include Continuous Read Mode bits following the address. The clock cycles for these
bits are not counted as part of the latency cycles shown in the table. Example: the legacy Quad I/O command has 2 Continuous Read Mode cycles following the
address. Therefore, the legacy Quad I/O command without additional read latency is supported only up to the frequency shown in the table for a read latency of 0
cycles. By increasing the variable read latency the frequency of the Quad I/O command can be increased to allow operation up to the maximum supported 133 MHz
frequency and QPI maximum supported 133 MHz.
3. Other commands have fixed latency, e.g. Read always has zero read latency, Read Unique ID has 32 dummy cycles and release from Deep Power-Down has 24
dummy cycles.
7.6.4.2
Configuration Register 3 Volatile (CR3V)
Related Commands: Read Configuration 3 (RDCR3 33h), Write Enable for Volatile (WRENV 50h), Write Registers (WRR 01h),
Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), Set Burst Length (SBL 77h). This is the register displayed by the
RDCR3 command.
Table 7.18 Configuration Register 3 Volatile (CR3V)
Bits
Field Name
Function
7
RFU
Reserved
Type
Default
State
Reserved for Future Use
6
WL
Wrap Length
WE
Wrap Enable
RL
Read Latency
00 = 8-byte wrap
01 = 16 byte wrap
10 = 32 byte wrap
11 = 64 byte wrap
5
4
Description
Volatile
CR3NV
0 = Wrap Enabled
1 = Wrap Disabled
3
2
1
0 to 15 latency (dummy) cycles following read address or continuous
mode bits.
0
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Wrap Length CR3V[6:5]: These bits controls the wrapped read length and alignment during normal operation. These volatile
configuration bits enable the user to adjust the burst wrapped read length during normal operation.
Wrap Enable CR3V[4]: This bit controls the burst wrap feature. This volatile configuration bit enables the device to enter and exit
burst wrapped read mode during normal operation.
When CR3V[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed.
When CR3V[4]=0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes is read starting at the
byte address provided by the read command and wrapping around at the group alignment boundary.
Read Latency CR3V[3:0]: These bits set the read latency (dummy cycle) delay in variable latency read commands. These volatile
configuration bits enable the user to adjust the read latency during normal operation to optimize the latency for different commands
or, at different operating frequencies, as needed.
7.6.5
Individual and Region Protection Register (IRP)
Related Commands: IRP Read (IRPRD 2Bh) and IRP Program (IRPP 2Fh), Read Any Register (RDAR 65h), Write Any Register
(WRAR 71h).
The IRP register is a 16 bit OTP memory location used to permanently configure the behavior of Individual and Region Protection
(IRP) features. IRP does not have user programmable volatile bits, all defined bits are OTP.
The default state of the IRP bits are programmed by Cypress.
Table 7.19 IRP Register (IRP)
Bits
Field Name
Function
Type
Default
State
15 to 7
RFU
Reserved
OTP
All bits are
1
SECRRP
Security Region 3
Read Password
Mode Enable Bit
OTP
1
RFU
Reserved
OTP
1
Reserved for Future Use
0 = All individual IBL bits are set to “1” at power-up in the unprotected state
1 = All individual IBL bits are set to “0” at power-up in the protected state
IRP[4] is programmable if IRP[2:0]= “111”
6
5
4
3
IBLLBB
0
Reserved for Future Use
0 = Security Region 3 Read password mode selected
1 = Security Region 3 Read Password not selected
IRP[6] is programmable if IRP[2:0]= “111”
IBL Lock Boot Bit
OTP
1
RFU
Reserved
OTP
1
Reserved for Future Use
PWDMLB
Password Protection
Mode Lock Bit
OTP
1
0 = Password Protection Mode permanently enabled.
1 = Password Protection Mode not permanently enabled.
IRP[2] is programmable if IRP[2:0]= “111”
Power Supply Lockdown protection
Mode Lock Bit
OTP
1
0 = Power Supply Lock-down protection Mode permanently enabled.
1 = Power Supply Lock-down protection Mode not permanently enabled.
IRP[1] is programmable if this is enabled by IRP[2:0]= “111”
Permanent Protection
Lock Bit
OTP
1
0 = Permanent Protection Mode permanently enabled.
1 = Permanent Protection Mode not permanently enabled.
IRP[0] is programmable if IRP[2:0]= “111”
2
1
Description
PSLMLB
PERMLB
Security Regions Read Password Mode Enable (SECRRP) IRP[6]: When programmed to “0”, SECRRP enables the Security
Region 3 read password mode when PWDMLB bit IRP[2] is program at same time or later. The SECRRP bit can only be
programmed when IRP[2:0] = “111”, if not programming will fail with P_ERR set to 1. See Section 8.7.4, Security Region Read
Password Protection on page 74.
IBL Lock Boot Bit (IBLLBB) IRP[4]: The default state is 1, all individual IBL bits are set to “0” in the protected state, following
power-up, hardware reset, or software reset. In order to Program or Erase the Array the Global IBL Unlock or the Sector / Block IBL
Unlock command must be given before the Program or Erase commands. When programmed to 0, all the individual IBL bits are in
the un-protected state following power-up, hardware reset, or software reset. The IBLLBB bit can only be programmed when
IRP[2:0] = “111”, if not programming will fail with P_ERR set to “1”. See Section 8.6.2, Individual Block Lock (IBL) Protection
on page 68.
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Password Protection Mode Lock Bit (PWDMLB) IRP[2]: When programmed to “0”, the Password Protection Mode is permanently
selected to protect the Security Regions 2 and 3 and Pointer Region. The PWDMLB bit can only be programmed when IRP[2:0] =
“111”, if not programming will fail with P_ERR set to 1. See Section 8.7.3, Password Protection Mode on page 73.
After the Password protection mode is selected by programming IRP[2] = “0”, the state of all IRP bits are locked and permanently
protected from further programming. Attempting to program any IRP bits will result in a programming error with P_ERR set to 1.
The Password must be programmed and verified, before the Password Mode (IRP[2]=0) is set.
Power Supply Lock-down protection Mode Lock Bit (PSLMLB) IRP[1]: When programmed to 0, the Power Supply Lock-down
protection Mode is permanently selected. The PSLMLB bit can only be programmed when IRP[2:0] = “111”, if not programming will
fail with P_ERR set to “1”.
After the Power Supply Lock-down protection mode is selected by programming IRP[1] = 0”, the state of all IRP bits are locked and
permanently protected from further programming. Attempting to program any IRP bits will result in a programming error with P_ERR
set to “1”. See Section 8.7.1, IRP Register on page 72
Permanent Protection Lock Bit (PERMLB) IRP[0]: When programmed to 0, the Permanent Protection Lock Bit permanently
protects the Pointer Region and Security Regions 2 and 3, This bit provides a simple way to permanently protect the Pointer Region
and Security Regions 2 and 3 without the use of a password or the PRL command. See Section 8.7.1, IRP Register on page 72
PWDMLB (IRP[2]), PSLMLB (IRP[1]) and PERMLB(IRP[0]) are mutually exclusive, only one may be programmed to zero. IRP bits
may only be programmed while IRP[2:0] = “111”. Attempting to program IRP bits when IRP[2:0] is not = “111” will result in a
programming error with P_ERR set to “1”. The IRP protection mode should be selected during system configuration to ensure that a
malicious program does not select an undesired protection mode at a later time. By locking all the protection configuration via the
IRP mode selection, later alteration of the protection methods by malicious programs is prevented.
7.6.6
Password Register (PASS)
Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h), Read Any Register (RDAR 65h), Write
Any Register (WRAR 71h). The PASS register is a 64 bit OTP memory location used to permanently define a password for the
Individual and Region Protection (IRP) feature. PASS does not have user programmable volatile bits, all defined bits are OTP. A
volatile copy of PASS is used to satisfy read latency requirements but the volatile register is not user writable or further described.
The Password can not be read or programmed after IRP[2] is programmed to “0”. See Table 7.19, IRP Register (IRP) on page 58.
Table 7.20 Password Register (PASS)
Bits
Field
Name
Function
Type
Default State
63 to 0
PWD
Hidden
Password
OTP
FFFFFFFFFFFFFFFFh
7.6.7
Description
Non-volatile OTP storage of 64 bit password. The password is no longer readable after the
password protection mode is selected by programming IRP register bit 2 to zero.
Protection Register (PR)
Related Commands: Protection Register Read (PRRD A7h) Protection Register Lock (PRL A6h), Read Any Register (RDAR 65h).
PR does not have separate user programmable non-volatile bits, all defined bits are volatile read only status. The default state of the
RFU bits is set by hardware. There is no non-volatile version of the PR register.
The NVLOCK bit is used to protect the Security Regions 2 and 3 and Pointer Region Protection. When NVLOCK[0] = 0, the Security
Regions 2 and 3 and Pointer Region Protection can not be changed.
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Table 7.21 Protection Status Register (PR)
Bits
Field Name
Function
7
RFU
Reserved
00h
6
SECRRP
Security Regions Read
Password
IRP[6]
5
RFU
Reserved
0
Reserved for Future Use
4
RFU
Reserved
0
Reserved for Future Use
3
RFU
Reserved
0
Reserved for Future Use
2
RFU
Reserved
0
Reserved for Future Use
1
RFU
Reserved
0
NVLOCK
Protect Non-volatile
configuration
0
Type
Default State
Volatile
Read Only
Description
Reserved for Future Use
0 = Security Region 3 password protected from read when NVLOCK = 0
1 = Security Region 3 not password protected from read
Reserved for Future Use
IRP[2] and IRP[0]
0 = Security Regions 2 and 3 and Pointer Region write protected
1 = Security Regions 2 and 3 and Pointer Region may be written. 1
Note:
1. The Command Protection Register Lock (PRL), sets the NVLOCK =”1”.
7.6.8
Individual Block Lock Access Register (IBLAR)
Related Commands: IBL Read (IBLRD 3Dh or 4IBLRD E0h), IBL Lock (IBL 36h or 4IBL E1h), IBL Unlock (IBLUL 39h or 4IBUL E2h),
Global IBL lock (GBL 7Eh), Global IBL unlock (GBUL 98h).
IBLAR does not have user programmable non-volatile bits, all bits are a representation of the volatile bits in the IBL array. The
default state of the IBL array bits is set by hardware. There is no non-volatile version of the IBLAR register.
Table 7.22 IBL Access Register (IBLAR)
Bits
7 to 0
Field Name
IBL
Function
Read or write IBL
for individual
sectors / blocks
Type
Volatile
Default State
Description
IRP[4]=1 then
00h
else FFh
00h = IBL for the sector / block addressed is set to “0” by the IBL, 4IBL and GBL
commands protecting that sector from program or erase operations.
FFh = IBL for the sector / block addressed is cleared to “1” by the IBUL, 4IBUL and
GBUL commands not protecting that sector from program or erase operations.
Note
1. See Figure 8.2, Individual Block Lock / Pointer Region Protection Control on page 68.
2. The IBL bits maybe read by the IBLRD and 4IBLRD commands.
7.6.9
Pointer Region Protection Register (PRPR)
Related Commands: Set Pointer Region (SPRP FBh or 4SPRP E3h), Read Any Register (RDAR 65h), Write Any Register (WRAR
71h).
PRPR contains user programmable non-volatile bits. The default state of the PRPR bits is set by hardware. There is no volatile
version of the PRPR register. See Section 8.6.3, Pointer Region Protection (PRP) on page 69 for additional details.
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S25FL256L
Table 7.23 PRP Register (PRPR)
Bits
Field Name
Function
A31 to A25
RFU
Reserved
Type
Default State
11111111b
A24
PRPAD
PRP Address
1
A23 to A16
A15 to A12
Description
Reserved for Future Use
Pointer Address
A24 in S25FL256L
FFh
Pointer Address A23 to A16
Fh
Pointer Address A15 to A12
1
0=Protect Pointer Region selected sectors
1=Protect All sectors
PRP Enable
1
0=Enable Pointer Region Protection
1=Disable Pointer Region Protection
PRP Top/Bottom
1
0=Pointer Region Protection starts from the top (high address)
1=Pointer Region Protection starts from the bottom (low address)
A11
PRPALL
PRP Protect All
A10
PRPEN
A9
PRPTB
Nonvolatile
A8
RFU
Reserved
1
Reserved for Future Use
A7 to A0
RFU
Reserved
FFh
Reserved for Future Use
7.6.10
DDR Data Learning Registers
Related Commands: Program DLRNV (PDLRNV 43h), Write DLRV (WDLRV 4Ah), Data Learning Pattern Read (DLPRD 41h), Read
Any Register (RDAR 65h), Write Any Register (WRAR 71h).
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (DLRNV) as well as an 8-bit Volatile Data
Learning Register (DLRV). When shipped from Cypress, the DLRNV value is 00h. Once programmed, the DLRNV cannot be
reprogrammed or erased; a copy of the data pattern in the DLRNV will also be written to the DLRV. The DLRV can be written to at
any time, but on hardware and software reset or power cycles the data pattern will revert back to what is in the DLRNV. During the
learning phase described in the SPI DDR modes, the DLP will come from the DLRV. Each IO will output the same DLP value for
every clock edge. For example, if the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0;
subsequently, the 2nd clock edge all I/O’s will output 0, the 3rd will output 1, etc.
When the DLRV value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands.
Table 7.24 Non-Volatile Data Learning Register (DLRNV)
Bits
7 to 0
Field Name
NVDLP
Function
Type
Non-Volatile Data
Learning Pattern
OTP
Default State
00h
Description
OTP value that may be transferred to the host during DDR read command latency (dummy)
cycles to provide a training pattern to help the host more accurately center the data capture
point in the received data bits.
Table 7.25 Volatile Data Learning Register (DLRV)
Bits
7 to 0
Field Name
VDLP
Function
Volatile Data
Learning Pattern
Type
Default State
Description
Volatile
Takes the value
of DLRNV during
POR or Reset
Volatile copy of the NVDLP used to enable and deliver the Data Learning Pattern (DLP) to the
outputs. The VDLP may be changed by the host during system operation.
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ADVANCE
8.
8.1
S25FL256L
Data Protection
Security Regions
The device has a 1024 byte address space that is separate from the main Flash array. This area is divided into 4, individually
lockable, 256 byte length regions. See Section 7.5, Security Regions Address Space on page 47.
The Security Region memory space is intended for increased system security. The data values can “mate” a flash component with
the system CPU/ASIC to prevent device substitution. The Security Region address space is protected by the Security Region Lock
bits or the Protection Register NVLOCK bit (PR[0]). See Section 8.1.4, Security Region Lock Bits (LB3, LB2, LB1, LB0) on page 62.
8.1.1
Reading Security Region Memory Regions
The Security Region Read command (SECRR) uses the same protocol as Fast Read. Read operations outside the valid 1024 byte
Security Region address range will yield indeterminate data. See Section 9.7.3, Security Regions Read (SECRR 48h) on page 116.
Security Region 3 may be password protected from read by setting the PWDMLB bit IRP[2] = 0 and SECRRP bit IRP[6] = 0 when
NVLOCK = 0.
8.1.2
Programming the Security Regions
The protocol of the Security Region programming command (SECRP) is the same as Page Program. See Section 9.7.2, Security
Region Program (SECRP 42h) on page 116
The valid address range for Security Region Program is depicted in Table 7.2 on page 47. Security Region Program operations
outside the valid Security Region address range will be ignored, without P_ERR in SR2V[5] set to “1”.
Security Regions 2 and 3 may be password protected from programming by setting the PWDMLB bit IRP[2] = 0.
8.1.3
Erasing the Security Regions
The protocol of the Security Region erasing command (SECRE) is the same as Sector erase. See Section 9.7.1, Security Region
Erase (SECRE 44h) on page 115
The valid address range for Security Region Erase is depicted in Table 7.2 on page 47. Security Region Erase operations outside
the valid Security Region address range will be ignored, without E_ERR in SR2V set to “1”.
Security Regions 2 and 3 may be password protected from erasing by setting the PWDMLB bit IRP[2] = 0.
8.1.4
Security Region Lock Bits (LB3, LB2, LB1, LB0)
The Security Region Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in Configuration Register
1(CR1NV[5:2]) that provide the write protect control and status to the Security Regions. The default state of Security Regions 0 to 3
are unlocked. LB[3:0] can be set to 1 individually using the Write Status Registers or Write Any Register command. LB[3:0] are One
Time Programmable (OTP), once it’s set to 1, the corresponding 256 Byte Security Region will become read-only permanently.
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8.2
S25FL256L
Deep Power Down
The Deep Power Down (DPD) command offers an alternative means of data protection as all commands are ignored during the DPD
state, except for the Release from Deep Power Down (RES ABh) command and hardware reset. Thus, preventing any program or
erase during the DPD state.
8.3
Write Enable Commands
8.3.1
Write Enable (WREN)
The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data. The WREN command
sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes) during power-up, hardware and software reset,
or after the device completes the following commands:
– Reset
– Page Program (PP or 4PP)
– Quad Page Program (QPP or 4QPP)
– Sector Erase (SE or 4SE)
– Half Block Erase (HBE or 4HBE)
– Block Erase (BE or 4BE)
– Chip Erase (CE)
– Write Disable (WRDI)
– Write Registers (WRR)
– Write Any Register (WRAR)
– Security Region Erase (SECRE)
– Security Region Byte Programming (SECRP)
– Individual and Region Protection Register Program (IRPP)
– Password Program (PASSP)
– Clear Status Register (CLSR)
– Set Pointer Region Protection (SPRP or 4SPRP)
– Program Non-Volatile Data Learning Register (PDLRNV)
– Write Volatile Data Learning Register (WDLRV)
8.3.2
Write Enable for Volatile Registers (WRENV)
The Write Enable Volatile (WRENV) command must be written prior to Write Register (WRR) command that modifies volatile
registers data.
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8.4
S25FL256L
Write Protect Signal
When not in Quad mode (CR1V[1] = 0) or QPI mode (CR2V[3] = 0), the Write Protect (WP#) input in combination with the Status
Register Protect 0 (SRP0) bit (SR1NV[7]) provide hardware input signal controlled protection. When WP# is Low and SRP0 is set to
“1” Status Register-1 (SR1NV and SR1V), Configuration register (CR1NV, CR1V, CR2NV, CR2V, CR2NV and CR3NV) and DDR
Data Learning Registers (DLRNV and DLRV) are protected from alteration. This prevents disabling or changing the protection
defined by the Legacy Block Protect bits or Security Region Lock Bits. See Section 7.6.1, Status Register-1 on page 48.
8.5
Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are volatile bits in the configuration and status registers (CR1V[0] and SR1V[7]).
The SRP bits control the method of write protection for SR1NV, SR1V, CR1NV, CR1V, CR2NV, CR2V, CR3NV, DLRNV and DLRV: software
protection, hardware protection, or power supply lock-down
Table 8.1 Status Register Protection Bits (High Security)
SRP1_D
CR1NV[0]
SRP1
CR1V[0]
SRP0
SR1V[7]
WP#
0
0
0
X
Software Protection
WP# pin has no control. SR1NV, SR1V, CR1NV, CR1V, CR2NV, CR2V,
CR3NV, DLRNV and DLRV can be written. [Factory Default]
0
0
1
0
Hardware Protected
When WP# pin is low SR1NV, SR1V, CR1NV, CR1V, CR2NV, CR2V,
CR3NV, DLRNV and DLRV are locked and can not be written.(1)(4)
0
0
1
1
Hardware Unprotected
When WP# pin is high SR1NV, SR1V, CR1NV, CR1V, CR2NV, CR2V,
CR3NV, DLRNV and DLRV are unlocked and can be written.(1)
0
1
X
X
SR1NV, SR1V, CR1NV, CR1V, CR2NV, CR2V, CR3NV, DLRNV and
Power Supply Lock-Down DLRV are protected and can not be written to again until the next
power-down, power-up cycle. (2)
1
1
X
X
One Time Program
Status Register
Description
SRP1_D CR1NV[0]= 1 SR1NV, SR1V, CR1NV, CR1V, CR2NV, CR2V,
CR3NV, DLRNV and DLRV are permanently protected and can not be
written.(3)
Notes:
1. SRP0 is reloaded from SRP0_NV (SR1NV[7]) default state after a power-down, power-up cycle, software or hardware reset. To enable hardware protection mode by
the WP# pin at power-up set the SRP0_NV bit to “1”.
2. When SRP1 = 1, a power-down, power-up cycle, or hardware reset, will change SRP1 to 0 as SRP1 is reloaded from SRP1_D.
3. SRP1_D can be written only when IRP[2:0] =”111”. When SRP1_D CR1NV[0]=”1” a power-down, power-up cycle, or hardware reset, will reload SRP1 from SRP1_D =
”1” the volatile bit SRP1 is not writable, thus providing OTP protection. When SRP1_D is programmed to 1, Recommended that SRP0_NV should also be programmed
to 1 as an indication that OTP protection is in use.
4. When QPI or QIO mode is enabled (CR2V[3] or CR1V[1] = “1”) the internal WP# signal level is = 1 because the WP# external input is used as IO2 when either mode
is active. This effectively turns off hardware protection when SRP1-SRP0 = 01b. The Register SR1NV, SR1V, CR1NV, CR1V, CR2NV, CR2V, CR3NV, DLRNV and
DLRV are unlocked and can be written.
5. WIP, WEL, and SUS (SR1[1:0] and CR1[7]) are volatile read only status bits that are never affected by the Write Status Registers command.
6. The non-volatile version of SR1NV, CR1NV, CR2NV and CR3NV are not writable when protected by the SRP bits and WP# as shown in the table. The non-volatile
version of these status register bits are selected for writing when the Write Enable (06h) command precedes the Write Status Registers (01h) command or the Write
Any Register (71h) command.
7. The volatile version of registers SR1V, CR1V and CR2V are not writable when protected by the SRP bits and WP# as shown in the table. The volatile version of these
status register bits are selected for writing when the Write Enable for volatile Status Register (50h) command precedes the Write Status Registers (01h) commandor
the Write Enable (06h) command precedes the Write Any Register (71h) command.
8. The volatile CR3V bits are not protected by the SRP bits and may be written at any time by volatile (50h) Write Enable command preceding the Write Status Registers
(01h) command. The WRAR (71h) and SBL (77h) commands are alternative ways to write bits in the CR3V register.
9. During system power up and boot code execution: Trusted boot code can determine whether there is any need to change SR1NV, SR1V, CR1NV, CR1V, CR2NV,
CR2V, CR3NV, DLRNV and DLRV values. If no changes are needed the SRP1 bit (CR1V[0]) can be set to 1 to protect the SR1NV, SR1V, CR1NV, CR1V, CR2NV,
CR2V, CR3NV, DLRNV and DLRV registers from changes during the remainder of normal system operation while power remains on.
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8.6
S25FL256L
Array Protection
There are three types of memory array protection: Legacy Block (LBP), Individual Block Lock (IBL) and Pointer Region (PRP). The
Write Protect Selection (WPS) bit is used by the user to enable one of two protection mechanisms: Legacy Block (LBP) protection
(WPS CR2V[2]=0)or Individual Block Lock (IBL) protection (WPS CR2V[2]=1). See Configuration Register 2 Volatile (CR2V)
on page 54. Only one protection mechanism can be enabled at one time. The Legacy Block Protection is the default protection and
is mutually exclusive with the IBL protection scheme. The Pointer Region Protection is enabled by the Set Pointer Region Protection
command or the WRAR command by the value of A10 = 0. See Pointer Region Command on page 121. When the Pointer Region
Protection is enabled it is logically ORed with the Legacy Block Protection or Individual Block Lock protection.
Figure 8.1 WPS Selection of LBP or IBL and PRP Array Protection
BP Bits
Command
Address
Legacy Block
Protection Logic
(Address Range
Compare)
WPS = 0
Mux
IBLBOOT
Individual Block
Protection Logic
(IBL Bit Array)
WPS = 1
OR
WPS
Array
Location
Protected
Pointer Region
Protection Logic
(Address range
compare)
NVLOCK
8.6.1
Legacy Block Protection
The Legacy Block Protect bits Status Register bits BP3, BP2, BP1, BP0 -- SR1V[5:2]) , Status Register bits BP2, BP1, BP0 -SR1V[4:2]) in combination with the Configuration Register TBPROT (SR1V[6]) bit, CMP (CR1V[6] bit ) can be used to protect an
address range of the main Flash array from program and erase operations. The size of the range is determined by the value of the
BP bits and the upper or lower starting point of the range is selected by the TBPROT bit of the configuration register (SR1V[6])
(SR1V[5,). The protection is complemented when the CMP bit (CR1V[6]) is set to 1.
If the Pointer Region Protection is enabled this region protection is logically ORed with the Legacy Block protection region.
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S25FL256L
Table 8.2 S25FL256L (256Mb) Upper Array Complement Legacy Block Protection (TBPROT = 0, CMP = 1)
Status Register Content
S25FL256L Legacy Block Protection (TBPROT =0, CMP =1)
Protected Blocks
Protected Density
(KB)
Protected Portion
BP3
BP2
BP1
BP0
Number Protected
Blocks
0
0
0
0
512
0-511
32768
All
0
0
0
1
511
0-510
32704
Lower 511/512
0
0
1
0
510
0-509
32640
Lower 255/256
0
0
1
1
508
0-507
32512
Lower 127/128
0
1
0
0
504
0-503
32256
Lower 63/64
0
1
0
1
496
0-495
31744
Lower 31/32
0
1
1
0
480
0-479
30720
Lower 15/16
0
1
1
1
448
0-447
28672
Lower 7/8
1
0
0
0
384
0-383
24576
Lower 3/4
1
0
0
1
256
0-255
16384
Lower 1/2
1
0
1
0
0
None
0
None
1
0
1
1
0
None
0
None
1
1
0
0
0
None
0
None
1
1
0
1
0
None
0
None
1
1
1
0
0
None
0
None
1
1
1
1
0
None
0
None
Table 8.3 S25FL256L (256Mb) Lower Array Complement Legacy Block Protection (TBPROT = 1, CMP = 1)
Status Register Content
S25FL256L Legacy Block Protection (TBPROT =1, CMP =1)
Protected Blocks
Protected Density
(KB)
BP3
BP2
BP1
BP0
Number Protected
Blocks
0
0
0
0
512
0-511
32768
All
0
0
0
1
511
1-511
32704
Upper 511/512
0
0
1
0
510
2-511
32640
Upper 255/256
0
0
1
1
508
4-511
32512
Upper 127/128
0
1
0
0
504
8-511
32256
Upper 63/64
0
1
0
1
496
16-511
31744
Upper 31/32
0
1
1
0
480
32-511
30720
Upper 15/16
0
1
1
1
448
64-511
28672
Upper 7/8
1
0
0
0
384
128-511
24576
Upper 3/4
1
0
0
1
256
256-511
16384
Upper 1/2
1
0
1
0
0
None
0
None
1
0
1
1
0
None
0
None
1
1
0
0
0
None
0
None
1
1
0
1
0
None
0
None
1
1
1
0
0
None
0
None
1
1
1
1
0
None
0
None
Document Number: 002-00124 Rev. *A
Protected Portion
Page 66 of 145
ADVANCE
S25FL256L
Table 8.4 S25FL256L (256Mb) Upper Array Legacy Block Protection (TBPROT = 0, CMP = 0)
Status Register Content
S25FL256L Legacy Block Protection (TBPROT =0, CMP =0)
Protected Blocks
Protected Density
(KB)
Protected Portion
None
0
None
BP3
BP2
BP1
BP0
Number Protected
Blocks
0
0
0
0
0
0
0
0
1
1
511
64
Upper 1/512
0
0
1
0
2
510-511
128
Upper 1/256
0
0
1
1
4
508-511
256
Upper 1/128
0
1
0
0
8
504-511
512
Upper 1/64
0
1
0
1
16
496-511
1024
Upper 1/32
0
1
1
0
32
480-511
2048
Upper 1/16
0
1
1
1
64
448-511
4096
Upper 1/8
1
0
0
0
128
384-511
8192
Upper 1/4
1
0
0
1
256
256-511
16384
Upper 1/2
1
0
1
0
512
0-511
32768
ALL
1
0
1
1
512
0-511
32768
ALL
1
1
0
0
512
0-511
32768
ALL
1
1
0
1
512
0-511
32768
ALL
1
1
1
0
512
0-511
32768
ALL
1
1
1
1
512
0-511
32768
ALL
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Page 67 of 145
ADVANCE
8.6.2
S25FL256L
Individual Block Lock (IBL) Protection
Individual Block Lock Bits (IBL) are volatile, with one bit for each sector / block, and each bit can be individually modified. By issuing
the IBL or GBL commands, a IBL bit is set to “0” protecting each related sector / block. By issuing the IBUL or GUL commands, a IBL
bit is cleared to “1” unprotecting each related sector or block. By issuing the IBLRD command the state of each IBL bit can be read.
This feature allows software to easily protect individual sectors / blocks against inadvertent changes, yet does not prevent the easy
removal of protection when changes are needed. The IBL’s can be set or cleared as often as needed as they are volatile bits.
Every main 64KB Block and the 4KB Sectors in bottom and top blocks has a volatile Individual Block Lock Bit (IBL) associated with
it. When a sector / block IBL bit is “0”, the related sector/block is protected from program and erase operations.
If the Pointer Region Protection is enabled this protected region is logically ORed with the IBL bits.
Following power-up, hardware reset, or software reset the default state [IBLLBB = 1] (see Table 7.19, IRP Register (IRP)
on page 58) all individual IBL bits are set to “0” in the protected state. In order to Program or Erase the Array the Global IBL Unlock
or the Sector / Block IBL Unlock command must be given before the Program or Erase commands. When [IBLLBB = 0], all the
individual IBL bits are set to “1” in the un-protected state following power-up, hardware reset, or software reset.
Figure 8.2 Individual Block Lock / Pointer Region Protection Control
F la s h
M e m o ry
A rra y
...
...
S e c to r 1 5
B lo c k 0
...
...
...
...
...
Logical OR
S e c to r 0
Logical OR
Logical OR
...
...
S e c to r 1 5
B lo c k 1
Logical OR
B lo c k 1
...
B lo c k M -1
Logical OR
...
B lo c k M -1
...
B lo c k M
S e c to r N -1 5
S e c to r N -1 5
P o in te r R e g io n
P ro te c tio n
E n a b le d
A 1 0 = “0 ”
S e c to r N
...
...
S e c to r N
Logical OR
In d iv id u a l B lo c k
L o c k B its (IB L ) A rra y
W P S = “1 ”
S e c to r 0
Note;
1. The “M” is the top 64KB Block.
2. The “N is the top 4KB Sector.
Document Number: 002-00124 Rev. *A
Page 68 of 145
ADVANCE
8.6.3
S25FL256L
Pointer Region Protection (PRP)
The Pointer Region Protection is defined by a non-volatile address pointer that selects any 4KB sector as the boundary between
protected and unprotected regions in the memory. This provides a protection scheme with individual sector granularity that remains
in effect across power cycles and reset operations. PRP settings can also be protected from modification until the next power cycle,
until a password is supplied, or can be permanently locked. PRP can be used in combination with either the Legacy Block Protection
or Individual Block Lock protection methods. When enabled, PRP protection is logically ORed with the protection method selected
by the WPS bit (CR2V[2])
The Set Pointer Region Protection (SPRP FBh or 4SPRP E3h) command (see Section 9.9 on page 121) or Write Any Register
(WRAR 71h) command to write the PRPR register (see Section 9.3.15 on page 94) is used to enable or disable PRP, and set the
pointer value.
The S25FL256L device must have 4 Byte addressing enabled (CR2V[0] = 1) to set the Pointer Region Protection register PRPR
(see Section 7.6.9 on page 60) this insures that A24 and A25 are set correctly.
After the Set Block/Pointer Protection command is given or Write Any Register (WRAR 71h) command to write the PRPR register,
the value of A10 enables or disables the pointer protection mechanism. If A10 = 1, then the pointer protection region is disabled.
This is the default state, and the rest of pointer values are don’t care. If A10=0, then the pointer protection region is enabled. The
value of A10 is written in the non-volatile pointer bit in the PRPR. The pointer address values for RFU bits are don’t care but these bit
locations will read back as ones. See Section 7.6.9 on page 60 for additional information on the PRPR.
If the pointer protection mechanism is enabled, the pointer value determines the block boundary between the protected and the
unprotected regions in the memory. The pointer boundary is set by the three (A23-A12) or four (A31-A12) address bytes written to
the non-volatile pointer value in the PRPR. The area that is unprotected will be inclusive of the 4KB sector selected by the pointer
value.
The value of A9 is used to determine whether the region that is unprotected will start from the top (highest address) or bottom
(lowest address) of the memory array to the location of the pointer. If A9=0 when the SPRP or 4SPRP command is issued followed
by a the address, then the 4-kB sector which includes that address and all the sectors from the bottom up (zero to higher address)
will be unprotected. If A9=1 when the SPRP or 4SPRPcommand is issued followed by address then the 4-kB sector which includes
that address and all the sectors from the Top down (max to lower address) will be unprotected. The value of A9 is in the non-volatile
pointer value in the PRPR.
The A11 bit can be used to protect all sectors. If A11=1, then all sectors are protected. If A11=0, then the unprotected range will be
determined by Amax-A12. The value of A11 is in the non-volatile pointer value in the PRPR.
The SPRP or 4SPRP command is ignored during a suspend operation because the pointer value cannot be erased and reprogrammed during a suspend.
The SPRP or 4SPRP command is ignored if NVLOCK PR[0]=0.
The Read Any Register 65h command (see Section 9.3.14 on page 92) reads the contents of PRP access register. This allows the
contents of the pointer to be read out for test and verification.
Table 8.5 PRP Table
A11
A10
A9
x
1
x
Protect
Address Range
Unprotect
Address Range
None
All
1FFFFFF to
A[31:12]
(A[31:12]+1)
to 0000000
to A[31:12]
0
0
0
0
0
1
(A[31;12]-1) to
0000000
1
0
x
1FFFFFF to
000000
1FFFFFF
Not Applicable
Comment
A10 = 1 is PRP disabled (this is the default state and the rest of pointer value is don't care).
The 4-kB sector which includes that address and all the sectors from the bottom up (zero to higher
address) will be unprotected.
The 4-kB sector which includes that address and all the sectors from the Top down (max to lower address)
will be unprotected.
A10=0 and A11 =1 means protect all sectors and Amax-A12 are don't care.
If the pointer protect scheme is active (A10=0), and the pointer protects any portion of the address space to which an erase
command is applied, the erase command fails. For example, if the pointer protection is protecting 4KB of the array that would be
affected by a Block erase command, that erase command fails. Chip Erase CEh command is ignored if PRP is enabled (A10=0) and
this will set the E_ERR status bit.
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Page 69 of 145
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S25FL256L
If the Pointer Region Protection is enabled this protection is logically ORed with either the Legacy Block protection region if WPS
CR2V[2]=0 or Individual Block Lock protection if WPS CR2V[2]=1 (See Figure 8.1, WPS Selection of LBP or IBL and PRP Array
Protection on page 65).
8.7
Individual and Region Protection
Individual and Region Protection (IRP) is the name used for a set of independent hardware and software methods used to disable or
enable programming or erase operations on Security Regions 2 and 3 and the Pointer Region Protection Register.
Each method manages the state of the NVLOCK bit (PR[0]). When NVLOCK =1, the Security Regions 2 and 3 and the Pointer
Region Protection Register (PRPR) may be programmed and erased. When NVLOCK =0, the Security Regions 2 and 3 and PRPR
can not be programmed or erased. Note, the Security Regions 2 and 3 are also protected respectively by LB2 or LB3=1
(CR1NV[4:5]).
Power Supply Lock-down protection is the default method. This method sets the NVLOCK bit to “1” during POR or Hardware Reset
so that the NVLOCK related areas and registers are unprotected by a device reset. The PRL (A6h) command clears the NVLOCK bit
to “0” to protect the NVLOCK related areas and registers. There is no command in the Power Supply Lock-down method to set the
NVLOCK bit to “1”, therefore the NVLOCK bit will remain at “0” until the next power-off or hardware reset. The Power Supply Lockdown method allows boot code the option of changing Security Regions 2 and 3 or the value in PRPR, by programming or erasing
these non-volatile areas, then protecting these non-volatile areas from further change for the remainder of normal system operation
by clearing the NVLOCK bit to “0”. This is sometimes called Boot-code controlled protection.
The Password method clears the Protection Register NVLOCK bit to 0 and sets the SECRRP bit = IRP[6] during POR or Hardware
Reset to protect the NVLOCK related areas and registers. The SECRRP bit determines whether Security Region 3 is readable. A 64
bit password may be permanently programmed and hidden for the password method. The PASSU (EAh) command can be used to
provide a password for comparison with the hidden password. If the password matches, the NVLOCK bit is set to “1” to unprotect the
NVLOCK related areas and registers. The PRL (A6h) command can be used to clear the NVLOCK bit to “0” to turn on protection
again.
The Permanent method permanently sets the SECRRP bit = 1 and clears NVLOCK to 0. This permanently protects the Security
Regions 2 and 3 and the PRPR.
The selection of the NVLOCK bit management method is made by programming OTP bits in the IRP Register (IRP[2 or 1 or 0] so as
to permanently select the method used.
An overview of all methods is shown in Figure 8.3, Permanent, Password and Power Supply Lock-down Protection Overview
on page 71.
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S25FL256L
Figure 8.3 Permanent, Password and Power Supply Lock-down Protection Overview
Power on Reset or
Hardware Reset
Password
Protection Enabled
IRP[2]=0
Permanent
Protection Enabled
IRP[0]=0
No
No
Yes
Yes
Default Power Lock
Protection
No
Yes
IRP Register Bits Locked
Status Register Protect
Locked
NVLOCK =0
Permanent Erase and
Program Protection of
Security Regions 2 & 3
and Pointer Region
Protection
IRP Register Bits Locked
Status Register Protect
Locked
Security
Region 3 Read
Password Protection
Enabled
IRP[6]=0
Power Supply
Lock-down
Protection Enabled
IRP[1]=0
No
IRP Register Bits Locked
Status Register Protect
Locked
IRP Register Bits
Programmable
Status Register Protect
OTP Option
Programmable
NVLOCK = 1
Security Regions 2 & 3
and Pointer Region
Protection are Unlocked
Readable, Erasable and
Programmable
NVLOCK = 1
Security Regions 2 & 3
and Pointer Region
Protection are Unlocked
Readable, Erasable and
Programmable
Yes
NVLOCK = 0
Security Region 3
Read & Write Locked
Security Region 2
Write Locked
Pointer Region
Protection Write Locked
NVLOCK = 0
Security Region 2 & 3
Write Locked
Pointer Region
Protection Write Locked
No
NVLOCK Bit Write
Yes
Password Unlock
Password Unlock
No
Yes
NVLOCK Bit Write
NVLOCK Bit Write
Yes
NVLOCK = 0
Security Regions 2 & 3
Write Locked
Pointer Region
Protection Write Locked
Yes
NVLOCK = 1
Security Regions 2 & 3
and Pointer Region
Protection are Unlocked
Readable, Erasable and
Programmable
Yes
No
NVLOCK = 0
Security Regions 2 & 3
Write Locked
Pointer Region
Protection Write Locked
No
NVLOCK = 1
Security Regions 2 & 3
and Pointer Region
Protection are Unlocked
Erasable and
Programmable
No
Read Password Protection Mode
Protects Security Regions 3 from
Read, Erase and Programming,
Security Region 2 and Pointer
Region Protection from erase and
programming after powerup . A
password unlock Command will
enable changes to Security Region
2 & 3 and Pointer Region
Protection. A NVLOCK bit write
command turns the protection back
on.
Document Number: 002-00124 Rev. *A
Yes
NVLOCK Bit Write
Power Supply Lock-down
Protection Mode
Does not protect Security Regions
2 & 3 and Pointer Region Protection
from erase and programming after
powerup. The NVLOCK Bit write
command protects Security
Regions 2 & 3 and Pointer Region
Protection until the next power off
or reset.
Default Mode
Does not protect Security Regions
2 & 3 and Pointer Region Protection
from erase and programming after
powerup. The NVLOCK Bit write
command protects Security
Regions 2 & 3 and Pointer Region
Protection until the next power off
or reset.
The OTP Option for Status Register
Protect is available to be
programmed.
Permanent Protection Mode
Permanently protects Security
Regions 2 & 3 and Pointer Region
Protection from Erase and
Programming
Note
If Security Region Lock bits LB 2 &
3 are protected CR1NV[5:4]=1, this
overrides the NVLOCK and the
Security Regions protected by the
LB bits will be permanently
protected from erase and
programming. If Read Password is
enabled Security Region 3 can still
be read password protected.
No
Password Protection Mode
Protects Security Regions 2 & 3
and Pointer Region Protection from
erase and programming after
powerup. A password unlock
Command will enable changes to
Security Region 2 & 3 and Pointer
Region Protection. A NVLOCK bit
write command turns the protection
back on.
Page 71 of 145
ADVANCE
8.7.1
S25FL256L
IRP Register
The IRP register is used to permanently configure the behavior of Individual and Region Protection (IRP) features. See Table 7.19,
IRP Register (IRP) on page 58.
As shipped from the factory, all devices default to the Power Supply Lock-down protection mode, with all regions unprotected.
The device programmer or host system must then choose which protection method to use by programming one of the, one-time
programmable bits, Permanent, Power Supply Lock-down or Password Protection Mode. Programming one of these bits locks the
part permanently in the selected mode:
Factory Defaults IRP Register
– IRP[6] = “1” = Read Password Protection Mode not enabled.
– IRP[4] = “1” = IBL bits power-up in protected state.
– IRP[2] = “1” = Password Protection Mode not enabled.
– IRP[1] = “1” = Power Supply Lock-down protection Mode not enabled but is the default mode.
– IRP[0] = “1” = Permanent Protection Mode not enabled.
IRP register programming rules:
If the Read Password mode is chosen, the SECRRP bit must be programmed prior or at the same time as setting the
Password Protection mode Lock Bits IRP[2].
If the IBL bits power-up in unprotected mode is chosen, the IBLLBB bit must be programmed prior or at the same time as
setting one of the Protection mode Lock Bits IRP[2:0].
If the password mode is chosen, the password must be programmed prior to setting the Password Protection mode Lock
Bits IRP[2].
The protection modes are mutually exclusive, only one may be selected. Once one of the Protection Modes is selected
IPRP[2:0], the IRP Register bits are permanently protected from programming and no further changes to the OTP register
bits is allowed. If an attempt to change any of the register bits above, after the Protection mode is selected, the operation
will fail and P_ERR (SR2V[5]) will be set to 1.
The programming time of the IRP Register is the same as the typical page programming time. The system can determine the status
of the IRP register programming operation by reading the WIP bit in the Status Register. See Section 7.6.1, Status Register-1
on page 48 for information on WIP.
See Section 8.7.3, Password Protection Mode on page 73.
8.7.1.1
IBL Lock Boot Bit
The default IBL Lock Bit IRP[4]=1, all the IBL bits on power-up or reset (after a hardware reset or software reset) to the “protected
state.” If the IBL Lock Bit IRP[4]=0 (programmed), the IBL power-up or reset to the “unprotected state.”
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Page 72 of 145
ADVANCE
8.7.2
8.7.2.1
S25FL256L
Protection Register (PR)
NVLOCK Bit (PR[0])
The NVLOCK bit is a volatile bit for protecting:
Pointer Region Protection Register
Security Regions 2 and 3
When cleared to “0”, NVLOCK locks the related regions. When set to “1”, it allows the related regions to be changed. See
Section 7.6.7, Protection Register (PR) on page 59 for more information.
The PRL command is used to clear the NVLOCK bit to “0”. The NVLOCK Bit should be cleared to “0” only after all the related regions
are configured to the desired settings.
In Power Supply Lock-down protection mode, the NVLOCK is set to “1” during POR or a hardware reset. A software reset command
does not affect the NVLOCK bit. When cleared to “0”, no software command sequence can set the NVLOCK bit to “1”, only another
hardware reset or power-up can set the NVLOCK bit.
In the Password Protection mode, the NVLOCK bit is cleared to “0” during POR, or a hardware reset. The NVLOCK bit can only be
set to “1” by the Password Unlock command.
The Permanent method permanently clears NVLOCK to 0. This permanently protects the Security Regons 2 and 3 and the PRPR.
8.7.2.2
Security Region Read Password Lock Bit (SECRRP, PR[6])
The SECRRP Bit is a volatile bit for read protecting Security Region 3. When SECRRP[6]=0 the Security Region 3 can not be read,
See Section 7.6.7, Protection Register (PR) on page 59 for more information.
In the Password Protection mode, the SECRRP bit is set equal to IRP[6] during POR or software or hardware reset. The NVLOCK
bit can only be set to “1” by the Password Unlock command. A software reset does not affect the NVLOCK bit.
The Permanent method permanently sets the SECRRP bit = 1. This permanently leaves Security Region 3 readable.
8.7.3
Password Protection Mode
Password Protection Mode allows an even higher level of security than the Power Supply Lock-down protection Mode, by requiring
a 64-bit password for unlocking the NVLOCK bit. In addition to this password requirement, after power up, hardware reset, the
NVLOCK bit is cleared to “0” to ensure protection after power-up or reset. Successful execution of the Password Unlock command
by entering the entire password sets the NVLOCK bit to 1, allowing for sector NVLOCK related areas and registers modifications.
Password Protection Notes:
Once the Password is programmed and verified, the Password Mode (IRP[2]=0) must be set in order to prevent reading the
password.
The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a
“0” results in the cell left as a “0” with no programming error set.
The password is all “1”s when shipped from Cypress. It is located in its own memory space and is accessible through the
use of the Password Program, Password Read, RDAR, and WRAR commands.
All 64-bit password combinations are valid as a password.
The Password Mode, once programmed, prevents reading the 64-bit password and further password programming. All
further program and read commands to the password region are disabled and these commands are ignored or return
undefined data. There is no means to verify what the password is after the Password Mode Lock Bit is selected. Password
verification is only allowed before selecting the Password Protection mode.
The Protection Mode Lock Bits are not erasable.
The exact password must be entered in order for the unlocking function to occur. If the password unlock command provided
password does not match the hidden internal password, the unlock operation fails in the same manner as a programming
operation on a protected sector. The P_ERR bit is set to one, the WIP Bit remains set, and the NVLOCK bit remains cleared
to 0.
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S25FL256L
The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an
unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly
match a password. The Read Status Register 1 command may be used to read the WIP bit to determine when the device
has completed the password unlock command or is ready to accept a new password command. When a valid password is
provided the password unlock command does not insert the 100 µs delay before returning the WIP bit to zero.
If the password is lost after selecting the Password Mode, there is no way to set the NVLOCK bit =1.
8.7.4
Security Region Read Password Protection
The Security Region Read Password Protection enables protecting Security Region 3 from read, program and erase.
Security Region Read Password Protection is an optional addition to the Password Protection Mode (described above).
The Security Regions Read Password Protection is enabled when the user programs SECRRP bit ‘IRP[6] = 0. The
SECRRP bit IRP[6] must be programmed prior or at the same time as setting the Password Protection mode Lock Bits
IRP[2].
The Security Regions Read Password Protection is not active until the password is programmed, IRP[2] is programmed to 0.
When the SECRRP (PR[6]) bit is set to 0 the Security Region 3 is not readable. If these regions are read the resulting data is invalid
and undefined.
8.7.5
Recommended IRP Protection Process
During system manufacture, the Flash device configuration should be defined by:
1. Programming the Security Regions as desired.
2. Set Pointer Region Protection Register as desired
3. Program the Password register (PASS) if password protection will be used.
4. Program the IRP Register as desired, including the selection of Permanent, Power Supply Lock-down or password IRP
protection mode in IRP[2:0]. It is very important to explicitly select a protection mode so that later accidental or malicious
programming of the IRP register is prevented. This is to ensure that only the intended protection features are enabled.
Before or while programming the IRP register:
a. The IBLLBB bit (IRP[4]) may be used to cause all the IBL bits to power up in the unprotected state.
b. The SECRRP bit (IRP[6]) may be programmed to select Security Regions Read Password Protection to use the
password to control read access to the Security Region 3.
During system power up and boot code execution: If the Power Supply Lock-down protection mode is in use, trusted boot code can
determine whether there is any need to modify the NVLOCK related areas or registers. If no changes are needed the NVLOCK bit
can be cleared to 0 via the PRL command to protect the NVLOCK related areas or registers from changes during the remainder of
normal system operation while power remains on.
Document Number: 002-00124 Rev. *A
Page 74 of 145
ADVANCE
9.
S25FL256L
Commands
All communication between the host system and FL-L family memory devices is in the form of units called commands. See
Section 3.2, Command Protocol on page 12 for details on command protocols.
Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host system
and the memory device generally handle the details of signal relationships and timing. For this reason, signal relationships and
timing are not covered in detail within this software interface focused section of the document. Instead, the focus is on the logical
sequence of bits transferred in each command rather than the signal timing and relationships. Following are some general signal
relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of
commands, see Section 3.2, Command Protocol on page 12.
– The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide transfers. The
memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive the IO0-IO3 signals
during Dual and Quad transfers.
– All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept
low throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for eight bit
transfer multiples to transfer byte granularity information. No commands will be accepted if CS# is returned high not at an 8 bit
boundary.
9.1
9.1.1
Command Set Summary
Extended Addressing
To accommodate addressing above 128 Mb, there are two options:
1. Instructions that always require a 4-Byte address, used to access up to 32 Gb of memory:
Table 9.1 Extended Address 4-Byte Address Commands
Command Name
Function
4READ
Read
Instruction (Hex)
13
4FAST_READ
Read Fast
0C
4DOR
Dual Output Read
3C
4QOR
Quad Output Read
6C
4DIOR
Dual I/O Read
BC
4QIOR
Quad I/O Read
EC
4DDRQIOR
DDR Quad I/O Read
EE
4PP
Page Program
12
4QPP
Quad Page Program
34
4SE
Sector Erase
21
4HBE
Half Block Erase
53
4BE
Block Erase
DC
4IBLRD
IBL Read
E0
4IBL
IBL Lock
E1
4IBUL
IBL Unlock
E2
4SPRP
Set Pointer Region Protection
E3
2. A 4 Byte address mode for backward compatibility to the 3 Byte address instructions. The standard 3 Byte instructions
can be used in conjunction with a 4 Byte address mode controlled by the Address Length configuration bit (CR2V[0]). The
default value of CR2V[0] is loaded from CR2NV[1] (following power up, hardware reset, or software reset), to enable
default 3-Byte (24-bit) or 4 Byte (32 bit) addressing. When the address length (CR2V[0]) set to 1, the legacy commands
are changed to require 4-Bytes (32-bits) for the address field. The following instructions can be used in conjunction with
the 4 Byte address mode configuration to switch from 3-Bytes to 4-Bytes of address field.
Document Number: 002-00124 Rev. *A
Page 75 of 145
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S25FL256L
Table 9.2 Extended Address 4-Byte Address Mode with 3-Byte Address Commands
Command Name
Function
Instruction (Hex)
RSFDP
Read SFDP
5A
READ
Read
03
FAST_READ
Read Fast
0B
3B
DOR
Dual Output Read
QOR
Quad Output Read
6B
DIOR
Dual I/O Read
BB
QIOR
Quad I/O Read
EB
DDRQIOR
DDR Quad I/O Read)
ED
PP
Page Program
02
QPP
Quad Page Program
32
SE
Sector Erase
20
HBE
Half Block Erase
52
BE
Block Erase
D8
RDAR
Read Any Register
65
WRAR
Write Any Register
71
SECRE
Security Region Erase
44
SECRP
Security Region Program
42
SECRR
Security Region Read
48
IBLRD
IBL Read
3D
IBL
IBL Lock
36
IBUL
IBL Unlock
39
SPRP
Set Pointer Region Protection
FB
Document Number: 002-00124 Rev. *A
Page 76 of 145
ADVANCE
9.1.2
S25FL256L
Command Summary by Function
Table 9.3 FL-L Family Command Set (sorted by function)
Function
Command Name
Read Device
ID
RSFDP
RDQID
RDID
RUID
0
Yes
133
3 or 4
Yes
AF
108
0
Yes
9F
Read JEDEC Serial Flash Discoverable Parameters
5A
Read Quad ID
4B
133
0
Yes
Read Status Register-1
05
108
0
Yes
RDSR2
Read Status Register-2
07
108
0
No
RDCR1
Read Configuration Register-1
35
108
0
No
RDCR2
Read Configuration Register-2
15
108
0
No
RDCR3
Read Configuration Register-3
33
108
0
No
Read Any Register
65
133
3 or 4
Yes
WRR
Write Register (Status-1 and Configuration-1,2,3)
01
133
0
Yes
WRDI
Write Disable
04
133
0
Yes
WREN
Write Enable for Non-volatile data change
06
133
0
Yes
Write Enable for Volatile Status and Configuration Registers
50
133
0
Yes
Write Any Register
71
133
3 or 4
Yes
WRENV
WRAR
CLSR
Clear Status Register
30
133
0
Yes
4BEN
Enter 4 Byte Address Mode
B7
133
0
Yes
4BEX
Exit 4 Byte Address Mode
E9
133
0
Yes
Set Burst Length
77
133
0
Yes
QPIEN
Enter QPI
38
133
0
No
QPIEX
Exit QPI
F5
133
0
Yes
DLPRD
Program
Flash Array
108
Read ID (JEDEC Manufacturer ID)
Read Unique ID
SBL
Read Flash
Array
QPI
Maximum
Frequency
(MHz)
RDSR1
RDAR
Register
Access
Address
Length
(Bytes)
instruction
Value (Hex)
Command Description
Data Learning Pattern Read
41
133
0
Yes
PDLRNV
Program NV Data Learning Register
43
133
0
Yes
WDLRV
Write Volatile Data Learning Register
4A
133
0
Yes
READ
Read
03
50
3 or 4
No
4READ
Read
13
50
4
No
FAST_READ
Fast Read
0B
133
3 or 4
No
4FAST_READ
Fast Read
0C
133
4
No
DOR
Dual Output Read
3B
133
3 or 4
No
4DOR
Dual Output Read
3C
133
4
No
QOR
Quad Output Read
6B
133
3 or 4
No
4QOR
Quad Output Read
6C
133
4
No
No
DIOR
Dual I/O Read
BB
133
3 or 4
4DIOR
Dual I/O Read
BC
133
4
No
QIOR
Quad I/O Read (CR1V[1]=1) or CR2V[3]=1
EB
133
3 or 4
Yes
4QIOR
Yes
Quad I/O Read (CR1V[1]=1) or CR2V[3]=1
EC
133
4
DDRQIOR
DDR Quad I/O Read (CR1V[1]=1 or CR2V[3]=1)
ED
66
3 or 4
Yes
4DDRQIOR
DDR Quad I/O Read (CR1V[1]=1 or CR2V[3]=1)
EE
66
4
Yes
PP
Page Program
02
133
3 or 4
Yes
4PP
Page Program
12
133
4
Yes
QPP
Quad Page Program
32
133
3 or 4
No
4QPP
Quad Page Program
34
133
4
No
Document Number: 002-00124 Rev. *A
Page 77 of 145
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S25FL256L
Table 9.3 FL-L Family Command Set (sorted by function) (Continued)
Function
Erase Flash
Array
Erase /
Program
Suspend /
Resume
Security
Region
Array
Array
Protection
Command Name
instruction
Value (Hex)
Maximum
Frequency
(MHz)
Address
Length
(Bytes)
QPI
SE
Sector Erase
20
133
3 or 4
Yes
4SE
Sector Erase
21
133
4
Yes
HBE
Half Block Erase
52
133
3 or 4
Yes
4HBE
Half Block Erase
53
133
4
Yes
BE
Block Erase
D8
133
3 or 4
Yes
4BE
Block Erase
DC
133
4
Yes
CE
Chip Erase
60
133
0
Yes
CE
Chip Erase (alternate instruction)
C7
133
0
Yes
EPS
Erase / Program Suspend
75
133
0
Yes
EPR
Erase / Program Resume
7A
133
0
Yes
SECRE
Security Region Erase
44
133
3 or 4
Yes
SECRP
Security Region Program
42
133
3 or 4
Yes
SECRR
Security Region Read
48
133
3 or 4
Yes
IBLRD
IBL Read
3D
133
3 or 4
Yes
4IBLRD
IBL Read
E0
133
4
Yes
IBL
IBL Lock
36
133
3 or 4
Yes
4IBL
IBL Lock
E1
133
4
Yes
IBUL
IBL Unlock
39
133
3 or 4
Yes
4IBUL
IBL Unlock
E2
133
4
Yes
GBL
GBUL
Individual
and Region
Protection
Command Description
Global IBL Lock
7E
133
0
Yes
Global IBL Unlock
98
133
0
Yes
Yes
SPRP
Set Pointer Region Protection
FB
133
3 or 4(2)
4SPRP
Set Pointer Region Protection
E3
133
4
Yes
IRPRD
IRP Register Read
2B
133
0
Yes
IRPP
IRP Register Program
2F
133
0
Yes
PRRD
Protection Register Read
A7
133
0
Yes
Yes
Protection Register Lock (NVLOCK Bit Write)
A6
133
0
Password Read
E7
133
0
Yes
PASSP
Password Program
E8
133
0
Yes
PASSU
Password Unlock
EA
133
0
Yes
RSTEN
Software Reset Enable
66
133
0
Yes
RST
Software Reset
99
133
0
Yes
MBR
Mode Bit Reset
FF
133
0
Yes
Deep Power
Down
DPD
Deep Power Down
B9
133
0
Yes
RES
Release from Deep Power Down / Device Id
AB
133
0
Yes
RFU
Reserved-18
Reserved
18
RFU
Reserved-41
Reserved
41
RFU
Reserved-43
Reserved
43
RFU
Reserved-4A
Reserved
4A
RFU
Reserved-ED
Reserved
ED
RFU
Reserved-EE
Reserved
EE
Reset
PRL
PASSRD
Notes
1. Commands not supported in QPI mode have undefined behavior if sent when the device is in QPI mode.
2. For S25FL256L device, the SPRP command must be in 4 byte address mode with CR2V[0]=1.
Document Number: 002-00124 Rev. *A
Page 78 of 145
ADVANCE
9.1.3
S25FL256L
Read Device Identification
There are multiple commands to read information about the device manufacturer, device type, and device features. SPI memories
from different vendors have used different commands and formats for reading information about the memories. The FL-L family
supports the three device information commands.
9.1.4
Register Read or Write
There are multiple registers for reporting embedded operation status or controlling device configuration options. There are
commands for reading or writing these registers. Registers contain both volatile and non-volatile bits. Non-volatile bits in registers
are automatically erased and programmed as a single (write) operation.
9.1.4.1
Monitoring Operation Status
The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the
Write in Progress (WIP) bit in the Status Register. The Read from Status Register-1 command or Read Any Register command
provides the state of the WIP bit. The Read from Status Register-2 or Read Any Register command provides the state of the
program error (P_ERR) and erase error (E_ERR) bits in the status register indicate whether the most recent program or erase
command has not completed successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating
the device remains busy and unable to receive most new operation commands. Only status reads (RDSR1 05h, RDSR2 07h), Read
Any Register (RDAR 65h), Read Configuration RDCR1 and RDCR3, status clear (CLSR 30h), and software reset (RSTEN 66h
followed by RST 99h) are valid commands when P_ERR or E_ERR is set to 1. A Clear Status Register (CLSR) command must be
sent to return the device to standby state. Alternatively, Hardware Reset, or Software Reset (RSTEN 66h followed by RST 99h) may
be used to return the device to standby state.
9.1.4.2
Configuration
There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length,
and some aspects of data protection.
9.1.5
Read Flash Array
Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incrementally higher byte
addresses until the host ends the data transfer by driving CS# input High. If the byte address reaches the maximum address of the
memory array, the read will continue at address zero of the array.
Burst Wrap read can be enabled by the Set Burst Length (SBL 77h) command with the requested wrapped read length and
alignment, see Section 9.3.16, Set Burst Length (SBL 77h) on page 95. Burst Wrap read is only for Quad I/O and QPI modes
There are several different read commands to specify different access latency and data path widths. Double Data Rate (DDR)
commands also define the address and data bit relationship to both SCK edges:
The Read command provides a single address bit per SCK rising edge on the SI/IO0 signal with read data returning a
single bit per SCK falling edge on the SO/IO1 signal. This command has zero latency between the address and the
returning data but is limited to a maximum SCK rate of 50MHz.
Other read commands have a latency period between the address and returning data but can operate at higher SCK
frequencies. The latency depends on a configuration register read latency value.
The Fast Read command provides a single address bit per SCK rising edge on the SI/IO0 signal with read data returning a
single bit per SCK falling edge on the SO/IO1 signal.
Dual or Quad Output Read commands provide address on SI/IO0 pin on the SCK rising edge with read data returning two
bits, or four bits of data per SCK falling edge on the IO0 - IO3 signals.
Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data returning two
bits, or four bits of data per SCK falling edge on the IO0 - IO3 signals. Continuous read feature is enabled if the mode bits
value is Axh.
Quad Double Data Rate read commands provide address four bits per every SCK edge with read data returning four bits of
data per every SCK edge on the IO0 - IO3 signals. Continuous read feature is enabled if the mode bits value is Axh.
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9.1.6
S25FL256L
Program Flash Array
Programming data requires two commands: Write Enable (WREN), and Page Program (PP, 4PP, QPP, 4QPP). The Page Program
command accepts from 1 byte up to 256 consecutive bytes of data (page) to be programmed in one operation. Programming means
that bits can either be left at 1, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation.
9.1.7
Erase Flash Array
The Sector Erase, Half Block Erase, Block Erase, or Chip Erase commands set all the bits in a sector or the entire memory array to
1. A bit needs to be first erased to 1 before programming can change it to a 0. While bits can be individually programmed from a 1 to
0, erasing bits from 0 to 1 must be done on a sector-wide, half block-wide, block-wide or array-wide (Chip) level. The Write Enable
(WREN) command must precede an erase command.
9.1.8
Security Regions, Legacy Block Protection, and Individual and Region
Protection
There are commands to read and program a separate One Time Protection (OTP) array for permanently protected data such as a
serial number. There are commands to control a contiguous group (block) of Flash memory array sectors that are protected from
program and erase operations.There are commands to control which individual Flash memory array sectors are protected from
program and erase operations. There is a mode to limit read access of Security Region 3 until a password is supplied.
9.1.9
Reset
There are commands to reset to the default conditions present after power on to the device. However, the software reset commands
do not affect the current state of the SRP1 or NVLOCK Bits. In all other respects a software reset is the same as a hardware reset.
There is a command to reset (exit from) the Continuous Read Mode.
9.1.10
Reserved
Some instructions are reserved for future use. In this generation of the FL-L family some of these command instructions may be
unused and not affect device operation, some may have undefined results.
Some commands are reserved to ensure that a legacy or alternate source device command is allowed without effect. This allows
legacy software to issue some commands that are not relevant for the current generation FL-L family with the assurance these
commands do not cause some unexpected action.
Some commands are reserved for use in special versions of the FL-L not addressed by this document or for a future generation.
This allows new host memory controller designs to plan the flexibility to issue these command instructions. The command format is
defined if known at the time this document revision is published.
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9.2
9.2.1
S25FL256L
Identification Commands
Read Identification (RDID 9Fh)
The Read Identification (RDID) command provides read access to manufacturer identification, device identification. The
manufacturer identification is assigned by JEDEC. The device identification values are assigned by Cypress.
Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the
program, erase, or write cycle that is in progress.
The RDID instruction is shifted on SI / IO0. After the last bit of the RDID instruction is shifted into the device, a byte of manufacturer
identification, two bytes of device identification, will be shifted sequentially out on SO / IO1, As a whole this information is referred to
as ID. See Section 11.2, Device ID Address Map on page 140 for the detail description of the ID contents.
Continued shifting of output beyond the end of the defined ID address space will provide undefined data. The RDID command
sequence is terminated by driving CS# to the logic high state anytime during data output. The RDID command is supported up to
108 MHz.
Figure 9.1 Read Identification (RDID) Command Sequence
CS#
SCK
SI_ IO0
7
6
5
4
3
2
1
0
SO_IO1
7
Phase
6
5
Instruction
4
3
2
1
0
7
6
5
Data 1
4
3
2
1
0
Data N
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
Figure 9.2 Read Identification (RDID) QPI Mode Command
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
9.2.2
Instruction
D1
D2
D3
D4
Data N
Read Quad Identification (RDQID AFh)
The Read Quad Identification (RDQID) command provides read access to manufacturer identification, device identification. This
command is an alternate way of reading the same information provided by the RDID command while in QPI mode. In all other
respects the command behaves the same as the RDID command.
The command is recognized only when the device is in QPI Mode (CR2V[3]=1) or Quad Mode (CR1V[1]=1). The instruction is
shifted in on IO0-IO3 for QPI Mode and IO0 for Quad Mode. After the last bit of the instruction is shifted into the device, a byte of
manufacturer identification, two bytes of device identification will be shifted sequentially out on IO0-IO3. As a whole this information
is referred to as ID. See Section 11.2, Device ID Address Map on page 140 for the detail description of the ID contents.
Continued shifting of output beyond the end of the defined ID address space will provide undefined data. The command sequence is
terminated by driving CS# to the logic high state anytime during data output.
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S25FL256L
Figure 9.3 Read Quad Identification (RDQID) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Instruction
D1
D2
D3
D4
Data N
Figure 9.4 Read Quad Identification (RDQID) Command Sequence Quad Mode
CS#
SCLK
IO0
7
6
5
4
4
0
4
0
IO1
5
1
5
1
IO2
6
2
6
2
IO3
7
3
7
3
Phase
9.2.3
3
2
1
0
Instruction
D1
Data N
Read Serial Flash Discoverable Parameters (RSFDP 5Ah)
The command is initiated by shifting on SI the instruction code “5Ah”, followed by a 24-bit (3 byte) address or 32-bit (4 byte) address
(depending on the current Address Length configuration of CR2V[0]), followed by the number of read latency (dummy cycles) set by
the Variable Read Latency configuration in CR3V[3:0].
The SFDP bytes are then shifted out on SO/IO1 starting at the falling edge of SCK after the dummy cycles. The SFDP bytes are
always shifted out with the MSB first. If the 24-bit (3 byte) address or 32-bit (4 byte) address is set to any non-zero value, the
selected location in the SFDP space is the starting point of the data read. This enables random access to any parameter in the
SFDP space. In SPI mode the RSFDP command is supported up to 133 MHz.
The Variable Read Latency should be set to 8 cycles for compliance with the JEDEC JESD216 SFDP standard. The non-volatile
default Variable Read Latency in CR3NV is set to 8 dummy cycles when the device is shipped from Cypress. However, because the
RSFDP command uses the same implementation as other variable address length and latency read commands, users are free to
modify the address length and latency of the command if desired.
Continuous (sequential) read is supported with the Read SFDP command.
Figure 9.5 RSFDP Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
7
Instruction
Address
Dummy Cycles
6
5
4
3
2
1
0
Data 1
Note
A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 13h.
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
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S25FL256L
Figure 9.6 RSFDP QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
20
4
0
4
0
4
0
4
0
4
0
IO1
5
1
21
5
1
5
1
5
1
5
1
5
1
IO2
6
2
22
6
2
6
2
6
2
6
2
6
2
IO3
7
3
23
7
3
7
3
7
3
7
3
7
3
Phase
9.2.4
Instruct.
Address
Dummy
D1
D2
D3
D4
Read Unique ID (RUID 4Bh)
The Read Identification (RUID) command provides read access to factory set read only 64 bit number that is unique to each device.
The RUID instruction is shifted on SI followed by four dummy bytes or 16 dummy bytes QPI (32 clock cycles). This latency period
(i.e., dummy bytes) allows the device’s internal circuitry enough time to access data at the initial address. During latency cycles, the
data value on IO0-IO3 are “don’t care” and may be high impedance.
Then the 8 bytes of Unique ID will be shifted sequentially out on SO / IO1.
Continued shifting of output beyond the end of the defined Unique ID address space will provide undefined data. The RUID
command sequence is terminated by driving CS# to the logic high state anytime during data output.
Figure 9.7 Read Unique ID (RUID) Command Sequence
CS#
SCK
SI_IO0
7 6 5 4 3 2 1 0
SO_IO1
63 62 61 60 59 58 57 56 55
Phase
Instruction
Dummy Byte 1
Dummy Byte 4
5 4 3 2 1 0
64 bit Unique Serial Number
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
Figure 9.8 Read Unique ID (RUID) QPI Mode Command
CS#
SCLK
IO0
4
0
60 56
4
IO1
5
1
61 57
IO2
6
2
62 58
IO3
7
3
63 59
Phase
InstructionDummy 1Dummy 2Dummy 3
Document Number: 002-00124 Rev. *A
8
4
0
5
9
5
1
6
10
6
2
7
11
7
3
Dummy 13
Dummy 14
Dummy 15
Dummy 16 64 bit Unique Serial Number
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9.3
9.3.1
S25FL256L
Register Access Commands
Read Status Register-1 (RDSR1 05h)
The Read Status Register-1 (RDSR1) command allows the Status Register-1 contents to be read from SO/IO1.
The volatile version of Status Register-1 (SR1V) contents may be read at any time, even while a program, erase, or write operation
is in progress. It is possible to read Status Register-1 continuously by providing multiples of eight clock cycles. The status is updated
for each eight cycle read.
Figure 9.9 Read Status Register-1 (RDSR1) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
7
Phase
6
5
4
Instruction
3
2
1
0
7
6
5
Status
4
3
2
1
0
Updated Status
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3. In QPI mode the read status register can be supported up to 108MHz clock frequency. To read Status Register-1
above 108Mhz use the Read Any Register command, see Section 9.3.14, Read Any Register (RDAR 65h) on page 92.
Figure 9.10 Read Status Register-1 (RDSR1) QPI Mode Command
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
9.3.2
Instruct.
Status
Updated Status
Updated Status
Read Status Register-2 (RDSR2 07h)
The Read Status Register-2 (RDSR2) command allows the Status Register-2 contents to be read from SO/IO1.
The volatile Status Register-2 SR2V contents may be read at any time, even while a program, erase, or write operation is in
progress. It is possible to read the Status Register-2 continuously by providing multiples of eight clock cycles. The status is updated
for each eight cycle read.
Figure 9.11 Read Status Register-2 (RDSR2) Command
CS#
SCK
SI_IO0
7
6
5 4
3
2
SO_IO1
Phase
1
0
7
Instruction
6 5
4
3
Status
2
1
0
7 6
5
4
3
2
1
0
Updated Status
In QPI mode, status register 2 may be read via the Read Any Register command, see Section 9.3.14, Read Any Register (RDAR
65h) on page 92.
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9.3.3
S25FL256L
Read Configuration Registers (RDCR1 35h) (RDCR2 15h) (RDCR3 33h)
The Read Configuration Register (RDCR1, RDCR2, RDCR3) commands allows the volatile Configuration Registers (CR1V, CR2V,
CR3V) contents to be read from SO/IO1.
It is possible to read CR1V, CR2V and CR3V continuously by providing multiples of eight clock cycles. The Configuration Registers
contents may be read at any time, even while a program, erase, or write operation is in progress. To read the Configuration Register1, 2 and 3 at higher frequencies use the read any register command, see Section 9.3.14, Read Any Register (RDAR 65h)
on page 92.
Figure 9.12 Read Configuration Register (RDCR1) (RDCR2) (RDCR3) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
7
6
Instruction
5
4
3
2
1
0
7
Register Read
6
5
4
3
2
1
0
Repeat Register Read
In QPI mode, configuration register 1, 2 and 3 may be read via the Read Any Register command, see Section 9.3.14, Read Any
Register (RDAR 65h) on page 92.
9.3.4
Write Registers (WRR 01h)
The Write Registers (WRR) command allows new values to be written to the Status Register 1, Configuration Register 1,
Configuration Register 2 and Configuration Register 3. Before the Write Registers (WRR) command can be accepted by the device,
a Write Enable (WREN) or Write Enable for Volatile Registers (WRENV) command must be received. After the Write Enable
(WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) in the Status Register to
enable non-volatile write operations and direct the values in the following WRR command to the non-volatile SR1NV, CR1NV,
CR2NV and CR3NV registers. After the Write Enable for Volatile Registers (WRENV) command has been decoded successfully, the
device directs the values in the following WRR command to the volatile SR1V, CR1V, CR2V and CRV3 registers.
The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI/IO0. The Status Register is one
data byte in length.
A WRR operation directed to non-volatile registers by a preceding WREN command, first erases non-volatile registers then
programs the new value as a single operation, then copies the new non-volatile values to the volatile version of the registers. A WRR
operation directed to volatile registers by a preceding WRENV command, updates the volatile registers without affecting the related
non-volatile register values. The Write Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR
operation. See Section 7.6.1.3, Status Register 2 Volatile (SR2V) on page 50 for a description of the error bits. The device hangs
busy until clear status register (CLSR) is used to clear the error and WIP for return to standby. Any Status or Configuration Register
bit reserved for the future must be written as a “0”.
CS# must be driven to the logic high state after the eighth, sixteenth, twenty-fourth, or thirty-second bit of data has been latched. If
not, the Write Registers (WRR) command is not executed. If CS# is driven high after the:
eighth cycle then only the Status Register 1 is written
sixteenth cycle both the Status 1 and Configuration 1 Registers are written;
twenty-fourth cycle Status 1 and Configuration 1 and 2 Registers are written;
thirty-second cycle Status 1and Configuration 1, 2 and 3 Registers are written.
As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated. While the Write
Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit.
The Write-In Progress (WIP) bit is a “1” during the self-timed Write Registers (WRR) operation, and is a “0” when it is completed.
When the Write Registers (WRR) operation is completed, the Write Enable Latch (WEL) is set to a “0”.
The WRR command is protected from a hardware and software reset, the hardware reset and software reset command are ignored
and have no effect on the execution of the WRR command.
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S25FL256L
Figure 9.13 Write Registers (WRR) Command Sequence
CS#
SCK
SI_IO0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SO_IO1
Phase
Instruction
Input Status Register-1
Input Conf Register-1
Input Conf Register-2
Input Conf Register-3
This command is also supported in QPI mode. In QPI mode the instruction and data is shifted in on IO0-IO3.
Figure 9.14 Write Register (WRR) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Input Status 1
Input Config 1
Input Config 2
Input Config 3
The Write Registers (WRR) command allows the user to change the values of the Legacy Block Protection bits in either the nonvolatile Status Register 1 or in the volatile Status Register 1, to define the size of the area that is to be treated as read-only.
The Write Registers (WRR) command also allows the user to set the Status Register Protect 0 (SRP0) bit to a “1” or a “0”. The
Status Register Protect 0 (SRP0) bit and Write Protect (WP#) signal allow the BP bits to be hardware protected.
When the Status Register Protect 0 (SRP0 SR1V[7]) bit is a “0”, it is possible to write to the Status Register provided that the WREN
or WRENV command has previously been sent, regardless of whether Write Protect (WP#) signal is driven to the logic high or logic
low state.
When the Status Register Protect 0 (SRP0) bit is set to a “1”, two cases need to be considered, depending on the state of Write
Protect (WP#):
If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and Configuration Registers
provided that the WREN or WRENV command has previously been sent before the WRR command.
If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and Configuration
Registers even if the WREN or WRENV command has previously been sent before the WRR command. Attempts to write
to the Status and Configuration Registers are rejected, not accepted for execution, and no error indication is provided. As a
consequence, all the data bytes in the memory area that are protected by the Legacy Block Protection bits of the Status
Register, are also hardware protected by WP#.
Note: It is recommended not to change Write Protect WP# signal during a command cycle because it may The WP# hardware
protection can be provided:
by setting the Status Register Protect 0 (SRP0) bit after driving Write Protect (WP#) signal to the logic low state;
or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Protect 0 (SRP0) bit to a “1”.
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high state. If WP# is
permanently tied high, hardware protection of the BP bits can never be activated.
Hardware protection is disabled when Quad Mode is enabled (CR1V[1] = 1) or QPI mode is enabled (CR2V[3] =1) because WP#
becomes IO2; therefore, it cannot be utilized.
See Section 8.5, Status Register Protect (SRP1, SRP0) on page 64 for a table showing the SRP and WP# control of Status and
Configuration protection.
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9.3.5
S25FL256L
Write Enable (WREN 06h)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1V[1]) to a “1”. The Write
Enable Latch (WEL) bit must be set to a “1” by issuing the Write Enable (WREN) command to enable write, program and erase
commands.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0. Without CS#
being driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0, the write enable
operation will not be executed.
Figure 9.15 Write Enable (WREN) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.16 Write Enable (WREN) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.3.6
Instruction
Write Disable (WRDI 04h)
The Write Disable (WRDI) command clears the Write Enable Latch (WEL) bit of the Status Register-1 (SR1V[1]) to a “0”.
The Write Enable Latch (WEL) bit may be cleared to a “0” by issuing the Write Disable (WRDI) command to disable Page Program
(PP, 4PP, QPP, 4QPP), Sector Erase (SE), Half Block Erase (HBE), Block Erase (BE), Chip Erase (CE), Write Registers (WRR or
WRAR), Security Region Erase (SECRE), Security Region Program (SECRP), and other commands, that require WEL be set to “1”
for execution. The WRDI command can be used by the user to protect memory areas against inadvertent writes that can possibly
corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0. Without CS#
being driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0, the write disable
operation will not be executed.
Figure 9.17 Write Disable (WRDI) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Document Number: 002-00124 Rev. *A
Instruction
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S25FL256L
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.18 Write Disable (WRDI) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.3.7
Instruction
Write Enable for Volatile Registers (WRENV 50h)
The volatile SR1V, CR1V, CR2V and CR3V registers described in Section 7.6, Registers on page 48, can be written by sending the
WRENV command followed by the WRR command. This gives more flexibility to change the system configuration and memory
protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the status or
configuration non-volatile register bits. The WRENV command will not set the Write Enable Latch (WEL) bit, WRENV is used only to
direct the following WRR command to change the volatile status and configuration register bit values.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0. Without CS#
being driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0, the write enable
operation will not be executed.
Figure 9.19 Write Enable for Volatile Registers (WRENV) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.20 Write Enable for Volatile Registers (WRENV) Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00124 Rev. *A
3
Instruction
Page 88 of 145
ADVANCE
9.3.8
S25FL256L
Clear Status Register (CLSR 30h)
The Clear Status Register command clears the WIP (SR1V[0]), WEL (SR1V[1]), P_ERR (SR2V[5]), and E_ERR (SR2V[6]) bits to
“0”. It is not necessary to set the WEL bit before a Clear Status Register command is executed. The Clear Status Register command
will be accepted even when the device remains busy with WIP set to 1, as the device does remain busy when either error bit is set.
Figure 9.21 Clear Status Register (CLSR) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.22 Clear Status Register (CLSR) QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.3.9
Instruction
Program DLRNV (PDLRNV 43h)
Before the Program DLRNV (PDLRNV) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the
Write Enable Latch (WEL) to enable the PDLRNV operation.
The PDLRNV command is entered by shifting the instruction and the data byte on SI/IO0.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the PDLRNV command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PDLRNV operation is initiated. While the PDLRNV
operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In
Progress (WIP) bit is a “1” during the self-timed PDLRNV cycle, and a is 0 when it is completed. The PDLRNV operation can report
a program error in the P_ERR bit of the status register. When the PDLRNV operation is completed, the Write Enable Latch (WEL) is
set to a “0”. The maximum clock frequency for the PDLRNV command is 133 MHz.
Figure 9.23 Program DLRNV (PDLRNV) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Input Data
This command is also supported in QPI mode. In QPI mode the instruction and data is shifted in on IO0-IO3.
Document Number: 002-00124 Rev. *A
Page 89 of 145
ADVANCE
S25FL256L
Figure 9.24 Program DLRNV (PDLRNV) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
IO1
5
1
5
1
IO2
6
2
6
2
IO3
7
3
7
Phase
9.3.10
3
Instruct.
Input Data
Write DLRV (WDLRV 4Ah)
Before the Write DLRV (WDLRV) command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write
Enable Latch (WEL) to enable WDLRV operation.
The WDLRV command is entered by shifting the instruction and the data byte on SI/IO0.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WDLRV command is not
executed. As soon as CS# is driven to the logic high state, the WDLRV operation is initiated with no delays. The maximum clock
frequency for the WDLRV command is 133 MHz.
Figure 9.25 Write DLRV (WDLRV) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Input Data
This command is also supported in QPI mode. In QPI mode the instruction and data is shifted in on IO0-IO3.
Figure 9.26 Write DLRV (WDLRV) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
IO1
5
1
5
1
IO2
6
2
6
2
IO3
7
3
7
3
Phase
Document Number: 002-00124 Rev. *A
Instruct.
Input Data
Page 90 of 145
ADVANCE
9.3.11
S25FL256L
Data Learning Pattern Read (DLPRD 41h)
The instruction 41h is shifted into SI/IO0 by the rising edge of the SCK signal followed by one dummy cycle. This latency period
allows the device’s internal circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0IO3 are “don’t care” and may be high impedance. Then the 8-bit DLP is shifted out on SO/IO1. It is possible to read the DLP
continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command is
133MHz.
Figure 9.27 DLP Read (DLPRD) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
7
Instruction
6
DY
5
4
3
2
1
0
7
Register Read
6
5
4
3
2
1
0
Repeat Register Read
This command is also supported in QPI mode. In QPI mode the instruction is shifted in and returning data out on IO0-IO3.
Figure 9.28 DLP Read (DLPRD) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
9.3.12
Instruct.
Dummy
Register Read
Register Read
Enter 4 Byte Address Mode (4BEN B7h)
The enter 4 Byte Address Mode (4BEN) command sets the volatile Address Length status (ADS) bit (CR2V[0]) to 1 to change all
3 Byte address commands to require 4 Bytes of address. This command will not affect 4 Byte only commands which will still
continue to expect 4 Bytes of address.
To return to 3 Byte Address mode the 4BEX command clears the volatile Address Length bit CR2V[0]=0). The WRAR command can
also clear the volatile Address Length bit CR2V[0]=0). Also, a hardware or software reset may be used to return to the 3 byte
address mode if the non-volatile Address Length bit CR2NV[1] = 0.
Figure 9.29 Enter 4 Byte Address Mode (4BEN B7h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Document Number: 002-00124 Rev. *A
Page 91 of 145
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S25FL256L
Figure 9.30 Enter 4 Byte Address QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.3.13
Instruction
Exit 4 Byte Address Mode (4BEX E9h)
The exit 4 Byte Address Mode (4BEX) command sets the volatile Address Length Status (ADS) bit (CR2V[0]) to 0 to change most
4 Byte address commands to require 3 Bytes of address. This command will not affect 4 Byte only commands which will still
continue to expect 4 Bytes of address.
Figure 9.31 Exit 4 Byte Address Mode (4BEX E9h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.32 Exit 4 Byte Address QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.3.14
Instruction
Read Any Register (RDAR 65h)
The Read Any Register (RDAR) command provides a way to read device registers. The instruction is followed by a 3 or 4 Byte
address (depending on the address length configuration CR2V[0]), followed by a number of latency (dummy) cycles set by
CR3V[3:0]. Then the selected register contents are returned. If the read access is continued the same addressed register contents
are returned until the command is terminated - only one register is read by each RDAR command.
Reading undefined locations provides undefined data.
The RDAR command may be used during embedded operations to read status register-1 (SR1V).
The RDAR command is not used for reading registers that act as a window into a larger array: IBLAR. There are separate
commands required to select and read the location in the array accessed.
The RDAR command will read invalid data from the PASS register locations if the IRP Password protection mode is selected by
programming IRP[2] to 0.
Document Number: 002-00124 Rev. *A
Page 92 of 145
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S25FL256L
Table 9.4 Register Address Map
Byte Address (Hex)
Register Name
000000
SR1NV
000001
N/A
000002
CR1NV
000003
CR2NV
000004
CR3NV
000005
NVDLP
...
N/A
000020
PASS[7:0]
Description
Non-volatile Status and Configuration Registers
Reading of Non-volatile Status and Configuration Registers actually reads the
volatile registers
000021
PASS[15:8]
000022
PASS[23:16]
000023
PASS[31:24]
000024
PASS[39:32]
000025
PASS[47:40]
000026
PASS[55:48]
000027
PASS[63:56]
Non-volatile Password Register
...
N/A
000030
IRP[7:0]
000031
IRP[15:8]
Non-volatile
...
N/A
000039
PRPR[A15:A8]
Pointer Region Protection Register A15:A8
00003A
PRPR[A23:A16]
Pointer Region Protection Register A23:A16
00003B
PRPR[A31:A24]
Pointer Region Protection Register A31:A24
...
N/A
800000
SR1V
800001
SR2V
800002
CR1V
800003
CR2V
800004
CR3V
800005
VDLP
...
N/A
Volatile Status and Configuration Registers
800040
PR
...
N/A
Volatile Protection Register
Figure 9.33 Read Any Register Read Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
7
Instruction
Address
Dummy Cycles
6
5
4
3
2
1
0
Data
Note
1. A = MSB of address = 23 for Address length CR2V[0] = 0, or 31 for CR2V[0]=1.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in and returning data out on IO0IO3.
Document Number: 002-00124 Rev. *A
Page 93 of 145
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S25FL256L
Figure 9.34 Read Any Register, QPI Mode, Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
Data
Data
Data
Data
Note
1. A = MSB of address = 23 for Address length CR2V[0] = 0, or 31 for CR2V[0]=1
9.3.15
Write Any Register (WRAR 71h)
The Write Any Register (WRAR) command provides a way to write any device register - non-volatile or volatile. The instruction is
followed by a 3 or 4 Byte address (depending on the address length configuration CR2V[0]), followed by one byte of data to write in
the address selected register.
The S25FL256L device must have 4 Byte addressing enabled (CR2V[0] = 1) to set the Pointer Region Protection register PRPR
(see Section 7.6.9 on page 60).
Before the WRAR command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the
device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit in SR1V may be
checked to determine when the operation is completed. The P_ERR and E_ERR bits in SR2V may be checked to determine if any
error occurred during the operation.
Some registers have a mixture of bit types and individual rules controlling which bits may be modified. Some bits are read only,
some are OTP.
Read only bits are never modified and the related bits in the WRAR command data byte are ignored without setting a program or
erase error indication (P_ERR or E_ERR in SR2V). Hence, the value of these bits in the WRAR data byte do not matter.
OTP bits may only be programmed to the level opposite of their default state. Writing of OTP bits back to their default state is
ignored and no error is set.
Non-volatile bits which are changed by the WRAR data, require non-volatile register write time (tW) to be updated. The update
process involves an erase and a program operation on the non-volatile register bits. If either the erase or program portion of the
update fails the related error bit in SR2V and WIP in SR1V will be set to 1.
Volatile bits which are changed by the WRAR data, require the volatile register write time (tCS) to be updated.
Status Register-1 may be repeatedly read (polled) to monitor the Write-In-Progress (WIP) bit (SR1V[0]) to determine when the
register write is completed and Status Register-2 for the error bits (SR2V[6,5]) to determine if there is write failure. If there is a write
failure, the clear status command is used to clear the error status and enable the device to return to standby state. When the WRAR
operation is completed, the Write Enable Latch (WEL) is set to a “0”
However, the PR register can not be written by the WRAR command. The PR register contents are treated as read only bits. Only
the NVLOCK Bit Write (PRL) command can write the PR register.
The WRAR command to write the SR1NV, CR1NV CR2NV and CR3NV is protected from a hardware and software reset, the WRAR
command to all other register are reset from a hardware or software reset.
The WRAR command sequence and behavior is the same as the PP or 4PP command with only a single byte of data provided. See
Section 9.5.2, Page Program (PP 02h or 4PP 12H) on page 106.
The address map of the registers is the same as shown for Table 9.4, Register Address Map on page 93.
Document Number: 002-00124 Rev. *A
Page 94 of 145
ADVANCE
9.3.16
S25FL256L
Set Burst Length (SBL 77h)
The Set Burst Length (SBL) command is used to configure the Burst Wrap feature. Burst Wrap is used in conjunction with Quad I/O
Read and DDR Quad I/O Read, in QIO or QPI modes, to access a fixed length and alignment of data. Certain applications can
benefit from this feature by improving the overall system code execution performance. The Burst Wrap feature allows applications
that use cache, to start filling a cache line with instruction or data from a critical address first, then fill the remainder of the cache line
afterwards within a fixed length (8/16/32/64-bytes) of data, without issuing multiple read commands.
The Set Burst Length command is initiated by driving the CS# pin low and then shifting the instruction code “77h” followed by 24
dummy bits and 8 “Wrap Length Bits (WL[7]-WL[0])”. The command sequence is shown in Figure 9.35, Set Burst Length Command
Sequence Quad I/O Mode on page 96 and Figure 9.36, Set Burst Length Command Sequence QPI Mode on page 96. Wrap
Length bit WL[7] and the lower nibble WL[3:0] are not used. See Configuration Register 3 (CR3V[6:4]) for the encoding of WL[6]WL[4] in Section 7.6.4, Configuration Register 3 on page 55.
Once WL[6:4] is set by a Set Burst Length command, all the following “Quad I/O Read” commands will use the WL[6:4] setting to
access the 8/16/32/64-byte section of data. Note, Configuration Register 1 Quad bit CR1V[1] or Configuration Register 2 QPI bit
CR2V[3] must be set to 1 in order to use the Quad I/O read and Set Burst Length commands. To exit the “Wrap Around” function and
return to normal read operation, another Set Burst with Wrap command should be issued to set WL4 = 1. The default value of
WL[6:4] upon power on, hardware or software reset as set in the CR2NV[6:5]. Use WRR or WRAR command to set the default wrap
length in CR2NV[6;2].
The Set Burst Length (SBL) command writes only to CR3V[6:4] bits to enable or disable the wrapped read feature and set the wrap
boundary. The SBL command cannot be used to set the read latency in CR3V[3:0]. The WRAR command must be used to set the
read latency in CR3V or CR3NV.
See Table 9.5, Example Burst Wrap Sequences on page 95 for CR3V[6:5] values for wrap boundary's and start address. When
enabled the wrapped read feature changes the related read commands from sequentially reading until the command ends, to
reading sequentially wrapped within a group of bytes.
When the wrap mode is not enabled (Table 7.15 and Table 7.18), an unlimited length sequential read is performed.
When the wrap mode is enabled (Table 7.15 and Table 7.18) a fixed length and aligned group of 8, 16, 32, or 64 bytes is read
starting at the byte address provided by the read command and wrapping around at the group alignment boundary.
The group of bytes is of length and aligned on an 8, 16, 32, or 64 byte boundary. CR3V[6:5] selects the boundary. See
Section 7.6.4.2, Configuration Register 3 Volatile (CR3V) on page 57.
The starting address of the read command selects the group of bytes and the first data returned is the addressed byte. Bytes are
then read sequentially until the end of the group boundary is reached. If the read continues the address wraps to the beginning of the
group and continues to read sequentially. This wrapped read sequence continues until the command is ended by CS# returning
high.
Table 9.5 Example Burst Wrap Sequences
CR3V Value
(Hex)
Wrap Boundary
(Bytes)
Start Address
(Hex)
1X
Sequential
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ...
00
8
XXXXXX00
00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ...
00
8
XXXXXX07
07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ...
01
16
XXXXXX02
02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, ...
01
16
XXXXXX0C
0C, 0D, 0E, 0F, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, ...
Address Sequence (Hex)
02
32
XXXXXX0A
0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, 03, 04, 05, 06, 07,
08, 09, 0A, 0B, 0C, 0D, 0E, 0F, ...
02
32
XXXXXX1E
1E, 1F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, ...
03
64
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20,
21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E,
3F, 00, 01, 02, ...
03
64
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B,
0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
2A, 2B, 2C, 2D,, ...
Document Number: 002-00124 Rev. *A
Page 95 of 145
ADVANCE
S25FL256L
The power-on reset, hardware reset, or software reset default burst length can be changed by programming CR3NV with the desired
value using the WRAR command.
Figure 9.35 Set Burst Length Command Sequence Quad I/O Mode
CS
SCLK
IO0
7
6
5
4
X
X
X
X
X
X
WL4
X
IO1
X
X
X
X
X
X
WL5
X
IO2
X
X
X
X
X
X
WL6
X
IO3
X
X
X
X
X
X
X
X
Phase
3
2
1
0
Instruction
Don't Care
Wrap
Figure 9.36 Set Burst Length Command Sequence QPI Mode
CS
SCLK
IO0
4
0
X
X
X
X
X
X
WL4
X
IO1
5
1
X
X
X
X
X
X
WL5
X
IO2
6
2
X
X
X
X
X
X
WL6
X
IO3
7
3
X
X
X
X
X
X
X
X
Phase
9.3.17
Instruct.
Don't Care
Wrap
Enter QPI Mode (QPIEN 38h)
The enter QPI Mode (QPIEN) command enables the QPI mode by setting the volatile QPI bit (CR2V[3]=1). See Table 7.10,
Configuration Register 2 Volatile (CR2V) on page 54. The time required to enter QPI Mode is tQEN, see Table 5.4, SDR AC
Characteristics on page 33, no other commands are allowed during the tQEN transition time to QPI mode.
To return to SPI mode the QPIEX command or a write to register (CR2V[3]=0) is required. A power on reset, hardware, or software
reset will also return the part to SPI mode if the Non-volatile QPI (CR2NV[3]=0). See Table 7.8, Configuration Register 2 Non-volatile
(CR2NV) on page 53.
Figure 9.37 Enter QPI Mode (QPIEN 38h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Document Number: 002-00124 Rev. *A
Instruction
Page 96 of 145
ADVANCE
9.3.18
S25FL256L
Exit QPI Mode (QPIEX F5h)
The exit QPI Mode (QPIEX) command disables the QPI mode by setting the volatile QPI bit (CR2V[3]=0) and returning to SPI mode.
See Table 7.10, Configuration Register 2 Volatile (CR2V) on page 54. The time required to exit QPI Mode is tQEX, see Table 5.4,
SDR AC Characteristics on page 33, no other commands are allowed during the tQEX transition time to exit the QPI mode.
Figure 9.38 Exit QPI (QPIEX F5h) Command Sequence
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
9.4
3
Instruction
Read Memory Array Commands
Read commands for the main Flash array provide many options for prior generation SPI compatibility or enhanced performance SPI:
Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands
(SDR).
Some SDR commands transfer address one bit per falling edge of SCK and return data 1bit of data per rising edge of SCK.
These are called Single width commands.
Some SDR commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called Dual I/O for 2
bit, Quad I/O, and QPI for 4 bit. QPI also transfers instructions 4 bits per rising edge.
Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called Double Data
Rate (DDR) commands.
There are DDR commands for 4 bits of address or data per SCK edge. These are called Quad I/O DDR and QPI DDR for 4
bit per edge transfer.
All of these commands, except QPI Read, begin with an instruction code that is transferred one bit per SCK rising edge. QPI Read
transfers the instruction 4 bits per SCK rising edge.The instruction is followed by either a 3 or 4 byte address transferred at SDR or
DDR. Commands transferring address or data 2 or 4 bits per clock edge are called Multiple I/O (MIO) commands. For FL-L family
devices at 256Mb or higher density, the traditional SPI 3 byte addresses are unable to directly address all locations in the memory
array. Separate 4 Byte address read commands are provided for access to the entire address space. These devices may be
configured to take a 4 byte address from the host system with the traditional 3 byte address commands. The 4 byte address mode
for traditional commands is activated by setting the Address Length bit in configuration register 2 to “1”. The Dual I/O, Quad I/O and
QPI commands provide a performance improvement option controlled by mode bits that are sent following the address bits. The
mode bits indicate whether the command following the end of the current read will be another read of the same type, without an
instruction at the beginning of the read. These mode bits give the option to eliminate the instruction cycles when doing a series of
Dual or Quad read accesses.
Some commands require delay cycles following the address or mode bits to allow time to access the memory array - read latency.
The delay or read latency cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus any data
provided by the host during these cycles is “don’t care” and the host may also leave the SI signal at high impedance during the
dummy cycles. When MIO commands are used the host must stop driving the IO signals (outputs are high impedance) before the
end of last dummy cycle. When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The
number of dummy cycles varies with the SCK frequency or performance option selected via the Configuration Register 2
(CR3V[3:0]) Latency Code. Dummy cycles are measured from SCK falling edge to next SCK falling edge. SPI outputs are
traditionally driven to a new value on the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the
memory on the same falling edge of SCK that the host stops driving address or mode bits.
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The DDR commands may optionally have an 8 edge Data Learning Pattern (DLP) driven by the memory, on all data outputs, in the
dummy cycles immediately before the start of data. The DLP can help the host memory controller determine the phase shift from
SCK to data edges so that the memory controller can capture data at the center of the data eye.
When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides 1 or more dummy cycles should be
selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict.
When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to allow 1
cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP.
Each read command ends when CS# is returned High at any point during data return. CS# must not be returned High during the
mode or dummy cycles before data returns as this may cause mode bits to be captured incorrectly; making it indeterminate as to
whether the device remains in continuous read mode.
9.4.1
Read (Read 03h or 4READ 13h)
The instruction
03h (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
03h (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
13h is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, are shifted out on SO/IO1.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 9.39 Read Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
SO_IO1
Phase
1
0
7
Instruction
6
Address
5
4
3
2
1
0
Data 1
7
6
5
4
3
2 1
0
Data N
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 13h.
9.4.2
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)
The instruction
0Bh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
0Bh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR3V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on SO/IO1 is “don’t care” and may be high impedance. Then the memory contents, at the address given, are shifted out on
SO/IO1.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
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Figure 9.40 Fast Read (FAST_READ) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
7
6
5
4
3
2
1
0
IO2-IO3
Phase
Instruction
Address
Dummy Cycles
Data 1
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 0Ch.
9.4.3
Dual Output Read (DOR 3Bh or 4DOR 3Ch)
The instruction
3Bh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
3Bh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
3Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR3V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on IO0 (SI) and IO1 (S0) is “don’t care” and may be high impedance.
Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO). Two bits are shifted
out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
For Dual Output Read commands, there are dummy cycles required after the last address bit is shifted into IO0 (SI) before data
begins shifting out of IO0 and IO1.
Figure 9.41 Dual Output Read Command Sequence
CS#
SCK
IO0
7
6
5
4
3
2
1
0
A
1
0
IO1
Phase
Instruction
Address
Dummy Cycles
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
Data 1
Data 2
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 3Ch.
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9.4.4
S25FL256L
Quad Output Read (QOR 6Bh or 4QOR 6Ch)
The instruction
6Bh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
6Bh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
6Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR3V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on IO0 - IO3 is “don’t care” and may be high impedance.
Then the memory contents, at the address given, is shifted out four bits at a time through IO0 - IO3. Each nibble (4 bits) is shifted out
at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
For Quad Output Read commands, there are dummy cycles required after the last address bit is shifted into IO0 before data begins
shifting out of IO0 - IO3.
Figure 9.42 Quad Output Read Command Sequence
CS#
SCK
IO0
4 0
4 0
4 0
4 0
4 0 4
IO1
5 1
5 1
5 1
5 1
5 1
5
IO2
6 2
6 2
6 2
6 2
6 2
6
IO3
7 3
7 3
7 3
7 3
7 3
7
D1
D2
D3
D4
D5
Phase
7
6 5
4 3
2 1
Instruction
0 A
1 0
Address
Dummy
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command 6Ch.
9.4.5
Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
BBh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
BBh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This command takes input of the
address and returns read data two bits per SCK rising edge. In some applications, the reduced address input and data output time
might allow for code execution in place (XIP) i.e. directly from the memory device.
The Dual I/O Read command has continuous read mode bits that follow the address so, a series of Dual I/O Read commands may
eliminate the 8 bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the following
command will also be a Dual I/O Read command. The first Dual I/O Read command in a series starts with the 8 bit instruction,
followed by address, followed by four cycles of mode bits, followed by an optional latency period. If the mode bit pattern is Axh the
next command is assumed to be an additional Dual I/O Read command that does not provide instruction bits. That command starts
with address, followed by mode bits, followed by optional latency.
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Variable latency may be added after the mode bits are shifted into SI and SO before data begins shifting out of IO0 and IO1. This
latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the
dummy cycles, the data value on SI and SO are “don’t care” and may be high impedance. The number of dummy cycles is
determined by the frequency of SCK. The latency is configured in CR3V[3:0].
The continuous read feature removes the need for the instruction bits in a sequence of read accesses and greatly improves code
execution (XIP) performance. The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read command
through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”)
and may be high impedance. If the Mode bits equal Axh, then the device remains in Dual I/O Continuous Read Mode and the next
address can be entered (after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in
Figure 9.44; thus, eliminating eight cycles of the command sequence. The following sequences will release the device from Dual I/O
Continuous Read mode; after which, the device can accept standard SPI commands:
1. During the Dual I/O continuous read command sequence, if the Mode bits are any value other than Axh, then the next
time CS# is raised high the device will be released from Dual I/O conti nous read mode.
2. Send the Mode Reset command.
Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial address after the last
address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock
speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is
allowed and may be helpful in preventing I/O signal contention, for the host system to turn off the I/O signal outputs (make them high
impedance) during the last two “don’t care” mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1
(SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Figure 9.43 Dual I/O Read Command Sequence
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
0 A-1
A
Phase
Instruction
2
0
6
4
2
0
6
4
2
0
6
4
2
0
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Address
Mode
Dum
Data 1
Data 2
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command BCh.
2. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these cycles to increase bus turn
around time between Mode bits from host and returning data from the memory.
Figure 9.44 Dual I/O Continuous Read Command Sequence
CS#
SCK
IO0
6
4
2
0
A-1
2
0
6
4
2
0
6
4
2
0
6
4
2
0
IO1
7
5
3
1
A
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Phase
Data N
Address
Mode
Dum
Data 1
Data 2
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command BCh.
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9.4.6
S25FL256L
Quad I/O Read (QIOR EBh or 4QIOR ECh)
The instruction,
EBh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
EBh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals IO0-IO3. It allows input of the address bits four bits per
serial SCK clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from FL-L
family devices. The QUAD bit of the Configuration Register 1 must be set (CR1V[1]=1) or the QPI bit of Configuration Register 2
must be set (CR2V[1]=1 to enable the Quad capability of FL-L family devices.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data begins shifting out of
IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to access data at the initial
address. During latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. The number of dummy
cycles is determined by the frequency of SCK. The latency is configured in CR3V[3:0].
Following the latency period, the memory contents at the address given, is shifted out four bits at a time through IO0-IO3. Each
nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through the setting of the
Mode bits (after the address sequence, as shown in Figure 9.45 on page 103. This added feature removes the need for the
instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of
the next Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the
Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode and
the next address can be entered (after CS# is raised high and then asserted low) without requiring the EBh or ECh instruction, as
shown in Figure 9.47 on page 103; thus, eliminating eight cycles for the command sequence. The following sequences will release
the device from Quad I/O High Performance Read mode; after which, the device can accept standard SPI commands:
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is
raised high the device will be released from Quad I/O High Performance Read mode.
2. Send the Mode Reset command.
Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal circuitry latency
time to access the initial address after the last address cycle that is clocked into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data out clock. At higher
clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished.
It is allowed and may be helpful in preventing IO0-IO3 signal contention, for the host system to turn off the IO0-IO3 signal outputs
(make them high impedance) during the last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
In QPI mode (CR2V[3]=1) the Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the command protocol is
identical to the Quad I/O commands.
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Figure 9.45 Quad I/O Read Initial Access Command Sequence
CS#
SCLK
IO0
7
6
5
0 A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
A
7
3
7
3
7
3
7
3
7
3
7
3
Phase
4
3
2
1
Instruction
Address Mode
Dummy
D1
D2
D3
D4
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command ECh.
Figure 9.46 Quad I/O Read Initial Access Command Sequence QPI mode
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command ECh.
Figure 9.47 Continuous Quad I/O Read Command Sequence
CS#
SCK
IO0
4
0
4
0
A-3
4
0
4
0
4
0
4
0
6
4
2
0
IO1
5
1
5
1
A-2
5
1
5
1
5
1
5
1
7
5
3
1
IO2
6
2
6
2
A-1
6
2
6
2
6
2
6
1
7
5
3
1
IO3
7
3
7
3
A
7
3
7
3
7
3
7
1
7
5
3
1
Phase
DN-1
DN
Address
Mode
Dummy
D1
D2
D3
D4
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command ECh.
2. The same sequence is used in QPI mode.
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9.4.7
S25FL256L
DDR Quad I/O Read (EDh, EEh)
The DDR Quad I/O Read command improves throughput with four I/O signals IO0-IO3. It is similar to the Quad I/O Read command
but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might
allow for code execution (XIP) directly from FL-L Family devices. The QUAD bit of the Configuration Register 1 must be set
(CR1V[1]=1) or the QPI bit of Configuration Register 2 must be set (CR2V[1]=1 to enable the Quad capability of FL-L family devices.
The instruction
EDh (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
EDh (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
EEh is followed by a 4-byte address (A31-A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four
bits at a time on each clock edge through IO0-IO3.
The maximum operating clock frequency for DDR Quad I/O Read command is 66 MHz.
For DDR Quad I/O Read, there is a latency required after the last address and mode bits are shifted into the IO0-IO3 signals before
data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access
the initial address. During these latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. When the
Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must
be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR3V[3:0].
Mode bits allow a series of Quad I/O DDR commands to eliminate the 8 bit instruction after the first command sends a
complementary mode bit pattern. This feature removes the need for the eight bit SDR instruction sequence and dramatically reduces
initial access times (improves XIP performance). The Mode bits control the length of the next DDR Quad I/O Read operation through
the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are
complementary (i.e. 5h and Ah) the device transitions to Continuous DDR Quad I/O Read Mode and the next address can be
entered (after CS# is raised high and then asserted low) without requiring the EDh or EEh instruction, thus eliminating eight cycles
from the command sequence. The following sequences will release the device from Continuous DDR Quad I/O Read mode; after
which, the device can accept standard SPI commands:
1. During the DDR Quad I/O Read Command Sequence, if the Mode bits are not complementary the next time CS# is raised
high and then asserted low the device will be released from DDR Quad I/O Read mode.
2. Send the Mode Reset command.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. Note that the memory
devices may drive the IOs with a preamble prior to the first data value. The preamble is a Data Learning Pattern (DLP) that is used
by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus for the four clock cycles
immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts
outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to
when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the
preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read
operation. The optimized capture point will be determined during the preamble period of every read operation. This optimization
strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
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Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h
(or 00110100) will be driven on each of the active outputs (i.e. all four IOs). This pattern was chosen to cover both “DC” and “AC”
data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks) followed by a
high going transition (001) and the complementary low going transition (110). The two AC transition scenarios include data low for a
short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). The
DC transitions will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully settled
to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC
transitions will bound the ending of the data valid period. These transitions will allow the host controller to identify the beginning and
ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be chosen. See
Section 7.6.10, DDR Data Learning Registers on page 61 for more details.
In QPI mode (CR2V[3]=1) the DDR Quad I/O instructions are sent 4 bits at SCK rising edge. The remainder of the command
protocol is identical to the DDR Quad I/O commands.
Figure 9.48 DDR Quad I/O Read Initial Access
CS#
SCK
IO0
A-3
8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
7
6
5
A-2
9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
A-1
10 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
A
11 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1
D2
\Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command EEh
2. Example DLP of 34h (or 00110100)
Figure 9.49 DDR Quad I/O Read Initial Access QPI Mode
CS#
SCLK
IO0
4
0
A-3
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
5
1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
6
2
A-1
10
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
7
3
A
11
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
DLP
D1
D2
Note:
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command EEh.
2. Example DLP of 34h (or 00110100).
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Figure 9.50 Continuous DDR Quad I/O Read Subsequent Access
CS#
SCK
IO0
A-3
8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
1
IO1
A-2
9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
2
IO2
A-1
10
6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
A
11
7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Address
Mode
Dummy
DLP
D1
D2
Note:
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1 or command EEh.
2. The same sequence is used in QPI mode.
3. Example DLP of 34h (or 00110100).
9.5
Program Flash Array Commands
9.5.1
9.5.1.1
Program Granularity
Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move
data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single
programming command. Page Programming allows up to a page size 256 bytes to be programmed in one operation. The page is
aligned on the page size address boundary. It is possible to program from one bit up to a page size in each Page programming
operation. For the very best performance, programming should be done in full pages of 256 bytes aligned on 256 byte boundaries
with each Page being programmed only once.
9.5.1.2
Single Byte Programming
Single Byte Programming allows full backward compatibility to the legacy standard SPI Page Programming (PP) command by
allowing a single byte to be programmed anywhere in the memory array.
9.5.2
Page Program (PP 02h or 4PP 12H)
The Page Program (PP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). Before the Page
Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the
device. After the Write Enable (WREN) command has been decoded successfully, the device sets the Write Enable Latch (WEL) in
the Status Register to enable any write operations.
The instruction
02h (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
02h (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
12h is followed by a 4-byte address (A31-A0)
and at least one data byte on SI/IO0. Up to a page can be provided on SI/IO0 after the 3-byte address with instruction 02h or 4-byte
address with instruction 12h has been provided. As with the write and erase commands, the CS# pin must be driven high after the
eighth bit of the last byte has been latched. If this is not done the Page Program command will not be executed. After CS# is driven
high, the self-timed Page Program command will commence for a time duration of tPP.
Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall programming time
versus loading less than a page into the program buffer.
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The programming process is managed by the Flash memory device internal control logic. After a programming command is issued,
the programming operation status can be checked using the Read Status Register-1 command. The WIP bit (SR1V[0]) will indicate
when the programming operation is completed. The P_ERR bit (SR2V[5]) will indicate if an error occurs in the programming
operation that prevents successful completion of programming. This includes attempted programming of a protected area.
Figure 9.51 Page Program (PP 02h or 4PP 12h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Address
Input Data 1
Input Data 2
Note
1. A = MSB of address = A23 for PP 02h with CR2V[0]=0, or A31 for PP 02h with CR2V[0]=1, or for 4PP 12h.
This command is also supported in QPI mode. In QPI mode the instruction, address and data is shifted in on IO0-IO3.
Figure 9.52 Page Program (PP 02h or 4PP 12h) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Input D1
Input D2
Input D3
Input D4
Note
1. A = MSB of address = A23 for PP 02h with CR2V[0]=0, or A31 for PP 02h with CR2V[0]=1, or for 4PP 12h.
9.5.3
Quad Page Program (QPP 32h or 4QPP 34h)
The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). The
Quad-input Page Program (QPP) command allows up to a page of data to be loaded into the Page Buffer using four signals: IO0IO3. QPP can improve performance for PROM Programmer and applications that have slower clock speeds (< 12 MHz) by loading 4
bits of data per clock cycle. Systems with faster clock speeds do not realize as much benefit for the QPP command since the
inherent page program time becomes greater than the time it takes to clock-in the data. The maximum frequency for the QPP
command is 133MHz.
To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD=1). A Write Enable command
must be executed before the device will accept the QPP command (Status Register-1, WEL=1).
The instruction
32h (CR2V[0]=0) is followed by a 3-byte address (A23-A0) or
32h (CR2V[0]=1) is followed by a 4-byte address (A31-A0) or
34h is followed by a 4-byte address (A31-A0)
and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory locations.
All other functions of QPP are identical to Page Program. The QPP command sequence is shown in the figure below.
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Figure 9.53 Quad Page Program Command Sequence
CS#
SCK
IO0
7
6
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
Phase
5
4
3
2
1
0
A
Instruction
1
0
Address
Data 1
Data 2
Data 3
Data 4
Data 5
...
Note
1. A = MSB of address = A23 for QPP 32h with CR2V[0]=0, or A31 for QPP 32h with CR2V[0]=1, or for 4QPP 34h.
9.6
Erase Flash Array Commands
9.6.1
Sector Erase (SE 20h or 4SE 21h)
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the Sector Erase (SE)
command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
20h [CR2V[0]=0] is followed by a 3-byte address (A23-A0), or
20h [CR2V[0]=1] is followed by a 4-byte address (A31-A0), or
21h is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of the address has been latched in on SI/IO0.
This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the chosen sector of the
flash memory array. If CS# is not driven high after the last bit of address, the sector erase operation will not be executed.
As soon as CS# is driven high, the internal erase cycle will be initiated. With the internal erase cycle in progress, the user can read
the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a “1”.
when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A SE or 4SE command applied to a sector that has been write protected through the Legacy Block Protection, Individual Block Lock
or Pointer Region Protection will not be executed and will set the E_ERR status.
Figure 9.54 Sector Erase (SE 20h or 4SE 21h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
1. A = MSB of address = A23 for SE 20h with CR2V[0]=0, or A31 for SE 20h with CR2V[0]=1 or for 4SE 21h.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in on IO0-IO3.
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Figure 9.55 Sector Erase (SE 20h or 4SE 21h) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
1. A = MSB of address = A23 for SE 20h with CR2V[0]=0, or A31 for SE 20h with CR2V[0]=1 or for 4SE 21h.
9.6.2
Half Block Erase (HBE 52h or 4HBE 53h)
The Half Block Erase (HBE) command sets all bits in the addressed half block to 1 (all bytes are FFh). Before the Half Block Erase
(HBE) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device,
which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
52h [CR2V[0]=0] is followed by a 3-byte address (A23-A0), or
52h [CR2V[0]=1] is followed by a 4-byte address (A31-A0), or
53h is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been latched in on SI/IO0. This
will initiate the erase cycle, which involves the pre-programming and erase of each sector of the chose block. If CS# is not driven
high after the last bit of address, the half block erase operation will not be executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal erase cycle in progress,
the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate
a “1” when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A Half Block Erase (HBE) command applied to a Block that has been Write Protected through the Legacy Block Protection,
Individual Block Lock or Pointer Region Protection will not be executed and will set the E_ERR status.
If a half block erase command is applied and if any region, sector or block in the half block erase area is protected the erase will not
be executed on the 32 KB range and will set the E_ERR status.
Figure 9.56 Half Block Erase (HBE 52h or 4HBE 53h) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
1. A = MSB of address = A23 for HBE 52h with CR2V[0]=0, or A31 for HBE 52h with CR2V[0]=1 or 4HBE 53h.
2. When A[15]=0 the sectors 0-7 of Block are erased and A[15]=1 then sectors 8-15 of Block are erased.
3. A = MSB of address = A23 for HBE 52h with CR2V[0]=0, or A31 for HBE 52h with CR2V[0]=1 or 4HBE 53h.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in on IO0-IO3.
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Figure 9.57 Half Block Erase (HBE 52h or 4HBE 53h) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
1. A = MSB of address = A23 for HBE 52h with CR2V[0]=0, or A31 for HBE 52h with CR2V[0]=1 or 4HBE 53h.
2. When A[15]=0 the sectors 0-7 of Block are erased and A[15]=1 then sectors 8-15 of Block are erased.
3. A = MSB of address = A23 for HBE 52h with CR2V[0]=0, or A31 for HBE 52h with CR2V[0]=1 or 4HBE 53h.
9.6.3
Block Erase (BE D8h or 4BE DCh)
The Block Erase (BE) command sets all bits in the addressed block to 1 (all bytes are FFh). Before the Block Erase (BE) command
can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
D8h [CR2V[0]=0] is followed by a 3-byte address (A23-A0), or
D8h [CR2V[0]=1] is followed by a 4-byte address (A31-A0), or
DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been latched in on SI/IO0. This
will initiate the erase cycle, which involves the pre-programming and erase of each sector of the chosen block. If CS# is not driven
high after the last bit of address, the block erase operation will not be executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal erase cycle in progress,
the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate
a “1” when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A Block Erase (BE) command applied to a Block that has been Write Protected through the Legacy Block Protection, Individual
Block Lock or Pointer Region Protection will not be executed and will set the E_ERR status.
If a block erase command is applied and if any region or sector area is protected the erase will not be executed on the 64 KB range
and will set the E_ERR status.
Figure 9.58 Block Erase (BE D8h or 4BE DCh) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
1. A = MSB of address = A23 for BE D8h with CR2V[0]=0, or A31 for BE D8h with CR2V[0]=1 or 4BE DCh.
2. A = MSB of address = A23 for BE D8h with CR2V[0]=0, or A31 for BE D8h with CR2V[0]=1 or 4BE DCh.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in on IO0-IO3.
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Figure 9.59 Block Erase (BE D8h or 4BE DCh) QPI Mode Command Sequence
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
1. A = MSB of address = A23 for BE D8h with CR2V[0]=0, or A31 for BE D8h with CR2V[0]=1 or 4BE DCh.
2. A = MSB of address = A23 for BE D8h with CR2V[0]=0, or A31 for BE D8h with CR2V[0]=1 or 4BE DCh.
9.6.4
Chip Erase (CE 60h or C7h)
The Chip Erase (CE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the CE command
can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI/IO0. This will initiate
the erase cycle, which involves the pre-programming and erase of the entire flash memory array. If CS# is not driven high after the
last bit of instruction, the CE operation will not be executed.
As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in progress, the user can
read the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a
“1” when the erase cycle is in progress and a “0” when the erase cycle has been completed.
A CE command will not be executed when the Legacy Block Protection, Individual Block Lock or Pointer Region Protection set to
protect any sector or block and this will set the E_ERR status bit.
Figure 9.60 Chip Erase Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.61 Chip Erase Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *A
Instruction
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9.6.5
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Program or Erase Suspend (PES 75h)
The PES command allows the system to interrupt a programming or erase operation and then read from any other non-erasesuspended sector or non-program-suspended-page. Program or Erase Suspend is valid only during a programming or sector erase,
half block erase or block erase operation. A Chip Erase operation cannot be suspended.
The Write in Progress (WIP) bit in Status Register 1 (SR1V[0]) must be checked to know when the programming or erase operation
has stopped. The Program Suspend Status bit in the Status Register-2 (SR2[0]) can be used to determine if a programming
operation has been suspended or was completed at the time WIP changes to 0. The Erase Suspend Status bit in the Status
Register-2 (SR2[1]) can be used to determine if an erase operation has been suspended or was completed at the time WIP changes
to 0. The time required for the suspend operation to complete is tSL, see Table 5.7, Program or Erase Suspend AC Parameters
on page 38.
An Erase can be suspended to allow a program operation or a read operation. During an erase suspend, the IBL array may be read
to examine sector protection and written to remove or restore protection on a sector to be programmed. The protection bits will not
be rechecked when the operation is resumed so any changes made will not impact current in progress operation.
A program operation may be suspended to allow a read operation.
A new suspend operation is not allowed with-in an already suspended erase or program operation. The suspend command is
ignored in this situation.
Table 9.6 Commands Allowed During Program or Erase Suspend
Instruction Name
Instruction
Code
(Hex)
Allowed
During Erase
Suspend
Allowed
During
Program
Suspend
READ
03
X
X
Comment
All array reads allowed in suspend
RDSR1
05
X
X
Needed to read WIP to determine end of suspend process
RDAR
65
X
X
Alternate way to read WIP to determine end of suspend process
RDSR2
07
X
X
Needed to read suspend status to determine whether the operation is suspended or complete.
RDCR1
35
X
X
Needed to read Configuration Register 1
RDCR2
15
X
X
Needed to read Configuration Register 2
RDCR3
33
X
X
Needed to read Configuration Register 3
RUID
4B
X
X
Needed to read Unique Id
RDID
9F
X
X
Needed to read Device Id
Needed to read Quad Device Id
RDQID
AF
X
X
RSFDP
5A
X
X
Needed to read SFDP
SBL
77
X
X
Needed to set Burst Length
WREN
06
X
X
Required for program command within erase suspend
WRDI
04
X
X
Required for program command within erase suspend
PP
02
X
Required for array program during erase suspend. Only allowed if there is no other program
suspended program operation (SR2V[0]=0). A program command will be ignored while there is
a suspended program. If a program command is sent for a location within an erase suspended
sector the program operation will fail with the P_ERR bit set.
4PP
12
X
Required for array program during erase suspend. Only allowed if there is no other program
suspended program operation (SR2V[0]=0). A program command will be ignored while there is
a suspended program. If a program command is sent for a location within an erase suspended
sector the program operation will fail with the P_ERR bit set.
QPP
32
X
Required for array program during erase suspend. Only allowed if there is no other program
suspended program operation (SR2V[0]=0). A program command will be ignored while there is
a suspended program. If a program command is sent for a location within an erase suspended
sector the program operation will fail with the P_ERR bit set.
4QPP
34
X
Required for array program during erase suspend. Only allowed if there is no other program
suspended program operation (SR2V[0]=0). A program command will be ignored while there is
a suspended program. If a program command is sent for a location within an erase suspended
sector the program operation will fail with the P_ERR bit set.
4READ
13
X
X
All array reads allowed in suspend
CLSR
30
X
X
Clear status may be used if a program operation fails during erase suspend.
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Table 9.6 Commands Allowed During Program or Erase Suspend (Continued)
Instruction Name
Instruction
Code
(Hex)
Allowed
During Erase
Suspend
Allowed
During
Program
Suspend
EPR
7A
X
X
Required to resume from erase or program suspend.
RSTEN
66
X
X
Reset allowed anytime
RST
99
X
X
Reset allowed anytime
FAST_READ
0B
X
X
All array reads allowed in suspend
4FAST_READ
0C
X
X
All array reads allowed in suspend
All array reads allowed in suspend
Comment
DOR
3B
X
X
4DOR
3C
X
X
All array reads allowed in suspend
DIOR
BB
X
X
All array reads allowed in suspend
4DIOR
BC
X
X
All array reads allowed in suspend
IBLRD
3D
X
X
It may be necessary to remove and restore Individual Block Lock during erase suspend to allow
programming during erase suspend.
4IBLRD
E0
X
X
It may be necessary to remove and restore Individual Block Lock during erase suspend to allow
programming during erase suspend.
IBL
36
X
X
It may be necessary to restore Individual Block Lock during erase suspend to allow
programming during erase suspend.
4IBL
E1
X
X
It may be necessary to restore Individual Block Lock during erase suspend to allow
programming during erase suspend.
IBUL
39
X
X
It may be necessary to remove Individual Block Lock during erase suspend to allow
programming during erase suspend.
4IBUL
E2
X
X
It may be necessary to remove Individual Block Lock during erase suspend to allow
programming during erase suspend.
QOR
6B
X
X
Read Quad Output (3 or 4 Byte Address) (1)
4QOR
6C
X
X
Read Quad Output (4 Byte Address)(1)
QIOR
EB
X
X
All array reads allowed in suspend (1)
All array reads allowed in suspend (1)
4QIOR
EC
X
X
DDRQIOR
ED
X
X
All array reads allowed in suspend (1)
DDR4QIOR
ED
X
X
All array reads allowed in suspend (1)
MBR
FF
X
X
May need to reset a read operation during suspend
SECRP
42
X
SECRR
48
X
All Security Regions program allowed in erase suspend
X
All Security Regions reads allowed in suspend
Notes:
1. For all Quad commands the Quad Enable CR1V[1] bit (SeeTable 7.7 on page 52) needs to be set to “1” before initial program or erase, since the WRR/WRAR
commands are not allowed inside of the suspend state.
All command not included in Table 9.6, Commands Allowed During Program or Erase Suspend on page 112 are not allowed during
Erase or Program Suspend. The WRR, WRAR, or SPRP commands are not allowed during Erase or Program Suspend, it is
therefore not possible to alter the Legacy Block Protection bits or Pointer Region Protection during Erase Suspend.
Reading at any address within an erase-suspended sector or program-suspended page produces undetermined data.
After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The system can
determine the status of the program operation by reading the WIP bit in the Status Register, just as in the standard program
operation.
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Figure 9.62 Program or Erase Suspend Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.63 Program or Erase Suspend Command Sequence QPI mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Instruction
Figure 9.64 Program or Erase Suspend Command with Continuing Instruction Commands Sequence
tSL
CS#
SCK
SI_IO0
7 6 5 4 3 2 1 0
SO
Phase
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Suspend Instruction
Phase
9.6.6
7 6 5 4 3 2 1 0
Read Status Instruction
Status
Instr. During Suspend
Repeat Status Read Until Suspended
Erase or Program Resume (EPR 7Ah)
After program or read operations are completed during a program or erase suspend the Erase or Program Resume command is
sent to continue the suspended operation.
After an Erase or Program Resume command is issued, the WIP bit in the Status Register-1 will be set to a 1 and the suspended
operation will resume if one is suspended. If there is no suspended program or erase operation the resume command is ignored.
Program or erase operations may be interrupted as often as necessary e.g. a program suspend command could immediately follow
a program resume command but, but in order for a program or erase operation to progress to completion there must be some
periods of time between resume and the next suspend command greater than or equal to tRNS. See Table 5.7, Program or Erase
Suspend AC Parameters on page 38.
The Program Suspend Status bit in the Status Register-2 (SR2[0]) can be used to determine if a programming operation has been
suspended or was completed at the time WIP changes to 0. The Erase Suspend Status bit in the Status Register-2 (SR2[1]) can be
used to determine if an erase operation has been suspended or was completed at the time WIP changes to 0. See Section 7.6.1.3,
Status Register 2 Volatile (SR2V) on page 50.
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An Erase or Program Resume command must be written to resume a suspended operation.
Figure 9.65 Erase or Program Resume command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.66 Erase or Program Resume command Sequence QPI mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.7
Instruction
Security Regions Array Commands
The Security Regions commands select which region to use by address A15 to A8 as shown below.
Security Region 0: A23-16 = 00h; A15-8 = 00h; A7-0 = byte address
Security Region 1: A23-16 = 00h; A15-8 = 01h; A7-0 = byte address
Security Region 2: A23-16 = 00h; A15-8 = 02h; A7-0 = byte address
Security Region 3: A23-16 = 00h; A15-8 = 03h; A7-0 = byte address
9.7.1
Security Region Erase (SECRE 44h)
The Security Region Erase command erases data in the Security Region, which is in a different address space from the main array
data. The Security Region is 1024 bytes so, the address bits (A24 to A10) must be zero for this command. Each region can be
individually erased. Refer to Section 7.5, Security Regions Address Space on page 47 for details on the Security Region.
Before the Security Region Erase command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit
in SR1V may be checked to determine when the operation is completed. The E_ERR bit in SR2V may be checked to determine if
any error occurred during the operation.
The Security Region Lock Bits (CR1NV[2-5]) in the Configuration Register-1 can be used to protect the Security Regions for erase.
Once a lock bit is set to 1, the corresponding Security Region will be permanently locked, Attempting to erase a region that is locked
will fail with the E_ERR bit in SR2V[6] set to “1”.
When the Protection Register NVLOCK Bit = “0”, Security Regions 2 and 3 are protected from program or erase. Attempting to erase
in a region that locked will fail with the E_ERR bits in SR2V[6] set to “1”. See Section 8.7.2.1, NVLOCK Bit (PR[0]) on page 73.
The Password Protection Mode Lock Bit (IRP[2]) allows regions 2 and 3 to be protected from erase operations until the correct
password is provided to enable erasing of these Security Regions. Attempting to erase in a region that is password locked will fail
with the E_ERR bit in SR2V[6] set to “1”. Security Region Read Password Protection on page 74
The protocol of the Security Region Erase command is the same as the Sector Erase command. See Section 9.6.1, Sector Erase
(SE 20h or 4SE 21h) on page 108 for the command sequence. QPI Mode is supported.
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9.7.2
S25FL256L
Security Region Program (SECRP 42h)
The Security Region Program command programs data in the Security Region, which is in a different address space from the main
array data. The Security Region is 1024 bytes so, the address bits (A24 to A10) must be zero for this command. Refer to
Section 7.5, Security Regions Address Space on page 47 for details on the Security Region.
Before the Security Region Program command can be accepted by the device, a Write Enable (WREN) command must be issued
and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP
bit in SR1V may be checked to determine when the operation is completed. The P_ERR bit in SR2V may be checked to determine if
any error occurred during the operation.
To program the Security Region array in bit granularity, the rest of the bits within a data byte can be set to “1”.
Each region in the Security Region memory space can be programmed one or more times, provided that the region is not locked.
However, for the best data integrity, it is recommended that one or more 16 byte length and aligned groups of bytes be programed
together and programmed only once between erase operations within each region.
The Security Region Lock Bits (CR1NV[2-5]) in the Configuration Register-1 can be used to protect the Security Regions for
Programming. Once a lock bit is set to 1, the corresponding Security Region will be permanently locked. Attempting to program
zeros or ones in a region that is locked (protected) will fail with the P_ERR bit in SR2V[5] set to “1”. Programming ones in a unprotected area does not cause an error and does not set P_ERR. (see Configuration Register 1 on page 51 for detail descriptions).
When the Protection Register NVLOCK Bit = “0”, Security Regions 2 and 3 are protected from program or erase. Attempting to
program in a region that locked will fail with the P_ERR bit in SR2V[5] set to “1”. See Section 8.7.2.1, NVLOCK Bit (PR[0])
on page 73.
The Password Protection Mode Lock Bit (IRP[2]) allows regions 2 and 3 to be protected from programming operations until the
correct password is provided to enable programming of these Security Regions 2 and 3. Attempting to program in a region that is
password locked will fail with the P_ERR bit in SR2V[5] set to “1”. See Password Protection Mode on page 73.
The protocol of the Security Region Program command is the same as the Page Program command. See Section 9.5.1.1, Page
Programming on page 106 for the command sequence. QPI Mode is supported.
9.7.3
Security Regions Read (SECRR 48h)
The Security Region Read (SECRR) command provides a way to read data from the Security Regions. The Security Region is 1024
bytes so, the address bits (A24 to A10) must be zero for this command. Refer to Section 7.5, Security Regions Address Space
on page 47 for details on the Security Regions.
The instruction is followed by a 3 or 4 Byte address (depending on the address length configuration CR2V[0], followed by a number
of latency (dummy) cycles set by CR3V[3:0]. Then the selected register data are returned. The protocol of the Security Region Read
command will not wrap to the starting address after the Security Region address is at its maximum; instead, the data beyond the
maximum address will be undefined. The Security Region Read command read latency is set by the latency value in CR3V[3:0].
The Security Region Read Password Mode Enable Bit (IRP[6]) allows regions 3 to be protected from read operations until the
correct password is provided to enable reading of this Security Region. Attempting to read in region 3 that is password locked will
return invalid and undefined data. See Security Region Read Password Protection on page 74
Figure 9.67 Security Regions Read Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
7
Instruction
Address
Dummy Cycles
6
5
4
3
2
1
0
Data 1
Note
1. A = MSB of address = 23 for Address length CR2V[0] = 0, or 31 for CR2V[0]=1.
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This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in and returning data out on IO0IO3.
Figure 9.68 Security Regions Read Command Sequence QPI mode
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
Note
1. A = MSB of address = 23 for CR2V[0]=0, or 31 for CR2V[0]=1.
9.8
Individual Block Lock Commands
In order to use Individual Block Lock, the IBL protection scheme must be selected by the WPS bit in Configuration Register 2
CR2V[2]=1. If if IBL protection scheme is not selected CR2V[2]=0 the IBL commands are ignored.
Individual Block Lock Bits (IBL) are volatile, with one for each sector / block, and can be individually modified. By issuing the IBL or
GBL commands, a IBL bit is set to “0” protecting each related sector / block. By issuing the IBUL or GUL commands, a IBL bit is
cleared to “1” unprotecting each related sector or block. By issuing the IBLRD command the state of each IBL bit protection can be
read.
9.8.1
IBL Read (IBLRD 3Dh or 4IBLRD E0h)
The IBLRD/4IBLRD command allows reading the state of each IBL bit protection.
The instruction is latched into SI by the rising edge of the SCK signal. The instruction is followed by the 24 or 32-Bit address,
depending on the address length configuration CR2V[0], selecting location zero within the desired sector.
Then the 8-bit IBL access register contents are shifted out on the serial output SO/IO1. Each bit is shifted out at the SCK frequency
by the falling edge of the SCK signal. It is possible to read the same IBL access register continuously by providing multiples of eight
clock cycles. The address of the IBL register does not increment so this is not a means to read the entire IBL array. Each location
must be read with a separate IBL Read command.
Figure 9.69 IBLRD Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
7
Instruction
Address
Dummy Cycles
6
5
4
3
2
1 0
Output IBL
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 3Dh.
2. A = MSB of address = 31 with command E0h.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in and returning data out on IO0IO3.
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Figure 9.70 IBLRD Command Sequence QPI
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
IBL
Repeat IBL
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 3Dh.
2. A = MSB of address = 31 with command E0h.
9.8.2
IBL Lock (IBL 36h or 4IBL E1h)
The IBL/4IBL commands sets the selected IBL bit to “0” protecting each related sector / block.
The IBL command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24 or 32-Bit address,
depending on the address length configuration CR2V[0]. The IBL command affects the WIP bits of the Status and Configuration
Registers in the same manner as any other programming operation.
CS# must be driven to the logic high state after the 24 or 32-Bit address (depending on the address length configuration CR2V[0])
has been latched in. As soon as CS# is driven to the logic high state, the self-timed IBL operation is initiated. While the IBL operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed IBL operation, and is a “0” when it is completed.
Figure 9.71 IBL Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 36h.
2. A = MSB of address = 31 with command E1h
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in on IO0-IO3.
Figure 9.72 IBL Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 36h.
2. A = MSB of address = 31 with command E1h.
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9.8.3
S25FL256L
IBL Unlock (IBUL 39h or 4IBUL E2h)
The IBUL/4IBULcommands clears the selected IBL bit to “1” unprotecting each related sector / block.
The IBUL command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24 or 32-Bit address,
depending on the address length configuration CR2V[0]. The IBUL command affects the WIP bits of the Status and Configuration
Registers in the same manner as any other programming operation.
CS# must be driven to the logic high state after the 24 or 32-Bit address (depending on the address length configuration CR2V[0])
has been latched in. As soon as CS# is driven to the logic high state, the self-timed IBL operation is initiated. While the IBUL
operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In
Progress (WIP) bit is a “1” during the self-timed IBUL operation, and is a “0” when it is completed.
Figure 9.73 IBUL Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 39h.
2. A = MSB of address = 31 with command E2h.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in on IO0-IO3.
Figure 9.74 IBUL Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command 39h.
2. A = MSB of address = 31 with command E2h.
9.8.4
Global IBL Lock (GBL 7Eh)
The GBL commands sets all the IBL bits to “0” protecting all sectors / blocks.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
GBL. If CS# is not driven high after the last bit of instruction, the GBL operation will not be executed.
As soon as CS# is driven into the logic high state, the GBL will be initiated. With the GBL in progress, the user can read the value of
the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a “1” when the GBL
is in progress and a “0” when the GBL has been completed.
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Figure 9.75 Global IBL Lock (GBL) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.76 Global IBL Lock (GBL) Command Sequence QPI mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.8.5
Instruction
Global IBL Unlock (GBUL 98h)
The GBUL commands clears all the IBL bits to “1” unprotecting all sectors / blocks.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
GBUL If CS# is not driven high after the last bit of instruction, the GBUL operation will not be executed.
As soon as CS# is driven into the logic high state, the GBL will be initiated. With the GBL in progress, the user can read the value of
the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a “1” when the GBUL
is in progress and a “0” when the GBUL has been completed.
Figure 9.77 Global IBL Unlock (GBUL) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.78 Global IBL Unlock (GBUL) Command Sequence QPI mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
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Instruction
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9.9
9.9.1
S25FL256L
Pointer Region Command
Set Pointer Region Protection (SPRP FBh or 4SPRP E3h)
The SPRP or 4SPRP command is ignored during a suspend operation because the pointer value cannot be erased and reprogrammed during a suspend.
The SPRP or 4SPRP command is ignored if default Power Supply Lock-down protection NVLOCK PR[0]=0 or Power Supply Lockdown protection enabled IRP[1]=0 or Password Protection enabled IRP[2]=0 and NVLOCK PR[0]=0.
The S25FL256L device must have 4 Byte addressing enabled (CR2V[0] = 1) to set the Pointer Region Protection register PRPR
(see Section 7.6.9 on page 60) this ensures that A24 and A25 are set correctly. Before the SPRP or 4SPRP command can be
accepted by the device, a Write Enable (WREN) command must be issued. After the Write Enable (WREN) command has been
decoded, the device will set the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The SPRP or 4SPRP command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24 or 32Bit address, depending on the address length configuration CR2V[0], see Pointer Region Protection (PRP) on page 69 for details on
address values to select protection options.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the SPRP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed SPRP operation is initiated. While the SPRP operation is in
progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
“1” during the self-timed SPRP operation, and is a “0” when it is completed. When the SPRP operation is completed, the Write
Enable Latch (WEL) is set to a “0”. The SPRP or 4SPRP command will set the P_ERR or E_ERR bits if there is a failure in the Set
Pointer Region Protection operation.
For details on the address pointer defining a sector boundary between protected and unprotected regions in the
memory, see Pointer Region Protection (PRP) on page 69.
Figure 9.79 SPRP Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
A
1
0
SO_IO1
Phase
Instruction
Address
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command FDh.
2. A = MSB of address = 31 with command E3h.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in on IO0-IO3.
Figure 9.80 SPRP Command Sequence QPI Mode
CS#
SCLK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
1. A = MSB of address = 23 for Address length (CR2V[0] = 0, or 31 for CR2V[0]=1 with command FDh.
2. A = MSB of address = 31 with command E3h.
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9.10
9.10.1
S25FL256L
Individual and Region Protection (IRP) Commands
IRP Register Read (IRPRD 2Bh)
The IRP Register Read instruction 2Bh is shifted into SI/IO0 by the rising edge of the SCK signal followed by one dummy cycle. This
latency period allows the device’s internal circuitry enough time to access data at the initial address. During latency cycles, the data
value on IO0-IO3 are “don’t care” and may be high impedance.
Then the 16-bit IRP register contents are shifted out on the serial output S0/IO1, least significant byte first. Each bit is shifted out at
the SCK frequency by the falling edge of the SCK signal. It is possible to read the IRP register continuously by providing multiples of
16 clock cycles.
Figure 9.81 IRPRD Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
7
Instruction
DY
6
5
4
3
2
1
0
7
Output IRP Low Byte
6
5
4
3
2
1
0
Output IRP High Byte
This command is also supported in QPI mode. In QPI mode the instruction is shifted in and returning data out on IO0-IO3.
Figure 9.82 IRPRD Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
9.10.2
Instruct.
Dummy
IRP Low Byte
IRP High Byte
IRP Program (IRPP 2Fh)
Before the IRP Program (IRPP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to
enable any write operations.
The IRPP command is entered by driving CS# to the logic low state, followed by the instruction and two data bytes on SI, least
significant byte first. The IRP Register is two data bytes in length.
The IRPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other
programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the IRPP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed IRPP operation is initiated. While the IRPP operation is in
progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
“1” during the self-timed IRPP operation, and is a “0” when it is completed. When the IRPP operation is completed, the Write Enable
Latch (WEL) is set to a “0”.
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S25FL256L
Figure 9.83 IRP Program (IRPP) Command
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Input IRP Low Byte
Input IRP High Byte
This command is also supported in QPI mode. In QPI mode the instruction and data is shifted in on IO0-IO3.
Figure 9.84 IRP Program (IRPP) Command QPI
CS#
SCLK
IO0
4
0
4
0
C
8
IO1
5
1
5
1
D
9
IO2
6
2
6
2
E
A
IO3
7
3
7
3
F
B
Phase
9.10.3
Instruct.
IRP Low Byte
IRP High Byte
Protection Register Read (PRRD A7h)
The Protection Register Read (PRRD) command allows the Protection Register contents to be read out of SO/IO1. The Read
instruction A7h is shifted into SI by the rising edge of the SCK signal followed by one dummy cycle. This latency period allows the
device’s internal circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3 are
“don’t care” and may be high impedance.
Then the 8-bit Protection Register contents are shifted out on the serial output SO/IO1. Each bit is shifted out at the SCK frequency
by the falling edge of the SCK signal. It is possible to read the Protection register continuously by providing multiples of eight clock
cycles.
The Protection Register contents may only be read when the device is in standby state with no other operation in progress.
Figure 9.85 Protection Register Read (PRRD) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
7
Instruction
DY
6
5
4
3
2
Register Read
1
0
7
6
5
4
3
2
1
0
Repeat Register Read
This command is also supported in QPI mode. In QPI mode the instruction is shifted in and returning data out on IO0-IO3.
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S25FL256L
Figure 9.86 Protection Register Read (PRRD) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
9.10.4
Instruct.
Dummy
Register Read
Register Read
Protection Register Lock (PRL A6h)
The Protection Register Lock (PRL) command clears the NVLOCK bit (PR[0]) to zero and loads the IRP[6] value in to SECRRP
(PR[6]). See Section 7.6.7, Protection Register (PR) on page 59. Before the PRL command can be accepted by the device, a Write
Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status
Register to enable any write operations.
The PRL command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the PRL command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PRL operation is initiated. While the PRL operation is in
progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed PRL operation, and is a “0” when it is completed. When the PRL operation is completed, the Write
Enable Latch (WEL) is set to a “0”.
Figure 9.87 Protection Register Lock (PRL) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.88 Protection Register Lock (PRL) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00124 Rev. *A
3
Instruction
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9.10.5
S25FL256L
Password Read (PASSRD E7h)
The correct password value may be read only after it is programmed and before the Password Mode has been selected by
programming the Password Protection Mode bit to 0 in the IRP Register (IRP[2]). After the Password Protection Mode is selected
the password is no longer readable, the PASSRD command will output undefined data.
The PASSRD command is shifted into SI followed by one dummy cycle. This latency period allows the device’s internal circuitry
enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3 are “don’t care” and may be high
impedance.
Then the 64-bit Password is shifted out on the serial output SO/IO1, least significant byte first, most significant bit of each byte first.
Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the Password continuously by
providing multiples of 64 clock cycles.
Figure 9.89 Password Read (PASSRD) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
IO2-IO3
Phase
Instruction
DY
Data 1
Data 8
This command is also supported in QPI mode. In QPI mode the instruction is shifted in and returning data out on IO0-IO3.
Figure 9.90 Password Read (PASSRD) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
9.10.6
Instruct.
Dummy
Data 1
Data 8
Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device. After the Write Enable (WREN) command has been decoded, the device sets the Write Enable
Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password Mode is selected by programming the Password Protection Mode bit
to 0 in the IRP Register (IRP[2]). After the Password Protection Mode is selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI/IO0, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PASSP operation is initiated. While the PASSP operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed PASSP cycle, and is a “0” when it is completed. The PASSP command can report a program error in the
P_ERR bit of the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a “0”.
Document Number: 002-00124 Rev. *A
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S25FL256L
Figure 9.91 Password Program (PASSP) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Password Byte 1
Password Byte 8
This command is also supported in QPI mode. In QPI mode the instruction and data is shifted in on IO0-IO3.
Figure 9.92 Password Program (PASSP) Command Sequence QPI mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
Phase
9.10.7
Instruct.
Password Byte 1
Password Byte 8
Password Unlock (PASSU EAh)
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSU command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PASSU operation is initiated. While the PASSU operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a “1” during the self-timed PASSU cycle, and is a “0” when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register, an error is reported by
setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is necessary to use the CLSR command to
clear the status register, the software reset command (RSTEN 66h followed by RST 99h) to reset the device, or drive the RESET#
and IO3 / RESET# input to initiate a hardware reset, in order to return the P_ERR and WIP bits to 0. This returns the device to
standby state, ready for new commands such as a retry of the PASSU command.
If the password does match, the NVLOCK bit is set to “1”.
Figure 9.93 Password Unlock (PASSU) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
Password Byte 1
Password Byte 8
This command is also supported in QPI mode. In QPI mode the instruction and data is shifted in on IO0-IO3.
Document Number: 002-00124 Rev. *A
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S25FL256L
Figure 9.94 Password Unlock (PASSU) Command Sequence QPI mode
CS#
SCLK
IO0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
IO3
7
7
3
7
3
7
3
3
Phase
9.11
Instruct.
Password Byte 1
Password Byte 8
Reset Commands
Software controlled Reset commands restore the device to its initial power up state, by reloading volatile registers from non-volatile
default values. If a software reset is initiated during a Erase, Program or writing of a Register operation the data in that Sector, Page
or Register is not stable, the operation that was interrupted needs to be initiated again.
However, the volatile SRP1 bit in the Configuration register CR1V[0] and the volatile NVLOCK bit in the Protection Register are not
changed by a software reset. The software reset cannot be used to circumvent the SRP1 or NVLOCK bit protection mechanisms for
the other security configuration bits.
The SRP1 bit and the NVLOCK bit will remain set at their last value prior to the software reset. To clear the SRP1 bit and set the
NVLOCK bit to its protection mode selected power on state, a full power-on-reset sequence or hardware reset must be done.
A software reset command (RSTEN 66h followed by RST 99h) is executed when CS# is brought high at the end of the instruction
and requires tRPH time to execute.
In the case of a previous Power-up Reset (POR) failure to complete, a reset command triggers a full power up sequence requiring
tPU to complete.
Figure 9.95 Software / Mode Bit Reset Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.96 Software Reset / Mode Bit Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *A
Instruction
Page 127 of 145
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9.11.1
S25FL256L
Software Reset Enable (RSTEN 66h)
The Reset Enable (RSTEN) command is required immediately before a software reset command (RST 99h) such that a software
reset is a sequence of the two commands. Any command other than RST following the RSTEN command, will clear the reset enable
condition and prevent a later RST command from being recognized.
9.11.2
Software Reset (RST 99h)
The Reset (RST) command immediately following a RSTEN command, initiates the software reset process. Any command other
than RST following the RSTEN command, will clear the reset enable condition and prevent a later RST command from being
recognized.
9.11.3
Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command is used to return the device from continuous high performance read mode back to normal
standby awaiting any new command. Because the hardware RESET# input may be disabled and a device that is in a continuous
high performance read mode may not recognize any normal SPI command, a system hardware reset or software reset command
may not be recognized by the device. It is recommended to use the MBR command after a system reset when the RESET# signal is
not available or, before sending a software reset, to ensure the device is released from continuous high performance read mode.
The MBR command sends Ones on SI/IO0 for eight SCK cycles. IO1-IO3 are “don’t care” during these cycles.
9.12
9.12.1
Deep Power Down Commands
Deep Power-Down (DPD B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep PowerDown command. The lower power consumption makes the Deep Power-down (DPD) command especially useful for battery
powered applications (see ICC1 and ICC2 in (Section 4.5, DC Characteristics on page 26). The command is initiated by driving the
CS# pin low and shifting the instruction code “B9h”.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power-Down command will not be
executed. After CS# is driven high, the power-down state will be entered within the time duration of tDP (Table 5.4 on page 33).
While in the power-down state only the Release from Deep Power-Down / Device ID command, which restores the device to normal
operation, will be recognized. All other commands are ignored. This includes the Read Status Register command, which is always
available during normal operation. Ignoring all but one command also makes the Power Down state a useful condition for securing
maximum write protection.
While in the deep power-down mode the device will only accept a hardware reset which will initiate a Power on Reset that will
restore the device to normal operation. The device always powers-up in the normal operation with the standby current of ICC1.
Figure 9.97 Deep Power Down (DPD) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
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S25FL256L
Figure 9.98 Deep Power Down (DPD) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.12.2
Instruction
Release from Deep Power-Down / Device ID (RES ABh)
The Release from Deep Power-Down /Device ID command is a multi-purpose command. It can be used to release the device from
the Deep Power-Down state, or obtain the devices electronic identification (ID) number.
To release the device from the Deep Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction
code “ABh” and driving CS# high. Release from Deep Power-Down will take the time duration of tRES (Table 5.4 on page 33) before
the device will resume normal operation and other commands are accepted. The CS# pin must remain high during the tRES time
duration.
When used only to obtain the Device ID while not in the Deep Power-Down state, the command is initiated by driving the CS# pin
low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of
CLK with most significant bit (MSB) first. The Device ID values for the S25FL-L Family is listed in and Table 11.5, Manufacturer
Device Type on page 140. Continued shifting of output beyond the end of the defined ID address space will provide undefined data.
The command is completed by driving CS# high.
When used to release the device from the Deep Power-Down state and obtain the Device ID, the command is the same as
previously described, and shown in Figure 9.101 and Figure 9.102, except that after CS# is driven high it must remain high for a time
duration of tRES. After this time duration the device will resume normal operation and other commands will be accepted. If the
Release from Deep Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when BUSY
equals 1) the command is ignored and will not have any effects on the current cycle.
Figure 9.99 Release from Deep Power Down (RES) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0
SO_IO1
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3.
Figure 9.100 Release from Deep Power Down (RES) Command Sequence – QPI Mode
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00124 Rev. *A
Instruction
Page 129 of 145
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S25FL256L
Figure 9.101 Read Identification (RES) Command Sequence
CS#
SCK
SI_IO0
7
6
5
4
3
2
1
0 23
1
SO_IO1
0
7
Phase
Instruction
6
5
4
Dummy
3
2
1
0
Dev ID
7
1
0
Dev ID
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
Figure 9.102 Read Identification (RES) QPI Mode Command
CS#
SCLK
IO0
4
0
IO1
5
1
IO2
6
IO3
7
Phase
4
0
4
0
4
5
5
1
5
1
5
2
6
6
2
6
2
6
3
7
7
3
7
3
7
Instruction
Document Number: 002-00124 Rev. *A
23
22
4
Dummy
0
Dev ID
Dev ID
Page 130 of 145
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S25FL256L
10. Data Integrity
10.1
10.1.1
Endurance
Erase Endurance
Table 10.1 Erase Endurance
Parameter
Program/Erase cycles main Flash array sector
Min
Typical
Unit
100K
PE cycle
1K
PE cycle
Program/Erase cycles Security Region or non-volatile register array
Notes:
1. Each write command to a non-volatile register causes a PE cycle on the entire non-volatile register array. OTP bits and registers internally reside in a separate array
that is not cycled.
2. For Industrial, Industrial Plus and Extended Temperature ranges.
10.2
Data Retention
Table 10.2 Data Retention
Typical
Unit
Data Retention Time main Flash Array
Parameter
@ 55°C
20
Years
Data Retention Time Security Region or non-volatile register array
@ 55°C
20
Years
Document Number: 002-00124 Rev. *A
Test Conditions
Page 131 of 145
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S25FL256L
11. Software Interface Reference
11.1
JEDEC JESD216B Serial Flash Discoverable Parameters
This document defines the Serial Flash Discoverable Parameters (SFDP) revision B data structure used in the following Cypress
Serial Flash Devices:
S25FL-L Family
These data structure values are an update to the earlier revision SFDP data structure currently existing in the above devices.
The Read SFDP (RSFDP) command (5Ah) reads information from a separate Flash memory address space for device identification,
feature, and configuration information, in accord with the JEDEC JESD216B standard for Serial Flash Discoverable Parameters.
The SFDP data structure consists of a header table that identifies the revision of the JESD216 header format that is supported and
provides a revision number and pointer for each of the SFDP parameter tables that are provided. The parameter tables follow the
SFDP header. However, the parameter tables may be placed in any physical location and order within the SFDP address space. The
tables are not necessarily adjacent nor in the same order as their header table entries.
The SFDP header points to the following parameter tables:
Basic Flash
– This is the original SFDP table. It has a few modified fields and new additional field added at the end of the table.
4 Byte Address Instruction
– This is the original SFDP table. It has a few modified fields and new additional field added at the end of the table.
The physical order of the tables in the SFDP address space is: SFDP Header, Basic Flash Sector Map, 4 Byte Instruction.
The SFDP address space is programmed by Cypress and read-only for the host system.
11.1.1
Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides a pointer to
each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B standard. Optional parameter tables for 4 Byte
Address Instructions follow the Basic Flash table.
Table 11.1 SFDP Overview Map
Byte Address
0000h
,,,
0300h
...
Description
Location zero within JEDEC JESD216B SFDP space - start of SFDP header
Remainder of SFDP header followed by undefined space
Start of SFDP parameter
Remainder of SFDP JEDEC parameter followed by undefined space
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11.1.2
S25FL256L
SFDP Header Field Definitions
Table 11.2 SFDP Header
SFDP Byte
Address
SFDP Dword
Name
00h
01h
SFDP Header 1st
DWORD
Data
Description
53h
This is the entry point for Read SFDP (5Ah) command i.e. location zero within SFDP space
ASCII “S”
46h
ASCII “F”
02h
44h
ASCII “D”
03h
50h
ASCII “P”
06h
SFDP Minor Revision (06h = JEDEC JESD216 Revision B)
- This revision is backward compatible with all prior minor revisions. SFDP reading and parsing software
will work with higher minor revision numbers than the software was designed to handle. Software
designed for a higher revisions must know how to handle earlier revisions. Example: SFDP reading and
parsing software for minor revision 0 will still work with minor revision 6. SFDP reading and parsing
software for minor revision 6 must be designed to also read minor revision 0 or 5. Do not do a simple
compare on the minor revision number, looking only for a match with the revision number that the
software is designed to handle. There is no problem with using a higher number minor revision.
05h
01h
SFDP Major Revision
This is the original major revision. This major revision is compatible with all SFDP reading and parsing
software.
06h
01h
Number of Parameter Headers (zero based, 01h = 2 parameters)
07h
FFh
Unused
08h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
06h
Parameter Minor Revision (06h = JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is compatible with this
major revision.
0Bh
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
0Ch
00h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC Basic SPI Flash parameter byte offset = 0300h address
03h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
04h
SFDP Header 2nd
DWORD
09h
0Ah
0Dh
0Eh
Parameter Header
0
1st DWORD
Parameter Header
0
2nd DWORD
0Fh
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
10h
84h
Parameter ID LSB (84h = SFDP 4 Byte Address Instructions Parameter)
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that recognizes this
parameter’s ID is compatible with this major revision.
13h
02h
Parameter Table Length (in double words = Dwords = 4 byte units) (2h = 2 Dwords)
14h
40h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC parameter byte offset = 0340h
03h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
11h
12h
15h
16h
17h
Parameter Header
1
1st DWORD
Parameter Header
1
2nd DWORD
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11.1.3
S25FL256L
JEDEC SFDP Basic SPI Flash Parameter
Table 11.3 Basic SPI Flash Parameter, JEDEC SFDP Rev B
SFDP Parameter
Relative Byte
Address
SFDP Dword Name
Data
Description
E5h
Start of SFDP JEDEC parameter
Bits 7:5 = unused = 111b
Bit 4:3 = 05h is volatile status register write instruction and status register is default non-volatile=
00b
Bit 2 = Program Buffer > 64Bytes = 1
Bits 1:0 = Uniform 4KB erase is supported through out the device = 01b
20h
Bits 15:8 = Uniform 4KB erase instruction = 20h
02h
FBh
Bit 23 = Unused = 1b
Bit 22 = Supports DOR Read, Yes = 1b
Bit 21 = Supports QIO Read, Yes =1b
Bit 20 = Supports DIO Read, Yes = 1b
Bit19 = Supports DDR, Yes = 1b
Bit 18:17 = Number of Address Bytes, 3 or 4 = 01b
Bit 16 = Supports Fast Read SIO and DIO Yes = 1b
03h
FFh
Bits 31:24 = Unused = FFh
04h
FFh
00h
01h
JEDEC Basic Flash
Parameter Dword-1
05h
06h
JEDEC Basic Flash
Parameter Dword-2
FFh
FFh
Density in bits, zero based,
256Mb = 0FFFFFFFh
07h
0Fh 256Mb
08h
48h
Bits 7:5 = number of QIO Mode cycles = 010b
Bits 4:0 = number of Fast Read QIO Dummy cycles = 01000b for default latency code
EBh
Fast Read QIO instruction code
0Ah
08h
Bits 23:21 = number of Quad Out Mode cycles = 000b
Bits 20:16 = number of Quad Out Dummy cycles = 01000b for default latency code
0Bh
6Bh
Quad Out instruction code
0Ch
08h
Bits 7:5 = number of Dual Out Mode cycles = 000b
Bits 4:0 = number of Dual Out Dummy cycles = 01000b for default latency code
09h
0Dh
JEDEC Basic Flash
Parameter Dword-3
3Bh
Dual Out instruction code
0Eh
88 h
Bits 23:21 = number of Dual I/O Mode cycles = 100b
Bits 20:16 = number of Dual I/O Dummy cycles = 01000b for default latency code
0Fh
BBh
Dual I/O instruction code
FEh
Bits 7:5 RFU = 111b
Bit 4 = QPI supported = 1b
Bits 3:1 RFU = 111b
Bit 0 = Dual All not supported = 0b
FFh
Bits 15:8 = RFU = FFh
12h
FFh
Bits 23:16 = RFU = FFh
13h
FFh
Bits 31:24 = RFU = FFh
14h
FFh
Bits 7:0 = RFU = FFh
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
17h
FFh
Dual All instruction code
18h
FFh
Bits 7:0 = RFU = FFh
19h
FFh
Bits 15:8 = RFU = FFh
48h
Bits 23:21 = number of QPI Mode cycles = 010b
Bits 20:16 = number of QPI Dummy cycles = 01000b for default latency code
EBh
QPI Fast Read instruction code (Same as QIO when QPI is enabled)
JEDEC Basic Flash
Parameter Dword-4
10h
11h
JEDEC Basic Flash
Parameter Dword-5
15h
16h
1Ah
JEDEC Basic Flash
Parameter Dword-6
JEDEC Basic Flash
Parameter Dword-7
1Bh
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S25FL256L
Table 11.3 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword Name
1Ch
1Dh
1Eh
JEDEC Basic Flash
Parameter Dword-8
Data
Description
0Ch
Sector type 1 size 2^N Bytes = 4KB = 0Ch (for Uniform 4KB)
20h
Sector type 1 instruction
0Fh
Sector type 2 size 2^N Bytes = 32KB = 0Fh (for Uniform 32KB)
1Fh
52h
Sector type 2 instruction
20h
10h
Sector type 3 size 2^N Bytes = 64KB = 10h (for Uniform 64KB)
D8h
Sector type 3 instruction
00h
Sector type 4 size 2^N Bytes = not supported = 00h
21h
22h
JEDEC Basic Flash
Parameter Dword-9
23h
FFh
Sector type 4 instruction = not supported = FFh
24h
21h
Bits 31:30 = Sector Type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s)
= RFU = 11b
Bits 29:25 = Sector Type 4 Erase, Typical time count = RFU = 1_1111b (typ erase time = count +1
* units = RFU =11111)
Bits 24:23 = Sector Type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s)
= 16mS = 01b
Bits 22:18 = Sector Type 3 Erase, Typical time count = 1_0000b (typ erase time = count +1 * units
= 17*16ms = 272ms)
Bits 17:16 = Sector Type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s)
= 16ms = 01b
Bits 15:11 = Sector Type 2 Erase, Typical time count = 0_1011b (typ erase time = count +1 * units
= 12*16ms = 192mS)
Bits 10:9 = Sector Type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s)
= 16ms = 01b
Bits 8:4 = Sector Type 1 Erase, Typical time count = 0_0010b (typ erase time = count +1 * units =
3*16mS = 48ms)
Bits 3:0 = Count = (Max Erase time / (2 * Typical Erase time))- 1 = 0001b
Multiplier from typical erase time to maximum erase time = 4x multiplier
Max Erase time = 2*(Count +1)*Typ Erase time
25h
5Ah
26h
C1h
JEDEC Basic Flash
Parameter Dword-10
27h
FEh
Binary Fields: 11-11111-01-10000-01-01011-01-00010-0001
Nibble Format: 1111_1110_1100_0001_0101_1010_0010_0001
Hex Format: FE_C1_5A_21
28h
81h
29h
E4h
2Ah
29h
JEDEC Basic Flash
Parameter Dword-11
Bits 23 = Byte Program Typical time, additional byte units (0b:1us, 1b:8us) = 1us = 0b
Bits 22:19 = Byte Program Typical time, additional byte count, (count+1)*units, count = 0101b, (typ
Program time = count +1 * units = 6*1us =6us
Bits 18 = Byte Program Typical time, first byte units (0b:1us, 1b:8us) = 1us = 0b
Bits 17:14 = Byte Program Typical time, first byte count, (count+1)*units, count = 0111b, (typ
Program time = count +1 * units = 8*1us = 8us
Bits 13 = Page Program Typical time units (0b:8us, 1b:64us) = 64us = 1b
Bits 12:8 = Page Program Typical time count, (count+1)*units, count = 00100b, (typ Program time =
count +1 * units = 5*64us = 320us)
Bits 7:4 = N = 1000b, Page size= 2^N = 256B page
Bits 3:0 = Count = 0001b = (Max Page Program time / (2 * Typ Page Program time))- 1
Multiplier from typical Page Program time to maximum Page Program time = 4x multiplier
Max Page Program time = 2*(Count +1)*Typ Page Program time
Binary Fields: 0-0101-0-0111-1-00100-1000-0001
Nibble Format: 0010_1001_1110_0100_1000_0001
Hex Format: 29_74_81
2Bh
Document Number: 002-00124 Rev. *A
E2h 256Mb
256Mb = 1110_0010b = E2h
Bit 31 Reserved = 1b
Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 64s =
11b
Bits 28:24 = Chip Erase, Typical time count, (count+1)*units, count = 00010b, (typ Program time =
count +1 * units = 3*64s = 192s
Page 135 of 145
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S25FL256L
Table 11.3 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword Name
Data
Description
2Ch
CCh
2Dh
83h
2Eh
18h
Bit 31 = Suspend and Resume supported = 0b
Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b:
64us) = 8us= 10b
Bits 28:24 = Suspend in-progress erase max latency count = 00100b, max erase suspend latency
= count +1 * units = 5*8us = 40us
Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = count +1 * 64us = 2 * 64us
= 128us
Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b:
64us) = 8us= 10b
Bits 17:13 = Suspend in-progress program max latency count = 00100b, max erase suspend
latency = count +1 * units = 5*8us = 40us
Bits 12:9 = Program resume to suspend interval count = 0001b, interval = count +1 * 64us = 2 *
64us = 128us
Bit 8 = RFU = 1b
Bits 7:4 = Prohibited operations during erase suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx0xb: May not initiate a page program anywhere
+ x1xxb: May not initiate a read in the erase suspended sector size
+ 1xxxb: The erase and program restrictions in bits 5:4 are sufficient
= 1100b
Bits 3:0 = Prohibited Operations During Program Suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx0xb: May not initiate a new page program anywhere (program nesting not permitted)
+ x1xxb: May not initiate a read in the program suspended page size
+ 1xxxb: The erase and program restrictions in bits 1:0 are sufficient
= 1100b
JEDEC Basic Flash
Parameter Dword-12
2Fh
44h
Binary Fields: 0-10-00100-0001-10-00100-0001-1-1100-1100
Nibble Format: 0100_0100_0001_1000_1000_0011_1100_1100
Hex Format: 44_18_83_CC
30h
31h
32h
7Ah
JEDEC Basic Flash
Parameter Dword-13
75h
7Ah
33h
75h
34h
F7h
35h
A2h
36h
D5h
JEDEC Basic Flash
Parameter Dword-14
37h
5Ch
Bits 31:24 = Erase Suspend Instruction = 75h
Bits 23:16 = Erase Resume Instruction = 7Ah
Bits 15:8 = Program Suspend Instruction = 75h
Bits 7:0 = Program Resume Instruction = 7Ah
Bit 31 = Deep Power Down Supported = supported = 0
Bits 30:23 = Enter Deep Power Down Instruction = B9h = 1011_1001b
Bits 22:15 = Exit Deep Power Down Instruction = ABh = 1010_1011b
Bits 14:13 = Exit Deep Power Down to next operation delay units = (00b: 128ns, 01b: 1us, 10b: 8us,
11b: 64us) = 1us = 01b
Bits 12:8 = Exit Deep Power Down to next operation delay count = 00010b, Exit Deep Power Down
to next operation delay = (count+1)*units = 3*1us=3us
Bits 7:4 = RFU = Fh
Bit 3:2 = Status Register Polling Device Busy
= 01b: Legacy status polling supported = Use legacy polling by reading the Status Register with
05h instruction and checking WIP bit[0] (0=ready; 1=busy).
Bits 1:0 = RFU = 11b
Binary Fields: 0-10111001-10101011-01-00010-1111-01-11
Nibble Format: 0101_1100_1101_0101_1010_0010_1111_0111
Hex Format: 5C_D5_A2_F7
Document Number: 002-00124 Rev. *A
Page 136 of 145
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S25FL256L
Table 11.3 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword Name
38h
Data
Description
22h
Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP Disable = not supported = 0b
Bits 22:20 = Quad Enable Requirements
= 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction
05h. Status register 2 is read using instruction 35h. QE is set via Write Status instruction 01h with
two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data
bytes where bit 1 of the second byte is zero.
Bits 19:16 0-4-4 Mode Entry Method
= xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode
+ x1xxb: Mode Bits[7:0] = Axh
+ 1xxxb: RFU
= 1101b
Bits 15:10 0-4-4 Mode Exit Method
= xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current read operation
+ xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate the mode prior
to the next read operation.
+ 11_x1xx: RFU
= 111101
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences
= 0_0010b: issue instruction 38h
Bits 3:0 = 4-4-4 mode disable sequences
= 0010b: 4-4-4 issues F5h instruction
39h
F6h
3Ah
5Dh
JEDEC Basic Flash
Parameter Dword-15
3Bh
FFh
Binary Fields: 11111111-0-101-1101-111101-1-00010-0010
Nibble Format: 1111_1111_0101_1101_1111_0110_0010_0010
Hex Format: FF_5D_F6_22
Document Number: 002-00124 Rev. *A
Page 137 of 145
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S25FL256L
Table 11.3 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Continued)
SFDP Parameter
Relative Byte
Address
SFDP Dword Name
3Ch
Data
Description
E8h
Bits 31:24 = Enter 4-Byte Addressing
= xxxx_xxx1b:issue instruction B7 (preceding write enable not required
= xxxx_1xxxb: 8-bit volatile bank register used to define A[30:24] bits. MSB (bit[7]) is used to
enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte address mode is active and
A[30:24] bits are don’t care. Read with instruction 16h. Write instruction is 17h with 1 byte of data.
When MSB is cleared to ‘0’, select the active 128 Mb segment by setting the appropriate A[30:24]
bits and use 3-Byte addressing.
+ xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data sheet for
the instruction set definition or look for 4 Byte Address Parameter Table.
+ 1xxx_xxxxb: Reserved
= 10100001b
Bits 23:14 = Exit 4-Byte Addressing
= xx_xxxx_xxx1b:issue instruction E9h to exit 4-Byte address mode (Write enable instruction 06h
is not required)
= xx_xxxx_1xxxb: 8-bit volatile bank register used to define A[30:24] bits. MSB (bit[7]) is used to
enable/disable 4-byte address mode. When MSB is cleared to ‘0’, 3-byte address mode is active
and A30:A24 are used to select the active 128 Mb memory segment. Read with instruction 16h.
Write instruction is 17h, data length is 1 byte.
+ xx_xx1x_xxxxb: Hardware reset
+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)
+ xx_1xxx_xxxxb: Power cycle
+ x1_xxxx_xxxxb: Reserved
+ 1x_xxxx_xxxxb: Reserved
= 1111100001b
Bits 13:8 = Soft Reset and Rescue Sequence Support
= x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The reset enable,
reset sequence may be issued on 1,2, or 4 wires depending on the device operating mode
= 010000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for Status Register 1
= xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value in the nonvolatile status register, use instruction 06h to enable write to non-volatile status register. Volatile
status register may be activated after power-up to override the non-volatile status register, use
instruction 50h to enable write and activate the volatile status register.
+ x1x_xxxxb: Reserved
+ 1xx_xxxxb: Reserved
= 1101000b
3Dh
50h
3Eh
F8h
JEDEC Basic Flash
Parameter Dword-16
3Fh
A1h
Binary Fields: 10100001-1111100001-010000-1-1101000
Nibble Format: 1010_0001_1111_1000_0101_0000_1110_1000
Hex Format: A1_F8_60_E8
Document Number: 002-00124 Rev. *A
Page 138 of 145
ADVANCE
11.1.4
S25FL256L
JEDEC SFDP 4-byte Address Instruction Table
Table 11.4 4-byte Address Instruction, JEDEC SFDP Rev B
SFDP Parameter
Relative Byte Address
SFDP Dword Name
Data
40h
FBh
41h
8Eh
42h
F3h
JEDEC 4 Byte Address
Instructions Parameter
Dword-1h
43h
FFh
Description
Supported = 1, Not Supported = 0
Bits 31:20 = RFU = FFFh
Bit 19 = Support for non-volatile individual sector lock write command, Instruction=E3h = 0
Bit 18 = Support for non-volatile individual sector lock read command, Instruction=E2h = 0
Bit 17 = Support for volatile individual sector lock Write command, Instruction=E1h = 1
Bit 16 = Support for volatile individual sector lock Read command, Instruction=E0h = 1
Bit 15 = Support for (1-4-4) DTR_Read Command, Instruction = EEh = 1
Bit 14 = Support for (1-2-2) DTR_Read Command, Instruction = BEh = 0
Bit 13 = Support for (1-1-1) DTR_Read Command, Instruction = 0Eh = 0
Bit 12 = Support for Erase Command – Type 4 = 0
Bit 11 = Support for Erase Command – Type 3 = 1
Bit 10 = Support for Erase Command – Type 2 = 1
Bit 9 = Support for Erase Command – Type 1 = 1
Bit 8 = Support for (1-4-4) Page Program Command, Instruction = 3Eh =0
Bit 7 = Support for (1-1-4) Page Program Command, Instruction = 34h = 1
Bit 6 = Support for (1-1-1) Page Program Command, Instruction = 12h = 1
Bit 5 = Support for (1-4-4) FAST_READ Command, Instruction = ECh = 1
Bit 4 = Support for (1-1-4) FAST_READ Command, Instruction = 6Ch = 1
Bit 3 = Support for (1-2-2) FAST_READ Command, Instruction = BCh = 1
Bit 2 = Support for (1-1-2) FAST_READ Command, Instruction = 3Ch = 0
Bit 1 = Support for (1-1-1) FAST_READ Command, Instruction = 0Ch = 1
Bit 0 = Support for (1-1-1) READ Command, Instruction = 13h = 1
Nibble Format: 1111_1111_1111_0011_1000_1110_1111_1011
Hex Format: FF_F3_8E_FB
21h
44h
45h
46h
JEDEC 4 Byte Address
Instructions Parameter
Dword-2h
47h
Document Number: 002-00124 Rev. *A
52h
DCh
FFh
Bits 31:24 = FFh = Instruction for Erase Type 4: RFU
Bits 23:16 = DCh = Instruction for Erase Type 3 Block
Bits 15:8 = 52h = Instruction for Erase Type 2 Half Block
Bits 7:0 = 21h = Instruction for Erase Type 1 Sector
Page 139 of 145
ADVANCE
11.2
S25FL256L
Device ID Address Map
11.2.1
Field Definitions
Table 11.5 Manufacturer Device Type
Byte Address
Data
Description
00h
01h
Manufacturer ID for Spansion
01h
60h
Device ID Most Significant Byte - Memory Interface Type
02h
19h (256Mb)
Device ID Least Significant Byte - Density and Features
03h
Undefined
Reserved for future use
Table 11.6 Unique Device ID
Byte Address
11.3
Data
00h to 07
8 Byte Unique Device ID
08h to 0F
Additional 8 Byte Unique Device ID
10 to 1Fh
Undefined
20h to 37h
24 Bytes OEM Name
Description
64-bit unique ID number see section Section 7.3.1, Device Unique ID on page 47
Additional bytes for 128-bit unique ID number
Reserved for future use
For OEM Name
Initial Delivery State
The device is shipped from Cypress with non-volatile bits set as follows:
The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).
The Security Region address space has all bytes erased to FFh.
The SFDP address space contains the values as defined in the description of the SFDP address space.
The ID address space contains the values as defined in the description of the ID address space.
The Status Register 1 Non-volatile contains 00h (all SR1NV bits are cleared to 0’s).
The Configuration Register 1 Non-volatile contains 00h.
The Configuration Register 2 Non-volatile contains 60h.
The Configuration Register 3 Non-volatile contains 78h.
The Password Register contains FFFFFFFF-FFFFFFFFh
The IRP Register bits are FFFDh for Standard Part and FFFFh for High Security Part.
The PRPR Register bits are FFFFFFh
Document Number: 002-00124 Rev. *A
Page 140 of 145
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S25FL256L
12. Ordering Information
12.1
Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S25FL
256
L
AG
M
F
I
00
1
Packing Type
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
00 = SOIC16 footprint (300 mil)
01 = 8-contact WSON footprint
02 = 5 x 5 ball BGA footprint
03 = 4 x 6 ball BGA footprint
Temperature Range
I = Industrial (–40°C to +85°C)
V = Industrial Plus (–40°C to +105°C)
N = Extended (–40°C to +125°C)
Package Materials
F = Lead (Pb)-free
H = L ow-Halogen, Lead (Pb)-free
Package Type
M = 16-pin SOIC
N = 8-contact WSON 6 x 8 mm
B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
AG = 133 MHz
DP = 66 MHz DDR
Device Technology
L = 0.065 µm Floating Gate Process Technology
Density
256 = 256 Mb
Device Family
S25FL Cypress Memory 3.0 Volt-only, SPI Flash Memory
Document Number: 002-00124 Rev. *A
Page 141 of 145
ADVANCE
S25FL256L
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Table 12.1 General Market Valid OPN Combinations
Valid Combinations General Market
Base Ordering Part
Number
Speed
Option
Package and
Temperature
Model Number
Packing Type
AG
MFI, MFV, MFN
00
0, 1, 3
AG
NFI, NFV, NFN
01
0, 1, 3
(Base) + A +(Temp) + F + (Model Number)
AG
BHI, BHV, BHN
02, 03
0, 3
(Base) + A +(Temp) + H + (Model Number)
DP
MFI, MFV, MFN
00
0, 1, 3
(Base) + A +(Temp) + F + (Model Number)
DP
NFI, NFV, NFN
01
0, 1, 3
(Base) + A +(Temp) + F + (Model Number)
DP
BHI, BHV, BHN
02, 03
0, 3
(Base) + A +(Temp) + H + (Model Number)
Package Marking
(Base) + A +(Temp) + F + (Model Number)
S25FL256L
Document Number: 002-00124 Rev. *A
Page 142 of 145
ADVANCE
S25FL256L
Glossary
BCD
Binary Coded Decimal. A value in which each 4 bit nibble represents a decimal numeral.
Command
All information transferred between the host system and memory during one period while CS# is low. This
includes the instruction (sometimes called an operation code or opcode) and any required address, mode
bits, latency cycles, or data.
DDP
Dual Die Package = Two die stacked within the same package to increase the memory capacity of a single
package. Often also referred to as a Multi-Chip Package (MCP).
DDR
Double Data Rate = When input and output are latched on every edge of SCK.
Flash
The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large
blocks of memory bits in parallel, making the erase operation much faster than early EEPROM.
High
A signal voltage level ≥ VIH or a logic level representing a binary one (“1”).
Instruction
The 8 bit code indicating the function to be performed by a command (sometimes called an operation code
or opcode). The instruction is always the first 8 bits transferred from host system to the memory in any
command.
Low
A signal voltage level VIL or a logic level representing a binary zero (“0”).
LSB
Least Significant Bit = Generally the right most bit, with the lowest order of magnitude value, within a group
of bits of a register or data value.
MSB
Most Significant Bit = Generally the left most bit, with the highest order of magnitude value, within a group
of bits of a register or data value.
N/A
Not Applicable. A value is not relevant to situation described.
Non-Volatile
No power is needed to maintain data stored in the memory.
OPN
Ordering Part Number = The alphanumeric string specifying the memory device type, density, package,
factory non-volatile configuration, etc. used to select the desired device.
QPI
Quad Peripheral Interface
Page
256 Byte length and aligned group of data.
PCB
Printed Circuit Board
Register Bit References In the format: Register_name[bit_number] or Register_name[bit_range_MSB: bit_range_LSB]
Sector
Erase unit size; depending on device model and sector location this may be 4KBytes, 32KBytes or
64KBytes
SDR
Single Data Rate = When input is latched on the rising edge and output on the falling edge of SCK.
Write
An operation that changes data within volatile or non-volatile registers bits or non-volatile Flash memory.
When changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is
done, as part of the operation, such that the non-volatile data is modified by the write operation, in the
same way that volatile data is modified – as a single operation. The non-volatile data appears to the host
system to be updated by the single write command, without the need for separate commands for erase
and reprogram of adjacent, but unaffected data.
Document Number: 002-00124 Rev. *A
Page 143 of 145
ADVANCE
S25FL256L
13. Document History
Document Title: S25FL256L 256 Mbit (32 Mbyte)
3.0 V FL-L Flash Memory 3.0 V FL-L Flash Memory
Document Number: 002-00124
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
4905743
BWHA
09/18/2015
Initial release
*A
5147318
BWHA
02/22/2016
DC Characteristics – Industrial, Industrial Plus and Extended tables: changed
ISB Max value
SDR AC Characteristics table: changed Min values for tCH and tCL
Embedded Algorithm Performance Tables: changed value for tPP Max
Registers: added sentences; When volatile register bits are written, only the
volatile version of the register has the appropriate bits updated.
When either a non-volatile or volatile register is read, the volatile version of
the register is delivered.
Basic SPI Flash Parameter, JEDEC SFDP Rev B: changed 3Dh Data from
60h to 50h
Document Number: 002-00124 Rev. *A
Page 144 of 145
ADVANCE
S25FL256L
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
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Interface......................................... cypress.com/go/interface
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Memory........................................... cypress.com/go/memory
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Touch Sensing .................................... cypress.com/go/touch
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Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
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© Cypress Semiconductor Corporation, 2015-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-00124 Rev. *A
Revised February 22, 2016
Page 145 of 145
Cypress®, Spansion®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All products and company
names mentioned in this document may be the trademarks of their respective holders.
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