Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
S25FS128S/S25FS256S
1.8 V, Serial Peripheral Interface
with Multi-I/O, MirrorBit® Non-Volatile Flash
Features
■
Density
❐ S25FS128S-128 Mbits (16 MB)
❐ S25FS256S-256 Mbits (32 MB)
Erase status evaluation
100,000 Program-Erase Cycles, minimum
❐ 20 Year Data Retention, minimum
❐
❐
■
Serial Peripheral Interface (SPI)
❐ SPI Clock polarity and phase modes 0 and 3
❐ Double Data Rate (DDR) option
❐ Extended Addressing: 24- or 32-bit address options
❐ Serial Command subset and footprint compatible with S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families
❐ Multi I/O Command subset and footprint compatible with
S25FL-P, and S25FL-S SPI families
■
Read
❐ Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad
I/O
❐ Modes: Burst Wrap, Continuous (XIP), QPI
❐ Serial Flash Discoverable Parameters (SFDP) and Common
Flash Interface (CFI), for configuration information
■
■
Program
❐ 256- or 512-byte Page Programming buffer
❐ Program suspend and resume
❐ Automatic ECC – internal hardware Error Correction Code
generation with single-bit error correction
Erase
❐ Hybrid sector options
• Physical set of eight 4-KB sectors and one 32-KB sector
at the top or bottom of address space with all remaining
sectors of 64 KB or
• Physical set of eight 4-KB sectors and one 224-KB sector
at the top or bottom of address space with all remaining
sectors of 256 KB
❐ Uniform sector options
• Uniform 64-KB or 256-KB blocks for software compatibility
with higher density and future devices
❐ Erase suspend and resume
Cypress Semiconductor Corporation
Document Number: 002-00368 Rev. *M
•
■
Security Features
❐ One-Time Program (OTP) array of 1024 bytes
❐ Block Protection:
• Status Register bits to control protection against program
or erase of a contiguous range of sectors
• Hardware and software control options
❐ Advanced Sector Protection (ASP)
• Individual sector protection controlled by boot code or
password
• Option for password control of read access
■
Technology
®
❐ Cypress 65 nm MirrorBit Technology with Eclipse™
Architecture
■
Supply Voltage
❐ 1.7V to 2.0V
■
Temperature Range / Grade
❐ Industrial (-40°C to +85°C)
❐ Industrial Plus (–40°C to +105°C)
❐ Automotive AEC-Q100 Grade 3 (–40°C to +85°C)
❐ Automotive AEC-Q100 Grade 2 (–40°C to +105°C)
❐ Automotive AEC-Q100 Grade 1 (–40°C to +125°C)
■
Packages (All Pb-Free)
❐ 8-lead SOIC 208 mil (SOC008) — FS128S only
❐ WSON 6 5 mm (WND008) — FS128S only
❐ WSON 6 8 mm (WNH008)
❐ 16-lead SOIC 300 mil (SO3016 — FS256S only)
❐ BGA-24 6 8 mm
• 5 5 ball (FAB024) footprint
• 4 6 ball (FAC024) footprint
❐ Known Good Die, and Known Tested Die
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 22, 2019
S25FS128S/S25FS256S
Performance Summary
Maximum Read Rates
Command
Clock Rate (MHz)
MBps
Read
50
6.25
Fast Read
133
16.5
Dual Read
133
33
Quad Read
133
66
Clock Rate (MHz)
MBps
80
80
Maximum Read Rates DDR
Command
DDR Quad I/O Read
Typical Program and Erase Rates
Operation
KBps
Page Programming (256-bytes Page Buffer)
712
Page Programming (512-bytes Page Buffer)
1080
4-KB Physical Sector Erase (Hybrid Sector Option)
16
64-KB Physical Sector Erase (Hybrid Sector Option)
275
256-KB Sector Erase (Uniform Logical Sector Option)
275
Typical Current Consumption (–40°C to +85°C)
Operation
Current (mA)
Serial Read 50 MHz
10
Serial Read 133 MHz
20
Quad Read 133 MHz
60
Quad DDR Read 80 MHz
70
Program
60
Erase
60
Standby
0.025
Deep Power-Down
0.006
Document Number: 002-00368 Rev. *M
Page 2 of 158
S25FS128S/S25FS256S
Contents
1.
1.1
1.2
1.3
1.4
Overview .......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
5
8
8
6.
6.1
6.2
6.3
6.4
Physical Interface ....................................................... 40
SOIC 16-Lead Package ................................................ 40
8-Connector Packages ................................................. 42
FAB024 24-Ball BGA Package ..................................... 46
FAC024 24-Ball BGA Package ..................................... 48
Hardware Interface
Software Interface
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
Signal Descriptions ..................................................... 9
Input/Output Summary................................................... 9
Multiple Input / Output (MIO)........................................ 10
Serial Clock (SCK) ....................................................... 10
Chip Select (CS#) ........................................................ 10
Serial Input (SI) / IO0 ................................................... 10
Serial Output (SO) / IO1............................................... 10
Write Protect (WP#) / IO2 ............................................ 11
IO3 / RESET# ............................................................. 11
Voltage Supply (VCC).................................................. 12
Supply and Signal Ground (VSS) ................................. 12
Not Connected (NC) .................................................... 12
Reserved for Future Use (RFU)................................... 12
Do Not Use (DNU) ....................................................... 12
Block Diagrams............................................................ 13
7.
7.1
7.2
7.3
7.4
3.
3.1
3.2
3.3
3.4
3.5
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
15
15
16
20
24
24
4.
4.1
4.2
4.3
4.4
4.5
4.6
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Latch-Up Characteristics..............................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
25
25
25
25
26
27
29
5.
5.1
5.2
5.3
5.4
5.5
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics ..............................................
31
31
31
32
35
38
7.5
7.6
Address Space Maps.................................................. 50
Overview....................................................................... 50
Flash Memory Array...................................................... 51
ID-CFI Address Space .................................................. 54
JEDEC JESD216 Serial Flash Discoverable
Parameters (SFDP) Space. .......................................... 54
OTP Address Space ..................................................... 54
Registers....................................................................... 56
8.
8.1
8.2
8.3
8.4
8.5
Data Protection ........................................................... 73
Secure Silicon Region (OTP)........................................ 73
Write Enable Command................................................ 74
Block Protection ............................................................ 74
Advanced Sector Protection ......................................... 76
Recommended Protection Process .............................. 81
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Commands .................................................................. 82
Command Set Summary............................................... 83
Identification Commands .............................................. 89
Register Access Commands......................................... 91
Read Memory Array Commands ................................ 103
Program Flash Array Commands ............................... 110
Erase Flash Array Commands.................................... 112
One-Time Program Array Commands ........................ 119
Advanced Sector Protection Commands .................... 120
Reset Commands ....................................................... 127
DPD Commands ......................................................... 129
10.
Embedded Algorithm Performance Tables............. 131
11.
11.1
11.2
11.3
Data Integrity ............................................................. 132
Erase Endurance ........................................................ 132
Data Retention ............................................................ 132
Serial Flash Discoverable Parameters
(SFDP) Address Map.................................................. 132
11.4 Device ID and Common Flash Interface (ID-CFI)
Address Map............................................................... 135
11.5 Initial Delivery State .................................................... 152
Ordering Information
12. Ordering Part Number .............................................. 153
Revision History ............................................................... 155
Sales, Solutions, and Legal Information ........................ 158
Document Number: 002-00368 Rev. *M
Page 3 of 158
S25FS128S/S25FS256S
1.
Overview
1.1
General Description
The Cypress S25FS-S family devices are flash non-volatile memory products using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
TheS25FS-S family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and
output (Single I/O or SIO) is supported as well as optional 2-bit (Dual I/O or DIO) and 4-bit wide Quad I/O (QIO) or Quad Peripheral
Interface (QPI) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, there are Double Data Rate
(DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.
The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation,
resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS-S family devices at the higher
clock rates supported, with Quad or DDR Quad commands, the instruction read transfer rate can match or exceed traditional parallel
interface, asynchronous, NOR flash memories, while reducing signal count dramatically.
The S25FS-S family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal
for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
Document Number: 002-00368 Rev. *M
Page 4 of 158
S25FS128S/S25FS256S
1.2
Migration Notes
1.2.1
Features Comparison
The S25FS-S family is command subset and footprint compatible with prior generation FL-S, FL-K, and FL-P families. However, the
power supply and interface voltages are nominal 1.8 V.
Table 1. Cypress SPI Families Comparison
Parameter
Technology Node
FS-S
FL-S
FL-K
FL-P
65 nm
65 nm
90 nm
90 nm
Architecture
MirrorBit Eclipse
MirrorBit Eclipse
Floating Gate
MirrorBit
Density
128 Mb, 256 Mb
128 Mb, 256 Mb, 512 Mb, 1
Gb
4 Mb - 128 Mb
32 Mb - 256 Mb
x1, x2, x4
x1, x2, x4
x1, x2, x4
x1, x2, x4
1.7 V–2.0 V
2.7 V–3.6 V / 1.65 V–3.6 V
VIO
2.7 V–3.6 V
2.7 V–3.6 V
Bus Width
Supply Voltage
Normal Read Speed (SDR)
6 MB/s (50 MHz)
6 MB/s (50 MHz)
6 MB/s (50 MHz)
6 MB/s (40 MHz)
Fast Read Speed (SDR)
16.5 MB/s (133 MHz)
17 MB/s (133 MHz)
13 MB/s (104 MHz)
13 MB/s (104 MHz)
Dual Read Speed (SDR)
33 MB/s (133 MHz)
26 MB/s (104 MHz)
26 MB/s (104 MHz)
20 MB/s (80 MHz)
Quad Read Speed (SDR)
66 MB/s (133 MHz)
52 MB/s (104 MHz)
52 MB/s (104 MHz)
40 MB/s (80 MHz)
Quad Read Speed (DDR)
80 MB/s (80 MHz)
80 MB/s (80 MHz)
256B / 512B
256B / 512B
256B
256B
64 kB / 256 kB
64 kB / 256 kB
4 kB / 32 kB / 64 kB
64 kB / 256 kB
4 kB (option)
4 kB (option)
4 kB
4 kB
Sector Erase Rate (typ.)
500 kB/s
500 kB/s
136 kB/s (4 kB)
437 kB/s (64 kB)
130 kB/s
Page Programming Rate
(typ.)
0.71 MB/s (256B)
1.08 MB/s (512B)
1.2 MB/s (256B)
1.5 MB/s (512B)
365 kB/s
170 kB/s
1024B
1024B
768B (3x256B)
506B
Advanced Sector Protection
Yes
Yes
No
No
Auto Boot Mode
No
Yes
No
No
Erase Suspend/Resume
Yes
Yes
Yes
No
Program Suspend/Resume
Yes
Yes
Yes
No
Yes
No
Yes
Yes
–40 °C to +85 °C / +105 °C /
+125 °C
–40 °C to +85 °C / +105 °C
–40 °C to +85 °C
–40 °C to +85 °C / +105 °C
Program Buffer Size
Erase Sector Size
Parameter Sector Size
OTP
Deep Power-Down
Operating Temperature
Notes
1. The 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. The FL-P column indicates FL129P MIO SPI device (for 128-Mb density), FL128P does not support MIO, OTP, or 4-kB sectors.
3. 64-kB Sector Erase option only for 128-Mb/256-Mb density FL-P, FL-S and FS-S devices.
4. The FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. 512-Mb/1-Gb FL-S devices support 256-kB sector only.
6. Only 128-Mb/256-Mb density FL-S devices have 4-kB parameter sector option.
7. Refer to individual data sheets for further details.
Document Number: 002-00368 Rev. *M
Page 5 of 158
S25FS128S/S25FS256S
1.2.2
Known Differences from Prior Generations
1.2.2.1 Error Reporting
FL-K and FL-P memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FS-S and FL-S families do have error reporting status bits for program and erase operations. These can be set when
there is an internal failure to program or erase, or when there is an attempt to program or erase a protected sector. In these cases
the program or erase operation did not complete as requested by the command. The P_ERR or E_ERR bits and the WIP bit will be
set to and remain 1 in SR1V. The clear Status Register command must be sent to clear the errors and return the device to standby
state.
1.2.2.2 Secure Silicon Region (OTP)
The FS-S size and format (address map) of the One-Time Program area is different from FL-K and FL-P generations. The method
for protecting each portion of the OTP area is different. For additional details see Secure Silicon Region (OTP) on page 73.
1.2.2.3 Configuration Register Freeze Bit
The Configuration Register 1 Freeze bit CR1V[0], locks the state of the Block Protection bits (SR1NV[4:2] and SR1V[4:2]),
TBPARM_O bit (CR1NV[2]), and TBPROT_O bit (CR1NV[5]), as in prior generations. In the FS-S and FL-S families the Freeze bit
also locks the state of the Configuration Register 1 BPNV_O bit (CR1NV[3]), and the Secure Silicon Region (OTP) area.
1.2.2.4 Sector Erase Commands
The command for erasing a 4-KB sector is supported only for use on 4-KB parameter sectors at the top or bottom of the FS-S device
address space.
The command for erasing an 8-KB area (two 4-KB sectors) is not supported.
The command for erasing a 32-KB area (eight 4-KB sectors) is not supported.
The Sector Erase command (SE) for FS-S 64-KB sectors is supported when the configuration option for uniform 64-KB sector is
selected or, when the hybrid configuration option for 4-KB parameter sectors with 64-KB uniform sectors is used. When the hybrid
option is in use, the 64-KB erase command may be used to erase the 32-KB of address space adjacent to the group of eight 4-KB
sectors. The 64-KB erase command in this case is erasing the 64-KB sector that is partially overlaid by the group of eight 4-KB
sectors without affecting the 4-KB sectors. This provides erase control over the 32 KB of address space without also forcing the
erase of the 4-KB sectors. This is different behavior than implemented in the FL-S family. In the FL-S family, the 64-KB Sector Erase
command can be applied to a 64-KB block of 4-KB sectors to erase the entire block of parameter sectors in a single operation. In the
FS-S, the parameter sectors do not fill an entire 64-KB block so only the 4-KB Parameter Sector Erase (20h) is used to erase
parameter sectors.
The erase command for a 256-KB sector replaces the 64-KB erase command when the configuration option for 256-KB uniform
logical sectors is used.
1.2.2.5 Deep Power-Down
The Deep Power-Down (DPD) function is supported in the FS-S family of devices.
1.2.2.6 WRR Single Register Write
In some legacy SPI devices, a Write Registers (WRR) command with only one data byte would update Status Register 1 and clear
some bits in Configuration Register 1, including the Quad Mode bit. This could result in unintended exit from Quad Mode. The
S25FS-S family only updates Status Register 1 when a single data byte is provided. The Configuration Register 1 is not modified in
this case.
Document Number: 002-00368 Rev. *M
Page 6 of 158
S25FS128S/S25FS256S
1.2.2.7 Other Legacy Commands Not Supported
Autoboot Related Commands
Bank Address Related Commands
Dual Output Read
Quad Output Read
Quad Page Program (QPP) - replaced by Page Program in QPI Mode
DDR Fast Read
DDR Dual I/O Read
1.2.2.8 New Features
The FS-S family introduces new features to Cypress SPI category memories:
Single 1.8V power supply for core and I/O voltage.
Configurable initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read commands
Quad Peripheral Interface (QPI, 4-4-4) read mode in which all transfers are 4 bits wide, including instructions
JEDEC JESD216 standard, Serial Flash Discoverable Parameters (SFDP) that provide device feature and configuration
information.
Evaluate Erase Status command to determine if the last erase operation on a sector completed successfully. This command can
be used to detect incomplete erase due to power loss or other causes. This command can be helpful to Flash File System software
in file system recovery after a power loss.
Advanced Sector Protection (ASP) Permanent Protection. A bit is added to the ASP register to provide the option to make
protection of the Persistent Protection Bits (PPB) permanent. Also, when one of the two ASP protection modes is selected, all OTP
configuration bits in all registers are protected from further programming so that all OTP configuration settings are made permanent.
The OTP address space is not protected by the selection of an ASP protection mode. The Freeze bit (CR1V[0]) may be used to
protect the OTP Address Space.
Document Number: 002-00368 Rev. *M
Page 7 of 158
S25FS128S/S25FS256S
1.3
Glossary
BCD
(Binary Coded Decimal)
A value in which each 4-bit nibble represents a decimal numeral.
Command
All information transferred between the host system and memory during one period while CS# is low. This
includes the instruction (sometimes called an operation code or opcode) and any required address, mode
bits, latency cycles, or data.
DDP
(Dual Die Package)
Two die stacked within the same package to increase the memory capacity of a single package. Often also
referred to as a Multi-Chip Package (MCP).
DDR
(Double Data Rate)
When input and output are latched on every edge of SCK.
ECC
ECC Unit = 16 byte aligned and length data groups in the main Flash array and OTP array, each of which has
its own hidden ECC syndrome to enable error correction on each group.
Flash
The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large
blocks of memory bits in parallel, making the erase operation much faster than early EEPROM.
High
A signal voltage level ≥ VIH or a logic level representing a binary one (1).
Instruction
The 8-bit code indicating the function to be performed by a command (sometimes called an operation code or
opcode). The instruction is always the first 8 bits transferred from host system to the memory in any
command.
Low
A signal voltage level VIL or a logic level representing a binary zero (0).
LSB
(Least Significant Bit)
Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or
data value.
MSB
(Most Significant Bit)
Generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or
data value.
N/A
(Not Applicable)
A value is not relevant to situation described.
Non-Volatile
No power is needed to maintain data stored in the memory.
OPN
Ordering Part Number. The alphanumeric string specifying the memory device type, density, package, factory
non-volatile configuration, etc. used to select the desired device.
Page
512-byte or 256-byte aligned and length group of data. The size assigned for a page depends on the
Ordering Part Number.
PCB
Printed Circuit Board.
Register Bit References
Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB: bit_range_LSB]
SDR
(Single Data Rate)
When input is latched on the rising edge and output on the falling edge of SCK.
Sector
Erase unit size; depending on device model and sector location this may be 4 KB, 64 KB or 256 KB.
Write
An operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory.
When changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done,
as part of the operation, such that the non-volatile data is modified by the write operation, in the same way
that volatile data is modified – as a single operation. The non-volatile data appears to the host system to be
updated by the single write command, without the need for separate commands for erase and reprogram of
adjacent, but unaffected data.
1.4
Other Resources
1.4.1
Cypress Flash Memory Roadmap
www.cypress.com/Flash-Roadmap
1.4.2
Links to Software
www.cypress.com/software-and-drivers-cypress-flash-memory
1.4.3
Links to Application Notes
www.cypress.com/cypressappnotes
Document Number: 002-00368 Rev. *M
Page 8 of 158
S25FS128S/S25FS256S
Hardware Interface
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large
number of signal connections and larger package size. The large number of connections increase power consumption due to so
many signals switching and the larger package increases cost.
The S25FS-S family reduces the number of signals for connection to the host system by serially transferring all control, address, and
data information over 4 to 6 signals. This reduces the cost of the memory package, reduces signal switching power, and either
reduces the host connection count or frees host connectors for use in providing other features.
The S25FS-S family uses the industry standard single-bit Serial Peripheral Interface (SPI) and also supports optional extension
commands for 2-bit (Dual) and 4-bit (Quad) wide serial transfers. This multiple width interface is called SPI Multi-I/O or SPI-MIO.
2.
Signal Descriptions
2.1
Input/Output Summary
Table 2. Signal List
Signal Name
Type
SCK
Input
Serial Clock.
Description
Chip Select.
CS#
Input
SI / IO0
I/O
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1
I/O
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
Write Protect when not in Quad Mode (CR1V[1] = 0 and SR1NV[7] = 1).
IO2 when in Quad Mode (CR1V[1] = 1).
WP# / IO2
I/O
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for
Quad commands or write protection. If write protection is enabled by SR1NV[7] = 1 and CR1V[1] = 0, the host
system is required to drive WP# high or low during a WRR or WRAR command.
IO3 in Quad-I/O mode, when Configuration Register 1 QUAD bit, CR1V[1] =1, and CS# is low.
IO3 / RESET#
I/O
RESET# when enabled by CR2V[5]=1 and not in Quad-I/O mode, CR1V[1] = 0, or when enabled in Quad
Mode, CR1V[1] = 1 and CS# is high.
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for
Quad commands or RESET#.
VCC
Supply
Power Supply.
VSS
Supply
Ground.
Unused
Not Connected. No device internal signal is connected to the package connector nor is there any future plan
to use the connector for a signal. The connection may safely be used for routing space for a signal on a
Printed Circuit Board (PCB). However, any signal connected to an NC must not have voltage levels higher
than VCC.
NC
RFU
DNU
Reserved
Reserved for Future Use. No device internal signal is currently connected to the package connector but
there is potential future use of the connector for a signal. It is recommended to not use RFU connectors for
PCB routing channels so that the PCB may take advantage of future enhanced features in compatible
footprint devices.
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The connection may be
used by Cypress for test or other purposes and is not intended for connection to any host system signal. Any
DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down
resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections
for PCB signal routing channels. Do not connect any host system signal to this connection.
Document Number: 002-00368 Rev. *M
Page 9 of 158
S25FS128S/S25FS256S
2.2
Multiple Input / Output (MIO)
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the Serial Input (SI)
signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI/IO0 signal. Address or data is sent from
the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host
similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
QPI Mode transfers all instructions, address, and data from the host to the memory as four bit (nibble) groups on IO0, IO1, IO2, and
IO3. Data is returned to the host similarly as four bit (nibble) groups on IO0, IO1, IO2, and IO3.
2.3
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on
the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR commands, and after every edge in
DDR commands.
2.4
Chip Select (CS#)
The Chip Select signal indicates when a command is transferring information to or from the device and the other signals are relevant
for the memory device.
When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are
high impedance. The device will be in the Standby Power mode, unless an internal embedded operation is in progress. An
embedded operation is indicated by the Status Register 1 Write-In-Progress bit (SR1V[1]) set to 1, until the operation is completed.
Some example embedded operations are: Program, Erase, or Write Registers (WRR) operations.
Driving the CS# input to the logic low state enables the device, placing it in the Active Power mode. After power-up, a falling edge on
CS# is required prior to the start of any command.
2.5
Serial Input (SI) / IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed.
Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses, and data to be
programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in
SDR commands, and on every edge of SCK, in DDR commands).
2.6
Serial Output (SO) / IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock
signal.
SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be programmed
(values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR commands,
and on every edge of SCK, in DDR commands).
Document Number: 002-00368 Rev. *M
Page 10 of 158
S25FS128S/S25FS256S
2.7
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), during a WRR or WRAR command and while the Status Register Write Disable (SRWD_NV) bit of
Status Register 1 (SR1NV[7]) is set to a 1, it is not possible to write to Status Register 1 or Configuration Register 1 related registers.
In this situation, a WRR command is ignored, a WRAR command selecting SR1NV, SR1V, CR1NV, or CR1V is ignored, and no
error is set.
This prevents any alteration of the Block Protection settings. As a consequence, all the data bytes in the memory area that are
protected by the Block Protection feature are also hardware protected against data modification if WP# is Low during a WRR or
WRAR command with SRWD_NV set to 1.
The WP# function is not available when the Quad Mode is enabled (CR1V[1] = 1). The WP# function is replaced by IO2 for input and
output during Quad Mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal)
as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host system if not
used for Quad Mode or protection.
2.8
IO3 / RESET#
IO3 is used for input and output during Quad Mode (CR1V[1] = 1) for receiving addresses, and data to be programmed (values are
latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every
edge of SCK, in DDR commands).
The IO3 / RESET# signal may also be used to initiate the hardware reset function when the reset feature is enabled by writing
Configuration Register 2 non-volatile bit 5 (CR2V[5] = 1). The input is only treated as RESET# when the device is not in Quad-I/O
mode, CR1V[1] = 0, or when CS# is high. When Quad I/O mode is in use, CR1V[1]=1, and the device is selected with CS# low, the
IO3 / RESET# is used only as IO3 for information transfer. When CS# is high, the IO3 / RESET# is not in use for information transfer
and is used as the RESET# input. By conditioning the reset operation on CS# high during Quad Mode, the reset function remains
available during Quad Mode.
When the system enters a reset condition, the CS# signal must be driven high as part of the reset process and the IO3 / RESET#
signal is driven low. When CS# goes high the IO3 / RESET# input transitions from being IO3 to being the RESET# input. The reset
condition is then detected when CS# remains high and the IO3 / RESET# signal remains low for tRP. If a reset is not intended, the
system is required to actively drive IO3 / Reset# to high along with CS# being driven high at the end of a transfer of data to the
memory. Following transfers of data to the host system, the memory will drive IO3 high during tCS. This will ensure that IO3 / Reset
is not left floating or being pulled slowly to high by the internal or an external passive pull-up. Thus, an unintended reset is not
triggered by the IO3 / RESET# not being recognized as high before the end of tRP.
The IO3 / RESET# signal is unused when the reset feature is disabled (CR2V[5] = 0).
The IO3 / RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Mode
or the reset function. The internal pull-up will hold IO3 / RESET high after the host system has actively driven the signal high and
then stops driving the signal.
Note that IO3 / RESET# cannot be shared by more than one SPI-MIO memory if any of them are operating in Quad I/O mode as IO3
being driven to or from one selected memory may look like a reset signal to a second non-selected memory sharing the same
IO3 / RESET# signal.
Document Number: 002-00368 Rev. *M
Page 11 of 158
S25FS128S/S25FS256S
2.9
Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read,
program, and erase.
2.10
Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.
2.11
Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The
connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).
2.12
Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but there is potential future use of the connector. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced
features in compatible footprint devices.
2.13
Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other
purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the
signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.
Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
Document Number: 002-00368 Rev. *M
Page 12 of 158
S25FS128S/S25FS256S
2.14
Block Diagrams
Figure 1. Bus Master and Memory Devices on the SPI Bus — Single Bit Data Path
RESET#
RESET#
WP#
SI
SO
SCK
WP#
SO
SI
SCK
CS2#
CS2#
CS1#
CS1#
FS-S
Flash
FS-S
Flash
SPI
Bus Master
Figure 2. Bus Master and Memory Devices on the SPI Bus — Dual Bit Data Path
RESET#
RESET#
WP#
IO1
IO0
SCK
WP#
IO1
IO0
SCK
CS2#
CS2#
CS1#
SPI
Bus Master
Document Number: 002-00368 Rev. *M
CS1#
FS-S
Flash
FS-S
Flash
Page 13 of 158
S25FS128S/S25FS256S
Figure 3. Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path
RESET# / IO3
IO2
IO1
IO0
SCK
CS1#
SPI
Bus Master
Document Number: 002-00368 Rev. *M
IO3 / RESET#
IO2
IO1
IO0
SCK
CS1#
FS-S
Flash
Page 14 of 158
S25FS128S/S25FS256S
3.
Signal Protocols
3.1
SPI Clock Modes
3.1.1
Single Data Rate (SDR)
The S25FS-S family can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is
always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data.
SCK will stay at logic low state with CPOL = 0, CPHA = 0
SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 4. SPI SDR Modes Supported
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
CS#
SI
MSB
SO
MSB
Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by showing SCK as both
high and low at the fall of CS#. In some cases a timing diagram may show only Mode 0 with SCK low at the fall of CS#. In such a
case, Mode 0 timing simply means the clock is high at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of
CS# is needed for Mode 0.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0 the beginning of the
first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low
at the beginning of a command.
3.1.2
Double Data Rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always latched on the rising
edge of clock, the same as in SDR commands. However, the address and input data that follow the instruction are latched on both
the rising and falling edges of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end
of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the next falling edge of
SCK. In Mode 0 the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge
of SCK because SCK is already low at the beginning of a command.
Figure 5. SPI DDR Modes Supported
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
CS#
Transfer_Phase
SI
SO
Document Number: 002-00368 Rev. *M
Instruction
Inst. 7
Address
Inst. 0 A31 A30
Mode
A0 M7 M6
Dummy / DLP
M0
DLP7
DLP0
D0 D1
Page 15 of 158
S25FS128S/S25FS256S
3.2
Command Protocol
All communication between the host system and S25FS-S family memory devices is in the form of units called commands.
All commands begin with an 8-bit instruction that selects the type of information transfer or device operation to be performed.
Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the
memory. All instruction, address, and data information is transferred sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three
command phases:
instruction
address and instruction modifier (Continuous Read mode bits)
data
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI signal. Data may be
sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol for single bit width instruction, single
bit width address and modifier, single bit data.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)
groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0,
IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command protocols.
The S25FS-S family also supports a QPI Mode in which all information is transferred in 4-bit width, including the instruction, address,
modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host driving
the Chip Select (CS#) signal low throughout a command.
The Serial Clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
Each command begins with an 8-bit (byte) instruction. The instruction selects the type of information transfer or device operation
to be performed. The instruction transfers occur on SCK rising edges. However, some read commands are modified by a prior read
command, such that the instruction is implied from the earlier command. This is called Continuous Read mode. When the device is
in Continuous Read mode, the instruction bits are not transmitted at the beginning of the command because the instruction is the
same as the read command that initiated the Continuous Read mode. In Continuous Read mode the command will begin with the
read address. Thus, Continuous Read mode removes eight instruction bits from each read command in a series of same type read
commands.
The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces
in the device. The instruction determines the address space used. The address may be either a 24-bit or a 32-bit, byte boundary,
address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
In legacy SPI mode, the width of all transfers following the instruction are determined by the instruction sent. Following transfers
may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per (dual)
transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per (quad) transfer on the IO0-IO3 signals. Within the dual
or quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher numbered IO
signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
In QPI Mode, the width of all transfers is a 4-bit wide (Quad) transfer on the IO0-IO3 signals.
Dual and Quad I/O read instructions send an instruction modifier called Continuous Read mode bits, following the address, to
indicate whether the next command will be of the same type with an implied, rather than an explicit, instruction. These mode bits
initiate or end the Continuous Read mode. In Continuous Read mode, the next command thus does not provide an instruction byte,
only a new address and mode bits. This reduces the time needed to send each command when the same command type is repeated
in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR
commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before
read data is returned to the host.
Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
Document Number: 002-00368 Rev. *M
Page 16 of 158
S25FS128S/S25FS256S
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles (also referred to
as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on SCK falling edge at
the end of the last read latency cycle. The first read data bits are considered transferred to the host on the following SCK rising edge.
Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
If the command returns read data to the host, the device continues sending data transfers until the host takes the CS# signal high.
The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the command.
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go high after the
eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be driven high
when the number of bits after the CS# signal was driven low is an exact multiple of eight bits. If the CS# signal does not go high
exactly at the eight bit boundary of the instruction or write data, the command is rejected and not executed.
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first. The data bits are
shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address byte sent first. The following
bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The
embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded
operation. These are discussed in the individual command descriptions.
Depending on the command, the time for execution varies. A command to read status information from an executing command is
available to determine when the command completes execution and whether the command was successful.
3.2.1
Command Sequence Examples
Figure 6. Stand Alone Instruction Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Figure 7. Single Bit Wide Input Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
Figure 8. Single Bit Wide Output Command
CS#
SCK
SI
7
6
5
4
3
SO
Phase
2
1
0
7
Instruction
Document Number: 002-00368 Rev. *M
6
5
4
3
Data 1
2
1
0
7
6
5
4
3
2
1
0
Data 2
Page 17 of 158
S25FS128S/S25FS256S
Figure 9. Single Bit Wide I/O Command without Latency
CS#
SCK
SI
7
6
5
4
3
2
1
0 31
1
0
SO
7
Phase
Instruction
6
5
4
Address
3
2
1
0
7
6
5
4
Data 1
3
2
1
0
2
1
0
4
2
0
5
3
1
Data 2
Figure 10. Single Bit Wide I/O Command with Latency
CS#
SCK
SI
7
6
5
4
3
2
1
0 31
1
0
SO
7
Phase
Instruction
Address
6
5
4
Dummy Cycles
3
Data 1
Figure 11. Dual I/O Command
CS#
SCK
IO0
7
6
5
4
3
2
1
0
30
IO1
31
Phase
Instruction
2
0
6
4
2
0
3
1
7
5
3
1
Address
6
7
Mode
Dum
4
2
0
6
5
3
1
7
Data 1
Data 2
Figure 12. Quad I/O Command
CS#
SCK
IO0
7
6
5
28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
D1
D2
D3
D4
Figure 13. Quad I/O Read Command in QPI Mode
CS#
SCK
IO0
4
0
28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
30
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
31
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Document Number: 002-00368 Rev. *M
Address
Mode
Dummy
D1
D2
D3
D4
Page 18 of 158
S25FS128S/S25FS256S
Figure 14. DDR Quad I/O Read
CS#
SCK
IO0
28 24 20 16 12 8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
7
6
5
29 25 21 17 13 9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
30 26 22 18 14 10 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
31 27 23 19 15 11 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1
D2
Figure 15. DDR Quad I/O Read in QPI Mode
CS#
SCK
IO0
4
0
28 24 20 16 12 8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
5
1
29 25 21 17 13 9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
6
2
30 26 22 18 14 10 6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
7
3
31 27 23 19 15 11 7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
DLP
D1
D2
Additional sequence diagrams, specific to each command, are provided in Commands on page 82.
Document Number: 002-00368 Rev. *M
Page 19 of 158
S25FS128S/S25FS256S
3.3
Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3. Interface States Summary
Interface State
Power-Off
VCC
SCK
CS#
IO3 /
RESET#
WP# / IO2
SO / IO1
SI / IO0
133 MHz SDR, or > 80 MHz DDR is not supported by this family of devices.
39. The Dual I/O, Quad I/O, QPI, DDR Quad I/O, and DDR QPI, command protocols include Continuous Read mode bits following the address. The clock cycles for these
bits are not counted as part of the latency cycles shown in the table. Example: the legacy
Quad I/O command has 2 Continuous Read mode cycles following the address. Therefore, the legacy Quad I/O command without additional read latency is supported
only up to the frequency shown in the table for a read latency of 0 cycles. By increasing the variable read latency the frequency of the Quad I/O command can be
increased to allow operation up to the maximum supported 133 MHz frequency.
40. Other read commands have fixed latency, e.g. Read always has zero read latency. RSFDP always has eight cycles of latency.
41. DDR QPI is only supported for Latency Cycles 1 through 5 and for clock frequency of up to 68 MHz.
Document Number: 002-00368 Rev. *M
Page 64 of 158
S25FS128S/S25FS256S
7.6.4.2 Configuration Register 2 Volatile (CR2V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), 4BAM.
Table 36. Configuration Register 2 Volatile (CR2V)
Bits
Field Name
Function
7
AL
Address Length
6
QA
QPI
5
IO3R_S
IO3 Reset
4
RFU
Reserved
RL
Read Latency
Type
Default
State
Description
1 = 4 byte address.
0 = 3 byte address.
1 = Enabled - QPI (4-4-4) protocol in use.
0 = Disabled - Legacy SPI protocols in use, instruction is
always serial on SI.
Volatile
CR2NV
1 = Enabled - IO3 is used as RESET# input when CS# is
high or Quad Mode is disabled CR1V[1]=1.
0 = Disabled - IO3 has no alternate function, hardware reset
is disabled.
Reserved for Future Use.
3
2
1
0 to 15 latency (dummy) cycles following read address or
continuous mode bits.
0
Address Length CR2V[7]: This bit controls the expected address length for all commands that require address and are not fixed
3-byte only or 4-byte (32-bit) only address. See S25FS-S Family Command Set (sorted by function) on page 85 for command
address length. This volatile Address Length configuration bit enables the address length to be changed during normal operation.
The 4-byte address mode (4BAM) command directly sets this bit into 4-byte address mode.
QPI CR2V[6]: This bit controls the expected instruction width for all commands. This volatile QPI configuration bit enables the
device to enter and exit QPI Mode during normal operation. When this bit is set to QPI Mode, the Quad bit is also set to Quad Mode
(CR1V[1] = 1). When this bit is cleared to legacy SPI mode, the Quad bit is not affected.
IO3 Reset CR2V[5]: This bit controls the IO3 / RESET# signal behavior. This volatile IO3 Reset configuration bit enables the use of
IO3 as a RESET# input during normal operation.
Read Latency CR2V[3:0]: This bit controls the read latency (dummy cycle) delay in variable latency read commands These volatile
configuration bits enable the user to adjust the read latency during normal operation to optimize the latency for different commands
or, at different operating frequencies, as needed.
Document Number: 002-00368 Rev. *M
Page 65 of 158
S25FS128S/S25FS256S
7.6.5
Configuration Register 3
Configuration Register 3 controls certain command behaviors. The register bits can be read and changed using the Read Any
Register and Write Any Register commands. The non-volatile register provides the POR, hardware reset, or software reset state of
the controls. These configuration bits are OTP and may be programmed to their opposite state one time during system configuration
if needed. The volatile version of Configuration Register 3 allows the configuration to be changed during system operation or testing.
7.6.5.1 Configuration Register 3 Non-Volatile (CR3NV)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 37. Configuration Register 3 Non-Volatile (CR3NV)
Bits
Field Name
Function
Type
Default
State
Description
7
RFU
Reserved
0
Reserved for Future Use.
6
RFU
Reserved
0
Reserved for Future Use.
5
BC_NV
Blank Check
0
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
4
02h_NV
Page Buffer Wrap
0
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
3
20h_NV
4-kB Erase
0
1 = 4-kB Erase disabled (Uniform Sector Architecture).
0 = 4-kB Erase enabled (Hybrid Sector Architecture).
2
30h_NV
Clear Status / Resume
Select
0
1 = 30h is Erase or Program Resume command.
0 = 30h is clear status command.
1
D8h_NV
Block Erase Size
0
1 = 256-kB Erase.
0 = 64-kB Erase.
0
F0h_NV
Legacy Software Reset
Enable
0
1 = F0h software reset is enabled.
0 = F0h software reset is disabled (ignored).
OTP
Blank Check Non-Volatile CR3NV[5]: This bit controls the POR, hardware reset, or software reset state of the blank check during
erase feature.
02h Non-Volatile CR3NV[4]: This bit controls the POR, hardware reset, or software reset state of the Page Programming Buffer
address wrap point.
20h Non-Volatile CR3NV[3]: This bit controls the POR, hardware reset, or software reset state of the availability of 4-kB parameter
sectors in the main flash array address map.
30h Non-Volatile CR3NV[2]: This bit controls the POR, hardware reset, or software reset state of the 30h instruction code is used.
D8h Non-Volatile CR3NV[1]: This bit controls the POR, hardware reset, or software reset state of the configuration for the size of
the area erased by the D8h or DCh instructions.
F0h Non-Volatile CR3NV[0]: This bit controls the POR, hardware reset, or software reset state of the availability of the Cypress
legacy FL-S family software reset instruction.
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7.6.5.2 Configuration Register 3 Volatile (CR3V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 38. Configuration Register 3 Volatile (CR3V)
Bits
Field Name
Function
Type
Default
State
Description
7
RFU
Reserved
Reserved for Future Use.
6
RFU
Reserved
Reserved for Future Use.
5
BC_V
Blank Check
4
02h_V
Page Buffer Wrap
3
20h_V
4-kB Erase
2
30h_V
Clear Status / Resume
Select
1
D8h_V
Block Erase Size
0
F0h_V
Legacy Software Reset
Enable
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
Volatile
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
Volatile,
Read Only
CR3NV
1 = 4-kB Erase disabled (Uniform Sector Architecture).
0 = 4-kB Erase enabled (Hybrid Sector Architecture).
1 = 30h is Erase or Program Resume command.
0 = 30h is Clear Status command.
Volatile
1 = 256-kB Erase.
0 = 64-kB Erase.
1 = F0h software reset is enabled.
0 = F0h software reset is disabled (ignored).
Blank Check Volatile CR3V[5]: This bit controls the blank check during erase feature. When this feature is enabled an erase
command first evaluates the Erase Status of the sector. If the sector is found to have not completed its last erase successfully, the
sector is unconditionally erased. If the last erase was successful, the sector is read to determine if the sector is still erased (blank).
The erase operation is started immediately after finding any programmed zero. If the sector is already blank (no programmed zero
bit found) the remainder of the erase operation is skipped. This can dramatically reduce erase time when sectors being erased do
not need the erase operation. When enabled the blank check feature is used within the parameter erase, Sector Erase, and Bulk
Erase commands. When blank check is disabled an Erase command unconditionally starts the Erase operation.
02h Volatile CR3V[4]: This bit controls the Page Programming Buffer address wrap point. Legacy SPI devices generally have used
a 256-byte Page Programming Buffer and defined that if data is loaded into the buffer beyond the 255-byte location, the address at
which additional bytes are loaded would be wrapped to address zero of the buffer. The S25FS-S family provides a 512-byte Page
Programming Buffer that can increase programming performance. For legacy software compatibility, this configuration bit provides
the option to continue the wrapping behavior at the 256-byte boundary or to enable full use of the available 512-byte buffer by not
wrapping the load address at the 256-byte boundary.
20h Volatile CR3V[3]: This bit controls the availability of 4-kB parameter sectors in the main flash array address map. The
parameter sectors can overlay the highest or lowest 32-kB address range of the device or they can be removed from the address
map so that all sectors are uniform size. This bit shall not be written to a value different than the value of CR3NV[3]. The value of
CR3V[3] may only be changed by writing CR3NV[3].
30h Volatile CR3V[2]: This bit controls how the 30h instruction code is used. The instruction may be used as a Clear Status
command or as an alternate Program / Erase Resume command. This allows software compatibility with either Cypress legacy SPI
devices or alternate vendor devices.
D8h Volatile CR3V[1]: This bit controls the area erased by the D8h or DCh instructions. The instruction can be used to erase 64-kB
physical sectors or 256-kB size and aligned blocks. The option to erase 256-kB blocks in the lower density family members allows
for consistent software behavior across all densities that can ease migration between different densities.
F0h Volatile CR3V[0]: This bit controls the availability of the Cypress legacy FL-S family software reset instruction. The S25FS-S
family supports the industry common 66h + 99h instruction sequence for software reset. This configuration bit allows the option to
continue use of the legacy F0h single command for software reset.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
7.6.6
Configuration Register 4
Configuration Register 4 controls the main Flash Array Read commands burst wrap behavior. The burst wrap configuration does not
affect commands reading from areas other than the main flash array e.g. read commands for registers or OTP array. The
non-volatile version of the register provides the ability to set the start up (boot) state of the controls as the contents are copied to the
volatile version of the register during the POR, hardware reset, or software reset. The volatile version of the register controls the
feature behavior during normal operation. The register bits can be read and changed using the Read Any Register and Write Any
Register commands. The volatile version of the register can also be written by the Set Burst Length (C0h) command.
7.6.6.1 Configuration Register 4 Non-Volatile (CR4NV)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 39. Configuration Register 4 Non-Volatile (CR4NV)
Bits
Field Name
Function
Type
7
6
Description
0
OI_O
Output Impedance
0
5
See Output Impedance Control.
0
4
WE_O
Wrap Enable
3
RFU
Reserved
2
RFU
Reserved
WL_O
Wrap Length
OTP
1
0
Default
State
1
0 = Wrap Enabled.
1 = Wrap Disabled.
0
Reserved for Future Use.
0
Reserved for Future Use.
0
00 = 8-byte wrap.
01 = 16-byte wrap.
10 = 32-byte wrap.
11 = 64-byte wrap.
0
Output Impedance Non-Volatile CR4NV[7:5]: These bits control the POR, hardware reset, or software reset state of the IO signal
output impedance (drive strength). Multiple drive strength are available to help match the output impedance with the system printed
circuit board environment to minimize overshoot and ringing. These non-volatile output impedance configuration bits enable the
device to start immediately (boot) with the appropriate drive strength.
Table 40. Output Impedance Control
CR4NV[7:5]
Impedance Selection
Typical Impedance to VSS
(Ohms)
Typical Impedance to VCC
(Ohms)
Notes
000
47
45
Factory Default
001
124
105
010
71
64
011
47
45
100
34
35
101
26
28
110
22
24
111
18
21
Wrap Enable Non-Volatile CR4NV[4]: This bit controls the POR, hardware reset, or software reset state of the Wrap Enable. The
commands affected by Wrap Enable are: Quad I/O Read, and DDR Quad I/O Read. This configuration bit enables the device to start
immediately (boot) in wrapped burst read mode rather than the legacy sequential read mode.
Wrap Length Non-Volatile CR4NV[1:0]: These bits controls the POR, hardware reset, or software reset state of the wrapped read
length and alignment. These non-volatile configuration bits enable the device to start immediately (boot) in wrapped burst read mode
rather than the legacy sequential read mode.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
7.6.6.2 Configuration Register 4 Volatile (CR4V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), Set Burst Length (SBL C0h).
Table 41. Configuration Register 4 Volatile (CR4V)
Bits
Field Name
Function
OI
Output Impedance
4
WE
Wrap Enable
3
RFU
Reserved
2
RFU
Reserved
Type
Default
State
Description
7
6
See Output Impedance Control (Table 40 on page 68) table.
5
0 = Wrap Enabled.
1 = Wrap Disabled.
Volatile
CR4NV
Reserved for Future Use.
1
0
WL
Reserved for Future Use.
00 = 8-byte wrap.
01 = 16-byte wrap.
10 = 32-byte wrap.
11 = 64-byte wrap.
Wrap Length
Output Impedance CR2V[7:5]: These bits control the IO signal output impedance (drive strength). This volatile output impedance
configuration bit enables the user to adjust the drive strength during normal operation.
Wrap Enable CR4V[4]: This bit controls the burst wrap feature. This volatile configuration bit enables the device to enter and exit
burst wrapped read mode during normal operation.
Wrap Length CR4V[1:0]: These bits controls the wrapped read length and alignment during normal operation. These volatile
configuration bits enable the user to adjust the burst wrapped read length during normal operation.
7.6.7
ECC Status Register (ECCSR)
Related Commands: ECC Read (ECCRD 18h or 19h). ECCSR does not have user programmable non-volatile bits, all defined bits
are volatile read only status. The default state of these bits are set by hardware.
The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read command is
written followed by an ECC unit address. The contents of the status register then indicates, for the selected ECC unit, whether there
is an error in the ECC, the ECC unit data, or that ECC is disabled for that ECC unit.
Table 42. ECC Status Register (ECCSR)
Bits
Field Name
Function
7 to 3
RFU
Reserved
2
EECC
Error in ECC
1
EECCD
0
ECCDI
Type
Default State
Description
0
Reserved for Future Use
Volatile, Read only
0
1 = Single Bit Error found in the ECC unit error
correction code
0 = No error.
Error in ECC unit
data
Volatile, Read only
0
1 = Single Bit Error corrected in ECC unit data.
0 = No error.
ECC Disabled
Volatile, Read only
0
1 = ECC is disabled in the selected ECC unit.
0 = ECC is enabled in the selected ECC unit.
ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC unit data.
ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures and ECC is enabled.
The ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to another.
These bits should be treated as “don’t care” and ignored by any software reading status.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
7.6.8
ASP Register (ASPR)
Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh), Read Any Register (RDAR 65h), Write Any Register
(WRAR 71h).
The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP)
features. ASPR does not have user programmable volatile bits, all defined bits are OTP.
The default state of the ASPR bits are programmed by Cypress.
Table 43. ASP Register (ASPR)
Bits
Field Name
Function
Type
Default
State
15 to 9
RFU
Reserved
OTP
1
8
RFU
Reserved
OTP
1
7
RFU
Reserved
OTP
1
Reserved for Future Use.
6
RFU
Reserved
OTP
1
Reserved for Future Use.
5
RFU
Reserved
OTP
1
Reserved for Future Use.
4
RFU
Reserved
RFU
1
Reserved for Future Use.
3
RFU
Reserved
RFU
1
Reserved for Future Use.
2
PWDMLB
Password
Protection Mode
Lock Bit
OTP
1
0 = Password Protection mode permanently enabled.
1 = Password Protection mode not permanently enabled.
1
PSTMLB
Persistent
Protection Mode
Lock Bit
OTP
1
0 = Persistent Protection mode permanently enabled.
1 = Persistent Protection mode not permanently enabled.
0
RFU
Reserved
RFU
1
Reserved for Future Use.
Description
Reserved for Future Use.
Reserved for Future Use.
Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password Protection mode is
permanently selected.
Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent Protection mode is
permanently selected.
PWDMLB (ASPR[2]) and PSTMLB (ASPR[1]) are mutually exclusive, only one may be programmed to 0.
ASPR bits may only be programmed while ASPR[2:1] = 11b. Attempting to program ASPR bits when ASPR[2:1] is not = 11b will
result in a programming error with P_ERR (SR1V[6]) set to 1. After the ASP protection mode is selected by programming
ASPR[2:1] = 10b or 01b, the state of all ASPR bits are locked and permanently protected from further programming. Attempting to
program ASPR[2:1] = 00b will result in a programming error with P_ERR (SR1V[6]) set to 1.
Similarly, OTP configuration bits listed in the ASP Register description (See ASP Register on page 78.), may only be programmed
while ASPR[2:1] = 11b. The OTP configuration must be selected before selecting the ASP protection mode. The OTP configuration
bits are permanently protected from further change when the ASP protection mode is selected. Attempting to program these OTP
configuration bits when ASPR[2:1] is not = 11b will result in a programming error with P_ERR (SR1V[6]) set to 1.
The ASP protection mode should be selected during system configuration to ensure that a malicious program does not select an
undesired protection mode at a later time. By locking all the protection configuration via the ASP mode selection, later alteration of
the protection methods by malicious programs is prevented.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
7.6.9
Password Register (PASS)
Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h), Read Any Register (RDAR 65h), Write
Any Register (WRAR 71h). The PASS register is a 64-bit OTP memory location used to permanently define a password for the
Advanced Sector Protection (ASP) feature. PASS does not have user programmable volatile bits, all defined bits are OTP. A volatile
copy of PASS is used to satisfy read latency requirements but the volatile register is not user writable or further described.
Table 44. Password Register (PASS)
Bits
Field
Name
Function
Type
63 to 0
PWD
Hidden
Password
OTP
Default State
Description
Non-Volatile OTP storage of 64-bit password. The password is no
FFFFFFFF-FFFFFFFF
longer readable after the password protection mode is selected by
h
programming ASP register bit 2 to 0.
7.6.10 PPB Lock Register (PPBL)
Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h), Read Any Register (RDAR 65h).
PPBL does not have separate user programmable non-volatile bits, all defined bits are volatile read only status. The default state of
the RFU bits is set by hardware. The default state of the PPBLOCK bit is defined by the ASP protection mode bits in ASPR[2:1].
There is no non-volatile version of the PPBL register.
The PPBLOCK bit is used to protect the PPB bits. When PPBL[0] = 0, the PPB bits can not be programmed.
Table 45. PPB Lock Register (PPBL)
Bits
Field Name
Function
Type
Default State
7 to 1
RFU
Reserved
Volatile
00h
0
PPBLOCK
Protect PPB Array
Volatile
Read Only
Description
Reserved for Future Use
ASPR[2:1] = 1xb = Persistent Protection 0 = PPB array protected.
Mode = 1
1 = PPB array may be programmed or erased.
ASPR[2:1] = 01b = Password Protection
Mode = 0
7.6.11 PPB Access Register (PPBAR)
Related Commands: PPB Read (PPBRD FCh or 4PPBRD E2h), PPB Program (PPBP FDh or 4PPBP E3h), PPB Erase (PPBE
E4h).
PPBAR does not have user writable volatile bits, all PPB array bits are non-volatile. The default state of the PPB array is erased to
FFh by Cypress. There is no volatile version of the PPBAR register.
Table 46. PPB Access Register (PPBAR)
Bits
7 to 0
Field Name
PPB
Function
Read or Program
per sector PPB
Document Number: 002-00368 Rev. *M
Type
Non-Volatile
Default State
Description
FFh
00h = PPB for the sector addressed by the PPBRD or PPBP
command is programmed to 0, protecting that sector from
program or erase operations.
FFh = PPB for the sector addressed by the PPBRD
command is 1, not protecting that sector from program or
erase operations.
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S25FS128S/S25FS256S
7.6.12 DYB Access Register (DYBAR)
Related Commands: DYB Read (DYBRD FAh or 4DYBRD E0h) and DYB Write (DYBWR FBh or 4DYBWR E1h).
DYBAR does not have user programmable non-volatile bits, all bits are a representation of the volatile bits in the DYB array. The
default state of the DYB array bits is set by hardware. There is no non-volatile version of the DYBAR register.
Table 47. DYB Access Register (DYBAR)
Bits
7 to 0
Field Name
DYB
Function
Read or Write
per sector DYB
Type
Default State
Volatile
FFh
Description
00h = DYB for the sector addressed by the DYBRD or DYBWR
command is cleared to 0, protecting that sector from program or erase
operations.
FFh = DYB for the sector addressed by the DYBRD or DYBWR
command is set to 1, not protecting that sector from program or erase
operations.
7.6.13 SPI DDR Data Learning Registers
Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read (DLPRD 41h), Read
Any Register (RDAR 65h), Write Any Register (WRAR 71h).
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data
Learning Register (VDLR). When shipped from Cypress, the NVDLR value is 00h. Once programmed, the NVDLR cannot be
reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR. The VDLR can be written to at
any time, but on reset or power cycles the data pattern will revert back to what is in the NVDLR. During the learning phase described
in the SPI DDR modes, the DLP will come from the VDLR. Each IO will output the same DLP value for every clock edge. For
example, if the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0; subsequently, the 2nd clock
edge all I/O’s will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands.
Table 48. Non-Volatile Data Learning Register (NVDLR)
Bits
7 to 0
Field Name
NVDLP
Function
Non-Volatile
Data Learning
Pattern
Type
Default State
OTP
00h
Description
OTP value that may be transferred to the host during DDR read
command latency (dummy) cycles to provide a training pattern to help
the host more accurately center the data capture point in the received
data bits.
Table 49. Volatile Data Learning Register (VDLR)
Bits
Field Name
Function
Type
7 to 0
VDLP
Volatile Data
Learning Pattern
Volatile
Document Number: 002-00368 Rev. *M
Default State
Description
Takes the value
Volatile copy of the NVDLP used to enable and deliver the Data Learning
of NVDLR
Pattern (DLP) to the outputs. The VDLP may be changed by the host
during POR or
during system operation.
Reset
Page 72 of 158
S25FS128S/S25FS256S
8.
Data Protection
8.1
Secure Silicon Region (OTP)
The device has a 1024 byte One-Time Program (OTP) address space that is separate from the main flash array. The OTP area is
divided into 32, individually lockable, 32-byte aligned and length regions.
The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with the system
CPU/ASIC to prevent device substitution. See OTP Address Space on page 54, OTP Program (OTPP 42h) on page 119, and OTP
Read (OTPR 4Bh) on page 119.
8.1.1
Reading OTP Memory Space
The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-kB OTP address range
will yield indeterminate data.
8.1.2
Programming OTP Memory Space
The protocol of the OTP programming command is the same as Page Program. The OTP Program command can be issued multiple
times to any given OTP address, but this address space can never be erased.
Automatic ECC is programmed on the first programming operation to each 16 byte region. Programming within a 16 byte region
more than once disables the ECC. It is recommended to program each 16 byte portion of each 32 byte region once so that ECC
remains enabled to provide the best data integrity.
The valid address range for OTP Program is depicted in Figure 46, OTP Address Space on page 55. OTP Program operations
outside the valid OTP address range will be ignored, without P_ERR in SR1V set to 1. OTP Program operations within the valid OTP
address range, while FREEZE = 1, will fail with P_ERR in SR1V set to 1. The OTP address space is not protected by the selection
of an ASP Protection mode. The Freeze bit (CR1V[0]) may be used to protect the OTP Address Space.
8.1.3
Cypress Programmed Random Number
Cypress standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit
random number using the Linear Congruential Random Number Method. The seed value for the algorithm is a random number
concatenated with the day and time of tester insertion.
8.1.4
Lock Bytes
The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the highest address region
related to the byte. The next higher address byte similarly protects the next higher 8 regions. The LSB bit of the lowest address Lock
Byte protects the higher address 16 bytes of the lowest address region. In other words, the LSB of location 0x10 protects all the Lock
Bytes and RFU bytes in the lowest address region from further programming. See OTP Address Space on page 54.
Document Number: 002-00368 Rev. *M
Page 73 of 158
S25FS128S/S25FS256S
8.2
Write Enable Command
The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data. The WREN command
sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes) during power-up, hardware reset, or after the
device completes the following commands:
Reset
Page Program (PP or 4PP)
Parameter 4-kB Erase (P4E or 4P4E)
Sector Erase (SE or 4SE)
Bulk Erase (BE)
Write Disable (WRDI)
Write Registers (WRR)
Write Any Register (WRAR)
OTP Byte Programming (OTPP)
Advanced Sector Protection Register Program (ASPP)
Persistent Protection Bit Program (PPBP)
Persistent Protection Bit Erase (PPBE)
Password Program (PASSP)
Program Non-Volatile Data Learning Register (PNVDLR)
8.3
Block Protection
The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register TBPROT_O bit can be
used to protect an address range of the main flash array from program and erase operations. The size of the range is determined by
the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT_O bit of the Configuration
Register (CR1NV[5]).
Table 50. Upper Array Start of Protection (TBPROT_O = 0)
Status Register Content
Protected Memory (KB)
BP2
BP1
BP0
Protected Fraction of
Memory Array
0
0
0
None
0
0
1
Upper 64th
256
512
0
1
0
Upper 32nd
512
1024
0
1
1
Upper 16th
1024
2048
1
0
0
Upper 8th
2048
4096
1
0
1
Upper 4th
4096
8192
1
1
0
Upper Half
8192
16384
1
1
1
All Sectors
16384
32768
Document Number: 002-00368 Rev. *M
FS128S
128 Mb
FS256S
256 Mb
0
0
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S25FS128S/S25FS256S
Table 51. Lower Array Start of Protection (TBPROT_O = 1)
Status Register Content
BP0
Protected Fraction of
Memory Array
Protected Memory (KB)
FS128S
128 Mb
FS256S
256 Mb
BP2
BP1
0
0
0
None
0
0
0
0
1
Lower 64th
256
512
0
1
0
Lower 32nd
512
1024
0
1
1
Lower 16th
1024
2048
1
0
0
Lower 8th
2048
4096
1
0
1
Lower 4th
4096
8192
1
1
0
Lower Half
8192
16384
1
1
1
All Sectors
16384
32768
When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still be used to protect
sectors not protected by the Block Protection scheme. In the case that both ASP and Block Protection are used on the same sector
the logical OR of ASP and Block Protection related to the sector is used.
8.3.1
Freeze Bit
Bit 0 of Configuration Register 1 (CR1V[0]) is the FREEZE bit. The Freeze bit, when set to 1, locks the current state of the Block
Protection control bits and OTP area until the next power off-on cycle. Additional details in Configuration Register 1 Volatile (CR1V)
on page 61.
8.3.2
Write Protect Signal
The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit (SR1NV[7]) provide hardware input
signal controlled protection. When WP# is Low and SRWD is set to 1 Status Register 1 (SR1NV and SR1V) and Configuration
Register 1 (CR1NV and CR1V) are protected from alteration. This prevents disabling or changing the protection defined by the Block
Protect bits. See Status Register 1 on page 57.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
8.4
Advanced Sector Protection
Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software methods used to disable or
enable programming or erase operations, individually, in any or all sectors.
Every main flash array sector has a non-volatile Persistent Protection Bit (PPB) and a volatile Dynamic Protection Bit (DYB)
associated with it. When either bit is 0, the sector is protected from program and erase operations. The PPB bits are protected from
program and erase when the volatile PPB Lock bit is 0. There are two methods for managing the state of the PPB Lock bit:
Password Protection and Persistent Protection. An overview of these methods is shown in Figure 48, Advanced Sector Protection
Overview on page 77.
Block Protection and ASP protection settings for each sector are logically ORed to define the protection for each sector i.e. if either
mechanism is protecting a sector the sector cannot be programmed or erased. Refer to Block Protection on page 74 for full details of
the BP2-0 bits.
Figure 47. Sector Protection Control
Dynamic
Protection
Bits Array
(DYB)
...
...
Sector N
Sector N
Document Number: 002-00368 Rev. *M
Sector 1
...
Sector 1
Block
Protection
Logic
Logical OR
Sector 1
Logical OR
Sector 0
Sector 0
...
Sector 0
Flash
Memory
Array
Logical OR
Persistent
Protection
Bits Array
(PPB)
Sector N
Page 76 of 158
S25FS128S/S25FS256S
Figure 48. Advanced Sector Protection Overview
Power On / Reset
ASPR[2]=0
ASPR[1]=0
No
No
Yes
Yes
Password Protection
ASPR Bits Locked
PPBLOCK = 0
PPB Bits Locked
Persistent Protection
Default
Persistent Protection
ASPR Bits Locked
ASPR Bits Are
Programmable
PPBLOCK = 1
PPB Bits Erasable
and Programmable
No
Password Unlock
Yes
PPBLOCK = 1
PPB Bits Erasable
and Programmable
No
PPB Lock Bit Write
Yes
PPBLOCK = 0
PPB Bits Locked
Default Mode allows
ASPR to be programmed
to permanently select
the Protection mode.
No
PPB Lock Bit Write
The default mode otherwise
acts the same as the
Persistent Protection Mode.
Yes
Password Protection
Mode protects the
PPB after power up.
A password unlock
command will enable
changes to PPB. A PPB
Lock Bit write command
turns protection back on.
Document Number: 002-00368 Rev. *M
Persistent Protection
Mode does not
protect the PPB after
power up. The bits may
be changed. A PPB
Lock Bit write command
protects the PPB bits
until the next power-off
or reset.
After one of the protection
modes is selected, ASPR
is no longer programmable,
making the selected protection
mode permanent.
Page 77 of 158
S25FS128S/S25FS256S
The Persistent Protection method sets the PPB Lock bit to 1 during POR, or hardware reset so that the PPB bits are unprotected by
a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB. There is no command in the Persistent
Protection method to set the PPB Lock bit to 1, therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.
The Persistent Protection method allows boot code the option of changing sector protection by programming or erasing the PPB,
then protecting the PPB from further change for the remainder of normal system operation by clearing the PPB Lock bit to 0. This is
sometimes called Boot-code controlled sector protection.
The Password method clears the PPB Lock bit to 0 during POR, or hardware reset to protect the PPB. A 64-bit password may be
permanently programmed and hidden for the password method. A command can be used to provide a password for comparison with
the hidden password. If the password matches, the PPB Lock bit is set to 1 to unprotect the PPB. A command can be used to clear
the PPB Lock bit to 0. This method requires use of a password to control PPB protection.
The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so as to permanently
select the method used.
8.4.1
ASP Register
The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features. See ASP Register
(ASPR) on page 70.
As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors unprotected, when power is
applied. The device programmer or host system must then choose which sector protection method to use. Programming either of
the, one-time programmable, Protection Mode Lock bits, locks the part permanently in the selected mode:
ASPR[2:1] = “11” = No ASP mode selected, Persistent Protection mode is the default.
ASPR[2:1] = “10” = Persistent Protection mode permanently selected.
ASPR[2:1] = “01” = Password Protection mode permanently selected.
ASPR[2:1] = “00” is an Illegal condition, attempting to program more than one bit to zero results in a programming failure.
ASP register programming rules:
If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock bits.
Once the Protection mode is selected, the following OTP Configuration Register bits are permanently protected from
programming and no further changes to the OTP register bits is allowed:
CR1NV[5:2]
CR2NV
❐ CR3NV
❐ CR4NV
❐ ASPR
❐ PASS
❐ NVDLR
❐ If an attempt to change any of the registers above, after the ASP mode is selected, the operation will fail and P_ERR (SR1V[6])
will be set to 1.
The programming time of the ASP register is the same as the typical page programming time. The system can determine the status
of the ASP register programming operation by reading the WIP bit in the Status Register. See Status Register 1 on page 57 for
information on WIP. See Sector Protection States Summary on page 79.
❐
❐
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S25FS128S/S25FS256S
8.4.2
Persistent Protection Bits
The Persistent Protection Bits (PPB) are located in a separate non-volatile flash array. One of the PPB bits is related to each sector.
When a PPB is 0, its related sector is protected from program and erase operations. The PPB are programmed individually but must
be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased
at the same time. The PPB have the same program and erase endurance as the main flash memory array. Preprogramming and
verification prior to erasure are handled by the device.
Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical Sector Erase time. During
PPB bit programming and PPB bit erasing, status is available by reading the Status Register. Reading of a PPB bit requires the
initial access time of the device.
Notes
42. Each PPB is individually programmed to 0 and all are erased to 1 in parallel.
43. If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails without programming or erasing the PPB.
44. The state of the PPB for a given sector can be verified by using the PPB Read command.
8.4.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYB only control the protection for
sectors that have their PPB set to 1. By issuing the DYB Write command, a DYB is cleared to 0 or set to 1, thus placing each sector
in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes,
yet does not prevent the easy removal of protection when changes are needed. The DYBs can be set or cleared as often as needed
as they are volatile bits.
8.4.4
PPB Lock Bit (PPBL[0])
The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs, when set to 1, it allows the PPBs to
be changed. See Section 7.6.10 PPB Lock Register (PPBL) on page 71 for more information.
The PLBWR command is used to clear the PPB Lock bit to 0. The PPB Lock Bit must be cleared to 0 only after all the PPBs are
configured to the desired settings.
In Persistent Protection mode, the PPB Lock is set to 1 during POR or a hardware reset. When cleared to 0, no software command
sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can set the PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or a hardware reset. The PPB Lock bit can only be
set to 1 by the Password Unlock command.
8.4.5
Sector Protection States Summary
Each sector can be in one of the following protection states:
Unlocked — The sector is unprotected and protection can be changed by a simple command. The protection state defaults to
unprotected when the device is shipped from Cypress.
Dynamically Locked — A sector is protected and protection can be changed by a simple command. The protection state is not
saved across a power cycle or reset.
Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock bit is set to 1. The protection
state is non-volatile and saved across a power cycle or reset. Changing the protection state requires programming and or erase of
the PPB bits.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
Table 52. Sector Protection States
Protection Bit Values
Sector State
PPB Lock
PPB
DYB
1
1
1
Unprotected – PPB and DYB are changeable.
1
1
0
Protected – PPB and DYB are changeable.
1
0
1
Protected – PPB and DYB are changeable.
8.4.6
1
0
0
Protected – PPB and DYB are changeable.
0
1
1
Unprotected – PPB not changeable, DYB is changeable.
0
1
0
Protected – PPB not changeable, DYB is changeable.
0
0
1
Protected – PPB not changeable, DYB is changeable.
0
0
0
Protected – PPB not changeable, DYB is changeable.
Persistent Protection Mode
The Persistent Protection method sets the PPB Lock bit to 1 during POR or hardware reset so that the PPB bits are unprotected by
a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR command can clear the PPB Lock bit to 0 to
protect the PPB. There is no command to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or
hardware reset.
8.4.7
Password Protection Mode
Password Protection mode allows an even higher level of security than the Persistent Sector Protection mode, by requiring a 64-bit
password for unlocking the PPB Lock bit. In addition to this password requirement, after power-up and hardware reset, the PPB
Lock bit is cleared to 0 to ensure protection at power-up. Successful execution of the Password Unlock command by entering the
entire password sets the PPB Lock bit to 1, allowing for sector PPB modifications.
Password Protection Notes:
Once the Password is programmed and verified, the Password mode (ASPR[2]=0) must be set in order to prevent reading the
password.
The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results
in the cell left as a 0 with no programming error set.
The password is all 1s when shipped from Cypress. It is located in its own memory space and is accessible through the use of the
Password Program, Password Read, RDAR, and WRAR commands.
All 64-bit password combinations are valid as a password.
The Password mode, once programmed, prevents reading the 64-bit password and further password programming. All further
program and read commands to the password region are disabled and these commands are ignored or return undefined data. There
is no means to verify what the password is after the Password Mode Lock bit is selected. Password verification is only allowed
before selecting the Password Protection mode.
The Protection Mode Lock bits are not erasable.
The exact password must be entered in order for the unlocking function to occur. If the password unlock command provided
password does not match the hidden internal password, the unlock operation fails in the same manner as a programming operation
on a protected sector. The P_ERR bit is set to 1, the WIP bit remains set, and the PPB Lock bit remains cleared to 0.
The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an
unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a
password. The Read Status Register 1 command may be used to read the WIP bit to determine when the device has completed the
password unlock command or is ready to accept a new password command. When a valid password is provided the password
unlock command does not insert the 100 µs delay before returning the WIP bit to 0.
If the password is lost after selecting the Password mode, there is no way to set the PPB Lock bit.
ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced to the boot sector
address. ECC status is only in that sector while read protection mode is active.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
8.5
Recommended Protection Process
During system manufacture, the flash device configuration should be defined by:
1. Programming the OTP configuration bits in CR1NV[5, 3:2], CR2NV, CR3NV, and CR4NV as desired.
2. Program the Secure Silicon Region (OTP area) as desired.
3. Program the PPB bits as desired via the PPBP command.
4. Program the Non-Volatile Data Learning Pattern (NVDLR) if it will be used in DDR read commands.
5. Program the Password register (PASS) if password protection will be used.
6. Program the ASP Register as desired, including the selection of the persistent or password ASP protection mode in
ASPR[2:1]. It is very important to explicitly select a protection mode so that later accidental or malicious programming of
the ASP register and OTP configuration is prevented. This is to ensure that only the intended OTP protection and
configuration features are enabled.
During system power-up and boot code execution:
1. Trusted boot code can determine whether there is any need to program additional SSR (OTP area) information. If no SSR
changes are needed the FREEZE bit (CR1V[0]) can be set to 1 to protect the SSR from changes during the remainder of
normal system operation while power remains on.
2. If the Persistent Protection mode is in use, trusted boot code can determine whether there is any need to modify the
persistent (PPB) sector protection via the PPBP or PPBE commands. If no PPB changes are needed the PPBLOCK bit
can be cleared to 0 via the PPBL to protect the PPB bits from changes during the remainder of normal system operation
while power remains on.
3. The Dynamic (DYB) Sector Protection bits can be written as desired via the DYBAR.
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S25FS128S/S25FS256S
9.
Commands
All communication between the host system and S25FS-S family memory devices is in the form of units called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands
may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All
instruction, address, and data information is transferred sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three
command phases:
instruction;
address and instruction modifier (mode);
data.
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI signal. Data may be
sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol for single bit width instruction, single
bit width address and modifier, single bit data.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)
groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0,
IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command protocols.
The S25FS-S family also supports a QPI Mode in which all information is transferred in 4-bit width, including the instruction, address,
modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
Each command begins with an eight bit (byte) instruction. However, some read commands are modified by a prior read
command, such that the instruction is implied from the earlier command. This is called Continuous Read mode. When the device is
in Continuous Read mode, the instruction bits are not transmitted at the beginning of the command because the instruction is the
same as the read command that initiated the Continuous Read mode. In Continuous Read mode the command will begin with the
read address. Thus, Continuous Read mode removes eight instruction bits from each read command in a series of same type read
commands.
The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces
in the device. The address may be either a 24-bit or 32-bit, byte boundary, address.
The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data information to be done
one, two, or four bits in parallel. This enables a trade off between the number of signal connections (IO bus width) and the speed of
information transfer. If the host system can support a two or four bit wide IO bus the memory performance can be increased by using
the instructions that provide parallel 2-bit (dual) or parallel 4-bit (quad) transfers.
In legacy SPI Multiple IO mode, the width of all transfers following the instruction are determined by the instruction sent. Following
transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per
(dual) transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per (quad) transfer on the IO0-IO3 signals. Within the
dual or quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher numbered
IO signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
In QPI Mode, the width of all transfers, including instructions, is a 4-bit wide (quad) transfer on the IO0-IO3 signals.
Dual I/O and Quad I/O read instructions send an instruction modifier called mode bits, following the address, to indicate that the
next command will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide
an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same
command type is repeated in a sequence of commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before
read data is returned to the host.
Read latency may be zero to several SCK cycles (also referred to as dummy cycles).
All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted into the device with
the most significant byte first. All data is transferred with the lowest address byte sent first. Following bytes of data are sent in lowest
to highest byte address order i.e. the byte address increments.
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S25FS128S/S25FS256S
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The
embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded
operation. These are discussed in the individual command descriptions. While a program, erase, or write operation is in progress, it
is recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the device, to ensure the new
command can be accepted.
Depending on the command, the time for execution varies. A command to read status information from an executing command is
available to determine when the command completes execution and whether the command was successful.
Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host
system and the memory device generally handle the details of signal relationships and timing. For this reason, signal relationships
and timing are not covered in detail within this software interface focused section of the document. Instead, the focus is on the logical
sequence of bits transferred in each command rather than the signal timing and relationships. Following are some general signal
relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of
commands, see Command Protocol on page 16.
The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide transfers. The
memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive the IO0-IO3 signals during
Dual and Quad transfers.
❐ All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept low
throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for eight bit transfer
multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned high not at an 8-bit
boundary.
❐
9.1
Command Set Summary
9.1.1
Extended Addressing
To accommodate addressing above 128 Mb, there are two options:
1. Instructions that always require a 4-byte address, used to access up to 32 Gb of memory.
Command Name
Function
Instruction (Hex)
4READ
Read
13
4FAST_READ
Read Fast
0C
4DIOR
Dual I/O Read
BC
4QIOR
Quad I/O Read
EC
4DDRQIOR
DDR Quad I/O Read
EE
4PP
Page Program
12
4P4E
Parameter 4-kB Erase
21
4SE
Erase 64/256 kB
DC
4ECCRD
ECC Status Read
18
4DYBRD
DYB Read
E0
4DYBWR
DYBWR
E1
4PPBRD
PPB Read
E2
4PPBP
PPB Program
E3
2. A 4-byte address mode for backward compatibility to the 3-byte address instructions. The standard 3-byte instructions
can be used in conjunction with a 4-byte address mode controlled by the Address Length configuration bit (CR2V[7]). The
default value of CR2V[7] is loaded from CR2NV[7] (following power-up, hardware reset, or software reset), to enable
default 3-byte (24-bit) or 4-byte (32-bit) addressing. When the address length (CR2V[7]) set to 1, the legacy commands
are changed to require 4-bytes (32-bits) for the address field. The following instructions can be used in conjunction with
the 4-byte address mode configuration to switch from 3 bytes to 4 bytes of address field.
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S25FS128S/S25FS256S
Command Name
Function
Instruction (Hex)
READ
Read
03
FAST_READ
Read Fast
0B
DIOR
Dual I/O Read
BB
QIOR
Quad I/O Read
EB
DDRQIOR
DDR Quad I/O Read)
ED
PP
Page Program
02
P4E
Parameter 4-kB Erase
20
SE
Erase 64 / 256 kB
D8
RDAR
Read Any Register
65
WRAR
Write Any Register
71
EES
Evaluate Erase Status
D0
OTPP
OTP Program
42
OTPR
OTP Read
4B
ECCRD
ECC Status Read
19
DYBRD
DYB Read
FA
DYBWR
DYBWR
FB
PPBRD
PPB Read
FC
PPBP
PPB Program
FD
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S25FS128S/S25FS256S
9.1.2
Command Summary by Function
Table 53. S25FS-S Family Command Set (sorted by function)
Function
Command Name
RDID
Read
Device ID
Register
Access
Address
Length
(Bytes)
QPI
9F
133
0
Yes
Read JEDEC Serial Flash Discoverable Parameters
5A
50
3
Yes
Read Quad ID
AF
133
0
Yes
RDSR1
Read Status Register 1
05
133
0
Yes
RDSR2
Read Status Register 2
07
133
0
No
RDCR
Read Configuration Register 1
35
133
0
No
RDAR
Read Any Register
65
133
3 or 4
Yes
WRR
Write Register (Status 1, Configuration 1)
01
133
0
Yes
WRDI
Write Disable
04
133
0
Yes
WREN
Write Enable
06
133
0
Yes
WRAR
Write Any Register
71
133
3 or 4
Yes
CLSR
Clear Status Register 1 - Erase/Prog. Fail Reset
This command may be disabled and the instruction value
instead used for a program / erase resume command - see
Configuration Register 3 on page 66
30
133
0
Yes
CLSR
Clear Status Register 1 (alternate instruction) Erase/Prog. Fail Reset
82
133
0
Yes
Enter 4-byte Address Mode
B7
133
0
No
SBL
Set Burst Length
C0
133
0
No
EES
Evaluate Erase Status
D0
133
3 or 4
Yes
ECC Read
19
133
3 or 4
Yes
4ECCRD
Program
Flash Array
Maximum
Frequency
(MHz)
RDQID
ECCRD
Read Flash
Array
Read ID (JEDEC Manufacturer ID and JEDEC CFI)
Instruction
Value (Hex)
RSFDP
4BAM
Register
Access
Command Description
DLPRD
ECC Read
18
133
4
Yes
Data Learning Pattern Read
41
133
0
No
PNVDLR
Program NV Data Learning Register
43
133
0
No
WVDLR
Write Volatile Data Learning Register
4A
133
0
No
READ
Read
03
50
3 or 4
No
4READ
Read
13
50
4
No
FAST_READ
Fast Read
0B
133
3 or 4
No
4FAST_READ
Fast Read
0C
133
4
No
DIOR
Dual I/O Read
BB
66
3 or 4
No
4DIOR
Dual I/O Read
BC
66
4
No
QIOR
Quad I/O Read
EB
133
3 or 4
Yes
4QIOR
Quad I/O Read
EC
133
4
Yes
DDRQIOR
DDR Quad I/O Read
ED
80
3 or 4
Yes
4DDRQIOR
DDR Quad I/O Read
EE
80
4
Yes
PP
Page Program
02
133
3 or 4
Yes
4PP
Page Program
12
133
4
Yes
Note
45. Commands not supported in QPI Mode have undefined behavior if sent when the device is in QPI Mode.
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S25FS128S/S25FS256S
Table 53. S25FS-S Family Command Set (sorted by function) (Continued)
Function
Command Name
P4E
4P4E
Erase
Flash Array
Erase
/Program
Suspend
/Resume
One-Time
Program
Array
DPD
Maximum
Frequency
(MHz)
Address
Length
(Bytes)
QPI
20
133
3 or 4
Yes
Parameter 4-kB Sector Erase
21
133
4
Yes
D8
133
3 or 4
Yes
4SE
Erase 64 kB or 256 kB
DC
133
4
Yes
BE
Bulk Erase
60
133
0
Yes
BE
Bulk Erase (alternate instruction)
C7
133
0
Yes
EPS
Erase / Program Suspend
75
133
0
Yes
EPS
Erase / Program Suspend (alternate instruction)
85
133
0
Yes
EPS
Erase / Program Suspend (alternate instruction)
B0
133
0
Yes
EPR
Erase / Program Resume
7A
133
0
Yes
EPR
Erase / Program Resume (alternate instruction)
8A
133
0
Yes
EPR
Erase / Program Resume (alternate instruction)
This command may be disabled and the instruction value
instead used for a clear status command - see Section 7.6.5
Configuration Register 3 on page 66
30
133
0
Yes
OTPP
OTP Program
42
133
3 or 4
No
OTPR
OTP Read
4B
133
3 or 4
No
DYBRD
DYB Read
FA
133
3 or 4
Yes
4DYBRD
DYB Read
E0
133
4
Yes
DYBWR
DYB Write
FB
133
3 or 4
Yes
4DYBWR
DYB Write
E1
133
4
Yes
PPBRD
PPB Read
FC
133
3 or 4
No
PPB Read
E2
133
4
No
PPBP
PPB Program
FD
133
3 or 4
No
4PPBP
PPB Program
E3
133
4
No
PPBE
PPB Erase
E4
133
0
No
ASPRD
ASP Read
2B
133
0
No
ASP Program
2F
133
0
No
ASPP
Reset
Parameter 4-kB Sector Erase
Instruction
Value (Hex)
Erase 64 kB or 256 kB
SE
4PPBRD
Advanced
Sector
Protection
Command Description
PLBRD
PPB Lock Bit Read
A7
133
0
No
PLBWR
PPB Lock Bit Write
A6
133
0
No
PASSRD
Password Read
E7
133
0
No
PASSP
Password Program
E8
133
0
No
PASSU
Password Unlock
E9
133
0
No
RSTEN
Software Reset Enable
66
133
0
Yes
RST
Software Reset
99
133
0
Yes
Legacy Software Reset
F0
133
0
No
MBR
Mode Bit Reset
FF
133
0
Yes
DPD
Enter Deep Power-Down Mode
B9
133
0
Yes
RES
Release from Deep Power-Down Mode
AB
133
0
Yes
RESET
Note
45. Commands not supported in QPI Mode have undefined behavior if sent when the device is in QPI Mode.
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S25FS128S/S25FS256S
9.1.3
Read Device Identification
There are multiple commands to read information about the device manufacturer, device type, and device features. SPI memories
from different vendors have used different commands and formats for reading information about the memories. The S25FS-S family
supports the three device information commands.
9.1.4
Register Read or Write
There are multiple registers for reporting embedded operation status or controlling device configuration options. There are
commands for reading or writing these registers. Registers contain both volatile and non-volatile bits. Non-Volatile bits in registers
are automatically erased and programmed as a single (write) operation.
9.1.4.1 Monitoring Operation Status
The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the
Write-In-Progress (WIP) bit in the Status Register. The Read from Status Register 1 command or Read Any Register command
provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the Status Register indicate whether
the most recent program or erase command has not completed successfully. When P_ERR or E_ERR bits are set to 1, the WIP bit
will remain set to one indicating the device remains busy and unable to receive most new operation commands. Only Status Read
(RDSR1 05h), Read Any Register (RDAR 65h), Status Clear (CLSR 30h or 82h), and Software Reset (RSTEN 66h, RST 99h or
RESET F0h) are valid commands when P_ERR or E_ERR is set to 1. A Clear Status Register (CLSR) followed by a Write Disable
(WRDI) command must be sent to return the device to standby state. Clear Status Register clears the WIP, P_ERR, and E_ERR
bits. WRDI clears the WEL bit. Alternatively, hardware reset, or software reset (RST or RESET) may be used to return the device to
standby state.
9.1.4.2 Configuration
There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length,
and some aspects of data protection.
9.1.5
Read Flash Array
Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incrementally higher byte
addresses until the host ends the data transfer by driving CS# input High. If the byte address reaches the maximum address of the
memory array, the read will continue at address zero of the array.
There are several different read commands to specify different access latency and data path widths. Double Data Rate (DDR)
commands also define the address and data bit relationship to both SCK edges:
The Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit per
SCK falling edge on the SO signal. This command has zero latency between the address and the returning data but is limited to a
maximum SCK rate of 50MHz.
Other read commands have a latency period between the address and returning data but can operate at higher SCK frequencies.
The latency depends on a Configuration Register read latency value.
The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit
per SCK falling edge on the SO signal.
Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data returning two bits, or
four bits of data per SCK falling edge on the IO0-IO3 signals.
Quad Double Data Rate read commands provide address four bits per every SCK edge with read data returning four bits of data
per every SCK edge on the IO0-IO3 signals.
Document Number: 002-00368 Rev. *M
Page 87 of 158
S25FS128S/S25FS256S
9.1.6
Program Flash Array
Programming data requires two commands: Write Enable (WREN), and Page Program (PP). The Page Program command accepts
from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed in one operation. Programming means that bits can
either be left at 1, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation.
9.1.7
Erase Flash Array
The Parameter Sector Erase, Sector Erase, or Bulk Erase commands set all the bits in a sector or the entire memory array to 1. A bit
needs to be first erased to 1 before programming can change it to a 0. While bits can be individually programmed from a 1 to 0,
erasing bits from 0 to 1 must be done on a sector-wide or array-wide (bulk) level. The Write Enable (WREN) command must precede
an erase command.
9.1.8
OTP, Block Protection, and Advanced Sector Protection
There are commands to read and program a separate One-Time Programmable (OTP) array for permanent data such as a serial
number. There are commands to control a contiguous group (block) of flash memory array sectors that are protected from program
and erase operations. There are commands to control which individual flash memory array sectors are protected from program and
erase operations.
9.1.9
Reset
There are commands to reset to the default conditions present after power-on to the device. However, the software reset commands
do not affect the current state of the FREEZE or PPB Lock bits. In all other respects a software reset is the same as a hardware
reset.
There is a command to reset (exit from) the Continuous Read mode.
9.1.10 DPD
A Deep Power-Down (DPD) mode is supported by the FS-S family of devices. If the device has been placed in DPD mode by the
DPD (B9h) command, the interface standby current is IDPD. The DPD command is accepted only while the device is not performing
an embedded operation as indicated by the Status Register-1 volatile Write In Progress (WIP) bit being cleared to zero
(SR1V[0] = 0). While in DPD mode, the device ignores all commands except the Release from DPD (RES ABh) command, that will
return the device to the Interface Standby state after a delay of tRES.
9.1.11 Reserved
Some instructions are reserved for future use. In this generation of the S25FS-S family some of these command instructions may be
unused and not affect device operation, some may have undefined results.
Some commands are reserved to ensure that a legacy or alternate source device command is allowed without effect. This allows
legacy software to issue some commands that are not relevant for the current generation S25FS-S family with the assurance these
commands do not cause some unexpected action.
Some commands are reserved for use in special versions of the FS-S not addressed by this document or for a future generation.
This allows new host memory controller designs to plan the flexibility to issue these command instructions. The command format is
defined if known at the time this document revision is published.
Document Number: 002-00368 Rev. *M
Page 88 of 158
S25FS128S/S25FS256S
9.2
Identification Commands
9.2.1
Read Identification (RDID 9Fh)
The Read Identification (RDID) command provides read access to manufacturer identification, device identification, and Common
Flash Interface (CFI) information. The manufacturer identification is assigned by JEDEC. The CFI structure is defined by JEDEC
standard. The device identification and CFI values are assigned by Cypress.
The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows a vendor-specified
software flash management program (driver) to be used for entire families of flash devices. Software support can then be
device-independent, JEDEC manufacturer ID independent, forward and backward-compatible for the specified flash device families.
System vendors can standardize their flash drivers for long-term software compatibility by using the CFI values to configure a family
driver from the CFI information of the device in use.
Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the
program, erase, or write cycle that is in progress.
The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte of manufacturer
identification, two bytes of device identification, extended device identification, and CFI information will be shifted sequentially out on
SO. As a whole this information is referred to as ID-CFI. See Device ID and Common Flash Interface (ID-CFI) Address Map
on page 135 for the detail description of the ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The RDID command
sequence is terminated by driving CS# to the logic high state anytime during data output.
The maximum clock frequency for the RDID command is 133 MHz.
Figure 49. Read Identification (RDID) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
Phase
6
5
4
Instruction
3
2
1
0
7
6
5
Data 1
4
3
2
1
0
Data N
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
Figure 50. Read Identification (RDID) QPI Mode Command
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
Phase
Instruction
Document Number: 002-00368 Rev. *M
D1
D2
D3
D4
3
D5
Page 89 of 158
S25FS128S/S25FS256S
9.2.2
Read Quad Identification (RDQID AFh)
The Read Quad Identification (RDQID) command provides read access to manufacturer identification, device identification, and
Common Flash Interface (CFI) information. This command is an alternate way of reading the same information provided by the
RDID command while in QPI Mode. In all other respects the command behaves the same as the RDID command.
The command is recognized only when the device is in QPI Mode (CR2V[6]=1). The instruction is shifted in on IO0-IO3. After the last
bit of the instruction is shifted into the device, a byte of manufacturer identification, two bytes of device identification, extended
device identification, and CFI information will be shifted sequentially out on IO0-IO3. As a whole this information is referred to as
ID-CFI. See Section 11.4 Device ID and Common Flash Interface (ID-CFI) Address Map on page 135 for the detail description of the
ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The command
sequence is terminated by driving CS# to the logic high state anytime during data output.
The maximum clock frequency for the command is 133 MHz.
Figure 51. Read Quad Identification (RDQID) Command Sequence
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
9.2.3
Instruction
D1
D2
D3
D4
D5
Read Serial Flash Discoverable Parameters (RSFDP 5Ah)
The command is initiated by shifting on SI the instruction code “5Ah”, followed by a 24-bit address of 000000h, followed by 8 dummy
cycles. The SFDP bytes are then shifted out on SO starting at the falling edge of SCK after the dummy cycles. The SFDP bytes are
always shifted out with the MSB first. If the 24-bit address is set to any other value, the selected location in the SFDP space is the
starting point of the data read. This enables random access to any parameter in the SFDP space. The RSFDP command is
supported up to 50 MHz.
Figure 52. RSFDP Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0 23
1
0
SO
7
Phase
Instruction
Address
6
5
4
Dummy Cycles
3
2
1
0
Data 1
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3 and the returning data is shifted
out on IO0–IO3.
Figure 53. RSFDP QPI Mode Command Sequence
CS#
SCK
IO0
4
0
20
4
0
4
0
4
0
4
0
4
0
IO1
5
1
21
5
1
5
1
5
1
5
1
5
1
IO2
6
2
22
6
2
6
2
6
2
6
2
6
2
IO3
7
3
23
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Document Number: 002-00368 Rev. *M
Address
Dummy
D1
D2
D3
D4
Page 90 of 158
S25FS128S/S25FS256S
9.3
Register Access Commands
9.3.1
Read Status Register 1 (RDSR1 05h)
The Read Status Register 1 (RDSR1) command allows the Status Register 1 contents to be read from SO. The volatile version of
Status Register 1 (SR1V) contents may be read at any time, even while a program, erase, or write operation is in progress. It is
possible to read Status Register 1 continuously by providing multiples of eight clock cycles. The status is updated for each eight
cycle read. The maximum clock frequency for the RDSR1 (05h) command is 133 MHz.
Figure 54. Read Status Register 1 (RDSR1) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
Phase
6
5
4
Instruction
3
2
1
0
7
6
Status
5
4
3
2
1
0
Updated Status
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3, two clock cycles per byte.
Figure 55. Read Status Register 1 (RDSR1) QPI Mode Command
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
9.3.2
Instruct.
D1
D2
D3
D4
D5
Read Status Register 2 (RDSR2 07h)
The Read Status Register 2 (RDSR2) command allows the Status Register 2 contents to be read from SO. The Status Register 2
contents may be read at any time, even while a program, erase, or write operation is in progress. It is possible to read the Status
Register 2 continuously by providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum
clock frequency for the RDSR2 command is 133 MHz.
Figure 56. Read Status Register 2 (RDSR2) Command
CS#
SCK
SI
7
6
5
4
3
SO
Phase
2
1
0
7
Instruction
6
5
4
3
Status
2
1
0
7
6
5
4
3
2
1
0
Updated Status
In QPI Mode, Status Register 2 may be read via the Read Any Register command, see Section 9.3.13 Read Any Register (RDAR
65h) on page 99.
Document Number: 002-00368 Rev. *M
Page 91 of 158
S25FS128S/S25FS256S
9.3.3
Read Configuration Register (RDCR 35h)
The Read Configuration Register (RDCR) command allows the volatile Configuration Register (CR1V) contents to be read from SO.
It is possible to read CR1V continuously by providing multiples of eight clock cycles. The Configuration Register contents may be
read at any time, even while a program, erase, or write operation is in progress.
Figure 57. Read Configuration Register (RDCR) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
Phase
6
Instruction
5
4
3
2
1
0
7
6
Register Read
5
4
3
2
1
0
Repeat Register Read
In QPI Mode, Configuration Register 1 may be read via the Read Any Register command, see Section 9.3.13 Read Any Register
(RDAR 65h) on page 99
9.3.4
Write Registers (WRR 01h)
The Write Registers (WRR) command allows new values to be written to both the Status Register 1 and Configuration Register 1.
Before the Write Registers (WRR) command can be accepted by the device, a Write Enable (WREN) command must be received.
After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) in the
Status Register to enable any write operations.
The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The Status Register is one data
byte in length.
The WRR operation first erases the register then programs the new value as a single operation. The Write Registers (WRR)
command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation. See Section 7.6.1.2 Status Register 1 Volatile
(SR1V) on page 58 for a description of the error bits. Any Status or Configuration Register bit reserved for the future must be written
as a 0.
CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the Write Registers (WRR)
command is not executed. If CS# is driven high after the eighth cycle then only the Status Register 1 is written; otherwise, after the
sixteenth cycle both the Status and Configuration Registers are written.
As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated. While the Write
Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit.
The Write-In Progress (WIP) bit is a 1 during the self-timed Write Registers (WRR) operation, and is a 0 when it is completed. When
the Write Registers (WRR) operation is completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the
WRR command is 133 MHz.
This command is also supported in QPI Mode. In QPI Mode the instruction and data is shifted in on IO0–IO3, two clock cycles per
byte.
Figure 58. Write Registers (WRR) Command Sequence – 8-Data Bits
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00368 Rev. *M
Instruction
Input Status Register 1
Page 92 of 158
S25FS128S/S25FS256S
Figure 59. Write Registers (WRR) Command Sequence – 16-Data Bits
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Status Register 1
Input Configuration Register 1
Figure 60. Write Registers (WRR) Command Sequence – 16-Data Bits QPI Mode
CS#
SCK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
Phase
Instruct.
Input Status
3
Input Config
The Write Register (WRR) command writes the non-volatile version of the Quad bit (CR1NV[1]), which also causes an update to the
volatile version CR1V[1]. The WRR command can not write the volatile version CR1V[1] without first affecting the non-volatile
version CR1NV[1]. The WRAR command must be used when it is desired to write the volatile Quad bit CR1V[1] without affecting the
non-volatile version CR1NV[1].
The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and BP0) bits in either
the non-volatile Status Register 1 or in the volatile Status Register 1, to define the size of the area that is to be treated as read-only.
The BPNV_O bit (CR1NV[3]) controls whether WRR writes the non-volatile or volatile version of Status Register 1. When
CR1NV[3] = 0 WRR writes SR1NV[4:2]. When CR1NV[3] = 1 WRR writes SR1V[4:2].
The Write Registers (WRR) command also allows the user to set the Status Register Write Disable (SRWD) bit to a 1 or a 0. The
Status Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow the BP bits to be hardware protected.
When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is possible to write to the
Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) command,
regardless of the whether Write Protect (WP#) signal is driven to the logic high or logic low state.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be considered, depending
on the state of Write Protect (WP#):
If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and Configuration Registers
provided that the Write Enable Latch (WEL) bit has previously been set to a 1 by initiating a Write Enable (WREN) command.
If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and Configuration Registers
even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write Enable (WREN) command. Attempts to write to
the Status and Configuration Registers are rejected, not accepted for execution, and no error indication is provided. As a
consequence, all the data bytes in the memory area that are protected by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected by WP#.
The WP# hardware protection can be provided:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic low state;
or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable (SRWD) bit to a 1.
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high state. If WP# is
permanently tied high, hardware protection of the BP bits can never be activated.
Document Number: 002-00368 Rev. *M
Page 93 of 158
S25FS128S/S25FS256S
Table 54. Block Protection Modes
WP#
SRWD Bit
1
1
1
0
0
0
0
1
Memory Content
Mode
Write Protection of Registers
Software
Protected
Status and Configuration Registers are Writable (if
WREN command has set the WEL bit). The values in
the SRWD, BP2, BP1, and BP0 bits and those in the
Configuration Register can be changed.
Hardware
Protected
Status and Configuration Registers are Hardware
Protected against Page Ready to accept Page
Write Protected. The values in the SRWD, BP2, BP1,
Program, Sector
Program or Erase
and BP0 bits and those in the Configuration Register
Erase, and Bulk Erase. commands.
cannot be changed.
Protected Area
Unprotected Area
Protected against Page Ready to accept Page
Program, Sector
Program, and Sector
Erase, and Bulk Erase. Erase commands.
Notes
46. The Status Register originally shows 00h when the device is first shipped from Cypress to the customer.
47. Hardware protection is disabled when Quad Mode is enabled (CR1V[1] = 1). WP# becomes IO2; therefore, it cannot be utilized.
9.3.5
Write Enable (WREN 06h)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1V[1]) to a 0. The Write
Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN) command to enable write, program and erase
commands.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being
driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write enable operation will not
be executed.
Figure 61. Write Enable (WREN) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 62. Write Enable (WREN) Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00368 Rev. *M
3
Instruction
Page 94 of 158
S25FS128S/S25FS256S
9.3.6
Write Disable (WRDI 04h)
The Write Disable (WRDI) command clears the Write Enable Latch (WEL) bit of the Status Register 1 (SR1V[1]) to a 1.
The Write Enable Latch (WEL) bit may be cleared to a 0 by issuing the Write Disable (WRDI) command to disable Page Program
(PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR or WRAR), OTP Program (OTPP), and other commands, that
require WEL be set to 1 for execution. The WRDI command can be used by the user to protect memory areas against inadvertent
writes that can possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while
WIP bit =1.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being
driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write disable operation will not
be executed.
Figure 63. Write Disable (WRDI) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 64. Write Disable (WRDI) Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00368 Rev. *M
3
Instruction
Page 95 of 158
S25FS128S/S25FS256S
9.3.7
Clear Status Register (CLSR 30h or 82h)
The Clear Status Register command resets bit SR1V[5] (Erase Fail Flag) and bit SR1V[6] (Program Fail Flag). It is not necessary to
set the WEL bit before a Clear Status Register command is executed. The Clear Status Register command will be accepted even
when the device remains busy with WIP set to 1, as the device does remain busy when either error bit is set. The WEL bit will be
unchanged after this command is executed.
The legacy Clear Status Register (CLSR 30h) instruction may be disabled and the 30h instruction value instead used for a program
/ erase resume command - see Configuration Register 3 on page 66. The Clear Status Register alternate instruction (CLSR 82h) is
always available to clear the Status Register.
Figure 65. Clear Status Register (CLSR) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 66. Clear Status Register (CLSR) Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00368 Rev. *M
3
Instruction
Page 96 of 158
S25FS128S/S25FS256S
9.3.8
ECC Status Register Read (ECCRD 19h or 4EECRD 18h)
To read the ECC Status Register, the command is followed by the ECC unit address, the four least significant bits (LSB) of address
must be set to zero. This is followed by the number of dummy cycles selected by the read latency value in CR2V[3:0]. Then the 8-bit
contents of the ECC Register, for the ECC unit selected, are shifted out on SO 16 times, once for each byte in the ECC Unit. If CS#
remains low the next ECC unit status is sent through SO 16 times, once for each byte in the ECC Unit. The maximum operating
clock frequency for the ECC READ command is 133 MHz.
Figure 67. ECC Status Register Read Command Sequence[48, 49]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
7
Phase
Instruction
Address
6
5
4
Dummy Cycles
3
2
1
0
Data 1
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 68. ECCRD (19h) o r 4ECCRD (18h), QPI Mode, Command Sequence[48, 49]
CS#
SCLK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
Notes
48. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command 19h.
49. A = MSB of address = 31 with command 18h.
Document Number: 002-00368 Rev. *M
Page 97 of 158
S25FS128S/S25FS256S
9.3.9
Program NVDLR (PNVDLR 43h)
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the
Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth bit of data has been latched. If not, the PNVDLR command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR operation is initiated. While the PNVDLR
operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In
Progress (WIP) bit is a 1 during the self-timed PNVDLR cycle, and is a 0. when it is completed. The PNVDLR operation can report a
program error in the P_ERR bit of the Status Register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is
set to a 0. The maximum clock frequency for the PNVDLR command is 133 MHz.
Figure 69. Program NVDLR (PNVDLR) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
9.3.10 Write VDLR (WVDLR 4Ah)
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write
Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth bit of data has been latched. If not, the WVDLR command is not executed.
As soon as CS# is driven to the logic high state, the WVDLR operation is initiated with no delays. The maximum clock frequency for
the PNVDLR command is 133 MHz.
Figure 70. Write VDLR (WVDLR) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
9.3.11 Data Learning Pattern Read (DLPRD 41h)
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP continuously by providing
multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command is 133 MHz.
Figure 71. DLP Read (DLPRD) Command Sequence
CS#
SCK
SI
7
6
5
4
3
SO
Phase
2
1
0
7
Instruction
Document Number: 002-00368 Rev. *M
6
5
4
3
2
Register Read
1
0
7
6
5
4
3
2
1
0
Repeat Register Read
Page 98 of 158
S25FS128S/S25FS256S
9.3.12 Enter 4-Byte Address Mode (4BAM B7h)
The enter 4-byte Address Mode (4BAM) command sets the volatile Address Length bit (CR2V[7]) to 1 to change most 3-byte
address commands to require 4 bytes of address. The Read SFDP (RSFDP) command is the only 3-byte command that is not
affected by the Address Length bit. RSFDP is required by the JEDEC JESD216 standard to always have only 3 bytes of address.
A hardware or software reset is required to exit the 4-byte address mode.
Figure 72. Enter 4-Byte Address Mode (4BAM B7h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
9.3.13 Read Any Register (RDAR 65h)
The Read Any Register (RDAR) command provides a way to read all device registers - non-volatile and volatile. The instruction is
followed by a 3- or 4-byte address (depending on the address length configuration CR2V[7], followed by a number of latency
(dummy) cycles set by CR2V[3:0]. Then the selected register contents are returned. If the read access is continued the same
addressed register contents are returned until the command is terminated - only one register is read by each RDAR command.
Reading undefined locations provides undefined data.
The RDAR command may be used during embedded operations to read Status Register 1 (SR1V).
The RDAR command is not used for reading registers that act as a window into a larger array:ECCSR, PPBAR, and DYBAR. There
are separate commands required to select and read the location in the array accessed.
The RDAR command will read invalid data from the PASS register locations if the ASP Password protection mode is selected by
programming ASPR[2] to 0.
Table 55. Register Address Map
Byte Address (Hex)
Register Name
00000000
SR1NV
00000001
N/A
00000002
CR1NV
00000003
CR2NV
00000004
CR3NV
00000005
CR4NV
...
N/A
00000010
NVDLR
...
N/A
00000020
PASS[7:0]
00000021
PASS[15:8]
00000022
PASS[23:16]
00000023
PASS[31:24]
00000024
PASS[39:32]
00000025
PASS[47:40]
00000026
PASS[55:48]
00000027
PASS[63:56]
...
N/A
00000030
ASPR[7:0]
Document Number: 002-00368 Rev. *M
Description
Non-Volatile Status and Configuration Registers
Non-Volatile Data Learning Register
Non-Volatile Password Register
Non-Volatile
Page 99 of 158
S25FS128S/S25FS256S
Table 55. Register Address Map (Continued)
Byte Address (Hex)
Register Name
00000031
ASPR[15:8]
...
N/A
00800000
SR1V
00800001
SR2V
00800002
CR1V
00800003
CR2V
00800004
CR3V
00800005
CR4V
...
N/A
00800010
VDLR
...
N/A
00800040
PPBL
...
N/A
Description
Volatile Status and Configuration Registers
Volatile Data Learning Register
Volatile PPB Lock Register
Figure 73. Read Any Register Read Command Sequence[50]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
7
Phase
Instruction
Address
6
5
Dummy Cycles
4
3
2
1
0
Data 1
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 74. Read Any Register, QPI Mode, Command Sequence[50]
CS#
SCK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
Note
50. A = MSB of address = 23 for Address length CR2V[7] = 0, or 31 for CR2V[7] = 1.
Document Number: 002-00368 Rev. *M
Page 100 of 158
S25FS128S/S25FS256S
9.3.14 Write Any Register (WRAR 71h)
The Write Any Register (WRAR) command provides a way to write any device register - non-volatile or volatile. The instruction is
followed by a 3- or 4-byte address (depending on the address length configuration CR2V[7], followed by one byte of data to write in
the address selected register.
Before the WRAR command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the
device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit in SR1V may be
checked to determine when the operation is completed. The P_ERR and E_ERR bits in SR1V may be checked to determine if any
error occurred during the operation.
Some registers have a mixture of bit types and individual rules controlling which bits may be modified. Some bits are read only,
some are OTP.
Read only bits are never modified and the related bits in the WRAR command data byte are ignored without setting a program or
erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the WRAR data byte do not matter.
OTP bits may only be programmed to the level opposite of their default state. Writing of OTP bits back to their default state is
ignored and no error is set.
Non-Volatile bits which are changed by the WRAR data, require non-volatile register write time (tW) to be updated. The update
process involves an erase and a program operation on the non-volatile register bits. If either the erase or program portion of the
update fails the related error bit and WIP in SR1V will be set to 1.
Volatile bits which are changed by the WRAR data, require the volatile register write time (tCS) to be updated.
Status Register 1 may be repeatedly read (polled) to monitor the Write-In-Progress (WIP) bit (SR1V[0]) and the error bits
(SR1V[6,5]) to determine when the register write is completed or failed. If there is a write failure, the clear status command is used to
clear the error status and enable the device to return to standby state.
However, the PPBL register can not be written by the WRAR command. Only the PPB Lock Bit Write (PLBWR) command can write
the PPBL register.
The command sequence and behavior is the same as the PP or 4PP command with only a single byte of data provided. See
Section 9.5.2 Page Program (PP 02h or 4PP 12h) on page 111.
The address map of the registers is the same as shown for Section 9.3.13 Read Any Register (RDAR 65h) on page 99.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
9.3.15 Set Burst Length (SBL C0h)
The Set Burst Length (SBL) command is used to configure the Burst Wrap feature. Burst Wrap is used in conjunction with Quad I/O
Read and DDR Quad I/O Read, in legacy SPI or QPI Mode, to access a fixed length and alignment of data. Certain applications can
benefit from this feature by improving the overall system code execution performance. The Burst Wrap feature allows applications
that use cache, to start filling a cache line with instruction or data from a critical address first, then fill the remainder of the cache line
afterwards within a fixed length (8/16/32/64-bytes) of data, without issuing multiple read commands.
The Set Burst Length (SBL) command writes the CR4V register to enable or disable the wrapped read feature and set the wrap
boundary. When enabled the wrapped read feature changes the related read commands from sequentially reading until the
command ends, to reading sequentially wrapped within a group of bytes.
When CR4V[4] = 1, the wrap mode is not enabled and unlimited length sequential read is performed.
When CR4V[4] = 0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes is read starting at the
byte address provided by the read command and wrapping around at the group alignment boundary.
The group of bytes is of length and aligned on an 8-, 16-, 32-, or 64-byte boundary. CR4V[1:0] selects the boundary. See
Section 7.6.6.2 Configuration Register 4 Volatile (CR4V) on page 69.
The starting address of the read command selects the group of bytes and the first data returned is the addressed byte. Bytes are
then read sequentially until the end of the group boundary is reached. If the read continues the address wraps to the beginning of the
group and continues to read sequentially. This wrapped read sequence continues until the command is ended by CS# returning
high.
Table 56. Example Burst Wrap Sequences
CR4V[4,1:0]
Value (Hex)
Wrap
Boundary
(Bytes)
Start Address
(Hex)
1X
Sequential
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ...
00
8
XXXXXX00
00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ...
00
8
XXXXXX07
07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ...
01
16
XXXXXX02
02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, ...
01
16
XXXXXX0C
0C, 0D, 0E, 0F, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, ...
02
32
XXXXXX0A
0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02,
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, ...
02
32
XXXXXX1E
1E, 1F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16,
17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, ...
03
64
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B,
1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34,
35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02 ...
03
64
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02, 03, 04, 05, 06,
07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F,
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, ...
Address Sequence (Hex)
The Power-On Reset, hardware reset, or software reset default burst length can be changed by programming CR4NV with the
desired value using the WRAR command.
Figure 75. Set Burst Length Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00368 Rev. *M
Instruction
Input Data
Page 102 of 158
S25FS128S/S25FS256S
9.4
Read Memory Array Commands
Read commands for the main flash array provide many options for prior generation SPI compatibility or enhanced performance SPI:
Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands (SDR).
Some SDR commands transfer address one bit per rising edge of SCK and return data 1bit of data per rising edge of SCK. These
are called Single width commands.
Some SDR commands transfer both address and data two or four bits per rising edge of SCK. These are called Dual I/O for two
bits, Quad I/O, and QPI for four bits. QPI also transfers instruction four bits per rising edge.
Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called Double Data Rate
(DDR) commands.
There are DDR commands for 4 bits of address or data per SCK edge. These are called Quad I/O DDR and QPI DDR for four bit
per edge transfer.
All of these commands, except QPI Read, begin with an instruction code that is transferred one bit per SCK rising edge. QPI Read
transfers the instruction four bits per SCK rising edge.The instruction is followed by either a 3- or 4-byte address transferred at SDR
or DDR. Commands transferring address or data 2 or 4 bits per clock edge are called Multiple I/O (MIO) commands. For S25FS-S
family devices at 256-Mbits or higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in the
memory array. Separate 4-byte address read commands are provided for access to the entire address space. These devices may
be configured to take a 4-byte address from the host system with the traditional 3-byte address commands. The 4-byte address
mode for traditional commands is activated by setting the Address Length bit in Configuration Register 2 to 0. In the FS128S, higher
order address bits above A23 in the 4-byte address commands, or commands using 4-byte address mode are not relevant and are
ignored because the flash array is only 128 Mbits in size.
The Quad I/O and QPI commands provide a performance improvement option controlled by mode bits that are sent following the
address bits. The mode bits indicate whether the command following the end of the current read will be another read of the same
type, without an instruction at the beginning of the read. These mode bits give the option to eliminate the instruction cycles when
doing a series of Quad Read accesses.
Some commands require delay cycles following the address or mode bits to allow time to access the memory array - read latency.
The delay or read latency cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus any data
provided by the host during these cycles is “don’t care” and the host may also leave the SI signal at high impedance during the
dummy cycles. When MIO commands are used the host must stop driving the IO signals (outputs are high impedance) before the
end of last dummy cycle. When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The
number of dummy cycles varies with the SCK frequency or performance option selected via the Configuration Register 2
(CR2V[3:0]) Latency Code. Dummy cycles are measured from SCK falling edge to next SCK falling edge. SPI outputs are
traditionally driven to a new value on the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the
memory on the same falling edge of SCK that the host stops driving address or mode bits.
The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on all data outputs, in the
dummy cycles immediately before the start of data. The DLP can help the host memory controller determine the phase shift from
SCK to data edges so that the memory controller can capture data at the center of the data eye.
When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides one or more dummy cycles should be
selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict.
When using DDR I/O commands with the DLP enabled, an LC that provides five or more dummy cycles should be selected to allow
one cycle of additional time for the host to stop driving before the memory starts driving the 4-cycle DLP.
Each read command ends when CS# is returned High at any point during data return. CS# must not be returned High during the
mode or dummy cycles before data returns as this may cause mode bits to be captured incorrectly; making it indeterminate as to
whether the device remains in Continuous Read mode.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
9.4.1
Read (Read 03h or 4READ 13h)
The instruction
03h (CR2V[7] = 0) is followed by a 3-byte address (A23–A0) or
03h (CR2V[7] = 1) is followed by a 4-byte address (A31–A0) or
13h is followed by a 4-byte address (A31–A0)
Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock frequency for the Read
command is 50 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 76. Read Command Sequence (3-Byte Address, 03h or 13h)[51]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
7
Phase
9.4.2
Instruction
6
Address
5
4
3
2
1
0
7
6
5
Data 1
4
3
2
1
0
Data N
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)
The instruction
0Bh (CR2V[7] = 0) is followed by a 3-byte address (A23–A0) or
0Bh (CR2V[7] = 1) is followed by a 4-byte address (A31–A0) or
0Ch is followed by a 4-byte address (A31–A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR2V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on SO is “don’t care” and may be high impedance. Then the memory contents, at the address given, are shifted out on SO.
The maximum operating clock frequency for Fast Read command is 133 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 77. Fast Read (FAST_READ) Command Sequence (3-Byte Address, 0Bh [CR2V[7]=0)[52]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
7
Instruction
Address
Dummy Cycles
6
5
4
3
2
1
0
Data 1
Notes
51. A = MSB of address = 23 for CR2V[7] = 0, or 31 for CR2V[7] = 1 or command 13h.
52. A = MSB of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 0Ch.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
9.4.3
Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
BBh (CR2V[7] = 0) is followed by a 3-byte address (A23–A0) or
BBh (CR2V[7] = 1) is followed by a 4-byte address (A31–A0) or
BCh is followed by a 4-byte address (A31–A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This command takes input of the
address and returns read data two bits per SCK rising edge. In some applications, the reduced address input and data output time
might allow for code execution in place (XIP) i.e. directly from the memory device.
The maximum operating clock frequency for Dual I/O Read is 133 MHz.
The Dual I/O Read command has Continuous Read mode bits that follow the address so, a series of Dual I/O Read commands may
eliminate the 8-bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the following
command will also be a Dual I/O Read command. The first Dual I/O Read command in a series starts with the 8-bit instruction,
followed by address, followed by four cycles of mode bits, followed by an optional latency period. If the mode bit pattern is Axh the
next command is assumed to be an additional Dual I/O Read command that does not provide instruction bits. That command starts
with address, followed by mode bits, followed by optional latency.
Variable latency may be added after the mode bits are shifted into SI and SO before data begins shifting out of IO0 and IO1. This
latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the
dummy cycles, the data value on SI and SO are “don’t care” and may be high impedance. The number of dummy cycles is
determined by the frequency of SCK. The latency is configured in CR2V[3:0].
The Continuous Read feature removes the need for the instruction bits in a sequence of read accesses and greatly improves code
execution (XIP) performance. The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read command
through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”)
and may be high impedance. If the Mode bits equal Axh, then the device remains in Dual I/O Continuous Read mode and the next
address can be entered (after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in Figure 79
on page 106; thus, eliminating eight cycles of the command sequence. The following sequences will release the device from Dual
I/O Continuous Read mode; after which, the device can accept standard SPI commands:
1. During the Dual I/O Continuous Read command sequence, if the Mode bits are any value other than Axh, then the next
time CS# is raised high the device will be released from Dual I/O con ti no us read mode.
2. Send the Mode Reset command.
Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial address after the last
address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock
speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is
allowed and may be helpful in preventing I/O signal contention, for the host system to turn off the I/O signal outputs (make them high
impedance) during the last two “don’t care” mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1
(SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Document Number: 002-00368 Rev. *M
Page 105 of 158
S25FS128S/S25FS256S
Figure 78. Dual I/O Read Command Sequence (BBh)[53, 54, 55]
CS#
SCK
IO0
7
6
5
4
3
2
1
IO1
Phase
0
A-1
2
0
6
4
2
0
6
4
2
0
6
4
2
0
A
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Instruction
Address
Mode
Dum
Data 1
Data 2
Figure 79. Dual I/O Continuous Read Command Sequence (4-Byte Address [CR2V[7] = 1])[53, 54]
CS#
SCK
IO0
6
IO1
7
Phase
9.4.4
4
2
0
A-1
5
3
1
A
Data N
2
0
6
4
2
0
3
1
7
5
3
1
Address
Mode
6
7
Dum
4
2
0
6
5
3
1
7
Data 1
4
2
0
5
3
1
Data 2
Quad I/O Read (QIOR EBh or 4QIOR ECh)
The instruction
EBh (CR2V[7] = 0) is followed by a 3-byte address (A23–A0) or
EBh (CR2V[7] = 1) is followed by a 4-byte address (A31–A0) or
ECh is followed by a 4-byte address (A31–A0)
The Quad I/O Read command improves throughput with four I/O signals — IO0–IO3. It allows input of the address bits four bits per
serial SCK clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from S25FS-S
family devices. The Quad bit of the Configuration Register must be set (CR1V[1] = 1) to enable the Quad capability of S25FS-S
family devices.
The maximum operating clock frequency for Quad I/O Read is 133 MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data begins shifting out of
IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to access data at the initial
address. During latency cycles, the data value on IO0–IO3 are “don’t care” and may be high impedance. The number of dummy
cycles is determined by the frequency of SCK. The latency is configured in CR2V[3:0].
Following the latency period, the memory contents at the address given, is shifted out four bits at a time through IO0–IO3. Each
nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Notes
53. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command BBh.
54. A = MSB of address = 31 with command BBh
55. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these cycles to increase bus turn
around time between Mode bits from host and returning data from the memory.
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S25FS128S/S25FS256S
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through the setting of the
Mode bits (after the address sequence, as shown in Figure 80, Quad I/O Read Command Sequence (EBh or ECh) [56, 57]
on page 107). This added feature removes the need for the instruction sequence and greatly improves code execution (XIP). The
upper nibble (bits 7-4) of the Mode bits control the length of the next Quad I/O instruction through the inclusion or exclusion of the
first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the
device remains in Quad I/O High Performance Read mode and the next address can be entered (after CS# is raised high and then
asserted low) without requiring the EBh or ECh instruction, as shown in Figure 82, Continuous Quad I/O Read Command Sequence
(EBh or ECh)[58, 59] on page 108; thus, eliminating eight cycles for the command sequence. The following sequences will release
the device from Quad I/O High Performance Read mode; after which, the device can accept standard SPI commands:
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is
raised high the device will be released from Quad I/O High Performance Read mode.
2. Send the Mode Reset command.
Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal circuitry latency
time to access the initial address after the last address cycle that is clocked into IO0–IO3.
It is important that the IO0–IO3 signals be set to high-impedance at or before the falling edge of the first data out clock. At higher
clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished.
It is allowed and may be helpful in preventing IO0–IO3 signal contention, for the host system to turn off the IO0–IO3 signal outputs
(make them high impedance) during the last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
In QPI Mode (CR2V[6] = 1) the Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the command protocol is
identical to the Quad I/O commands.
Figure 80. Quad I/O Read Command Sequence (EBh or ECh)[56, 57]
CS#
SCK
IO0
A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
7
6
5
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
A-1
6
2
6
0
6
2
6
2
6
2
6
2
IO3
A
7
3
7
1
7
3
7
3
7
3
7
3
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
D1
D2
D3
D4
Figure 81. Quad I/O Read Command Sequence (EBh or ECh), QPI Mode[56, 57]
CS#
SCK
IO0
4
0
A-3
4
0
4
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
0
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
1
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
D4
Notes
56. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EBh.
57. A = MSB of address = 31 with command ECh.
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S25FS128S/S25FS256S
Figure 82. Continuous Quad I/O Read Command Sequence (EBh or ECh)[58, 59]
CS#
SCK
IO0
4
0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
A
7
3
7
3
7
3
7
3
7
3
7
3
Phase
9.4.5
DN-1
DN
Address
Mode
Dummy
D1
D2
D3
D4
DDR Quad I/O Read (EDh, EEh)
The DDR Quad I/O Read command improves throughput with four I/O signals - IO0–IO3. It is similar to the Quad I/O Read command
but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might
allow for code execution (XIP) directly from S25FS-S family devices. The Quad bit of the Configuration Register must be set
(CR1V[1] = 1) to enable the Quad capability.
The instruction
EDh (CR2V[7] = 0) is followed by a 3-byte address (A23–A0) or
EDh (CR2V[7] = 1) is followed by a 4-byte address (A31–A0) or
EEh is followed by a 4-byte address (A31–A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four
bits at a time on each clock edge through IO0–IO3.
The maximum operating clock frequency for DDR Quad I/O Read command is 80 MHz.
For DDR Quad I/O Read, there is a latency required after the last address and mode bits are shifted into the IO0-IO3 signals before
data begins shifting out of IO0–IO3. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access
the initial address. During these latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. When the
Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must
be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR2V[3:0].
Mode bits allow a series of Quad I/O DDR commands to eliminate the 8-bit instruction after the first command sends a
complementary mode bit pattern, as shown in Figure 83, DDR Quad I/O Read Initial Access (EDh or EEh)[60, 61] on page 109. This
feature removes the need for the 8-bit SDR instruction sequence and dramatically reduces initial access times (improves XIP
performance). The Mode bits control the length of the next DDR Quad I/O Read operation through the inclusion or exclusion of the
first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah)
the device transitions to Continuous DDR Quad I/O Read mode and the next address can be entered (after CS# is raised high and
then asserted low) without requiring the EDh or EEh instruction, as shown in Figure 84, Continuous DDR Quad I/O Read
Subsequent Access (EDh or EEh)[60, 61] on page 109, thus eliminating eight cycles from the command sequence. The following
sequences will release the device from Continuous DDR Quad I/O Read mode; after which, the device can accept standard SPI
commands:
1. During the DDR Quad I/O Read Command Sequence, if the Mode bits are not complementary the next time CS# is raised
high and then asserted low the device will be released from DDR Quad I/O Read mode.
2. Send the Mode Reset command.
Notes
58. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EBh.
59. A = MSB of address = 31 with command ECh.
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S25FS128S/S25FS256S
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. Note that the memory
devices may drive the IOs with a preamble prior to the first data value. The preamble is a Data Learning Pattern (DLP) that is used
by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus for the four clock cycles
immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts
outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to
when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the
preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read
operation. The optimized capture point will be determined during the preamble period of every read operation. This optimization
strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h
(or 00110100) will be driven on each of the active outputs (i.e. all four SIOs). This pattern was chosen to cover both “DC” and “AC”
data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks) followed by a
high going transition (001) and the complementary low going transition (110). The two AC transition scenarios include data low for a
short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). The
DC transitions will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully settled
to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC
transitions will bound the ending of the data valid period. These transitions will allow the host controller to identify the beginning and
ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be chosen. See SPI DDR
Data Learning Registers on page 72 for more details.
In QPI Mode (CR2V[6] = 1) the DDR Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the command
protocol is identical to the DDR Quad I/O commands.
Figure 83. DDR Quad I/O Read Initial Access (EDh or EEh)[60, 61]
CS#
SCK
IO0
A-2
12 8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
A-2
13 9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
A-1
14 10 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
A
15 11 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
7
6
5
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1
D2
Figure 84. Continuous DDR Quad I/O Read Subsequent Access (EDh or EEh)[60, 61]
CS#
SCK
IO0
A-3
12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
A-2
13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
A-1
14 10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
A
15 11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Address
Mode
Dummy
D1
D2
D3
D4
D5
Notes
60. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EDh.
61. A = MSB of address = 31 with command EEh.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
Figure 85. DDR Quad I/O Read Initial Access (EDh or EEh), QPI Mode[62, 63]
CS#
SCK
IO0
4
0
A-3
12 8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
5
1
A-2
13 9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
6
2
A-1
14 10 6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
7
3
A
15 11 7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Instruct.
Address
Mode
9.5
Program Flash Array Commands
9.5.1
Program Granularity
Dummy
DLP
D1
D2
9.5.1.1 Automatic ECC
Each 16 byte aligned and 16 byte length Programming Block has an automatic Error Correction Code (ECC) value. The data block
plus ECC form an ECC unit. In combination with Error Detection and Correction (EDC) logic the ECC is used to detect and correct
any single bit error found during a read access. When data is first programmed within an ECC unit the ECC value is set for the entire
ECC unit. If the same ECC unit is programmed more than once the ECC value is changed to disable the EDC function. A sector
erase is needed to again enable Automatic ECC on that Programming Block. The 16 byte Program Block is the smallest program
granularity on which Automatic ECC is enabled.
These are automatic operations transparent to the user. The transparency of the Automatic ECC feature enhances data accuracy
for typical programming operations which write data once to each ECC unit but, facilitates software compatibility to previous
generations of FL family of products by still allowing for single byte programming and bit walking in which the same ECC unit is
programmed more than once. When an ECC unit has Automatic ECC disabled, EDC is not done on data read from the ECC unit
location.
An ECC status register is provided for determining if ECC is enabled on an ECC unit and whether any errors have been detected
and corrected in the ECC unit data or the ECC. The ECC Status Register Read (ECCRD) command is used to read the ECC status
on any ECC unit.
Error Detection and Correction (EDC) is applied to all parts of the Flash address spaces other than registers. An Error Correction
Code (ECC) is calculated for each group of bytes protected and the ECC is stored in a hidden area related to the group of bytes. The
group of protected bytes and the related ECC are together called an ECC unit.
ECC is calculated for each 16 byte aligned and length ECC unit
Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1 bit for an ECC disable Flag
Sector erase resets all ECC disable flags in a sector to the default state (enabled)
ECC is programmed as part of the standard Program commands operation
ECC is disabled automatically if multiple programming operations are done on the same ECC unit.
Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16 byte ECC unit.
The ECC disable flag is programmed when ECC is disabled
To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased
To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC is stored for that
unit and not disabled.
The calculation, programming, and disabling of ECC is done automatically as part of programming operations. The detection and
correction if needed is done automatically as part of read operations. The host system sees only corrected data from a read
operation.
ECC protects the OTP region — however a second program operation on the same ECC unit will disable ECC permanently on
that ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC enable/indicator bit is prohibited)
Notes
62. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EDh.
63. A = MSB of address = 31 with command EEh.
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S25FS128S/S25FS256S
9.5.1.2 Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move
data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single
programming command. Page Programming allows up to a page size (either 256 or 512 bytes) to be programmed in one operation.
The page size is determined by the Configuration Register bit CR3V[4]. The page is aligned on the page size address boundary. It is
possible to program from one bit up to a page size in each Page programming operation. It is recommended that a multiple of
16-byte length and aligned Program Blocks be written. This insures that Automatic ECC is not disabled. For the very best
performance, programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each Page being
programmed only once.
9.5.1.3 Single Byte Programming
Single Byte Programming allows full backward compatibility to the legacy standard SPI Page Programming (PP) command by
allowing a single byte to be programmed anywhere in the memory array. While single byte programming is supported, this will
disable Automatic ECC on the 16 byte ECC unit where the byte is located.
9.5.2
Page Program (PP 02h or 4PP 12h)
The Page Program (PP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). Before the Page
Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the
device. After the Write Enable (WREN) command has been decoded successfully, the device sets the Write Enable Latch (WEL) in
the Status Register to enable any write operations.
The instruction
02h (CR2V[7] = 0) is followed by a 3-byte address (A23–A0) or
02h (CR2V[7] = 1) is followed by a 4-byte address (A31–A0) or
12h is followed by a 4-byte address (A31–A0)
and at least one data byte on SI. Depending on CR3V[4], the page size can either be 256 or 512 bytes. Up to a page can be
provided on SI after the 3-byte address with instruction 02h or 4-byte address with instruction 12h has been provided.
If more data is sent to the device than the space between the starting address and the page aligned end boundary, the data loading
sequence will wrap from the last byte in the page to the zero byte location of the same page and begin overwriting any data
previously loaded in the page. The last page worth of data is programmed in the page. This is a result of the device being equipped
with a page program buffer that is only page size in length. If less than a page of data is sent to the device, these data bytes will be
programmed in sequence, starting at the provided address within the page, without having any affect on the other bytes of the same
page.
Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall programming time
versus loading less than a page into the program buffer.
The programming process is managed by the flash memory device internal control logic. After a programming command is issued,
the programming operation status can be checked using the Read Status Register 1 command. The WIP bit (SR1V[0]) will indicate
when the programming operation is completed. The P_ERR bit (SR1V[6]) will indicate if an error occurs in the programming
operation that prevents successful completion of programming. This includes attempted programming of a protected area.
Figure 86. Page Program (PP 02h or 4PP 12h) Command Sequence[64]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Address
Input Data1
Input Data2
Note
64. A = MSB of address = A23 for PP 02h, or A31 for 4PP 12h.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 87. Page Program (PP 02h or 4PP 12h) QPI Mode Command Sequence[65]
CS#
SCK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Input D1
Input D2
9.6
Erase Flash Array Commands
9.6.1
Parameter 4-kB Sector Erase (P4E 20h or 4P4E 21h)
Input D3
Input D4
The main flash array address map may be configured to overlay 4-kB parameter sectors over the lowest address portion of the
lowest address uniform sector (bottom parameter sectors) or over the highest address portion of the highest address uniform sector
(top parameter sectors). The main flash array address map may also be configured to have only uniform size sectors. The
parameter sector configuration is controlled by the configuration bit CR3V[3]. The P4E and 4P4E commands are ignored when the
device is configured for uniform sectors only (CR3V[3] = 1).
The parameter 4-kB Sector Erase commands set all the bits of a 4-kB parameter sector to 1 (all bytes are FFh). Before the P4E or
4P4E command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device,
which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
20h [CR2V[7] = 0] is followed by a 3-byte address (A23–A0), or
20h [CR2V[7] = 1] is followed by a 4-byte address (A31–A0), or
21h is followed by a 4-byte address (A31–A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of the address has been latched in on SI. This
will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the chosen sector of the flash
memory array. If CS# is not driven high after the last bit of address, the Sector Erase operation will not be executed.
As soon as CS# is driven high, the internal erase cycle will be initiated. With the internal erase cycle in progress, the user can read
the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a 1.
when the erase cycle is in progress and a 0 when the erase cycle has been completed.
A P4E or 4P4E command applied to a sector that has been write protected through the Block Protection bits or ASP, will not be
executed and will set the E_ERR status. A P4E command applied to a sector that is larger than 4 KB will not be executed and will
not set the E_ERR status.
Figure 88. Parameter Sector Erase (P4E 20h or 4P4E 21h) Command Sequence[66]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
Note
65. A = MSB of address = A23 for PP 02h, or A31 for 4PP 12h.
66. A = MSB of address = A23 for P4E 20h with CR2V[7] = 0, or A31 for P4E 20h with CR2V[7] = 1 or 4P4E 21h.
Document Number: 002-00368 Rev. *M
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This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 89. Parameter Sector Erase (P4E 20h or 4P4E 21h) QPI Mode Command Sequence[67]
CS#
SCK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
9.6.2
Instructtion
Address
Sector Erase (SE D8h or 4SE DCh)
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the Sector Erase (SE)
command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
D8h [CR2V[7] = 0] is followed by a 3-byte address (A23–A0), or
D8h [CR2V[7] = 1] is followed by a 4-byte address (A31–A0), or
DCh is followed by a 4-byte address (A31–A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been latched in on SI. This will
initiate the erase cycle, which involves the pre-programming and erase of the chosen sector. If CS# is not driven high after the last
bit of address, the Sector Erase operation will not be executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal erase cycle in progress,
the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate
a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed.
A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection bits or ASP, will not
be executed and will set the E_ERR status.
A device configuration option (CR3V[1]) determines whether the SE command erases 64 KB or 256 KB. The option to use this
command to always erase 256 KB provides for software compatibility with higher density and future S25FS family devices.
A device configuration option (CR3V[3]) determines whether 4-kB parameter sectors are in use. When CR3V[3] = 0, 4-kB parameter
sectors overlay a portion of the highest or lowest address 32 kB of the device address space. If a Sector Erase command is applied
to a 64-kB sector that is overlaid by 4-kB sectors, the overlaid 4-kB sectors are not affected by the erase. Only the visible
(non-overlaid) portion of the 64-kB sector appears erased. Similarly if a Sector Erase command is applied to a 256-kB range that is
overlaid by 4-kB sectors, the overlaid 4-kB sectors are not affected by the erase. When CR3V[3] = 1, there are no 4-kB parameter
sectors in the device address space and the Sector Erase command always operates on fully visible 64-kB or 256-kB sectors.
ASP has a PPB and a DYB protection bit for each physical sector, including any 4-kB sectors. If a Sector Erase command is applied
to a 256-kB range that includes a 64-kB protected physical sector, the erase will not be executed on the 256-kB range and will set
the E_ERR status.
Note
67. A = MSB of address = A23 for P4E 20h with CR2V[7] = 0, or A31 for P4E 20h with CR2V[7] = 1 or 4P4E 21h.
Document Number: 002-00368 Rev. *M
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Figure 90. Sector Erase (SE D8h or 4SE DCh) Command Sequence[68]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 91. Sector Erase (SE D8h or 4SE DCh) QPI Mode Command Sequence[69]
CS#
SCK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
9.6.3
Instructtion
Address
Bulk Erase (BE 60h or C7h)
The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the BE command
can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
erase cycle, which involves the pre-programming and erase of the entire flash memory array. If CS# is not driven high after the last
bit of instruction, the BE operation will not be executed.
As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in progress, the user can
read the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a 1
when the erase cycle is in progress and a 0 when the erase cycle has been completed.
A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0s. If the BP bits are not 0, the BE
command is not executed and E_ERR is not set. The BE command will skip any sectors protected by the DYB or PPB and the
E_ERR status will not be set.
Figure 92. Bulk Erase Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Notes
68. A = MSB of address = A23 for SE D8h with CR2V[7] = 0, or A31 for SE D8h with CR2V[7] = 1 or 4P4E DCh.
69. A = MSB of address = A23 for P4E 20h with CR2V[7] = 0, or A31 for P4E 20h with CR2V[7] = 1 or 4P4E 21h.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 93. Bulk Erase Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.6.4
Instruction
Evaluate Erase Status (EES D0h)
The Evaluate Erase Status (EES) command verifies that the last erase operation on the addressed sector was completed
successfully. If the selected sector was successfully erased the Erase Status bit (SR2V[2]) is set to 1. If the selected sector was not
completely erased SR2V[2] is 0.
The EES command can be used to detect erase operations failed due to loss of power, reset, or failure during the erase operation.
The EES instruction is followed by a 3- or 4-byte address, depending on the address length configuration (CR2V[7]). The EES
command requires tEES to complete and update the Erase Status in SR2V. The WIP bit (SR1V[0]) may be read using the RDSR1
(05h) command, to determine when the EES command is finished. Then the RDSR2 (07h) or the RDAR (65h) command can be
used to read SR2V[2]. If a sector is found not erased with SR2V[2] = 0, the sector must be erased again to ensure reliable storage of
data in the sector.
The Write Enable command (to set the WEL bit) is not required before the EES command. However, the WEL bit is set by the device
itself and cleared at the end of the operation, as visible in SR1V[1] when reading status.
Figure 94. EES Command Sequence[70]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 95. EES QPI Mode Command Sequence[70]
CS#
SCK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Notes
70. A = MSB of address = A23 for CR2V[7] = 0, or A31 for CR2V[7] = 1.
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S25FS128S/S25FS256S
9.6.5
Program or Erase Suspend (PES 85h, 75h, B0h)
There are three instruction codes for Program or Erase Suspend (PES) to enable legacy and alternate source software compatibility.
The PES command allows the system to interrupt a programming or erase operation and then read from any other
non-erase-suspended sector or non-program-suspended-page. Program or Erase Suspend is valid only during a programming or
Sector Erase operation. A Bulk Erase operation cannot be suspended.
The Write-In-Progress (WIP) bit in Status Register 1 (SR1V[0]) must be checked to know when the programming or erase operation
has stopped. The Program Suspend Status bit in the Status Register 2 (SR2[0]) can be used to determine if a programming
operation has been suspended or was completed at the time WIP changes to 0. The Erase Suspend Status bit in the Status Register
2 (SR2[1]) can be used to determine if an erase operation has been suspended or was completed at the time WIP changes to 0. The
time required for the suspend operation to complete is tSL, see Program and Erase Performance on page 131.
An Erase can be suspended to allow a program operation or a read operation. During an erase suspend, the DYB array may be read
to examine sector protection and written to remove or restore protection on a sector to be programmed.
A program operation may be suspended to allow a read operation.
A new erase operation is not allowed with an already suspended erase or program operation. An erase command is ignored in this
situation.
Table 57. Commands Allowed During Program or Erase Suspend
Instruction
Name
Instruction
Code
(Hex)
Allowed
During
Erase
Suspend
PP
02
X
READ
03
X
Allowed
During
Program
Suspend
Comment
Required for array program during erase suspend. Only allowed if there is no other
program suspended program operation (SR2V[0]=0). A program command will be
ignored while there is a suspended program. If a program command is sent for a
location within an erase suspended sector the program operation will fail with the
P_ERR bit set.
X
All array reads allowed in suspend.
RDSR1
05
X
X
Needed to read WIP to determine end of suspend process.
RDAR
65
X
X
Alternate way to read WIP to determine end of suspend process.
WREN
06
X
RDSR2
07
X
Required for program command within erase suspend.
X
Needed to read suspend status to determine whether the operation is suspended or
complete.
Required for array program during erase suspend. Only allowed if there is no other
program suspended program operation (SR2V[0] = 0). A program command will be
ignored while there is a suspended program. If a program command is sent for a
location within an erase suspended sector the program operation will fail with the
P_ERR bit set.
4PP
12
X
4READ
13
X
CLSR
30
X
Clear status may be used if a program operation fails during erase suspend. Note
the instruction is only valid if enabled for clear status by CR4NV[2] = 1.
CLSR
82
X
Clear status may be used if a program operation fails during erase suspend.
EPR
30
X
X
Required to resume from erase or program suspend. Note the command must be
enabled for use as a resume command by CR4NV[2] = 0.
EPR
7A
X
X
Required to resume from erase or program suspend.
EPR
8A
X
X
Required to resume from erase or program suspend.
RSTEN
66
X
X
Reset allowed anytime.
RST
99
X
X
Reset allowed anytime.
X
All array reads allowed in suspend.
FAST_READ
0B
X
X
All array reads allowed in suspend.
4FAST_READ
0C
X
X
All array reads allowed in suspend.
EPR
7A
X
Required to resume from erase suspend.
EPR
8A
X
Required to resume from erase suspend.
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S25FS128S/S25FS256S
Table 57. Commands Allowed During Program or Erase Suspend (Continued)
Instruction
Name
Instruction
Code
(Hex)
Allowed
During
Erase
Suspend
Allowed
During
Program
Suspend
Comment
DIOR
BB
X
X
All array reads allowed in suspend.
4DIOR
BC
X
X
All array reads allowed in suspend.
DYBRD
FA
X
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
DYBWR
FB
X
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
PPBRD
FC
X
Allowed for checking Persistent Protection before attempting a program command
during erase suspend.
4DYBRD
E0
X
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
4DYBWR
E1
X
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
4PPBRD
E2
X
Allowed for checking Persistent Protection before attempting a program command
during erase suspend.
QIOR
EB
X
X
All array reads allowed in suspend.
4QIOR
EC
X
X
All array reads allowed in suspend.
DDRQIOR
ED
X
X
All array reads allowed in suspend.
4DDRQIOR
EE
X
X
All array reads allowed in suspend.
RESET
F0
X
X
Reset allowed anytime.
MBR
FF
X
X
May need to reset a read operation during suspend.
Reading at any address within an erase-suspended sector or program-suspended page produces undetermined data.
The WRR, WRAR, or PPB Erase commands are not allowed during Erase or Program Suspend, it is therefore not possible to alter
the Block Protection or PPB bits during Erase Suspend. If there are sectors that may need programming during Erase suspend,
these sectors should be protected only by DYB bits that can be turned off during Erase Suspend.
After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The system can
determine the status of the program operation by reading the WIP bit in the Status Register, just as in the standard program
operation.
Figure 96. Program or Erase Suspend Command Sequence
tSL
CS#
SCK
SI
7 6 5 4 3
2 1 0
7 6 5
4 3 2 1 0
SO
Phase
7 6 5
7 6 5
Suspend Instruction
Phase
Document Number: 002-00368 Rev. *M
Read Status Instruction
4 3 2 1 0
4 3 2 1 0
Status
Instr. During Suspend
Repeat Status Read Until Suspended
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S25FS128S/S25FS256S
Figure 97. Program or Erase Suspend Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 98. Program or Erase Suspend Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.6.6
Instruction
Erase or Program Resume (EPR 7Ah, 8Ah, 30h)
There are three instruction codes for Erase or Program Resume (EPR) to enable legacy and alternate source software compatibility.
After program or read operations are completed during a program or erase suspend the Erase or Program Resume command is
sent to continue the suspended operation.
After an Erase or Program Resume command is issued, the WIP bit in the Status Register 1 will be set to a 1 and the programming
operation will resume if one is suspended. If no program operation is suspended the suspended erase operation will resume. If there
is no suspended program or erase operation the resume command is ignored.
Program or erase operations may be interrupted as often as necessary e.g. a program suspend command could immediately follow
a program resume command but, in order for a program or erase operation to progress to completion there must be some periods of
time between resume and the next suspend command greater than or equal to tRS. See Program or Erase Suspend AC Parameters
on page 131.
An Erase or Program Resume command must be written to resume a suspended operation.
Figure 99. Erase or Program Resume Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00368 Rev. *M
Instruction
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S25FS128S/S25FS256S
Figure 100. Erase or Program Resume Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
3
Instruction
9.7
One-Time Program Array Commands
9.7.1
OTP Program (OTPP 42h)
The OTP Program command programs data in the One-Time Program region, which is in a different address space from the main
array data. The OTP region is 1024 bytes so, the address bits from A31 to A10 must be 0 for this command. Refer to OTP Address
Space on page 54 for details on the OTP region.
Before the OTP Program command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded
by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit in SR1V
may be checked to determine when the operation is completed. The P_ERR bit in SR1V may be checked to determine if any error
occurred during the operation.
To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to 1.
Each region in the OTP memory space can be programmed one or more times, provided that the region is not locked. Attempting to
program 0s in a region that is locked will fail with the P_ERR bit in SR1V set to 1. Programming ones, even in a protected area does
not cause an error and does not set P_ERR. Subsequent OTP programming can be performed only on the un-programmed bits (that
is, 1 data). Programming more than once within an ECC unit will disable ECC on that unit.
The protocol of the OTP Program command is the same as the Page Program command. See Page Program (PP 02h or 4PP 12h)
on page 111 for the command sequence.
9.7.2
OTP Read (OTPR 4Bh)
The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits from A31 to A10 must
be zero for this command. Refer to OTP Address Space on page 54 for details on the OTP region. The protocol of the OTP Read
command is similar to the Fast Read command except that it will not wrap to the starting address after the OTP address is at its
maximum; instead, the data beyond the maximum OTP address will be undefined. The OTP Read command read latency is set by
the latency value in CR2V[3:0]. See Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch) on page 104 for the command sequence.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
9.8
Advanced Sector Protection Commands
9.8.1
ASP Read (ASPRD 2Bh)
The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP register contents are
shifted out on the serial output SO, least significant byte first. Each bit is shifted out at the SCK frequency by the falling edge of the
SCK signal. It is possible to read the ASP register continuously by providing multiples of 16 clock cycles. The maximum operating
clock frequency for the ASP Read (ASPRD) command is 133 MHz.
Figure 101. ASPRD Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
7
Phase
9.8.2
6
Instruction
5
4
3
2
1
0
7
Output ASPR Low Byte
6
5
4
3
2
1
0
Output ASPR High Byte
ASP Program (ASPP 2Fh)
Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to
enable any write operations.
The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data bytes on SI, least
significant byte first. The ASP Register is two data bytes in length.
The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other
programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the ASPP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed ASPP operation is initiated. While the ASPP operation is in
progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
1 during the self-timed ASPP operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable
Latch (WEL) is set to a 0.
Figure 102. ASPP Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Document Number: 002-00368 Rev. *M
Input ASPR Low Byte
Input ASPR High Byte
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S25FS128S/S25FS256S
9.8.3
DYB Read (DYBRD FAh or 4DYBRD E0h)
The instruction is latched into SI by the rising edge of the SCK signal. The instruction is followed by the 24 or 32-bit address,
depending on the address length configuration CR2V[7], selecting location zero within the desired sector. Note, the high order
address bits not used by a particular density device must be zero. Then the 8-bit DYB access register contents are shifted out on the
serial output SO. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the same
DYB access register continuously by providing multiples of eight clock cycles. The address of the DYB register does not increment
so this is not a means to read the entire DYB array. Each location must be read with a separate DYB Read command. The maximum
operating clock frequency for READ command is 133 MHz.
Figure 103. DYBRD Command Sequence[71, 72]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
7
Instruction
Address
6
5
4
3
2
1
0
7
6
Register
5
4
3
2
1
0
Repeat Register
This command is also supported in QPI Mode. In QPI Mode the instruction and address is shifted in on IO0–IO3 and returning data
is shifted out on IO0–IO3.
Figure 104. DYBRD QPI Mode Command Sequence[71, 72]
CS#
SCK
IO0
4
0
A-3
4
0
4
0
IO1
5
1
A-2
5
1
5
1
IO2
6
2
A-1
6
2
6
2
IO3
7
3
A
7
3
7
3
Phase
Instruction
Address
Output DYBAR
Notes
71. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7] = 1 with command FAh.
72. A = MSB of address = 31 with command E0h.
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S25FS128S/S25FS256S
9.8.4
DYB Write (DYBWR FBh or 4DYBWR E1h)
Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to
enable any write operations.
The DYBWR command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24- or 32-bit
address, depending on the address length configuration CR2V[7], selecting location zero within the desired sector (note, the high
order address bits not used by a particular density device must be zero), then the data byte on SI. The DYB Access Register is one
data byte in length. The data value must be 00h to protect or FFh to unprotect the selected sector.
The DYBWR command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other
programming operation. CS# must be driven to the logic high state after the eighth bit of data has been latched in. As soon as CS#
is driven to the logic high state, the self-timed DYBWR operation is initiated. While the DYBWR operation is in progress, the Status
Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the
self-timed DYBWR operation, and is a 0 when it is completed. When the DYBWR operation is completed, the Write Enable Latch
(WEL) is set to a 0.
Figure 105. DYBWR Command Sequence[73, 74]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Address
Input Data
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 106. DYBWR QPI Mode Command Sequence[73, 74]
CS#
SCK
IO0
4
0
A-3
4
0
4
0
IO1
5
1
A-2
5
1
5
1
IO2
6
2
A-1
6
2
6
2
IO3
7
3
A
7
3
7
3
Phase
Instruction
Address
Input DYBAR
Notes
73. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7] = 1 with command FBh.
74. A = MSB of address = 31 with command E1h.
Document Number: 002-00368 Rev. *M
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S25FS128S/S25FS256S
9.8.5
PPB Read (PPBRD FCh or 4PPBRD E2h)
The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 24- or 32-bit address, depending on the
address length configuration CR2V[7], selecting location zero within the desired sector (note, the high order address bits not used by
a particular density device must be zero). Then the 8-bit PPB access register contents are shifted out on SO.
It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles. The address of the PPB
register does not increment so this is not a means to read the entire PPB array. Each location must be read with a separate PPB
Read command. The maximum operating clock frequency for the PPB Read command is 133 MHz.
Figure 107. PPBRD Command Sequence[75, 76]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
7
Phase
9.8.6
Instruction
6
Address
5
4
3
2
1
0
7
Register
6
5
4
3
2
1
0
Repeat Register
PPB Program (PPBP FDh or 4PPBP E3h)
Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to
enable any write operations.
The PPBP command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24- or 32-bit
address, depending on the address length configuration CR2V[7], selecting location zero within the desired sector (note, the high
order address bits not used by a particular density device must be zero).
The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other
programming operation.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is initiated. While the PPBP operation is in
progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The WIP bit is a 1 during the
self-timed PPBP operation, and is a 0 when it is completed. When the PPBP operation is completed, the Write Enable Latch (WEL)
is set to a 0.
Figure 108. PPBP Command Sequence[77, 78]
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
Notes
75. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7] = 1 with command FCh.
76. A = MSB of address = 31 with command E2h.
77. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7] = 1 with command FDh.
78. A = MSB of address = 31 with command E3h.
Document Number: 002-00368 Rev. *M
Page 123 of 158
S25FS128S/S25FS256S
9.8.7
PPB Erase (PPBE E4h)
The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by the device, a Write
Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status
Register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
beginning of internal erase cycle, which involves the pre-programming and erase of the entire PPB memory array. Without CS#
being driven to the logic high state after the eighth bit of the instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has
been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed.
Erase suspend is not allowed during PPB Erase.
Figure 109. PPB Erase Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
9.8.8
Instruction
PPB Lock Bit Read (PLBRD A7h)
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is possible to read the
PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock Register contents may only be read when
the device is in standby state with no other operation in progress. It is recommended to check the Write-In Progress (WIP) bit of the
Status Register before issuing a new command to the device.
Figure 110. PPB Lock Register Read Command Sequence
CS#
SCK
SI
7
6
5
4
3
SO
Phase
2
1
0
7
Instruction
Document Number: 002-00368 Rev. *M
6
5
4
3
Register Read
2
1
0
7
6
5
4
3
2
1
0
Repeat Register Read
Page 124 of 158
S25FS128S/S25FS256S
9.8.9
PPB Lock Bit Write (PLBWR A6h)
The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR command can be accepted
by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch
(WEL) in the Status Register to enable any write operations.
The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the PLBWR command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR operation is initiated. While the PLBWR operation
is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress
(WIP) bit is a 1 during the self-timed PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed,
the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.
Figure 111. PPB Lock Bit Write Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
9.8.10 Password Read (PASSRD E7h)
The correct password value may be read only after it is programmed and before the Password mode has been selected by
programming the Password Protection mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection mode is selected
the password is no longer readable, the PASSRD command will output undefined data.
The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO, least significant byte first,
most significant bit of each byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible
to read the Password continuously by providing multiples of 64 clock cycles. The maximum operating clock frequency for the
PASSRD command is 133 MHz.
Figure 112. Password Read Command Sequence
CS#
SCK
SI
7
6
5
4
3
SO
Phase
2
1
0
7
Instruction
Document Number: 002-00368 Rev. *M
6
5
4
3
Data 1
2
1
0
7
6
5
4
3
2
1
0
Data N
Page 125 of 158
S25FS128S/S25FS256S
9.8.11 Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device. After the Write Enable (WREN) command has been decoded, the device sets the Write Enable
Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password mode is selected by programming the Password Protection mode bit
to 0 in the ASP Register (ASP[2]). After the Password Protection mode is selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PASSP operation is initiated. While the PASSP operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a 1 during the self-timed PASSP cycle, and is a 0 when it is completed. The PASSP command can report a program error in the
P_ERR bit of the Status Register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The
maximum clock frequency for the PASSP command is 133 MHz.
Figure 113. Password Program Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Password Low Byte
Input Password High Byte
9.8.12 Password Unlock (PASSU E9h)
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSU command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PASSU operation is initiated. While the PASSU operation
is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit
is a 1 during the self-timed PASSU cycle, and is a 0 when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register, an error is reported by
setting the P_ERR bit to 1. The WIP bit of the Status Register also remains set to 1. It is necessary to use the CLSR command to
clear the Status Register, the RESET command to software reset the device, or drive the RESET# input low to initiate a hardware
reset, in order to return the P_ERR and WIP bits to 0. This returns the device to standby state, ready for new commands such as a
retry of the PASSU command.
If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU command is 133 MHz.
Figure 114. Password Unlock Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Document Number: 002-00368 Rev. *M
Input Password Low Byte
Input Password High Byte
Page 126 of 158
S25FS128S/S25FS256S
9.9
Reset Commands
Software controlled Reset commands restore the device to its initial power-up state, by reloading volatile registers from non-volatile
default values. However, the volatile FREEZE bit in the Configuration Register CR1V[0] and the volatile PPB Lock bit in the PPB
Lock Register are not changed by a software reset. The software reset cannot be used to circumvent the FREEZE or PPB Lock bit
protection mechanisms for the other security configuration bits.
The Freeze bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the FREEZE bit and set the
PPB Lock bit to its protection mode selected power-on state, a full power-on-reset sequence or hardware reset must be done.
The non-volatile bits in the Configuration Register (CR1NV), TBPROT_O, TBPARM, and BPNV_O, retain their previous state after a
software reset.
The Block Protection bits BP2, BP1, and BP0, in the Status Register (SR1V) will only be reset to their default value if FREEZE = 0.
A reset command (RST or RESET) is executed when CS# is brought high at the end of the instruction and requires tRPH time to
execute.
In the case of a previous Power-Up Reset (POR) failure to complete, a reset command triggers a full power-up sequence requiring
tPU to complete.
Figure 115. Software Reset Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 116. Software Reset Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00368 Rev. *M
Instruction
Page 127 of 158
S25FS128S/S25FS256S
9.9.1
Software Reset Enable (RSTEN 66h)
The Reset Enable (RSTEN) command is required immediately before a Reset command (RST) such that a software reset is a
sequence of the two commands. Any command other than RST following the RSTEN command, will clear the reset enable condition
and prevent a later RST command from being recognized.
9.9.2
Software Reset (RST 99h)
The Reset (RST) command immediately following a RSTEN command, initiates the software reset process.
9.9.3
Legacy Software Reset (RESET F0h)
The Legacy Software Reset (RESET) is a single command that initiates the software reset process. This command is disabled by
default but can be enabled by programming CR3V[0] = 1, for software compatibility with Cypress legacy FL-S devices.
9.9.4
Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command is used to return the device from continuous high performance read mode back to normal
standby awaiting any new command. Because some device packages lack a hardware RESET# input and a device that is in a
continuous high performance read mode may not recognize any normal SPI command, a system hardware reset or software reset
command may not be recognized by the device. It is recommended to use the MBR command after a system reset when the
RESET# signal is not available or, before sending a software reset, to ensure the device is released from continuous high
performance read mode.
The MBR command sends 1s on SI or IO0 for 8 SCK cycles. IO1 to IO3 are “don’t care” during these cycles.
Figure 117. Mode Bit Reset Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 118. Mode Bit Reset Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00368 Rev. *M
3
Instruction
Page 128 of 158
S25FS128S/S25FS256S
9.10
DPD Commands
9.10.1 Enter Deep Power-Down (DPD B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep Power
Down command. The lower power consumption makes the Deep Power-Down (DPD) command especially useful for battery
powered applications (see IDPD in Section 4.6 DC Characteristics on page 29).
The DPD command is accepted only while the device is not performing an embedded operation as indicated by the Status
Register-1 volatile Write In Progress (WIP) bit being cleared to zero (SR1V[0] = 0).
The command is initiated by driving the CS# pin low and shifting the instruction code “B9h” as shown in Figure 119 on page 129.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done, the Deep Power-Down command will not
be executed. After CS# is driven high, the power-down state will be entered within the time duration of tDPD (See Section 5. Timing
Specifications on page 31).
While in the power-down state, only the Release from Deep Power-Down command, which restores the device to normal operation,
will be recognized. All other commands are ignored. This includes the Read Status Register command, which is always available
during normal operation. Ignoring all but one command also makes the Power Down state useful for write protection. The device
always powers-up in the interface standby state with the standby current of ICC1.
Figure 119. Deep Power-Down Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 120. DPD Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00368 Rev. *M
Instruction
Page 129 of 158
S25FS128S/S25FS256S
9.10.2 Release from Deep Power-Down (RES ABh)
The Release from Deep Power-Down command is used to release the device from the deep power-down state. In some legacy SPI
devices, the RES command could also be used to obtain the device electronic identification (ID) number. However, the device ID
function is not supported by the RES command.
To release the device from the deep power-down state, the command is issued by driving the CS# pin low, shifting the instruction
code ‘ABh’ and driving CS# high as shown in Figure 121. Release from deep power-down will take the time duration of tRES (See
Section 5. Timing Specifications on page 31) before the device will resume normal operation and other commands are accepted.
The CS# pin must remain high during the tRES time duration.
Hardware Reset will also release the device from the DPD state as part of the hardware reset process.
Figure 121. Release from Deep Power-Down Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0–IO3, two clock cycles per byte.
Figure 122. RES Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00368 Rev. *M
Instruction
Page 130 of 158
S25FS128S/S25FS256S
10.
Embedded Algorithm Performance Tables
The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural requirements for performing
valid endurance and retention tests based on a qualification specification. This methodology is intended to determine the ability of a
flash device to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life
(data retention). Endurance and retention qualification specifications are specified in JESD47 or may be developed using
knowledge-based methods as in JESD94.
Table 58. Program and Erase Performance
Symbol
Parameter
Typ[80]
Max
Unit
tW
Non-Volatile Register Write Time
240
750
ms
tPP
Page Programming (512 bytes)
Page Programming (256 bytes)
475
360
2000
2000
µs
Sector Erase Time (64-kB or 4-kB physical sectors)
240
725
ms
Sector Erase Time (256-kB logical sectors = 4x64K physical sectors)
930
2900
ms
tSE
Min
[79]
Bulk Erase Time (S25FS128S)
60
180
sec
tBE [79]
Bulk Erase Time (S25FS256S)
120
360
sec
tBE
tEES
Evaluate Erase Status Time (64-kB or 4-kB physical sectors)
20
25
Evaluate Erase Status Time (256-kB physical or logical sectors)
80
100
Erase per sector
100,000
µs
cycles
Notes
79. Not 100% tested.
80. Typical program and erase times assume the following conditions: 25 °C, VCC = 1.8 V; random data pattern.
81. The programming time for any OTP programming command is the same as tPP. This includes OTPP 42h, PNVDLR 43h, ASPP 2Fh, and PASSP E8h.
82. The programming time for the PPBP E3h command is the same as tPP. The erase time for PPBE E4h command is the same as tSE.
83. Data retention of 20 years is based on 1k erase cycles or less.
Table 59. Program or Erase Suspend AC Parameters
Parameter
Typ
Suspend Latency (tSL)
Resume to next Program Suspend (tRS)
Document Number: 002-00368 Rev. *M
100
Max
Unit
Comments
50
µs
The time from Suspend command until the WIP bit is 0.
µs
Minimum is the time needed to issue the next Suspend
command but ≥ typical periods are needed for Program
or Erase to progress to completion.
Page 131 of 158
S25FS128S/S25FS256S
11.
Data Integrity
11.1
Erase Endurance
Table 60. Erase Endurance
Parameter
Minimum
Unit
Program/Erase cycles per main Flash array sectors
100K
P/E cycle
Program/Erase cycles per PPB array or non-volatile register array [84]
100K
P/E cycle
Note
84. Each write command to a non-volatile register causes a P/E cycle on the entire non-volatile register array. OTP bits and registers internally reside in a separate array
that is not P/E cycled.
11.2
Data Retention
Table 61. Data Retention
Parameter
Test Conditions
Data Retention Time
Minimum Time
Unit
10K Program/Erase Cycles
20
Years
100K Program/Erase Cycles
2
Years
Contact Cypress Sales or an FAE representative for additional information on data integrity. An application note is available at:
http://www.cypress.com/appnotes.
11.3
Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides a pointer to
each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B standard. Two optional parameter tables for
Sector Map and 4-Byte Address Instructions follow the Basic Flash table. Cypress provides an additional parameter by pointing to
the ID-CFI address space i.e. the ID-CFI address space is a sub-set of the SFDP address space. The parameter tables portion of the
SFDP data structure are located within the ID-CFI address space and is thus both a CFI parameter and an SFDP parameter. In this
way both SFDP and ID-CFI information can be accessed by either the RSFDP or RDID commands.
Table 62. SFDP Overview Map
Byte Address
0000h
,,,
1000h
...
1090h
...
Description
Location zero within JEDEC JESD216B SFDP space – start of SFDP header.
Remainder of SFDP header followed by undefined space.
Location zero within ID-CFI space – start of ID-CFI parameter tables.
ID-CFI parameters.
Start of SFDP parameter tables which are also grouped as one of the CFI parameter tables (the CFI parameter itself starts
at 108Eh, the SFDP parameter table data is double word aligned starting at 1090h).
Remainder of SFDP parameter tables followed by either more CFI parameters or undefined space.
Document Number: 002-00368 Rev. *M
Page 132 of 158
S25FS128S/S25FS256S
11.3.1 Field Definitions
Table 63. SFDP Header
SFDP Byte
Address
SFDP Dword
Name
00h
01h
02h
SFDP Header 1st
DWORD
03h
Data
Description
53h
This is the entry point for Read SFDP (5Ah) command i.e. location zero within SFDP
space ASCII “S”
46h
ASCII “F”
44h
ASCII “D”
50h
ASCII “P”
06h
SFDP Minor Revision (06h = JEDEC JESD216 Revision B) This revision is backward
compatible with all prior minor revisions. Minor revisions are changes that define
previously reserved fields, add fields to the end, or that clarify definitions of existing fields.
Increments of the minor revision value indicate that previously reserved parameter fields
may have been assigned a new definition or entire Dwords may have been added to the
parameter table. However, the definition of previously existing fields is unchanged and
therefore remain backward compatible with earlier SFDP parameter table revisions.
Software can safely ignore increments of the minor revision number, as long as only
those parameters the software was designed to support are used i.e. previously reserved
fields and additional Dwords must be masked or ignored. Do not do a simple compare on
the minor revision number, looking only for a match with the revision number that the
software is designed to handle. There is no problem with using a higher number minor
revision.
01h
SFDP Major Revision This is the original major revision. This major revision is
compatible with all SFDP reading and parsing software.
06h
05h
Number of Parameter Headers (zero based, 05h = 6 parameters)
07h
FFh
Unused
08h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
00h
Parameter Minor Revision (00h = JESD216) - This older revision parameter header is
provided for any legacy SFDP reading and parsing software that requires seeing a minor
revision 0 parameter header. SFDP software designed to handle later minor revisions
should continue reading parameter headers looking for a higher numbered minor revision
that contains additional parameters for that software revision.
0Ah
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is
compatible with this major revision.
0Bh
09h
Parameter Table Length (in double words = Dwords = 4 byte units) 09h = 9 Dwords
0Ch
90h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI Flash
parameter byte offset = 1090h
04h
SFDP Header
2nd DWORD
05h
09h
0Dh
0Eh
Parameter
Header 0 1st
DWORD
Parameter
Header 0 2nd
DWORD
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
0Fh
FFh
Parameter ID MSB (FFh = JEDEC defined legacy Parameter ID)
10h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
05h
Parameter Minor Revision (05h = JESD216 Revision A) - This older revision parameter
header is provided for any legacy SFDP reading and parsing software that requires
seeing a minor revision 5 parameter header. SFDP software designed to handle later
minor revisions should continue reading parameter headers looking for a later minor
revision that contains additional parameters.
12h
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is
compatible with this major revision.
13h
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
14h
90h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI Flash
parameter byte offset = 1090h address
10h
Parameter Table Pointer Byte 1
11h
15h
16h
Parameter
Header 1 1st
DWORD
Parameter
Header 1 2nd
DWORD
17h
Document Number: 002-00368 Rev. *M
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
Page 133 of 158
S25FS128S/S25FS256S
Table 63. SFDP Header (Continued)
SFDP Byte
Address
SFDP Dword
Name
Data
18h
19h
00h
Description
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
06h
Parameter Minor Revision (06h = JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is
compatible with this major revision.
1Bh
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
1Ch
90h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC Basic SPI Flash
parameter byte offset = 1090h address
10h
Parameter Table Pointer Byte 1
1Ah
1Dh
1Eh
Parameter
Header 2 1st
DWORD
Parameter
Header 2 2nd
DWORD
00h
Parameter Table Pointer Byte 2
1Fh
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
20h
81h
Parameter ID LSB (81h = SFDP Sector Map Parameter)
21h
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that
recognizes this parameter’s ID is compatible with this major revision.
22h
Parameter
Header 3 1st
DWORD
23h
Parameter Table Length (in double words = Dwords = 4 byte units) OPN Dependent 26 =
1Ah (128Mb) 1Ah
1Ah (128Mb)
(256Mb)
26 = 1Ah (256Mb)
24h
25h
26h
Parameter
Header 3 2nd
DWORD
27h
D8h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC parameter byte offset =
10D8h
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
28h
84h
Parameter ID LSB (00h = SFDP 4 Byte Address Instructions Parameter)
29h
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that
recognizes this parameter’s ID is compatible with this major revision.
2Bh
02h
Parameter Table Length (in double words = Dwords = 4 byte units) (2h = 2 Dwords)
2Ch
D0h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) JEDEC parameter byte offset =
10D0h
2Ah
2Dh
2Eh
Parameter
Header 4 1st
DWORD
Parameter
Header 4 2nd
DWORD
2Fh
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
30h
01h
Parameter ID LSB (Cypress Vendor Specific ID-CFI parameter) Legacy Manufacturer ID
01h = AMD / Cypress
31h
01h
Parameter Minor Revision (01h = ID-CFI updated with SFDP Rev B table)
32h
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that
recognizes this parameter’s ID is compatible with this major revision.
Parameter
Header 5 1st
DWORD
33h
Parameter Table Length (in double words = Dwords = 4 byte units) Parameter Table
Length (in double words = Dwords = 4 byte units) CFI starts at 1000h, the final SFDP
parameter (CFI ID = A5) starts at 111Eh (SFDP starting point of 1090h -2hB of CFI
50h (128Mb) 50h parameter header), for a length of 8EhB excluding the CFI A5 parameter.
The final CFI A5 parameter for 128Mb adds an additional B2hB for a total of 8Eh + B2h =
(256Mb)
140hB. 140hB/4 = 50h Dwords
The final CFI A5 parameter for 256Mb adds an additional B2hB for a total of 8Eh + B2h =
140hB. 140hB/4 = 50h Dwords
Document Number: 002-00368 Rev. *M
Page 134 of 158
S25FS128S/S25FS256S
Table 63. SFDP Header (Continued)
SFDP Byte
Address
SFDP Dword
Name
34h
Parameter
Header 5 2nd
DWORD
35h
36h
37h
11.4
Data
Description
00h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) Entry point for ID-CFI parameter
is byte offset = 1000h relative to SFDP location zero.
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
01h
Parameter ID MSB (01h = JEDEC JEP106 Bank Number 1)
Device ID and Common Flash Interface (ID-CFI) Address Map
11.4.1 Field Definitions
Table 64. Manufacturer and Device ID
Byte Address
Data
00h
01h
Description
01h
20h (128 Mb)
02h (256 Mb)
Device ID Most Significant Byte - Memory Interface Type
02h
18h (128 Mb)
19h (256 Mb)
Device ID Least Significant Byte - Density
Manufacturer ID for Cypress
ID-CFI Length - number bytes following. Adding this value to the current
location of 03h gives the address of the last valid location in the ID-CFI
legacy address map. The legacy CFI address map ends with the Primary
Vendor-Specific Extended Query. The original legacy length is maintained
for backward software compatibility. However, the CFI Query
Identification String also includes a pointer to the Alternate
Vendor-Specific Extended Query that contains additional information
related to the FS-S family.
03h
4Dh
04h
00h (Uniform 256-kB physical sectors)
01h (Uniform 64-kB physical sectors)
05h
81h (S25FS-S Family)
06h
xxh
07h
xxh
ASCII characters for Model
Refer to Ordering Information on page 153 for the model number
definitions.
08h
xxh
Reserved
Physical Sector Architecture
The S25FS-S family may be configured with or without 4-kB parameter
sectors in addition to the uniform sectors.
Family ID
09h
xxh
Reserved
0Ah
xxh
Reserved
0Bh
xxh
Reserved
0Ch
xxh
Reserved
0Dh
xxh
Reserved
0Eh
xxh
Reserved
0Fh
xxh
Reserved
Document Number: 002-00368 Rev. *M
Page 135 of 158
S25FS128S/S25FS256S
Table 65. CFI Query Identification String
Byte Address
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
FL-P backward compatible command set ID
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
53h
46h
Alternate OEM Command Set
ASCII characters “FS” for SPI (F) interface, S Technology
19h
1Ah
51h
00h
Address for Alternate OEM Extended Table
Table 66. CFI System Interface String
Byte Address
Data
1Bh
17h
VCC Min. (erase/program): 100 millivolts BCD
1Ch
19h
VCC Max. (erase/program): 100 millivolts BCD
1Dh
00h
VPP Min. voltage (00h = no VPP present)
1Eh
00h
VPP Max. voltage (00h = no VPP present)
1Fh
09h
Typical timeout per single byte program 2N µs
20h
09h
Typical timeout for Min. size Page program 2N µs
(00h = not supported)
21h
08h (4 kB or 64 kB)
0Ah (256 kB)
Typical timeout per individual Sector Erase 2N ms
22h
10h (128 Mb)
11h (256 Mb)
23h
02h
Max. timeout for byte program 2N times typical
24h
02h
Max. timeout for page program 2N times typical
25h
05h (4 kB or 64 kB)
04h (256 kB)
26h
03h
Document Number: 002-00368 Rev. *M
Description
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout per individual Sector Erase 2N times typical
Max. timeout for full chip erase 2N times typical
(00h = not supported)
Page 136 of 158
S25FS128S/S25FS256S
Table 67. Device Geometry Definition for Bottom Boot Initial Delivery State
Byte Address
Data
27h
18h (128 Mb)
19h (256 Mb)
28h
02h
29h
01h
2Ah
08h
2Bh
00h
2Ch
03h
2Dh
07h
2Eh
00h
2Fh
10h
30h
00h
31h
00h
32h
00h
33h
80h
34h
00h (128 Mb)
00h (256 Mb)
35h
FEh
36h
00h (128 Mb)
01h (256 Mb)
37h
00h
38h
01h (128 Mb)
01h (256 Mb)
39h thru 3Fh
FFh
Description
Device Size = 2N bytes
Flash Device Interface Description;
0000h = x8 only
0001h = x16 only
0002h = x8/x16 capable
0003h = x32 only
0004h = Single I/O SPI, 3-byte address
0005h = Multi I/O SPI, 3-byte address
0102h = Multi I/O SPI, 3- or 4-byte address
Max. number of bytes in multi-byte write = 2N
0000 = not supported
0008h = 256B page
Number of Erase Block Regions within device
1 = Uniform Device, >1 = Boot Device
Erase Block Region 1 Information (refer to JEDEC JEP137)
8 sectors = 8-1 = 0007h
4-kB sectors = 256 bytes x 0010h
Erase Block Region 2 Information (refer to JEDEC JEP137)
128 Mb and 256 Mb:
1 sector = 1-1 = 0000h
32-kB sector = 256 bytes x 0080h
Erase Block Region 3 Information
128 Mb and 256 Mb:
255 sectors = 255-1 = 00FEh (128 Mb)
511 sectors = 511-1 = 01FEh (256 Mb)
64-kB sectors = 0100h x 256 bytes
RFU
Note
85. FS-S devices are user configurable to have either a hybrid sector architecture (with eight 4-kB sectors and all remaining sectors are uniform 64 kB or 256 kB) or a
uniform sector architecture with all sectors uniform 64 kB or 256 kB. FS-S devices are also user configurable to have the 4-kB parameter sectors at the top of memory
address space. The CFI geometry information of the above table is relevant only to the initial delivery state. All devices are initially shipped from Cypress with the
hybrid sector architecture with the 4-kB sectors located at the bottom of the array address map. However, the device configuration TBPARM bit CR1NV[2] may be
programed to invert the sector map to place the 4-kB sectors at the top of the array address map. The 20h_NV bit (CR3NV[3} may be programmed to remove the
4-kB sectors from the address map. The flash device driver software must examine the TBPARM and 20h_NV bits to determine if the sector map was inverted or
hybrid sectors removed at a later time.
Document Number: 002-00368 Rev. *M
Page 137 of 158
S25FS128S/S25FS256S
Table 68. CFI Primary Vendor-Specific Extended Query
Byte Address
Data
40h
50h
41h
52h
42h
49h
43h
31h
Major version number = 1, ASCII
44h
33h
Minor version number = 3, ASCII
45h
21h
Address Sensitive Unlock (Bits 1-0)
00b = Required, 01b = Not Required
Process Technology (Bits 5-2)
0000b = 0.23 µm Floating Gate
0001b = 0.17 µm Floating Gate
0010b = 0.23 µm MirrorBit
0011b = 0.11 µm Floating Gate
0100b = 0.11 µm MirrorBit
0101b = 0.09 µm MirrorBit
1000b = 0.065 µm MirrorBit
46h
02h
Erase Suspend
0 = Not Supported
1 = Read Only
2 = Read and Program
47h
01h
Sector Protect
00 = Not Supported
X = Number of sectors in group
48h
00h
Temporary Sector Unprotect
00 = Not Supported
01 = Supported
49h
08h
Sector Protect/Unprotect Scheme
04 = High Voltage Method
05 = Software Command Locking Method
08 = Advanced Sector Protection Method
4Ah
00h
Simultaneous Operation
00 = Not Supported
X = Number of Sectors
4Bh
01h
Burst Mode (Synchronous sequential read) support
00 = Not Supported
01 = Supported
4Ch
03h
Page Mode Type, initial delivery configuration, user configurable for 512B page
00 = Not Supported
01 = 4 Word Read Page
02 = 8-Read Word Page
03 = 256-byte Program Page
04 = 512-byte Program Page
4Dh
00h
ACC (Acceleration) Supply Minimum
00 = Not Supported, 100 mV
4Eh
00h
ACC (Acceleration) Supply Maximum
00 = Not Supported, 100 mV
4Fh
07h
WP# Protection
01 = Whole Chip
04 = Uniform Device with Bottom WP Protect
05 = Uniform Device with Top WP Protect
07 = Uniform Device with Top or Bottom Write Protect (user configurable)
50h
01h
Program Suspend
00 = Not Supported
01 = Supported
Document Number: 002-00368 Rev. *M
Description
Query-unique ASCII string “PRI”
Page 138 of 158
S25FS128S/S25FS256S
The Alternate Vendor-Specific Extended Query provides information related to the expanded command set provided by the FS-S
family. The alternate query parameters use a format in which each parameter begins with an identifier byte and a parameter length
byte. Driver software can check each parameter ID and can use the length value to skip to the next parameter if the parameter is not
needed or not recognized by the software.
Table 69. CFI Alternate Vendor-Specific Extended Query Header
Byte Address
Data
51h
41h
Description
52h
4Ch
53h
54h
54h
32h
Major version number = 2, ASCII
55h
30h
Minor version number = 0, ASCII
Query-unique ASCII string “ALT”
Table 70. CFI Alternate Vendor-Specific Extended Query Parameter 0
Parameter Relative
Byte Address Offset
Data
00h
00h
Parameter ID (Ordering Part Number)
01h
10h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
53h
ASCII “S” for manufacturer (Cypress)
03h
32h
04h
35h
05h
46h
06h
53h
07h
31h (128 Mb)
32h (256 Mb)
08h
32h (128 Mb)
35h (256 Mb)
09h
38h (128 Mb)
36h (256 Mb)
0Ah
53h
Description
ASCII “25” for Product Characters (Single Die SPI)
ASCII “FS” for Interface Characters (SPI 1.8 Volt)
ASCII characters for density
ASCII “S” for Technology (65 nm MirrorBit)
0Bh
FFh
0Ch
FFh
0Dh
FFh
0Eh
FFh
0Fh
FFh
Reserved for Future Use
10h
xxh
11h
xxh
ASCII characters for Model. Refer to Ordering Information on page 153 for the model number
definitions.
Document Number: 002-00368 Rev. *M
Reserved for Future Use
Reserved for Future Use
Page 139 of 158
S25FS128S/S25FS256S
Table 71. Alternate Vendor-Specific Extended Query Parameter 80h Address Options
Parameter Relative
Byte Address Offset
Data
00h
80h
Parameter ID (Ordering Part Number)
01h
01h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
EBh
Bits 7:5 - Reserved = 111b
Bit 4 - Address Length Bit in CR2V[7] - Yes = 0b
Bit 3 - AutoBoot support - No = 1b
Bit 2 - 4 byte address instructions supported - Yes = 0b
Bit 1 - Bank address + 3-byte address instructions supported - No = 1b
Bit 0 - 3-byte address instructions supported - No = 1b
02h
Description
Table 72. CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands
Parameter Relative
Byte Address Offset
Data
00h
84h
Parameter ID (Suspend Commands)
01h
08h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
75h
Program suspend instruction code
Description
03h
28h
Program suspend latency maximum (µs)
04h
7Ah
Program resume instruction code
05h
64h
Program resume to next suspend typical (µs)
06h
75h
Erase suspend instruction code
07h
28h
Erase suspend latency maximum (µs)
08h
7Ah
Erase resume instruction code
09h
64h
Erase resume to next suspend typical (µs)
Table 73. CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protectio
Parameter Relative
Byte Address Offset
Data
00h
88h
Parameter ID (Data Protection)
01h
04h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
0Ah
OTP size 2N bytes, FFh = not supported
03h
01h
OTP address map format,
01h = FL-S and FS-S format
FFh = not supported
04h
xxh
Block Protect Type, model dependent
00h = FL-P, FL-S, FS-S
FFh = not supported
05h
xxh
Advanced Sector Protection type, model dependent
01h = FL-S and FS-S ASP.
Document Number: 002-00368 Rev. *M
Description
Page 140 of 158
S25FS128S/S25FS256S
Table 74. CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing
Parameter Relative
Byte Address Offset
Data
00h
8Ch
Parameter ID (Reset Timing)
01h
06h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
96h
POR maximum value
03h
01h
POR maximum exponent 2N µs
04h
23h
Hardware Reset maximum value, FFh = not supported (the initial delivery state has hardware
reset disabled but it may be enabled by the user at a later time)
05h
00h
Hardware Reset maximum exponent 2N µs
Description
06h
23h
Software Reset maximum value, FFh = not supported
07h
00h
Software Reset maximum exponent 2N µs
Table 75. CFI Alternate Vendor-Specific Extended Query Parameter 94h ECC
Parameter Relative
Byte Address Offset
Data
00h
94h
Parameter ID (ECC)
01h
01h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
10h
ECC unit size byte, FFh = ECC disabled
Description
Table 76. CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU
Parameter Relative
Byte Address Offset
Data
00h
F0h
Parameter ID (RFU)
01h
09h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
FFh
RFU
...
FFh
RFU
10h
FFh
RFU
Description
This parameter type (Parameter ID F0h) may appear multiple times and have a different length each time. The parameter is used to
reserve space in the ID-CFI map or to force space (pad) to align a following parameter to a required boundary.
Document Number: 002-00368 Rev. *M
Page 141 of 158
S25FS128S/S25FS256S
Table 77. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4 Byte Address Instructions Parameter
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
SFDP
Relative
Dword Name
Data
00h
--
N/A
A5h
01h
--
02h
00h
03h
01h
N/A
FFh
04h
02h
B2h
(FSxxxSAG)
05h
03h
FFh
06h
04h
07h
05h
08h
06h
09h
07h
0Ah
08h
0Bh
09h
0Ch
0Ah
0Dh
CFI Parameter ID (JEDEC SFDP)
CFI Parameter Length (The number of following bytes in this parameter. Adding
this value to the current location value +1 = the first byte of the next parameter).
B0h (128Mb)
OPN dependent:
B0h (256Mb)
18Dw + 26Dw = 44Dw *4B = 176B = B0h B (128Mb)
B0h (256Mb)
E7h
JEDEC Basic
Flash
Parameter
Dword-1
Description
Start of SFDP JEDEC parameter, located at 1090h in the overall SFDP address
space.
Bits 7:5 = unused = 111b
Bit 4:3 = 06h is status register write instruction & status register is default
non-volatile= 00b
Bit 2 = Program Buffer > 64Bytes = 1
Bits 1:0 = Uniform 4KB erase unavailable = 11b
Bits 15:8 = Uniform 4KB erase opcode = not supported = FFh
Bit 23 = Unused = 1b
Bit 22 = Supports Quad Out Read = No = 0b
Bit 21 = Supports Quad I/O Read = Yes =1b
Bit 20 = Supports Dual I/O Read = Yes = 1b
Bit19 = Supports DDR 0= No, 1 = Yes; FS-SAG = 0b, FS-SDS = 1b
Bit 18:17 = Number of Address Bytes, 3 or 4 = 01b
Bit 16 = Supports Dual Out Read = No = 0b
Bits 31:24 = Unused = FFh
FFh
JEDEC Basic
Flash
Parameter
Dword-2
FFh
FFh
Density in bits, zero based
07h (128Mb)
0Fh (256Mb)
48h
Bits 7:5 = number of Quad I/O (1-4-4) Mode cycles = 010b Bits
4:0 = number of Quad I/O Dummy cycles = 01000b (Initial Delivery State)
EBh
Quad I/O instruction code
FFh
Bits 23:21 = number of Quad Out (1-1-4) Mode cycles = 111b
Bits 20:16 = number of Quad Out Dummy cycles = 11111b
0Bh
FFh
Quad Out instruction code
0Eh
0Ch
FFh
Bits 7:5 = number of Dual Out (1-1-2) Mode cycles = 111b
Bits 4:0 = number of Dual Out Dummy cycles = 11111b
0Fh
0Dh
FFh
Dual Out instruction code
10h
0Eh
88h
Bits 23:21 = number of Dual I/O (1-2-2) Mode cycles = 100b
Bits 20:16 = number of Dual I/O Dummy cycles = 01000b (Initial Delivery State)
11h
0Fh
12h
10h
13h
11h
14h
12h
15h
13h
JEDEC Basic
Flash
Parameter
Dword-3
JEDEC Basic
Flash
Parameter
Dword-4
JEDEC Basic
Flash
Parameter
Dword-5
Document Number: 002-00368 Rev. *M
BBh
Dual I/O instruction code
FEh
Bits 7:5 RFU = 111b
Bit 4 = QPI supported = Yes = 1b
Bits 3:1 RFU = 111b
Bit 0 = Dual All not supported = 0b
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:16 = RFU = FFh
FFh
Bits 31:24 = RFU = FFh
Page 142 of 158
S25FS128S/S25FS256S
Table 77. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4 Byte Address Instructions Parameter (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
16h
14h
17h
15h
18h
16h
19h
17h
1Ah
18h
1Bh
19h
1Ch
1Ah
SFDP
Relative
Dword Name
JEDEC Basic
Flash
Parameter
Dword-6
JEDEC Basic
Flash
Parameter
Dword-7
Data
Description
FFh
Bits 7:0 = RFU = FFh
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
FFh
Dual All instruction code
FFh
Bits 7:0 = RFU = FFh
FFh
Bits 15:8 = RFU = FFh
48h
Bits 23:21 = number of QPI Mode cycles = 010b
Bits 20:16 = number of QPI Dummy cycles = 01000b
1Dh
1Bh
EBh
QPI mode Quad I/O (4-4-4) instruction code
1Eh
1Ch
0Ch
Erase type 1 size 2N Bytes = 4KB = 0Ch for Hybrid (Initial Delivery State)
1Fh
1Dh
20h
1Eh
21h
1Fh
22h
20h
23h
21h
24h
22h
25h
23h
26h
24h
27h
25h
72h
28h
26h
1Dh
29h
27h
JEDEC Basic
Flash
Parameter
Dword-8
JEDEC Basic
Flash
Parameter
Dword-9
JEDEC Basic
Flash
Parameter
Dword-10
Document Number: 002-00368 Rev. *M
20h
Erase type 1 instruction
10h
Erase type 2 size 2N Bytes = 64KB = 10h
D8h
Erase type 2 instruction
12h
Erase type 3 size 2N Bytes = 256KB = 12h
D8h
Erase type 3 instruction
00h
Erase type 4 size 2N Bytes = not supported = 00h
FFh
Erase type 4 instruction = not supported = FFh
E2h
Bits 31:30 = Erase type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:
128 ms, 11b: 1 s) = 1S = 11b (RFU)
Bits 29:25 = Erase type 4 Erase, Typical time count = 11111b ( RFU)
Bits 24:23 = Erase type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:
128 ms, 11b: 1 s) = 128mS = 10b
Bits 22:18 = Erase type 3 Erase, Typical time count = 00111b (typ erase time =
count +1 * units = 8*128mS = 930 ms)
Bits 17:16 = Erase type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:
128 ms, 11b: 1 s) = 16mS = 01b
Bits 15:11 = Erase type 2 Erase, Typical time count = 01110b (typ erase time =
count +1 * units = 15*16mS = 240mS)
Bits 10:9 = Erase type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:
128 ms, 11b: 1 s) = 16mS = 01b
Bits 8:4 = Erase type 1 Erase, Typical time count = 01110b (typ erase time =
count +1 * units = 15*16mS = 240mS)
Bits 3:0 = Multiplier from typical erase time to maximum erase time = 2*(N+1),
N=2h
Binary Fields: 11-11111-10-00111-01-01110-01-01110-0010 Nibble Format:
1111_1111_0001_1101_0111_0010_1110_0010 Hex Format: FF_11_42_82
FFh
Page 143 of 158
S25FS128S/S25FS256S
Table 77. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4 Byte Address Instructions Parameter (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
2Ah
28h
2Bh
29h
2Ch
2Ah
2Dh
2Bh
SFDP
Relative
Dword Name
Data
Description
91h
Bit 31 Reserved = 1b
Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s,
11b: 64 s) =
128Mb = 4s = 10b;
07h
256Mb = 4s = 10b
Bits 28:24 = Chip Erase, Typical time count, (count+1)*units,
128Mb = 4s = 01110b = 14+1*4 = 60s;
256Mb = 11101 = 29+1*4 = 120s
Bits 23 = Byte Program Typical time, additional byte units (0b:1uS, 1b:8uS) =
1uS = 0b
Bits 22:19 = Byte Program Typical time, additional byte count, (count+1)*units,
count = 0000b, ( typ Program time = count +1 * units = 1*1uS = 1uS
Bits 18 = Byte Program Typical time, first byte units (0b:1uS, 1b:8uS) = 8uS = 1b
Bits 17:14 = Byte Program Typical time, first byte count, (count+1)*units, count =
1100b, ( typ Program time = count +1 * units = 13*8uS = 104uS
Bits 13 = Page Program Typical time units (0b:8uS, 1b:64uS) = 64uS = 1b
C7h (128Mb)
Bits 12:8 = Page Program Typical time count, (count+1)*units, count = 00110b, (
DDh (256Mb)
typ Program time = count +1 * units = 7*64uS = 448uS)
Bits 7:4 = Page size 2N, N=9h, = 512B page
Bits 3:0 = Multiplier from typical time to maximum for Page or Byte program =
2*(N+1), N=1h = 4x multiplier
26h
JEDEC Basic
Flash
Parameter
Dword-11
128Mb Binary Fields: 1-10-01110-0-0000-1-1100-1-00110-1001-0001 Nibble
Format: 1100_1110_0000_0111_0010_0110_1001_0001 Hex Format:
C7_07_26_91
256Mb Binary Fields: 1-10-11101-0-0000-1-1100-1-00110-1001-0001 Nibble
Format: 1101_1101_0000_0111_0010_0110_1001_0001 Hex Format:
DD_07_26_91
2Eh
2Ch
ECh
2Fh
2Dh
83h
30h
2Eh
18h
31h
2Fh
JEDEC Basic
Flash
Parameter
Dword-12
44h
Bit 31 = Suspend and Resume supported = 0b Bits
30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us,
10b: 8us, 11b: 64us) = 8us= 10b
Bits 28:24 = Suspend in-progress erase max latency count = 00100b, max erase
suspend latency = count +1 * units = 5*8uS = 40uS
Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = count
+1 * 64us = 2 * 64us = 128us
Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b:
1us, 10b: 8us, 11b: 64us) = 8us= 10b Bits
17:13 = Suspend in-progress program max latency count = 00100b, max erase
suspend latency = count +1 * units = 5*8uS = 40uS
Bits 12:9 = Program resume to suspend interval count = 0001b, interval = count
+1 * 64us = 2 * 64us = 128us Bit 8 = RFU = 1b
Bits 7:4 = Prohibited operations during erase suspend = xxx0b: May not initiate a
new erase anywhere (erase nesting not permitted) + xx1xb: May not initiate a
page program in the erase suspended sector size + x1xxb: May not initiate a
read in the erase suspended sector size + 1xxxb: The erase and program
restrictions in bits 5:4 are sufficient = 1110b
Bits 3:0 = Prohibited Operations During Program Suspend = xxx0b: May not
initiate a new erase anywhere (erase nesting not permitted) + xx0xb: May not
initiate a new page program anywhere (program nesting not permitted) + x1xxb:
May not initiate a read in the program suspended page size + 1xxxb: The erase
and program restrictions in bits 1:0 are sufficient = 1100b
Binary Fields: 0-10-00100-0001-10-00100-0001-1-1110-1100 Nibble Format:
0100_0100_0001_1000_1000_0011_1110_1100 Hex Format: 44_18_83_EC
Document Number: 002-00368 Rev. *M
Page 144 of 158
S25FS128S/S25FS256S
Table 77. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4 Byte Address Instructions Parameter (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
32h
30h
33h
31h
34h
32h
35h
33h
SFDP
Relative
Dword Name
JEDEC Basic
Flash
Parameter
Dword-13
Data
8Ah
85h
7Ah
75h
36h
34h
F7h
37h
35h
BDh
38h
36h
D5h
39h
37h
JEDEC Basic
Flash
Parameter
Dword-14
5Ch
3Ah
38h
8Ch
3Bh
39h
F6h
3Ch
3Ah
5Dh
3Dh
3Bh
JEDEC Basic
Flash
Parameter
Dword-15
FFh
Description
Bits 31:24 = Erase Suspend Instruction = 75h
Bits 23:16 = Erase Resume Instruction = 7Ah
Bits 15:8 = Program Suspend Instruction = 85h
Bits 7:0 = Program Resume Instruction = 8Ah
Bit 31 = Deep Power Down Supported = supported = 0
Bits 30:23 = Enter Deep Power Down Instruction = B9h
Bits 22:15 = Exit Deep Power Down Instruction = ABh
Bits 14:13 = Exit Deep Power Down to next operation delay units = (00b: 128ns,
01b: 1us, 10b: 8us, 11b: 64us) = 1us = 01b
Bits 12:8 = Exit Deep Power Down to next operation delay count = 11101b, Exit
Deep Power Down to next operation delay = (count+1)*units = 29+1 *1us = 30us
Bits 7:4 = RFU = Fh
Bit 3:2 = Status Register Polling Device Busy = 01b: Legacy status polling
supported = Use legacy polling by reading the Status Register with 05h
instruction and checking WIP bit[0] (0=ready; 1=busy). = 01b
Bits 1:0 = RFU = 11b
Binary Fields: 0-10111001-10101011-01-11101-1111-01-11 Nibble Format:
0101_1100_1101_0101_1011_1101_1111_0111 Hex Format: 5C_D5_BD_F7
Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP Disable = not supported = 0b
Bits 22:20 = Quad Enable Requirements = 101b: QE is bit 1 of the status register
2. Status register 1 is read using Read Status instruction 05h. Status register 2 is
read using instruction 35h. QE is set via Write Status instruction 01h with two
data bytes where bit 1 of the second byte is one. It is cleared via Write Status
with two data bytes where bit 1 of the second byte is zero.
Bits 19:16 0-4-4 Mode Entry Method = xxx1b: Mode Bits[7:0] = A5h Note: QE
must be set prior to using this mode + x1xxb: Mode Bit[7:0]=Axh + 1xxxb: RFU =
1101b Bits 15:10 0-4-4 Mode Exit Method = xx_xxx1b: Mode Bits[7:0] = 00h will
terminate this mode at the end of the current read operation + xx_1xxxb: Input
Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate the mode prior
to the next read operation. + x1_xxxxb: Mode Bit[7:0] != Axh + 1x_x1xx: RFU =
11_1101
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences = x_1xxxb: device uses a
read-modify-write sequence of operations: read configuration using instruction
65h followed by address 800003h, set bit 6, write configuration using instruction
71h followed by address 800003h. This configuration is volatile. = 01000b
Bits 3:0 = 4-4-4 mode disable sequences = x1xxb: device uses a
read-modify-write sequence of operations: read configuration instruction 65h
followed by address 800003h, clear bit 6, write configuration using instruction
71h followed by address 800003h.. This configuration is volatile. + 1xxxb: issue
the Soft Reset 66/99 sequence = 1100b
Binary Fields: 11111111-0-101-1101-111101-1-01000-1100 Nibble Format:
1111_1111_0101_1101_1111_0110_1000-1100 Hex Format: FF_5D_F6_8C
Document Number: 002-00368 Rev. *M
Page 145 of 158
S25FS128S/S25FS256S
Table 77. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4 Byte Address Instructions Parameter (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
3Eh
3Fh
40h
41h
SFDP
Relative
Dword Name
Data
Description
3Ch
F0h
3Dh
30h
3Eh
F8h
Bits 31:24 = Enter 4-Byte Addressing = xxxx_xxx1b: issue instruction B7h
(preceding write enable not required) + xx1x_xxxxb: Supports dedicated 4-Byte
address instruction set. Consult vendor data sheet for the instruction set
definition. + 1xxx_xxxxb: Reserved = 10100001b
Bits 23:14 = Exit 4-Byte Addressing = xx_xx1x_xxxxb: Hardware reset +
xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD) + xx_1xxx_xxxxb:
Power cycle + x1_xxxx_xxxxb: Reserved + 1x_xxxx_xxxxb: Reserved =
11_1110_0000b
Bits 13:8 = Soft Reset and Rescue Sequence Support = x1_xxxxb: issue reset
enable instruction 66h, then issue reset instruction 99h. The reset enable, reset
sequence may be issued on 1, 2, or 4 wires depending on the device operating
mode. + 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences
above if the device may be operating in this mode. = 110000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for
Status Register 1 = + xx1_xxxxb: Status Register 1 contains a mix of volatile and
non-volatile bits. The 06h instruction is used to enable writing of the register. +
x1x_xxxxb: Reserved + 1xx_xxxxb: Reserved = 1110000b
3Fh
JEDEC Basic
Flash
Parameter
Dword-16
A1h
Binary Fields: 10100001-1111100000-110000-1-1110000 Nibble Format:
1010_0001_1111_1000_0011_0000_1111_0000 Hex Format: A1_F8_30_F0
42h
40h
6Bh
43h
41h
8Eh
44h
42h
FFh
45h
43h
46h
44h
47h
45h
48h
46h
49h
47h
JEDEC 4 Byte
Address
Instructions
Parameter
Dword-1
JEDEC 4 Byte
Address
Instructions
Parameter
Dword-2
Document Number: 002-00368 Rev. *M
FFh
21h
DCh
DCh
FFh
Supported = 1, Not Supported = 0
Bits 31:20 = RFU = FFFh
Bit 19 = Support for non-volatile individual sector lock write command,
Instruction=E3h = 1
Bit 18 = Support for non-volatile individual sector lock read command,
Instruction=E2h = 1
Bit 17 = Support for volatile individual sector lock Write command,
Instruction=E1h = 1
Bit 16 = Support for volatile individual sector lock Read command,
Instruction=E0h = 1
Bit 15 = Support for (1-4-4) DTR_Read Command, Instruction = EEh = 1
Bit 14 = Support for (1-2-2) DTR_Read Command, Instruction = BEh = 0
Bit 13 = Support for (1-1-1) DTR_Read Command, Instruction = 0Eh = 0
Bit 12 = Support for Erase Command – Type 4 = 0
Bit 11 = Support for Erase Command – Type 3 = 1
Bit 10 = Support for Erase Command – Type 2 = 1
Bit 9 = Support for Erase Command – Type 1 = 1
Bit 8 = Support for (1-4-4) Page Program Command, Instruction = 3Eh =0
Bit 7 = Support for (1-1-4) Page Program Command, Instruction = 34h = 0
Bit 6 = Support for (1-1-1) Page Program Command, Instruction = 12h = 1
Bit 5 = Support for (1-4-4) FAST_READ Command, Instruction = ECh = 1
Bit 4 = Support for (1-1-4) FAST_READ Command, Instruction = 6Ch = 0
Bit 3 = Support for (1-2-2) FAST_READ Command, Instruction = BCh = 1
Bit 2 = Support for (1-1-2) FAST_READ Command, Instruction = 3Ch = 0
Bit 1 = Support for (1-1-1) FAST_READ Command, Instruction = 0Ch = 1
Bit 0 = Support for (1-1-1) READ Command, Instruction=13h = 1
Bits 31:24 = FFh = Instruction for Erase Type 4: RFU
Bits 23:16 = DCh = Instruction for Erase Type 3
Bits 15:8 = DCh = Instruction for Erase Type 2
Bits 7:0 = 21h = Instruction for Erase Type 1
Page 146 of 158
S25FS128S/S25FS256S
Table 78. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 128Mb and 256Mb
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
4Ah
48h
4Bh
49h
4Ch
4Ah
4Dh
4Bh
4Eh
4Ch
4Fh
4Dh
50h
4Eh
51h
4Fh
52h
50h
53h
51h
54h
52h
55h
53h
56h
54h
57h
55h
58h
56h
59h
57h
5Ah
58h
5Bh
59h
5Ch
5Ah
5Dh
5Bh
5Eh
5Ch
5Fh
5Dh
60h
5Eh
61h
5Fh
SFDP Dword
Name
JEDEC Sector
Map
Parameter
Dword-1
Config.
Detect-1
JEDEC Sector
Map
Parameter
Dword-2
Config.
Detect-1
Data
Description
FCh
Bits 31:24 = Read data mask = 0000_1000b: Select bit 3 of the data byte for
20h_NV value 0= Hybrid map with 4KB parameter sectors 1= Uniform map
Bits 23:22 = Configuration detection command address length = 11b: Variable
length
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 1111b: variable latency
Bits 15:8 = Configuration detection instruction = 65h: Read any register
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
Bit 0 = not the end descriptor = 0
65h
FFh
08h
04h
00h
00h
00h
FCh
65h
JEDEC Sector
Map
Parameter
Dword-3
Config.
Detect-2
FFh
JEDEC Sector
Map
Parameter
Dword-4
Config.
Detect-2
02h
04h
00h
00h
JEDEC Sector
Map
Parameter
Dword-6
Config.
Detect-3
Document Number: 002-00368 Rev. *M
Bits 31:24 = Read data mask = 0000_0100b: Select bit 2 of the data byte for
TBPARM_O value
0= 4KB parameter sectors at bottom
1= 4KB parameter sectors at top
Bits 23:22 = Configuration detection command address length = 11b: Variable
length
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 1111b: variable latency
Bits 15:8 = Configuration detection instruction = 65h: Read any register
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
Bit 0 = not the end descriptor = 0
Bits 31:0 = Sector map configuration detection command address =
00_00_00_02h: address of CR1NV
00h
FDh
JEDEC Sector
Map
Parameter
Dword-5
Config.
Detect-3
Bits 31:0 = Sector map configuration detection command address =
00_00_00_04h: address of CR3NV
65h
FFh
02h
Bits 31:24 = Read data mask = 0000_0010b: Select bit 1 of the data byte for
D8h_NV value 0= 64KB uniform sectors 1= 256KB uniform sectors
Bits 23:22 = Configuration detection command address length = 11b: Variable
length
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 1111b: variable latency
Bits 15:8 = Configuration detection instruction = 65h: Read any register
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
Bit 0 = The end descriptor = 1
04h
00h
00h
Bits 31:0 = Sector map configuration detection command address =
00_00_00_04h: address of CR3NV
00h
Page 147 of 158
S25FS128S/S25FS256S
Table 78. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 128Mb and 256Mb (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
SFDP Dword
Name
Data
FEh
62h
60h
63h
61h
64h
62h
65h
63h
66h
64h
F1h
67h
65h
7Fh
68h
66h
69h
67h
JEDEC Sector
Map
Parameter
Dword-7
Config-0
Header
JEDEC Sector
Map
Parameter
Dword-8
Config-0
Region-0
00h
02h
FFh
00h
00h
6Ah
68h
F2h
6Bh
69h
7Fh
6Ch
6Ah
6Dh
6Bh
6Eh
6Ch
F2h
6Fh
6Dh
FFh
70h
6Eh
71h
6Fh
72h
70h
73h
71h
74h
72h
75h
73h
JEDEC Sector
Map
Parameter
Dword-9
Config-0
Region-1
JEDEC Sector
Map
Parameter
Dword-10
Config-0
Region-2
JEDEC Sector
Map
Parameter
Dword-11
Config-2
Header
Document Number: 002-00368 Rev. *M
00h
00h
FEh
00h (128Mb)
01h (256Mb)
Description
Bits 31:24 = RFU = FFh
Bits 23:16 = Region count (Dwords -1) = 02h: Three regions
Bits 15:8 = Configuration ID = 00h: 4KB sectors at bottom with remainder 64KB
sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = not the end descriptor = 0
Bits 31:8 = Region size = 00007Fh: Region size as count-1 of 256 Byte units = 8
x 4KB sectors = 32KB Count = 32KB/256 = 128, value = count -1 = 128 -1 = 127
= 7Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 4KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 4KB sector region
Bit 0 = Erase Type 1 support = 1b ---Erase Type 1 is 4KB erase and is supported
in the 4KB sector region
Bits 31:8 = Region size = 00007Fh: Region size as count-1 of 256 Byte units = 1
x 32KB sectors = 32KB Count = 32KB/256 = 128, value = count -1 = 128 -1 =
127 = 7Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 32KB sector region
Bit 1 = Erase Type 2 support = 1b ---Erase Type 2 is 64KB erase and is
supported in the 32KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 32KB sector region
Bits 31:8 = 128Mb device Region size = 00FEFFh:
Region size as count-1 of 256 Byte units = 255 x 64KB sectors = 16320KB
Count = 16320KB/256 = 65280, value = count -1 = 65280 -1 = 65279 = FEFFh
Bits 31:8 = 256Mb device Region size = 01FEFFh: Region size as count-1 of
256 Byte units = 511 x 64KB sectors = 32704KB Count = 32704KB/256 =
130816, value = count -1 = 130816 -1 = 130815 = 1FEFFh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 64KB sector region
Bit 1 = Erase Type 2 support = 1b ---Erase Type 2 is 64KB erase and is
supported in the 64KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 64KB sector region
FEh
02h
02h
FFh
Bits 31:24 = RFU = FFh Bits 23:16 = Region count (Dwords -1) = 02h: Three
regions Bits 15:8 = Configuration ID = 02h: 4KB sectors at top with remainder
64KB sectors Bits 7:2 = RFU = 111111b Bit 1 = Map Descriptor = 1 Bit 0 = not the
end descriptor = 0
Page 148 of 158
S25FS128S/S25FS256S
Table 78. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 128Mb and 256Mb (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
SFDP Dword
Name
Data
Description
Bits 31:8 = 128Mb device Region size = 00FEFFh: Region size as count-1 of
256 Byte units = 255 x 64KB sectors = 16320KB Count = 16320KB/256 = 65280,
value = count -1 = 65280 -1 = 65279 = FEFFh
Bits 31:8 = 256Mb device Region size = 01FEFFh: Region size as count-1 of
256 Byte units = 511 x 64KB sectors = 32704KB Count = 32704KB/256 =
130816, value = count -1 = 130816 -1 = 130815 = 1FEFFh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 64KB sector region
Bit 1 = Erase Type 2 support = 1b ---Erase Type 2 is 64KB erase and is
supported in the 64KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 64KB sector region
76h
74h
F2h
77h
75h
FFh
78h
76h
79h
77h
7Ah
78h
7Bh
79h
7Ch
7Ah
7Dh
7Bh
7Eh
7C
7Fh
7D
80h
7E
81h
7F
82h
80h
83h
81h
84h
82h
85h
83h
86h
84h
87h
85h
88h
86h
89h
87h
JEDEC Sector
Map
Parameter
Dword-12
Config-2
Region-0
FEh
00h (128Mb)
01h (256Mb)
F2h
JEDEC Sector
Map
Parameter
Dword-13
Config-2
Region-1
7Fh
00h
00h
F1h
JEDEC Sector
Map
Parameter
Dword-14
Config-2
Region-2
JEDEC Sector
Map
Parameter
Dword-15
Config-1
Header
7Fh
00h
00h
FEh
01h
02h
FFh
F1h
JEDEC Sector
Map
Parameter
Dword-16
Config-1
Region-0
Document Number: 002-00368 Rev. *M
7Fh
00h
00h
Bits 31:8 = Region size = 00007Fh:
Region size as count-1 of 256 Byte units = 1 x 32KB sectors = 32KB
Count = 32KB/256 = 128, value = count -1 = 128 -1 = 127 = 7Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 32KB sector region
Bit 1 = Erase Type 2 support = 1b ---Erase Type 2 is 64KB erase and is
supported in the 32KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 32KB sector region
Bits 31:8 = Region size = 00007Fh:
Region size as count-1 of 256 Byte units = 8 x 4KB sectors = 32KB
Count = 32KB/256 = 128, value = count -1 = 128 -1 = 127 = 7Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 4KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 4KB sector region
Bit 0 = Erase Type 1 support = 1b ---Erase Type 1 is 4KB erase and is supported
in the 4KB sector region
Bits 31:24 = RFU = FFh Bits 23:16 = Region count (Dwords -1) = 02h: Three
regions
Bits 15:8 = Configuration ID = 01h: 4KB sectors at bottom with remainder 256KB
sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = not the end descriptor = 0
Bits 31:8 = Region size = 00007Fh:
Region size as count-1 of 256 Byte units = 8 x 4KB sectors = 32KB
Count = 32KB/256 = 128, value = count -1 = 128 -1 = 127 = 7Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b --- Erase Type 3 is 256KB erase and is
supported in the 4KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 4KB sector region
Bit 0 = Erase Type 1 support = 1b ---Erase Type 1 is 4KB erase and is supported
in the 4KB sector region
Page 149 of 158
S25FS128S/S25FS256S
Table 78. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 128Mb and 256Mb (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
SFDP Dword
Name
Data
Description
Bits 31:8 = Region size = 00037Fh:
Region size as count-1 of 256 Byte units = 1 x 224KB sectors = 224KB Count =
224KB/256 = 896, value = count -1 = 896 -1 = 895 = 37Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b ---Erase Type 3 is 256KB erase and is
supported in the 32KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 32KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 32KB sector region
8Ah
88h
F4h
8Bh
89h
7Fh
8Ch
8Ah
8Dh
8Bh
8Eh
8Ch
F4h
8Fh
8Dh
FFh
90h
8Eh
91h
8F
92h
90h
93h
91h
94h
92h
95h
93h
JEDEC Sector
Map
Parameter
Dword-17
Config-1
Region-1
03h
00h
FBh
JEDEC Sector
Map
Parameter
Dword-18
Config-1
Region-2
JEDEC Sector
Map
Parameter
Dword-19
Config-3
Header
00h (128Mb)
01h (256Mb)
FEh
03h
02h
FFh
96h
94h
F4h
97h
95h
FFh
98h
96h
99h
97h
9Ah
98h
9Bh
99h
9Ch
9Ah
9Dh
9Bh
JEDEC Sector
Map
Parameter
Dword-20
Config-3
Region-0
FBh
00h (128Mb)
01h (256Mb)
F4h
JEDEC Sector
Map
Parameter
Dword-21
Config-3
Region-1
Document Number: 002-00368 Rev. *M
7Fh
03h
00h
Bits 31:8 = 128Mb device Region size = 00FBFFh:
Region size as count-1 of 256 Byte units = 63 x 256KB sectors = 16128KB
Count = 16128KB/256 = 64512, value = count -1 = 64512 -1 = 64511 = FBFFh
Bits 31:8 = 256Mb device Region size = 01FBFFh:
Region size as count-1 of 256 Byte units = 127 x 256KB sectors = 32512KB
Count = 32512KB/256 = 130048, value = count -1 = 130048 -1 = 130047 =
1FBFFh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b ---Erase Type 3 is 256KB erase and is
supported in the 64KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 64KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 64KB sector region
Bits 31:24 = RFU = FFh
Bits 23:16 = Region count (Dwords -1) = 02h: Three regions
Bits 15:8 = Configuration ID = 03h: 4KB sectors at top with remainder 256KB
sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = not the end descriptor = 0
Bits 31:8 = 128Mb device Region size = 00FBFFh:
Region size as count-1 of 256 Byte units = 63 x 256KB sectors = 16128KB
Count = 16128KB/256 = 64512, value = count -1 = 64512 -1 = 64511 = FBFFh
Bits 31:8 = 256Mb device Region size = 01FBFFh: Region size as count-1 of
256 Byte units = 127 x 256KB sectors = 32512KB Count = 32512KB/256 =
130048, value = count -1 = 130048 -1 = 130047 = 1FBFFh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b ---Erase Type 3 is 256KB erase and is
supported in the 256KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 256KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 256KB sector region
Bits 31:8 = Region size = 00037Fh:
Region size as count-1 of 256 Byte units = 1 x 224KB sectors = 224KB Count =
224KB/256 = 896, value = count -1 = 896 -1 = 895 = 37Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b ---Erase Type 3 is 256KB erase and is
supported in the 224KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 224KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 224KB sector region
Page 150 of 158
S25FS128S/S25FS256S
Table 78. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 128Mb and 256Mb (Continued)
CFI Parameter
Relative Byte
Address
Offset
SFDP
Parameter
Relative Byte
Address
Offset
9Eh
9Fh
A0h
9Eh
A1h
9Fh
A2h
A0h
A3h
A1h
A4h
A2h
A5h
A3h
A6h
A4h
F2h
A7h
A5h
FFh
A8h
A6h
FFh
SFDP Dword
Name
Data
Description
9Ch
F1h
9Dh
7Fh
Bits 31:8 = Region size = 00007Fh:
Region size as count-1 of 256 Byte units = 8 x 4KB sectors = 32KB
Count = 32KB/256 = 128, value = count -1 = 128 -1 = 127 = 7Fh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 4KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 4KB sector region
Bit 0 = Erase Type 1 support = 1b ---Erase Type 1 is 4KB erase and is supported
in the 4KB sector region
A9h
A7h
AAh
A8h
JEDEC Sector
Map
Parameter
Dword-22
Config-3
Region-2
JEDEC Sector
Map
Parameter
Dword-23
Config-4
Header
JEDEC Sector
Map
Parameter
Dword-24
Config-4
Region-0
JEDEC Sector
Map
Parameter
Dword-25
Config-5
Header
00h
00h
FEh
04h
00h
FFh
00h (128Mb)
01h (256Mb)
FFh
ABh
A9h
ACh
AAh
ADh
ABh
AEh
ACh
F4h
AFh
ADh
FFh
B0h
AEh
B1h
AFh
05h
00h
FFh
FFh
JEDEC Sector
Map
Parameter
Dword-26
Config-5
Region-0
Document Number: 002-00368 Rev. *M
00h (128Mb)
01h (256Mb)
Bits 31:24 = RFU = FFh
Bits 23:16 = Region count (Dwords -1) = 00h: One region
Bits 15:8 = Configuration ID = 04h: Uniform 64KB sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = not the end descriptor = 0
Bits 31:8 = 128Mb device
Region size = 00FFFFh: Region size as count-1 of 256 Byte units = 256 x 64KB
sectors = 16MB
Count = 16MB/256 = 65536, value = count -1 = 65536 -1 = 65535 = FFFFh Bits
31:8 = 256Mb device Region size = 01FFFFh: Region size as count-1 of 256
Byte units = 512 x 64KB sectors = 32MB Count = 32MB/256 = 131072, value =
count -1 = 131072 -1 = 131071 = 1FFFFh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b ---Erase Type 3 is 256KB erase and is not
supported in the 64KB sector region
Bit 1 = Erase Type 2 support = 1b ---Erase Type 2 is 64KB erase and is
supported in the 64KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 64KB sector region
Bits 31:24 = RFU = FFh
Bits 23:16 = Region count (Dwords -1) = 00h: One region
Bits 15:8 = Configuration ID = 05h: Uniform 256KB sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = The end descriptor = 1
Bits 31:8 = 128Mb device
Region size = 00FFFFh: Region size as count-1 of 256 Byte units = 64 x 256KB
sectors = 16MB
Count = 16MB/256 = 65536, value = count -1 = 65536 -1 = 65535 = FFFFh Bits
31:8 = 256Mb device Region size = 01FFFFh: Region size as count-1 of 256
Byte units = 128 x 256KB sectors = 32MB Count = 32MB/256 = 131072, value =
count -1 = 131072 -1 = 131071 = 1FFFFh
Bits 7:4 = RFU = Fh Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b ---Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b ---Erase Type 3 is 256KB erase and is
supported in the 256KB sector region
Bit 1 = Erase Type 2 support = 0b ---Erase Type 2 is 64KB erase and is not
supported in the 256KB sector region
Bit 0 = Erase Type 1 support = 0b --- Erase Type 1 is 4KB erase and is not
supported in the 256KB sector region
Page 151 of 158
S25FS128S/S25FS256S
11.5
Initial Delivery State
The device is shipped from Cypress with non-volatile bits set as follows:
The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).
The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh.
The 33DP address space contains the values as defined in the description of the SFDP address space.
The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.
The Status Register 1 Non-Volatile contains 00h (all SR1NV bits are cleared to 0’s).
The Configuration Register 1 Non-Volatile contains 00h.
The Configuration Register 2 Non-Volatile contains 08h.
The Configuration Register 3 Non-Volatile contains 00h.
The Configuration Register 4 Non-Volatile contains 10h.
The Password Register contains FFFFFFFF–FFFFFFFFh.
All PPB bits are 1.
The ASP Register bits are FFFFh.
Document Number: 002-00368 Rev. *M
Page 152 of 158
S25FS128S/S25FS256S
Ordering Information
12.
Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S25FS
256
S
AG
M
F
I
00
1
Packing Type
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
00 = SOIC16 / WSON 6x8 mm footprint
10 = SOIC8 / WSON 6x5 mm footprint
20 = 5x5 ball BGA footprint
30 = 4x6 ball BGA footprint
1D = SOIC8, DDR
Temperature Range / Grade
I = Industrial (–40°C to + 85°C)
V = Industrial Plus (–40°C to + 105°C)
A = Automotive, AEC-Q100 Grade 3 (-40°C to +85°C)
B = Automotive, AEC-Q100 Grade 2 (-40°C to +105°C)
M = Automotive, AEC-Q100 Grade 1 (-40°C to +125°C)
Package Materials
F = Lead (Pb)-free
H = Low-Halogen, Lead (Pb)-free
Package Type
M = 16-pin SOIC / 8-Lead SOIC
N = 8-contact WSON 6 x 8 mm / WSON 6 x 5 mm
B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
AG = 133 MHz SDR
DS = 80 MHz DDR
Device Technology
S = 65 nm MirrorBit Process Technology
Density
128 = 128 Mbit
256 = 256 Mbit
Device Family
S25FS
Cypress Memory 1.8 Volt-Only, Serial Peripheral Interface (SPI) Flash
Memory
Document Number: 002-00368 Rev. *M
Page 153 of 158
S25FS128S/S25FS256S
Valid Combinations — Standard
Valid Combinations list configurations planned to be supported in volume for this device. Contact your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Table 79. S25FS128S, S25FS256S Valid Combinations — Standard
Valid Combinations
Base Ordering
Part Number
S25FS128S
S25FS256S
Speed
Option
Package and
Temperature
Model Number
Packing Type
AG
MFI, MFV
10
0, 1, 3
Package Marking
FS128S + (Temp) + F + (Model Number)
AG
NFI, NFV
00, 10
0, 1, 3
FS128S + A + (Temp) + F + (Model Number)
AG
BHI, BHV
20, 30
0, 3
FS128S + A + (Temp) + H + (Model Number)
DS
MFI, MFV
1D
0, 1, 3
FS128S + (Temp) + F + (Model Number)
DS
NFI, NFV
00, 10
0, 1, 3
FS128S + D + (Temp) + F + (Model Number)
DS
BHI, BHV
20, 30
0, 3
FS128S + D + (Temp) + H + (Model Number)
AG
MFI, MFV
00
0, 1, 3
FS256S + A + (Temp) + F + (Model Number)
AG
NFI, NFV
00
0, 1, 3
FS256S + A + (Temp) + F + (Model Number)
AG
BHI, BHV
20, 30
0, 3
FS256S + A + (Temp) + H + (Model Number)
DS
MFI, MFV
00
0, 1, 3
FS256S + D + (Temp) + F + (Model Number)
DS
NFI, NFV
00
0, 1, 3
FS256S + D + (Temp) + F + (Model Number)
DS
BHI, BHV
20, 30
0, 3
FS256S + D + (Temp) + H + (Model Number)
Valid Combinations — Automotive Grade / AEC-Q100
The table below lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The
table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific
combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with
ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Table 80. S25FS128S, S25FS256S Valid Combinations — Automotive Grade / AEC-Q100
Valid Combinations
Base Ordering
Part Number
S25FS128S
S25FS256S
Speed
Option
Package and Temperature
Model Number
Packing Type
AG
MFA, MFB, MFM
10
0, 1, 3
Package Marking
FS128S + (Temp) + F + (Model Number)
AG
NFA, NFB, NFM
00, 10
0, 1, 3
FS128S + A + (Temp) + F + (Model Number)
AG
BHA, BHB, BHM
20, 30
0, 3
FS128S + A + (Temp) + H + (Model Number)
DS
MFA, MFB, MFM
1D
0, 1, 3
FS128S + (Temp) + F + (Model Number)
DS
NFA, NFB, NFM
00, 10
0, 1, 3
FS128S + D + (Temp) + F + (Model Number)
DS
BHA, BHB, BHM
20, 30
0, 3
FS128S + D + (Temp) + H + (Model Number)
AG
MFA, MFB, MFM
00
0, 1, 3
FS256S + A + (Temp) + F + (Model Number)
AG
NFA, NFB, NFM
00
0, 1, 3
FS256S + A + (Temp) + F + (Model Number)
AG
BHA, BHB, BHM
20, 30
0, 3
FS256S + A + (Temp) + H + (Model Number)
DS
MFA, MFB, MFM
00
0, 1, 3
FS256S + D + (Temp) + F + (Model Number)
DS
NFA, NFB, NFM
00
0, 1, 3
FS256S + D + (Temp) + F + (Model Number)
DS
BHA, BHB, BHM
20, 30
0, 3
FS256S + D + (Temp) + H + (Model Number)
Document Number: 002-00368 Rev. *M
Page 154 of 158
S25FS128S/S25FS256S
Revision History
Document Title: S25FS128S/S25FS256S, 1.8 V, Serial Peripheral Interface with Multi-I/O, MirrorBit® Non-Volatile Flash
Document Number: 002-00368
Rev.
ECN No.
Submission
Date
Description of Change
**
-
04/05/2013
Initial release
*A
-
04/08/2013
Initial Delivery State
Corrected information on Configuration Register 2
*B
-
08/22/2013
Global Replaced ‘Quad All’ with ‘QPI’
Performance Summary Typical Program and Erase Rates table: corrected KB / s
Migration Notes Spansion SPI Families Comparison table: corrected Page Programming Rate (typ.)
for FS-S
DC Characteristics FS-S DC Characteristics table: added ISB (Automotive)
SDR AC Characteristics AC Characteristics table: updated Parameter for FSCK, C
Registers
Latency Code (Cycles) Versus Frequency table:
updated table
added Note 4
Embedded Algorithm Performance Tables
Program and Erase Performance table: corrected Typ and Max values for tPP
Ordering Information
Added 1D and 5D to Model Number
Valid Combinations table: corrected Model Number for S25FS128S
*C
-
11/06/2013
Global
Changed data sheet designation from “Advance Information” to “Preliminary” Changed USON to
WSON
Physical Interface
Added figure: 8-Pin Plastic Small Outline Package (SOIC8)
Updated figure: 8-Connector Package (WSON 6x5)
Removed figure: VSOP Thin 8-Lead, 208 mil Body Width, (SOV008)
Configuration Register 4 Updated Output Impedance Control table
Ordering Information Updated Model Numbers and Package Type
*D
-
12/20/2013
Migration Notes Changed Quad Read Speed (DDR) for FL-S
DDR AC Characteristics Updated AC Characteristics 80 MHz Operation table
DDR Output Timing SPI DDR Data Valid Window figure: updated figure and Notes
*E
-
11/06/2014
Global
Changed ‘Quad All’ to ‘QPI’
Changed ‘SCLK’ to ‘SCK’
Performance Summary Typical Current Consumption (–40°C to +85°C) table: added Deep
Power-Down
Migration Notes
Spansion SPI Families Comparison table: added Deep Power-Down
Updated Deep Power-Down section
Interface States Updated Interface Standby section
Data Protection Added Deep Power-Down (DPD) section
DC Characteristics
FS-S DC Characteristics table: added IDPD (Industrial and Automotive)
Updated Active Power and Standby Power Modes section
SDR AC Characteristics AC Characteristics table: added tDPD and tRES
DDR AC Characteristics AC Characteristics table: added tDPD and tRES
Command Set Summary
S25FS-S Family Command Set (sorted by function) table: added DPD and RES
Added DPD section
Reset Commands Added DPD Commands section
Embedded Algorithm Performance Tables
Corrected ‘Program and Erase Performance’ table
Software Interface Reference S25FS-S Family Command Set (sorted by instruction) table: added
DPD and RES
*F
5043003
12/09/2015
Updated to Cypress Template
Document Number: 002-00368 Rev. *M
Page 155 of 158
S25FS128S/S25FS256S
Document Title: S25FS128S/S25FS256S, 1.8 V, Serial Peripheral Interface with Multi-I/O, MirrorBit® Non-Volatile Flash
Document Number: 002-00368
Rev.
ECN No.
Submission
Date
*G
5074674
02/02/2016
Global
Changed status from Preliminary to Final.
Replaced “Automotive” with “Industrial Plus” in all instances across the document.
*H
5180929
03/18/2016
Updated Software Interface on page 50:
Updated Commands on page 82:
Updated Read Memory Array Commands on page 103:
Updated Quad I/O Read (QIOR EBh or 4QIOR ECh) on page 106:
Updated Figure 82 (fixed bit values).
Updated Figure 10.39 (fixed bit values).
*I
5445453
11/16/2016
Added ECC related information in all instances across the document.
Updated Program and Erase cycles and Retention to Features on page 1.
Updated Typical Program and Erase Rates on page 2.
Updated Typical Current Consumption (–40°C to +85°C) on page 2.
Added Thermal Resistance on page 25.
Added Automotive Grade to Temperature Ranges on page 26.
Updated FS-S DC Characteristics on page 29.
Updated AC Characteristics on page 35.
Added ECC Status Register (ECCSR) on page 69.
Added ECC Status Register Read (ECCRD 19h or 4EECRD 18h) on page 97.
Description of Change
Updated Read Any Register, QPI Mode, Command Sequence[50] on page 100.
Updated Dual I/O Read Command Sequence (BBh)[53, 54, 55] on page 106.
Updated Dual I/O Continuous Read Command Sequence (4-Byte Address [CR2V[7] = 1])[53, 54]
on page 106.
Updated figures in Quad I/O Read (QIOR EBh or 4QIOR ECh) on page 106.
Updated figures in DDR Quad I/O Read (EDh, EEh) on page 108.
Added Automatic ECC on page 110.
Updated Embedded Algorithm Performance Tables on page 131.
Updated Program and Erase Performance on page 131.
Updated Program or Erase Suspend AC Parameters on page 131.
Added Data Integrity on page 132.
Removed Software Interface Reference section.
Added Valid Combinations — Automotive Grade / AEC-Q100 on page 154.
Updated Copyright and Disclaimer.
*J
5705491
04/21/2017
Document Number: 002-00368 Rev. *M
Replaced VDD with VCC in all instances across the document.
Updated Electrical Specifications on page 25:
Updated Operating Ranges on page 26:
Updated Temperature Ranges on page 26:
Added “Automotive AEC-Q100 Grade 1 (–40°C to +125°C)” Temperature Range related information.
Updated Physical Interface on page 40:
Updated SOIC 16-Lead Package on page 40:
Updated SOIC 16 Physical Diagram on page 41:
Updated Figure 36.
Updated 8-Connector Packages on page 42:
Updated 8-Connector Physical Diagrams on page 43:
Updated Figure 39.
Updated Figure 40.
Updated Figure 41.
Updated FAB024 24-Ball BGA Package on page 46:
Updated Physical Diagram on page 47:
Updated Figure 43.
Updated FAC024 24-Ball BGA Package on page 48:
Updated Physical Diagram on page 49:
Page 156 of 158
S25FS128S/S25FS256S
Document Title: S25FS128S/S25FS256S, 1.8 V, Serial Peripheral Interface with Multi-I/O, MirrorBit® Non-Volatile Flash
Document Number: 002-00368
Rev.
ECN No.
Submission
Date
*J (cont.)
5705491
04/21/2017
Updated Figure 45.
Updated Ordering Part Number on page 153:
Added “Automotive AEC-Q100 Grade 1 (–40°C to +125°C)” Temperature Range related information.
Updated Valid Combinations — Automotive Grade / AEC-Q100 on page 154:
Added “Automotive AEC-Q100 Grade 1 (–40°C to +125°C)” Temperature Range related information.
Updated to new template.
*K
6125350
04/03/2018
Added Section 4.6.2 Deep Power Down Mode on page 30
*L
6385427
11/21/2018
Updated description of block size in Features on page 1.
Updated Thermal Resistance Table in Section 4.2 Thermal Resistance on page 25.
*M
6735857
11/22/2019
Updated Table 33.
Updated Section 9.3.4 Write Registers (WRR 01h) on page 92.
Document Number: 002-00368 Rev. *M
Description of Change
Page 157 of 158
S25FS128S/S25FS256S
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-00368 Rev. *M
Revised November 22, 2019
Page 158 of 158