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S25FS512S
512 Mb, 1.8 V Serial Peripheral Interface
with Multi-I/O Flash
Features
■
Serial Peripheral Interface (SPI) with Multi-I/O
❐ SPI Clock polarity and phase modes 0 and 3
❐ Double Data Rate (DDR) option
❐ Extended Addressing – 24 or 32-bit address options
❐ Serial Command subset and footprint compatible with
S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families
❐ Multi I/O Command subset and footprint compatible with
S25FL-P, and S25FL-S SPI families
■
Read
❐ Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O
❐ Modes: Burst Wrap, Continuous (XIP), QPI
❐ Serial Flash Discoverable Parameters (SFDP) and Common
Flash Interface (CFI), for configuration information.
■
Program
❐ 256 or 512 Bytes Page Programming buffer
❐ Program suspend and resume
❐ Automatic Error Checking and Correction (ECC) – internal
hardware ECC with single bit error correction
■
■
Erase
❐ Hybrid sector option
• Physical set of eight 4-KB sectors and one
224-KB sector at the top or bottom of address space with
all remaining sectors of 256-KB
❐ Uniform sector option
• Uniform 256-KB blocks
❐ Erase suspend and resume
❐ Erase status evaluation
■
Data Retention
❐ 20 Year Data Retention, minimum
■
Security Features
❐ One Time Program (OTP) array of 1024 bytes
❐ Block Protection:
• Status Register bits to control protection against program
or erase of a contiguous range of sectors.
• Hardware and software control options
❐ Advanced Sector Protection (ASP)
• Individual sector protection controlled by boot code or
password
• Option for password control of read access
■
Technology
❐ Cypress 65-nm MirrorBit Technology with Eclipse
Architecture
■
Supply Voltage
❐ 1.7 V to 2.0 V
■
Temperature Range / Grade
❐ Industrial (40 °C to +85 °C)
❐ Industrial Plus (40 °C to +105 °C)
❐ Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
❐ Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
❐ Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
■
Packages (all Pb-free)
❐ 16-lead SOIC 300 mil (SO3016)
❐ WSON 6 8 mm (WNH008)
❐ BGA-24 6 8 mm
• 5 5 ball (FAB024) footprint
❐ Known Good Die and Known Tested Die
Cycling Endurance
❐ 100,000 Program-Erase Cycles, minimum
Cypress Semiconductor Corporation
Document Number: 002-00488 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 22, 2019
S25FS512S
Logic Block Diagram
CS#
X Decoders
SRAM
SCK
SI/IO0
SO/IO1
MirrorBit Array
Y Decoders
I/O
Data Latch
WP#/IO2
Control
Logic
RESET#/IO3
Data Path
Performance Summary
Maximum Read Rates
Command
Clock Rate (MHz)
MBps
Read
50
6.25
Fast Read
133
16.5
Dual Read
133
33
Quad Read
133
66
DDR Quad I/O Read
80
80
Typical Program and Erase Rates
Operation
KBps
Page Programming (256-bytes page buffer)
712
Page Programming (512-bytes page buffer)
1080
4-KB Physical Sector Erase (Hybrid Sector Option)
28
256-KB Sector Erase (Uniform Logical Sector Option)
250
Typical Current Consumption, 40°C to +85°C
Operation
Current (mA)
Serial Read 50 MHz
10
Serial Read 133 MHz
20
Quad Read 133 MHz
60
Quad DDR Read 80 MHz
70
Program
60
Erase
60
Standby
0.07
Deep Power Down
0.006
Document Number: 002-00488 Rev. *M
Page 2 of 139
S25FS512S
Contents
1.
1.1
1.2
1.3
1.4
Overview .......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
4
7
7
Hardware Interface
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
Signal Descriptions ..................................................... 8
Input/Output Summary................................................... 8
Multiple Input / Output (MIO).......................................... 9
Serial Clock (SCK) ......................................................... 9
Chip Select (CS#) .......................................................... 9
Serial Input (SI) / IO0 ..................................................... 9
Serial Output (SO) / IO1................................................. 9
Write Protect (WP#) / IO2 .............................................. 9
IO3 / RESET# ............................................................. 10
Voltage Supply (VCC)................................................... 10
Supply and Signal Ground (VSS) ................................. 10
Not Connected (NC) .................................................... 10
Reserved for Future Use (RFU)................................... 10
Do Not Use (DNU) ....................................................... 10
Block Diagrams............................................................ 11
3.
3.1
3.2
3.3
3.4
3.5
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
12
12
13
16
20
21
4.
4.1
4.2
4.3
4.4
4.5
4.6
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Latchup Characteristics ...............................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
22
22
22
22
22
23
25
5.
5.1
5.2
5.3
5.4
5.5
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics ..............................................
DDR AC Characteristics. .............................................
28
28
28
29
31
33
6.
6.1
6.2
6.3
Physical Interface ......................................................
SOIC 16-Lead Package ...............................................
8-Connector Package ..................................................
BGA 24-Ball, 5x5 Ball Footprint (FAB024)...................
36
36
38
40
Document Number: 002-00488 Rev. *M
Software Interface
7.
7.1
7.2
7.3
7.4
7.5
7.6
Address Space Maps.................................................. 42
Overview....................................................................... 42
Flash Memory Array...................................................... 42
ID-CFI Address Space .................................................. 43
JEDEC JESD216 Serial Flash Discoverable
Parameters (SFDP) Space ........................................... 43
OTP Address Space ..................................................... 44
Registers....................................................................... 45
8.
8.1
8.2
8.3
8.4
8.5
Data Protection ........................................................... 62
Secure Silicon Region (OTP)........................................ 62
Write Enable Command................................................ 63
Block Protection ............................................................ 63
Advanced Sector Protection ......................................... 64
Recommended Protection Process .............................. 69
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Commands .................................................................. 70
Command Set Summary............................................... 71
Identification Commands .............................................. 77
Register Access Commands......................................... 79
Read Memory Array Commands .................................. 90
Program Flash Array Commands ................................. 97
Erase Flash Array Commands...................................... 99
One Time Program Array Commands ........................ 105
Advanced Sector Protection Commands .................... 106
Reset Commands ....................................................... 112
DPD Commands ......................................................... 113
10.
Embedded Algorithm Performance Tables............. 115
11.
11.1
11.2
11.3
Data Integrity ............................................................. 116
Erase Endurance ........................................................ 116
Data Retention ............................................................ 116
Serial Flash Discoverable Parameters
(SFDP) Address Map.................................................. 116
11.4 Device ID and Common Flash Interface
(ID-CFI) Address Map................................................. 119
11.5 Initial Delivery State .................................................... 134
Ordering Information
12.
Ordering Part Number .............................................. 135
13. Revision History........................................................ 137
Sales, Solutions, and Legal Information ........................ 139
Worldwide Sales and Design Support ......................... 139
Products ...................................................................... 139
PSoC® Solutions ........................................................ 139
Cypress Developer Community ................................... 139
Technical Support ....................................................... 139
Page 3 of 139
S25FS512S
1. Overview
1.1
General Description
The Cypress S25FS512S device is a flash nonvolatile memory product using:
MirrorBit technology — that stores two data bits in each memory array transistor
Eclipse architecture — that dramatically improves program and erase performance
65 nm process lithography
The S25FS512S connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two-bit (Dual I/O or DIO) and four-bit wide Quad I/O (QIO) or Quad Peripheral
Interface (QPI) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, there are Double Data Rate
(DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.
The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation,
resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS512S devices at the higher clock
rates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel
interface, asynchronous, NOR flash memories, while reducing signal count dramatically.
The S25FS512S products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal
for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
1.2
Migration Notes
1.2.1
Features Comparison
The S25FS512S is command subset and footprint compatible with prior generation FL-S, FL-K, and FL-P families. However, the
power supply and interface voltages are nominal 1.8V.
Table 1. Cypress SPI Families Comparison
Parameter
FS-S
FL-S
FL-K
FL-P
Technology Node
65 nm
65 nm
90 nm
90 nm
Architecture
MirrorBit® Eclipse™
MirrorBit® Eclipse™
Floating Gate
MirrorBit®
Density
128 Mb - 512 Mb
128 Mb - 1 Gb
4 Mb - 128 Mb
32 Mb - 256 Mb
Bus Width
x1, x2, x4
x1, x2, x4
x1, x2, x4
Supply Voltage
1.7 V - 2.0 V
2.7 V - 3.6 V / 1.65 V - 3.6 V VIO 2.7 V - 3.6 V
Normal Read Speed (SDR)
6 MB/s (50 MHz)
6 MB/s (50 MHz)
6 MB/s (50 MHz)
5 MB/s (40 MHz)
Fast Read Speed (SDR)
16.5 MB/s (133 MHz)
17 MB/s (133 MHz)
13 MB/s (104 MHz)
13 MB/s (104 MHz)
Dual Read Speed (SDR)
33 MB/s (133 MHz)
26 MB/s (104 MHz)
26 MB/s (104 MHz)
20 MB/s (80 MHz)
Quad Read Speed (SDR)
66 MB/s (133 MHz)
52 MB/s (104 MHz)
52 MB/s (104 MHz)
40 MB/s (80 MHz)
Quad Read Speed (DDR)
80 MB/s (80 MHz)
80 MB/s (80 MHz)
—
—
Program Buffer Size
256B / 512B
256B / 512B
256B
256B
x1, x2, x4
2.7 V - 3.6 V
Erase Sector Size
64 KB / 256 KB
64 KB / 256 KB
4 KB / 32 KB / 64 KB
64 KB / 256 KB
Parameter Sector Size
4 KB (option)
4 KB (option)
4 KB
4 KB
Sector Erase Rate (typ.)
500 KB/s
500 KB/s
136 KB/s (4 KB)
437 KB/s (64 KB)
130 KB/s
Page Programming Rate (typ.)
0.71 MB/s (256B)
1.08 MB/s (512B)
1.2 MB/s (256B)
1.5 MB/s (512B)
365 KB/s
170 KB/s
OTP
1024B
1024B
768B (3x256B)
506B
Advanced Sector Protection
Yes
Yes
No
No
Document Number: 002-00488 Rev. *M
Page 4 of 139
S25FS512S
Table 1. Cypress SPI Families Comparison (Continued)
Parameter
FS-S
FL-S
FL-K
FL-P
Auto Boot Mode
No
Yes
No
No
Erase Suspend/Resume
Yes
Yes
Yes
No
Program Suspend/Resume
Yes
Yes
Yes
No
Deep Power-Down Mode
Yes
No
Yes
Yes
Operating Temperature
-40°C to +85°C / +105°C
-40°C to +85°C / +105°C /
-40°C to +85°C
+125°C
-40°C to
+105°C
+85°C
/
Notes
1. 256B program page option only for 128 Mb and 256 Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128 Mb density), FL128P does not support MIO, OTP, or 4 KB sectors.
3. 64-KB sector erase option only for 128 Mb / 256 Mb density FL-P, FL-S, and FS-S devices.
4. FL-K family devices can erase 4-KB sectors in groups of 32 KB or 64 KB.
5. Only 128 Mb/256 Mb density FL-S devices have 4-KB parameter sector option.
6. 512 Mb / 1 Gb FL-S devices support 256 KB-sector only.
7. The FS512 device does not support 64 KB-sectors.
8. Refer to individual product data sheets for further details.
1.2.2
Known Differences from Prior Generations
1.2.2.1 Error Reporting
FL-K and FL-P memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FS-S and FL-S families do have error reporting status bits for program and erase operations. These can be set when
there is an internal failure to program or erase, or when there is an attempt to program or erase a protected sector. In these cases
the program or erase operation did not complete as requested by the command. The P_ERR or E_ERR bits and the WIP bit will be
set to and remain 1 in SR1V. The clear status register command must be sent to clear the errors and return the device to standby
state.
1.2.2.2 Secure Silicon Region (OTP)
The FS-S size and format (address map) of the One Time Program area is different from FL-K and FL-P generations. The method
for protecting each portion of the OTP area is different. For additional details, see Secure Silicon Region (OTP) on page 62.
1.2.2.3 Configuration Register Freeze Bit
The Configuration Register 1 Freeze Bit CR1V[0], locks the state of the Block Protection bits (SR1NV[4:2] and SR1V[4:2]),
TBPARM_O bit (CR1NV[2]), and TBPROT_O bit (CR1NV[5]), as in prior generations. In the FS-S and FL-S families the Freeze Bit
also locks the state of the Configuration Register 1 BPNV_O bit (CR1NV[3]), and the Secure Silicon Region (OTP) area.
1.2.2.4 Sector Erase Commands
The command for erasing a 4-KB sector is supported only for use on 4-KB parameter sectors at the top or bottom of the FS-S device
address space.
The command for erasing an 8-KB area (two 4-KB sectors) is not supported.
The command for erasing a 32-KB area (eight 4-KB sectors) is not supported.
The 64 KB erase command is not supported for the 512 Mb density FS-S device.
1.2.2.5 Deep Power-Down
A Deep Power-Down (DPD) function is supported in the FS-S family devices.
Document Number: 002-00488 Rev. *M
Page 5 of 139
S25FS512S
1.2.2.6 WRR Single Register Write
In some legacy SPI devices, a Write Registers (WRR) command with only one data byte would update Status Register 1 and clear
some bits in Configuration Register 1, including the Quad mode bit. This could result in unintended exit from Quad mode. The
S25FS512S only updates Status Register 1 when a single data byte is provided. The Configuration Register 1 is not modified in this
case.
1.2.2.7 Hold Input Not Supported
In some legacy SPI devices, the IO3 input has an alternate function as a HOLD# input used to pause information transfer without
stopping the serial clock. This function is not supported in the FS-S family.
1.2.2.8 Separate Reset Input Not Supported
In some legacy SPI devices, a separate hardware RESET# input is supported in packages having more than eight connections. The
FS-S family does not support a separate RESET# input. The FS-S family provides an alternate function for the IO3 input as a
RESET# input. When the CS# signal is high and the IO3 / RESET feature is enabled, the IO3 / RESET# input is used to initiate a
hardware reset when the input goes low.
1.2.2.9 Other Legacy Commands Not Supported
Autoboot Related Commands
Bank Address Related Commands
Dual Output Read
Quad Output Read
Quad Page Program (QPP) — replaced by Page Program in QPI mode
DDR Fast Read
DDR Dual I/O Read
1.2.2.10 New Features
The FS-S family introduces new features to Cypress SPI category memories:
Single 1.8 V power supply for core and I/O voltage.
Configurable initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read commands.
QPI (QPI, 4-4-4) read mode in which all transfers are 4 bits wide, including instructions.
JEDEC JESD216 standard, Serial Flash Discoverable Parameters (SFDP) that provide device feature and configuration
information.
Evaluate Erase Status command to determine if the last erase operation on a sector completed successfully. This command can
be used to detect incomplete erase due to power loss or other causes. This command can be helpful to Flash File System
software in file system recovery after a power loss.
Advanced Sector Protection (ASP) Permanent Protection. A bit is added to the ASP register to provide the option to make
protection of the Persistent Protection Bits (PPB) permanent. Also, when one of the two ASP protection modes is selected, all
OTP configuration bits in all registers are protected from further programming so that all OTP configuration settings are made
permanent. The OTP address space is not protected by the selection of an ASP protection mode. The Freeze bit (CR1V[0]) may
be used to protect the OTP Address Space.
Document Number: 002-00488 Rev. *M
Page 6 of 139
S25FS512S
1.3
Glossary
BCD
Binary Coded Decimal. A value in which each 4-bit nibble represents a decimal numeral.
Command
All information transferred between the host system and memory during one period while CS# is low. This includes the
instruction (sometimes called an operation code or opcode) and any required address, mode bits, latency cycles, or
data.
DDP
Dual Die Package. Two die stacked within the same package to increase the memory capacity of a single package.
Often also referred to as a Multi-Chip Package (MCP).
DDR
Double Data Rate. When input and output are latched on every edge of SCK.
ECC
ECC Unit = 16 byte aligned and length data groups in the main Flash array and OTP array, each of which has its own
hidden ECC syndrome to enable error correction on each group.
Flash
The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large blocks of
memory bits in parallel, making the erase operation much faster than early EEPROM.
High
A signal voltage level VIH or a logic level representing a binary one (‘1’).
Instruction
8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). The
instruction is always the first 8 bits transferred from host system to the memory in any command.
Low
A signal voltage level VIL or a logic level representing a binary zero (‘0’).
LSb
Least Significant Bit. Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a
register or data value.
MSb
Most Significant Bit. Generally the left most bit, with the highest order of magnitude value, within a group of bits of a
register or data value.
LSB
Least Significant Byte.
MSB
Most Significant Byte.
N/A
Not Applicable. A value is not relevant to situation described.
Nonvolatile
No power is needed to maintain data stored in the memory.
OPN
Ordering Part Number. The alphanumeric string specifying the memory device type, density, package, factory
nonvolatile configuration, etc. used to select the desired device.
Page
512-byte or 256-byte aligned and length group of data. The size assigned for a page depends on the Ordering Part
Number.
PCB
Printed Circuit Board.
Register Bit References Format: Register_name[bit_number] or Register_name[bit_range_MSb: bit_range_LSb].
SDR
Single Data Rate. When input is latched on the rising edge and output on the falling edge of SCK.
Sector
Erase unit size; depending on device model and sector location this may be 4 KB, 64 KB, or 256 KB.
Write
An operation that changes data within volatile or nonvolatile registers bits or nonvolatile flash memory. When changing
nonvolatile data, an erase and reprogramming of any unchanged nonvolatile data is done, as part of the operation, such
that the nonvolatile data is modified by the write operation, in the same way that volatile data is modified – as a single
operation. The nonvolatile data appears to the host system to be updated by the single write command, without the
need for separate commands for erase and reprogram of adjacent, but unaffected data.
1.4
Other Resources
1.4.1
Cypress Flash Memory Roadmap
www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap
1.4.2
Links to Software
www.cypress.com/software-and-drivers-cypress-flash-memory
1.4.3
Links to Application Notes
www.cypress.com/appnotes
Document Number: 002-00488 Rev. *M
Page 7 of 139
S25FS512S
Hardware Interface
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large
number of signal connections and larger package size. The large number of connections increase power consumption due to so
many signals switching and the larger package increases cost.
The S25FS512S reduces the number of signals for connection to the host system by serially transferring all control, address, and
data information over 4 to 6 signals. This reduces the cost of the memory package, reduces signal switching power, and either
reduces the host connection count or frees host connectors for use in providing other features.
The S25FS512S uses the industry standard single bit Serial Peripheral Interface (SPI) and also supports optional extension
commands for two-bit (Dual) and four-bit (Quad) wide serial transfers. This multiple width interface is called SPI Multi-I/O or
SPI-MIO.
2. Signal Descriptions
2.1
Input/Output Summary
Table 2. Signal List
Signal Name
Type
SCK
Input
Serial Clock.
Description
Chip Select.
CS#
Input
SI / IO0
I/O
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1
I/O
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
Write Protect when not in Quad mode (CR1V[1] = 0 and SR1NV[7] = 1). See Table 20 on page 46.
IO2 when in Quad mode (CR1V[1] = 1).
WP# / IO2
I/O
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for
Quad commands or write protection. If write protection is enabled by SR1NV[7] = 1 and CR1V[1] = 0, the host
system is required to drive WP# high or low during a WRR or WRAR command.
IO3 in Quad-I/O mode, when Configuration Register 1 QUAD bit, CR1V[1] =1, and CS# is low.
IO3 / RESET#
I/O
RESET# when enabled by CR2V[5]=1 and not in Quad-I/O mode, CR1V[1] = 0, or when enabled in quad
mode, CR1V[1] = 1 and CS# is high.
The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for
Quad commands or RESET#.
VCC
Supply
Power Supply.
VSS
Supply
Ground.
Unused
Not Connected. No device internal signal is connected to the package connector nor is there any future plan
to use the connector for a signal. The connection may safely be used for routing space for a signal on a
Printed Circuit Board (PCB). However, any signal connected to an NC must not have voltage levels higher
than VCC.
NC
RFU
DNU
Reserved
Reserved for Future Use. No device internal signal is currently connected to the package connector but
there is potential future use of the connector for a signal. It is recommended to not use RFU connectors for
PCB routing channels so that the PCB may take advantage of future enhanced features in compatible
footprint devices.
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The connection may be
used by Cypress for test or other purposes and is not intended for connection to any host system signal. Any
DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down
resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections
for PCB signal routing channels. Do not connect any host system signal to this connection.
Document Number: 002-00488 Rev. *M
Page 8 of 139
S25FS512S
2.2
Multiple Input / Output (MIO)
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the Serial Input (SI)
signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI / IO0 signal. Address or data is sent
from the host to the memory as bit pairs on IO0 and IO1 or four-bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the
host similarly as bit pairs on IO0 and IO1 or four-bit (nibble) groups on IO0, IO1, IO2, and IO3.
QPI mode transfers all instructions, address, and data from the host to the memory as four-bit (nibble) groups on IO0, IO1, IO2, and
IO3. Data is returned to the host similarly as four-bit (nibble) groups on IO0, IO1, IO2, and IO3.
2.3
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on
the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR commands, and after every edge in
DDR commands.
2.4
Chip Select (CS#)
The chip select signal indicates when a command is transferring information to or from the device and the other signals are relevant
for the memory device.
When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are
high impedance. The device will be in the Standby Power mode, unless an internal embedded operation is in progress. An
embedded operation is indicated by the Status Register 1 Write-In-Progress bit (SR1V[1]) set to 1, until the operation is completed.
Some example embedded operations are: Program, Erase, or Write Registers (WRR) operations.
Driving the CS# input to the logic low state enables the device, placing it in the Active Power mode. After Power-up, a falling edge on
CS# is required prior to the start of any command.
2.5
Serial Input (SI) / IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed.
Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 — an input and output during Dual and Quad commands for receiving instructions, addresses, and data to be
programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in
SDR commands, and on every edge of SCK, in DDR commands).
2.6
Serial Output (SO) / IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock
signal.
SO becomes IO1 — an input and output during Dual and Quad commands for receiving addresses, and data to be programmed
(values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR commands,
and on every edge of SCK, in DDR commands).
2.7
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), during a WRR or WRAR command and while the Status Register Write Disable (SRWD_NV) bit of
Status Register 1 (SR1NV[7]) is set to a 1, it is not possible to write to Status Register 1 or Configuration Register 1 related registers.
In this situation, a WRR command is ignored, a WRAR command selecting SR1NV, SR1V, CR1NV, or CR1V is ignored, and no
error is set.
This prevents any alteration of the Block Protection settings. As a consequence, all the data bytes in the memory area that are
protected by the Block Protection feature are also hardware protected against data modification if WP# is Low during a WRR or
WRAR command with SRWD_NV set to 1.
The WP# function is not available when the Quad mode is enabled (CR1V[1]=1). The WP# function is replaced by IO2 for input and
output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal)
as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
Document Number: 002-00488 Rev. *M
Page 9 of 139
S25FS512S
WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host system if not
used for Quad mode or protection.
2.8
IO3 / RESET#
IO3 is used for input and output during Quad mode (CR1V[1]=1) for receiving addresses, and data to be programmed (values are
latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every
edge of SCK, in DDR commands).
The IO3 / RESET# signal may also be used to initiate the hardware reset function when the reset feature is enabled by writing
Configuration Register 2 nonvolatile bit 5 (CR2V[5]=1). The input is only treated as RESET# when the device is not in Quad-I/O
mode, CR1V[1] = 0, or when CS# is high. When Quad I/O mode is in use, CR1V[1]=1, and the device is selected with CS# low, the
IO3 / RESET# is used only as IO3 for information transfer. When CS# is high, the IO3 / RESET# is not in use for information transfer
and is used as the RESET# input. By conditioning the reset operation on CS# high during Quad mode, the reset function remains
available during Quad mode.
When the system enters a reset condition, the CS# signal must be driven high as part of the reset process and the IO3 / RESET#
signal is driven low. When CS# goes high the IO3 / RESET# input transitions from being IO3 to being the RESET# input. The reset
condition is then detected when CS# remains high and the IO3 / RESET# signal remains low for tRP. If a reset is not intended, the
system is required to actively drive IO3 / Reset# to high along with CS# being driven high at the end of a transfer of data to the
memory. Following transfers of data to the host system, the memory will drive IO3 high during tCS. This will ensure that IO3 / Reset
is not left floating or being pulled slowly to high by the internal or an external passive pull-up. Thus, an unintended reset is not
triggered by the IO3 / RESET# not being recognized as high before the end of tRP.
The IO3 / RESET# signal is unused when the reset feature is disabled (CR2V[5]=0).
The IO3 / RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode
or the reset function. The internal pull-up will hold IO3 / Reset high after the host system has actively driven the signal high and then
stops driving the signal.
Note that IO3 / Reset# cannot be shared by more than one SPI-MIO memory if any of them are operating in Quad I/O mode as IO3
being driven to or from one selected memory may look like a reset signal to a second non-selected memory sharing the same IO3 /
RESET# signal.
2.9
Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read,
program, and erase.
2.10
Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.
2.11
Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The
connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).
2.12
Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but there is potential future use of the connector. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced
features in compatible footprint devices.
2.13
Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other
purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the
signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.
Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
Document Number: 002-00488 Rev. *M
Page 10 of 139
S25FS512S
2.14
Block Diagrams
Figure 1. Bus Master and Memory Devices on the SPI Bus — Single Bit Data Path
RESET#
RESET#
WP#
SI
SO
SCK
CS2#
CS1#
WP#
SO
SI
SCK
CS2#
CS1#
FS-S
Flash
FS-S
Flash
SPI
Bus Master
Figure 2. Bus Master and Memory Devices on the SPI Bus — Dual Bit Data Path
RESET#
RESET#
WP#
IO1
IO0
SCK
CS2#
CS1#
WP#
IO1
IO0
SCK
CS2#
CS1#
FS-S
Flash
FS-S
Flash
SPI
Bus Master
Figure 3. Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path
RESET# / IO3
IO2
IO1
IO0
SCK
CS1#
SPI
Bus Master
Document Number: 002-00488 Rev. *M
IO3 / RESET#
IO2
IO1
IO0
SCK
CS1#
FS -S
Flash
Page 11 of 139
S25FS512S
3.
Signal Protocols
3.1
SPI Clock Modes
3.1.1
Single Data Rate (SDR)
The S25FS512S can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is
always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data.
SCK will stay at logic low state with CPOL = 0, CPHA = 0
SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 4. SPI SDR Modes Supported
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
CS#
SI
MSb
SO
MSb
Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by showing SCK as both
high and low at the fall of CS#. In some cases a timing diagram may show only Mode 0 with SCK low at the fall of CS#. In such a
case, Mode 3 timing simply means clock is high at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of
CS# is needed for Mode 3.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0 the beginning of the
first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low
at the beginning of a command.
3.1.2
Double Data Rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always latched on the rising
edge of clock, the same as in SDR commands. However, the address and input data that follow the instruction are latched on both
the rising and falling edges of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end
of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the next falling edge of
SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge
of SCK because SCK is already low at the beginning of a command.
Figure 5. SPI DDR Modes Supported
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
CS#
Transfer_Phase
SI
Instruction
Inst. 7
SO
Document Number: 002-00488 Rev. *M
Address
Inst. 0
A31
A30
Mode
A0
M7
M6
Dummy / DLP
Read Data
M0
DLP7
DLP0
D0
D1
Page 12 of 139
S25FS512S
3.2
Command Protocol
All communication between the host system and S25FS512S devices is in the form of units called commands.
All commands begin with an 8-bit instruction that selects the type of information transfer or device operation to be performed.
Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the
memory. All instruction, address, and data information is transferred sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three
command phases:
instruction
address and instruction modifier (continuous read mode bits)
data
Single-bit wide commands start with an instruction and may provide an address or data, all sent only on the SI signal. Data may be
sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol for single-bit width instruction,
single-bit width address and modifier, single-bit data.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four-bit (nibble)
groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four-bit (nibble) groups on
IO0, IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command protocols.
The S25FS512S also supports a QPI mode in which all information is transferred in 4-bit width, including the instruction, address,
modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host driving
the Chip Select (CS#) signal low throughout a command.
The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
Each command begins with an eight bit (byte) instruction. The instruction selects the type of information transfer or device
operation to be performed. The instruction transfers occur on SCK rising edges. However, some read commands are modified by
a prior read command, such that the instruction is implied from the earlier command. This is called Continuous Read Mode. When
the device is in continuous read mode, the instruction bits are not transmitted at the beginning of the command because the
instruction is the same as the read command that initiated the Continuous Read Mode. In Continuous Read mode the command
will begin with the read address. Thus, Continuous Read Mode removes eight instruction bits from each read command in a
series of same type read commands.
The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces
in the device. The instruction determines the address space used. The address may be either a 24-bit or a 32-bit, byte boundary,
address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
In legacy SPI mode, the width of all transfers following the instruction are determined by the instruction sent. Following transfers
may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per (dual)
transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per (quad) transfer on the IO0-IO3 signals. Within the
dual or quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher
numbered IO signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
In QPI mode, the width of all transfers is a 4-bit wide (quad) transfer on the IO0-IO3 signals.
Dual and Quad I/O read instructions send an instruction modifier called Continuous Read mode bits, following the address, to
indicate whether the next command will be of the same type with an implied, rather than an explicit, instruction. These mode bits
initiate or end the continuous read mode. In continuous read mode, the next command thus does not provide an instruction byte,
only a new address and mode bits. This reduces the time needed to send each command when the same command type is
repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK
edge, in DDR commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before
read data is returned to the host.
Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
Document Number: 002-00488 Rev. *M
Page 13 of 139
S25FS512S
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles (also referred to
as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on SCK falling edge at
the end of the last read latency cycle. The first read data bits are considered transferred to the host on the following SCK rising
edge. Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
If the command returns read data to the host, the device continues sending data transfers until the host takes the CS# signal high.
The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the command.
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go high after the
eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be driven high
when the number of bits after the CS# signal was driven low is an exact multiple of eight bits. If the CS# signal does not go high
exactly at the eight-bit boundary of the instruction or write data, the command is rejected and not executed.
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSb) first. The data bits are
shifted in and out of the device MSb first. All data is transferred in byte units with the lowest address byte sent first. Following
bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The
embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an
embedded operation. These are discussed in the individual command descriptions.
Depending on the command, the time for execution varies. A command to read status information from an executing command is
available to determine when the command completes execution and whether the command was successful.
3.2.1
Command Sequence Examples
Figure 6. Stand Alone Instruction Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Figure 7. Single Bit Wide Input Command
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
Figure 8. Single Bit Wide Output Command
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
Phase
Document Number: 002-00488 Rev. *M
7
Instruction
6 5 4 3 2 1 0 7
Data 1
6 5 4 3 2 1 0
Data 2
Page 14 of 139
S25FS512S
Figure 9. Single Bit Wide I/O Command without latency
CS#
SCK
SI
7 6 5 4 3 2 1 0 31
1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
Address
Instruction
Data 1
Data 2
Figure 10. Single Bit Wide I/O Command with latency
CS#
SCK
SI
7 6 5 4 3 2 1 0 31
1 0
SO
7 6 5 4 3 2 1 0
Phase
Dummy Cycles
Address
Instruction
Data 1
Figure 11. Dual I/O Command
CS#
SCK
IO0
7 6 5 4 3 2 1 0 30
2 0 6 4 2 0
6 4 2 0 6 4 2 0
IO1
31
3 1 7 5 3 1
7 5 3 1 7 5 3 1
Phase
Instruction
Address
Mode
Dum
Data 1
Data 2
Figure 12. Quad I/O Command
CS#
SCK
IO0
7 6 5 4 3 2 1 0 28
4 0 4 0
4 0 4 0 4 0 4 0
IO1
29
5 1 5 1
5 1 5 1 5 1 5 1
IO2
30
6 2 6 2
6 2 6 2 6 2 6 2
IO3
31
Phase
Instruction
7 3 7 3
Address Mode
7 3 7 3 7 3 7 3
Dummy
D1
D2
D3
D4
Figure 13. Quad I/O Read Command in QPI Mode
CS#
SCK
IO0
4
0 28
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1 29
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2 30
6
2
6
2
6
2
6
2
6
2
6
2
7
3 31
7
3
7
3
3
7
3
7
3
7
IO3
Phase
Instruct.
Document Number: 002-00488 Rev. *M
Address
Mode
7
Dummy
D1
D2
D3
3
D4
Page 15 of 139
S25FS512S
Figure 14. DDR Quad I/O Read
CS#
SCK
IO0
2824201612 8
4 0 40
7 65 4 3 2 1 0 4 0 40
IO1
7
6
2925211713 9
5 1 51
7 65 4 3 2 1 0 5 1 51
IO2
302622181410 6
2 62
7 65 4 3 2 1 0 6 2 62
IO3
312723191511 7
3 73
7 65 4 3 2 1 0 7 3 73
Phase
5
4
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1 D2
Figure 15. DDR Quad I/O Read in QPI Mode
CS#
SCK
IO0
4
0 28 24 20 16 12 8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
5
1 29 25 21 17 13 9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
6
2 30 26 22 18 14 10 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
7
3 31 27 23 19 15 11 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
Phase
Instruct.
Address
Mode
Dummy
DLP
D1
D2
Additional sequence diagrams, specific to each command, are provided in Section 9. Commands on page 70.
3.3
Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3. Interface States Summary
VCC
SCK
CS#
IO3 /
RESET#
WP# /
IO2
SO / IO1
SI / IO0
133 MHz SDR, or 80 MHz DDR is not supported by this family of devices.
44. The Dual I/O, Quad I/O, QPI, DDR Quad I/O, and DDR QPI, command protocols include Continuous Read Mode bits following the address. The clock cycles for these
bits are not counted as part of the latency cycles shown in the table. Example: the legacy Quad I/O command has 2 Continuous Read Mode cycles following the
address. Therefore, the legacy Quad I/O command without additional read latency is supported only up to the frequency shown in the table for a read latency of 0
cycles. By increasing the variable read latency the frequency of the Quad I/O command can be increased to allow operation up to the maximum supported 133 MHz
frequency.
45. Other read commands have fixed latency, e.g. Read always has zero read latency. RSFDP always has eight cycles of latency.
46. DDR QPI is only supported for Latency Cycles 1 through 5 and for clock frequency of up to 68 MHz.
Document Number: 002-00488 Rev. *M
Page 53 of 139
S25FS512S
7.6.4.2 Configuration Register 2 Volatile (CR2V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), 4BAM.
Table 28. Configuration Register 2 Volatile (CR2V)
Bits
Field Name
Function
Type
Default
State
Description
7
AL
Address Length
1 = 4-byte address.
0 = 3-byte address.
6
QA
QPI
1 = Enabled – QPI (4-4-4) protocol in use.
0 = Disabled – Legacy SPI protocols in use, instruction is always serial on SI.
5
IO3R_S
IO3 Reset
1 = Enabled – IO3 is used as RESET# input when CS# is high or Quad Mode is
disabled CR1V[1]=0.
0 = Disabled – IO3 has no alternate function, hardware reset is disabled.
4
RFU
Reserved
Reserved for Future Use.
RL
Read Latency
0 to 15 latency (dummy) cycles following read address or continuous mode bits.
Volatile
CR2NV
3
2
1
0
Address Length CR2V[7]: This bit controls the expected address length for all commands that require address and are not fixed
3-byte only or 4-byte (32 bit) only address. See Table 45 on page 73 for command address length. This volatile Address Length
configuration bit enables the address length to be changed during normal operation. The 4-byte address mode (4BAM) command
directly sets this bit into 4-byte address mode.
QPI CR2V[6]: This bit controls the expected instruction width for all commands. This volatile QPI configuration bit enables the
device to enter and exit QPI mode during normal operation. When this bit is set to QPI mode, the QUAD bit is also set to Quad mode
(CR1V[1]=1). When this bit is cleared to legacy SPI mode, the QUAD bit is not affected.
IO3 Reset CR2V[5]: This bit controls the IO3 / RESET# signal behavior. This volatile IO3 Reset configuration bit enables the use of
IO3 as a RESET# input during normal operation.
Read Latency CR2V[3:0]: This bit controls the read latency (dummy cycle) delay in variable latency read commands These volatile
configuration bits enable the user to adjust the read latency during normal operation to optimize the latency for different commands
or, at different operating frequencies, as needed.
Document Number: 002-00488 Rev. *M
Page 54 of 139
S25FS512S
7.6.5
Configuration Register 3
Configuration Register 3 controls certain command behaviors. The register bits can be read and changed using the Read Any
Register and Write Any Register commands. The nonvolatile register provides the POR, hardware reset, or software reset state of
the controls. These configuration bits are OTP and may be programmed to their opposite state one time during system configuration
if needed. The volatile version of Configuration Register 3 allows the configuration to be changed during system operation or testing.
7.6.5.1 Configuration Register 3 Nonvolatile (CR3NV)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 29. Configuration Register 3 Nonvolatile (CR3NV)
Bits
Field Name
Function
Type
Default
State
Description
7
RFU
Reserved
0
Reserved for Future Use.
6
RFU
Reserved
0
Reserved for Future Use.
5
BC_NV
Blank Check
0
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
4
02h_NV
Page Buffer Wrap
0
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
3
20h_NV
4 KB Erase
0
1 = 4 KB Erase disabled (Uniform Sector Architecture).
0 = 4 KB Erase enabled (Hybrid Sector Architecture).
2
30h_NV
Clear Status / Resume
Select
0
1 = 30h is Erase or Program Resume command.
0 = 30h is clear status command.
1
RFU
Reserved
0
Reserved for Future Use.
F0h_NV
Legacy Software Reset
Enable
0
1 = F0h Software Reset is enabled.
0 = F0h Software Reset is disabled (ignored).
0
OTP
Blank Check Nonvolatile CR3NV[5]: This bit controls the POR, hardware reset, or software reset state of the blank check during
erase feature.
02h Nonvolatile CR3NV[4]: This bit controls the POR, hardware reset, or software reset state of the page programming buffer
address wrap point.
20h Nonvolatile CR3NV[3]: This bit controls the POR, hardware reset, or software reset state of the availability of 4-KB parameter
sectors in the main flash array address map.
30h Nonvolatile CR3NV[2]: This bit controls the POR, hardware reset, or software reset state of the 30h instruction code is used.
F0h Nonvolatile CR3NV[0]: This bit controls the POR, hardware reset, or software reset state of the availability of the Cypress
legacy FL-S family software reset instruction.
Document Number: 002-00488 Rev. *M
Page 55 of 139
S25FS512S
7.6.5.2 Configuration Register 3 Volatile (CR3V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 30. Configuration Register 3 Volatile (CR3V)
Bits
Field Name
Function
Type
Default
State
Description
7
RFU
Reserved
Reserved for Future Use.
6
RFU
Reserved
Reserved for Future Use.
5
BC_V
Blank Check
4
02h_V
Page Buffer Wrap
3
20h_V
4 KB Erase
2
30h_V
Clear Status / Resume
Select
1
RFU
Reserved
F0h_V
Legacy Software Reset
Enable
0
1 = Blank Check during erase enabled.
0 = Blank Check disabled.
Volatile
1 = Wrap at 512 bytes.
0 = Wrap at 256 bytes.
Volatile,
Read Only
CR3NV
1 = 4 KB Erase disabled (Uniform Sector Architecture).
0 = 4 KB Erase enabled (Hybrid Sector Architecture).
1 = 30h is Erase or Program Resume command.
0 = 30h is clear status command.
Volatile
Reserved for Future Use.
1= F0h Software Reset is enabled .
0= F0h Software Reset is disabled (ignored).
Blank Check Volatile CR3V[5]: This bit controls the blank check during erase feature. When this feature is enabled an erase
command first evaluates the erase status of the sector. If the sector is found to have not completed its last erase successfully, the
sector is unconditionally erased. If the last erase was successful, the sector is read to determine if the sector is still erased (blank).
The erase operation is started immediately after finding any programmed zero. If the sector is already blank (no programmed zero
bit found) the remainder of the erase operation is skipped. This can dramatically reduce erase time when sectors being erased do
not need the erase operation. When enabled the blank check feature is used within the parameter erase, sector erase, and bulk
erase commands. When blank check is disabled an erase command unconditionally starts the erase operation.
02h Volatile CR3V[4]: This bit controls the page programming buffer address wrap point. Legacy SPI devices generally have used
a 256-byte page programming buffer and defined that if data is loaded into the buffer beyond the 255-byte location, the address at
which additional bytes are loaded would be wrapped to address zero of the buffer. The S25FS512S provides a 512-byte page
programming buffer that can increase programming performance. For legacy software compatibility, this configuration bit provides
the option to continue the wrapping behavior at the 256-byte boundary or to enable full use of the available 512-byte buffer by not
wrapping the load address at the 256-byte boundary.
20h Volatile CR3V[3]: This bit controls the availability of 4-KB parameter sectors in the main flash array address map. The
parameter sectors can overlay the highest or lowest 32-KB address range of the device or they can be removed from the address
map so that all sectors are uniform size. This bit shall not be written to a value different than the value of CR3NV[3]. The value of
CR3V[3] may only be changed by writing CR3NV[3].
30h Volatile CR3V[2]: This bit controls how the 30h instruction code is used. The instruction may be used as a clear status
command or as an alternate program / erase resume command. This allows software compatibility with either Cypress legacy SPI
devices or alternate vendor devices.
F0h Volatile CR3V[0]: This bit controls the availability of the Cypress legacy FL-S family software reset instruction. The S25FS512S
supports the industry common 66h + 99h instruction sequence for software reset. This configuration bit allows the option to continue
use of the legacy F0h single command for software reset.
Document Number: 002-00488 Rev. *M
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S25FS512S
7.6.6
Configuration Register 4
Configuration Register 4 controls the main flash array read commands burst wrap behavior. The burst wrap configuration does not
affect commands reading from areas other than the main flash array e.g. read commands for registers or OTP array. The nonvolatile
version of the register provides the ability to set the start up (boot) state of the controls as the contents are copied to the volatile
version of the register during the POR, hardware reset, or software reset. The volatile version of the register controls the feature
behavior during normal operation. The register bits can be read and changed using the Read Any Register and Write Any Register
commands. The volatile version of the register can also be written by the Set Burst Length (C0h) command.
7.6.6.1 Configuration Register 4 Nonvolatile (CR4NV)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).
Table 31. Configuration Register 4 Nonvolatile (CR4NV)
Bits
Field Name
Function
Type
7
6
Description
0
OI_O
Output Impedance
0
5
See Table 32 on page 57.
0
4
WE_O
3
RFU
Reserved
2
RFU
Reserved
Wrap Enable
OTP
1
0
Default
State
WL_O
Wrap Length
1
0 = Wrap Enabled
1 = Wrap Disabled
0
Reserved for Future Use
0
Reserved for Future Use
0
00 = 8-byte wrap
01 = 16-byte wrap
10 = 32-byte wrap
11 = 64-byte wrap
0
Output Impedance Nonvolatile CR4NV[7:5]: These bits control the POR, hardware reset, or software reset state of the IO signal
output impedance (drive strength). Multiple drive strength are available to help match the output impedance with the system printed
circuit board environment to minimize overshoot and ringing. These nonvolatile output impedance configuration bits enable the
device to start immediately (boot) with the appropriate drive strength.
Table 32. Output Impedance Control
CR4NV[7:5]
Impedance Selection
Typical Impedance to VSS
(Ohms)
Typical Impedance to VCC
(Ohms)
Notes
000
47
45
Factory Default
001
124
105
–
010
71
64
–
011
47
45
–
100
34
35
–
101
26
28
–
110
22
24
–
111
18
21
–
Wrap Enable Nonvolatile CR4NV[4]: This bit controls the POR, hardware reset, or software reset state of the wrap enable. The
commands affected by Wrap Enable are: Quad I/O Read, and DDR Quad I/O Read. This configuration bit enables the device to start
immediately (boot) in wrapped burst read mode rather than the legacy sequential read mode.
Wrap Length Nonvolatile CR4NV[1:0]: These bits controls the POR, hardware reset, or software reset state of the wrapped read
length and alignment. These nonvolatile configuration bits enable the device to start immediately (boot) in wrapped burst read mode
rather than the legacy sequential read mode.
Document Number: 002-00488 Rev. *M
Page 57 of 139
S25FS512S
7.6.6.2 Configuration Register 4 Volatile (CR4V)
Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h), Set Burst Length (SBL C0h).
Table 33. Configuration Register 4 Volatile (CR4V)
Bits
Field Name
Function
Default
State
Type
Description
7
6
OI
Output Impedance
See Table 32 on page 57.
4
WE
Wrap Enable
0 = Wrap Enabled
1 = Wrap Disabled
3
RFU
Reserved
2
RFU
Reserved
Reserved for Future Use
Wrap Length
00 = 8-byte wrap
01 = 16-byte wrap
10 = 32-byte wrap
11 = 64-byte wrap
5
Volatile
CR4NV
1
0
WL
Reserved for Future Use
Output Impedance CR2V[7:5]: These bits control the IO signal output impedance (drive strength). This volatile output impedance
configuration bit enables the user to adjust the drive strength during normal operation.
Wrap Enable CR4V[4]: This bit controls the burst wrap feature. This volatile configuration bit enables the device to enter and exit
burst wrapped read mode during normal operation.
Wrap Length CR4V[1:0]: These bits controls the wrapped read length and alignment during normal operation. These volatile
configuration bits enable the user to adjust the burst wrapped read length during normal operation.
7.6.7
ECC Status Register (ECCSR)
Related Commands: ECC Read (ECCRD 18h or 19h). ECCSR does not have user programmable nonvolatile bits, all defined bits
are volatile read only status. The default state of these bits are set by hardware.
The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read command is
written followed by an ECC unit address. The contents of the status register then indicates, for the selected ECC unit, whether there
is an error in the ECC, the ECC unit data, or that ECC is disabled for that ECC unit.
Table 34. ECC Status Register (ECCSR)
Bits
Field Name
7 to 3
RFU
2
EECC
1
0
Function
Type
Reserved
Default State
Description
0
Reserved for Future Use
Error in ECC
Volatile, Read only
0
1 = Single Bit Error found in the ECC unit error
correction code
0 = No error.
EECCD
Error in ECC unit data
Volatile, Read only
0
1 = Single Bit Error corrected in ECC unit data.
0 = No error.
ECCDI
ECC Disabled
Volatile, Read only
0
1 = ECC is disabled in the selected ECC unit.
0 = ECC is enabled in the selected ECC unit.
ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC unit data.
ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures and ECC is enabled.
The ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to another.
These bits should be treated as “don’t care” and ignored by any software reading status.
Document Number: 002-00488 Rev. *M
Page 58 of 139
S25FS512S
7.6.8
ASP Register (ASPR)
Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh), Read Any Register (RDAR 65h), Write Any Register
(WRAR 71h).
The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP)
features. ASPR does not have user programmable volatile bits, all defined bits are OTP.
The default state of the ASPR bits are programmed by Cypress.
Table 35. ASP Register (ASPR)
Type
Default
State
Reserved
OTP
1
Reserved for Future Use
Reserved
OTP
1
Reserved for Future Use
RFU
Reserved
OTP
1
Reserved for Future Use
RFU
Reserved
OTP
1
Reserved for Future Use
5
RFU
Reserved
OTP
1
Reserved for Future Use
4
RFU
Reserved
OTP
1
Reserved for Future Use
3
RFU
Reserved
OTP
1
Reserved for Future Use
Bits
Field Name
15 to 9
RFU
8
RFU
7
6
Function
Description
2
PWDMLB
Password Protection Mode Lock Bit
OTP
1
0 = Password Protection Mode permanently enabled.
1 = Password Protection Mode not permanently enabled.
1
PSTMLB
Persistent Protection Mode Lock Bit
OTP
1
0 = Persistent Protection Mode permanently enabled.
1 = Persistent Protection Mode not permanently enabled.
0
RFU
Reserved
RFU
1
Reserved for Future Use
Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password Protection Mode is
permanently selected.
Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent Protection Mode is
permanently selected.
PWDMLB (ASPR[2]) and PSTMLB (ASPR[1]) are mutually exclusive, only one may be programmed to zero.
ASPR bits may only be programmed while ASPR[2:1] = 11b. Attempting to program ASPR bits when ASPR[2:1] is not = 11b will
result in a programming error with P_ERR (SR1V[6]) set to 1. After the ASP protection mode is selected by programming ASPR[2:1]
= 10b or 01b, the state of all ASPR bits are locked and permanently protected from further programming. Attempting to program
ASPR[2:1] = 00b will result in a programming error with P_ERR (SR1V[6]) set to 1.
Similarly, OTP configuration bits listed in the ASP Register description (ASP Register on page 66), may only be programmed while
ASPR[2:1] = 11b. The OTP configuration must be selected before selecting the ASP protection mode. The OTP configuration bits
are permanently protected from further change when the ASP protection mode is selected. Attempting to program these OTP
configuration bits when ASPR[2:1] is not = 11b will result in a programming error with P_ERR (SR1V[6]) set to 1.
The ASP protection mode should be selected during system configuration to ensure that a malicious program does not select an
undesired protection mode at a later time. By locking all the protection configuration via the ASP mode selection, later alteration of
the protection methods by malicious programs is prevented.
Document Number: 002-00488 Rev. *M
Page 59 of 139
S25FS512S
7.6.9
Password Register (PASS)
Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h), Read Any Register (RDAR 65h), Write
Any Register (WRAR 71h). The PASS register is a 64-bit OTP memory location used to permanently define a password for the
Advanced Sector Protection (ASP) feature. PASS does not have user programmable volatile bits, all defined bits are OTP. A volatile
copy of PASS is used to satisfy read latency requirements but the volatile register is not user writable or further described.
Table 36. Password Register (PASS)
Bits
Field
Name
63 to 0
PWD
Function
Type
Hidden
Password
Default State
Description
Nonvolatile OTP storage of 64-bit password. The password is no
FFFFFFFF-FFFFFFFFh longer readable after the password protection mode is selected by
programming ASP register bit 2 to zero.
OTP
7.6.10 PPB Lock Register (PPBL)
Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h), Read Any Register (RDAR 65h).
PPBL does not have separate user programmable nonvolatile bits, all defined bits are volatile read only status. The default state of
the RFU bits is set by hardware. The default state of the PPBLOCK bit is defined by the ASP protection mode bits in ASPR[2:1].
There is no nonvolatile version of the PPBL register.
The PPBLOCK bit is used to protect the PPB bits. When PPBL[0] = 0, the PPB bits can not be programmed.
Table 37. PPB Lock Register (PPBL)
Bits
Field Name
7 to 1
RFU
0
Function
Reserved
PPBLOCK Protect PPB Array
Type
Volatile
Default State
00h
Description
Reserved for Future Use
ASPR[2:1] = 1xb =
Persistent Protection Mode = 1
Volatile
Read Only ASPR[2:1] = 01b =
Password Protection Mode = 0
0 = PPB array protected
1 = PPB array may be programmed or erased.
7.6.11 PPB Access Register (PPBAR)
Related Commands: PPB Read (PPBRD FCh or 4PPBRD E2h), PPB Program (PPBP FDh or 4PPBP E3h), PPB Erase (PPBE
E4h).
PPBAR does not have user writable volatile bits, all PPB array bits are nonvolatile. The default state of the PPB array is erased to
FFh by Cypress. There is no volatile version of the PPBAR register.
Table 38. PPB Access Register (PPBAR)
Bits
Field Name
7 to 0
PPB
Function
Type
Default State
Description
FFh
00h = PPB for the sector addressed by the PPBRD or PPBP command is
programmed to 0, protecting that sector from program or erase operations.
FFh = PPB for the sector addressed by the PPBRD command is 1, not
protecting that sector from program or erase operations.
Read or Program
Nonvolatile
per sector PPB
7.6.12 DYB Access Register (DYBAR)
Related Commands: DYB Read (DYBRD FAh or 4DYBRD E0h) and DYB Write (DYBWR FBh or 4DYBWR E1h).
DYBAR does not have user programmable nonvolatile bits, all bits are a representation of the volatile bits in the DYB array. The
default state of the DYB array bits is set by hardware. There is no nonvolatile version of the DYBAR register.
Table 39. DYB Access Register (DYBAR)
Bits Field Name
7 to 0
DYB
Function
Type
Read or Write
Volatile
per sector DYB
Document Number: 002-00488 Rev. *M
Default State
Description
FF
00h = DYB for the sector addressed by the DYBRD or DYBWR command is
cleared to 0, protecting that sector from program or erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBWR command is set to
1, not protecting that sector from program or erase operations.
Page 60 of 139
S25FS512S
7.6.13 SPI DDR Data Learning Registers
Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read (DLPRD 41h), Read
Any Register (RDAR 65h), Write Any Register (WRAR 71h).
The Data Learning Pattern (DLP) resides in an 8-bit nonvolatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data
Learning Register (VDLR). When shipped from Cypress, the NVDLR value is 00h. Once programmed, the NVDLR cannot be
reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR. The VDLR can be written to at
any time, but on power cycles the data pattern will revert back to what is in the NVDLR. During the learning phase described in the
SPI DDR modes, the DLP will come from the VDLR. Each IO will output the same DLP value for every clock edge. For example, if
the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0; subsequently, the 2nd clock edge all I/O’s
will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands.
Table 40. Nonvolatile Data Learning Register (NVDLR)
Bits
7 to 0
Field Name
NVDLP
Function
Nonvolatile Data
Learning Pattern
Type
Default State
OTP
00h
Description
OTP value that may be transferred to the host during DDR read
command latency (dummy) cycles to provide a training pattern to help
the host more accurately center the data capture point in the received
data bits.
Table 41. Volatile Data Learning Register (VDLR)
Bits
7 to 0
Field Name
VDLP
Function
Volatile Data
Learning Pattern
Document Number: 002-00488 Rev. *M
Type
Volatile
Default State
Description
Takes the value
Volatile copy of the NVDLP used to enable and deliver the Data Learning
of NVDLR
Pattern (DLP) to the outputs. The VDLP may be changed by the host
during POR or
during system operation.
Reset
Page 61 of 139
S25FS512S
8.
8.1
Data Protection
Secure Silicon Region (OTP)
The device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash array. The OTP area is
divided into 32, individually lockable, 32-byte aligned and length regions.
The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with the system
CPU/ASIC to prevent device substitution. See OTP Address Space on page 44, OTP Program (OTPP 42h) on page 105, and OTP
Read (OTPR 4Bh) on page 106.
8.1.1
Reading OTP Memory Space
The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-KB OTP address range
will yield indeterminate data.
8.1.2
Programming OTP Memory Space
The protocol of the OTP programming command is the same as Page Program. The OTP Program command can be issued multiple
times to any given OTP address, but this address space can never be erased.
Automatic ECC is programmed on the first programming operation to each 16 byte region. Programming within a 16 byte region
more than once disables the ECC. It is recommended to program each 16 byte portion of each 32 byte region once so that ECC
remains enabled to provide the best data integrity.
The valid address range for OTP Program is depicted in Figure 42 on page 44. OTP Program operations outside the valid OTP
address range will be ignored, without P_ERR in SR1V set to 1. OTP Program operations within the valid OTP address range, while
FREEZE = 1, will fail with P_ERR in SR1V set to 1. The OTP address space is not protected by the selection of an ASP protection
mode. The Freeze bit (CR1V[0]) may be used to protect the OTP Address Space.
8.1.3
Cypress Programmed Random Number
Cypress standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit
random number using the Linear Congruential Random Number Method. The seed value for the algorithm is a random number
concatenated with the day and time of tester insertion.
8.1.4
Lock Bytes
The LSb of each Lock byte protects the lowest address region related to the byte, the MSb protects the highest address region
related to the byte. The next higher address byte similarly protects the next higher eight regions. The LSb bit of the lowest address
Lock Byte protects the higher address 16 bytes of the lowest address region. In other words, the LSb of location 0x10 protects all the
Lock Bytes and RFU bytes in the lowest address region from further programming. See OTP Address Space on page 44.
Document Number: 002-00488 Rev. *M
Page 62 of 139
S25FS512S
8.2
Write Enable Command
The Write Enable (WREN) command must be written prior to any command that modifies nonvolatile data. The WREN command
sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes) during power-up, hardware reset, or after the
device completes the following commands:
■
Reset
■
Page Program (PP or 4PP)
■
Parameter 4-KB Erase (P4E or 4P4E)
■
Sector Erase (SE or 4SE)
■
Bulk Erase (BE)
■
Write Disable (WRDI)
■
Write Registers (WRR)
■
Write Any Register (WRAR)
■
OTP Byte Programming (OTPP)
■
Advanced Sector Protection Register Program (ASPP)
■
Persistent Protection Bit Program (PPBP)
■
Persistent Protection Bit Erase (PPBE)
■
Password Program (PASSP)
■
Program Nonvolatile Data Learning Register (PNVDLR)
8.3
Block Protection
The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register TBPROT_O bit can be
used to protect an address range of the main flash array from program and erase operations. The size of the range is determined by
the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT_O bit of the configuration
register (CR1NV[5]).
Table 42. Upper Array Start of Protection (TBPROT_O = 0)
Status Register Content
Protected Fraction of
Memory Array
Protected Memory (KB)
FS512S
512 Mb
BP2
BP1
BP0
0
0
0
None
0
0
0
1
Upper 64th
1024
0
1
0
Upper 32nd
2048
0
1
1
Upper 16th
4096
1
0
0
Upper 8th
8192
1
0
1
Upper 4th
16384
1
1
0
Upper Half
32768
1
1
1
All Sectors
65536
Document Number: 002-00488 Rev. *M
Page 63 of 139
S25FS512S
Table 43. Lower Array Start of Protection (TBPROT_O = 1)
Status Register Content
Protected Fraction of
Memory Array
Protected Memory (KB)
FS512S
512 Mb
BP2
BP1
BP0
0
0
0
None
0
0
0
1
Lower 64th
1024
0
1
0
Lower 32nd
2048
0
1
1
Lower 16th
4096
1
0
0
Lower 8th
8192
1
0
1
Lower 4th
16384
1
1
0
Lower Half
32768
1
1
1
All Sectors
65536
When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still be used to protect
sectors not protected by the Block Protection scheme. In the case that both ASP and Block Protection are used on the same sector
the logical OR of ASP and Block Protection related to the sector is used.
8.3.1
Freeze Bit
Bit 0 of Configuration Register 1 (CR1V[0]) is the FREEZE bit. The Freeze Bit, when set to 1, locks the current state of the Block
Protection control bits and OTP area until the next power off-on cycle. Additional details in Configuration Register 1 Volatile (CR1V)
on page 50
8.3.2
Write Protect Signal
The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit (SR1NV[7]) provide hardware input
signal controlled protection. When WP# is Low and SRWD is set to 1 Status Register-1 (SR1NV and SR1V) and Configuration
Register 1 (CR1NV and CR1V) are protected from alteration. This prevents disabling or changing the protection defined by the Block
Protect bits. See Table 22 on page 47.
8.4
Advanced Sector Protection
Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software methods used to disable or
enable programming or erase operations, individually, in any or all sectors.
Every main flash array sector has a nonvolatile Persistent Protection Bit (PPB) and a volatile Dynamic Protection Bit (DYB)
associated with it. When either bit is 0, the sector is protected from program and erase operations. The PPB bits are protected from
program and erase when the volatile PPB Lock bit is 0. There are two methods for managing the state of the PPB Lock bit:
Password Protection, and Persistent Protection. An overview of these methods is shown in Figure 44 on page 65.
Block Protection and ASP protection settings for each sector are logically ORed to define the protection for each sector i.e. if either
mechanism is protecting a sector the sector cannot be programmed or erased. Refer to Block Protection on page 63 for full details of
the BP2-0 bits.
Document Number: 002-00488 Rev. *M
Page 64 of 139
S25FS512S
Figure 43. Sector Protection Control
Dynamic
Protection
Bits Array
(DYB)
Sector 0
Sector 1
Sector 1
Sector 0
Sector 1
...
Logical OR
...
...
Block
Protection
Logic
Sector N
Sector N
...
Sector 0
Logical OR
Flash
Memory
Array
Logical OR
Persistent
Protection
Bits Array
(PPB)
Sector N
Figure 44. Advanced Sector Protection Overview
Power On / Reset
ASPR[2]=0
ASPR[1]=0
No
No
Yes
Yes
Password Protection
Persistent Protection
ASPR Bits Locked
ASPR Bits Locked
PPBLOCK = 0
PPB Bits Locked
PPBLOCK = 1
PPB Bits Erasable
and Programmable
No
Password Unlock
Yes
PPBLOCK = 1
PPB Bits Erasable
and Programmable
Default
Persistent Protection
ASPR Bits Are
Programmable
No
PPB Lock Bit Write
Yes
PPBLOCK = 0
PPB Bits Locked
No
PPB Lock Bit Write
Default Mode allows
ASPR to be programmed
to permanently select the
Protection mode.
Yes
Password Protection
Mode protects the
PPB after power up.
A password unlock
command will enable
changes to PPB. A
PPB Lock Bit write
command turns
protection back on.
Document Number: 002-00488 Rev. *M
Persistent Protection
Mode does not protect
the PPB after power
up. The PPB bits may
be changed. A PPB
Lock Bit write command
protects the PPB bits
until the next power off
or reset.
The default mode otherwise
acts the same as the
Persistent Protection Mode.
After one of the protection
modes is selected, ASPR is
no longer programmable,
making the selected
protection mode permanent.
Page 65 of 139
S25FS512S
The Persistent Protection method sets the PPB Lock bit to 1 during POR, or Hardware Reset so that the PPB bits are unprotected by
a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB. There is no command in the Persistent
Protection method to set the PPB Lock bit to 1, therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.
The Persistent Protection method allows boot code the option of changing sector protection by programming or erasing the PPB,
then protecting the PPB from further change for the remainder of normal system operation by clearing the PPB Lock bit to 0. This is
sometimes called Boot-code controlled sector protection.
The Password method clears the PPB Lock bit to 0 during POR, or Hardware Reset to protect the PPB. A 64-bit password may be
permanently programmed and hidden for the password method. A command can be used to provide a password for comparison with
the hidden password. If the password matches, the PPB Lock bit is set to 1 to unprotect the PPB. A command can be used to clear
the PPB Lock bit to 0. This method requires use of a password to control PPB protection.
The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so as to permanently
select the method used.
8.4.1
ASP Register
The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features. See Table 35 on
page 59.
As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors unprotected, when power is
applied. The device programmer or host system must then choose which sector protection method to use. Programming either of
the, one-time programmable, Protection Mode Lock Bits, locks the part permanently in the selected mode:
ASPR[2:1] = ‘11’ = No ASP mode selected, Persistent Protection Mode is the default.
ASPR[2:1] = ‘10’ = Persistent Protection Mode permanently selected.
ASPR[2:1] = ‘01’ = Password Protection Mode permanently selected.
ASPR[2:1] = ‘00’ is an Illegal condition, attempting to program more than one bit to zero results in a programming failure.
ASP register programming rules:
If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock Bits.
Once the Protection Mode is selected, the following OTP configuration register bits are permanently protected from programming
and no further changes to the OTP register bits is allowed:
CR1NV[5:2]
CR2NV
❐ CR3NV
❐ CR4NV
❐ ASPR
❐ PASS
❐ NVDLR
❐ If an attempt to change any of the registers above, after the ASP mode is selected, the operation will fail and P_ERR (SR1V[6])
will be set to 1.
The programming time of the ASP Register is the same as the typical page programming time. The system can determine the status
of the ASP register programming operation by reading the WIP bit in the Status Register. See Table 21 on page 46 for information
on WIP. See Sector Protection States Summary on page 67.
❐
❐
Document Number: 002-00488 Rev. *M
Page 66 of 139
S25FS512S
8.4.2
Persistent Protection Bits
The Persistent Protection Bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is related to each sector.
When a PPB is 0, its related sector is protected from program and erase operations. The PPB are programmed individually but must
be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased
at the same time. The PPB have the same program and erase endurance as the main flash memory array. Preprogramming and
verification prior to erasure are handled by the device.
Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical sector erase time. During
PPB bit programming and PPB bit erasing, status is available by reading the Status register. Reading of a PPB bit requires the initial
access time of the device.
Notes
Each PPB is individually programmed to 0 and all are erased to 1 in parallel.
If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails without programming or erasing the
PPB.
The state of the PPB for a given sector can be verified by using the PPB Read command.
8.4.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYB only control the protection for
sectors that have their PPB set to 1. By issuing the DYB Write command, a DYB is cleared to 0 or set to 1, thus placing each sector
in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes,
yet does not prevent the easy removal of protection when changes are needed. The DYBs can be set or cleared as often as needed
as they are volatile bits.
8.4.4
PPB Lock Bit (PPBL[0])
The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs, when set to 1, it allows the PPBs to
be changed. See PPB Lock Register (PPBL) on page 60 for more information.
The PLBWR command is used to clear the PPB Lock bit to 0. The PPB Lock Bit must be cleared to 0 only after all the PPBs are
configured to the desired settings.
In Persistent Protection mode, the PPB Lock is set to 1 during POR or a hardware reset. When cleared to 0, no software command
sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can set the PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or a hardware reset. The PPB Lock bit can only be
set to 1 by the Password Unlock command.
8.4.5
Sector Protection States Summary
Each sector can be in one of the following protection states:
Unlocked — The sector is unprotected and protection can be changed by a simple command. The protection state defaults to
unprotected when the device is shipped from Cypress.
Dynamically Locked — A sector is protected and protection can be changed by a simple command. The protection state is not
saved across a power cycle or reset.
Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock Bit is set to 1. The protection
state is nonvolatile and saved across a power cycle or reset. Changing the protection state requires programming and or erase of
the PPB bits.
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S25FS512S
Table 44. Sector Protection States
Protection Bit Values
Sector State
PPB Lock
PPB
DYB
1
1
1
Unprotected – PPB and DYB are changeable
1
1
0
Protected – PPB and DYB are changeable
1
0
1
Protected – PPB and DYB are changeable
1
0
0
Protected – PPB and DYB are changeable
0
1
1
Unprotected – PPB not changeable, DYB is changeable
0
1
0
Protected – PPB not changeable, DYB is changeable
0
0
1
Protected – PPB not changeable, DYB is changeable
0
0
0
Protected – PPB not changeable, DYB is changeable
8.4.6
Persistent Protection Mode
The Persistent Protection method sets the PPB Lock bit to 1 during POR or Hardware Reset so that the PPB bits are unprotected by
a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR command can clear the PPB Lock bit to 0 to
protect the PPB. There is no command to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or
hardware reset.
8.4.7
Password Protection Mode
Password Protection Mode allows an even higher level of security than the Persistent Sector Protection Mode, by requiring a 64-bit
password for unlocking the PPB Lock bit. In addition to this password requirement, after power up and hardware reset, the PPB Lock
bit is cleared to 0 to ensure protection at power-up. Successful execution of the Password Unlock command by entering the entire
password sets the PPB Lock bit to 1, allowing for sector PPB modifications.
Password Protection Notes:
Once the Password is programmed and verified, the Password Mode (ASPR[2]=0) must be set in order to prevent reading the
password.
The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results
in the cell left as a 0 with no programming error set.
The password is all 1s when shipped from Cypress. It is located in its own memory space and is accessible through the use of the
Password Program, Password Read, RDAR, and WRAR commands.
All 64-bit password combinations are valid as a password.
The Password Mode, once programmed, prevents reading the 64-bit password and further password programming. All further
program and read commands to the password region are disabled and these commands are ignored or return undefined data.
There is no means to verify what the password is after the Password Mode Lock Bit is selected. Password verification is only
allowed before selecting the Password Protection mode.
The Protection Mode Lock Bits are not erasable.
The exact password must be entered in order for the unlocking function to occur. If the password unlock command provided
password does not match the hidden internal password, the unlock operation fails in the same manner as a programming
operation on a protected sector. The P_ERR bit is set to one, the WIP Bit remains set, and the PPB Lock bit remains cleared to 0.
The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an
unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a
password. The Read Status Register 1 command may be used to read the WIP bit to determine when the device has completed
the password unlock command or is ready to accept a new password command. When a valid password is provided the
password unlock command does not insert the 100 µs delay before returning the WIP bit to zero.
If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.
ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced to the boot sector
address. ECC status is only in that sector while read protection mode is active.
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S25FS512S
8.5
Recommended Protection Process
During system manufacture, the flash device configuration should be defined by:
Programming the OTP configuration bits in CR1NV[5, 3:2], CR2NV, CR3NV, and CR4NV as desired.
Program the Secure Silicon Region (OTP area) as desired.
Program the PPB bits as desired via the PPBP command.
Program the NVDLR if it will be used in DDR read commands.
Program the Password register (PASS) if password protection will be used.
Program the ASP Register as desired, including the selection of the persistent or password ASP protection mode in ASPR[2:1]. It
is very important to explicitly select a protection mode so that later accidental or malicious programming of the ASP register and
OTP configuration is prevented. This is to ensure that only the intended OTP protection and configuration features are enabled.
During system power up and boot code execution:
Trusted boot code can determine whether there is any need to program additional SSR (OTP area) information. If no SSR
changes are needed the FREEZE bit (CR1V[0]) can be set to 1 to protect the SSR from changes during the remainder of normal
system operation while power remains on.
If the persistent protection mode is in use, trusted boot code can determine whether there is any need to modify the persistent
(PPB) sector protection via the PPBP or PPBE commands. If no PPB changes are needed the PPBLOCK bit can be cleared to 0
via the PPBL to protect the PPB bits from changes during the remainder of normal system operation while power remains on.
The dynamic (DYB) sector protection bits can be written as desired via the DYBAR.
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S25FS512S
9.
Commands
All communication between the host system and S25FS512S memory devices is in the form of units called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands
may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All
instruction, address, and data information is transferred sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three
command phases:
instruction
address and instruction modifier (mode)
data
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI signal. Data may be
sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol for single bit width instruction, single
bit width address and modifier, single bit data.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four-bit (nibble)
groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four-bit (nibble) groups on
IO0, IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command protocols.
The S25FS512S also supports a QPI mode in which all information is transferred in 4-bit width, including the instruction, address,
modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
■
Each command begins with an eight bit (byte) instruction. However, some read commands are modified by a prior read command,
such that the instruction is implied from the earlier command. This is called Continuous Read Mode. When the device is in continuous
read mode, the instruction bits are not transmitted at the beginning of the command because the instruction is the same as the read
command that initiated the Continuous Read Mode. In Continuous Read mode the command will begin with the read address. Thus,
Continuous Read Mode removes eight instruction bits from each read command in a series of same type read commands.
■
The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in
the device. The address may be either a 24-bit or 32-bit, byte boundary, address.
■
The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data information to be done
one, two, or four bits in parallel. This enables a trade off between the number of signal connections (IO bus width) and the speed
of information transfer. If the host system can support a two or four bit wide IO bus the memory performance can be increased by
using the instructions that provide parallel two bit (dual) or parallel four bit (quad) transfers.
■
In legacy SPI Multiple IO mode, the width of all transfers following the instruction are determined by the instruction sent. Following
transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per
(dual) transfer on the IO0 and IO1 signals, or they may be done in 4-bit groups per (quad) transfer on the IO0-IO3 signals. Within
the dual or quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher
numbered IO signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
■
In QPI mode, the width of all transfers, including instructions, is a 4-bit wide (quad) transfer on the IO0-IO3 signals.
■
Dual I/O and Quad I/O read instructions send an instruction modifier called mode bits, following the address, to indicate that the
next command will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide
an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same
command type is repeated in a sequence of commands.
■
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read
data is returned to the host.
■
Read latency may be zero to several SCK cycles (also referred to as dummy cycles).
■
All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted into the device with the
most significant byte first. All data is transferred with the lowest address byte sent first. Following bytes of data are sent in lowest
to highest byte address order i.e. the byte address increments.
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S25FS512S
■
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The
embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded
operation. These are discussed in the individual command descriptions. While a program, erase, or write operation is in progress,
it is recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the device, to ensure the
new command can be accepted.
■
Depending on the command, the time for execution varies. A command to read status information from an executing command is
available to determine when the command completes execution and whether the command was successful.
■
Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host system
and the memory device generally handle the details of signal relationships and timing. For this reason, signal relationships and
timing are not covered in detail within this software interface focused section of the document. Instead, the focus is on the logical
sequence of bits transferred in each command rather than the signal timing and relationships. Following are some general signal
relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of
commands, see Section 3.2 Command Protocol on page 13.
❐ The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) – SI for single bit wide transfers. The
memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive the IO0-IO3 signals during
Dual and Quad transfers.
❐ All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept low
throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for eight bit transfer
multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned high not at an 8-bit
boundary.
9.1
Command Set Summary
9.1.1
Extended Addressing
To accommodate addressing above 128 Mb, there are two options:
1. Instructions that always require a 4-byte address, used to access up to 32 Gb of memory.
Command Name
Function
Instruction (Hex)
4READ
Read
13
4FAST_READ
Read Fast
0C
4DIOR
Dual I/O Read
BC
4QIOR
Quad I/O Read
EC
4DDRQIOR
DDR Quad I/O Read
EE
4PP
Page Program
12
4P4E
Parameter 4-KB Erase
21
4SE
Erase 64 / 256 KB
DC
4ECCRD
ECC Status Read
18
4DYBRD
DYB Read
E0
4DYBWR
DYBWR
E1
4PPBRD
PPB Read
E2
4PPBP
PPB Program
E3
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S25FS512S
2. A 4-byte address mode for backward compatibility to the 3-byte address instructions. The standard 3-byte instructions
can be used in conjunction with a 4-byte address mode controlled by the Address Length configuration bit (CR2V[7]). The
default value of CR2V[7] is loaded from CR2NV[7] (following power up, hardware reset, or software reset), to enable
default 3-byte (24-bit) or 4-byte (32 bit) addressing. When the address length (CR2V[7]) set to 1, the legacy commands
are changed to require 4 bytes (32-bits) for the address field. The following instructions can be used in conjunction with
the 4-byte address mode configuration to switch from 3 bytes to 4 bytes of address field.
Command Name
Function
Instruction (Hex)
READ
Read
03
FAST_READ
Read Fast
0B
DIOR
Dual I/O Read
BB
QIOR
Quad I/O Read
EB
DDRQIOR
DDR Quad I/O Read)
ED
PP
Page Program
02
P4E
Parameter 4 KB Erase
20
SE
Erase 256 KB
D8
RDAR
Read Any Register
65
WRAR
Write Any Register
71
EES
Evaluate Erase Status
D0
OTPP
OTP Program
42
OTPR
OTP Read
4B
ECCRD
ECC Status Read
19
DYBRD
DYB Read
FA
DYBWR
DYBWR
FB
PPBRD
PPB Read
FC
PPBP
PPB Program
FD
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S25FS512S
9.1.2
Command Summary by Function
Table 45. S25FS512S Command Set (sorted by function)
Function
Read
Device ID
Register
Access
Command Name
Command Description
Instruction
Value (Hex)
Maximum
Frequency
(MHz)
Address
Length
(Bytes)
QPI
RDID
Read ID (JEDEC Manufacturer ID and JEDEC CFI)
9F
133
0
Yes
RSFDP
Read JEDEC Serial Flash Discoverable Parameters
5A
50
3
Yes
RDQID
Read Quad ID
AF
133
0
Yes
RDSR1
Read Status Register 1
05
133
0
Yes
RDSR2
Read Status Register 2
07
133
0
No
RDCR
Read Configuration Register 1
35
133
0
No
RDAR
Read Any Register
65
133
3 or 4
Yes
WRR
Write Register (Status 1, Configuration 1)
01
133
0
Yes
WRDI
Write Disable
04
133
0
Yes
WREN
Write Enable
06
133
0
Yes
WRAR
Write Any Register
71
133
3 or 4
Yes
CLSR
Clear Status Register 1 — Erase / Program Fail Reset
This command may be disabled and the instruction value
instead used for a program / erase resume command - see
Configuration Register 3 on page 55
30
133
0
Yes
CLSR
Clear Status Register 1 (Alternate instruction) —
Erase / Program Fail Reset
82
133
0
Yes
4BAM
Enter 4-byte Address Mode
B7
133
0
No
SBL
Set Burst Length
C0
133
0
No
EES
Evaluate Erase Status
D0
133
3 or 4
Yes
ECCRD
ECC Read
19
133
3 or 4
Yes
4ECCRD
ECC Read
18
133
4
Yes
DLPRD
Data Learning Pattern Read
41
133
0
No
PNVDLR
Program NV Data Learning Register
43
133
0
No
WVDLR
Write Volatile Data Learning Register
4A
133
0
No
READ
Read
03
50
3 or 4
No
4READ
Read
13
50
4
No
FAST_READ
Fast Read
0B
133
3 or 4
No
4FAST_READ
Fast Read
0C
133
4
No
Dual I/O Read
BB
66
3 or 4
No
Dual I/O Read
BC
66
4
No
Quad I/O Read
EB
133
3 or 4
Yes
4QIOR
Quad I/O Read
EC
133
4
Yes
DDRQIOR
DDR Quad I/O Read
ED
80
3 or 4
Yes
4DDRQIOR
DDR Quad I/O Read
EE
80
4
Yes
PP
Page Program
02
133
3 or 4
Yes
Page Program
12
133
4
Yes
Read Flash DIOR
Array
4DIOR
QIOR
Program
Flash Array 4PP
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S25FS512S
Table 45. S25FS512S Command Set (sorted by function) (Continued)
Function
Command Name
P4E
One Time
Program
Array
Advanced
Sector
Protection
Reset
DPD
Parameter 4 KB-sector Erase
Instruction
Value (Hex)
20
Maximum
Frequency
(MHz)
133
Address
Length
(Bytes)
3 or 4
QPI
Yes
4P4E
Parameter 4 KB-sector Erase
21
133
4
Yes
SE
Erase 256 KB
D8
133
3 or 4
Yes
Erase 256 KB
DC
133
4
Yes
BE
Bulk Erase
60
133
0
Yes
BE
Bulk Erase (alternate instruction)
C7
133
0
Yes
EPS
Erase / Program Suspend
75
133
0
Yes
EPS
Erase / Program Suspend (alternate instruction)
85
133
0
Yes
EPS
Erase / Program Suspend (alternate instruction
B0
133
0
Yes
EPR
Erase / Program Resume
7A
133
0
Yes
EPR
Erase / Program Resume (alternate instruction)
8A
133
0
Yes
EPR
Erase / Program Resume (alternate instruction
This command may be disabled and the instruction value
instead used for a clear status command — see Configuration
Register 3 on page 55
30
133
0
Yes
OTPP
OTP Program
42
133
3 or 4
No
OTPR
OTP Read
4B
133
3 or 4
No
DYBRD
DYB Read
FA
133
3 or 4
Yes
4DYBRD
DYB Read
E0
133
4
Yes
DYBWR
DYB Write
FB
133
3 or 4
Yes
4DYBWR
DYB Write
E1
133
4
Yes
PPBRD
PPB Read
FC
133
3 or 4
No
4PPBRD
PPB Read
E2
133
4
No
PPBP
PPB Program
FD
133
3 or 4
No
4PPBP
PPB Program
E3
133
4
No
PPBE
PPB Erase
E4
133
0
No
ASPRD
ASP Read
2B
133
0
No
ASPP
ASP Program
2F
133
0
No
PLBRD
PPB Lock Bit Read
A7
133
0
No
PLBWR
PPB Lock Bit Write
A6
133
0
No
PASSRD
Password Read
E7
133
0
No
PASSP
Password Program
E8
133
0
No
PASSU
Password Unlock
E9
133
0
No
RSTEN
Software Reset Enable
66
133
0
Yes
RST
Software Reset
99
133
0
Yes
RESET
Legacy Software Reset
F0
133
0
No
MBR
Mode Bit Reset
FF
133
0
Yes
DPD
Enter Deep Power-Down Mode
B9
133
0
Yes
RES
Release from Deep Power-Down Mode
AB
133
0
Yes
Erase
Flash Array 4SE
Erase
/Program
Suspend
/Resume
Command Description
Note
47. Commands not supported in QPI mode have undefined behavior if sent when the device is in QPI mode.
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S25FS512S
9.1.3
Read Device Identification
There are multiple commands to read information about the device manufacturer, device type, and device features. SPI memories
from different vendors have used different commands and formats for reading information about the memories. The S25FS512S
supports the three device information commands.
9.1.4
Register Read or Write
There are multiple registers for reporting embedded operation status or controlling device configuration options. There are
commands for reading or writing these registers. Registers contain both volatile and non-volatile bits. Nonvolatile bits in registers are
automatically erased and programmed as a single (write) operation.
9.1.4.1 Monitoring Operation Status
The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the
Write in Progress (WIP) bit in the Status Register. The Read from Status Register 1 command or Read Any Register command
provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the status register indicate whether
the most recent program or erase command has not completed successfully. When P_ERR or E_ERR bits are set to one, the WIP
bit will remain set to one indicating the device remains busy and unable to receive most new operation commands. Only status read
(RDSR1 05h), Read Any Register (RDAR 65h), status clear (CLSR 30h or 82h), and software reset (RSTEN 66h, RST 99h or
RESET F0h) are valid commands when P_ERR or E_ERR is set to 1. A Clear Status Register (CLSR) followed by a Write Disable
(WRDI) command must be sent to return the device to standby state. Clear Status Register clears the WIP, P_ERR, and E_ERR
bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software Reset (RST or RESET) may be used to return the device
to standby state.
9.1.4.2 Configuration
There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length,
and some aspects of data protection.
9.1.5
Read Flash Array
Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incrementally higher byte
addresses until the host ends the data transfer by driving CS# input High. If the byte address reaches the maximum address of the
memory array, the read will continue at address zero of the array.
There are several different read commands to specify different access latency and data path widths. Double Data Rate (DDR)
commands also define the address and data bit relationship to both SCK edges:
The Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit per
SCK falling edge on the SO signal. This command has zero latency between the address and the returning data but is limited to a
maximum SCK rate of 50 MHz.
Other read commands have a latency period between the address and returning data but can operate at higher SCK frequencies.
The latency depends on a configuration register read latency value.
The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit
per SCK falling edge on the SO signal.
Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data returning two bits, or
four bits of data per SCK falling edge on the IO0-IO3 signals.
Quad Double Data Rate read commands provide address four bits per every SCK edge with read data returning four bits of data
per every SCK edge on the IO0-IO3 signals.
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S25FS512S
9.1.6
Program Flash Array
Programming data requires two commands: Write Enable (WREN), and Page Program (PP). The Page Program command accepts
from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed in one operation. Programming means that bits can
either be left at 1, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation.
9.1.7
Erase Flash Array
The Parameter Sector Erase, Sector Erase, or Bulk Erase commands set all the bits in a sector or the entire memory array to 1. A bit
needs to be first erased to 1 before programming can change it to a 0. While bits can be individually programmed from a 1 to 0,
erasing bits from 0 to 1 must be done on a sector-wide or array-wide (bulk) level. The Write Enable (WREN) command must precede
an erase command.
9.1.8
OTP, Block Protection, and Advanced Sector Protection
There are commands to read and program a separate One Time Programmable (OTP) array for permanent data such as a serial
number. There are commands to control a contiguous group (block) of flash memory array sectors that are protected from program
and erase operations.There are commands to control which individual flash memory array sectors are protected from program and
erase operations.
9.1.9
Reset
There are commands to reset to the default conditions present after power on to the device. However, the software reset commands
do not affect the current state of the FREEZE or PPB Lock bits. In all other respects a software reset is the same as a hardware
reset.
There is a command to reset (exit from) the Continuous Read Mode.
9.1.10 DPD
A Deep Power-Down (DPD) mode is supported by the S25FS512S devices. If the device has been placed in DPD mode by the DPD
(B9h) command, the interface standby current is (IDPD). The DPD command is accepted only while the device is not performing an
embedded algorithm as indicated by the Status Register-1 volatile Write In Progress (WIP) bit being cleared to zero (SR1V[0] = 0).
While in DPD mode the device ignores all commands except the Release from DPD (RES ABh) command, that will return the device
to the Interface Standby state after a delay of tRES.
9.1.11 Reserved
Some instructions are reserved for future use. In this generation of the S25FS512S some of these command instructions may be
unused and not affect device operation, some may have undefined results.
Some commands are reserved to ensure that a legacy or alternate source device command is allowed without effect. This allows
legacy software to issue some commands that are not relevant for the current generation S25FS512S with the assurance these
commands do not cause some unexpected action.
Some commands are reserved for use in special versions of the FS-S not addressed by this document or for a future generation.
This allows new host memory controller designs to plan the flexibility to issue these command instructions. The command format is
defined if known at the time this document revision is published.
Document Number: 002-00488 Rev. *M
Page 76 of 139
S25FS512S
9.2
Identification Commands
9.2.1
Read Identification (RDID 9Fh)
The Read Identification (RDID) command provides read access to manufacturer identification, device identification, and Common
Flash Interface (CFI) information. The manufacturer identification is assigned by JEDEC. The CFI structure is defined by JEDEC
standard. The device identification and CFI values are assigned by Cypress.
The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows a vendor-specified
software flash management program (driver) to be used for entire families of flash devices. Software support can then be
device-independent, JEDEC manufacturer ID independent, forward and backward-compatible for the specified flash device families.
System vendors can standardize their flash drivers for long-term software compatibility by using the CFI values to configure a family
driver from the CFI information of the device in use.
Any RDID command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the
program, erase, or write cycle that is in progress.
The RDID instruction is shifted on SI. After the last bit of the RDID instruction is shifted into the device, a byte of manufacturer
identification, two bytes of device identification, extended device identification, and CFI information will be shifted sequentially out on
SO. As a whole this information is referred to as ID-CFI. See Device ID and Common Flash Interface (ID-CFI) Address Map on page
119 for the detail description of the ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The RDID command
sequence is terminated by driving CS# to the logic high state anytime during data output.
The maximum clock frequency for the RDID command is 133 MHz.
Figure 45. Read Identification (RDID) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
Instruction
Data 1
Data N
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
Figure 46. Read Identification (RDID) QPI Mode Command
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Document Number: 002-00488 Rev. *M
Instruction
D1
D2
D3
D4
D5
Page 77 of 139
S25FS512S
9.2.2
Read Quad Identification (RDQID AFh)
The Read Quad Identification (RDQID) command provides read access to manufacturer identification, device identification, and
Common Flash Interface (CFI) information. This command is an alternate way of reading the same information provided by the
RDID command while in QPI mode. In all other respects the command behaves the same as the RDID command.
The command is recognized only when the device is in QPI Mode (CR2V[6]=1). The instruction is shifted in on IO0-IO3. After the last
bit of the instruction is shifted into the device, a byte of manufacturer identification, two bytes of device identification, extended
device identification, and CFI information will be shifted sequentially out on IO0-IO3. As a whole this information is referred to as
ID-CFI. See Device ID and Common Flash Interface (ID-CFI) Address Map on page 119 for the detail description of the ID-CFI
contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data. The command
sequence is terminated by driving CS# to the logic high state anytime during data output.
The maximum clock frequency for the command is 133 MHz.
Figure 47. Read Quad Identification (RDQID) Command Sequence
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
9.2.3
Instruction
D1
D2
D3
D4
D5
Read Serial Flash Discoverable Parameters (RSFDP 5Ah)
The command is initiated by shifting on SI the instruction code ‘5Ah’, followed by a 24-bit address of 000000h, followed by 8 dummy
cycles. The SFDP bytes are then shifted out on SO starting at the falling edge of SCK after the dummy cycles. The SFDP bytes are
always shifted out with the MSb first. If the 24-bit address is set to any other value, the selected location in the SFDP space is the
starting point of the data read. This enables random access to any parameter in the SFDP space. The RSFDP command is
supported up to 50 MHz.
Figure 48. RSFDP Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0 23
1 0
SO
7 6 5 4 3 2 1 0
Phase
Address
Instruction
Dummy Cycles
Data 1
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3.
Figure 49. RSFDP QPI Mode Command Sequence
CS#
SCK
IO0
4
0 20
4
0
4
0
4
0
4
0
4
0
IO1
5
1 21
5
1
5
1
5
1
5
1
5
1
IO2
6
2 22
6
2
6
2
6
2
6
2
6
2
7
3 23
7
3
7
3
7
3
7
3
7
3
IO3
Phase
Document Number: 002-00488 Rev. *M
Instruct.
Address
Dummy
D1
D2
D3
D4
Page 78 of 139
S25FS512S
9.3
Register Access Commands
9.3.1
Read Status Register 1 (RDSR1 05h)
The Read Status Register 1 (RDSR1) command allows the Status Register 1 contents to be read from SO. The volatile version of
Status Register 1 (SR1V) contents may be read at any time, even while a program, erase, or write operation is in progress. It is
possible to read Status Register 1 continuously by providing multiples of eight clock cycles. The status is updated for each eight
cycle read. The maximum clock frequency for the RDSR1 (05h) command is 133 MHz.
Figure 50. Read Status Register 1 (RDSR1) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
Instruction
Status
Updated Status
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3 and the returning data is shifted
out on IO0-IO3, two clock cycles per byte.
Figure 51. Read Status Register 1 (RDSR1) QPI Mode Command
CS#
SCK
IO0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
9.3.2
Instruct.
D1
D2
D3
D4
D5
Read Status Register 2 (RDSR2 07h)
The Read Status Register 2 (RDSR2) command allows the Status Register 2 contents to be read from SO. The Status Register 2
contents may be read at any time, even while a program, erase, or write operation is in progress. It is possible to read the Status
Register 2 continuously by providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum
clock frequency for the RDSR2 command is 133 MHz.
Figure 52. Read Status Register 2 (RDSR2) Command
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
Phase
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction
Status
Updated Status
In QPI mode, Status Register 2 may be read via the Read Any Register command, see Read Any Register (RDAR 65h) on page 86.
Document Number: 002-00488 Rev. *M
Page 79 of 139
S25FS512S
9.3.3
Read Configuration Register (RDCR 35h)
The Read Configuration Register (RDCR) command allows the volatile Configuration Register (CR1V) contents to be read from SO.
It is possible to read CR1V continuously by providing multiples of eight clock cycles. The configuration register contents may be read
at any time, even while a program, erase, or write operation is in progress.
Figure 53. Read Configuration Register (RDCR) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Repeat Register Read
Phase
Instruction
Register Read
In QPI mode, Configuration Register 1 may be read via the Read Any Register command, see Read Any Register (RDAR 65h) on
page 86
9.3.4
Write Registers (WRR 01h)
The Write Registers (WRR) command allows new values to be written to both the Status Register 1 and Configuration Register 1.
Before the Write Registers (WRR) command can be accepted by the device, a Write Enable (WREN) command must be received.
After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) in the
Status Register to enable any write operations.
The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The Status Register is one data
byte in length.
The WRR operation first erases the register then programs the new value as a single operation. The Write Registers (WRR)
command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation. See Status Register 1 Volatile (SR1V) on
page 47 for a description of the error bits. Any status or configuration register bit reserved for the future must be written as a 0.
CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the Write Registers (WRR)
command is not executed. If CS# is driven high after the eighth cycle then only the Status Register 1 is written; otherwise, after the
sixteenth cycle both the status and configuration registers are written.
As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated. While the Write
Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit.
The Write-In Progress (WIP) bit is a 1 during the self-timed Write Registers (WRR) operation, and is a 0 when it is completed. When
the Write Registers (WRR) operation is completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the
WRR command is 133 MHz.
This command is also supported in QPI mode. In QPI mode the instruction and data is shifted in on IO0-IO3, two clock cycles per
byte.
Figure 54. Write Registers (WRR) Command Sequence – 8 Data Bits
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00488 Rev. *M
Instruction
Input Status Register-1
Page 80 of 139
S25FS512S
Figure 55. Write Registers (WRR) Command Sequence – 16 Data Bits
CS#
SCK
SI
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5
4
3 2 1 0
SO
Phase
Instruction
Input Status Register-1
Input Configuration Register-1
Figure 56. Write Registers (WRR) Command Sequence – 16 Data Bits QPI Mode
CS#
SCK
IO0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
Phase
Instruct.
Input Status
Input Config
The Write Register (WRR) command writes the non-volatile version of the Quad bit (CR1NV[1]), which also causes an update to the
volatile version CR1V[1]. The WRR command can not write the volatile version CR1V[1] without first affecting the non-volatile
version CR1NV[1]. The WRAR command must be used when it is desired to write the volatile Quad bit CR1V[1] without affecting the
non-volatile version CR1NV[1].
The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and BP0) bits in either
the nonvolatile Status Register 1 or in the volatile Status Register 1, to define the size of the area that is to be treated as read-only.
The BPNV_O bit (CR1NV[3]) controls whether WRR writes the nonvolatile or volatile version of Status Register 1. When
CR1NV[3]=0 WRR writes SR1NV[4:2]. When CR1NV[3]=1 WRR writes SR1V[4:2].
The Write Registers (WRR) command also allows the user to set the Status Register Write Disable (SRWD) bit to a 1 or a 0. The
Status Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow the BP bits to be hardware protected.
When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is possible to write to the
status register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) command,
regardless of the whether Write Protect (WP#) signal is driven to the logic high or logic low state.
When the Status Register Write Disable (SRWD) bit of the status register is set to a 1, two cases need to be considered, depending
on the state of Write Protect (WP#):
If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the status and configuration registers
provided that the Write Enable Latch (WEL) bit has previously been set to a 1 by initiating a Write Enable (WREN) command.
If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the status and configuration registers even
if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write Enable (WREN) command. Attempts to write to the
status and configuration registers are rejected, not accepted for execution, and no error indication is provided. As a consequence,
all the data bytes in the memory area that are protected by the Block Protect (BP2, BP1, BP0) bits of the status register, are also
hardware protected by WP#.
The WP# hardware protection can be provided:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic low state;
or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable (SRWD) bit to a 1.
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high state. If WP# is
permanently tied high, hardware protection of the BP bits can never be activated.
Document Number: 002-00488 Rev. *M
Page 81 of 139
S25FS512S
Table 46. Block Protection Modes
WP#
SRWD Bit
1
1
1
0
0
0
0
1
Mode
Memory Content
Write Protection of Registers
Protected Area
Unprotected Area
Software
Protected
Status and Configuration Registers are Writable (if
WREN command has set the WEL bit). The values in
the SRWD, BP2, BP1, and BP0 bits and those in the
Configuration Register can be changed
Hardware
Protected
Status and Configuration Registers are Hardware
Protected against Page Ready to accept Page
Write Protected. The values in the SRWD, BP2, BP1,
Program or Erase
Program, Sector
and BP0 bits and those in the Configuration Register
Erase, and Bulk Erase commands
cannot be changed
Protected against Page Ready to accept Page
Program, Sector
Program, and Sector
Erase, and Bulk Erase Erase commands
Notes
48. The Status Register originally shows 00h when the device is first shipped from Cypress to the customer.
49. Hardware protection is disabled when Quad Mode is enabled (CR1V[1] = 1). WP# becomes IO2; therefore, it cannot be utilized.
9.3.5
Write Enable (WREN 06h)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1V[1]) to a 1. The Write
Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN) command to enable write, program and erase
commands.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being
driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write enable operation will not
be executed.
Figure 57. Write Enable (WREN) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 58. Write Enable (WREN) Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Document Number: 002-00488 Rev. *M
Instruction
Page 82 of 139
S25FS512S
9.3.6
Write Disable (WRDI 04h):
The Write Disable (WRDI) command clears the Write Enable Latch (WEL) bit of the Status Register 1 (SR1V[1]) to a 0.
The Write Enable Latch (WEL) bit may be cleared to a 0 by issuing the Write Disable (WRDI) command to disable Page Program
(PP), Sector Erase (SE), Bulk Erase (BE), Write Registers (WRR or WRAR), OTP Program (OTPP), and other commands, that
require WEL be set to 1 for execution. The WRDI command can be used by the user to protect memory areas against inadvertent
writes that can possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while
WIP bit =1.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being
driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write disable operation will not
be executed.
Figure 59. Write Disable (WRDI) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 60. Write Disable (WRDI) Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.3.7
Instruction
Clear Status Register (CLSR 30h or 82h)
The Clear Status Register command resets bit SR1V[5] (Erase Fail Flag) and bit SR1V[6] (Program Fail Flag). It is not necessary to
set the WEL bit before a Clear Status Register command is executed. The Clear Status Register command will be accepted even
when the device remains busy with WIP set to 1, as the device does remain busy when either error bit is set. The WEL bit will be
unchanged after this command is executed.
The legacy Clear Status Register (CLSR 30h) instruction may be disabled and the 30h instruction value instead used for a program
/ erase resume command, see Configuration Register 3 on page 55. The Clear Status Register alternate instruction (CLSR 82h) is
always available to clear the status register.
Figure 61. Clear Status Register (CLSR) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00488 Rev. *M
Instruction
Page 83 of 139
S25FS512S
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 62. Clear Status Register (CLSR) Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.3.8
Instruction
ECC Status Register Read (ECCRD 19h or 4EECRD 18h)
To read the ECC Status Register, the command is followed by the ECC unit address, the four least significant bits (LSb) of address
must be set to zero. This is followed by the number of dummy cycles selected by the read latency value in CR2V[3:0]. Then the 8-bit
contents of the ECC Register, for the ECC unit selected, are shifted out on SO 16 times, once for each byte in the ECC Unit. If CS#
remains low the next ECC unit status is sent through SO 16 times, once for each byte in the ECC Unit. The maximum operating
clock frequency for the ECC READ command is 133 MHz.
Figure 63. ECC Status Register Read Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
7
Phase
Instruction
Address
6
5
4
Dummy Cycles
3
2
1
0
Data 1
Notes
50. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command 19h.
51. A = MSb of address = 31 with command 18h.
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 64. ECCRD (19h), QPI Mode, CR2[7] = 0, Command Sequence
CS#
SCLK
IO0
4
0
20
4
0
4
0
4
0
4
0
4
0
IO1
5
1
21
5
1
5
1
5
1
5
1
5
1
IO2
6
2
22
6
2
6
2
6
2
6
2
6
2
IO3
7
3
23
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Document Number: 002-00488 Rev. *M
Address
Dummy
D1
D2
D3
D4
Page 84 of 139
S25FS512S
Figure 65. ECCRD (19h), QPI Mode, CR2[7] = 1, or 4ECCRD (18h) Command Sequence
CS#
SCLK
IO0
4
0
28
4
0
4
0
4
0
4
0
4
0
IO1
5
1
29
5
1
5
1
5
1
5
1
5
1
IO2
6
2
30
6
2
6
2
6
2
6
2
6
2
IO3
7
3
31
7
3
7
3
7
3
7
3
7
3
Phase
9.3.9
Instruct.
Address
Dummy
D1
D2
D3
D4
Program NVDLR (PNVDLR 43h)
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the
Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the PNVDLR command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR operation is initiated. While the PNVDLR
operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In
Progress (WIP) bit is a 1 during the self-timed PNVDLR cycle, and is a 0 when it is completed. The PNVDLR operation can report a
program error in the P_ERR bit of the status register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is
set to a 0 The maximum clock frequency for the PNVDLR command is 133 MHz.
Figure 66. Program NVDLR (PNVDLR) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Input Data
9.3.10 Write VDLR (WVDLR 4Ah)
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write
Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WVDLR command is not
executed. As soon as CS# is driven to the logic high state, the WVDLR operation is initiated with no delays. The maximum clock
frequency for the PNVDLR command is 133 MHz.
Figure 67. Write VDLR (WVDLR) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00488 Rev. *M
Instruction
Input Data
Page 85 of 139
S25FS512S
9.3.11 Data Learning Pattern Read (DLPRD 41h)
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP continuously by providing
multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command is 133 MHz.
Figure 68. DLP Read (DLPRD) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
Phase
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction
Repeat Register Read
Register Read
9.3.12 Enter 4-Byte Address Mode (4BAM B7h)
The enter 4-byte Address Mode (4BAM) command sets the volatile Address Length bit (CR2V[7]) to 1 to change most 3-byte
address commands to require 4 bytes of address. The Read SFDP (RSFDP) command is the only 3-byte command that is not
affected by the Address Length bit. RSFDP is required by the JEDEC JESD216 standard to always have only 3 bytes of address.
A hardware or software reset is required to exit the 4-byte address mode.
Figure 69. Enter 4-Byte Address Mode (4BAM B7h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
9.3.13 Read Any Register (RDAR 65h)
The Read Any Register (RDAR) command provides a way to read all device registers - nonvolatile and volatile. The instruction is
followed by a 3- or 4-byte address (depending on the address length configuration CR2V[7], followed by a number of latency
(dummy) cycles set by CR2V[3:0]. Then the selected register contents are returned. If the read access is continued the same
addressed register contents are returned until the command is terminated – only one register is read by each RDAR command.
Reading undefined locations provides undefined data.
The RDAR command may be used during embedded operations to read Status Register 1 (SR1V).
The RDAR command is not used for reading registers that act as a window into a larger array: PPBAR, and DYBAR. There are
separate commands required to select and read the location in the array accessed.
Document Number: 002-00488 Rev. *M
Page 86 of 139
S25FS512S
The RDAR command will read invalid data from the PASS register locations if the ASP Password protection mode is selected by
programming ASPR[2] to 0.
Table 47. Register Address Map
Byte Address (Hex)
Register Name
00000000
SR1NV
00000001
N/A
00000002
CR1NV
00000003
CR2NV
00000004
CR3NV
00000005
CR4NV
...
N/A
00000010
NVDLR
...
N/A
00000020
PASS[7:0]
00000021
PASS[15:8]
00000022
PASS[23:16]
00000023
PASS[31:24]
00000024
PASS[39:32]
00000025
PASS[47:40]
00000026
PASS[55:48]
00000027
PASS[63:56]
...
N/A
00000030
ASPR[7:0]
00000031
ASPR[15:8]
...
N/A
00800000
SR1V
00800001
SR2V
00800002
CR1V
00800003
CR2V
00800004
CR3V
00800005
CR4V
...
N/A
00800010
VDLR
...
N/A
00800040
PPBL
...
N/A
Description
Nonvolatile Status and Configuration Registers
Nonvolatile Data Learning Register
Nonvolatile Password Register
Nonvolatile
Volatile Status and Configuration Registers
Volatile Data Learning Register
Volatile PPB Lock Register
Figure 70. Read Any Register Read Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0 A
1 0
SO
Phase
7 6 5 4 3 2 1 0
Instruction
Address
Dummy Cycles
Data 1
Note
52. A = MSb of address = 23 for Address length CR2V[7] = 0, or 31 for CR2V[7]=1.
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S25FS512S
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 71. Read Any Register, QPI Mode, Command Sequence
CS#
SCK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Dummy
D1
D2
D3
D4
Note
53. A = MSb of address = 23 for Address length CR2V[7] = 0, or 31 for CR2V[7] = 1.
9.3.14 Write Any Register (WRAR 71h)
The Write Any Register (WRAR) command provides a way to write any device register - nonvolatile/volatile. The instruction is
followed by a 3 or 4-byte address (depending on the address length configuration CR2V[7], followed by one byte of data to write in
the address selected register.
Before the WRAR command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the
device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit in SR1V may be
checked to determine when the operation is completed. The P_ERR and E_ERR bits in SR1V may be checked to determine if any
error occurred during the operation.
Some registers have a mixture of bit types and individual rules controlling which bits may be modified. Some bits are read only,
some are OTP.
Read only bits are never modified and the related bits in the WRAR command data byte are ignored without setting a program or
erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the WRAR data byte do not matter.
OTP bits may only be programmed to the level opposite of their default state. Writing of OTP bits back to their default state is
ignored and no error is set.
Nonvolatile bits which are changed by the WRAR data, require nonvolatile register write time (tW) to be updated. The update process
involves an erase and a program operation on the nonvolatile register bits. If either the erase or program portion of the update fails
the related error bit and WIP in SR1V will be set to 1.
Volatile bits which are changed by the WRAR data, require the volatile register write time (tCS) to be updated.
Status Register 1 may be repeatedly read (polled) to monitor the Write-In-Progress (WIP) bit (SR1V[0]) and the error bits
(SR1V[6,5]) to determine when the register write is completed or failed. If there is a write failure, the clear status command is used to
clear the error status and enable the device to return to standby state.
However, the PPBL register can not be written by the WRAR command. Only the PPB Lock Bit Write (PLBWR) command can write
the PPBL register.
The command sequence and behavior is the same as the PP or 4PP command with only a single byte of data provided. See Page
Program (PP 02h or 4PP 12h) on page 98.
The address map of the registers is the same as shown for Read Any Register (RDAR 65h) on page 86.
9.3.15 Set Burst Length (SBL C0h)
The Set Burst Length (SBL) command is used to configure the Burst Wrap feature. Burst Wrap is used in conjunction with Quad I/O
Read and DDR Quad I/O Read, in legacy SPI or QPI mode, to access a fixed length and alignment of data. Certain applications can
benefit from this feature by improving the overall system code execution performance. The Burst Wrap feature allows applications
that use cache, to start filling a cache line with instruction or data from a critical address first, then fill the remainder of the cache line
afterwards within a fixed length (8/16/32/64-bytes) of data, without issuing multiple read commands.
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S25FS512S
The Set Burst Length (SBL) command writes the CR4V register bits 4, 1, and 0 to enable or disable the wrapped read feature and
set the wrap boundary. Other bits of the CR4V register are not affected by the SBL command. When enabled the wrapped read
feature changes the related read commands from sequentially reading until the command ends, to reading sequentially wrapped
within a group of bytes.
When CR4V[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed.
When CR4V[4]=0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes is read starting at the
byte address provided by the read command and wrapping around at the group alignment boundary.
The group of bytes is of length and aligned on an 8, 16, 32, or 64 byte boundary. CR4V[1:0] selects the boundary. See Configuration
Register 4 Volatile (CR4V) on page 58.
The starting address of the read command selects the group of bytes and the first data returned is the addressed byte. Bytes are
then read sequentially until the end of the group boundary is reached. If the read continues the address wraps to the beginning of the
group and continues to read sequentially. This wrapped read sequence continues until the command is ended by CS# returning
high.
Table 48. Example Burst Wrap Sequences
Wrap
Boundary
(Bytes)
CR4V[4,1:0]
Value (Hex)
Start Address
(Hex)
Address Sequence (Hex)
1X
Sequential
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ...
00
8
XXXXXX00
00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ...
00
8
XXXXXX07
07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ...
01
16
XXXXXX02
02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, ...
01
16
XXXXXX0C
0C, 0D, 0E, 0F, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, ...
02
32
XXXXXX0A
0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02,
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, ...
02
32
XXXXXX1E
1E, 1F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16,
17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, ...
03
64
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B,
1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34,
35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02 ...
03
64
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02, 03, 04, 05, 06,
07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F,
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, ...
The power-on reset, hardware reset, or software reset default burst length can be changed by programming CR4NV with the desired
value using the WRAR command.
Figure 72. Set Burst Length Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00488 Rev. *M
Instruction
Input Data
Page 89 of 139
S25FS512S
9.4
Read Memory Array Commands
Read commands for the main flash array provide many options for prior generation SPI compatibility or enhanced performance SPI:
Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands (SDR).
Some SDR commands transfer address one bit per rising edge of SCK and return data 1 bit of data per rising edge of SCK. These
are called Single width commands.
Some SDR commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called Dual I/O for 2 bit,
Quad I/O, and QPI for 4 bit. QPI also transfers instructions 4 bits per rising edge.
Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called Double Data Rate
(DDR) commands.
There are DDR commands for 4 bits of address or data per SCK edge. These are called Quad I/O DDR and QPI DDR for 4 bit per
edge transfer.
All of these commands, except QPI Read, begin with an instruction code that is transferred one bit per SCK rising edge. QPI Read
transfers the instruction 4 bits per SCK rising edge.The instruction is followed by either a 3- or 4-byte address transferred at SDR or
DDR. Commands transferring address or data 2 or 4 bits per clock edge are called Multiple I/O (MIO) commands. For S25FS512S
devices, the traditional SPI 3-byte addresses are unable to directly address all locations in the memory array. Separate 4-byte
address read commands are provided for access to the entire address space. These devices may be configured to take a 4-byte
address from the host system with the traditional 3-byte address commands. The 4-byte address mode for traditional commands is
activated by setting the Address Length bit in Configuration Register 2 to 0.
The Quad I/O and QPI commands provide a performance improvement option controlled by mode bits that are sent following the
address bits. The mode bits indicate whether the command following the end of the current read will be another read of the same
type, without an instruction at the beginning of the read. These mode bits give the option to eliminate the instruction cycles when
doing a series of Quad read accesses.
Some commands require delay cycles following the address or mode bits to allow time to access the memory array - read latency.
The delay or read latency cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus any data
provided by the host during these cycles is ‘don’t care’ and the host may also leave the SI signal at high impedance during the
dummy cycles. When MIO commands are used the host must stop driving the IO signals (outputs are high impedance) before the
end of last dummy cycle. When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The
number of dummy cycles varies with the SCK frequency or performance option selected via the Configuration Register 2
(CR2V[3:0]) Latency Code. Dummy cycles are measured from SCK falling edge to next SCK falling edge. SPI outputs are
traditionally driven to a new value on the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the
memory on the same falling edge of SCK that the host stops driving address or mode bits.
The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on all data outputs, in the
dummy cycles immediately before the start of data. The DLP can help the host memory controller determine the phase shift from
SCK to data edges so that the memory controller can capture data at the center of the data eye.
When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides 1 or more dummy cycles should be
selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict.
When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to allow 1
cycle of additional time for the host to stop driving before the memory starts driving the 4-cycle DLP.
Each read command ends when CS# is returned High at any point during data return. CS# must not be returned High during the
mode or dummy cycles before data returns as this may cause mode bits to be captured incorrectly; making it indeterminate as to
whether the device remains in continuous read mode.
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S25FS512S
9.4.1
Read (Read 03h or 4READ 13h)
The instruction
03h (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
03h (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
13h is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock frequency for the READ
command is 50 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 73. Read Command Sequence (3-Byte Address, 03h or 13h)
CS#
SCK
SI
7 6 5 4 3 2 1 0 A
1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
Instruction
Address
Data 1
Data N
Note
54. A = MSb of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 13h.
9.4.2
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)
The instruction
0Bh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
0Bh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The address is followed by dummy cycles depending on the latency code set in the Configuration Register CR2V[3:0]. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on SO is ‘don’t care’ and may be high impedance. Then the memory contents, at the address given, are shifted out on SO.
The maximum operating clock frequency for FAST READ command is 133 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 74. Fast Read (FAST_READ) Command Sequence (3-Byte Address, 0Bh [CR2V[7]=0)
CS#
SCK
SI
7 6 5 4 3 2 1 0 A
1 0
SO
Phase
7 6 5 4 3 2 1 0
Instruction
Address
Dummy Cycles
Data 1
Note
55. A = MSb of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 0Ch.
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S25FS512S
9.4.3
Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
BBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
BBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This command takes input of the
address and returns read data two bits per SCK rising edge. In some applications, the reduced address input and data output time
might allow for code execution in place (XIP) i.e. directly from the memory device.
The maximum operating clock frequency for Dual I/O Read is 133 MHz.
The Dual I/O Read command has continuous read mode bits that follow the address so, a series of Dual I/O Read commands may
eliminate the 8 bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the following
command will also be a Dual I/O Read command. The first Dual I/O Read command in a series starts with the 8 bit instruction,
followed by address, followed by four cycles of mode bits, followed by an optional latency period. If the mode bit pattern is Axh the
next command is assumed to be an additional Dual I/O Read command that does not provide instruction bits. That command starts
with address, followed by mode bits, followed by optional latency.
Variable latency may be added after the mode bits are shifted into SI and SO before data begins shifting out of IO0 and IO1. This
latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the
dummy cycles, the data value on SI and SO are ‘don’t care’ and may be high impedance. The number of dummy cycles is
determined by the frequency of SCK. The latency is configured in CR2V[3:0].
The continuous read feature removes the need for the instruction bits in a sequence of read accesses and greatly improves code
execution (XIP) performance. The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read command
through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are ‘don’t care’ (“x”)
and may be high impedance. If the Mode bits equal Axh, then the device remains in Dual I/O Continuous Read Mode and the next
address can be entered (after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in Figure 76;
thus, eliminating eight cycles of the command sequence. The following sequences will release the device from Dual I/O Continuous
Read mode; after which, the device can accept standard SPI commands:
1. During the Dual I/O continuous read command sequence, if the Mode bits are any value other than Axh, then the next
time CS# is raised high the device will be released from Dual I/O continuous read mode.
2. Send the Mode Reset command.
Note that the four-mode bit cycles are part of the device’s internal circuitry latency time to access the initial address after the last
address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock
speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is
allowed and may be helpful in preventing I/O signal contention, for the host system to turn off the I/O signal outputs (make them high
impedance) during the last two ‘don’t care’ mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1
(SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
Document Number: 002-00488 Rev. *M
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S25FS512S
Figure 75. Dual I/O Read Command Sequence (BBh)
CS#
SCK
IO0
7
6
5
4
3
2
1
0
IO1
Phase
A-1
2
0
6
4
2
0
6
4
2
0
6
4
2
0
A
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Instruction
Address
Mode
Dum
Data 1
Data 2
Notes
56. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command BBh.
57. A = MSb of address = 31 with command BBh.
58. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these cycles to increase bus turn
around time between Mode bits from host and returning data from the memory.
Figure 76. Dual I/O Continuous Read Command Sequence (BBh])
CS#
SCK
IO0
6
4
2
0
A-1
2
0
6
4
2
0
6
4
2
0
6
4
2
0
IO1
7
5
3
1
A
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Phase
Data N
Address
Mode
Dum
Data 1
Data 2
Notes
59. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command BBh.
60. A = MSb of address = 31 with command BBh.
9.4.4
Quad I/O Read (QIOR EBh or 4QIOR ECh)
The instruction
EBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
EBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals: IO0-IO3. It allows input of the address bits four bits per
serial SCK clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from
S25FS512S devices. The QUAD bit of the configuration register must be set (CR1V[1]=1) to enable the Quad capability of
S25FS512S devices.
The maximum operating clock frequency for Quad I/O Read is 133 MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data begins shifting out of
IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to access data at the initial
address. During latency cycles, the data value on IO0-IO3 are ‘don’t care’ and may be high impedance. The number of dummy
cycles is determined by the frequency of SCK. The latency is configured in CR2V[3:0].
Following the latency period, the memory contents at the address given, is shifted out four bits at a time through IO0-IO3. Each
nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through the setting of the
Mode bits (after the address sequence, as shown in Figure 77 on page 94). This added feature removes the need for the instruction
sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next
Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits
are ‘don’t care’ (x). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode and the next
address can be entered (after CS# is raised high and then asserted low) without requiring the EBh or ECh instruction, as shown in
Figure 79 on page 94; thus, eliminating eight cycles for the command sequence.
Document Number: 002-00488 Rev. *M
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S25FS512S
The following sequences will release the device from Quad I/O High Performance Read mode; after which, the device can accept
standard SPI commands:
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is
raised high the device will be released from Quad I/O High Performance Read mode.
2. Send the Mode Reset command.
Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal circuitry latency
time to access the initial address after the last address cycle that is clocked into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data out clock. At higher
clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished.
It is allowed and may be helpful in preventing IO0-IO3 signal contention, for the host system to turn off the IO0-IO3 signal outputs
(make them high impedance) during the last ‘don’t care’ mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
In QPI mode (CR2V[6]=1) the Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the command protocol is
identical to the Quad I/O commands.
Figure 77. Quad I/O Read Command Sequence (EBh or ECh)
CS#
SCK
IO0
A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
7
6
5
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
A-1
6
2
6
0
6
2
6
2
6
2
6
2
IO3
A
7
3
7
1
7
3
7
3
7
3
7
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
D1
D2
D3
3
D4
Notes
61. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EBh.
62. A = MSb of address = 31 with command ECh.
Figure 78. Quad I/O Read Command Sequence (EBh or ECh), QPI Mode
CS#
SCK
IO0
4
0
A-3
4
0
4
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
0
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
1
7
3
7
3
7
3
7
Phase
Instruct.
Address
Mode
Dummy
D1
D2
D3
3
D4
Notes
63. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EBh.
64. A = MSb of address = 31 with command ECh.
Figure 79. Continuous Quad I/O Read Command Sequence (EBh or ECh)
CS#
SCK
IO0
4
0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
A
7
3
7
3
7
3
7
3
7
3
7
Phase
DN-1
DN
Address
Mode
Dummy
D1
D2
D3
3
D4
Notes
65. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EBh.
66. A = MSb of address = 31 with command ECh.
Document Number: 002-00488 Rev. *M
Page 94 of 139
S25FS512S
9.4.5
DDR Quad I/O Read (EDh, EEh)
The DDR Quad I/O Read command improves throughput with four I/O signals: IO0-IO3. It is similar to the Quad I/O Read command
but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might
allow for code execution (XIP) directly from S25FS512S devices. The QUAD bit of the Configuration Register must be set
(CR1V[1]=1) to enable the Quad capability.
The instruction
EDh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
EDh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
EEh is followed by a 4-byte address (A31-A0)
The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four
bits at a time on each clock edge through IO0-IO3.
The maximum operating clock frequency for DDR Quad I/O Read command is 80 MHz.
For DDR Quad I/O Read, there is a latency required after the last address and mode bits are shifted into the IO0-IO3 signals before
data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access
the initial address. During these latency cycles, the data value on IO0-IO3 are ‘don’t care’ and may be high impedance. When the
Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must
be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.
The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR2V[3:0].
Mode bits allow a series of Quad I/O DDR commands to eliminate the 8 bit instruction after the first command sends a
complementary mode bit pattern, as shown in Figure 80 on page 96. This feature removes the need for the eight bit SDR instruction
sequence and dramatically reduces initial access times (improves XIP performance). The Mode bits control the length of the next
DDR Quad I/O Read operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and
lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to Continuous DDR Quad I/O Read
Mode and the next address can be entered (after CS# is raised high and then asserted low) without requiring the EDh or EEh
instruction, as shown in Figure 81 on page 96, thus eliminating eight cycles from the command sequence. The following sequences
will release the device from Continuous DDR Quad I/O Read mode; after which, the device can accept standard SPI commands:
1. During the DDR Quad I/O Read Command Sequence, if the Mode bits are not complementary the next time CS# is raised
high and then asserted low the device will be released from DDR Quad I/O Read mode.
2. Send the Mode Reset command.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. Note that the memory
devices may drive the IOs with a preamble prior to the first data value. The preamble is a Data Learning Pattern (DLP) that is used
by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus for the four clock cycles
immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts
outputting the preamble.
The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to
when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the
preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read
operation. The optimized capture point will be determined during the preamble period of every read operation. This optimization
strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Document Number: 002-00488 Rev. *M
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S25FS512S
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h
(or 00110100) will be driven on each of the active outputs (i.e. all four SIOs). This pattern was chosen to cover both ‘DC’ and ‘AC’
data transition scenarios. The two DC transition scenarios include data low for a long period of time (two half clocks) followed by a
high going transition (001) and the complementary low going transition (110). The two AC transition scenarios include data low for a
short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). The
DC transitions will typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully settled
to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data valid period and the AC
transitions will bound the ending of the data valid period. These transitions will allow the host controller to identify the beginning and
ending of the valid data eye. Once the data eye has been characterized the optimal data capture point can be chosen. See SPI DDR
Data Learning Registers on page 61 for more details.
In QPI mode (CR2V[6]=1) the DDR Quad I/O instructions are sent 4 bits per SCK rising edge. The remainder of the command
protocol is identical to the DDR Quad I/O commands.
Figure 80. DDR Quad I/O Read Initial Access (EDh or EEh)
CS#
SCK
IO0
A-2
12 8 4 0 4 0
7 6 5 4 3 2 1 0 4 0 4 0
IO1
A-2
13 9 5 1 5 1
7 6 5 4 3 2 1 0 5 1 5 1
IO2
A-1
14 10 6 2 6 2
7 6 5 4 3 2 1 0 6 2 6 2
IO3
A
15 11 7 3 7 3
7 6 5 4 3 2 1 0 7 3 7 3
7
6
5
Phase
4
3
2
1
0
Instruction
Address
Mode
Dummy
DLP
D1
D2
Notes
67. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EDh.
68. A = MSb of address = 31 with command EEh.
Figure 81. Continuous DDR Quad I/O Read Subsequent Access (EDh or EEh)
CS#
SCK
IO0
A-3
12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
A-2
13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
A-1
14 10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
A
15 11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Phase
Address
Mode
Dummy
D1
D2
D3
D4
D5
Notes
69. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EDh.
70. A = MSb of address = 31 with command EEh.
Figure 82. DDR Quad I/O Read Initial Access (EDh or EEh), QPI Mode
CS#
SCK
IO0
4
0
A-3
12 8
4
0
4
0
7
6
5
4
3
2
1
0
4
0
4
0
IO1
5
1
A-2
13 9
5
1
5
1
7
6
5
4
3
2
1
0
5
1
5
1
IO2
6
2
A-1
14 10 6
2
6
2
7
6
5
4
3
2
1
0
6
2
6
2
IO3
7
3
A
15 11 7
3
7
3
7
6
5
4
3
2
1
0
7
3
7
3
Phase
Instruct.
Address
Mode
Dummy
DLP
D1
D2
Notes
71. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command EDh.
72. A = MSb of address = 31 with command EEh.
Document Number: 002-00488 Rev. *M
Page 96 of 139
S25FS512S
9.5
Program Flash Array Commands
9.5.1
Program Granularity
9.5.1.1 Automatic ECC
Each 16 byte aligned and 16 byte length Programming Block has an automatic Error Correction Code (ECC) value. The data block
plus ECC form an ECC unit. In combination with Error Detection and Correction (EDC) logic the ECC is used to detect and correct
any single bit error found during a read access. When data is first programmed within an ECC unit the ECC value is set for the entire
ECC unit. If the same ECC unit is programmed more than once the ECC value is changed to disable the EDC function. A sector
erase is needed to again enable Automatic ECC on that Programming Block. The 16 byte Program Block is the smallest program
granularity on which Automatic ECC is enabled.
These are automatic operations transparent to the user. The transparency of the Automatic ECC feature enhances data accuracy
for typical programming operations which write data once to each ECC unit but, facilitates software compatibility to previous
generations of FL family of products by still allowing for single byte programming and bit walking in which the same ECC unit is
programmed more than once. When an ECC unit has Automatic ECC disabled, EDC is not done on data read from the ECC unit
location.
An ECC status register is provided for determining if ECC is enabled on an ECC unit and whether any errors have been detected
and corrected in the ECC unit data or the ECC. The ECC Status Register Read (ECCRD) command is used to read the ECC status
on any ECC unit.
Error Detection and Correction (EDC) is applied to all parts of the Flash address spaces other than registers. An Error Correction
Code (ECC) is calculated for each group of bytes protected and the ECC is stored in a hidden area related to the group of bytes. The
group of protected bytes and the related ECC are together called an ECC unit.
ECC is calculated for each 16 byte aligned and length ECC unit
Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1 bit for an ECC disable Flag
Sector erase resets all ECC disable flags in a sector to the default state (enabled)
ECC is programmed as part of the standard Program commands operation
ECC is disabled automatically if multiple programming operations are done on the same ECC unit.
Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16 byte ECC unit.
The ECC disable flag is programmed when ECC is disabled
To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased
To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC is stored for that
unit and not disabled.
The calculation, programming, and disabling of ECC is done automatically as part of programming operations. The detection and
correction if needed is done automatically as part of read operations. The host system sees only corrected data from a read
operation.
ECC protects the OTP region — however a second program operation on the same ECC unit will disable ECC permanently on
that ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC enable/indicator bit is prohibited)
9.5.1.2 Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move
data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single
programming command. Page Programming allows up to a page size (either 256 or 512 bytes) to be programmed in one operation.
The page size is determined by the configuration register bit CR3V[4]. The page is aligned on the page size address boundary. It is
possible to program from one bit up to a page size in each Page programming operation. It is recommended that a multiple of
16-byte length and aligned Program Blocks be written. This insures that Automatic ECC is not disabled. For the very best
performance, programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each Page being
programmed only once.
Document Number: 002-00488 Rev. *M
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S25FS512S
9.5.1.3 Single Byte Programming
Single Byte Programming allows full backward compatibility to the legacy standard SPI Page Programming (PP) command by
allowing a single byte to be programmed anywhere in the memory array. While single byte programming is supported, this will
disable Automatic ECC on the 16 byte ECC unit where the byte is located.
9.5.2
Page Program (PP 02h or 4PP 12h)
The Page Program (PP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). Before the Page
Program (PP) commands can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the
device. After the Write Enable (WREN) command has been decoded successfully, the device sets the Write Enable Latch (WEL) in
the Status Register to enable any write operations.
The instruction
02h (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or
02h (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or
12h is followed by a 4-byte address (A31-A0)
and at least one data byte on SI. Depending on CR3V[4], the page size can either be 256 or 512 bytes. Up to a page can be
provided on SI after the 3-byte address with instruction 02h or 4-byte address with instruction 12h has been provided.
If more data is sent to the device than the space between the starting address and the page aligned end boundary, the data loading
sequence will wrap from the last byte in the page to the zero byte location of the same page and begin overwriting any data
previously loaded in the page. The last page worth of data is programmed in the page. This is a result of the device being equipped
with a page program buffer that is only page size in length. If less than a page of data is sent to the device, these data bytes will be
programmed in sequence, starting at the provided address within the page, without having any affect on the other bytes of the same
page.
Using the Page Program (PP) command to load an entire page, within the page boundary, will save overall programming time
versus loading less than a page into the program buffer.
The programming process is managed by the flash memory device internal control logic. After a programming command is issued,
the programming operation status can be checked using the Read Status Register 1 command. The WIP bit (SR1V[0]) will indicate
when the programming operation is completed. The P_ERR bit (SR1V[6]) will indicate if an error occurs in the programming
operation that prevents successful completion of programming. This includes attempted programming of a protected area.
Figure 83. Page Program (PP 02h or 4PP 12h) Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0 A
5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SO
Phase
Instruction
Address
Input Data 1
Input Data2
Note
73. A = MSb of address = A23 for PP 02h, or A31 for 4PP 12h.
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 84. Page Program (PP 02h or 4PP 12h) QPI Mode Command Sequence
CS#
SCK
IO0
4
0
A-3
4
0
4
0
4
0
4
0
4
0
IO1
5
1
A-2
5
1
5
1
5
1
5
1
5
1
IO2
6
2
A-1
6
2
6
2
6
2
6
2
6
2
IO3
7
3
A
7
3
7
3
7
3
7
3
7
3
Phase
Instruct.
Address
Input D1
Input D2
Input D3
Input D4
Note
74. A = MSb of address = A23 for PP 02h, or A31 for 4PP 12h.
Document Number: 002-00488 Rev. *M
Page 98 of 139
S25FS512S
9.6
Erase Flash Array Commands
9.6.1
Parameter 4 KB-Sector Erase (P4E 20h or 4P4E 21h)
The main flash array address map may be configured to overlay 4-KB parameter sectors over the lowest address portion of the
lowest address uniform sector (bottom parameter sectors) or over the highest address portion of the highest address uniform sector
(top parameter sectors). The main flash array address map may also be configured to have only uniform size sectors. The
parameter sector configuration is controlled by the configuration bit CR3V[3]. The P4E and 4P4E commands are ignored when the
device is configured for uniform sectors only (CR3V[3]=1).
The Parameter 4 KB-sector Erase commands set all the bits of a 4-KB parameter sector to 1 (all bytes are FFh). Before the P4E or
4P4E command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device,
which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
20h [CR2V[7]=0] is followed by a 3-byte address (A23-A0), or
20h [CR2V[7]=1] is followed by a 4-byte address (A31-A0), or
21h is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of the address has been latched in on SI. This
will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the chosen sector of the flash
memory array. If CS# is not driven high after the last bit of address, the sector erase operation will not be executed.
As soon as CS# is driven high, the internal erase cycle will be initiated. With the internal erase cycle in progress, the user can read
the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a 1.
when the erase cycle is in progress and a 0 when the erase cycle has been completed.
A P4E or 4P4E command applied to a sector that has been write protected through the Block Protection bits or ASP, will not be
executed and will set the E_ERR status. A P4E command applied to a sector that is larger than 4 KB will not be executed and will
not set the E_ERR status.
Figure 85. Parameter Sector Erase (P4E 20h or 4P4E 21h) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
Note
75. A = MSb of address = A23 for P4E 20h with CR2V[7]=0, or A31 for P4E 20h with CR2V[7]=1 or 4P4E 21h.
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 86. Parameter Sector Erase (P4E 20h or 4P4E 21h) QPI Mode Command Sequence
CS#
SCK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instructtion
Address
Note
76. A = MSb of address = A23 for P4E 20h with CR2V[7]=0, or A31 for P4E 20h with CR2V[7]=1 or 4P4E 21h.
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S25FS512S
9.6.2
Sector Erase (SE D8h or 4SE DCh)
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the Sector Erase (SE)
command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction
D8h [CR2V[7]=0] is followed by a 3-byte address (A23-A0), or
D8h [CR2V[7]=1] is followed by a 4-byte address (A31-A0), or
DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been latched in on SI. This will
initiate the erase cycle, which involves the pre-programming and erase of the chosen sector. If CS# is not driven high after the last
bit of address, the sector erase operation will not be executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal erase cycle in progress,
the user can read the value of the Write-In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate
a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed.
A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection bits or ASP, will not
be executed and will set the E_ERR status.
A device configuration option (CR3V[3]) determines whether 4-KB parameter sectors are in use. When CR3V[3] = 0, 4-KB
parameter sectors overlay a portion of the highest or lowest address 32-KB of the device address space. If a sector erase command
is applied to a 256-KB range that is overlaid by 4-KB sectors, the overlaid 4-KB sectors are not affected by the erase. When CR3V[3]
= 1, there are no 4-KB parameter sectors in the device address space and the Sector Erase command always operates on fully
visible 256-KB sectors.
ASP has a PPB and a DYB protection bit for each physical sector, including any 4-KB sectors.
Figure 87. Sector Erase (SE D8h or 4SE DCh) Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
Note
77. A = MSb of address = A23 for SE D8h with CR2V[7]=0, or A31 for SE D8h with CR2V[7]=1 or 4P4E DCh.
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 88. Sector Erase (SE D8h or 4SE DCh) QPI Mode Command Sequence
CS#
SCK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instruction
Address
Note
78. A = MSb of address = A23 for SE D8h with CR2V[7]=0, or A31 for SE D8h with CR2V[7]=1 or 4P4E DCh.
Document Number: 002-00488 Rev. *M
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S25FS512S
9.6.3
Bulk Erase (BE 60h or C7h)
The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the BE command
can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write
Enable Latch (WEL) in the Status Register to enable any write operations.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
erase cycle, which involves the pre-programming and erase of the entire flash memory array. If CS# is not driven high after the last
bit of instruction, the BE operation will not be executed.
As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in progress, the user can
read the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a 1
when the erase cycle is in progress and a 0 when the erase cycle has been completed.
A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0s. If the BP bits are not zero, the
BE command is not executed and E_ERR is not set. The BE command will skip any sectors protected by the DYB or PPB and the
E_ERR status will not be set.
Figure 89. Bulk Erase Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode, the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 90. Bulk Erase Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.6.4
Instruction
Evaluate Erase Status (EES D0h)
The Evaluate Erase Status (EES) command verifies that the last erase operation on the addressed sector was completed
successfully. If the selected sector was successfully erased the erase status bit (SR2V[2]) is set to 1. If the selected sector was not
completely erased SR2V[2] is 0.
The EES command can be used to detect erase operations failed due to loss of power, reset, or failure during the erase operation.
The EES instruction is followed by a 3- or 4-byte address, depending on the address length configuration (CR2V[7]). The EES
command requires tEES to complete and update the erase status in SR2V. The WIP bit (SR1V[0]) may be read using the RDSR1
(05h) command, to determine when the EES command is finished. Then the RDSR2 (07h) or the RDAR (65h) command can be
used to read SR2V[2]. If a sector is found not erased with SR2V[2]=0, the sector must be erased again to ensure reliable storage of
data in the sector.
The Write Enable command (to set the WEL bit) is not required before the EES command. However, the WEL bit is set by the device
itself and cleared at the end of the operation, as visible in SR1V[1] when reading status.
Document Number: 002-00488 Rev. *M
Page 101 of 139
S25FS512S
Figure 91. EES Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
Note
79. A = MSb of address = A23 for CR2V[7]=0, or A31 for CR2V[7]=1.
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 92. EES QPI Mode Command Sequence
CS#
SCK
IO0
4
0
A-3
4
0
IO1
5
1
A-2
5
1
IO2
6
2
A-1
6
2
IO3
7
3
A
7
3
Phase
Instruction
Address
Note
80. A = MSb of address = A23 for CR2V[7]=0, or A31 for CR2V[7]=1.
9.6.5
Erase or Program Suspend (EPS 85h, 75h, B0h)
There are three instruction codes for Program or Erase Suspend (EPS) to enable legacy and alternate source software compatibility.
The EPS command allows the system to interrupt a programming or erase operation and then read from any other
non-erase-suspended sector or non-program-suspended-page. Program or Erase Suspend is valid only during a programming or
sector erase operation. A Bulk Erase operation cannot be suspended.
The Write in Progress (WIP) bit in Status Register 1 (SR1V[0]) must be checked to know when the programming or erase operation
has stopped. The Program Suspend Status bit in the Status Register 2 (SR2[0]) can be used to determine if a programming
operation has been suspended or was completed at the time WIP changes to 0. The Erase Suspend Status bit in the Status Register
2 (SR2[1]) can be used to determine if an erase operation has been suspended or was completed at the time WIP changes to 0. The
time required for the suspend operation to complete is tSL, see Table 51 on page 115.
An Erase can be suspended to allow a program operation or a read operation. During an erase suspend, the DYB array may be read
to examine sector protection and written to remove or restore protection on a sector to be programmed.
A program operation may be suspended to allow a read operation.
A new erase operation is not allowed with an already suspended erase or program operation. An erase command is ignored in this
situation.
Document Number: 002-00488 Rev. *M
Page 102 of 139
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Table 49. Commands Allowed During Program or Erase Suspend
Instruction
Name
Instruction
Code (Hex)
Allowed
During
Erase
Suspend
Allowed
During
Program
Suspend
Comment
02
X
–
Required for array program during erase suspend. Only allowed if there is no other
program suspended program operation (SR2V[0]=0). A program command will be
ignored while there is a suspended program. If a program command is sent for a
location within an erase suspended sector the program operation will fail with the
P_ERR bit set.
READ
03
X
X
All array reads allowed in suspend.
RDSR1
05
X
X
Needed to read WIP to determine end of suspend process.
RDAR
65
X
X
Alternate way to read WIP to determine end of suspend process.
WREN
06
X
RDSR2
07
X
PP
Required for program command within erase suspend.
X
Needed to read suspend status to determine whether the operation is suspended or
complete.
4PP
12
X
–
Required for array program during erase suspend. Only allowed if there is no other
program suspended program operation (SR2V[0]=0). A program command will be
ignored while there is a suspended program. If a program command is sent for a
location within an erase suspended sector the program operation will fail with the
P_ERR bit set.
4READ
13
X
X
All array reads allowed in suspend.
CLSR
30
X
–
Clear status may be used if a program operation fails during erase suspend. Note
the instruction is only valid if enabled for clear status by CR4NV[2=1].
CLSR
82
X
–
Clear status may be used if a program operation fails during erase suspend.
EPR
30
X
X
Required to resume from erase or program suspend. Note the command must be
enabled for use as a resume command by CR3NV[2]=1.
EPR
7A
X
X
Required to resume from erase or program suspend.
EPR
8A
X
X
Required to resume from erase or program suspend.
RSTEN
66
X
X
Reset allowed anytime.
RST
99
X
X
Reset allowed anytime.
FAST_READ
0B
X
X
All array reads allowed in suspend.
4FAST_READ
0C
X
X
All array reads allowed in suspend.
EPR
7A
X
–
Required to resume from erase suspend.
EPR
8A
X
–
Required to resume from erase suspend.
DIOR
BB
X
X
All array reads allowed in suspend.
4DIOR
BC
X
X
All array reads allowed in suspend.
DYBRD
FA
X
–
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
DYBWR
FB
X
–
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
PPBRD
FC
X
–
Allowed for checking persistent protection before attempting a program command
during erase suspend.
4DYBRD
E0
X
–
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
4DYBWR
E1
X
–
It may be necessary to remove and restore dynamic protection during erase
suspend to allow programming during erase suspend.
4PPBRD
E2
X
–
Allowed for checking persistent protection before attempting a program command
during erase suspend.
QIOR
EB
X
X
All array reads allowed in suspend.
4QIOR
EC
X
X
All array reads allowed in suspend.
Document Number: 002-00488 Rev. *M
Page 103 of 139
S25FS512S
Table 49. Commands Allowed During Program or Erase Suspend (Continued)
Instruction
Code (Hex)
Allowed
During
Erase
Suspend
Allowed
During
Program
Suspend
DDRQIOR
ED
X
X
All array reads allowed in suspend.
4DDRQIOR
EE
X
X
All array reads allowed in suspend.
RESET
F0
X
X
Reset allowed anytime.
MBR
FF
X
X
May need to reset a read operation during suspend.
Instruction
Name
Comment
Reading at any address within an erase-suspended sector or program-suspended page produces undetermined data.
The WRR, WRAR, or PPB Erase commands are not allowed during Erase or Program Suspend, it is therefore not possible to alter
the Block Protection or PPB bits during Erase Suspend. If there are sectors that may need programming during Erase suspend,
these sectors should be protected only by DYB bits that can be turned off during Erase Suspend.
After an erase-suspended program operation is complete, the device returns to the erase-suspend mode. The system can
determine the status of the program operation by reading the WIP bit in the Status Register, just as in the standard program
operation.
Figure 93. Program or Erase Suspend Command Sequence
tSL
CS#
SCK
SI
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SO
Phase
7 6 5 4 3 21 0
7 6 5 4 3 2 1 0
Suspend Instruction
Read Status Instruction
Phase
Instr. During Suspend
Status
Repeat Status Read Until Suspended
Figure 94. Erase or Program Suspend Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 95. Erase or Program Suspend Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00488 Rev. *M
3
Instruction
Page 104 of 139
S25FS512S
9.6.6
Erase or Program Resume (EPR 7Ah, 8Ah, 30h)
An Erase or Program Resume command must be written to resume a suspended operation. There are three instruction codes for
Erase or Program Resume (EPR) to enable legacy and alternate source software compatibility.
After program or read operations are completed during a program or erase suspend the Erase or Program Resume command is
sent to continue the suspended operation.
After an Erase or Program Resume command is issued, the WIP bit in the Status Register 1 will be set to a 1 and the programming
operation will resume if one is suspended. If no program operation is suspended the suspended erase operation will resume. If there
is no suspended program or erase operation the resume command is ignored.
Program or erase operations may be interrupted as often as necessary, e.g. a program suspend command could immediately follow
a program resume command but, in order for a program or erase operation to progress to completion there must be some periods of
time between resume and the next suspend command greater than or equal to tRS. See Table 51 on page 115.
Figure 96. Erase or Program Resume Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Figure 97. Erase or Program Resume Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
Instruction
9.7
One Time Program Array Commands
9.7.1
OTP Program (OTPP 42h)
The OTP Program command programs data in the One Time Program region, which is in a different address space from the main
array data. The OTP region is 1024 bytes so, the address bits from A31 to A10 must be zero for this command. Refer to OTP
Address Space on page 44 for details on the OTP region.
Before the OTP Program command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded
by the device, which sets the Write Enable Latch (WEL) in the status register to enable any write operations. The WIP bit in SR1V
may be checked to determine when the operation is completed. The P_ERR bit in SR1V may be checked to determine if any error
occurred during the operation.
To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to 1.
Each region in the OTP memory space can be programmed one or more times, provided that the region is not locked. Attempting to
program zeros in a region that is locked will fail with the P_ERR bit in SR1V set to 1. Programming ones, even in a protected area
does not cause an error and does not set P_ERR. Subsequent OTP programming can be performed only on the un-programmed
bits (that is, 1 data). Programming more than once within an ECC unit will disable ECC on that unit.
The protocol of the OTP Program command is the same as the Page Program command. See Page Program (PP 02h or 4PP 12h)
on page 98 for the command sequence.
Document Number: 002-00488 Rev. *M
Page 105 of 139
S25FS512S
9.7.2
OTP Read (OTPR 4Bh)
The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits from A31 to A10 must
be zero for this command. Refer to OTP Address Space on page 44 for details on the OTP region. The protocol of the OTP Read
command is similar to the Fast Read command except that it will not wrap to the starting address after the OTP address is at its
maximum; instead, the data beyond the maximum OTP address will be undefined. The OTP Read command read latency is set by
the latency value in CR2V[3:0]. See Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch) on page 91 for the command sequence.
9.8
Advanced Sector Protection Commands
9.8.1
ASP Read (ASPRD 2Bh)
The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP register contents are
shifted out on the serial output SO, least significant byte first. Each bit is shifted out at the SCK frequency by the falling edge of the
SCK signal. It is possible to read the ASP register continuously by providing multiples of 16 clock cycles. The maximum operating
clock frequency for the ASP Read (ASPRD) command is 133 MHz.
Figure 98. ASPRD Command
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7
Phase
9.8.2
Instruction
6 5 4 3 2 1 0 7
Output ASPR Low Byte
6 5 4 3 2 1 0
Output ASPR High Byte
ASP Program (ASPP 2Fh)
Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to
enable any write operations.
The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data bytes on SI, least
significant byte first. The ASP Register is two data bytes in length.
The ASPP command affects the P_ERR and WIP bits of the status and configuration registers in the same manner as any other
programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the ASPP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed ASPP operation is initiated. While the ASPP operation is in
progress, the status register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
1 during the self-timed ASPP operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable
Latch (WEL) is set to a 0.
Figure 99. ASPP Command
CS#
SCK
SI
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5
4
3 2 1 0
SO
Phase
Document Number: 002-00488 Rev. *M
Instruction
Input ASPR Low Byte
Input ASPR High Byte
Page 106 of 139
S25FS512S
9.8.3
DYB Read (DYBRD FAh or 4DYBRD E0h)
The instruction is latched into SI by the rising edge of the SCK signal. The instruction is followed by the 24- or 32-bit address,
depending on the address length configuration CR2V[7], selecting location zero within the desired sector. Note, the high order
address bits not used by a particular density device must be zero. Then the 8-bit DYB access register contents are shifted out on the
serial output SO. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible to read the same
DYB access register continuously by providing multiples of eight clock cycles. The address of the DYB register does not increment
so this is not a means to read the entire DYB array. Each location must be read with a separate DYB Read command. The maximum
operating clock frequency for READ command is 133 MHz.
Figure 100. DYBRD Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0 A
1 0
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Phase
Address
Instruction
Register
Repeat Register
Notes
81. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FAh.
82. A = MSb of address = 31 with command E0h.
This command is also supported in QPI mode. In QPI mode the instruction and address is shifted in on IO0-IO3 and returning data
is shifted out on IO0-IO3.
Figure 101. DYBRD QPI Mode Command Sequence
CS#
SCK
IO0
4
0
A-3
4
0
4
0
IO1
5
1
A-2
5
1
5
1
IO2
6
2
A-1
6
2
6
2
7
3
A
7
3
7
3
IO3
Phase
Instruction
Address
Output DYBAR
Notes
83. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FAh.
84. A = MSb of address = 31 with command E0h.
9.8.4
DYB Write (DYBWR FBh or 4DYBWR E1h)
Before the DYB Write (DYBWR) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the status register to
enable any write operations.
The DYBWR command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24- or 32-bit
address, depending on the address length configuration CR2V[7], selecting location zero within the desired sector (note, the high
order address bits not used by a particular density device must be zero), then the data byte on SI. The DYB Access Register is one
data byte in length. The data value must be 00h to protect or FFh to unprotect the selected sector.
The DYBWR command affects the P_ERR and WIP bits of the status and configuration registers in the same manner as any other
programming operation. CS# must be driven to the logic high state after the eighth bit of data has been latched in. As soon as CS#
is driven to the logic high state, the self-timed DYBWR operation is initiated. While the DYBWR operation is in progress, the status
register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the
self-timed DYBWR operation, and is a 0 when it is completed. When the DYBWR operation is completed, the Write Enable Latch
(WEL) is set to a 0.
Document Number: 002-00488 Rev. *M
Page 107 of 139
S25FS512S
Figure 102. DYBWR Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0 31
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Phase
Instruction
Address
Input Data
Notes
85. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FBh.
86. A = MSb of address = 31 with command E1h.
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 103. DYBWR QPI Mode Command Sequence
CS#
SCK
IO0
4
0
A-3
4
0
4
0
IO1
5
1
A-2
5
1
5
1
IO2
6
2
A-1
6
2
6
2
7
3
A
7
3
7
3
IO3
Phase
Instruction
Address
Input DYBAR
Notes
87. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FBh.
88. A = MSb of address = 31 with command E1h.
9.8.5
PPB Read (PPBRD FCh or 4PPBRD E2h)
The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 24- or 32-bit address, depending on the
address length configuration CR2V[7], selecting location zero within the desired sector (note, the high order address bits not used by
a particular density device must be zero). Then the 8-bit PPB access register contents are shifted out on SO.
It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles. The address of the PPB
register does not increment so this is not a means to read the entire PPB array. Each location must be read with a separate PPB
Read command. The maximum operating clock frequency for the PPB Read command is 133 MHz.
Figure 104. PPBRD Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0 A
1 0
SO
Phase
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction
Address
Register
Repeat Register
Notes
89. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FCh.
90. A = MSb of address = 31 with command E2h.
Document Number: 002-00488 Rev. *M
Page 108 of 139
S25FS512S
9.8.6
PPB Program (PPBP FDh or 4PPBP E3h)
Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After
the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the status register to
enable any write operations.
The PPBP command is entered by driving CS# to the logic low state, followed by the instruction, followed by the 24 or 32-bit
address, depending on the address length configuration CR2V[7], selecting location zero within the desired sector (note, the high
order address bits not used by a particular density device must be zero).
The PPBP command affects the P_ERR and WIP bits of the status and configuration registers in the same manner as any other
programming operation.
CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is initiated. While the PPBP operation is in
progress, the status register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
1 during the self-timed PPBP operation, and is a 0 when it is completed. When the PPBP operation is completed, the Write Enable
Latch (WEL) is set to a 0.
Figure 105. PPBP Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
A
1
0
SO
Phase
Instruction
Address
Notes
91. A = MSb of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FDh.
92. A = MSb of address = 31 with command E3h.
9.8.7
PPB Erase (PPBE E4h)
The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by the device, a Write
Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the status
register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
beginning of internal erase cycle, which involves the pre-programming and erase of the entire PPB memory array. Without CS#
being driven to the logic high state after the eighth bit of the instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has
been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed.
Erase suspend is not allowed during PPB Erase.
Figure 106. PPB Erase Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Document Number: 002-00488 Rev. *M
Instruction
Page 109 of 139
S25FS512S
9.8.8
PPB Lock Bit Read (PLBRD A7h)
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is possible to read the
PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock Register contents may only be read when
the device is in standby state with no other operation in progress. It is recommended to check the Write-In Progress (WIP) bit of the
status register before issuing a new command to the device.
Figure 107. PPB Lock Register Read Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
7
Phase
9.8.9
6 5 4 3 2 1 0 7
Instruction
Register Read
6 5 4 3 2 1 0
Repeat Register Read
PPB Lock Bit Write (PLBWR A6h)
The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR command can be accepted
by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch
(WEL) in the Status Register to enable any write operations.
The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the PLBWR command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR operation is initiated. While the PLBWR operation
is in progress, the status register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP)
bit is a 1 during the self-timed PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed, the
Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.
Figure 108. PPB Lock Bit Write Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
9.8.10 Password Read (PASSRD E7h)
The correct password value may be read only after it is programmed and before the Password Mode has been selected by
programming the Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected
the password is no longer readable, the PASSRD command will output undefined data.
The PASSRD command is shifted into SI. Then the 64-bit password is shifted out on the serial output SO, least significant byte first,
most significant bit of each byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible
to read the password continuously by providing multiples of 64 clock cycles. The maximum operating clock frequency for the
PASSRD command is 133 MHz.
Figure 109. Password Read Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
SO
Phase
Document Number: 002-00488 Rev. *M
7
Instruction
6 5 4 3 2 1 0 7
Data 1
6 5 4 3 2 1 0
Data N
Page 110 of 139
S25FS512S
9.8.11 Password Program (PASSP E8h)
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device. After the Write Enable (WREN) command has been decoded, the device sets the Write Enable
Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password Mode is selected by programming the Password Protection Mode bit
to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI, least significant byte first, most significant bit of each byte first. The password is 64 bits in length.
CS# must be driven to the logic high state after the 64th bit of data has been latched. If not, the PASSP command is not executed.
As soon as CS# is driven to the logic high state, the self-timed PASSP operation is initiated. While the PASSP operation is in
progress, the status register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
1 during the self-timed PASSP cycle, and is a 0 when it is completed. The PASSP command can report a program error in the
P_ERR bit of the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The
maximum clock frequency for the PASSP command is 133 MHz.
Figure 110. Password Program Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5
4
3 2 1 0
SO
Phase
Instruction
Input Password Low Byte
Input Password High Byte
9.8.12 Password Unlock (PASSU E9h)
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on
SI, least significant byte first, most significant bit of each byte first. The password is 64 bits in length.
CS# must be driven to the logic high state after the 64th bit of data has been latched. If not, the PASSU command is not executed.
As soon as CS# is driven to the logic high state, the self-timed PASSU operation is initiated. While the PASSU operation is in
progress, the status register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a
1 during the self-timed PASSU cycle, and is a 0 when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register, an error is reported by
setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is necessary to use the CLSR command to
clear the status register, the RESET command to software reset the device, or drive the RESET# input low to initiate a hardware
reset, in order to return the P_ERR and WIP bits to 0. This returns the device to standby state, ready for new commands such as a
retry of the PASSU command.
If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU command is 133 MHz.
Figure 111. Password Unlock Command Sequence
CS#
SCK
SI
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SO
Phase
Document Number: 002-00488 Rev. *M
Instruction
Input Password Low Byte
Input Password High
Page 111 of 139
S25FS512S
9.9
Reset Commands
Software controlled Reset commands restore the device to its initial power up state, by reloading volatile registers from nonvolatile
default values. However, the volatile FREEZE bit in the Configuration Register CR1V[0] and the volatile PPB Lock bit in the PPB
Lock Register are not changed by a software reset. The software reset cannot be used to circumvent the FREEZE or PPB Lock bit
protection mechanisms for the other security configuration bits.
The Freeze bit and the PPB Lock bit will remain set at their last value prior to the software reset. To clear the FREEZE bit and set the
PPB Lock bit to its protection mode selected power on state, a full power-on-reset sequence or hardware reset must be done.
The nonvolatile bits in the configuration register (CR1NV), TBPROT_O, TBPARM, and BPNV_O, retain their previous state after a
Software Reset.
The Block Protection bits BP2, BP1, and BP0, in the status register (SR1V) will only be reset to their default value if FREEZE = 0.
A reset command (RST or RESET) is executed when CS# is brought high at the end of the instruction and requires tRPH time to
execute.
In the case of a previous Power-up Reset (POR) failure to complete, a reset command triggers a full power-up sequence requiring
tPU to complete.
Figure 112. Software Reset Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 113. Software Reset Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Phase
9.9.1
Instruction
Software Reset Enable (RSTEN 66h)
The Reset Enable (RSTEN) command is required immediately before a Reset command (RST) such that a software reset is a
sequence of the two commands. Any command other than RST following the RSTEN command, will clear the reset enable condition
and prevent a later RST command from being recognized.
9.9.2
Software Reset (RST 99h)
The Reset (RST) command immediately following a RSTEN command, initiates the software reset process.
9.9.3
Legacy Software Reset (RESET F0h)
The Legacy Software Reset (RESET) is a single command that initiates the software reset process. This command is disabled by
default but can be enabled by programming CR3V[0]=1, for software compatibility with Cypress legacy FL-S devices.
Document Number: 002-00488 Rev. *M
Page 112 of 139
S25FS512S
9.9.4
Mode Bit Reset (MBR FFh)
The Mode Bit Reset (MBR) command is used to return the device from continuous high performance read mode back to normal
standby awaiting any new command. Because some device packages lack a hardware RESET# input and a device that is in a
continuous high performance read mode may not recognize any normal SPI command, a system hardware reset or software reset
command may not be recognized by the device. It is recommended to use the MBR command after a system reset when the
RESET# signal is not available or, before sending a software reset, to ensure the device is released from continuous high
performance read mode.
The MBR command sends Ones on SI or IO0 for 8 SCK cycles. IO1 to IO3 are ‘don’t care’ during these cycles.
Figure 114. Mode Bit Reset Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 115. Mode Bit Reset Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
9.10
3
Instruction
DPD Commands
9.10.1 Enter Deep Power-Down (DPD B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep
Power-Down command. The lower power consumption makes the Deep Power-Down (DPD) command especially useful for battery
powered applications (see IDPD in Section 4.6 DC Characteristics on page 25).
The DPD command is accepted only while the device is not performing an embedded algorithm as indicated by the Status Register
1 volatile Write In Progress (WIP) bit being cleared to zero (SR1V[0] = 0).
The command is initiated by driving the CS# pin low and shifting the instruction code ‘B9h’ as shown in Figure 116 on page 114. The
CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power-Down command will not be
executed. After CS# is driven high, the power-down state will be entered within the time duration of t DPD (refer to Timing
Specifications on page 28).
While in the power-down state only the Release from Deep Power-Down command, which restores the device to normal operation,
will be recognized. All other commands are ignored. This includes the Read Status Register command, which is always available
during normal operation. Ignoring all but one command also makes the Power Down state useful for write protection. The device
always powers-up in the interface standby state with the standby current of ICC1.
Document Number: 002-00488 Rev. *M
Page 113 of 139
S25FS512S
Figure 116. Deep Power-Down Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 117. DPD Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
3
Instruction
9.10.2 Release from Deep Power-Down (RES ABh)
The Release from Deep Power-Down command is used to release the device from the deep power-down state. In some legacy SPI
devices the RES command could also be used to obtain the device electronic identification (ID) number. However, the device ID
function is not supported by the RES command.
To release the device from the deep power-down state, the command is issued by driving the CS# pin low, shifting the instruction
code ‘ABh’ and driving CS# high as shown in Figure 118 on page 114. Release from deep power-down will take the time duration of
tRES (Timing Specifications on page 28) before the device will resume normal operation and other commands are accepted. The
CS# pin must remain high during the tRES time duration.
Hardware Reset will also release the device from the DPD state as part of the hardware reset process.
Figure 118. Release from Deep Power-Down Command Sequence
CS#
SCK
SI
7
6
5
4
3
2
1
0
SO
Phase
Instruction
This command is also supported in QPI mode. In QPI mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.
Figure 119. RES Command Sequence QPI Mode
CS#
SCK
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
Phase
Document Number: 002-00488 Rev. *M
3
Instruction
Page 114 of 139
S25FS512S
10. Embedded Algorithm Performance Tables
Table 50. Program and Erase Performance
Symbol
tW
tPP
tSE
tBE [93]
tEES
Parameter
Min
Typ [94]
Max
Unit
Nonvolatile Register Write Time
240
750
ms
Page Programming (512 bytes)
Page Programming (256 bytes)
475
360
2000
2000
µs
Sector Erase Time (256 KB physical sectors)
930
2900
Sector Erase Time (4 KB sectors)
240
725
Bulk Erase Time (S25FS512S)
220
720
Evaluate Erase Status Time (64-KB or 4-KB physical sectors)
20
25
Evaluate Erase Status Time (256-KB physical or logical sectors)
80
100
ms
sec
µs
Notes
93. Not 100% tested.
94. Typical program and erase times assume the following conditions: 25°C, VCC = 1.8V; random data pattern.
95. The programming time for any OTP programming command is the same as tPP. This includes OTPP 42h, PNVDLR 43h, ASPP 2Fh, and PASSP E8h.
96. The programming time for the PPBP E3h command is the same as tPP. The erase time for PPBE E4h command is the same as tSE.
97. Data retention of 20 years is based on 1k erase cycles or less.
Table 51. Program or Erase Suspend AC Parameters
Parameter
Typical
Suspend Latency (tSL)
Resume to next Program Suspend (tRS)
100
Document Number: 002-00488 Rev. *M
Max
Unit
Comments
50
µs
The time from Suspend command until the WIP bit is 0.
µs
Minimum is the time needed to issue the next Suspend command but ≥ typical
periods are needed for Program or Erase to progress to completion.
Page 115 of 139
S25FS512S
11. Data Integrity
11.1
Erase Endurance
Table 52. Erase Endurance
Minimum
Unit
Program/Erase cycles per main Flash array sectors
Parameter
100K
P/E cycle
Program/Erase cycles per PPB array or Nonvolatile register array [98]
100K
P/E cycle
Note
98. Each write command to a nonvolatile register causes a P/ E cycle on the entire nonvolatile register array. OTP bits and registers internally reside in a separate array
that is not P/E cycled.
11.2
Data Retention
Table 53. Data Retention
Parameter
Data Retention Time
Test Conditions
Minimum Time
Unit
10K Program/Erase Cycles
20
Years
100K Program/Erase Cycles
2
Years
Contact Cypress Sales or an FAE representative for additional information on data integrity. An application note is available at:
www.cypress.com/appnotes.
11.3
Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides a pointer to
each parameter. One parameter is mandated by the JEDEC JESD216 standard. Cypress provides an additional parameter by
pointing to the ID-CFI address space, i.e. the ID-CFI address space is a sub-set of the SFDP address space. The JEDEC parameter
is located within the ID-CFI address space and is thus both a CFI parameter and an SFDP parameter. In this way both SFDP and
ID-CFI information can be accessed by either the RSFDP or RDID commands.
Table 54. SFDP Overview Map
Byte Address
Description
0000h
Location zero within JEDEC JESD216B SFDP space – start of SFDP header
,,,
Remainder of SFDP header followed by undefined space
1000h
Location zero within ID-CFI space – start of ID-CFI parameter tables
...
ID-CFI parameters
1090h
Start of SFDP parameter tables which are also grouped as one of the CFI parameter tables (the CFI parameter itself starts at
108Eh, the SFDP parameter table data is double word aligned starting at 1090h)
...
Remainder of SFDP parameter tables followed by either more CFI parameters or undefined space
Document Number: 002-00488 Rev. *M
Page 116 of 139
S25FS512S
11.3.1 Field Definitions
Table 55. SFDP Header
SFDP Byte SFDP Dword
Address
Name
Data
Description
This is the entry point for Read SFDP (5Ah) command i.e. location zero within SFDP space
ASCII “S”
00h
53h
01h
ASCII “F”
02h
SFDP Header 46h
1st DWORD
44h
03h
50h
ASCII “P”
06h
SFDP Minor Revision (06h = JEDEC JESD216 Revision B)
This revision is backward compatible with all prior minor revisions. Minor revisions are changes that
define previously reserved fields, add fields to the end, or that clarify definitions of existing fields.
Increments of the minor revision value indicate that previously reserved parameter fields may have been
assigned a new definition or entire Dwords may have been added to the parameter table. However, the
definition of previously existing fields is unchanged and therefore remain backward compatible with
earlier SFDP parameter table revisions. Software can safely ignore increments of the minor revision
number, as long as only those parameters the software was designed to support are used i.e. previously
reserved fields and additional Dwords must be masked or ignored . Do not do a simple compare on the
minor revision number, looking only for a match with the revision number that the software is designed to
handle. There is no problem with using a higher number minor revision.
01h
SFDP Major Revision
This is the original major revision. This major revision is compatible with all SFDP reading and parsing
software.
04h
SFDP Header
2nd DWORD
05h
ASCII “D”
06h
05h
Number of Parameter Headers (zero based, 05h = 6 parameters)
07h
FFh
Unused
08h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
00h
Parameter Minor Revision (00h = JESD216)
- This older revision parameter header is provided for any legacy SFDP reading and parsing software
that requires seeing a minor revision 0 parameter header. SFDP software designed to handle later minor
revisions should continue reading parameter headers looking for a higher numbered minor revision that
contains additional parameters for that software revision.
0Ah
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is compatible with this
major revision.
0Bh
09h
Parameter Table Length (in double words = Dwords = 4 byte units) 09h = 9 Dwords
0Ch
90h
Parameter Table Pointer Byte 0 (Dword = 4-byte aligned)
JEDEC Basic SPI Flash parameter byte offset = 1090h
09h
0Dh
0Eh
Parameter
Header 0
1st DWORD
Parameter
Header 0
2nd DWORD
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
0Fh
FFh
Parameter ID MSB (FFh = JEDEC defined legacy Parameter ID)
10h
00h
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
05h
Parameter Minor Revision (05h = JESD216 Revision A)
- This older revision parameter header is provided for any legacy SFDP reading and parsing software
that requires seeing a minor revision 5 parameter header. SFDP software designed to handle later minor
revisions should continue reading parameter headers looking for a later minor revision that contains
additional parameters.
12h
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is compatible with this
major revision.
13h
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
14h
90h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC Basic SPI Flash parameter byte offset = 1090h address
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
11h
15h
16h
17h
Parameter
Header 1
1st DWORD
Parameter
Header 1
2nd DWORD
Document Number: 002-00488 Rev. *M
Page 117 of 139
S25FS512S
Table 55. SFDP Header (Continued)
SFDP Byte SFDP Dword
Address
Name
00h
18h
19h
Data
Description
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
06h
Parameter Minor Revision (06h = JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software is compatible with this
major revision.
1Bh
10h
Parameter Table Length (in double words = Dwords = 4 byte units) 10h = 16 Dwords
1Ch
90h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC Basic SPI Flash parameter byte offset = 1090h address
10h
Parameter Table Pointer Byte 1
1Ah
1Dh
1Eh
Parameter
Header 2
1st DWORD
Parameter
Header 2
2nd DWORD
00h
Parameter Table Pointer Byte 2
1Fh
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
20h
81h
Parameter ID LSB (81h = SFDP Sector Map Parameter)
21h
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that recognizes this
parameter’s ID is compatible with this major revision.
22h
Parameter
Header 3
1st DWORD
23h
10h
Mb)
24h
D8h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC parameter byte offset = 10D8h
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
25h
26h
Parameter
Header 3
2nd DWORD
27h
(512 Parameter Table Length (in double words = Dwords = 4 byte units) OPN Dependent
16 = 10h (512 Mb)
28h
84h
Parameter ID LSB (00h = SFDP 4 Byte Address Instructions Parameter)
29h
00h
Parameter Minor Revision (00h = Initial version as defined in JESD216 Revision B)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that recognizes this
parameter’s ID is compatible with this major revision.
2Bh
02h
Parameter Table Length (in double words = Dwords = 4 byte units) (2h = 2 Dwords)
2Ch
D0h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
JEDEC parameter byte offset = 10D0h
2Ah
2Dh
2Eh
Parameter
Header 4
1st DWORD
Parameter
Header 4
2nd DWORD
2Fh
30h
31h
32h
Parameter
Header 5
1st DWORD
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
FFh
Parameter ID MSB (FFh = JEDEC defined Parameter)
01h
Parameter ID LSB (Cypress Vendor Specific ID-CFI parameter)
Legacy Manufacturer ID 01h = AMD / Cypress
01h
Parameter Minor Revision (01h = ID-CFI updated with SFDP Rev B table)
01h
Parameter Major Revision (01h = The original major revision - all SFDP software that recognizes this
parameter’s ID is compatible with this major revision.
33h
47h
Mb)
34h
00h
Parameter Table Pointer Byte 0 (Dword = 4 byte aligned)
Entry point for ID-CFI parameter is byte offset = 1000h relative to SFDP location zero.
10h
Parameter Table Pointer Byte 1
00h
Parameter Table Pointer Byte 2
01h
Parameter ID MSB (01h = JEDEC JEP106 Bank Number 1)
35h
36h
37h
Parameter
Header 5
2nd DWORD
(512 Parameter Table Length (in double words = Dwords = 4 byte units) Parameter Table Length (in double
words = Dwords = 4 byte units)
Document Number: 002-00488 Rev. *M
Page 118 of 139
S25FS512S
11.4
Device ID and Common Flash Interface (ID-CFI) Address Map
11.4.1 Field Definitions
Table 56. Manufacturer and Device ID
Byte Address
Data
Description
00h
01h
Manufacturer ID for Cypress
01h
02h (512 Mb)
Device ID Most Significant Byte — Memory Interface Type
02h
20h (512 Mb)
Device ID Least Significant Byte — Density
03h
4Dh
ID-CFI Length - number bytes following. Adding this value to the current location of 03h
gives the address of the last valid location in the ID-CFI legacy address map. The legacy
CFI address map ends with the Primary Vendor-Specific Extended Query. The original
legacy length is maintained for backward software compatibility. However, the CFI Query
Identification String also includes a pointer to the Alternate Vendor-Specific Extended
Query that contains additional information related to the FS-S family.
04h
00h
(Uniform
sectors)
05h
81h (S25FS512S)
Family ID
06h
xxh
07h
xxh
ASCII characters for Model. Refer to Section 12. Ordering Part Number on page 135 for
the model number definitions.
08h
xxh
Reserved
256-KB
physical
Physical Sector Architecture
The S25FS512S may be configured with or without 4-KB parameter sectors in addition to
the uniform sectors.
09h
xxh
Reserved
0Ah
xxh
Reserved
0Bh
xxh
Reserved
0Ch
xxh
Reserved
0Dh
xxh
Reserved
0Eh
xxh
Reserved
0Fh
xxh
Reserved
Table 57. CFI Query Identification String
Byte Address
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
FL-P backward compatible command set ID
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
53h
46h
Alternate OEM Command Set
ASCII characters “FS” for SPI (F) interface, S Technology
19h
1Ah
51h
00h
Address for Alternate OEM Extended Table
Document Number: 002-00488 Rev. *M
Page 119 of 139
S25FS512S
Table 58. CFI System Interface String
Byte Address
Data
Description
1Bh
17h
VCC Min. (erase / program): 100 millivolts BCD)
1Ch
19h
VCC Max. (erase / program): 100 millivolts BCD)
1Dh
00h
VPP Min. voltage (00h = no VPP present)
1Eh
00h
VPP Max. voltage (00h = no VPP present)
1Fh
09h
Typical timeout per single byte program 2N µs
20h
09h
Typical timeout for Min. size Page program 2N µs (00h = not supported)
21h
0Ah (256 KB)
Typical timeout per individual sector erase 2N ms
22h
11h (512 Mb)
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
02h
Max. timeout for byte program 2N times typical
24h
02h
Max. timeout for page program 2N times typical
25h
03h
Max. timeout per individual sector erase 2N times typical
26h
03h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 59. Device Geometry Definition for Bottom Boot Initial Delivery State
Byte Address
Data
Description
27h
1Ah (512 Mb)
Device Size = 2N bytes
28h
02h
29h
01h
Flash Device Interface Description:
0000h = x8 only
0001h = x16 only
0002h = x8/x16 capable
0003h = x32 only
0004h = Single I/O SPI, 3-byte address
0005h = Multi I/O SPI, 3-byte address
0102h = Multi I/O SPI, 3- or 4-byte address
2Ah
08h
2Bh
00h
2Ch
03h
2Dh
07h
2Eh
00h
2Fh
10h
30h
00h
31h
00h
32h
00h
33h
80h
34h
00h (128 Mb)
00h (256 Mb)
03h (512 Mb)
Document Number: 002-00488 Rev. *M
Max. number of bytes in multi-byte write = 2N
0000h = not supported
0008h = 256B page
0009h = 512B page
Number of Erase Block Regions within device
1 = Uniform Device, >1 = Boot Device
Erase Block Region 1 Information (refer to JEDEC JEP137)
8 sectors = 8-1 = 0007h
4-KB sectors = 256 bytes x 0010h
Erase Block Region 2 Information (refer to JEDEC JEP137)
512 Mb:
1 sectors = 1-1 = 0000h
224-KB sector = 256 bytes x 0380h
Page 120 of 139
S25FS512S
Table 59. Device Geometry Definition for Bottom Boot Initial Delivery State (Continued)
Byte Address
Data
35h
FEh
36h
00h (128 Mb)
01h (256 Mb)
00h (512 Mb)
01h (1 Gb
37h
00h
38h
01h (128 Mb)
01h (256 Mb)
04h (512 Mb)
04h (1 Gb)
39h thru 3Fh
FFh
Description
Erase Block Region 3 Information
512 Mb:
255 sectors = 255-1 = 00FEh
256-KB sectors = 0400h x 256 bytes
RFU
Note
99. FS512S devices are user configurable to have either a hybrid sector architecture (with eight 4-KB sectors / one 224-KB sector and all remaining sectors are uniform
256 KB) or a uniform sector architecture with all sectors uniform 256 KB. FS-S devices are also user configurable to have the 4-KB parameter sectors at the top of
memory address space. The CFI geometry information of the above table is relevant only to the initial delivery state. All devices are initially shipped from Cypress with
the hybrid sector architecture with the 4-KB sectors located at the bottom of the array address map. However, the device configuration TBPARM bit CR1NV[2] may be
programed to invert the sector map to place the 4-KB sectors at the top of the array address map. The 20h_NV bit (CR3NV[3} may be programmed to remove the 4-KB
sectors from the address map. The flash device driver software must examine the TBPARM and 20h_NV bits to determine if the sector map was inverted or hybrid
sectors removed at a later time.
Table 60. CFI Primary Vendor-Specific Extended Query
Byte Address
Data
40h
50h
41h
52h
42h
49h
Description
Query-unique ASCII string “PRI”
43h
31h
Major version number = 1, ASCII
44h
33h
Minor version number = 3, ASCII
45h
21h
Address Sensitive Unlock (Bits 1-0)
00b = Required, 01b = Not Required
Process Technology (Bits 5-2)
0000b = 0.23 µm Floating Gate
0001b = 0.17 µm Floating Gate
0010b = 0.23 µm MirrorBit
0011b = 0.11 µm Floating Gate
0100b = 0.11 µm MirrorBit
0101b = 0.09 µm MirrorBit
1000b = 0.065 µm MirrorBit
46h
02h
Erase Suspend
0 = Not Supported, 1 = Read Only, 2 = Read and Program
47h
01h
Sector Protect
00 = Not Supported, X = Number of sectors in group
48h
00h
Temporary Sector Unprotect
00 = Not Supported, 01 = Supported
49h
08h
Sector Protect/Unprotect Scheme
04 = High Voltage Method
05 = Software Command Locking Method
08 = Advanced Sector Protection Method
4Ah
00h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors
4Bh
01h
Burst Mode (Synchronous sequential read) support
00 = Not Supported, 01 = Supported
Document Number: 002-00488 Rev. *M
Page 121 of 139
S25FS512S
Table 60. CFI Primary Vendor-Specific Extended Query (Continued)
Byte Address
Data
Description
4Ch
03h
Page Mode Type, initial delivery configuration, user configurable for 512B page
00 = Not Supported, 01 = 4 Word Read Page, 02 = 8 Read Word Page, 03 = 256 Byte Program Page, 04 = 512
Byte Program Page
4Dh
00h
ACC (Acceleration) Supply Minimum
00 = Not Supported, 100 mV
4Eh
00h
ACC (Acceleration) Supply Maximum
00 = Not Supported, 100 mV
4Fh
07h
WP# Protection
01 = Whole Chip
04 = Uniform Device with Bottom WP Protect
05 = Uniform Device with Top WP Protect
07 = Uniform Device with Top or Bottom Write Protect (user configurable)
50h
01h
Program Suspend
00 = Not Supported, 01 = Supported
The Alternate Vendor-Specific Extended Query provides information related to the expanded command set provided by the FS-S
family. The alternate query parameters use a format in which each parameter begins with an identifier byte and a parameter length
byte. Driver software can check each parameter ID and can use the length value to skip to the next parameter if the parameter is not
needed or not recognized by the software.
Table 61. CFI Alternate Vendor-Specific Extended Query Header
Byte Address
Data
51h
41h
52h
4Ch
Description
Query-unique ASCII string “ALT”
53h
54h
54h
32h
Major version number = 2, ASCII
55h
30h
Minor version number = 0, ASCII
Table 62. CFI Alternate Vendor-Specific Extended Query Parameter 0
Parameter Relative
Byte Address Offset
Data
Description
00h
00h
Parameter ID (Ordering Part Number)
01h
10h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
53h
ASCII “S” for manufacturer (Cypress)
03h
32h
04h
35h
05h
46h
06h
53h
07h
35h (512 Mb)
08h
31h (512 Mb)
09h
32h (512 Mb)
0Ah
53h
0Bh
FFh
0Ch
FFh
0Dh
FFh
0Eh
FFh
0Fh
FFh
Document Number: 002-00488 Rev. *M
ASCII “25” for Product Characters (Single Die SPI)
ASCII “FS” for Interface Characters (SPI 1.8Volt)
ASCII characters for density
ASCII “S” for Technology (65nm MirrorBit)
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Page 122 of 139
S25FS512S
Table 62. CFI Alternate Vendor-Specific Extended Query Parameter 0 (Continued)
Parameter Relative
Byte Address Offset
Data
10h
xxh
11h
xxh
Description
ASCII characters for Model.
Refer to Section 12. Ordering Part Number on page 135 for the model number definitions.
Table 63. CFI Alternate Vendor-Specific Extended Query Parameter 80h Address Options
Parameter Relative
Byte Address Offset
Data
Description
00h
80h
Parameter ID (Ordering Part Number)
01h
01h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
EBh
Bits 7:5 – Reserved = 111b
Bit 4 – Address Length Bit in CR2V[7] – Yes= 0b
Bit 3 – AutoBoot support – No = 1b
Bit 2 – 4 byte address instructions supported – Yes= 0b
Bit 1 – Bank address + 3 byte address instructions supported –No = 1b
Bit 0 - 3 byte address instructions supported – No = 1b
02h
Table 64. CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands
Parameter Relative
Byte Address Offset
Data
Description
00h
84h
Parameter ID (Suspend Commands
01h
08h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
75h
Program suspend instruction code
03h
32h
Program suspend latency maximum (µs)
04h
7Ah
Program resume instruction code
05h
64h
Program resume to next suspend typical (µs)
06h
75h
Erase suspend instruction code
07h
32h
Erase suspend latency maximum (µs)
08h
7Ah
Erase resume instruction code
09h
64h
Erase resume to next suspend typical (µs)
Table 65. CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection
Parameter Relative
Byte Address Offset
00h
Data
Description
88h
Parameter ID (Data Protection)
01h
04h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
0Ah
OTP size 2N bytes, FFh = not supported
03h
01h
OTP address map format, 01h = FL-S and FS-S format, FFh = not supported
04h
xxh
Block Protect Type, model dependent
00h = FL-P, FL-S, FS-S
FFh = not supported
05h
xxh
Advanced Sector Protection type, model dependent
01h = FL-S and FS-S ASP
Document Number: 002-00488 Rev. *M
Page 123 of 139
S25FS512S
Table 66. CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing
Parameter Relative
Byte Address Offset
Data
Description
00h
8Ch
Parameter ID (Reset Timing)
01h
06h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
96h
POR maximum value
03h
01h
POR maximum exponent 2N µs
04h
23h
Hardware Reset maximum value, FFh = not supported (the initial delivery state has hardware
reset disabled but it may be enabled by the user at a later time)
05h
00h
Hardware Reset maximum exponent 2N µs
06h
23h
Software Reset maximum value, FFh = not supported
07h
00h
Software Reset maximum exponent 2N µs
Table 67. CFI Alternate Vendor-Specific Extended Query Parameter 94h ECC
Parameter Relative
Byte Address Offset
Data
Description
00h
94h
Parameter ID (ECC)
01h
01h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
10h
ECC unit size byte, FFh = ECC disabled
Table 68. CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU
Parameter Relative
Byte Address Offset
Data
Description
00h
F0h
Parameter ID (RFU)
01h
09h
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
02h
FFh
RFU
...
FFh
RFU
0Ah
FFh
RFU
This parameter type (Parameter ID F0h) may appear multiple times and have a different length each time. The parameter is used to
reserve space in the ID-CFI map or to force space (pad) to align a following parameter to a required boundary.
11.4.1.1 JEDEC SFDP Rev B Parameter Tables
From the view point of the CFI data structure, all of the SFDP parameter tables are combined into a single CFI Parameter as a
contiguous byte sequence.
From the viewpoint of the SFDP data structure, there are three independent parameter tables. Two of the tables have a fixed length
and one table has a variable structure and length depending on the device density Ordering Part Number (OPN). The Basic Flash
Parameter table and the 4-byte Address Instructions Parameter table have a fixed length and are presented below as a single table.
This table is Section 1 of the overall CFI parameter.
The JEDEC Sector Map Parameter table structure and length depends on the density OPN and is presented as a set of tables, one
for each device density. The appropriate table for the OPN is Section 2 of the overall CFI parameter and is appended to Section 1.
Document Number: 002-00488 Rev. *M
Page 124 of 139
S25FS512S
Table 69. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4-Byte Address Instructions Parameter
CFI
Parameter
Relative
Byte
Address
Offset
SFDP
Parameter
Relative
Byte
Address
Offset
SFDP Dword
Name
00h
--
N/A
A5h
01h
--
N/A
CFI Parameter Length (The number of following bytes in this parameter. Adding this value to
88h (512 Mb) the current location value +1 = the first byte of the next parameter). OPN dependent:
18Dw + 16Dw = 34Dw * 4B = 136B = 88h B (512 Mb)
02h
00h
03h
01h
04h
02h
Data
E7h
JEDEC
Basic Flash
Parameter
Dword-1
Bits 15:8 = Uniform 4-KB erase opcode = not supported = FFh
B2h
(FSxxxSAG)
BAh
(FSxxxSDS)
Bits 31:24 = Unused = FFh
03h
FFh
04h
FFh
07h
05h
08h
06h
09h
07h
0Ah
08h
0Bh
09h
0Ch
0Ah
0Dh
0Bh
0Eh
0Fh
0Ch
0Dh
JEDEC
Basic Flash
Parameter
Dword-4
Start of SFDP JEDEC parameter, located at 1090h in the overall SFDP address space.
Bits 7:5 = unused = 111b
Bit 4:3 = 06h is status register write instruction and status register is default nonvolatile= 00b
Bit 2 = Program Buffer > 64 bytes = 1
Bits 1:0 = Uniform 4-KB erase unavailable = 11b
Bit 23 = Unused = 1b
Bit 22 = Supports Quad Out Read = No = 0b
Bit 21 = Supports Quad I/O Read = Yes =1b
Bit 20 = Supports Dual I/O Read = Yes = 1b
Bit19 = Supports DDR 0= No, 1 = Yes; FS-SAG = 0b, FS-SDS = 1b
Bit 18:17 = Number of Address Bytes, 3 or 4 = 01b
Bit 16 = Supports Dual Out Read = No = 0b
06h
JEDEC
Basic Flash
Parameter
Dword-3
CFI Parameter ID (JEDEC SFDP)
FFh
05h
JEDEC
Basic Flash
Parameter
Dword-2
Description
FFh
FFh
Density in bits, zero based, 512 Mb = 1FFFFFFFh
1Fh (512 Mb)
48h
Bits 7:5 = number of Quad I/O (1-4-4) Mode cycles = 010b
Bits 4:0 = number of Quad I/O Dummy cycles = 01000b (Initial Delivery State)
EBh
Quad I/O instruction code
FFh
Bits 23:21 = number of Quad Out (1-1-4) Mode cycles = 111b
Bits 20:16 = number of Quad Out Dummy cycles = 11111b
FFh
Quad Out instruction code
FFh
Bits 7:5 = number of Dual Out (1-1-2) Mode cycles = 111b
Bits 4:0 = number of Dual Out Dummy cycles = 11111b
FFh
Dual Out instruction code
88h
Bits 23:21 = number of Dual I/O (1-2-2) Mode cycles = 100b
Bits 20:16 = number of Dual I/O Dummy cycles = 01000b (Initial Delivery State)
10h
0Eh
11h
0Fh
BBh
Dual I/O instruction code
12h
10h
FEh
Bits 7:5 RFU = 111b
Bit 4 = QPI supported = Yes = 1b
Bits 3:1 RFU = 111b
Bit 0 = Dual All not supported = 0b
13h
11h
FFh
Bits 15:8 = RFU = FFh
14h
12h
FFh
Bits 23:16 = RFU = FFh
JEDEC
Basic Flash
Parameter
Dword-5
15h
13h
FFh
Bits 31:24 = RFU = FFh
16h
14h
FFh
Bits 7:0 = RFU = FFh
17h
15h
18h
16h
19h
17h
JEDEC
Basic Flash
Parameter
Dword-6
FFh
Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
FFh
Dual All instruction code
Document Number: 002-00488 Rev. *M
Page 125 of 139
S25FS512S
Table 69. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4-Byte Address Instructions Parameter (Continued)
CFI
Parameter
Relative
Byte
Address
Offset
1Ah
1Bh
1Ch
SFDP
Parameter
Relative
Byte
Address
Offset
SFDP Dword
Name
FFh
18h
19h
1Ah
Data
JEDEC
Basic Flash
Parameter
Dword-7
Description
Bits 7:0 = RFU = FFh
FFh
Bits 15:8 = RFU = FFh
48h
Bits 23:21 = number of QPI Mode cycles = 010b
Bits 20:16 = number of QPI Dummy cycles = 01000b
1Dh
1Bh
EBh
QPI mode Quad I/O (4-4-4) instruction code
1Eh
1Ch
0Ch
Erase type 1 size 2N bytes = 4 KB = 0Ch for Hybrid (Initial Delivery State)
1Fh
1Dh
20h
1Eh
JEDEC
Basic Flash
Parameter
Dword-8
20h
Erase type 1 instruction
10h
Erase type 2 size 2N bytes = 64 KB = 10h
21h
1Fh
22h
20h
23h
21h
24h
22h
25h
23h
FFh
Erase type 4 instruction = not supported = FFh
26h
24h
82h
27h
25h
42h
28h
26h
11h
Bits 31:30 = Erase type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:
1 s) = 1S = 11b (RFU)
Bits 29:25 = Erase type 4 Erase, Typical time count = 11111b (RFU)
Bits 24:23 = Erase type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:
1 s) = 128mS = 10b
Bits 22:18 = Erase type 3 Erase, Typical time count = 00100b (typ erase time = count +1 *
units = 5*128mS = 640mS)
Bits 17:16 = Erase type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:
1 s) = 16mS = 01b
Bits 15:11 = Erase type 2 Erase, Typical time count = 01000b ( typ erase time = count +1 *
units = 9*16mS = 144mS)
Bits 10:9 = Erase type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1
s) = 16mS = 01b
Bits 8:4 = Erase type 1 Erase, Typical time count = 01000b ( typ erase time = count +1 * units
= 9*16mS = 144mS)
Bits 3:0 = Multiplier from typical erase time to maximum erase time = 2*(N+1), N=2h = 6x
multiplier
29h
27h
JEDEC
Basic Flash
Parameter
Dword-9
JEDEC
Basic Flash
Parameter
Dword-10
D8h
Erase type 2 instruction
12h
Erase type 3 size 2N bytes = 256 KB = 12h
D8h
Erase type 3 instruction
00h
Erase type 4 size 2N bytes = not supported = 00h
FFh
Binary Fields: 11-11111-10-00100-01-01000-01-01000-0010
Nibble Format: 1111_1111_0001_0001_0100_0010_1000_0010
Hex Format: FF_11_42_82
Document Number: 002-00488 Rev. *M
Page 126 of 139
S25FS512S
Table 69. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4-Byte Address Instructions Parameter (Continued)
CFI
Parameter
Relative
Byte
Address
Offset
SFDP
Parameter
Relative
Byte
Address
Offset
SFDP Dword
Name
Data
2Ah
28h
91h
2Bh
29h
26h
2Ch
2Ah
07h
JEDEC
Basic Flash
Parameter
Dword-11
2Dh
2Bh
2Eh
2Ch
ECh
2Fh
2Dh
83h
30h
2Eh
18h
31h
2Fh
JEDEC
Basic Flash
Parameter
Dword-12
E2h (512 Mb)
44h
Description
Bit 31 Reserved = 1b
Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) =
512 Mb = 64s = 11b
Bits 28:24 = Chip Erase, Typical time count, (count+1)*units,
512 Mb = 00010b = 2+1*64uS = 192s
Bits 23 = Byte Program Typical time, additional byte units (0b:1uS, 1b:8uS) = 1uS = 0b
Bits 22:19 = Byte Program Typical time, additional byte count, (count+1)*units, count = 0000b,
(typ Program time = count +1 * units = 1*1uS = 1uS
Bits 18 = Byte Program Typical time, first byte units (0b:1uS, 1b:8uS) = 8uS = 1b
Bits 17:14 = Byte Program Typical time, first byte count, (count+1)*units, count = 1100b, ( typ
Program time = count +1 * units = 13*8uS = 104uS
Bits 13 = Page Program Typical time units (0b:8uS, 1b:64uS) = 64uS = 1b
Bits 12:8 = Page Program Typical time count, (count+1)*units, count = 00110b, ( typ Program
time = count +1 * units = 7*64uS = 448uS)
Bits 7:4 = Page size 2N, N=9h, = 512B page
Bits 3:0 = Multiplier from typical time to maximum for Page or Byte program = 2*(N+1), N=1h
= 4x multiplier
128 Mb
Binary Fields: 1-10-01000-0-0000-1-1100-1-00110-1001-0001
Nibble Format: 1100_1000_0000_0111_0010_0110_1001_0001
Hex Format: C8_07_26_91
256 Mb
Binary Fields: 1-10-10001-0-0000-1-1100-1-00110-1001-0001
Nibble Format: 1101_0001_0000_0111_0010_0110_1001_0001
Hex Format: D1_07_26_91
512 Mb
Binary Fields: 1-11-00010-0-0000-1-1100-1-00110-1001-0001
Nibble Format: 1110_0010_0000_0111_0010_0110_1001_0001
Hex Format: E2_07_26_91
Bit 31 = Suspend and Resume supported = 0b
Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8us,
11b: 64us) = 8us= 10b
Bits 28:24 = Suspend in-progress erase max latency count = 00100b, max erase suspend
latency = count +1 * units = 5*8uS = 40uS
Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = count +1 * 64us = 2 *
64us = 128us
Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b: 1us, 10b: 8us,
11b: 64us) = 8us= 10b
Bits 17:13 = Suspend in-progress program max latency count = 00100b, max erase suspend
latency = count +1 * units = 5*8uS = 40uS
Bits 12:9 = Program resume to suspend interval count = 0001b, interval = count +1 * 64us = 2
* 64us = 128us
Bit 8 = RFU = 1b
Bits 7:4 = Prohibited operations during erase suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx1xb: May not initiate a page program in the erase suspended sector size
+ x1xxb: May not initiate a read in the erase suspended sector size
+ 1xxxb: The erase and program restrictions in bits 5:4 are sufficient
= 1110b
Bits 3:0 = Prohibited Operations During Program Suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx0xb: May not initiate a new page program anywhere (program nesting not permitted)
+ x1xxb: May not initiate a read in the program suspended page size
+ 1xxxb: The erase and program restrictions in bits 1:0 are sufficient
= 1100b
Binary Fields: 0-10-00100-0001-10-00100-0001-1-1110-1100
Nibble Format: 0100_0100_0001_1000_1000_0011_1110_1100
Hex Format: 44_18_83_EC
32h
30h
33h
31h
34h
32h
35h
33h
JEDEC
Basic Flash
Parameter
Dword-13
8Ah
85h
7Ah
Bits 31:24 = Erase Suspend Instruction = 75h
Bits 23:16 = Erase Resume Instruction = 7Ah
Bits 15:8 = Program Suspend Instruction = 85h
Bits 7:0 = Program Resume Instruction = 8Ah
75h
Document Number: 002-00488 Rev. *M
Page 127 of 139
S25FS512S
Table 69. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4-Byte Address Instructions Parameter (Continued)
CFI
Parameter
Relative
Byte
Address
Offset
36h
SFDP
Parameter
Relative
Byte
Address
Offset
SFDP Dword
Name
34h
Data
F7h
37h
35h
BDh
38h
36h
D5h
39h
37h
JEDEC
Basic Flash
Parameter
Dword-14
5Ch
Description
Bit 31 = Deep Power Down Supported = supported = 0
Bits 30:23 = Enter Deep Power Down Instruction = B9h
Bits 22:15 = Exit Deep Power Down Instruction = ABh
Bits 14:13 = Exit Deep Power Down to next operation delay units = (00b: 128ns, 01b: 1us,
10b: 8us, 11b: 64us) = 1us = 01b
Bits 12:8 = Exit Deep Power Down to next operation delay count = 11101b, Exit Deep Power
Down to next operation delay = (count+1)*units = 29+1 *1us = 30us
Bits 7:4 = RFU = Fh
Bit 3:2 = Status Register Polling Device Busy
= 01b: Legacy status polling supported = Use legacy polling by reading the Status Register
with 05h instruction and checking WIP bit[0] (0=ready; 1=busy).
= 01b
Bits 1:0 = RFU = 11b
Binary Fields: 0-10111001-10101011-01-11101-1111-01-11
Nibble Format: 0101_1100_1101_0101_1011_1101_1111_0111
Hex Format: 5C_D5_BD_F7
3Ah
38h
8Ch
3Bh
39h
F6h
3Ch
3Ah
5Dh
3Dh
3Bh
JEDEC
Basic Flash
Parameter
Dword-15
FFh
Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP Disable = not supported = 0b
Bits 22:20 = Quad Enable Requirements
= 101b: QE is bit 1 of the Status Register 2. Status register 1 is read using Read Status
instruction 05h. Status register 2 is read using instruction 35h. QE is set via Write Status
instruction 01h with two data bytes where bit 1 of the second byte is one. It is cleared via Write
Status with two data bytes where bit 1 of the second byte is zero.
Bits 19:16 0-4-4 Mode Entry Method
= xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode
+ x1xxb: Mode Bit[7:0]=Axh
+ 1xxxb: RFU
= 1101b
Bits 15:10 0-4-4 Mode Exit Method
= xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current read
operation
+ xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate the mode
prior to the next read operation.
+ x1_xxxxb: Mode Bit[7:0] != Axh
+ 1x_x1xx: RFU
= 11_1101
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences
= x_1xxxb: device uses a read-modify-write sequence of operations: read configuration using
instruction 65h followed by address 800003h, set bit 6, write configuration using instruction
71h followed by address 800003h. This configuration is volatile.
= 01000b
Bits 3:0 = 4-4-4 mode disable sequences
= x1xxb: device uses a read-modify-write sequence of operations: read configuration using
instruction 65h followed by address 800003h, clear bit 6, write configuration using instruction
71h followed by address 800003h.. This configuration is volatile.
+ 1xxxb: issue the Soft Reset 66/99 sequence
= 1100b
Binary Fields: 11111111-0-101-1101-111101-1-01000-1100
Nibble Format: 1111_1111_0101_1101_1111_0110_1000-1100
Hex Format: FF_5D_F6_8C
Document Number: 002-00488 Rev. *M
Page 128 of 139
S25FS512S
Table 69. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 1, Basic Flash
Parameter and 4-Byte Address Instructions Parameter (Continued)
CFI
Parameter
Relative
Byte
Address
Offset
3Eh
SFDP
Parameter
Relative
Byte
Address
Offset
SFDP Dword
Name
Data
F0h
3Ch
3Fh
3Dh
30h
40h
3Eh
F8h
41h
3Fh
JEDEC
Basic Flash
Parameter
Dword-16
A1h
Description
Bits 31:24 = Enter 4-Byte Addressing
= xxxx_xxx1b: issue instruction B7h (preceding write enable not required)
+ xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data sheet
for the instruction set definition.
+ 1xxx_xxxxb: Reserved
= 10100001b
Bits 23:14 = Exit 4-Byte Addressing
= xx_xx1x_xxxxb: Hardware reset
+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)
+ xx_1xxx_xxxxb: Power cycle
+ x1_xxxx_xxxxb: Reserved
+ 1x_xxxx_xxxxb: Reserved
= 11_1110_0000b
Bits 13:8 = Soft Reset and Rescue Sequence Support
= x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The reset
enable, reset sequence may be issued on 1, 2, or 4 wires depending on the
device operating mode.
+ 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the device
may be operating in this mode.
= 110000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Nonvolatile Register and Write Enable Instruction for Status Register 1
= + xx1_xxxxb: Status Register 1 contains a mix of volatile and nonvolatile bits. The 06h
instruction is used to enable writing of the register.
+ x1x_xxxxb: Reserved
+ 1xx_xxxxb: Reserved
= 1110000b
Binary Fields: 10100001-1111100000-110000-1-1110000
Nibble Format: 1010_0001_1111_1000_0011_0000_1111_0000
Hex Format: A1_F8_30_F0
42h
40h
nonvolatile
6Bh
43h
41h
8Eh
44h
42h
FFh
45h
43h
46h
44h
47h
45h
48h
46h
49h
47h
JEDEC 4
Byte
Address
Instructions
Parameter
Dword-1
JEDEC 4
Byte
Address
Instructions
Parameter
Dword-2
FFh
Supported = 1, Not Supported = 0
Bits 31:20 = RFU = FFFh
Bit 19 = Support for nonvolatile individual sector lock write command, Instruction=E3h = 1
Bit 18 = Support for nonvolatile individual sector lock read command, Instruction=E2h = 1
Bit 17 = Support for volatile individual sector lock Write command, Instruction=E1h = 1
Bit 16 = Support for volatile individual sector lock Read command, Instruction=E0h = 1
Bit 15 = Support for (1-4-4) DTR_Read Command, Instruction=EEh = 1
Bit 14 = Support for (1-2-2) DTR_Read Command, Instruction=BEh = 0
Bit 13 = Support for (1-1-1) DTR_Read Command, Instruction=0Eh = 0
Bit 12 = Support for Erase Command – Type 4 = 0
Bit 11 = Support for Erase Command – Type 3 = 1
Bit 10 = Support for Erase Command – Type 2 = 1
Bit 9 = Support for Erase Command – Type 1 = 1
Bit 8 = Support for (1-4-4) Page Program Command, Instruction=3Eh =0
Bit 7 = Support for (1-1-4) Page Program Command, Instruction=34h = 0
Bit 6 = Support for (1-1-1) Page Program Command, Instruction=12h = 1
Bit 5 = Support for (1-4-4) FAST_READ Command, Instruction=ECh = 1
Bit 4 = Support for (1-1-4) FAST_READ Command, Instruction=6Ch = 0
Bit 3 = Support for (1-2-2) FAST_READ Command, Instruction=BCh = 1
Bit 2 = Support for (1-1-2) FAST_READ Command, Instruction=3Ch = 0
Bit 1 = Support for (1-1-1) FAST_READ Command, Instruction=0Ch = 1
Bit 0 = Support for (1-1-1) READ Command, Instruction=13h = 1
21h
DCh
DCh
Bits 31:24 = FFh = Instruction for Erase Type 4: RFU
Bits 23:16 = DCh = Instruction for Erase Type 3
Bits 15:8 = DCh = Instruction for Erase Type 2
Bits 7:0 = 21h = Instruction for Erase Type 1
FFh
Document Number: 002-00488 Rev. *M
Page 129 of 139
S25FS512S
Sector Map Parameter Table Notes
The Table 70 on page 130 table provides a means to identify how the device address map is configured and provides a sector map
for each supported configuration. This is done by defining a sequence of commands to read out the relevant configuration register
bits that affect the selection of an address map. When more than one configuration bit must be read, all the bits are concatenated
into an index value that is used to select the current address map.
To identify the sector map configuration in FS512S the following configuration bits are read in the following MSb to LSb order to form
the configuration map index value:
CR3NV[3] — 0 = Hybrid Architecture, 1 = Uniform Architecture
CR1NV[2] — 0 = 4 KB parameter sectors at bottom, 1 = 4 KB sectors at top
The value of some configuration bits may make other configuration bit values not relevant (don’t care), hence not all possible
combinations of the index value define valid address maps. Only selected configuration bit combinations are supported by the SFDP
Sector Map Parameter Table. Other combinations must not be used in configuring the sector address map when using this SFDP
parameter table to determine the sector map. The following index value combinations are supported.
Table 70. Sector Map Parameter
Device
FS512S
CR3NV[3]
CR1NV[2]
Index Value
0
0
01h
4 KB sectors at bottom with remainder 256 KB sectors
0
1
03h
4 KB sectors at top with remainder 256 KB sectors
1
0
05h
Uniform 256 KB sectors
Document Number: 002-00488 Rev. *M
Description
Page 130 of 139
S25FS512S
Table 71. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 512 Mb
CFI
SFDP
Paramete Parameter
r Relative Relative
Byte
Byte
Address Address
Offset
Offset
SFDP Dword Name
Data
4Ah
48h
FCh
4Bh
49h
65h
4Ch
4Ah
4Dh
4Bh
4Eh
4Ch
4Fh
4Dh
50h
4Eh
51h
4Fh
JEDEC Sector Map
Parameter Dword-1
Config. Detect-1
FFh
08h
00h
00h
50h
FCh
51h
65h
54h
52h
55h
53h
56h
54h
55h
56h
JEDEC Sector Map
Parameter Dword-3
Config. Detect-2
FFh
04h
00h
00h
57h
00h
5Ah
58h
FDh
5Bh
59h
65h
5Ch
5Ah
5Dh
5Bh
5Eh
5Ch
5Fh
5Dh
60h
5Eh
61h
5Fh
62h
60h
61h
64h
62h
65h
63h
Bits 31:24 = Read data mask = 0000_0100b: Select bit 2 of the data byte for
TBPARM_O value
0= 4-KB parameter sectors at bottom
1= 4-KB parameter sectors at top
Bits 23:22 = Configuration detection command address length = 11b: Variable length
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 1111b: variable latency
Bits 15:8 = Configuration detection instruction = 65h: Read any register
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
Bit 0 = not the end descriptor = 0
02h
JEDEC Sector Map
Parameter Dword-4
Config. Detect-2
59h
63h
Bits 31:0 = Sector map configuration detection command address = 00_00_00_04h:
address of CR3NV
00h
52h
58h
Bits 31:24 = Read data mask = 0000_1000b: Select bit 3 of the data byte for 20h_NV
value
0= Hybrid map with 4-KB parameter sectors
1= Uniform map
Bits 23:22 = Configuration detection command address length = 11b: Variable length
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 1111b: variable latency
Bits 15:8 = Configuration detection instruction = 65h: Read any register
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
Bit 0 = not the end descriptor = 0
04h
JEDEC Sector Map
Parameter Dword-2
Config. Detect-1
53h
57h
Description
JEDEC Sector Map
Parameter Dword-5
Config. Detect-3
FFh
02h
Bits 31:0 = Sector map configuration detection command address = 00_00_00_02h:
address of CR1NV
Bits 31:24 = Read data mask = 0000_0010b: Select bit 1 of the data byte for D8h_NV
value
0= 64-KB uniform sectors
1= 256-KB uniform sectors
Bits 23:22 = Configuration detection command address length = 11b: Variable length
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 1111b: variable latency
Bits 15:8 = Configuration detection instruction = 65h: Read any register
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
Bit 0 = The end descriptor = 1
04h
JEDEC Sector Map
Parameter Dword-6
Config. Detect-3
00h
00h
Bits 31:0 = Sector map configuration detection command address = 00_00_00_04h:
address of CR3NV
00h
FEh
JEDEC Sector Map
Parameter Dword-7
Config-1 Header
Document Number: 002-00488 Rev. *M
01h
02h
FFh
Bits 31:24 = RFU = FFh
Bits 23:16 = Region count (Dwords -1) = 02h: Three regions
Bits 15:8 = Configuration ID = 01h: 4-KB sectors at bottom with remainder 256-KB
sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = not the end descriptor = 0
Page 131 of 139
S25FS512S
Table 71. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 512 Mb (Continued)
CFI
SFDP
Paramete Parameter
r Relative Relative
Byte
Byte
Address Address
Offset
Offset
SFDP Dword Name
Data
66h
64h
F1h
67h
65h
7Fh
68h
66h
00h
JEDEC Sector Map
Parameter Dword-8
Config-1 Region-0
69h
67h
00h
6Ah
68h
F4h
6Bh
69h
7Fh
6Ch
6Ah
03h
JEDEC Sector Map
Parameter Dword-9
Config-1 Region-1
6Dh
6Bh
00h
6Eh
6Ch
F4h
6Fh
6Dh
FFh
70h
6Eh
FBh
JEDEC Sector Map
Parameter Dword-10
Config-1 Region-2
71h
6Fh
72h
70h
73h
71h
74h
72h
75h
73h
03h
(512
Mb
FEh
JEDEC Sector Map
Parameter Dword-11
Config-3 Header
03h
02h
FFh
76h
74h
F4h
77h
75h
FFh
78h
76h
FBh
JEDEC Sector Map
Parameter Dword-12
Config-3 Region-0
79h
77h
Document Number: 002-00488 Rev. *M
03h
(512
Mb
Description
Bits 31:8 = Region size = 00007Fh:
Region size as count-1 of 256 Byte units = 8 x 4 KB sectors = 32 KB
Count = 32 KB/256 = 128, value = count -1 = 128 -1 = 127 = 7Fh
Bits 7:4 = RFU = Fh
Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b
--- Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b
--- Erase Type 3 is 256-KB erase and is supported in the 4-KB sector region
Bit 1 = Erase Type 2 support = 0b
--- Erase Type 2 is 64-KB erase and is not supported in the 4-KB sector region
Bit 0 = Erase Type 1 support = 1b
--- Erase Type 1 is 4-KB erase and is supported in the 4-KB sector region
Bits 31:8 = Region size = 00037Fh:
Region size as count-1 of 256 Byte units = 1 x 224 KB sectors = 224 KB
Count = 224 KB/256 = 896, value = count -1 = 896 -1 = 895 = 37Fh
Bits 7:4 = RFU = Fh
Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b
--- Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b
--- Erase Type 3 is 256-KB erase and is supported in the 32-KB sector region
Bit 1 = Erase Type 2 support = 0b
--- Erase Type 2 is 64-KB erase and is not supported in the 32-KB sector region
Bit 0 = Erase Type 1 support = 0b
--- Erase Type 1 is 4-KB erase and is not supported in the 32-KB sector region
Bits 31:8 = 512 Mb device Region size = 03FBFFh:
Region size as count-1 of 256 Byte units = 255 x 256 KB sectors = 65280 KB
Count = 65280 KB/256 = 261120, value = count -1 = 261120 -1 = 261119 = 3FBFFh
Bits 7:4 = RFU = Fh
Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b
--- Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b
--- Erase Type 3 is 256-KB erase and is supported in the 64-KB sector region
Bit 1 = Erase Type 2 support = 0b
--- Erase Type 2 is 64-KB erase and is not supported in the 64-KB sector region
Bit 0 = Erase Type 1 support = 0b
--- Erase Type 1 is 4-KB erase and is not supported in the 64-KB sector region
Bits 31:24 = RFU = FFh
Bits 23:16 = Region count (Dwords -1) = 02h: Three regions
Bits 15:8 = Configuration ID = 03h: 4 KB sectors at top with remainder 256 KB sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = not the end descriptor = 0
Bits 31:8 = 512 Mb device Region size = 03FBFFh:
Region size as count-1 of 256 Byte units = 255 x 256 KB sectors = 65280 KB
Count = 65280 KB/256 = 261120, value = count -1 = 261120 -1 = 261119 = 3FBFFh
Bits 7:4 = RFU = Fh
Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b
--- Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b
--- Erase Type 3 is 256-KB erase and is supported in the 64-KB sector region
Bit 1 = Erase Type 2 support = 0b
--- Erase Type 2 is 64-KB erase and is not supported in the 64-KB sector region
Bit 0 = Erase Type 1 support = 0b
--- Erase Type 1 is 4-KB erase and is not supported in the 64-KB sector region
Page 132 of 139
S25FS512S
Table 71. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B, Section 2, Sector Map
Parameter Table, 512 Mb (Continued)
CFI
SFDP
Paramete Parameter
r Relative Relative
Byte
Byte
Address Address
Offset
Offset
SFDP Dword Name
Data
7Ah
78h
F4h
7Bh
79h
7Fh
7Ch
7Ah
03h
JEDEC Sector Map
Parameter Dword-13
Config-3 Region-1
7Dh
7Bh
00h
7Eh
7C
F1h
7Fh
7D
7Fh
80h
7E
00h
JEDEC Sector Map
Parameter Dword-14
Config-3 Region-2
81h
7F
82h
80h
00h
FFh
JEDEC Sector Map
Parameter Dword-15
Config-4 Header
83h
81h
84h
82h
05h
85h
83h
FFh
86h
84h
F4h
87h
85h
FFh
88h
86h
00h
FFh
JEDEC Sector Map
Parameter Dword-16
Config-4 Region-0
89h
87h
Document Number: 002-00488 Rev. *M
03h
Description
Bits 31:8 = Region size = 00037Fh:
Region size as count-1 of 256 Byte units = 1 x 224 KB sectors = 224 KB
Count = 224 KB/256 = 896, value = count -1 = 896 -1 = 895 = 37Fh
Bits 7:4 = RFU = Fh
Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b
--- Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b
--- Erase Type 3 is 256-KB erase and is supported in the 224-KB sector region
Bit 1 = Erase Type 2 support = 0b
--- Erase Type 2 is 64-KB erase and is not supported in the 224-KB sector region
Bit 0 = Erase Type 1 support = 0b
--- Erase Type 1 is 4-KB erase and is not supported in the 224-KB sector region
Bits 31:8 = Region size = 00007Fh:
Region size as count-1 of 256 Byte units = 8 x 4 KB sectors = 32 KB
Count = 32 KB/256 = 128, value = count -1 = 128 -1 = 127 = 7Fh
Bits 7:4 = RFU = Fh
Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b
--- Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 0b
--- Erase Type 3 is 256-KB erase and is not supported in the 4-KB sector region
Bit 1 = Erase Type 2 support = 0b
--- Erase Type 2 is 64-KB erase and is not supported in the 4-KB sector region
Bit 0 = Erase Type 1 support = 1b
--- Erase Type 1 is 4-KB erase and is supported in the 4-KB sector region
Bits 31:24 = RFU = FFh
Bits 23:16 = Region count (Dwords -1) = 00h: One region
Bits 15:8 = Configuration ID = 05h: Uniform 256-KB sectors
Bits 7:2 = RFU = 111111b
Bit 1 = Map Descriptor = 1
Bit 0 = The end descriptor = 1
Bits 31:8 = 512 Mb device Region size = 03FFFFh:
Region size as count-1 of 256 Byte units = 256 x 256 KB sectors = 65536 KB
Count = 65536 KB/256 = 262144, value = count -1 = 262144 -1 = 262143 = 3FFFFh
Bits 7:4 = RFU = Fh
Erase Type not supported = 0/ supported = 1
Bit 3 = Erase Type 4 support = 0b
--- Erase Type 4 is not defined
Bit 2 = Erase Type 3 support = 1b
--- Erase Type 3 is 256-KB erase and is supported in the 256-KB sector region
Bit 1 = Erase Type 2 support = 0b
--- Erase Type 2 is 64-KB erase and is not supported in the 256-KB sector region
Bit 0 = Erase Type 1 support = 0b
--- Erase Type 1 is 4-KB erase and is not supported in the 256-KB sector region
Page 133 of 139
S25FS512S
11.5
Initial Delivery State
The device is shipped from Cypress with nonvolatile bits set as follows:
The entire memory array is erased: i.e., all bits are set to 1 (each byte contains FFh).
The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh.
The SFDP address space contains the values as defined in the description of the SFDP address space.
The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.
The Status Register 1 nonvolatile contains 00h (all SR1NV bits are cleared to 0’s).
The Configuration Register 1 nonvolatile contains 00h.
The Configuration Register 2 nonvolatile contains 08h.
The Configuration Register 3 nonvolatile contains 00h.
The Configuration Register 4 nonvolatile contains 10h.
The Password Register contains FFFFFFFF-FFFFFFFFh.
All PPB bits are 1.
The ASP Register bits are FFFFh.
Document Number: 002-00488 Rev. *M
Page 134 of 139
S25FS512S
Ordering Information
12. Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S25FS
512
S
AG
M
F
I
01
1
Packing Type
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
01 = SOIC16 / WSON 6 x 8 footprint, 256-KB Physical Sector
21 = 5 x 5 ball BGA footprint, 256-KB Physical Sector
Temperature Range / Grade
I = Industrial (-40°C to +85°C)
V = Industrial Plus (-40°C to +105°C)
A = Automotive, AEC-Q100 Grade 3 (-40°C to +85°C)
B = Automotive, AEC-Q100 Grade 2 (-40°C to +105°C)
M = Automotive, AEC-Q100 Grade 1 (-40°C to +125°C)
Package Materials[100]
F = Halogen-free, Lead (Pb)-free
H = Halogen-free, Lead (Pb)-free
Package Type
M = 16-pin SOIC
N = 8-contact WSON 6 x 8 mm
B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
AG = 133 MHz
DS = 80 MHz DDR
Device Technology
S = 65 nm MirrorBit Process Technology
Density
512 = 512 Mb
Device Family
S25FS
Cypress Memory 1.8 V-only, Serial Peripheral Interface (SPI) Flash Memory
Note
100.Halogen free definition is in accordance with IE 61249-2-21 specification.
Document Number: 002-00488 Rev. *M
Page 135 of 139
S25FS512S
Valid Combinations — Standard
Valid Combinations list configurations planned to be supported in volume for this device. Contact the local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Valid Combinations — Standard
Base Ordering Part
Number
Speed
Option
AG
S25FS512S
DS
Package and
Temperature
Model Number
Packing Type
MFI, MFV
01
0, 1, 3
FS512S + A +(Temp) + F + (Model Number)
NFI, NFV
01
0, 1, 3
FS512S + A +(Temp) + F + (Model Number)
Package Marking
BHI, BHV
21
0, 3
FS512S + A +(Temp) + H + (Model Number)
MFI, MFV
01
0, 1, 3
FS512S + D +(Temp) + F + (Model Number)
NFI, NFV
01
0, 1, 3
FS512S + D +(Temp) + F + (Model Number)
BHI, BHV
21
0, 3
FS512S + D +(Temp) + H + (Model Number)
Valid Combinations — Automotive Grade / AEC-Q100
The table below lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The
table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific
combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with
ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Valid Combinations — Automotive Grade / AEC-Q100
Base Ordering Part
Number
Speed
Option
AG
S25FS512S
DS
Package and
Temperature
Model Number
Packing Type
MFA, MFB, MFM
01
0, 1, 3
Package Marking
FS512S + A +(Temp) + F + (Model Number)
NFA, NFB, NFM
01
0, 1, 3
FS512S + A +(Temp) + F + (Model Number)
BHA, BHB, BHM
21
0, 3
FS512S + A +(Temp) + H + (Model Number)
MFA, MFB, MFM
01
0, 1, 3
FS512S + D +(Temp) + F + (Model Number)
NFA, NFB, NFM
01
0, 1, 3
FS512S + D +(Temp) + F + (Model Number)
BHA, BHB, BHM
21
0, 3
FS512S + D +(Temp) + H + (Model Number)
Document Number: 002-00488 Rev. *M
Page 136 of 139
S25FS512S
13. Revision History
Document Title: S25FS512S, 512 Mb, 1.8 V Serial Peripheral Interface with Multi-I/O Flash
Document Number: 002-00488
Rev.
ECN No.
Submission
Date
**
10/14/2014
Initial release
Description of Change
*A
12/17/2014
General
Promoted data sheet from ‘Advance Information’ to ‘Preliminary’
8-Connector Package
8-Connector Package (WSON 6x8), Top View figure: added second note
*B
5043169
12/09/2015
Updated to Cypress template
*C
5057701
12/23/2015
Changed document status from Preliminary to Final.
Replaced Automotive and Automotive - In Cabin with “Industrial Plus” in all instances across the
document.
Updated Section 12. Ordering Part Number on page 135:
Added “Industrial Plus with AECQ-100 and GT Grade” Temperature Range related information.
Updated Section 5. Timing Specifications on page 28:
Updated Section 5.5 DDR AC Characteristics. on page 33:
Updated Section 5.5.2 DDR Output Timing on page 34:
Replaced “4.125 ns” with “4.325 ns” in Note 5c below Figure 35.
Updated “12., Software Interface Reference” on page 126:
*D
5126709
02/05/2016
Updated Section 11.4 Device ID and Common Flash Interface (ID-CFI) Address Map
on page 119:
Updated Section 11.4.1 Field Definitions on page 119:
Updated Table 63: Replaced “02h” with “01h” in “Data” column.
Updated Table 64: Replaced “09h” with “08h” in “Data” column.
Updated Table 65: Replaced “05h” with “04h” in “Data” column.
Updated Table 66: Replaced “07h” with “06h” in “Data” column.
Updated Table 68: Replaced “0Ah” with “09h” in “Data” column.
Added Automotive Grade to Features on page 1.
Added Extended Temperature Range to Features on page 1.
Logic Block Diagram Typical Program and Erase Rates: Corrected
256-KB Sector Erase (Uniform Logical Sector Option) value.
Added Section 4.2 Thermal Resistance on page 22.
Added Automotive Grade to Section 4.4.2 Temperature Ranges on page 22.
Added Section 7.6.7 ECC Status Register (ECCSR) on page 58.
Added ECC to Section 7.5 OTP Address Space on page 44.
Added ECC to Section 8.4.7 Password Protection Mode on page 68.
Added ECC to Section 9.1.1 Extended Addressing on page 71.
Added ECC to Section 9.1 Command Set Summary on page 71.
*E
5459641
10/03/2016
Added Section 9.3.8 ECC Status Register Read (ECCRD 19h or 4EECRD 18h) on page 84.
Updated Section 9.3.13 Read Any Register (RDAR 65h) on page 86.
Updated Section 9.4.3 Dual I/O Read (DIOR BBh or 4DIOR BCh) on page 92.
Updated figures in Section 9.4.4 Quad I/O Read (QIOR EBh or 4QIOR ECh) on page 93.
Updated figures in Section 9.4.5 DDR Quad I/O Read (EDh, EEh) on page 95.
Added Section 9.5.1.1 Automatic ECC on page 97.
Added Section 11. Data Integrity on page 116.
Added ECC to Table 12.1, S25FS512S Command Set (sorted by instruction) on page 126.
Added Table 67 on page 124.
Removed Software Interface Reference section.
Section Ordering Information on page 135: added Automotive Grade.
Document Number: 002-00488 Rev. *M
Page 137 of 139
S25FS512S
Document Title: S25FS512S, 512 Mb, 1.8 V Serial Peripheral Interface with Multi-I/O Flash
Document Number: 002-00488
Rev.
ECN No.
Submission
Date
*F
5649411
03/03/2017
Description of Change
Removed Extended Temperature Range Options (-40°C to +125°C) in datasheet.
Updated Sales and Copyright information.
Updated Package Drawings on Section 6. Physical Interface on page 36.
Updated Cypress logo and Sales page.
*G
5688179
12/22/2017
Updated Section 12. Ordering Part Number on page 135 definition of letters in OPN indicating
package material.
Changed VDD to VCC
Updated Section 5.5.3 DDR Data Valid Timing Using DLP on page 34, Example
Added Section Logic Block Diagram on page 2
Updated Sales Page.
*H
6090180
03/06/2018
Corrected DDR AC tV timing to 6.0 ns in Section 15 DDR 80 Mhz AC Characteristics Operation
on page 33
*I
6125350
04/02/2018
Added Section 4.6.2 Deep Power Down Mode (DPD) on page 27
*J
6227233
0703/2018
Updated Section 5.5.3 DDR Data Valid Timing Using DLP on page 34 and Section 12. Ordering
Part Number on page 135.
Added the definition for LSb and MSb in Glossary on page 7.
Replaced MSB, LSB to MSb and LSb throughout the document.
Updated Section 4.6.2 Deep Power Down Mode (DPD) on page 27, Section 7.6.5.1
Configuration Register 3 Nonvolatile (CR3NV) on page 55, Section 7.6.5.2 Configuration
Register 3 Volatile (CR3V) on page 56, and Section 11.4.1.1 JEDEC SFDP Rev B Parameter
Tables on page 124.
*K
6401339
12/14/2018
Updated DDR QPI note in Table 27.
Updated Table 29 and Table 30: Bit 1 set to RFU with default 0.
Updated Table 70: Removed CR3NV[1] column.
Updated Figure 102.
*L
6585789
05/31/2019
*M
6735857
11/22/2019
Document Number: 002-00488 Rev. *M
Updated Table 26 and Table 28.
Updated Copyright information.
Updated Table 25.
Updated Section 9.3.4 Write Registers (WRR 01h) on page 80.
Page 138 of 139
S25FS512S
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-00488 Rev. *M
Revised November 22, 2019
Page 139 of 139
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