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S27KL0642/S27KS0642
3.0 V/1.8 V, 64 Mb (8 MB),
HyperRAM Self-Refresh DRAM
S27KL0642/S27KS0642, 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM
Features
Wrapped burst lengths:
• 16 bytes (eight clocks)
• 32 bytes (16 clocks)
• 64 bytes (32 clocks)
• 128 bytes (64 clocks)
❐ Hybrid option - one wrapped burst followed by linear burst
❐
Interface
■
HyperBus Interface
■
1.8 V / 3.0 V interface support
❐ Single-ended clock (CK) - 11 bus signals
❐ Optional differential clock (CK, CK#) - 12 bus signals
■
Configurable output drive strength
■
Chip Select (CS#)
■
■
8-bit data bus (DQ[7:0])
■
Hardware reset (RESET#)
Power Modes
❐ Hybrid Sleep Mode
❐ Deep Power Down
Bidirectional Read-Write Data Strobe (RWDS)
❐ Output at the start of all transactions to indicate refresh
latency
❐ Output during read transactions as Read Data Strobe
❐ Input during write transactions as Write Data Mask
■
■
Array Refresh
❐ Partial Memory Array(1/8, 1/4, 1/2, and so on)
❐ Full
■
Package
❐ 24-ball FBGA
■
Operating Temperature Range
❐ Industrial (I): –40 °C to +85 °C
❐ Industrial Plus (V): –40 °C to +105 °C
❐ Automotive, AEC-Q100 Grade 3: –40 °C to +85 °C
❐ Automotive, AEC-Q100 Grade 2: –40 °C to +105 °C
■
Optional DDR Center-Aligned Read Strobe (DCARS)
❐ During read transactions RWDS is offset by a second clock,
phase shifted from CK
❐ The Phase Shifted Clock is used to move the RWDS
transition edge within the read data eye
Technology
Performance, Power, and Packages
■
200 MHz maximum clock rate
■
DDR - transfers data on both edges of the clock
■
Data throughput up to 400 MBps (3,200 Mbps)
■
Configurable Burst Characteristics
❐ Linear burst
■
38-nm DRAM
Performance Summary
Read Transaction Timings
Unit
Maximum Clock Rate at 1.8 V VCC/VCCQ
200 MHz
Maximum Clock Rate at 3.0 V VCC/VCCQ
200 MHz
Maximum Access Time (tACC)
35 ns
Maximum Current Consumption
Unit
Burst Read or Write (linear burst at 200 MHz, 1.8 V)
25 mA
Burst Read or Write (linear burst at 200 MHz, 3.0 V)
30 mA
Standby (CS# = VCC = 3.6 V, 105 °C)
360 µA
Deep Power Down (CS# = VCC = 3.6 V, 105 °C)
15 µA
Standby (CS# = VCC = 2.0 V, 105 °C)
330 µA
Deep Power Down (CS# = VCC = 2.0 V, 105 °C)
12 µA
Cypress Semiconductor Corporation
Document Number: 002-24692 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 05, 2020
S27KL0642/S27KS0642
X Decoders
Logic Block Diagram
CS#
CK/CK#
Memory
RWDS
I/O
DQ[7:0]
Control
Logic
Y Decoders
Data Latch
RESET#
Data Path
Document Number: 002-24692 Rev. *G
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Contents
General Description ......................................................... 4
HyperBus Interface ...................................................... 4
Product Overview ............................................................. 6
HyperBus Interface ...................................................... 6
Signal Description ............................................................ 7
Input/Output Summary ................................................ 7
HyperBus Transaction Details ........................................ 8
Command/Address Bit Assignments ........................... 8
Read Transactions .................................................... 12
Write Transactions (Memory Array Write) ................. 13
Write Transactions without Initial Latency
(Register Write) ......................................................... 15
Memory Space ................................................................ 16
HyperBus Interface .................................................... 16
Register Space ................................................................ 16
HyperBus Interface .................................................... 16
Device Identification Registers .................................. 17
Register Space Access ............................................. 18
Interface States ............................................................... 24
Power Conservation Modes .......................................... 25
Interface Standby ...................................................... 25
Active Clock Stop ...................................................... 25
Hybrid Sleep .............................................................. 25
Deep Power Down .................................................... 26
Electrical Specifications ................................................ 27
Absolute Maximum Ratings ....................................... 27
Latch-up Characteristics ............................................ 28
Operating Ranges ..................................................... 28
DC Characteristics .................................................... 29
Power-Up Initialization ............................................... 33
Power Down .............................................................. 34
Hardware Reset ........................................................ 35
Document Number: 002-24692 Rev. *G
Timing Specifications .................................................... 36
Key to Switching Waveforms ..................................... 36
AC Test Conditions ................................................... 36
CLK Characteristics ................................................... 37
AC Characteristics ..................................................... 39
Timing Reference Levels ........................................... 42
Physical Interface ........................................................... 43
FBGA 24-Ball 5 x 5 Array Footprint ........................... 43
Package Diagrams .................................................... 44
DDR Center-Aligned Read Strobe
(DCARS) Functionality ................................................... 45
HyperRAM Products with
DCARS Signal Descriptions ...................................... 45
HyperRAM Products with
DCARS — FBGA 24-ball, 5 x 5 Array Footprint ........ 46
HyperRAM Memory with DCARS Timing .................. 46
Ordering Information ...................................................... 48
Ordering Part Number ............................................... 48
Valid Combinations ................................................... 49
Valid Combinations — Automotive Grade /
AEC-Q100 ................................................................. 49
Revision History ............................................................. 50
Sales, Solutions, and Legal Information ...................... 51
Worldwide Sales and Design Support ....................... 51
Products .................................................................... 51
PSoC® Solutions ....................................................... 51
Cypress Developer Community ................................. 51
Technical Support ..................................................... 51
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S27KL0642/S27KS0642
General Description
The Cypress 64 Mb HyperRAM device is a high-speed CMOS, self-refresh DRAM, with HyperBus interface. The DRAM array uses
dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM
array when the memory is not being actively read or written by the HyperBus interface master (host). Since the host is not required
to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data
without refresh. Hence, the memory is more accurately described as Pseudo Static RAM (PSRAM).
Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write
burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of
transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh
operation is needed.
HyperBus Interface
HyperBus is a low signal count, DDR interface, that achieves high-speed read and write throughput. The DDR protocol transfers two
data bytes per clock cycle on the DQ[7:0] input/output signals. A read or write transaction on HyperBus consists of a series of 16-bit
wide, one clock cycle data transfers at the internal HyperRAM array with two corresponding 8-bit wide, one-half-clock-cycle data
transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Device are available as 1.8 V VCC/(VCCQ or 3.0 V
VCC/VCCQ (nominal) for array (VCC) and I/O buffer (VCCQ) supplies, through different Ordering Part Numbers (OPN).
Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock (CK#, CK) is used for
information capture by a HyperBus slave device when receiving command, address, or data on the DQ signals. Command or
Address values are center-aligned with clock transitions.
Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock transitions to
transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is deasserted.
Figure 1. Read Transaction, Single Initial Latency Count
CS#
tRWR =Read Write Recovery
t ACC = Access
CK#,CK
Latency Count
RWDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
DQ[7:0]
47:40
39:32
31:24
23:16
15:8
7:0
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Memory drives DQ[7:0]
and RWDS
The RWDS is a bidirectional signal that indicates:
■
when data will start to transfer from a HyperRAM device to the master device in read transactions (initial read latency)
■
when data is being transferred from a HyperRAM device to the master device during read transactions (as a source synchronous
read data strobe)
■
when data may start to transfer from the master device to a HyperRAM device in write transactions (initial write latency)
■
data masking during write data transfers
During the CA transfer portion of a read or write transaction, RWDS acts as an output from a HyperRAM device to indicate whether
additional initial access latency is needed in the transaction.
During read data transfers, RWDS is a read data strobe with data values edge-aligned with the transitions of RWDS.
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Figure 2. Read Transaction, Additional Latency Count
CS#
tRWR=Read Write Recovery
Additional Latency
tACC = Access
Latency Count 1
Latency Count 2
CK#, CK
RWDS
DQ[7:0]
High = 2x Latency Count
Low = 1x Latency Count
47:40 39:32 31:24 23:16 15:8
RWDS and Data
are edge aligned
Dn
A
7:0
Command-Address
Dn
B
Dn+1 Dn+1
A
B
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
During write data transfers, RWDS indicates whether each data byte transfer is masked with RWDS HIGH (invalid and prevented
from changing the byte location in a memory) or not masked with RWDS Low (valid and written to a memory). Data masking may be
used by the host to byte align write data within a memory or to enable merging of multiple non-word aligned writes in a single burst
write. During write transactions, data is center-aligned with clock transitions.
Figure 3. Write Transaction, Single Initial Latency Count
CS#
tRWR =Read Write Recovery
tACC = Access
CK#, CK
CK and Data
are center aligned
Latency Count
RWDS
DQ[7:0]
High = 2x Latency Count
Low = 1x Latency Count
47:40
39:32
31:24
23:16
15:8
7:0
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Host drives DQ[7:0]
and RWDS
Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle. Each individual read
or write transaction can use either a wrapped or linear burst sequence.
Figure 4. Linear Versus Wrapped Burst Sequence
16 word group alignment boundaries
Linear Burst
4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h
Initial address = 4h
Wrapped Burst
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh
During wrapped transactions, accesses start at a selected location and continue to the end of a configured word group aligned
boundary, then wrap to the beginning location in the group, then continue back to the starting location. Wrapped bursts are generally
used for critical word first cache line fill read transactions. During linear transactions, accesses start at a selected location and
continue in a sequential manner until the transaction is terminated when CS# returns HIGH. Linear transactions are generally used
for large contiguous data transfers such as graphic images. Since each transaction command selects the type of burst sequence for
that transaction, wrapped and linear bursts transactions can be dynamically intermixed as needed.
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Product Overview
The 64 Mb HyperRAM device is 1.8 V or 3.0 V array and I/O, synchronous self-refresh DRAM. The HyperRAM device provides a
HyperBus slave interface to the host system. The HyperBus interface has an 8-bit (1 byte) wide DDR data bus and use only
word-wide (16-bit data) address boundaries. Read transactions provide 16 bits of data during each clock cycle (8 bits on both clock
edges). Write transactions take 16 bits of data from each clock cycle (8 bits on each clock edge).
Figure 5. HyperRAM Interface[1]
RESET#
CS#
CK
CK#
VCC
VCCQ
DQ[7:0]
RWDS
VSS
VSSQ
HyperBus Interface
Read and write transactions require two clock cycles to define the target row address and burst type, then an initial access latency of
tACC. During the CA part of a transaction, the memory will indicate whether an additional latency for a required refresh time (tRFH) is
added to the initial latency; by driving the RWDS signal to the HIGH state. During the CA period, the third clock cycle will specify the
target word address within the target row. During a read (or write) transaction, after the initial data value has been output (or input),
additional data can be read from (or written to) the row on subsequent clock cycles in either a wrapped or linear sequence. When
configured in linear burst mode, the device will automatically fetch the next sequential row from the memory array to support a
continuous linear burst. Simultaneously accessing the next row in the array while the read or write data transfer is in progress, allows
for a linear sequential burst operation that can provide a sustained data rate of 400 MBps [1 byte (8 bit data bus) * 2 (data clock
edges) * 200 MHz = 400 MBps].
Note
1. CK# is used in Differential Clock mode, but optional.
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Signal Description
Input/Output Summary
HyperRAM signals are shown in Table 1. Active Low signal names have a hash symbol (#) suffix.
Table 1. I/O Summary[3]
Symbol
CS#
CK,
CK#[2]
Type
Description
Chip Select. Bus transactions are initiated with a HIGH to LOW transition. Bus transacMaster Output, Slave Input tions are terminated with a LOW to HIGH transition. The master device has a separate
CS# for each slave.
Differential Clock. Command, address, and data information is output with respect to the
crossing of the CK and CK# signals. Use of differential clock is optional.
Master Output, Slave Input
Single Ended Clock. CK# is not used, only a single ended CK is used. The clock is not
required to be free-running.
Input/Output
Data Input/Output. Command, Address, and Data information is transferred on these
signals during Read and Write transactions.
RWDS
Input/Output
Read-Write Data Strobe. During the Command/Address portion of all bus transactions,
RWDS is a slave output and indicates whether additional initial latency is required. Slave
output during read data transfer, data is edge-aligned with RWDS. Slave input during
data transfer in write transactions to function as a data mask.
(HIGH = additional latency, LOW = no additional latency).
RESET#
Master Output, Slave
Input, Internal Pull-up
Hardware RESET. When LOW, the slave device will self initialize and return to the
STANDBY state. RWDS and DQ[7:0] are placed into the HIGH-Z state when RESET#
is LOW. The slave RESET# input includes a weak pull-up, if RESET# is left unconnected
it will be pulled up to the HIGH state.
VCC
Power Supply
Array Power.
VCCQ
Power Supply
Input/Output Power.
VSS
Power Supply
Array Ground.
VSSQ
Power Supply
Input/Output Ground.
No Connect
Reserved for Future Use. May or may not be connected internally, the signal/ball location
should be left unconnected and unused by PCB routing channel for future compatibility.
The signal/ball may be used by a signal in the future.
DQ[7:0]
RFU
Notes
2. CK# is used in Differential Clock mode, but optional connection. Tie the CK# input pin to either VccQ or VssQ if not connected to the host controller, but do not leave
it floating.
3. Optional Center-Aligned Read Strobe (DCARS) pinout and pin description are outlined in section DDR Center-Aligned Read Strobe (DCARS) Functionality on page 45.
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HyperBus Transaction Details
Command/Address Bit Assignments
All HyperRAM bus transactions can be classified as either read or write. A bus transaction is started with CS# going LOW with clock
in idle state (CK = LOW and CK# = HIGH). The first three clock cycles transfer three words of Command/Address (CA0, CA1, CA2)
information to define the transaction characteristics. The Command/Address words are presented with DDR timing, using the first six
clock edges.
The following characteristics are defined by the Command/Address information:
■
Read or Write transaction
■
Address Space: memory array space or register space
❐ Register space is used to access Device Identification (ID) registers and Configuration Registers (CR) that identify the device
characteristics and determine the slave specific behavior of read and write transfers on the HyperBus interface.
■
Whether a transaction will use a linear or wrapped burst sequence.
■
The target row (and half-page) address (upper order address)
■
The target column (word within half-page) address (lower order address)
Figure 6. Command-Address (CA) Sequence[4, 5, 6, 7]
CS#
CK , CK#
DQ[7:0]
CA0[47:40] CA0[39:32] CA1[31:24] CA1[23:16]
CA2[15:8]
CA2[7:0]
Table 2. CA Bit Assignment to DQ Signals
Signal
CA0[47:40]
CA0[39:32]
CA1[31:24]
CA1[23:16]
CA2[15:8]
CA2[7:0]
DQ[7]
CA[47]
CA[39]
CA[31]
CA[23]
CA[15]
CA[7]
DQ[6]
CA[46]
CA[38]
CA[30]
CA[22]
CA[14]
CA[6]
DQ[5]
CA[45]
CA[37]
CA[29]
CA[21]
CA[13]
CA[5]
DQ[4]
CA[44]
CA[36]
CA[28]
CA[20]
CA[12]
CA[4]
DQ[3]
CA[43]
CA[35]
CA[27]
CA[19]
CA[11]
CA[3]
DQ[2]
CA[42]
CA[34]
CA[26]
CA[18]
CA[10]
CA[2]
DQ[1]
CA[41]
CA[33]
CA[25]
CA[17]
CA[9]
CA[1]
DQ[0]
CA[40]
CA[32]
CA[24]
CA[16]
CA[8]
CA[0]
Notes
4. Figure 6 shows the initial three clock cycles of all transactions on the HyperBus.
5. CK# of differential clock is shown as dashed line waveform.
6. CA information is “center-aligned” with the clock during both Read and Write transactions.
7. Data bits in each byte are always in high to low order with bit 7 on DQ7 and bit 0 on DQ0.
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Table 3. Command/Address Bit Assignments[8, 9, 10, 11]
CA Bit#
Bit Name
47
Bit Function
Identifies the transaction as a read or write.
R/W# = 1 indicates a Read transaction
R/W# = 0 indicates a Write transaction
R/W#
Indicates whether the read or write transaction accesses the memory or register space.
Address Space AS = 0 indicates memory space
(AS)
AS = 1 indicates the register space
The register space is used to access device ID and Configuration registers.
46
45
Burst Type
44-16
Indicates whether the burst will be linear or wrapped.
Burst Type = 0 indicates wrapped burst
Burst Type = 1 indicates linear burst
Row & Upper Column component of the target address: System word address bits A31-A3
Row & Upper Any upper Row address bits not used by a particular device density should be set to 0 by the host
Column Address controller master interface. The size of Rows and therefore the address bit boundary between
Row and Column address is slave device dependent.
15-3
Reserved
2-0
Lower Column
Address
Reserved for future column address expansion.
Reserved bits are don’t care in current HyperBus devices but should be set to 0 by the host
controller master interface for future compatibility.
Lower Column component of the target address: System word address bits A2-A0 selecting the
starting word within a half-page.
Figure 7. Data Placement During a Read Transaction[12, 13, 14, 15, 16]
CS#
CK , CK#
RWDS
DQ[7:0]
Dn A
Dn B
Dn+1 A
Dn+1 B
Dn+2 A
Notes
8. A Row is a group of words relevant to the internal memory array structure. The number of Rows is also used in the calculation of a distributed refresh interval for
HyperRAM memory.
9. The Column address selects the burst transaction starting word location within a Row. The Column address is split into an upper and lower portion. The upper portion
selects an 8-word (16-byte) Half-page and the lower portion selects the word within a Half-page where a read or write transaction burst starts.
10. The initial read access time starts when the Row and Upper Column (Half-page) address bits are captured by a slave interface. Continuous linear read burst is
enabled by memory devices internally interleaving access to 16 byte half-pages.
11. HyperBus protocol address space limit, assuming:
29 Row &Upper Column address bits
3 Lower Column address bits
Each address selects a word wide (16 bit = 2 byte) data value
29 + 3 = 32 address bits = 4G addresses supporting 8GB (64Gb) maximum address space
Future expansion of the column address can allow for 29 Row &Upper Column + 16 Lower Column address bits = 35 Tera-word = 70 Tera-byte address space.
12. Figure 7 shows a portion of a Read transaction on the HyperBus. CK# of differential clock is shown as dashed line waveform.
13. Data is “edge-aligned” with the RWDS serving as a read data strobe during read transactions.
14. Data is always transferred in full word increments (word granularity transfers).
15. Word address increments in each clock cycle. Byte A is between RWDS rising and falling edges and is followed by byte B between RWDS falling and rising edges,
of each word.
16. Data bits in each byte are always in high to low order with bit 7 on DQ7 and bit 0 on DQ0.
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Data placement during memory Read/Write is dependent upon the host. The device will output data (read) as it was written in
(write). Hence both Big Endian and Little Endian are supported for the memory array.
Data placement during register Read/Write is Big Endian.
Table 4. Data Bit Placement During Read or Write Transaction
Address
Space
Byte
Order
Byte
Position
A
Bigendian
B
Memory
A
Littleendian
B
Word
Data
Bit
DQ
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
Document Number: 002-24692 Rev. *G
Bit Order
When data is being accessed in memory space:
The first byte of each word read or written is the “A” byte and the second is the “B” byte.
The bits of the word within the A and B bytes depend on how the data was written. If the word
lower address bits 7-0 are written in the A byte position and bits 15-8 are written into the B
byte position, or vice versa, they will be read back in the same order.
Memory space can be stored and read in either little-endian or big-endian order.
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Table 4. Data Bit Placement During Read or Write Transaction (Continued)
Address
Space
Byte
Order
Byte
Position
A
Register
Bigendian
B
Word
Data
Bit
DQ
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Bit Order
When data is being accessed in register space:
During a Read transaction on the HyperBus two bytes are transferred on each clock cycle.
The upper order byte A (Word[15:8]) is transferred between the rising and falling edges of
RWDS (edge-aligned). The lower order byte B (Word[7:0]) is transferred between the falling
and rising edges of RWDS.
During a write, the upper order byte A (Word[15:8]) is transferred on the CK rising edge and
the lower order byte B (Word[7:0]) is transferred on the CK falling edge.
So, register space is always read and written in Big-endian order because registers have
device dependent fixed bit location and meaning definitions.
Figure 8. Data Placement During a Write Transaction[17, 18, 19, 20]
CS#
CK , CK#
RWDS
DQ[7:0]
Dn A
Dn B
Dn+1 A
Dn+1 B
Dn+2 A
Notes
17. Figure 8 shows a portion of a Write transaction on the HyperBus.
18. Data is “center-aligned” with the clock during a Write transaction.
19. RWDS functions as a data mask during write data transfers with initial latency. Masking of the first and last byte is shown to illustrate an unaligned 3 byte write of data.
20. RWDS is not driven by the master during write data transfers with zero initial latency. Full data words are always written in this case. RWDS may be driven LOW or
left HIGH-Z by the slave in this case.
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Read Transactions
The HyperBus master begins a transaction by driving CS# LOW while clock is idle. The clock then begins toggling while CA words
are transferred.
In CA0, CA[47] = 1 indicates that a Read transaction is to be performed. CA[46] = 0 indicates the memory space is being read or
CA[46] = 1 indicates the register space is being read. CA[45] indicates the burst type (wrapped or linear). Read transactions can
begin the internal array access as soon as the row and upper column address has been presented in CA0 and CA1 (CA[47:16]).
CA2 (CA(15:0]) identifies the target Word address within the chosen row.
The HyperBus master then continues clocking for a number of cycles defined by the latency count setting in Configuration Register
0. The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is LOW during the CA cycles, one
latency count is inserted. If RWDS is HIGH during the CA cycles, an additional latency count is inserted. Once these latency clocks
have been completed the memory starts to simultaneously transition the RWDS and output the target data.
New data is output edge-aligned with every transition of RWDS. Data will continue to be output as long as the host continues to
transition the clock while CS# is LOW. Note that burst transactions should not be so long as to prevent the memory from doing
distributed refreshes.
Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential manner across row
boundaries. When a linear burst read reaches the last address in the array, continuing the burst beyond the last address will provide
data from the beginning of the address range. Read transfers can be ended at any time by bringing CS# HIGH when the clock is
idle.
The clock is not required to be free-running. The clock may remain idle while CS# is HIGH.
Figure 9. Read Transaction with Additional Initial Latency[21-28]
CS#
Additional Latency
t RWR = Read Write Recovery
tACC = Access
CK# , CK
RWDS
High = 2x Latency Count
Low = 1x Latency Count
Latency Count 1
DQ[7:0]
47:40 39:32 31:24 23:16 15:8
Latency Count 2
7:0
Command-Address
RWDS and Data
are edge aligned
Dn
A
Dn Dn+1 Dn+1
B
A
B
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Notes
21. Transactions are initiated with CS# falling while CK = LOW and CK# = HIGH.
22. CS# must return HIGH before a new transaction is initiated.
23. CK# is the complement of the CK signal.CK# of a differential clock is shown as a dashed line waveform.
24. Read access array starts once CA[23:16] is captured.
25. The read latency is defined by the initial latency value in a configuration register.
26. In this read transaction example the initial latency count was set to four clocks.
27. In this read transaction a RWDS HIGH indication during CA delays output of target data by an additional four clocks.
28. The memory device drives RWDS during read transactions.
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Figure 10. Read Transaction Without Additional Initial Latency[29]
CS#
t RWR =Read Write Recovery
t ACC = Initial Acces
s
CK, CK#
RWDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
4 cycle latency
DQ[7:0]
47:40
39:32
31:24
23:16
15:8
7:0
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Memory drives DQ[7:0]
and RWDS
Write Transactions (Memory Array Write)
The HyperBus master begins a transaction by driving CS# LOW while clock is idle. Then the clock begins toggling while CA words
are transferred.
In CA0, CA[47] = 0 indicates that a Write transaction is to be performed. CA[46] = 0 indicates the memory space is being written.
CA[45] indicates the burst type (wrapped or linear). Write transactions can begin the internal array access as soon as the row and
upper column address has been presented in CA0 and CA1 (CA[47:16]). CA2 (CA(15:0]) identifies the target word address within
the chosen row.
The HyperBus master then continues clocking for a number of cycles defined by the latency count setting in configuration register 0.
The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is LOW during the CA cycles, one
latency count is inserted. If RWDS is HIGH during the CA cycles, an additional latency count is inserted.
Once these latency clocks have been completed, the HyperBus master starts to output the target data. Write data is center-aligned
with the clock edges. The first byte of data in each word is captured by the memory on the rising edge of CK and the second byte is
captured on the falling edge of CK.
During the CA clock cycles, RWDS is driven by the memory.
During the write data transfers, RWDS is driven by the host master interface as a data mask. When data is being written and RWDS
is HIGH, the byte will be masked and the array will not be altered. When data is being written and RWDS is LOW, the data will be
placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor the HyperRAM device
are able to indicate a need for latency within the data transfer portion of a write transaction. The acceptable write data burst length
setting is also shown in configuration register 0.
Data will continue to be transferred as long as the HyperBus master continues to transition the clock while CS# is LOW. Note that
burst transactions should not be so long as to prevent the memory from doing distributed refreshes. Legacy format wrapped bursts
will continue to wrap within the burst length. Hybrid wrap will wrap once then switch to linear burst starting at the next wrap
boundary. Linear burst accepts data in a sequential manner across page boundaries. Write transfers can be ended at any time by
bringing CS# HIGH when the clock is idle.
When a linear burst write reaches the last address in the memory array space, continuing the burst will write to the beginning of the
address range.
The clock is not required to be free-running. The clock may remain idle while CS# is HIGH.
Note
29. RWDS is LOW during the CA cycles. In this Read Transaction, there is a single initial latency count for read data access because, this read transaction does not
begin at a time when additional latency is required by the slave.
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Figure 11. Write Transaction with Additional Initial Latency[30-36]
CS#
Additional Latency
t RWR = Read Write Recovery
tACC = Initial Access
CK, CK#
RWDS
DQ[7:0]
High = 2x Latency Count
Low = 1x Latency Count
Latency Count 1
47:40 39:32 31:24 23:16 15:8
CK and Data
are center aligned
Latency Count 2
Dn
A
7:0
Dn Dn+1 Dn+1
B
B
A
Host drives DQ[7:0]
and RWDS
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Figure 12. Write Transaction Without Additional Initial Latency[32-36]
CS#
tRWR=Read Write Recovery
tACC = Access
CK# , CK
RWDS
High = 2x Latency Count
Low = 1x Latency Count
CK and Data
are center aligned
Latency Count
DQ[7:0]
47:40
39:32
31:24
23:16
15:8
7:0
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Host drives DQ[7:0]
and RWDS
Notes
30. Transactions must be initiated with CK = LOW and CK# = HIGH.
31. CS# must return HIGH before a new transaction is initiated.
32. During CA, RWDS is driven by the memory and indicates whether additional latency cycles are required.
33. In this example, RWDS indicates that additional initial latency cycles are required.
34. At the end of CA cycles the memory stops driving RWDS to allow the host HyperBus master to begin driving RWDS. The master must drive RWDS to a valid LOW
before the end of the initial latency to provide a data mask preamble period to the slave.
35. During data transfer, RWDS is driven by the host to indicate which bytes of data should be either masked or loaded into the array.
36. The figure shows RWDS masking byte Dn A and byte Dn+1 B to perform an unaligned word write to bytes Dn B and Dn+1 A.
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Write Transactions without Initial Latency (Register Write)
A Write transaction starts with the first three clock cycles providing the Command/Address information indicating the transaction
characteristics. CA0 may indicate that a Write transaction is to be performed and also indicates the address space and burst type
(wrapped or linear).
Writes without initial latency are used for register space writes. HyperRAM device write transactions with zero latency mean that the
CA cycles are followed by write data transfers. Writes with zero initial latency, do not have a turn around period for RWDS. The
HyperRAM device will always drive RWDS during the CA period to indicate whether extended latency is required for a transaction
that has initial latency. However, the RWDS is driven before the HyperRAM device has received the first byte of CA i.e., before the
HyperRAM device knows whether the transaction is a read or write to register space. In the case of a write with zero latency, the
RWDS state during the CA period does not affect the initial latency of zero. Since master write data immediately follows the CA
period in this case, the HyperRAM device may continue to drive RWDS LOW or may take RWDS to HIGH-Z during write data
transfer. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not use RWDS as a data
mask function. All bytes of write data are written (full word writes).
The first byte of data in each word is presented on the rising edge of CK and the second byte is presented on the falling edge of CK.
Write data is center-aligned with the clock inputs. Write transfers can be ended at any time by bringing CS# HIGH when clock is idle.
The clock is not required to be free-running.
Figure 13. Write Operation without Initial Latency
CS#
CK#, CK
RWDS
DQ[7:0]
High: 2X Latency Count*
Low: 1X Latency Count*
CA
[47:40]
CA
[39:32]
CA
[31:24]
CA
[23:16]
CA
[15:8]
Command - Address
(Host drives DQ[7:0], Memory drives RWDS)
CA
[7:0]
RG
[15:8]
RG
[7:0]
Write Data
*: Latency count is not applicable for Register Write. The RWDS driven Low or High during
CA cycle should be ignored by the host and the host must continue Register Write with zero
latency.
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Memory Space
HyperBus Interface
Table 5. Memory Space Address Map (word based - 16 bits)
Unit Type
Count
System Word
Address Bits
CA Bits
Notes
Rows within 64 Mb device
8192 (rows)
A21 - A9
34 - 22
−
1 (row)
A8 - A3
21 - 16
512 (word addresses)
1 KB
8 (word addresses)
A2 - A0
2-0
8 words (16 bytes)
Row
Half-page
Register Space
HyperBus Interface
When CA[46] is 1, a read or write transaction accesses the Register Space.
Table 6. Register Space Address Map
Register
System
Address
—
—
—
31-27
26-19
18-11
10-3
—
2-0
CA Bits
47
46
45[37]
44-40
39-32
31-24
23-16
15-8
7-0
Identification Register 0
Read[38]
C0h or E0h
00h
00h
00h
00h
00h
Identification Register 1
Read[38]
C0h or E0h
00h
00h
00h
00h
01h
Configuration Register 0 Read
C0h or E0h
00h
01h
00h
00h
00h
Configuration Register 0 Write
60h
00h
01h
00h
00h
00h
Configuration Register 1 Read
C0h or E0h
00h
01h
00h
00h
01h
Configuration Register 1 Write
60h
00h
01h
00h
00h
01h
C0h or E0h
00h
02h
00h
00h
00h - 11h
Die Manufacture Information
Register (0-17) Read
Notes
37. CA45 may be either 0 or 1 for either wrapped or linear read. CA45 must be 1 as only linear single word register writes are supported.
38. The Burst type (wrapped/linear) definition is not supported in Register Reads. Hence C0h/E0h have the same effect.
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Device Identification Registers
There are two read only, nonvolatile word registers, that provide information on the device selected when CS# is LOW.
The device information fields identify:
■
Manufacturer
■
Type
■
Density
❐ Row address bit count
❐ Column address bit count
Table 7. Identification Register 0 (ID0) Bit Assignments
Bits
Function
[15:14]
MCP Die Address
00 - Default
[13]
Reserved
0 - Default
[12:8]
Row Address Bit Count
[7:4]
Column Address Bit Count
[3:0]
Manufacturer
Settings (Binary)
00000 - One row address bit
...
11111 - Thirty-two row address bits
...
01100 - 64 Mb - Thirteen row address bits (default)
0000 - One column address bits
...
1000 - Nine column address bits (default)
...
1111 - Sixteen column address bits
0001 - Cypress
0000, 0010 to 1111 - Reserved
:
Table 8. Identification Register 1 (ID1) Bit Assignments
Bits
Function
[15:4]
Reserved
[3:0]
Device Type
Settings (Binary)
0000_0000_0000 (default)
0001 - HyperRAM 2.0
0000, 0010 to 1111 - Reserved
Density and Row Boundaries
The DRAM array size (density) of the device can be determined from the total number of system address bits used for the row and
column addresses as indicated by the Row Address Bit Count and Column Address Bit Count fields in the ID0 register. For example:
a 64 Mb HyperRAM device has 9 column address bits and 13 row address bits for a total of 22 word address bits = 222 = 4 Mwords
= 8 MBs. The 9 column address bits indicate that each row holds 29 = 512 words = 1 KB. The row address bit count indicates there
are 8196 rows to be refreshed within each array refresh interval. The row count is used in calculating the refresh interval.
ID0 value for the 64 Mb HyperRAM is 0x0C81.
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Register Space Access
Register default values are loaded upon power-up or hardware reset. The registers can be altered at any time while the device is in
the STANDBY state.
Loading a register is accomplished with write transaction without initial latency using a single 16-bit word write transaction.
Each register is written with a separate single word write transaction. Register write transactions have zero latency, the single word
of data immediately follows the CA. RWDS is not driven by the host during the write because RWDS is always driven by the memory
during the CA cycles to indicate whether a memory array refresh is in progress. Because a register space write goes directly to a
register, rather than the memory array, there is no initial write latency, related to an array refresh that may be in progress. In a
register write, RWDS is also not used as a data mask because both bytes of a register are always written and never masked.
Reserved register fields must be written with their default value. Writing reserved fields with other than default values may produce
undefined results.
Notes
■
The host must not drive RWDS during a write to register space.
■
The RWDS signal is driven by the memory during the CA period based on whether the memory array is being refreshed. This refresh
indication does not affect the writing of register data.
■
The RWDS signal returns to high impedance after the CA period. Register data is never masked. Both data bytes of the register
data are loaded into the selected register.
Reading of a register is accomplished with read transaction with single or double initial latency using a single 16 bit read transaction.
If more than one word is read, the output becomes indeterminate. The contents of the register is returned in the same manner as
reading the memory array, as shown in Figure 9, with one or two latency counts, based on the state of RWDS during the CA period.
The latency count is defined in the Configuration Register 0 Read Latency field (CR0[7:4]).
Configuration Register 0
Configuration Register 0 (CR0) is used to define the power state and access protocol operating conditions for the HyperRAM device.
Configurable characteristics include:
■
Wrapped Burst Length (16, 32, 64, or 128 byte aligned and length data group)
■
Wrapped Burst Type
❐ Legacy wrap (Sequential access with wrap around within a selected length and aligned group)
❐ Hybrid wrap (Legacy wrap once then linear burst at start of the next sequential group)
■
Initial Latency
■
Variable Latency
❐ Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected the memory will always
indicate a refresh latency and delay the read data transfer accordingly. If variable latency is selected, latency for a refresh is only
added when a refresh is required at the same time a new transaction is starting.
■
Output Drive Strength
■
Deep Power Down (DPD) Mode
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Table 9. Configuration Register 0 (CR0) Bit Assignments
CR0 Bit
[15]
Function
Deep Power Down Enable
[14:12]
Drive Strength
[11:8]
Reserved
[7:4]
Initial Latency
[3]
Fixed Latency Enable
Settings (Binary)
1 - Normal operation (default). HyperRAM will automatically set this value to
“1” after DPD exit
0 - Writing 0 causes the device to enter Deep Power Down
000 - 34 ohms (default)
001 - 115 ohms
010 - 67 ohms
011 - 46 ohms
100 - 34 ohms
101 - 27 ohms
110 - 22 ohms
111 - 19 ohms
1 - Reserved (default)
Reserved for Future Use. When writing this register, these bits should be set to
1 for future compatibility.
0000 - 5 Clock Latency @ 133 MHz Max Frequency
0001 - 6 Clock Latency @ 166 MHz Max Frequency
0010 - 7 Clock Latency @ 200 MHz/166 MHz Max Frequency (default)
0011 - Reserved
0100 - Reserved
...
1101 - Reserved
1110 - 3 Clock Latency @ 85 MHz Max Frequency
1111 - 4 Clock Latency @ 104 MHz Max Frequency
0 - Variable Latency - 1 or 2 times Initial Latency depending on RWDS during
CA cycles.
1 - Fixed 2 times Initial Latency (default)
0: Wrapped burst sequence to follow hybrid burst sequencing
1: Wrapped burst sequence in legacy wrapped burst manner (default)
[2]
[1:0]
Hybrid Burst Enable
Burst Length
This bit setting is effective only when the "Burst Type" bit in the
Command/Address register is set to '0', i.e. CA[45] = '0'; otherwise, it is
ignored.
00 - 128 bytes
01 - 64 bytes
10- 16 bytes
11 - 32 bytes (default)
Wrapped Burst
A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching the length of the
configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes alignment and length. During wrapped
transactions, access starts at the CA selected location within the group, continues to the end of the configured word group aligned
boundary, then wraps around to the beginning location in the group, then continues back to the starting location. Wrapped bursts are
generally used for critical word first instruction or data cache line fill read accesses.
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Hybrid Burst
The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing to the next
half-page of data beyond the end of the wrap group. Continued access is in linear burst order until the transfer is ended by returning
CS# HIGH. This hybrid of a wrapped burst followed by a linear burst starting at the beginning of the next burst group, allows multiple
sequential address cache lines to be filled in a single access. The first cache line is filled starting at the critical word. Then the next
sequential line in memory can be read in to the cache while the first line is being processed.
Table 10. CR0[2] Control of Wrapped Burst Sequence
Bit
Default Value
2
1
Name
Hybrid Burst Enable
CR0[2] = 0: Wrapped burst sequence to follow hybrid burst sequencing
CR0[2] = 1: Wrapped burst sequence in legacy wrapped burst manner
Table 11. Example Wrapped Burst Sequences (HyperBus Addressing)
Burst Type
Wrap
Boundary
(bytes)
Start Address
(Hex)
Sequence of Word Addresses (Hex) of Data Words
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16,
17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A,
2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E,
3F, 00, 01, 02
(Wrap complete, now linear beyond the end of the initial 128 byte wrap group)
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ...
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02
(wrap complete, now linear beyond the end of the initial 64 byte wrap group)
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, ...
Hybrid 64
64 Wrap
once then
Linear
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 2A, 2B, 2C, 2D
(wrap complete, now linear beyond the end of the initial 64 byte wrap group)
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ...
Hybrid 16
16 Wrap
once then
Linear
XXXXXX02
02, 03, 04, 05, 06, 07, 00, 01
(wrap complete, now linear beyond the end of the initial 16 byte wrap group)
08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, ...
Hybrid 16
16 Wrap
once then
Linear
XXXXXX0C
0C, 0D, 0E, 0F, 08, 09, 0A, 0B
(wrap complete, now linear beyond the end of the initial 16 byte wrap group)
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, ...
Hybrid 32
32 Wrap
once then
Linear
XXXXXX0A
0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09
(wrap complete, now linear beyond the end of the initial 32 byte wrap group)
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, ...
Wrap 64
64
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, ...
Wrap 64
64
XXXXXX2E
2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, ...
Wrap 16
16
XXXXXX02
02, 03, 04, 05, 06, 07, 00, 01, ...
Wrap 16
16
XXXXXX0C
0C, 0D, 0E, 0F, 08, 09, 0A, 0B, ...
Wrap 32
32
XXXXXX0A
0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ...
Linear
Linear Burst
XXXXXX03
03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ...
Hybrid 128
128 Wrap
once then
Linear
Hybrid 64
64 Wrap
once then
Linear
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Initial Latency
Memory Space read and write transactions or Register Space read transactions require some initial latency to open the row selected
by the CA. This initial latency is tACC. The number of latency clocks needed to satisfy tACC depends on the HyperBus frequency can
vary from 3 to 7 clocks. The value in CR0[7:4] selects the number of clocks for initial latency. The default value is 7 clocks, allowing
for operation up to a maximum frequency of 200 MHz prior to the host system setting a lower initial latency value that may be more
optimal for the system.
In the event a distributed refresh is required at the time a Memory Space read or write transaction or Register Space read
transaction begins, the RWDS signal goes HIGH during the CA to indicate that an additional initial latency is being inserted to allow
a refresh operation to complete before opening the selected row.
Register Space write transactions always have zero initial latency. RWDS may be HIGH or LOW during the CA period. The level of
RWDS during the CA period does not affect the placement of register data immediately after the CA, as there is no initial latency
needed to capture the register data. A refresh operation may be performed in the memory array in parallel with the capture of
register data.
Fixed Latency
A configuration register option bit CR0[3] is provided to make all Memory Space read and write transactions or Register Space read
transactions require the same initial latency by always driving RWDS HIGH during the CA to indicate that two initial latency periods
are required. This fixed initial latency is independent of any need for a distributed refresh, it simply provides a fixed (deterministic)
initial latency for all of these transaction types. The fixed latency option may simplify the design of some HyperBus memory
controllers or ensure deterministic transaction performance. Fixed latency is the default POR or reset configuration. The system may
clear this configuration bit to disable fixed latency and allow variable initial latency with RWDS driven HIGH only when additional
latency for a refresh is required.
Drive Strength
DQ and RWDS signal line loading, length, and impedance vary depending on each system design. Configuration register bits
CR0[14:12] provide a means to adjust the DQ[7:0] and RWDS signal output impedance to customize the DQ and RWDS signal
impedance to the system conditions to minimize high speed signal behaviors such as overshoot, undershoot, and ringing. The
default POR or reset configuration value is 000b to select the mid point of the available output impedance options.
The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process conditions, nominal
operating voltage (1.8 V or 3.0 V) and 50°C. The impedance values may vary from the typical values depending on the Process,
Voltage, and Temperature (PVT) conditions. Impedance will increase with slower process, lower voltage, or higher temperature.
Impedance will decrease with faster process, higher voltage, or lower temperature.
Each system design should evaluate the data signal integrity across the operating voltage and temperature ranges to select the best
drive strength settings for the operating conditions.
Deep Power Down
When the HyperRAM device is not needed for system operation, it may be placed in a very low power consuming state called Deep
Power Down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the DPD state within tDPDIN time and
all refresh operations stop. The data in RAM is lost, (becomes invalid without refresh) during DPD state. Exiting DPD requires driving
CS# LOW then HIGH, POR, or a reset. Only CS# and RESET# signals are monitored during DPD mode. For additional details, see
Deep Power Down on page 26.
Configuration Register 1
Configuration Register 1 (CR1) is used to define the refresh array size, refresh rate and hybrid sleep for the HyperRAM device.
Configurable characteristics include:
■
Partial Array Refresh
■
Hybrid Sleep State
■
Refresh rate
Table 12. Configuration Register 1 (CR1) Bit Assignments
CR1 Bit
Function
[15:8]
Reserved
FFh - Reserved (default)
These bits should always be set to FFh
[7]
Reserved
1 - Reserved (default)
[6]
Master Clock Type
Document Number: 002-24692 Rev. *G
Setting (Binary)
1 - Single-Ended - CK (default)
0 - Differential - CK#, CK
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Table 12. Configuration Register 1 (CR1) Bit Assignments (Continued)
CR1 Bit
Function
Setting (Binary)
Hybrid Sleep
1 - Causes the device to enter Hybrid Sleep State
0 - Normal operation (default)
[4:2]
Partial Array
Refresh
000 - Full Array (default)
001 - Bottom 1/2 Array
010 - Bottom 1/4 Array
011 - Bottom 1/8 Array
100 - none
101 - Top 1/2 Array
110 - Top 1/4 Array
111 - Top 1/8 Array
[1:0]
Distributed Refresh
Interval (Read Only)
[5]
10 - 1μs tCSM (Industrial Plus temperature range devices)
11 - Reserved
00 - Reserved
01 - 4μs tCSM (Industrial temperature range devices)
Master Clock Type
Two clock types, namely single ended and differential, are supported. CR1[6] selects which type to use.
Partial Array Refresh
The partial array refresh configuration restricts the refresh operation in HyperRAM to a portion of the memory array specified by
CR1[5:3]. This reduces the standby current. The default configuration refreshes the whole array.
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Hybrid Sleep (HS)
When the HyperRAM is not needed for system operation but data in the device needs to be retained, it may be placed in Hybrid
Sleep state to save more power. Enter Hybrid Sleep state by writing 0 to CR1[5]. Bringing CS# LOW will cause the device to exit HS
state and set CR1[5] to 1. Also, POR, or a hardware reset will cause the device to exit Hybrid Sleep state. Note that a POR or a
hardware reset disables refresh where the memory core data can potentially get lost.
Distributed Refresh Interval
The DRAM array requires periodic refresh of all bits in the array. This can be done by the host system by reading or writing a location
in each row within a specified time limit. The read or write access copies a row of bits to an internal buffer. At the end of the access
the bits in the buffer are written back to the row in memory, thereby recharging (refreshing) the bits in the row of DRAM memory
cells.
HyperRAM devices include self-refresh logic that will refresh rows automatically. The automatic refresh of a row can only be done
when the memory is not being actively read or written by the host system. The refresh logic waits for the end of any active read or
write before doing a refresh, if a refresh is needed at that time. If a new read or write begins before the refresh is completed, the
memory will drive RWDS HIGH during the CA period to indicate that an additional initial latency time is required at the start of the
new access in order to allow the refresh operation to complete before starting the new access.
The required refresh interval for the entire memory array varies with temperature as shown in Table 13. This is the time within which
all rows must be refreshed. Refresh of all rows could be done as a single batch of accesses at the beginning of each interval, in
groups (burst refresh) of several rows at a time, spread throughout each interval, or as single row refreshes evenly distributed
throughout the interval. The self-refresh logic distributes single row refresh operations throughout the interval so that the memory is
not busy doing a burst of refresh operations for a long period, such that the burst refresh would delay host access for a long period.
Table 13. Array Refresh Interval per Temperature
Device Temperature (°C)
Array Refresh Interval (ms)
Array Rows
Recommended tCSM (µs)
85
64
8192
4
105
16
8192
1
The distributed refresh method requires that the host does not do burst transactions that are so long as to prevent the memory from
doing the distributed refreshes when they are needed. This sets an upper limit on the length of read and write transactions so that
the refresh logic can insert a refresh between transactions. This limit is called the CS# LOW maximum time (tCSM). The tCSM value is
determined by the array refresh interval divided by the number of rows in the array, then reducing this calculation by half to ensure
that a distributed refresh interval cannot be entirely missed by a maximum length host access starting immediately before a
distributed refresh is needed. Because tCSM is set to half the required distributed refresh interval, any series of maximum length host
accesses that delay refresh operations will catch up on refresh operations at twice the rate required by the refresh interval divided by
the number of rows.
The host system is required to respect the tCSM value by ending each transaction before violating tCSM. This can be done by host
memory controller logic splitting long transactions when reaching the tCSM limit, or by host system hardware or software not
performing a single read or write transaction that would be longer than tCSM.
As noted in Table 13, the array refresh interval is longer at lower temperatures such that tCSM could be increased to allow longer
transactions. The host system can either use the tCSM value from the table for the maximum operating temperature or, may
determine it dynamically by reading the read only CR1[1:0] bits in order to set the distributed refresh interval prior to every access.
Document Number: 002-24692 Rev. *G
Page 23 of 51
S27KL0642/S27KS0642
Interface States
Table 14 describes the required value of each signal for each interface state.
Table 14. Interface States
Interface State
VCC / VCCQ
CS#
CK, CK#
DQ7-DQ0
RWDS
RESET#
< VLKO
X
X
HIGH-Z
HIGH-Z
X
Power-On (Cold) Reset
≥ VCC / VCCQ min
X
X
HIGH-Z
HIGH-Z
X
Hardware (Warm) Reset
≥ VCC / VCCQ min
X
X
HIGH-Z
HIGH-Z
L
Interface Standby
≥ VCC / VCCQ min
H
X
HIGH-Z
HIGH-Z
H
Y
H
Power-Off
≥ VCC / VCCQ min
L
T
Master Output
Valid
Read Initial Access Latency
≥ VCC / VCCQ min
(data bus turn around period)
L
T
HIGH-Z
L
H
Write Initial Access Latency
(RWDS turn around period)
≥ VCC / VCCQ min
L
T
HIGH-Z
HIGH-Z
H
Read data transfer
≥ VCC / VCCQ min
L
T
Slave Output Valid
Slave Output Valid
Z or T
H
Write data transfer with Initial
Latency
≥ VCC / VCCQ min
L
T
Master Output
Valid
Master Output Valid
X or T
H
Write data transfer without
Initial Latency[39]
≥ VCC / VCCQ min
L
T
Master Output
Valid
Slave Output
L or HIGH-Z
H
Active Clock Stop[40]
≥ VCC / VCCQ min
L
Idle
Master or Slave
Output Valid or
HIGH-Z
Y
H
Deep Power Down
≥ VCC / VCCQ min
H
X or T
HIGH-Z
HIGH-Z
H
Hybrid Sleep
≥ VCC / VCCQ min
H
X or T
HIGH-Z
HIGH-Z
H
CA
Legend
L = VIL
H = VIH
X = either VIL or VIH
Y= either VIL or VIH or VOL or VOH
Z = either VOL or VOH
L/H = rising edge
H/L = falling edge
T = Toggling during information transfer
Idle = CK is LOW and CK# is HIGH.
Valid = all bus signals have stable L or H level
Notes
39. Writes without initial latency (with zero initial latency), do not have a turn around period for RWDS. The HyperRAM device will always drive RWDS during the CA
period to indicate whether extended latency is required. Since master write data immediately follows the CA period the HyperRAM device may continue to drive
RWDS LOW or may take RWDS to HIGH-Z. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not use RWDS as a data
mask function. All bytes of write data are written (full word writes).
40. Active Clock Stop is described in Active Clock Stop on page 25. DPD is described in Hybrid Sleep on page 25.
Document Number: 002-24692 Rev. *G
Page 24 of 51
S27KL0642/S27KS0642
Power Conservation Modes
Interface Standby
STANDBY is the default, low power, state for the interface while the device is not selected by the host for data transfer (CS# =
HIGH). All inputs, and outputs other than CS# and RESET# are ignored in this state.
Active Clock Stop
The Active Clock Stop state reduces device interface energy consumption to the ICC6 level during the data transfer portion of a read
or write operation. The device automatically enables this state when clock remains stable for tACC + 30 ns. While in Active Clock
Stop state, read data is latched and always driven onto the data bus. ICC6 shown in DC Characteristics on page 29.
Active Clock Stop state helps reduce current consumption when the host system clock has stopped to pause the data transfer. Even
though CS# may be LOW throughout these extended data transfer cycles, the memory device host interface will go into the Active
Clock Stop current level at tACC + 30 ns. This allows the device to transition into a lower current state if the data transfer is stalled.
Active read or write current will resume once the data transfer is restarted with a toggling clock. The Active Clock Stop state must not
be used in violation of the tCSM limit. CS# must go HIGH before tCSM is violated. Clock can be stopped during any portion of the
active transaction as long as it is in the LOW state. Note that it is recommended to avoid stopping the clock during register access.
Figure 14. Active Clock Stop During Read Transaction (DDR)[41]
CS#
Clock Stopped
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
DQ[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutB
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
DoutA+1
[7:0]
Output Driven
DoutB+1
[7:0]
Read Data
Hybrid Sleep
In the Hybrid Sleep (HS) state, the current consumption is reduced (iHS). HS state is entered by writing a 0 to CR1[5]. The device
reduces power within tHSIN time. The data in Memory Space and Register Space is retained during HS state. Bringing CS# LOW will
cause the device to exit HS state and set CR1[5] to 1. Also, POR, or a hardware reset will cause the device to exit Hybrid Sleep
state. Note that a POR or a hardware reset disables refresh where the memory core data can potentially get lost. Returning to
STANDBY state requires tEXITHS time. Following the exit from HS due to any of these events, the device is in the same state as
entering Hybrid Sleep.
Figure 15. Enter HS Transaction
CS#
C K#, C K
H ig h: 2 X L a te n cy C o u n t
L o w : 1 X L a te n cy C o u n t
RW DS
t H S IN
D Q [7 :0]
CM D
[7 :0 ]
CMD
[7:0 ]
ADR
[3 1 :2 4 ]
ADR
[2 3 :1 6 ]
ADR
[1 5 :8 ]
C o m m a n d - A d d re ss
(H o st d rive s D Q [7:0], M e m o ry d rive s R W D S)
ADR
[7 :0 ]
RG
[1 5:8 ]
RG
[7 :0 ]
W rite D a ta
C R 0 V a lu e
E n te r H yb rid S le e p
t H S IN
HS
Figure 16. Exit HS Transaction
CS#
tCSHS
tEXTHS
Note
41. RWDS is LOW during the CA cycles. In this Read Transaction, there is a single initial latency count for read data access because, this read transaction does not
begin at a time when additional latency is required by the slave.
Document Number: 002-24692 Rev. *G
Page 25 of 51
S27KL0642/S27KS0642
Table 15. Hybrid Sleep Timing Parameters
Parameter
Min
Max
Unit
tHSIN
Hybrid Sleep CR1[5] = 0 register write to DPD power level
Description
−
3
µs
tCSHS
CS# Pulse Width to Exit HS
60
3000
ns
tEXTHS
CS# Exit Hybrid Sleep to Standby wakeup time
−
100
µs
Deep Power Down
In the Deep Power Down (DPD) state, current consumption is driven to the lowest possible level (IDPD). DPD state is entered by
writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop. The data in Memory Space is
lost, (becomes invalid without refresh) during DPD state. Driving CS# LOW then HIGH will cause the device to exit DPD state. Also,
POR, or a hardware reset will cause the device to exit DPD state. Returning to STANDBY state requires tEXTDPD time. Returning to
STANDBY state following a POR requires tVCS time, as with any other POR. Following the exit from DPD due to any of these events,
the device is in the same state as following POR.
Figure 17. Enter DPD Transaction
CS#
C K#, CK
RW DS
H ig h: 2 X L ate n cy C ou n t
Lo w : 1X L ate ncy C ou n t
t D P D IN
D Q [7 :0]
CM D
[7 :0]
CMD
[7:0 ]
ADR
[3 1:24 ]
ADR
[2 3:1 6]
ADR
[15 :8 ]
C om m a n d - A dd re ss
(H ost d rive s D Q [7:0], M em ory drive s R W D S)
ADR
[7:0 ]
RG
[15:8 ]
RG
[7:0 ]
W rite D a ta
C R 0 V a lu e
E nte r D e e p P o w e r D o w n
t D P D IN
D PD
Figure 18. Exit DPD Transaction
CS#
tCSDPD
tEXTDPD
Table 16. Deep Power Down Timing Parameters
Parameter
Description
tDPDIN
Deep Power Down CR0[15] = 0 register write to DPD power level
tCSDPD
CS# Pulse Width to Exit DPD
tEXTDPD
CS# Exit Deep Power Down to Standby wakeup time
Document Number: 002-24692 Rev. *G
Min
Max
Unit
−
3
µs
200
3000
ns
−
150
µs
Page 26 of 51
S27KL0642/S27KS0642
Electrical Specifications
Absolute Maximum Ratings[44]
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
−65 °C to +150 °C
−65 °C to +115 °C
Voltage with Respect to Ground
−0.5V to +(VCC + 0.5 V)
All signals[42]
Output Short Circuit Current[43]
100 mA
−0.5 V to +4.0 V
VCC, VCCQ
Electrostatic Discharge Voltage:
Human Body Model (JEDEC Std JESD22-A114-B)
2000 V
Charged Device Model (JEDEC Std JESD22-C101-A)
500 V
Input Signal Overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage transitions, inputs or I/Os
may negative overshoot VSS to −1.0 V or positive overshoot to VCC +1.0 V, for periods up to 20 ns.
Figure 19. Maximum Negative Overshoot Waveform
VSSQ to VCCQ
- 1.0V
≤ 20 ns
Figure 20. Maximum Positive Overshoot Waveform
≤ 20 ns
VCCQ + 1.0V
VSSQ to VCCQ
Notes
42. Minimum DC voltage on input or I/O signal is -1.0 V. During voltage transitions, input or I/O signals may undershoot VSS to -1.0 V for periods of up to 20 ns. See
Figure 19. Maximum DC voltage on input or I/O signals is VCC +1.0 V. During voltage transitions, input or I/O signals may overshoot to VCC +1.0 V for periods up
to 20 ns. See Figure 20.
43. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
44. Stresses above those listed under Absolute Maximum Ratings[44] on page 27 may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device
to absolute maximum rating conditions for extended periods may affect device reliability.
Document Number: 002-24692 Rev. *G
Page 27 of 51
S27KL0642/S27KS0642
Latch-up Characteristics
Latch-up Specification[45]
Description
Min
Max
Unit
Input voltage with respect to VSSQ on all input only connections
−1.0
VCCQ + 1.0
V
Input voltage with respect to VSSQ on all I/O connections
−1.0
VCCQ + 1.0
V
VCCQ Current
−100
+100
mA
Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
Temperature Ranges
Parameter
Ambient Temperature
Symbol
TA
Spec
Device
Unit
Min
Max
Industrial (I)
−40
85
°C
Industrial Plus (V)
−40
105
°C
Automotive, AEC-Q100 Grade 3 (A)
−40
85
°C
Automotive, AEC-Q100 Grade 2 (B)
−40
105
°C
Power Supply Voltages
Description
Min
Max
Unit
1.8 V VCC Power Supply
1.7
2.0
V
3.0 V VCC Power Supply
2.7
3.6
V
Note
45. Excludes power supplies VCC/VCCQ. Test conditions: VCC = VCCQ, one connection at a time tested, connections not being tested are at VSS.
Document Number: 002-24692 Rev. *G
Page 28 of 51
S27KL0642/S27KS0642
DC Characteristics
Table 17. DC Characteristics (CMOS Compatible)
Parameter
Description
Test Conditions
64 Mb
Min
Typ[46]
Max
Unit
ILI1
Input Leakage Current
3.0 V Device Reset Signal High Only
VIN = VSS to VCC,
VCC = VCC max
-
-
−0.1
µA
ILI2
Input Leakage Current
1.8 V Device Reset Signal High Only
VIN = VSS to VCC,
VCC = VCC max
-
-
−0.1
µA
ILI3
Input Leakage Current
VIN = VSS to VCC,
3.0 V Device Reset Signal Low Only[47] VCC = VCC max
-
-
+15.0
µA
ILI4
Input Leakage Current
VIN = VSS to VCC,
1.8 V Device Reset Signal Low Only[47] VCC = VCC max
-
-
+15.0
µA
CS# = VSS, @200 MHz,
VCC = 2.0V
-
15
25
mA
CS# = VSS, @166 MHz,
VCC = 3.6V
-
15
28
mA
CS# = VSS, @200 MHz,
VCC = 3.6V
-
15
30
mA
CS# = VSS, @200 MHz,
VCC = 2.0V
-
15
25
mA
CS# = VSS, @166 MHz,
VCC = 3.6V
-
15
28
mA
CS# = VSS, @200 MHz,
VCC = 3.6V
-
15
30
mA
CS# = VCC, VCC = 2.0 V; Full Array
-
80
220
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/2 Array
-
-
200
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/4 Array
-
-
180
µA
VCC Standby Current (−40 °C to +85 °C) CS# = VCC, VCC = 2.0 V; Bottom 1/8 Array
-
-
170
µA
CS# = VCC, VCC = 2.0 V; Top 1/2 Array
-
-
200
µA
CS# = VCC, VCC = 2.0 V; Top 1/4 Array
-
-
180
µA
ICC1
ICC2
VCC Active Read Current
VCC Active Write Current
ICC4I
CS# = VCC, VCC = 2.0 V; Top 1/8 Array
-
-
170
µA
CS# = VCC, VCC = 3.6 V; Full Array
-
90
250
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/2 Array
-
-
230
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/4 Array
-
-
200
µA
VCC Standby Current (−40 °C to +85 °C) CS# = VCC, VCC = 3.6 V; Bottom 1/8 Array
-
-
190
µA
CS# = VCC, VCC = 3.6 V; Top 1/2 Array
-
-
230
µA
CS# = VCC, VCC = 3.6 V; Top 1/4 Array
-
-
200
µA
CS# = VCC, VCC = 3.6 V; Top 1/8 Array
-
-
190
µA
Notes
46. Not 100% tested.
47. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.
Document Number: 002-24692 Rev. *G
Page 29 of 51
S27KL0642/S27KS0642
Table 17. DC Characteristics (CMOS Compatible) (Continued)
Parameter
Description
Test Conditions
64 Mb
Unit
Min
Typ[46]
Max
CS# = VCC, VCC = 2.0 V; Full Array
-
80
330
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/2 Array
-
-
300
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/4 Array
-
-
270
µA
VCC Standby Current (−40 °C to +105 °C) CS# = VCC, VCC = 2.0 V; Bottom 1/8 Array
-
-
250
µA
CS# = VCC, VCC = 2.0 V; Top 1/2 Array
-
-
300
µA
CS# = VCC, VCC = 2.0 V; Top 1/4 Array
-
-
270
µA
CS# = VCC, VCC = 2.0 V; Top 1/8 Array
-
-
250
µA
CS# = VCC, VCC = 3.6 V; Full Array
-
90
360
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/2 Array
-
-
330
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/4 Array
-
-
290
µA
VCC Standby Current (−40 °C to +105 °C) CS# = VCC, VCC = 3.6 V; Bottom 1/8 Array
-
-
270
µA
CS# = VCC, VCC = 3.6 V; Top 1/2 Array
-
-
330
µA
CS# = VCC, VCC = 3.6 V; Top 1/4 Array
-
-
290
µA
CS# = VCC, VCC = 3.6 V; Top 1/8 Array
-
-
270
µA
-
-
1
mA
ICC4P
ICC5
Reset Current
CS# = VCC, RESET# = VSS,
VCC = VCC max
ICC6I
Active Clock Stop Current (−40 °C to
+85 °C)
CS# = VSS, RESET# = VCC,
VCC = VCC max
-
5
8
mA
ICC6IP
Active Clock Stop Current (−40 °C to
+105 °C)
CS# = VSS, RESET# = VCC,
VCC = VCC max
-
8
12
mA
VCC Current during power up[46]
CS# = VCC, VCC = VCC max,
VCC = VCCQ = 2.0V or 3.6 V
-
-
35
mA
ICC7
IDPD[47]
Deep Power Down Current 3.0 V (−40 °C
CS# = VCC, VCC = 3.6V
to +85 °C)
-
-
12
µA
IDPD[47]
Deep Power Down Current 1.8 V (−40 °C
CS# = VCC, VCC = 2.0V
to +85 °C)
-
-
10
µA
IDPD[47]
Deep Power Down Current 3.0 V (−40 °C
CS# = VCC, VCC = 3.6V
to +105 °C)
-
-
15
µA
IDPD[47]
Deep Power Down Current 1.8 V (−40 °C
CS# = VCC, VCC = 2.0V
to +105 °C)
-
-
12
µA
Notes
46. Not 100% tested.
47. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.
Document Number: 002-24692 Rev. *G
Page 30 of 51
S27KL0642/S27KS0642
Table 17. DC Characteristics (CMOS Compatible) (Continued)
Parameter
Description
Hybrid Sleep Current 3.0 V (−40 °C to
+85 °C)
Hybrid Sleep Current 3.0 V (−40 °C to
+85 °C)
IHS[47]
Hybrid Sleep Current 3.0 V (−40 °C to
+105 °C)
Hybrid Sleep Current 3.0 V (−40 °C to
+105 °C)
Test Conditions
64 Mb
Unit
Min
Typ[46]
Max
CS# = VCC, VCC = 2.0 V; Full Array
-
25
200
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/2 Array
-
-
170
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/4 Array
-
-
150
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/8 Array
-
-
140
µA
CS# = VCC, VCC = 2.0 V; Top 1/2 Array
-
-
170
µA
CS# = VCC, VCC = 2.0 V; Top 1/4 Array
-
-
150
µA
CS# = VCC, VCC = 2.0 V; Top 1/8 Array
-
-
140
µA
CS# = VCC, VCC = 3.6 V; Full Array
-
35
230
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/2 Array
-
-
200
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/4 Array
-
-
170
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/8 Array
-
-
150
µA
CS# = VCC, VCC = 3.6 V; Top 1/2 Array
-
-
200
µA
CS# = VCC, VCC = 3.6 V; Top 1/4 Array
-
-
170
µA
CS# = VCC, VCC = 3.6 V; Top 1/8 Array
-
-
150
µA
CS# = VCC, VCC = 2.0 V; Full Array
-
25
300
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/2 Array
-
-
270
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/4 Array
-
-
240
µA
CS# = VCC, VCC = 2.0 V; Bottom 1/8 Array
-
-
210
µA
CS# = VCC, VCC = 2.0 V; Top 1/2 Array
-
-
270
µA
CS# = VCC, VCC = 2.0 V; Top 1/4 Array
-
-
240
µA
CS# = VCC, VCC = 2.0 V; Top 1/8 Array
-
-
210
µA
CS# = VCC, VCC = 3.6 V; Full Array
-
35
330
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/2 Array
-
-
300
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/4 Array
-
-
260
µA
CS# = VCC, VCC = 3.6 V; Bottom 1/8 Array
-
-
250
µA
CS# = VCC, VCC = 3.6 V; Top 1/2 Array
-
-
300
µA
CS# = VCC, VCC = 3.6 V; Top 1/4 Array
-
-
260
µA
-
-
250
µA
VIL
Input Low Voltage
−
CS# = VCC, VCC = 3.6 V; Top 1/8 Array
−0.15 x VCCQ
−
0.30 x VCCQ
V
VIH
Input High Voltage
−
0.70 x VCCQ
−
1.15 x VCCQ
V
VOL
Output Low Voltage
IOL = 100 µA for DQ[7:0]
−
−
0.20
V
VOH
Output High Voltage
IOH = 100 µA for DQ[7:0]
VCCQ-0.20
−
−
V
Notes
46. Not 100% tested.
47. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.
Document Number: 002-24692 Rev. *G
Page 31 of 51
S27KL0642/S27KS0642
Capacitance Characteristics
Table 18. 1.8 V Capacitive Characteristics[48, 49, 50]
Description
Parameter
64 Mb
Unit
Max
Input Capacitance (CK, CK#, CS#)
CI
3.0
pF
Delta Input Capacitance (CK, CK#)
CID
0.25
pF
Output Capacitance (RWDS)
CO
3.0
pF
IO Capacitance (DQx)
CIO
3.0
pF
CIOD
0.25
pF
IO Capacitance Delta (DQx)
Table 19. 3.0 V Capacitive Characteristics[48, 49, 50]
Description
Parameter
64 Mb
Unit
Max
Input Capacitance (CK, CK#, CS#)
CI
3.0
pF
Delta Input Capacitance (CK, CK#)
CID
0.25
pF
Output Capacitance (RWDS)
CO
3.0
pF
IO Capacitance (DQx)
IO Capacitance Delta (DQx)
CIO
3.0
pF
CIOD
0.25
pF
Table 20. Thermal Resistance
Parameter[51]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
24-ball FBGA
Package
Unit
66.7
°C/W
37
°C/W
Notes
48. These values are guaranteed by design and are tested on a sample basis only.
49. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VCC, VCCQ are applied and all other
signals (except the signal under test) floating. DQ’s should be in the high impedance state.
50. Note that the capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance values to allow for signal propagation time matching in the
system. The capacitance value for CS# is not as critical because there are no critical timings between CS# going active (LOW) and data being presented on the DQs
bus.
51. This parameter is guaranteed by characterization; not tested in production.
Document Number: 002-24692 Rev. *G
Page 32 of 51
S27KL0642/S27KS0642
Power-Up Initialization
HyperRAM products include an on-chip voltage sensor used to launch the power-up initialization process. VCC and VCCQ must be
applied simultaneously. When the power supply reaches a stable level at or above VCC(min), the device will require tVCS time to
complete its self-initialization process.
The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min) is reached during
power-up, and then CS# must remain HIGH for a further delay of tVCS. A simple pull-up resistor from VCCQ to Chip Select (CS#) can
be used to insure safe and proper power-up.
If RESET# is LOW during power up, the device delays start of the tVCS period until RESET# is HIGH. The tVCS period is used
primarily to perform refresh operations on the DRAM array to initialize it.
When initialization is complete, the device is ready for normal operation.
Figure 21. Power-up with RESET# HIGH
Vcc_VccQ
VCC Minimum
Device
Access Allowed
tVCS
CS#
RESET#
Figure 22. Power-up with RESET# LOW
Vcc_VccQ
VCC Minimum
CS#
Device
Access Allowed
tVCS
RESET#
Table 21. Power Up and Reset Parameters[52, 53, 54]
Parameter
Min
Max
Unit
VCC
1.8 V VCC Power Supply
Description
1.7
2.0
V
VCC
3.0 V VCC Power Supply
2.7
3.6
V
tVCS
VCC and VCCQ ≥ minimum and RESET# HIGH to first
access
−
150
µs
Notes
52. Bus transactions (read and write) are not allowed during the power-up reset time (tVCS).
53. VCCQ must be the same voltage as VCC.
54. VCC ramp rate may be non-linear.
Document Number: 002-24692 Rev. *G
Page 33 of 51
S27KL0642/S27KS0642
Power Down
HyperRAM devices are considered to be powered-off when the array power supply (VCC) drops below the VCC Lock-Out voltage
(VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or equal to VCC. At the VLKO level, the
HyperRAM device will have lost configuration or array data.
VCC must always be greater than or equal to VCCQ (VCC ≥ VCCQ).
During Power-Down or voltage drops below VLKO, the array power supply voltages must also drop below VCC Reset (VRST) for a
Power Down period (tPD) for the part to initialize correctly when the power supply again rises to VCC minimum. See Figure 23.
If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is again above VCC
minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no assurance that the POR process
will be performed. In this case, a hardware reset will be required ensure the HyperBus device is properly initialized.
Figure 23. Power Down or Voltage Drop
VCC (Max)
VCC
No Device Access Allowed
VCC (Min)
tVCS
VLKO
Device Access
Allowed
VRST
t PD
Time
The following section describes the HyperRAM device-dependent aspects of power down specifications.
Table 22. 1.8 V Power-Down Voltage and Timing[55]
Symbol
Min
Max
Unit
VCC
VCC Power Supply
1.7
2.0
V
VLKO
VCC Lock-out below which re-initialization is required
1.5
−
V
VRST
VCC Low Voltage needed to ensure initialization will occur
0.7
−
V
Duration of VCC ≤ VRST
50
−
µs
tPD
Parameter
Table 23. 3.0 V Power-Down Voltage and Timing[55]
Symbol
Min
Max
Unit
VCC
VCC Power Supply
2.7
3.6
V
VLKO
VCC Lock-out below which re-initialization is required
2.4
−
V
VRST
VCC Low Voltage needed to ensure initialization will occur
0.7
−
V
Duration of VCC ≤ VRST
50
−
µs
tPD
Parameter
Note
55. VCC ramp rate can be non-linear.
Document Number: 002-24692 Rev. *G
Page 34 of 51
S27KL0642/S27KS0642
Hardware Reset
The RESET# input provides a hardware method of returning the device to the STANDBY state.
During tRPH the device will draw ICC5 current. If RESET# continues to be held LOW beyond tRPH, the device draws CMOS standby
current (ICC4). While RESET# is LOW (during tRP), and during tRPH, bus transactions are not allowed.
A hardware reset will do the following:
■
Cause the configuration registers to return to their default values
■
Halt self-refresh operation while RESET# is LOW - memory array data is considered as invalid
■
Force the device to exit the Hybrid Sleep state
■
Force the device to exit the Deep Power Down state
After RESET# returns HIGH, the self-refresh operation will resume. Because self-refresh operation is stopped during RESET# LOW,
and the self-refresh row counter is reset to its default value, some rows may not be refreshed within the required array refresh interval
per Table 13. This may result in the loss of DRAM array data during or immediately following a hardware reset. The host system should
assume DRAM array data is lost after a hardware reset and reload any required data.
Figure 24. Hardware Reset Timing Diagram
tRP
RESET#
tRH
tRPH
CS#
Table 24. Power Up and Reset Parameters
Parameter
Description
Min
Max
Unit
tRP
RESET# Pulse Width
200
−
ns
tRH
Time between RESET# (HIGH) and CS# (LOW)
200
−
ns
tRPH
RESET# LOW to CS# LOW
400
−
ns
Document Number: 002-24692 Rev. *G
Page 35 of 51
S27KL0642/S27KS0642
Timing Specifications
The following section describes HyperRAM device dependent aspects of timing specifications.
Key to Switching Waveforms
Valid_High_or_Low
High_to_Low_Transition
Low_to_High_Transition
Invalid
High_Impedance
AC Test Conditions
Figure 25. Test Setup
Device
Under
Test
CL
Table 25. Test Specification[57]
Parameter
All Speeds
Unit
15
pF
1.13
V/ns
Output Load Capacitance, CL
Minimum Input Rise and Fall Slew Rates (1.8 V)
[56]
Minimum Input Rise and Fall Slew Rates (3.0 V)
[56]
2.06
V/ns
0.0-VCCQ
V
Input timing measurement reference levels
VCCQ/2
V
Output timing measurement reference levels
VCCQ/2
V
Input Pulse Levels
Figure 26. Input Waveforms and Measurement Levels[58]
VccQ
Input VccQ / 2
Measurement Level
VccQ / 2 Output
Vss
Notes
56. All AC timings assume this input slew rate.
57. Input and output timing is referenced to VCCQ/2 or to the crossing of CK/CK#.
58. Input timings for the differential CK/CK# pair are measured from clock crossings.
Document Number: 002-24692 Rev. *G
Page 36 of 51
S27KL0642/S27KS0642
CLK Characteristics
Figure 27. Clock Characteristics
tCK
tCKHP
tCKHP
CK#
VIX (Max)
VCCQ / 2
VIX (Min)
CK
Table 26. Clock Timings[59, 60, 61]
Parameter
CK Period
Symbol
200 MHZ
Min
166 MHZ
Max
Min
Max
Unit
tCK
5
–
6
–
ns
CK Half Period - Duty Cycle
tCKHP
0.45
0.55
0.45
0.55
tCK
CK Half Period at Frequency
Min = 0.45 tCK Min
Max = 0.55 tCK Min
tCKHP
2.25
2.75
2.7
3.3
ns
Notes
59. Clock jitter of ±5% is permitted.
60. Minimum Frequency (Maximum tCK) is dependent upon maximum CS# LOW time (tCSM), Initial Latency and Burst Length.
61. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).
Document Number: 002-24692 Rev. *G
Page 37 of 51
S27KL0642/S27KS0642
Figure 28. Differential Clock (CK/CK#) Input Swing
Differential Input Voltage (CK-CK#)
VID (AC) (min)
VID (DC) (min)
0
half cycle
-VID (DC) (min)
-VID (AC) (min)
time
Table 27. Clock AC/DC Electrical Characteristics[62, 63]
Parameter
Symbol
Min
Max
Unit
VIN
–0.3
VCCQ+ 0.3
V
DC Input Differential Voltage
VID(DC)
VCCQ × 0.4
VCCQ+ 0.6
V
AC Input Differential Voltage
VID(AC)
VCCQ × 0.6
VCCQ + 0.6
V
VIX
VCCQ × 0.4
VCCQ x 0.6
V
DC Input Voltage
AC Differential Crossing Voltage
Notes
62. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
63. The value of VIX is expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of VCCQ.
Document Number: 002-24692 Rev. *G
Page 38 of 51
S27KL0642/S27KS0642
AC Characteristics
Read Transactions
Table 28. HyperRAM Specific Read Timing Parameters
Parameter
Chip Select High Between Transactions - 1.8V
Chip Select High Between Transactions - 3.0V
HyperRAM Read-Write Recovery Time - 1.8V
HyperRAM Read-Write Recovery Time - 3.0V
Chip Select Setup to next CK Rising Edge
Data Strobe Valid - 1.8V
Data Strobe Valid - 3.0V
Input Setup - 1.8V
Input Setup - 3.0V
Input Hold - 1.8V
Input Hold - 3.0V
HyperRAM Read Initial Access Time - 1.8V
HyperRAM Read Initial Access Time- 3.0V
Clock to DQs Low Z
CK transition to DQ Valid - 1.8V
CK transition to DQ Valid - 3.0V
CK transition to DQ Invalid - 1.8V
CK transition to DQ Invalid - 3.0V
Data Valid (tDV min = the lesser of: tCKHP min - tCKD max + tCKDI max)
or tCKHP min - tCKD min + tCKDI min) - 1.8V
Data Valid (tDV min = the lesser of: tCKHP min - tCKD max + tCKDI max) or
tCKHP min - tCKD min + tCKDI min) - 3.0V
CK transition to RWDS Valid - 1.8V
CK transition to RWDS Valid - 3.0V
RWDS transition to DQ Valid - 1.8V
RWDS transition to DQ Valid - 3.0V
RWDS transition to DQ Invalid - 1.8V
RWDS transition to DQ Invalid - 3.0V
Chip Select Hold After CK Falling Edge
Chip Select Inactive to RWDS High-Z - 1.8V
Chip Select Inactive to RWDS High-Z - 3.0V
Chip Select Inactive to DQ High-Z - 1.8V
Chip Select Inactive to DQ High-Z - 3.0V
Refresh Time - 1.8V
Refresh Time - 3.0V
Symbol
tCSHI
tRWR
tCSS
tDSV
tIS
tIH
tACC
tDQLZ
tCKD
tCKDI
200 MHz
166 MHz
Min
Max
Min
Max
6
–
6
–
6
–
6
–
35
–
36
–
35
–
36
–
4.0
–
3
–
–
5.0
–
12
–
6.5
–
12
0.5
–
0.6
–
0.5
–
0.6
–
0.5
–
0.6
–
0.5
–
0.6
–
35
–
36
–
35
–
36
–
0
–
0
–
1
5.0
1
5.5
1
6.5
1
7
0
4.2
0
4.6
0.5
5.7
0.5
5.6
1.45
–
1.8
–
tDV[64]
tCKDS
tDSS
tDSH
tCSH
tDSZ
tOZ
tRFH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.45
–
1.3
–
–
5.0
1
5.5
–
6.5
1
7
–0.4
+0.4
–0.45
+0.45
–0.4
+0.4
–0.8
+0.8
–0.4
+0.4
–0.45
+0.45
–0.4
+0.4
–0.8
+0.8
0
–
0
–
–
5.0
–
6
–
6.5
–
7
–
5
–
6
–
6.5
–
7
35
–
36
–
35
–
36
–
ns
ns
ns
ns
ns
ns
ns
Note
64. Refer to Figure 39 for data valid timing.
Document Number: 002-24692 Rev. *G
Page 39 of 51
S27KL0642/S27KS0642
Table 28. HyperRAM Specific Read Timing Parameters (Continued)
Parameter
Symbol
CK transition to RWDS Low @CA phase @Read - 1.8V
tCKDSR
CK transition to RWDS Low @CA phase @Read - 3.0V
200 MHz
166 MHz
Min
Max
Min
Max
1
5.5
1
5.5
1
7
1
7
Unit
ns
Figure 29. Read Timing Diagram — No Additional Latency Required
t CSHI
t CSM
CS#
t CSS
t CSH
t RWR =Read Write Recovery
t ACC = Access
t CSS
CK , CK#
t DSV
4 cycle latency
t CKDS
t DSZ
High = 2x Latency Count
Low = 1x Latency Count
RWDS
t DSS
t IS
DQ[7:0]
t IH
47:40 39:32 31:24 23:16 15:8
t DQLZ
Command-Address
t CKD
Dn
A
7:0
RWDS and Data
are edge aligned
Host drives DQ[7:0] and Memory drives RWDS
t OZ
t DSH
Dn
B
Dn+1
A
Dn+1
B
Memory drives DQ[7:0]
and RWDS
Figure 30. Read Timing Diagram — With Additional Latency Required
CS#
tRWR =Read Write Recovery
Additional Latency
tACC = Access
4 cycle latency 1
4 cycle latency 2
CK , CK#
tDSV
tCKDS
RWDS
High = 2x Latency Count
Low = 1x Latency Count
DQ[7:0]
47:40 39:32 31:24 23:16 15:8
tCKDS
tCKD
7:0
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Document Number: 002-24692 Rev. *G
Dn
A
Dn
B
Dn+1
A
Dn+1
B
Memory drives DQ[7:0]
and RWDS
Page 40 of 51
S27KL0642/S27KS0642
Write Transactions
Table 29. Write Timing Parameters
Parameter
200 MHz
Symbol
166 MHz
Min
Max
Min
Max
Unit
Read-Write Recovery Time
tRWR
35
−
36
−
ns
Access Time
tACC
35
−
36
−
ns
Refresh Time
tRFH
35
−
36
−
ns
Chip Select Maximum Low Time (85 °C)
tCSM
−
4
−
4
µs
Chip Select Maximum Low Time (105 °C)
tCSM
−
1
−
1
µs
RWDS Data Mask Valid
tDMV
0
−
0
−
µs
Figure 31. Write Timing Diagram — No Additional Latency
t CSHI
t CSM
CS#
t CSS
t CSH
t RWR =Read Write Recovery
t ACC = Access
t CSS
CK, CK#
t DSV
RWDS
4 cycle latency
t DSZ
High = 2x Latency Count
Low = 1x Latency Count
t IS
t DMV
t IH
t IS
t IS
DQ[7:0]
47:40
t IH
39:32
31:24
t IH
23:16
15:8
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Document Number: 002-24692 Rev. *G
Dn
A
7:0
CK and Data
are center aligned
Dn
B
Dn+1
A
Dn+1
B
Host drives DQ[7:0]
and RWDS
Page 41 of 51
S27KL0642/S27KS0642
Timing Reference Levels
Figure 32. DDR Input Timing Reference Levels
tCK
VCCQ
CK, CK#
VSSQ
tIS
DQ[7:0]
tIH
tIS
tIH
VCCQ
VIH(min)
VIL(max)
VSSQ
Figure 33. DDR Output Timing Reference Levels
tSCK
VCCQ
RWDS
VSSQ
tDSS
DQ[7:0]
VOH(min)
VOL(max)
Document Number: 002-24692 Rev. *G
tDSH
VCCQ
VSSQ
Page 42 of 51
S27KL0642/S27KS0642
Physical Interface
FBGA 24-Ball 5 x 5 Array Footprint
HyperRAM devices are provided in Fortified Ball Grid Array (FBGA), 1 mm pitch, 24-ball, 5 × 5 ball array footprint, with 6mm x 8mm
body.
Figure 34. 24-Ball FBGA, 6 × 8 mm, 5 × 5 Ball Footprint, Top View
1
2
3
4
5
RFU
CS#
CK#
CK
Vss
Vcc
RFU
VssQ
RFU
RWDS
DQ2
RFU
VccQ
DQ1
DQ0
DQ3
DQ4
DQ7
DQ6
DQ5
VccQ
VssQ
A
RESET# RFU
B
C
D
E
Document Number: 002-24692 Rev. *G
Page 43 of 51
S27KL0642/S27KS0642
Package Diagrams
Figure 35. Fortified Ball Grid Array 24-ball 6 × 8 × 1.0 mm (VAA024)
NOTES:
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
1.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
4.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
A
-
-
1.00
A1
0.20
-
-
D
8.00 BSC
E
6.00 BSC
D1
4.00 BSC
E1
4.00 BSC
MD
5
ME
5
N
24
b
0.35
0.40
eE
1.00 BSC
eD
1.00 BSC
SD
0.00 BSC
SE
0.00 BSC
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
0.45
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
8.
9.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION
OR OTHER MEANS.
10.
Document Number: 002-24692 Rev. *G
JEDEC SPECIFICATION NO. REF: N/A
002-15550 *A
Page 44 of 51
S27KL0642/S27KS0642
DDR Center-Aligned Read Strobe (DCARS) Functionality
The HyperRAM device offers an optional feature that enables independent skewing (phase shifting) of the RWDS signal with respect
to the read data outputs. This feature is provided in certain devices, based on the Ordering Part Number (OPN).
When the DCARS feature is provided, a second differential Phase Shifted Clock input PSC/PSC# is used as the reference for
RWDS edges instead of CK/CK#. The second clock is generally a copy of CK/CK# that is phase shifted 90 degrees to place the
RWDS edges centered within the DQ signals valid data window. However, other degrees of phase shift between CK/CK# and
PSC/PSC# may be used to optimize the position of RWDS edges within the DQ signals valid data window so that RWDS provides
the desired amount of data setup and hold time in relation to RWDS edges.
PSC/PSC# is not used during a write transaction. PSC and PSC# may be driven LOW and HIGH respectively or, both may be driven
LOW during write transactions.
The PSC/PSC# is used in HyperBus devices. If single-ended mode is selected, then PSC# must be driven LOW but must not be left
floating (leakage concerns).
HyperRAM Products with DCARS Signal Descriptions
Figure 36. HyperBus Product with DCARS Signal Diagram
RESET#
CS#
CK
CK#
PSC
PSC#
VCC
VCCQ
DQ[7:0]
RWDS
VSS
VSSQ
Table 30. Signal Descriptions
Symbol
Type
Description
CS#
Input
Chip Select. HyperBus transactions are initiated with a HIGH to LOW transition. HyperBus transactions are
terminated with a LOW to HIGH transition.
CK, CK#
Input
Differential Clock. Command, address, and data information is output with respect to the crossing of the CK
and CK# signals. Use of differential clock is optional.
Single Ended Clock. CK# is not used, only a single ended CK is used.
The clock is not required to be free-running.
Input
Phase Shifted Clock. PSC/PSC# allows independent skewing of the RWDS signal with respect to the
CK/CK# inputs. If the CK/CK# (differential mode) is configured, then PSC/PSC# are used. Otherwise, only
PSC is used (Single Ended).
PSC (and PSC#) may be driven HIGH and LOW respectively or both may be driven LOW during write
transactions.
RWDS
Output
Read-Write Data Strobe. Data bytes output during read transactions are aligned with RWDS based on the
phase shift from CK, CK# to PSC, PSC#. PSC, PSC# cause the transitions of RWDS, thus the phase shift
from CK, CK# to PSC, PSC# is used to place RWDS edges within the data valid window. RWDS is an input
during write transactions to function as a data mask. At the beginning of all bus transactions RWDS is an
output and indicates whether additional initial latency count is required
(1 = additional latency count, 0 = no additional latency count).
DQ[7:0]
Input/Output
Data Input/Output. CA/Data information is transferred on these DQs during Read and Write transactions.
RESET#
Input
Hardware RESET. When LOW, the device will self initialize and return to the idle state. RWDS and DQ[7:0]
are placed into the HIGH-Z state when RESET# is LOW. RESET# includes a weak pull-up, if RESET# is left
unconnected it will be pulled up to the HIGH state.
VCC
Power Supply
Array Power.
VCCQ
Power Supply
Input/Output Power.
VSS
Power Supply
Array Ground.
VSSQ
Power Supply
Input/Output Ground.
PSC, PSC#
Document Number: 002-24692 Rev. *G
Page 45 of 51
S27KL0642/S27KS0642
HyperRAM Products with DCARS — FBGA 24-ball, 5 x 5 Array Footprint
Figure 37. 24-ball FBGA, 5 × 5 Ball Footprint, Top View
1
2
3
4
RFU
CS#
CK#
CK
Vss
Vcc
PSC
VssQ
RFU
RWDS
DQ2
PSC#
VccQ
DQ1
DQ0
DQ3
DQ4
DQ7
DQ6
DQ5
VccQ
VssQ
5
A
RESET# RFU
B
C
D
E
HyperRAM Memory with DCARS Timing
The illustrations and parameters shown here are only those needed to define the DCARS feature and show the relationship between
the Phase Shifted Clock, RWDS, and data.
Figure 38. HyperRAM Memory DCARS Timing Diagram[65, 66, 67]
t CSHI
CS#
t CSH
t CSS
t ACC = Access time
t CSS
CK , CK#
4 cycle latency
PSC , PSC#
t DSV
t PSCRWDS
t DSZ
High = 2x Latency Count
Low = 1x Latency Count
RWDS
t IS
DQ[7:0]
t IH
47:40 39:32 31:24 23:16 15:8
t DQLZ
Dn
A
7:0
Command-Address
t CKD
RWDS aligned
by PSC
t OZ
Dn
B
Dn+1
A
Dn+1
B
Memory drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Notes
65. Transactions must be initiated with CK = LOW and CK# = HIGH. CS# must return HIGH before a new transaction is initiated.
66. The memory drives RWDS during read transactions.
67. This example demonstrates a latency code setting of four clocks and no additional initial latency required.
Document Number: 002-24692 Rev. *G
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S27KL0642/S27KS0642
Figure 39. DCARS Data Valid Timing[69, 70, 70]
CS#
t CKHP
tCSH
tCSS
CK ,CK#
PSC , PSC#
t IS
tPSCRWDS
t IH
tDSZ
RWDS
tCKDI
tCKD
tDQLZ
tDV
tCKD
Dn
A
DQ[7:0]
tOZ
Dn
B
Dn+1
A
Dn+1
B
RWDS and Data are driven by the memory
Table 31. DCARS Read Timing
Parameter
Symbol
Input Setup - CK/CK# setup w.r.t PSC/PSC#
(edge to edge)
CK Half Period - Duty Cycle
(edge to edge)
200 MHZ
166 MHZ
Unit
Min
Max
Min
Max
tIS
0.5
–
0.6
–
ns
tIH
0.5
–
0.6
–
ns
HyperRAM PSC transition to RWDS transition
tPSCRWDS
–
5
–
6.5
ns
Time delta between CK to DQ valid and PSC
to RWDS[68]
tPSCRWDS - tCKD
–1.0
+0.5
–1.0
+0.5
ns
Notes
68. Sampled, not 100% tested.
69. This figure shows a closer view of the data transfer portion of Figure 36 on page 45 in order to more clearly show the Data Valid period as affected by clock jitter and
clock to output delay uncertainty.
70. The delay (phase shift) from CK to PSC is controlled by the HyperBus master interface (Host) and is generally between 40 and 140 degrees in order to place the
RWDS edge within the data valid window with sufficient set-up and hold time of data to RWDS. The requirements for data set-up and hold time to RWDS are
determined by the HyperBus master interface design and are not addressed by the HyperBus slave timing parameters.
71. The HyperBus timing parameters of tCKD, and tCKDI define the beginning and end position of the data valid period. The tCKD and tCKDI values track together (vary by
the same ratio) because RWDS and Data are outputs from the same device under the same voltage and temperature conditions.
Document Number: 002-24692 Rev. *G
Page 47 of 51
S27KL0642/S27KS0642
Ordering Information
Ordering Part Number
The ordering part number is formed by a valid combination of the following:
S27KS
064
2
DP
B
H
I
02
0
Packing Type
0 = Tray
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
02 = Standard 6 × 8 × 1.0 mm package (VAA024)
03 = DDR center-aligned Read Strobe (DCARS) 6 × 8 × 1.0 mm package (VAA024)
Temperature Range / Grade
I = Industrial (–40 °C to + 85 °C)
V = Industrial Plus (–40 °C to + 105 °C)
A = Automotive, AEC-Q100 Grade 3 (–40 °C to + 85 °C)
B = Automotive, AEC-Q100 Grade 2 (–40 °C to + 105 °C)
Package Materials
H = Low-Halogen, Pb-free
Package Type
B = 24-ball FBGA, 1.00 mm pitch (5x5 ball footprint)
Speed
GA = 200 MHz
DP = 166 MHz
Device Technology
2 = 38-nm DRAM Process Technology - HyperBus
3 = 38-nm DRAM Process Technology - Octal
Density
064 = 64 Mb
Device Family
S27KS
Cypress Memory 1.8 V-only, HyperRAM Self-refresh DRAM
S27KL
Cypress Memory 3.0 V-only, HyperRAM Self-refresh DRAM
Document Number: 002-24692 Rev. *G
Page 48 of 51
S27KL0642/S27KS0642
Valid Combinations
The Recommended Combinations table lists configurations planned to be available in volume. Table 32 will be updated as new
combinations are released. Contact your local sales representative to confirm availability of specific combinations and to check on
newly released combinations.
Table 32. Valid Combinations — Standard
Device
Family
S27KL
Density Technology
064
Speed
2
DP
Package,
Model Packing
Ordering Part Number
Material, and
Number
Type
Temperature
BHI
02
0
S27KL0642DPBHI020
Package Marking
7KL0642DPHI02
S27KL
064
2
DP
BHI
02
3
S27KL0642DPBHI023
7KL0642DPHI02
S27KL
064
2
GA
BHI
02
0
S27KL0642GABHI020
7KL0642GAHI02
S27KL
064
2
GA
BHI
02
3
S27KL0642GABHI023
7KL0642GAHI02
S27KL
064
2
DP
BHV
02
0
S27KL0642DPBHV020
7KL0642DPHV02
S27KL
064
2
DP
BHV
02
3
S27KL0642DPBHV023
7KL0642DPHV02
S27KS
064
2
GA
BHI
02
0
S27KS0642GABHI020
7KS0642GAHI02
S27KS
064
2
GA
BHI
02
3
S27KS0642GABHI023
7KS0642GAHI02
S27KS
064
2
GA
BHV
02
0
S27KS0642GABHV020
7KS0642GAHV02
S27KS
064
2
GA
BHV
02
3
S27KS0642GABHV023
7KS0642GAHV02
Valid Combinations — Automotive Grade / AEC-Q100
Table 33 list configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table
will be updated as new combinations are released. Contact your local sales representative to confirm availability of specific
combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with
ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Table 33. Valid Combinations — Automotive Grade / AEC-Q100
Device
Family
Density Technology
Speed
Package,
Model Packing
Ordering Part Number Package Marking
Material, and
Number
Type
Temperature
S27KL
064
2
DP
BHA
02
0
S27KL0642DPBHA020
7KL0642DPHA02
S27KL
064
2
DP
BHA
02
3
S27KL0642DPBHA023
7KL0642DPHA02
S27KL
064
2
DP
BHB
02
0
S27KL0642DPBHB020
7KL0642DPHB02
S27KL
064
2
DP
BHB
02
3
S27KL0642DPBHB023
7KL0642DPHB02
S27KL
064
2
GA
BHB
02
0
S27KL0642GABHB020
7KL0642GAHB02
S27KL
064
2
GA
BHB
02
3
S27KL0642GABHB023
7KL0642GAHB02
S27KS
064
2
GA
BHA
02
0
S27KS0642GABHA020 7KS0642GAHA02
S27KS
064
2
GA
BHA
02
3
S27KS0642GABHA023 7KS0642GAHA02
S27KS
064
2
GA
BHB
02
0
S27KS0642GABHB020 7KS0642GAHB02
S27KS
064
2
GA
BHB
02
3
S27KS0642GABHB023 7KS0642GAHB02
Document Number: 002-24692 Rev. *G
Page 49 of 51
S27KL0642/S27KS0642
Revision History
Document Title: S27KL0642/S27KS0642, 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM
Document Number: 002-24692
Rev.
ECN No.
Submission
Date
*F
6713022
11/25/2019
Changed document status to Final.
05/05/2020
Added note in Figure 13.
Updated tCKDS and tCKD in Figure 30.
Updated Hybrid Burst Enable binary in Table 9.
Added Hybrid 128 burst in Table 11.
Fixed typos in Table 12 and Table 27.
Updated parameters in Table 17.
Added Thermal values in Table 20.
Added Figure 32, and Figure 33 in Timing Reference Levels.
Added ESD information in Electrical Specifications.
Added Figure 28 Differential Clock (CK/CK#) Input Swing.
Removed Valid Combinations — DCARS MPNs in Valid Combinations.
Removed Valid Combinations — DCARS Automotive Grade / AEC-Q100 MPNs in Valid
Combinations — Automotive Grade / AEC-Q100.
*G
6869309
Document Number: 002-24692 Rev. *G
Description of Change
Page 50 of 51
S27KL0642/S27KS0642
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Document Number: 002-24692 Rev. *G
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