Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
S29AL008J
8-Mbit (1M × 8-Bit/512K × 16-Bit), 3 V,
Boot Sector Flash
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
Single Power Supply Operation
– Full voltage range: 2.7 to 3.6 volt read and write operations
for battery-powered applications
Manufactured on 110 nm Process Technology
– Fully compatible with 200 nm S29AL008D
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random Electronic
Serial Number accessible through a command sequence
– May be programmed and locked at the factory or by the
customer
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64
Kbyte sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32
Kword sectors (word mode)
Sector Group Protection Features
– A hardware method of locking a sector to prevent any
program or erase operations within that sector
– Sectors can be locked in-system or via programming
equipment
– Temporary Sector Unprotect feature allows code changes
in previously locked sectors
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple
program command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply
Flash
– Superior inadvertent write protection
High Performance
– Access times as fast as 55 ns
– Extended temperature range (–40°C to +125°C)
– Automotive AEC-Q100 Grade 3 (–40 °C to +85 °C)
– Automotive AEC-Q100 Grade 1 (–40 °C to +125 °C)
Ultra Low Power Consumption (typical values at 5 MHz)
– 0.2 µA Automatic Sleep mode current
– 0.2 µA standby mode current
– 7 mA read current
– 20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball Fine-pitch BGA
48-pin TSOP
Software Features
CFI (Common Flash Interface) Compliant
– Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or
program data to, a sector that is not being erased, then
resumes the erase operation
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or
erase cycle completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
WP# input pin
– For boot sector devices: at VIL, protects first or last
16 Kbyte sector depending on boot configuration (top boot
or bottom boot)
Cypress Semiconductor Corporation
Document Number: 002-00778 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 21, 2020
S29AL008J
General Description
The S29AL008J is a 8 Mbit, 3.0 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in
48-ball Fine-pitch BGA (0.8 mm pitch), and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the bytewide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC
supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard
EPROM programmers.
The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The S29AL008J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes.
Cypress Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
Document Number: 002-00778 Rev. *Q
Page 2 of 50
S29AL008J
Contents
Distinctive Characteristics .................................................. 1
1.
Product Selector Guide ............................................... 4
2.
Block Diagram.............................................................. 4
3.
3.1
Connection Diagrams.................................................. 5
Special Handling Instructions......................................... 5
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
4.
Pin Configuration......................................................... 6
12.
Absolute Maximum Ratings....................................... 32
5.
Logic Symbol ............................................................... 6
13.
Operating Ranges ....................................................... 33
6.
6.1
Ordering Information ................................................... 7
S29AL008J Standard Products...................................... 7
14. DC Characteristics...................................................... 34
14.1 CMOS Compatible ........................................................ 34
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
Device Bus Operations................................................ 9
Word/Byte Configuration.............................................. 10
Requirements for Reading Array Data......................... 10
Writing Commands/Command Sequences.................. 10
Program and Erase Operation Status.......................... 10
Standby Mode.............................................................. 10
Automatic Sleep Mode................................................. 11
RESET#: Hardware Reset Pin..................................... 11
Output Disable Mode ................................................... 11
Autoselect Mode .......................................................... 13
Sector Group Protection/Unprotection ......................... 14
Temporary Sector Group Unprotect............................. 15
15.
Test Conditions ........................................................... 35
16.
Key to Switching Waveforms..................................... 35
17.
17.1
17.2
17.3
17.4
17.5
17.6
AC Characteristics...................................................... 36
Read Operations........................................................... 36
Hardware Reset (RESET#)........................................... 37
Word/Byte Configuration (BYTE#) ................................ 38
Erase/Program Operations ........................................... 39
Temporary Sector Group Unprotect.............................. 42
Alternate CE# Controlled Erase/Program Operations .. 43
18.
Erase and Programming Performance ..................... 44
8.
8.1
Secured Silicon Sector Flash Memory Region ....... 17
Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory........................................ 17
Customer Lockable: Secured Silicon Sector NOT Programmed
or Protected at the Factory .......................................... 17
19.
TSOP and BGA Pin Capacitance ............................... 44
General Description ............................................................. 2
8.2
9.
9.1
Common Flash Memory Interface (CFI) ................... 19
Hardware Data Protection............................................ 21
10.
10.1
10.2
10.3
10.4
Command Definitions................................................ 22
Reading Array Data ..................................................... 22
Reset Command .......................................................... 22
Autoselect Command Sequence ................................. 22
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence ................................................... 23
10.5 Word/Byte Program Command Sequence................... 23
10.6 Unlock Bypass Command Sequence .......................... 23
10.7 Chip Erase Command Sequence ................................ 24
10.8 Sector Erase Command Sequence ............................. 25
10.9 Erase Suspend/Erase Resume Commands ................ 25
10.10Command Definitions Table ........................................ 26
Document Number: 002-00778 Rev. *Q
Write Operation Status ............................................... 28
DQ7: Data# Polling ....................................................... 28
RY/BY#: Ready/Busy#.................................................. 29
DQ6: Toggle Bit I .......................................................... 29
DQ2: Toggle Bit II ......................................................... 29
Reading Toggle Bits DQ6/DQ2..................................... 30
DQ5: Exceeded Timing Limits ...................................... 31
DQ3: Sector Erase Timer.............................................. 31
20. Physical Dimensions .................................................. 45
20.1 48-Pin TSOP (18.4 mm × 12.0 mm × 1.2 mm) Package
Outline .......................................................................... 45
20.2 48-Ball VFBGA (8.15 mm x 6.15 mm × 1.00 mm) Package
Outline .......................................................................... 46
21. Revision History.......................................................... 47
Document History Page ..................................................... 47
Sales, Solutions, and Legal Information .......................... 50
Worldwide Sales and Design Support ........................... 50
Products ........................................................................ 50
PSoC® Solutions .......................................................... 50
Cypress Developer Community ..................................... 50
Technical Support ......................................................... 50
Page 3 of 50
S29AL008J
1.
Product Selector Guide
Family Part Number
S29AL008J
Voltage Range: VCC = 2.7-3.6 V
–
70
VCC = 3.0-3.6 V
55
–
Max access time, ns (tACC)
55
70
Max CE# access time, ns (tCE)
55
70
Max CE# access time, ns (tOE)
30
30
Speed Option
Note
See AC Characteristics on page 36 for full specifications.
2. Block Diagram
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WP#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
A0–A18
Document Number: 002-00778 Rev. *Q
Timer
Address Latch
WE#
BYTE#
Input/Output
Buffers
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Page 4 of 50
S29AL008J
3.
Connection Diagrams
Figure 1. 48-pin Standard TSOP (TS048)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Figure 2. 48-ball Fine-pitch BGA (VBK048)
(Top View, Balls Facing Down)
3.1
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
F6
G6
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
BYTE# DQ15/A-1
H6
VSS
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
WP#
A18
NC
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Special Handling Instructions
Special handling is required for Flash Memory products in BGA packages.
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time.
Document Number: 002-00778 Rev. *Q
Page 5 of 50
S29AL008J
4.
Pin Configuration
A0–A18
DQ0–DQ14
DQ15/A-1
BYTE#
19 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
CE#
Chip enable
OE#
Output enable
WE#
Write enable
WP#
Write protect: The WP# contains an internal pull-up; when unconnected, WP is at VIH.
RESET#
Hardware reset
RY/BY#
Ready/Busy output
VCC
3.0 volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage
supply tolerances)
VSS
Device ground
NC
Pin not connected internally
5. Logic Symbol
19
A0–A18
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
WP#
Document Number: 002-00778 Rev. *Q
Page 6 of 50
S29AL008J
6.
Ordering Information
6.1
S29AL008J Standard Products
Cypress standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
S29AL008J
70
T
F
I
01
0
Packing Type
0 = Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
Model Number
01 = VCC = 2.7-3.6 V, top boot sector device (CFI Support)
02 = VCC = 2.7-3.6 V, bottom boot sector device (CFI Support)
03 = VCC = 2.7-3.6 V, top boot sector device (No CFI Support)
04 = VCC = 2.7-3.6 V, bottom boot sector device (No CFI Support)
R1 = VCC = 3.0-3.6 V, top boot sector device (CFI Support)
R2 = VCC = 3.0-3.6 V, bottom boot sector device (CFI Support)
Temperature Range
I = Industrial (-40 °C to +85 °C)
N = Extended (-40 °C to +125 °C)
A = Automotive, AEC-Q100 Grade 3 (-40 °C to +85 °C)
M = Automotive, AEC-Q100 Grade 1 (-40 °C to +125 °C)
Package Material Set
F = Pb-free
H = Low-Halogen, Pb-free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
B = Fine-pitch Ball-Grid Array Package
Speed Option
55 = 55 ns Access Speed
70 = 70 ns Access Speed
Device Number/Description
S29AL008J
8 Megabit Flash Memory manufactured using 110 nm process technology
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
S29AL008J Valid Combination
Device Number
Speed
Option
55
Package Type, Material,
and Temperature Range
TFI, TFN
BFI, BFN, BHI, BHN
TFI, TFN
S29AL008J
70
BFI, BFN, BHI, BHN
TFI
BFN, BHN
Model
Number
R1, R2
01, 02
03, 04
Packing Type
Package Description
0, 3 (Note 1)
TS048 (Note 3)
TSOP
0, 2, 3 (Note 1)
VBK048 (Note 4)
Fine-Pitch BGA
0, 3 (Note 1)
TS048 (Note 3)
TSOP
0, 2, 3 (Note 1)
VBK048 (Note 4)
Fine-Pitch BGA
0, 3 (Note 1)
TS048 (Note 3)
TSOP
0, 2, 3 (Note 1)
VBK048 (Note 4)
Fine-Pitch BGA
Notes
1. Type 0 is standard. Specify other options as required.
2. Type 1 is standard. Specify other options as required.
3. TSOP package markings omit packing type designator from ordering part number.
4. BGA package marking omits leading S29 and packing type designator from ordering part number.
Document Number: 002-00778 Rev. *Q
Page 7 of 50
S29AL008J
Valid Combinations – Automotive Grade / AEC-Q100
The following table lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume.
The table will be updated as new combinations are released. Contact your local sales representative to confirm availability of
specific combinations and to check on newly released combinations.
S29AL008J Valid Combination
Device
Number
S29AL008J
Package Description
Speed
Options
Package Type, Material,
and Temperature Range
Model
Number
55
TFA
R2
0, 3 (Note 1)
TS048 (Note 3)
TSOP
70
BFA, BFM
01, 02
0, 3 (Note 1)
VBK048 (Note 4)
Fine-Pitch BGA
70
TFA
02
0, 3 (Note 1)
TS048 (Note 3)
TSOP
70
TFM
02
0
TS048
TSOP
Packing Type
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/TS16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Document Number: 002-00778 Rev. *Q
Page 8 of 50
S29AL008J
7.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command
register. The command register itself does not occupy any addressable memory location. The register is composed of latches that
store the commands, along with the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The following table lists
the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe
each of these operations in further detail.
Table 1. S29AL008J Device Bus Operations
Operation
Read
Write
CE#
DQ8–DQ15
WP#
Addresses
(Note 1)
DQ0–
DQ7
H
X
AIN
DOUT
DOUT
OE# WE# RESET#
BYTE#
= VIH
BYTE#
= VIL
L
L
H
L
H
L
H
(Note 3)
AIN
X
X
High-Z
High-Z
High-Z
DQ8–DQ14 = High-Z,
DQ15 = A-1
(Note 4) (Note 4)
VCC
0.3 V
X
X
VCC
0.3 V
Output Disable
L
H
H
H
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
High-Z
High-Z
High-Z
H
Sector Address,
A6 = L,
A3 = A2 = L,
A1 = H, A0 = L
(Note 4)
X
X
(Note 4)
X
X
Standby
Sector Group Protect
(2) (3)
L
H
L
VID
Sector Group
Unprotect (2) (3)
L
H
L
VID
H
Sector Address,
A6 = H,
A3 = A2 = L,
A1 = H, A0 = L
Temporary Sector
Group Unprotect
X
X
X
VID
H
AIN
(Note 4) (Note 4)
High-Z
Legend
L = Logic Low = VIL; H = Logic High = VIH; VID = 8.5 V to 12.5 V; X = Don’t Care; AIN = Address In; DOUT = Data Out
Notes
1. Address In = Amax:A0 in WORD mode (BYTE#=VIH), Address In = Amax:A-1 in BYTE mode (BYTE#=VIL). Sector addresses are Amax to A12 in both WORD mode
and BYTE mode.
2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See Sector Group Protection/Unprotection
on page 14.
3. If WP# = VIL, the outermost sector remains protected (determined by device configuration). If WP# = VIH, the outermost sector protection depends on whether the
sector was last protected or unprotected using the method described in Section 7.10, Sector Group Protection/Unprotection on page 14. The WP# contains an internal
pull-up; when unconnected, WP is at VIH.
4. DIN or DOUT as required by command sequence, data polling, or sector group protection algorithm.
Document Number: 002-00778 Rev. *Q
Page 9 of 50
S29AL008J
7.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is
set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by
CE# and OE#. The data I/O pins DQ8–DQ14 are tristated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
7.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register contents are altered.
See Reading Array Data on page 22 for more information. Refer to the AC Read Operations on page 36 for timing specifications and
to Figure 14 on page 36 for the timing diagram. ICC1 in DC Characteristics on page 34 represents the active current specification for
reading array data.
7.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word/Byte
Configuration on page 10 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,
only two write cycles are required to program a word or byte, instead of four. Word/Byte Program Command Sequence on page 23
has details on programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 11 and Table 4 on page 12 indicate
the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector.
The Command Definitions on page 22 has details on erasing a sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to Autoselect Mode on page 13 and Autoselect Command Sequence on page 22 for more information.
ICC2 in DC Characteristics on page 34 represents the active current specification for the write mode. AC Characteristics on page 36
contains timing specification tables and timing diagrams for write operations.
7.4
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0.
Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 28 for more information, and
to AC Characteristics on page 36 for timing diagrams.
7.5
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
ICC3 and ICC4 represents the standby current specification shown in the table in DC Characteristics on page 34.
Document Number: 002-00778 Rev. *Q
Page 10 of 50
S29AL008J
7.6
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. I CC4 in the DC Characteristics on page 34 represents the automatic sleep mode current
specification.
7.7
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET#
pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and
ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence,
to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ±0.3 V, the device draws CMOS standby
current (ICC4). If RESET# is held at VIL but not within VSS ±0.3/0.1 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory. Note that the CE# pin should only go to VIL after RESET# has gone to
VIH. Keeping CE# at VIL from power up through the first read could cause the first read to retrieve erroneous data.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is
1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Refer to the tables in AC Characteristics on page 36 for RESET# parameters and to Figure 15 on page 37 for the timing diagram.
7.8
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 2. S29AL008J Top Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
0
0
0
0
X
X
X
64/32
00000h–0FFFFh
00000h–07FFFh
SA1
0
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA2
0
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA3
0
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA4
0
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA5
0
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA6
0
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA7
0
1
1
1
X
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
SA8
1
0
0
0
X
X
X
64/32
80000h–8FFFFh
40000h–47FFFh
SA9
1
0
0
1
X
X
X
64/32
90000h–9FFFFh
48000h–4FFFFh
SA10
1
0
1
0
X
X
X
64/32
A0000h–AFFFFh
50000h–57FFFh
SA11
1
0
1
1
X
X
X
64/32
B0000h–BFFFFh
58000h–5FFFFh
SA12
1
1
0
0
X
X
X
64/32
C0000h–CFFFFh
60000h–67FFFh
SA13
1
1
0
1
X
X
X
64/32
D0000h–DFFFFh
68000h–6FFFFh
SA14
1
1
1
0
X
X
X
64/32
E0000h–EFFFFh
70000h–77FFFh
Document Number: 002-00778 Rev. *Q
Page 11 of 50
S29AL008J
Table 2. S29AL008J Top Boot Block Sector Addresses (Continued)
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
(x8)
Address Range
SA15
1
1
1
1
0
X
X
32/16
F0000h–F7FFFh
78000h–7BFFFh
SA16
1
1
1
1
1
0
0
8/4
F8000h–F9FFFh
7C000h–7CFFFh
SA17
1
1
1
1
1
0
1
8/4
FA000h–FBFFFh
7D000h–7DFFFh
SA18
1
1
1
1
1
1
X
16/8
FC000h–FFFFFh
7E000h–7FFFFh
(x16)
Address Range
Note
Address range is A18:A-1 in byte mode and A19:A0 in word mode. See Word/Byte Configuration on page 10.
Table 3. Secured Silicon Sector Addresses (Top Boot)
Sector Size (bytes/words)
x8 Address Range
x16 Address Range
256/128
FFF00h–FFFFFh
7FF80h–7FFFFh
Table 4. S29AL008J Bottom Boot Block Sector Addresses
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
0
0
X
SA1
0
0
0
0
0
1
0
SA2
0
0
0
0
0
1
SA3
0
0
0
0
1
SA4
0
0
0
1
SA5
0
0
1
0
SA6
0
0
1
SA7
0
1
SA8
0
SA9
0
SA10
SA11
Address Range (in hexadecimal)
(x8)
Address Range
(x16)
Address Range
16/8
00000h–03FFFh
00000h–01FFFh
8/4
04000h–05FFFh
02000h–02FFFh
1
8/4
06000h–07FFFh
03000h–03FFFh
X
X
32/16
08000h–0FFFFh
04000h–07FFFh
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
0
1
1
1
X
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
1
0
0
0
X
X
X
64/32
80000h–8FFFFh
40000h–47FFFh
SA12
1
0
0
1
X
X
X
64/32
90000h–9FFFFh
48000h–4FFFFh
SA13
1
0
1
0
X
X
X
64/32
A0000h–AFFFFh
50000h–57FFFh
SA14
1
0
1
1
X
X
X
64/32
B0000h–BFFFFh
58000h–5FFFFh
SA15
1
1
0
0
X
X
X
64/32
C0000h–CFFFFh
60000h–67FFFh
SA16
1
1
0
1
X
X
X
64/32
D0000h–DFFFFh
68000h–6FFFFh
SA17
1
1
1
0
X
X
X
64/32
E0000h–EFFFFh
70000h–77FFFh
SA18
1
1
1
1
X
X
X
64/32
F0000h–FFFFFh
78000h–7FFFFh
Note
Address range is A18:A-1 in byte mode and A19:A0 in word mode. See the Word/Byte Configuration on page 10.
Table 5. Secured Silicon Sector Addresses (Bottom Boot)
Sector Size (bytes/words)
x8 Address Range
x16 Address Range
256/128
000000h–0000FFh
00000h–0007Fh
Document Number: 002-00778 Rev. *Q
Page 12 of 50
S29AL008J
7.9
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier
codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID (8.5 V to 12.5 V) on address pin A9. Address pins A6 and
A3–A0 must be as shown in Table 6. In addition, when verifying sector group protection, the sector address must appear on the
appropriate highest order address bits (see Table 2 on page 11 and Table 4 on page 12). Table 6 shows the remaining address bits
that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the
corresponding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown
in Table 13 on page 26. This method does not require VID. See Command Definitions on page 22 for details on using the autoselect
mode.
Table 6. S29AL008J Autoselect Codes (High Voltage Method)
Description
Mode CE# OE# WE#
Manufacturer ID: Cypress
L
L
H
DQ8
A18
A8
A5 A3
to
to A9 to A6 to to A1 A0
A10
A7
A4 A2
DQ15
X
VID
X
L
X
L
L
L
X
VID
X
L
X
L
L
H
X
VID
X
L
X
L
L
H
Device ID: S29AL008J
(Top Boot Block)
Word
L
L
H
Byte
L
L
H
Device ID: S29AL008J
(Bottom Boot Block)
Word
L
L
H
Byte
L
L
H
Sector Group Protection Verification
L
L
H
SA
VID
X
L
X
L
H
L
Secured Silicon Sector Indicator Bit
(DQ7) Top Boot Block
L
L
H
X
VID
X
L
X
L
H
Secured Silicon Sector Indicator Bit
(DQ7) Bottom Boot Block
L
L
H
X
VID
X
L
X
L
H
DQ7 to DQ0
X
01h
22h
DAh
X
DAh
22h
5Bh
X
5Bh
X
01h (protected)
X
00h (unprotected)
H
X
8Eh (factory locked)
0Eh (not factory locked)
H
X
96h (factory locked)
16h (not factory locked)
Legend
L = Logic Low = VIL; H = Logic High = VIH; SA = Sector Address; X = Don’t care
Note
The autoselect codes may also be accessed in-system via command sequences. See Table 13 on page 26.
Document Number: 002-00778 Rev. *Q
Page 13 of 50
S29AL008J
7.10
Sector Group Protection/Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group (see Table 2
on page 11 to Table 5 on page 12). The hardware sector group unprotection feature re-enables both program and erase operations
in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming
equipment. Figure 4 on page 16 shows the algorithms and Figure 24 on page 42 shows the timing diagram. This method uses
standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to
the first sector group unprotect write cycle.
The device is shipped with all sector groups unprotected. Cypress offers the option of programming and protecting sector groups at
its factory prior to shipping the device through Cypress Programming Service. Contact a Cypress representative for details.
It is possible to determine whether a sector group is protected or unprotected. See Autoselect Mode on page 13 for details.
Table 7. S29AL008J Top Boot Device Sector/Sector Group Protection
Sector / Sector Block
A18
A17
A16
A15
A14
A13
A12
Sector / Sector Block Size
SA0-SA3
0
0
X
X
X
X
X
256 (4x64) Kbytes
SA4-SA7
0
1
X
X
X
X
X
256 (4x64) Kbytes
SA8-SA11
1
0
X
X
X
X
X
256 (4x64) Kbytes
SA12-SA13
1
1
0
X
X
X
X
128 (2x64) Kbytes
SA14
1
1
1
0
X
X
X
64 Kbytes
SA15
1
1
1
1
0
X
X
32 Kbytes
SA16
1
1
1
1
1
0
0
8 Kbytes
SA17
1
1
1
1
1
0
1
8 Kbytes
SA18
1
1
1
1
1
1
X
16 Kbytes
Table 8. S29AL008J Bottom Boot Device Sector/Sector Group Protection
Sector / Sector Block
A18
A17
A16
A15
A14
A13
A12
Sector / Sector Block Size
SA0
0
0
0
0
0
0
X
16 Kbytes
SA1
0
0
0
0
0
1
0
8 Kbytes
SA2
0
0
0
0
0
1
1
8 Kbytes
SA3
0
0
0
0
1
X
X
32 Kbytes
SA4
0
0
0
1
X
X
X
64 Kbytes
SA5-SA6
0
0
1
X
X
X
X
128 (2x64) Kbytes
SA7-SA10
0
1
X
X
X
X
X
256 (4x64) Kbytes
SA11-SA14
1
0
X
X
X
X
X
256 (4x64) Kbytes
SA15-SA18
1
1
X
X
X
X
X
256 (4x64) Kbytes
Document Number: 002-00778 Rev. *Q
Page 14 of 50
S29AL008J
7.11
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group
Unprotect mode is activated by setting the RESET# pin to V ID . During this mode, formerly protected sector groups can be
programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected
sector groups are protected again. Figure 3 shows the algorithm, and Figure 24 on page 42 shows the timing diagrams, for this
feature.
Figure 3. Temporary Sector Group Unprotect Operation
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector Group
Unprotect Completed
(Note 2)
Notes
1. All protected sector groups unprotected. (If WP# = VIL, the highest or lowest address sector remains protected for uniform sector devices; the top or bottom two
address sectors remains protected for boot sector devices).
2. All previously protected sector groups are protected once again.
Document Number: 002-00778 Rev. *Q
Page 15 of 50
S29AL008J
Figure 4. In-System Sector Group Protect/Unprotect Algorithms
START
Protect all sectors:
The indicated portion
of the sector group protect
algorithm must be
performed for all
unprotected sector groups
prior to issuing the
first sector group
unprotect address
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Temporary Sector Group
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
No
Yes
All sectors
protected?
Set up sector group
address
Yes
Set up first sector
group address
Sector Group Protect:
Write 60h to sector group
address with
A6 = 0,
A3 = A2 = 0,
A1 = 1, A0 = 0
Sector GroupUnprotect:
Write 60h to sector
address with
A6 = 1,
A3 = A2 = 0,
A1 = 1, A0 = 0
Wait 150 µs
Increment
PLSCNT
Verify Sector Group
Protect: Write 40h
to sector group address
with A6 = 0,
A3 = A2 = 0,
A1 = 1, A0 = 0
Read from
sector group address
with A6 = 0,
A3 = A2 = 0,
A1 = 1, A0 = 0
Wait 1.5 ms
Reset
PLSCNT = 1
Increment
PLSCNT
No
Yes
Data = 01h?
No
Yes
Yes
Device failed
Verify Sector Group
Unprotect: Write
40h to sector
address with
A6 = 1,
A3 = A2 = 0,
A1 = 1, A0 = 0
Read from
sector groupaddress
with A6 = 1,
A3 = A2 = 0,
A1 = 1, A0 = 0
No
PLSCNT
= 25?
Temporary Sector
Group Unprotect
Mode
Protect another
sector?
PLSCNT
= 1000?
Yes
No
Remove VID
from RESET#
Device failed
Set up
next sector group
address
No
Data = 00h?
Yes
Last sector
group verified?
No
Yes
Write reset
command
Sector Group
Protect Algorithm
Sector Group
Protect complete
Sector Group Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Document Number: 002-00778 Rev. *Q
Page 16 of 50
S29AL008J
8. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables permanent part identification through an
Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether
or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be
changed, which prevents cloning of a factory-locked part. This ensures the security of the ESN once the product is shipped to the
field.
Cypress offers the device with the Secured Silicon Sector either factory-locked or customer-lockable. The factory-locked version is
always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. The
customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize the that sector in
any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a 0. Thus,
the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory
locked.
The system accesses the Secured Silicon Sector through a command sequence (see “Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence”
on page 23). After the system writes the Enter Secured Silicon Sector command sequence, it may read the Secured
Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system
issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending commands to the boot sectors.
8.1
Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory
In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon
Sector cannot be modified in any way. The device is available pre-programmed with one of the following:
A random, secure ESN only.
Customer code through the ExpressFlash service.
Both a random, secure ESN and customer code through the ExpressFlash service.
In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at addresses 00000h–0000Fh in byte
mode (or 00000h–00007h in word mode). In the Top Boot device, the ESN is in sector 18 at addresses FFFF0h–FFFFFh in byte
mode (or 7FFF8h–7FFFFh in word mode).
Customers may opt to have their code programmed by Cypress through the Cypress ExpressFlash service. Cypress programs the
customer’s code, with or without the random ESN. The devices are then shipped from the Cypress factory with the Secured Silicon
Sector permanently locked. Contact a Cypress representative for details on using the Cypress ExpressFlash service.
8.2
Customer Lockable: Secured Silicon Sector NOT Programmed
or Protected at the Factory
The customer lockable version allows the Secured Silicon Sector to be programmed once, and then permanently locked after it
ships from Cypress. Note that the unlock bypass functions is not available when programming the Secured Silicon Sector.
The Secured Silicon Sector area can be protected using the following procedures:
Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system sector group protect
algorithm as shown in Figure 4 on page 16, substituting the sector group address with the Secured Silicon Sector group address
(A0=0, A1=1, A2=0, A3=1, A4=1, A5=0, A6=0, A7=0). Note that this method is only applicable to the Secured Silicon Sector.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 5 on page 18.
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command
sequence to return to reading and writing the remainder of the array.
The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for
unprotecting the Secured Silicon Sector area, and none of the bits in the Secured Silicon Sector memory space can be modified in
any way.
Document Number: 002-00778 Rev. *Q
Page 17 of 50
S29AL008J
Figure 5. Secured Silicon Sector Protect Verify
START
RESET# = VID
Wait 1 ms
Write 60h to
any address
Write 40h to SecSi
Sector address
with A0=0, A1=1,
A2=0, A3=1, A4=1,
A5=0, A6=0, A7=0
Read from SecSi
Sector address
with A0=0, A1=1,
A2=0, A3=1, A4=1,
A5=0, A6=0, A7=0
Document Number: 002-00778 Rev. *Q
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove VID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
Page 18 of 50
S29AL008J
9.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows
specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or
address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses
given in Table 9 to Table 12 on page 20. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query
mode, and the system can read CFI data at the addresses given in the following tables. The system must write the reset command
to return the device to the autoselect mode.
Table 9. CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Description
Table 10. System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
1Bh
36h
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0003h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
0009h
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Document Number: 002-00778 Rev. *Q
Description
Page 19 of 50
S29AL008J
Table 11. Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
N
27h
4Eh
0014h
Device Size = 2 byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
000Eh
0000h
0000h
0001h
Erase Block Region 4 Information
Table 12. Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII
44h
88h
0033h
Minor version number, ASCII
Description
45h
8Ah
000Ch
Address Sensitive Unlock
0 = Required, 1 = Not Required
Process Technology (Bits 5-2)
0011b = 0.11 µm Floating Gate NOR
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Group Protect
0 = Not Supported, X= Number of sectors in smallest sector group
48h
90h
0001h
Sector Group Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Group Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, 01 = Supported
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S29AL008J
Table 12. Primary Vendor-Specific Extended Query (Continued)
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
0000h
ACC (Acceleration) Supply Minimum
00 = Not Supported, D7-D4: Volt, D3-D0: 100mV
4Eh
9Ch
0000h
ACC (Acceleration) Supply Maximum
00 = Not Supported, D7-D4: Volt, D3-D0: 100mV
Description
4Fh
9Eh
00XXh
WP# Protection
00 = Uniform Device without WP Protect
01 = Boot Device with TOP and Bottom WP Protect
02 = Bottom Boot Device with WP Protect
03 = Top Boot Device with WP Protect
04 = Uniform Device with Bottom WP Protect
05 = Uniform Device with Top WP Protect
06 = Uniform Device with All Sectors WP Protect
50h
A0h
00XXh
Program Suspend
00 = Not Supported, 01 = Supported
9.1
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to 13S29AL008J Command Definitions on page 26 for command definitions). In addition, the following hardware data
protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or from system noise.
9.1.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is greater than VLKO.
9.1.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
9.1.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
9.1.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to reading array data on power-up.
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S29AL008J
10. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 13
on page 26 defines the valid register command sequences. Writing incorrect address and data values or writing them in the
improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#
or CE#, whichever happens first. Refer to the appropriate timing diagrams in AC Characteristics on page 36.
10.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device
is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.
After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 25 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect
mode. See Reset Command on page 22.
See also Requirements for Reading Array Data on page 10 for more information. The Read Operations on page 36 provides the
read parameters, and Figure 14 on page 36 shows the timing diagram.
10.2
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is
complete.
If the reset command is issued after sending the program command, the command will be mistakenly treated as data and will be
programmed to a memory location instead of resetting the device. For resetting the device during program operation, reset
command can be sent only till before sending the program command. After the program command has been sent, 0xF0 will be
treated as data.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also
applies during Erase Suspend).
10.3
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether
or not a sector is protected. Table 13 on page 26 shows the address and data requirements. This method is an alternative to that
shown in Table 6 on page 13, which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then
enters the autoselect mode, and the system may read at any address any number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read
cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Table 2 on page 11 and Table 4 on page 12 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
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S29AL008J
10.4
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN).
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command
sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured
Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation.
13S29AL008J Command Definitions on page 26 shows the addresses and data requirements for both command sequences. Note
that the unlock bypass mode is not available when the device enters the Secured Silicon Sector. See also “Secured Silicon Sector
Flash Memory Region” on page 17 for further information.
10.5
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is
not required to provide further controls or timings. The device automatically generates the program pulses and verifies the
programmed cell margin. Table 13 on page 26 shows the address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer
latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status
on page 28 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to
reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1.
Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.
10.6
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the
unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. Table 13 on page 26 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 6 on page 24 illustrates the algorithm for the program operation. See Erase/Program Operations on page 39 for parameters,
and to Figure 18 on page 39 for timing diagrams.
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S29AL008J
Figure 6. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note
See Table 13 on page 26 for program command sequence.
10.7
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations. Table 13 on page 26 shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip
erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device
has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status
on page 28 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Figure 7 on page 26 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 39 for parameters,
and Figure 19 on page 40 for timing diagrams.
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S29AL008J
10.8
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector
erase command. Table 13 on page 26 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically
programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector
addresses and sector erase commands may be written. However, these additional erase commands are only one bus cycle long
and should be identical to the sixth cycle of the standard erase command explained above. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles
must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed
to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer on page 31.) The
time-out begins from the rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that
a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence
should be reinitiated once the device has returned to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write Operation Status
on page 28 for information on these status bits.)
Figure 7 on page 26 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 39 for parameters,
and to Figure 19 on page 40 for timing diagrams.
10.9
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,
any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 35 µs to suspend
the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions
apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 28
for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within non-suspended
sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See Write Operation Status on page 28 for more information.
The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows
reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 22 for more information.
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S29AL008J
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the
sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after
the device has resumed erasing.
Figure 7. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes
1. See Table 13 on page 26 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 31 for more information.
10.10 Command Definitions Table
Command Sequence (Note 1)
Cycles
Table 13. S29AL008J Command Definitions
Bus Cycles (Notes 2–5)
First
Second
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Autoselect (Note 8)
Manufacturer ID
Device ID,
Top Boot Block
Device ID,
Bottom Boot
Block
Sector Group
Protect Verify
(Note 9)
Word
Byte
Word
Byte
Word
Byte
4
4
4
Word
555
AAA
555
AAA
555
AAA
AA
AA
555
4
Byte
Enter Secured Silicon Word
Sector
Byte
AA
Document Number: 002-00778 Rev. *Q
555
2AA
555
2AA
555
AA
555
AAA
55
55
55
2AA
AAA
3
2AA
555
AAA
555
AAA
555
AAA
55
2AA
555
Fourth
90
90
90
555
555
AA
Third
90
AAA
55
555
AAA
X00
01
X01
22DA
X02
DA
X01
225B
X02
5B
(SA)
X02
XX00
(SA)
X04
00
Fifth
Sixth
XX01
01
88
Page 26 of 50
S29AL008J
Command Sequence (Note 1)
Exit Secured Silicon
Sector
CFI Query (Note 10)
Program
Unlock Bypass
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Cycles
Table 13. S29AL008J Command Definitions (Continued)
4
1
4
3
Bus Cycles (Notes 2–5)
First
555
AAA
55
AA
555
AAA
555
AAA
Second
AA
2AA
555
Third
555
55
AAA
AA
AA
2AA
555
2AA
555
555
55
AAA
555
55
AAA
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 12)
2
XXX
90
XXX
00
Sector Erase
(Note 15)
Word
Byte
Word
Byte
6
6
555
AAA
555
AAA
90
XXX
00
A0
PA
PD
Fifth
Sixth
98
Unlock Bypass Program
(Note 11)
Chip Erase
Fourth
AA
AA
Erase Suspend (Note 13)
1
XXX
B0
Erase Resume (Note 14)
1
XXX
30
2AA
555
2AA
555
55
55
Legend
X = Don’t care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on
the falling edge of the WE# or CE# pulse, whichever happens later.
Notes
1. See Table 1 on page 9 for description of bus operations.
555
AAA
555
AAA
20
80
80
555
AAA
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
PD = Data to be programmed at location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits A18–A12 uniquely select any sector.
2. All values are in hexadecimal.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See
“Autoselect Command Sequence” for more information.
3. Except for the read cycle and the fourth cycle of the autoselect command
sequence, all bus cycles are write cycles.
10. Command is valid when device is ready to read array data or when device is
in autoselect mode.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
11. The Unlock Bypass command is required prior to the Unlock Bypass
Program command.
5. Address bits A18–A11 are don’t cares for unlock and command cycles,
unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device
is in the autoselect mode, or if DQ5 goes high (while the device is providing
status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
12. The Unlock Bypass Reset command is required to return to reading array
data when the device is in the unlock bypass mode. F0 is also acceptable.
13. The system may read and program in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
14. The Erase Resume command is valid only during the Erase Suspend mode.
15. Additional sector erase commands during the time-out period after an initial
sector erase are one cycle long and identical to the sixth cycle of the sector
erase command sequence (SA / 30).
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S29AL008J
11. Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 14
on page 31 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
11.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether
the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if
the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum
output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following
read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low.
Figure 21 on page 41, illustrates this.
Write Operation Status on page 31 shows the outputs for Data# Polling on DQ7. Figure 9 on page 30 shows the Data# Polling
algorithm.
Figure 8. Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
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S29AL008J
11.2
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.
Table 14 on page 31 shows the outputs for RY/BY#. Figures Figure 14 on page 36, Figure 15 on page 37, Figure 18 on page 39
and Figure 19 on page 40 shows RY/BY# for read, reset, program, and erase operations, respectively.
11.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 28).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is
written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
Table 14 on page 31 shows the outputs for Toggle Bit I on DQ6. Figure 9 on page 30 shows the toggle bit algorithm in flowchart
form, and Reading Toggle Bits DQ6/DQ2 on page 30 explains the algorithm. Figure 22 on page 41 shows the toggle bit timing
diagrams. Figure 23 on page 41 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2:
Toggle Bit II.
11.4
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use
either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 14
on page 31 to compare outputs for DQ2 and DQ6.
Figure 9 on page 30 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 30
explains the algorithm. See also the DQ6: Toggle Bit I on page 29 subsection. Figure 22 on page 41 shows the toggle bit timing
diagram. Figure 23 on page 41 shows the differences between DQ2 and DQ6 in graphical form.
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Page 29 of 50
S29AL008J
11.5
Reading Toggle Bits DQ6/DQ2
Refer to Figure 9 on page 30 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read
DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value
of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–
DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully,
and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 9 on page 30).
Figure 9. Toggle Bit Algorithm
START
(Note 1)
Read DQ7–DQ0
Read DQ7–DQ0
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
(Notes 1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
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11.6
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the reset command to return the device to reading array data.
11.7
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has
begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire
time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The
system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less
than 50 s. See also Sector Erase Command Sequence on page 25.
After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle
has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the
device will accept additional sector erase commands. To ensure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check,
the last command might not have been accepted. The following table shows the outputs for DQ3.
Table 14. Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits
on page 31 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
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12. Absolute Maximum Ratings
Parameter
Rating
Storage Temperature Plastic Packages
–65 C to +150 C
Ambient Temperature with Power Applied
–65 C to +125 C
Voltage with Respect to Ground
VCC (Note 1)
–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2)
–0.5 V to +12.5 V
All other pins (Note 1)
Output Short Circuit Current (Note 3)
–0.5 V to VCC+0.5 V
200 mA
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 10
on page 33. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 11 on page 33.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 10 on page 33. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
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13. Operating Ranges
Parameter
Ambient Temperature
VCC Supply Voltages
Range
Industrial (I) Devices
–40 C to +85 C
Automotive, AEC-Q100 Grade 3 (A)
Devices
–40 C to +85 C
Extended (N) Devices
–40 °C to +125 °C
Automotive, AEC-Q100 Grade 1 (M)
Devices
–40 °C to +125 °C
Full
2.7 V to 3.6 V
Regulated
3.0 V to 3.6 V
Note
Operating ranges define those limits between which the functionality of the device is guaranteed.
Figure 10. Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 11. Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
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14. DC Characteristics
14.1
CMOS Compatible
Parameter
ILI
Description
Test Conditions
Min
Typ
Max
Input Load Current
VIN = VSS to VCC, VCC = VCC max
1.0
WP# Input Load Current
VCC = VCC max, WP# = VSS to VCC
25
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
35
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
Unit
µA
1.0
CE# = VIL, OE# = VIH,
VCC = VCC max, Byte Mode
5 MHz
7
12
1 MHz
2
4
CE# = VIL, OE# = VIH,,
VCC = VCC max, Word Mode
5 MHz
7
12
1 MHz
mA
ICC1
VCC Active Read Current (Note 1)
2
4
ICC2
VCC Active Erase/Program Current
(Notes 2, 3, 4)
CE# = VIL, OE# = VIH,
VCC = VCC max
20
30
mA
ICC3
VCC Standby Current (Note 4)
OE# = VIH,
CE#, RESET# = VCC 0.3 V/-0.1V,
WP# = VCC or open, VCC = VCC max
(Note 5)
0.2
5
µA
ICC4
VCC Standby Current During Reset
(Note 4)
VCC = VCC max;
RESET# = VSS 0.3 V/-0.1V
WP# = VCC or open, (Note 5)
0.2
5
µA
ICC5
Automatic Sleep Mode
(Notes 3, 4)
VCC = VCC max, VIH = VCC 0.3 V,
VIL = VSS 0.3 V/-0.1 V,
WP# = VCC or open, (Note 5)
0.2
5
µA
VIL
Input Low Voltage
-0.1
0.8
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 2.7–3.6 V
8.5
12.5
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
VOH1
VOH2
VLKO
Output High Voltage
0.45
IOH = -2.0 mA, VCC = VCC min
0.85 x VCC
IOH = -100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage
2.1
V
2.5
Notes
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
4. Not 100% tested.
5. When device operated in Extended Temperature range, the currents shall be as follows:
ICC3 = 0.2 µA (typ), 10 µA (max)
ICC4 = 0.2 µA (typ), 10 µA (max)
ICC5 = 0.2 µA (typ), 10 µA (max)
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15. Test Conditions
Figure 12. Test Setup
3.3 V
2.7 k
Device
Under
Test
CL
6.2 k
Note
Diodes are IN3064 or equivalent.
Table 15. Test Specifications
Test Condition
70
55
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
0.0 or VCC
Input timing measurement reference levels
0.5 VCC
Output timing measurement reference levels
0.5 VCC
V
16. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change
Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Figure 13. Input Waveforms and Measurement Levels
VCC
Input
0.5 VCC
Measurement Level
0.5 VCC
Output
0.0 V
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17. AC Characteristics
17.1
Read Operations
Parameter
JEDEC
Std
tAVAV
tRC
tAVQV
Description
Speed Options
Test Setup
Read Cycle Time (Note 1)
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
OE# = VIL
55
70
Min
55
70
Max
55
70
tELQV
tCE
Chip Enable to Output Delay
Max
55
70
tGLQV
tOE
Output Enable to Output Delay
Max
30
30
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
Latency Between Read and Write Operations
tSR/W
tAXQX
Min
20
Read
Min
0
Toggle and
Data# Polling
Min
10
Min
0
tOEH
Output Enable
Hold Time (Note 1)
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Unit
ns
Notes
1. Not 100% tested.
2. See Figure 12 on page 35 and Table 15 on page 35 for test specifications.
Figure 14. Read Operations Timings
tRC
Addresses Stable
Addresses
tACC
CE#
OE#
tDF
tOE
tSR/W
tOEH
WE#
tCE
HIGH Z
Outputs
tOH
Output Valid
HIGH Z
RESET#
RY/BY#
0V
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17.2
Hardware Reset (RESET#)
Parameter
JEDEC
Description
Std
Test Setup
All Speed Options
Unit
µs
tREADY
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
Max
35
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
tRP
RESET# Pulse Width
500
tRH
RESET# High Time Before Read (See Note)
tRPD
RESET# Low to Standby Mode
tRB
RY/BY# Recovery Time
ns
50
Min
35
µs
0
ns
Note
Not 100% tested.
Figure 15. RESET# Timings
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms (Note 1)
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Note
1. CE# should only go low after RESET# has gone high. Keeping CE# low from power up through the first read could cause the first read to retrieve erroneous data.
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17.3
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Speed Options
Description
Std
tELFL/tELFH
55
70
CE# to BYTE# Switching Low or High
Max
5
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
16
tFHQV
BYTE# Switching High to Output Active
Min
55
Unit
ns
70
Figure 16. BYTE# Timings for Read Operations
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0–DQ14)
DQ0–DQ14
Data Output
(DQ0–DQ7)
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 17. BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note
Refer to the Erase/Program Operations table for tAS and tAH specifications.
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17.4
Erase/Program Operations
Parameter
Speed Options
Description
Std
tAVAV
tWC
Write Cycle Time (Note 1)
tAVWL
tAS
Address Setup Time
Min
0
ns
tWLAX
tAH
Address Hold Time
Min
45
ns
tDVWH
tDS
Data Setup Time
Min
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tGHWL
tGHWL
Min
55
70
55
70
Unit
JEDEC
35
35
ns
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWPH
Write Pulse Width High
Min
25
ns
tSR/W
Latency Between Read and Write Operations
Min
20
ns
tWHWL
tWHWH1
tWHWH1
Programming Operation (Note 2)
tWHWH2
tWHWH2
35
35
Byte
Typ
6
Word
Typ
6
ns
µs
Sector Erase Operation (Note 2)
Typ
0.5
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
Program/Erase Valid to RY/BY# Delay
Max
90
tBUSY
ns
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 44 for more information.
Figure 18. Program Operation Timings
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
Read Status Data (last two cycles)
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
tVCS
VCC
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
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Figure 19. Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 28).
2. Illustration shows device in word mode.
Figure 20. Back to Back Read/Write Cycle Timing
Addresses
tWC
tWC
tRC
Valid PA
Valid RA
tWC
Valid PA
Valid PA
tAH
tCPH
tACC
tCE
CE#
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tWPH
tDF
tDS
tOH
tDH
Valid
Out
Valid
In
Data
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Document Number: 002-00778 Rev. *Q
Read Cycle
CE# Controlled Write Cycles
Page 40 of 50
S29AL008J
Figure 21. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
Status Data
Status Data
Valid Data
True
High Z
DQ0–DQ6
Valid Data
True
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 22. Toggle Bit Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 23. DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
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17.5
Temporary Sector Group Unprotect
Parameter
JEDEC
Description
Std
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
Min
4
µs
Note
Not 100% tested.
Figure 24. Temporary Sector Group Unprotect/Timing Diagram
12V
RESET#
0 or 3V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 25. Sector Group Protect/Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6, A3, A2
A1, A0
Valid*
Valid*
Sector Group Protect/Unprotect
Data
60h
1 µs
Valid*
Verify
60h
40h
Status
Sector Group Protect: 150 µs
Sector Group Unprotect: 1.5 ms
CE#
WE#
OE#
Note
For sector group protect, A6 = 0, A3 = A2 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A3 = A2 = 0, A1 = 1, A0 = 0.
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17.6
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std
Speed Options
Description
55
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
tDVEH
tDS
Data Setup Time
Min
70
55
70
0
ns
ns
45
35
Unit
ns
35
ns
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
tELEH
tCP
CE# Pulse Width
Min
tCPH
CE# Pulse Width High
Min
25
ns
tSR/W
Latency Between Read and Write Operations
Min
20
ns
tEHDX
tEHEL
tWHWH1
tWHWH1
Programming Operation (Note 2)
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
0
35
ns
35
Byte
Typ
6
Word
Typ
6
Typ
0.5
ns
µs
sec
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 44 for more information.
Figure 26. Alternate CE# Controlled Write Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
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18. Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
0.5
10
s
Chip Erase Time
10
Byte Programming Time
6
150
µs
Word Programming Time
6
150
µs
Byte Mode
6.3
80
s
Word Mode
3.2
60
s
Chip Programming Time
s
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Notes
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 on page 26 for further information
on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.
19. TSOP and BGA Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
CIN2
Output Capacitance
Control Pin Capacitance
CIN3
WP# Pin Capacitance
VOUT = 0
VIN = 0
VIN = 0
Package
Typ
Max
TSOP
4
6
BGA
4
6
TSOP
4.5
5.5
BGA
4.5
5.5
TSOP
5
6.5
BGA
5
6.5
TSOP
8.5
10
BGA
8.5
10
Unit
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Document Number: 002-00778 Rev. *Q
Page 44 of 50
S29AL008J
20. Physical Dimensions
20.1
48-Pin TSOP (18.4 mm × 12.0 mm × 1.2 mm) Package Outline
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Note
For reference only. BSC is an ANSI standard for Basic Space Centering.
Document Number: 002-00778 Rev. *Q
Page 45 of 50
S29AL008J
20.2
48-Ball VFBGA (8.15 mm x 6.15 mm × 1.00 mm) Package Outline
002-19063 **
Document Number: 002-00778 Rev. *Q
Page 46 of 50
S29AL008J
21. Revision History
Document History Page
Document Title: S29AL008J, 8-Mbit (1M × 8-Bit/512K × 16-Bit), 3 V, Boot Sector Flash
Document Number: 002-00778
Rev.
ECN No.
Submission
Date
Description of Change
**
–
06/26/2007
Initial release
*A
–
10/29/2007
Distinctive Characteristics Corrected number of 64 Kbyte / 32 Kword sectors
Global Removed 44-pin SOP package
Ordering Information Removed all leaded package offerings
S29AL008J Device Bus Operations Table Under Note 3: Removed the line
“If WP# = VHH, all sectors will be unprotected.”
CFI Query Identification String Table Updated the data for CFI addresses 2C hex & 39 hex
S29AL008J Command Definitions Table The 2nd cycle data for the “Unlock Bypass
Reset” command was updated from ‘F0’ to ‘00’.
Absolute Maximum Ratings Updated VCC Absolute Maximum Rating
CMOS Compatible Table
Updated ICC3 Standby current test condition
Updated maximum value of VOL
Updated minimum value of VLKO
Figure Back to Back Read/Write Cycle Timing Corrected the tSR/W duration
*B
–
03/27/2008
Reset #: Hardware Reset Pin Updated current consumption during RESET# pulse
CMOS Compatible Table
Updated maximum value of ILI
Updated test condition, typical and maximum value of Icc3
Updated test condition, typical and maximum value of Icc4
Updated test condition, typical and maximum value of Icc5
Updated minimum value of VIL
Added Note 5
Ordering Information
Updated valid combination
• Removed 45 ns, added 70 ns
*C
–
05/23/2008
Global Removed fortified BGA package option
Ordering Information
Added the Regulated Voltage option
Added the Extended Temperature Range
Updated the Valid Combination table
Pin Configuration Updated Pin Configuration table
Device Bus Operation
Updated the S29AL008J Device Bus Operation table and modified Note 3
Operating Ranges
Added Extended Temperature Range information
Added Regulated Voltage
Document Number: 002-00778 Rev. *Q
Page 47 of 50
S29AL008J
Document History Page (Continued)
Document Title: S29AL008J, 8-Mbit (1M × 8-Bit/512K × 16-Bit), 3 V, Boot Sector Flash
Document Number: 002-00778
Rev.
ECN No.
Submission
Date
Description of Change
*D
–
08/12/2008
Sector Protection/Unprotection
Title changed to Sector Group Protection and Unprotection
Section amended and restated to Sector Group Protection and Unprotection
Temporary Sector Unprotect
Title changed to Temporary Sector Group Unprotect
Figure 7.1; Title changed to Temporary Sector Group Unprotect Operation
Figure 7.2; Title changed to In-System Sector Protect/Unprotect Algorithms
Temporary Sector Unprotect
Title changed to Temporary Sector Group Unprotect
Figure 17.11; Title changed to Temporary Sector Group Unprotect/Timing Diagram
Figure 17.12; Sector Group Protect/Unprotect Timing Diagram
Reading Toggle Bits DQ6/DQ2 Updated Figure 11.2
Ordering Information
Added SSOP56 package option
Updated the Valid Combination table
Connection Diagrams Added 56-pin Shrink Small Outline Package (SSOP56)
Physical Dimensions Added 56-pin Shrink Small Outline Package (SSOP56)
Alternate CE# Controlled Erase/Program
Operations TDS value changed from 45 ns to 35 ns
Erase/Program Operation Added figure Toggle Bit Timing (During Embedded Algorithm)
Product Selector Guide Updated Table
*E
–
10/29/2008
Customer Lockable: Secured Silicon Sector Programmed and Protected at the
Factory
Modified first bullet
Updated figure Secured Silicon Sector Protect Verify
TSOP and Pin Capacitance Updated Table
*F
–
02/03/2009
Ordering Information Updated the Valid Combination table
Erase/Program Operation
Updated Table
Removed Figure Toggle Bit Timing (During Embedded Algorithm)
Erase and Programming Performance Updated Table
*G
–
07/09/2009
General Corrected minor typos
Physical Dimensions Updated TS048
Customer Lockable: Secured Silicon Sector NOT Programmed and Protected at the
Factory
Modified first bullet
Erase and Programming Performance Updated Table
*H
–
02/23/2010
Sector Erase Command Sequence Added clarification regarding additional sector erase
commands during time-out period
Command Definitions Table Added Note 15 to clarify additional sector erase commands
during time-out period
*I
–
12/09/2011
Ordering Information Added Low-Halogen 48-ball BGA ordering option
RESET#: Hardware Reset Pin Added sentence regarding use of CE# with RESET#
RESET# Timings Figure Added note
*J
–
04/12/2012
Global
Removed SSOP-56
*K
5042120
12/11/2015
Updated to Cypress template.
*L
5690582
04/27/2017
Updated Cypress Logo and Copyright.
*M
5768904
06/09/2017
Updated Ordering Information:
Updated S29AL008J Standard Products:
Added Automotive Temperature Range related information.
Added Valid Combinations – Automotive Grade / AEC-Q100.
Document Number: 002-00778 Rev. *Q
Page 48 of 50
S29AL008J
Document History Page (Continued)
Document Title: S29AL008J, 8-Mbit (1M × 8-Bit/512K × 16-Bit), 3 V, Boot Sector Flash
Document Number: 002-00778
Rev.
ECN No.
Submission
Date
*N
5812614
07/13/2017
Updated Ordering Information:
Updated Valid Combinations – Automotive Grade / AEC-Q100:
Updated details in the table.
Updated to new template.
*O
5923085
10/12/2017
Updated Physical Dimensions:
Updated 48-Ball VFBGA (8.15 mm x 6.15 mm × 1.00 mm) Package Outline:
Updated diagram (to show dimensions table).
*P
6132765
04/11/2018
Updated to new template.
Completing Sunset Review.
*Q
6804814
02/21/2020
Updated Command Definitions:
Updated Reset Command:
Updated description.
Updated to new template.
Document Number: 002-00778 Rev. *Q
Description of Change
Page 49 of 50
S29AL008J
Sales, Solutions, and Legal Information
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Document Number: 002-00778 Rev. *Q
Revised February 21, 2020
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