S29NS512P0PBJW000

"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion, Inc." products to new and existing customers. Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Cypress products and solutions. S29NS512P, S29NS256P, S29NS128P 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V MirrorBit Flash Memory Features  Single 1.8V read/program/erase (1.70–1.95V)  Command set compatible with JEDEC (42.4) standard  90 nm MirrorBit Technology  Hardware (WP#) protection of highest two sectors  Multiplexed Data and Address for reduced I/O count  Top Boot sector configuration (NS256/128P)  Simultaneous Read/Write operation  Handshaking by monitoring RDY  Full/Half drive output slew rate control  Offered Packages – NS512P: 64-ball FBGA (8 mm x 9.2 mm) – NS256P/NS128P: 44-ball FBGA (6.2 mm x 7.7 mm)  32-word Write Buffer  Sixteen-bank architecture consisting of 64/32/16 MB for NS512/256/128P, respectively  Low VCC write inhibit  Four 32 kB sectors at the top of memory array (NS256/128P)  Persistent and Password methods of Advanced Sector Protection  512 128 kB sectors (NS512P), 255/127 128 kB sectors (NS256/128P)  Write operation status bits indicate program and erase operation completion  Programmable linear (8/16/32) with or without wrap around and continuous burst read modes  Suspend and Resume commands for Program and Erase operations  Secured Silicon Sector region consisting of 128 words each for factory and customer  Unlock Bypass program command to reduce programming time  20-year data retention (typical)  Synchronous or Asynchronous program operation, independent of burst control register settings  Cycling Endurance: 100,000 cycles per sector (typical)  VPP input pin to reduce factory programming time  RDY output indicates data available to system  Support for Common Flash Interface (CFI) Performance Characteristics Read Access Times Typical Program & Erase Times Speed Option (MHz) 83 MHz Single Word Programming 40 µs 9.4 µs Max. Synch. Burst Access, ns (tBACC) 9.0 ns Effective Write Buffer Programming (VCC) Per Word Max. Asynch. Access Time, ns (tACC) 80 ns Effective Write Buffer Programming (VPP) Per Word Max OE# Access Time, ns (tOE) 7.0 ns Sector Erase (16 Kword Sector) 450 ms Sector Erase (64 Kword Sector) 900 ms 6 µs Current Consumption (typical values) Continuous Burst Read @ 83 MHz 42 mA Simultaneous Operation 83 MHz 60 mA Program 30 mA Standby Mode 20 µA Cypress Semiconductor Corporation Document Number: 002-01103 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 13, 2015 S29NS512P S29NS256P, S29NS128P Contents Features................................................................................. 2 Performance Characteristics............................................... 2 1. General Description..................................................... 4 2. Ordering Information ................................................... 4 3. Input/Output Descriptions and Logic Symbol........... 5 4. Block Diagrams............................................................ 6 5. 5.1 5.2 Physical Dimensions/Connection Diagrams............. 7 Related Documents ....................................................... 7 Special Handling Instructions for FBGA Package.......... 7 6. 6.1 Product Overview ...................................................... 11 Memory Map ................................................................ 11 7. 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 Device Operations ..................................................... Device Operation Table ............................................... Asynchronous Read..................................................... Synchronous (Burst) Read Operation.......................... Autoselect .................................................................... Program/Erase Operations .......................................... Simultaneous Read/Write ............................................ Writing Commands/Command Sequences.................. Handshaking ................................................................ Hardware Reset ........................................................... Software Reset ............................................................ Programmable Output Slew Rate Control.................... 26 26 26 27 33 35 50 50 51 51 51 52 8. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Advanced Sector Protection/Unprotection ............. Lock Register ............................................................... Persistent Protection Bits............................................. Dynamic Protection Bits............................................... Persistent Protection Bit Lock Bit................................. Password Protection Method ....................................... Advanced Sector Protection Software Examples ........ Hardware Data Protection Methods............................. 53 54 54 56 57 58 59 60 9. 9.1 9.2 9.3 9.4 Power Conservation Modes...................................... Standby Mode.............................................................. Automatic Sleep Mode................................................. Hardware RESET# Input Operation............................. Output Disable (OE#)................................................... 61 61 61 61 61 10. 10.1 10.2 10.3 Secured Silicon Sector Flash Memory Region ....... Factory Secured Silicon Sector .................................... Customer Secured Silicon Sector ................................ Secured Silicon Sector Entry and Exit Command Sequences ................................................. 62 62 62 Document Number: 002-01103 Rev. *A 11. Electrical Specifications............................................. 65 11.1 Absolute Maximum Ratings .......................................... 65 11.2 Operating Ranges......................................................... 65 11.3 DC Characteristics ........................................................ 66 11.4 Capacitance .................................................................. 67 11.5 Test Conditions ............................................................. 67 11.6 Key to Switching Waveforms ........................................ 67 11.7 Switching Waveforms ................................................... 68 11.8 CLK Characterization.................................................... 68 11.9 AC Characteristics ........................................................ 69 11.10Erase and Programming Performance ......................... 80 12. Appendix ..................................................................... 81 12.1 Common Flash Memory Interface................................. 85 13. Revision History.......................................................... 89 63 Page 3 of 106 S29NS512P S29NS256P, S29NS128P 1. General Description The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins. These products can operate up to 83 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered power consumption.Ordering Information 2. Ordering Information The ordering part number is formed by a valid combination of the following: S29NS 512 P xx BJ W 00 0 Packing Type 0 = Tray (standard; (Note 1)) 3 = 13-inch Tape and Reel Model Number 00 = Standard Temperature Range W = Wireless (–25°C to +85°C) Package Type & Material Set BJ = Very Thin Fine-Pitch BGA,Lead (Pb)-free LF35 Package Speed Option (Burst Frequency) 0P = 66 MHz 0S = 83 MHz Process Technology P = 90 nm MirrorBit Technology Flash Density 512 =512 Mb 256 =256 Mb 128 =128 Mb Product Family S29NS =1.8 Volt-Only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory Valid Combinations Base Ordering Part Number Speed Option Package Type Package Type, Material, & Temperature Range Packing Type Model Number S29NS512P S29NS256P 8.0 mm x 9.2 mm, 64-ball 0P, 0S BJW (Lead (Pb)-free, LF35) 0, 3 (1) 00 6.2 mm x 7.7 mm, 44-ball S29NS128P Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S29 and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Document Number: 002-01103 Rev. *A Page 4 of 93 S29NS512P S29NS256P, S29NS128P 3. Input/Output Descriptions and Logic Symbol Table 3.1 identifies the input and output package connections provided on the device. Table 3.1 Input/Output Descriptions Symbol Type Description A24 – A16 Input Address inputs, S29NS512P. A23 – A16 Input Address inputs, S29NS256P. A22 – A16 Input A/DQ15 – A/DQ0 I/O Address inputs, S29NS128P. Multiplexed Address/Data input/output. CE# Input Chip Enable. Asynchronous relative to CLK for the Burst mode. OE# Input Output Enable. Asynchronous relative to CLK for the Burst mode. WE# Input VCC Supply VCCQ Supply Write Enable. Device Power Supply. Input/Output Power Supply (must be ramped simultaneously with VCC). VSS I/O Ground. VSSQ I/O Input/Output Ground. NC RDY Not Connected Output No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). Ready. Indicates when valid burst data is ready to be read. Input The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. AVD# Input Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only). VIL = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be latched on rising edge of CLK. VIH = device ignores address inputs. RESET# Input Hardware Reset. Low = device resets and returns to reading array data. WP# Input Write Protect. At VIL, disables program and erase functions in the four top sectors. Should be at VIH for all other conditions. VPP Input Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL,disables all program and erase functions. Should be at VIH for all other conditions. RFU Reserved Reserved for Future Use. No device internal signal is currently connected to the package connector but there is potential future use for the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices. Do Not Use A device internal signal may be connected to the package connector. The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pulldown resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections. CLK DNU Document Number: 002-01103 Rev. *A Page 5 of 93 S29NS512P S29NS256P, S29NS128P 4. Block Diagrams Figure 4.1 Simultaneous Operation Circuit Bank Address VSSQ Bank 0 Latches and Control Logic VSS VCCQ Y-Decoder VCC DQ15–DQ0 Amax–A0 X-Decoder OE# STATE CONTROL & COMMAND REGISTER DQ15–DQ0 Status Control Amax–A16 X-Decoder Bank Address Amax–A16 Bank (n-1) Latches and Control Logic A/DQ15–A/DQ0 DQ15–DQ0 X-Decoder Amax–A0 Y-Decoder WP# VPP RESET# WE# CE# AVD# RDY Bank 1 Latches and Control Logic Y-Decoder Bank Address DQ15–DQ0 Bank (n) Latches and Control Logic Bank Address Y-Decoder X-Decoder DQ15–DQ0 Notes 1. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P. 2. Bank (n) = 15 for NS512P/ NS256P/ NS128P. Document Number: 002-01103 Rev. *A Page 6 of 93 S29NS512P S29NS256P, S29NS128P 5. Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the OPN. 5.1 Related Documents The following documents contain information relating to the S29NS-P devices. Click on the title or go to www.spansion.com, or request a copy from your sales office.  5.2 Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 5.2.1 64-Ball Fine-Pitch Grid Array, S29NS512P Figure 5.1 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A nc nc B DNU DNU VSS A24 VCC VSS VCC RFU DNU DNU RDY A21 VSS CLK VCC WE# VPP A19 A17 A22 Legend C Flash Only D VCCQ A16 A20 ADV# A23 RESET# WP# A18 CE# VSSQ No Connect E VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 VCCQ VSSQ DNU DNU Reserved for Future Use F A/DQ15 A/DQ14 VSSQ G DNU DNU DNU RFU VCCQ DNU Do Not Use H nc Document Number: 002-01103 Rev. *A nc Page 7 of 93 S29NS512P S29NS256P, S29NS128P 5.2.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Figure 5.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down NC NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 RDY A21 VSS CLK VCC WE# VPP A19 A17 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 VCCQ A16 A20 AVD# A23 RESET# WP# A18 CE# VSSQ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# D1 D2 D6 D7 A/DQ15 A/DQ14 D3 D4 D5 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 D8 D9 D10 VCCQ A/DQ1 A/DQ0 NC 5.2.3 NC 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Figure 5.3 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down NC NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 RDY A21 VSS CLK VCC WE# VPP A19 A17 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 VCCQ A16 A20 AVD# NC RESET# WP# A18 CE# VSSQ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# D1 D2 D6 D7 A/DQ15 A/DQ14 NC Document Number: 002-01103 Rev. *A D3 D4 D5 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 D8 D9 D10 VCCQ A/DQ1 A/DQ0 NC Page 8 of 93 S29NS512P S29NS256P, S29NS128P 5.2.4 VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array Figure 5.4 VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P D 10 A D1 A1 CORNER INDEX MARK A1 CORNER e 10 9 8 7 6 5 4 3 2 1 NF1 NF2 e A B C D E E NF3 NF4 B SD 1.00 Øb A A2 0.10 C C 0.08 C E1 F 0.50 TOP VIEW 7 SE 7 6 Ø 0.05 M C Ø 0.15 M C A B A1 SEATING PLANE BOTTOM VIEW SIDE VIEW NOTES: PACKAGE VDD 064 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 8.00 mm x 9.20 mm NOM PACKAGE 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). SYMBOL MIN NOM MAX NOTE A 0.86 --- 1.00 A1 0.20 --- --- A2 0.66 0.71 0.76 BODY THICKNESS D 7.90 8.00 8.10 BODY SIZE E 9.10 9.20 9.30 BODY SIZE OVERALL THICKNESS BALL HEIGHT D1 4.50 BALL FOOTPRINT E1 2.50 BALL FOOTPRINT MD 10 ROW MATRIX SIZE D DIRECTION ME 6 ROW MATRIX SIZE E DIRECTION N 64 TOTAL BALL COUNT Øb 0.25 0.30 0.35 BALL DIAMETER e 0.50 BALL PITCH SD / SE 0.25 SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3533 \ 16-038.27 \ 12.13.05 Document Number: 002-01103 Rev. *A Page 9 of 93 S29NS512P S29NS256P, S29NS128P 5.2.5 VDE44-44-Ball Very Thin Fine-Pitch Ball Grid Array, 7.7 mm x 6.2 mm Figure 5.5 VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P D A1 CORNER INDEX MARK D1 A A1 CORNER 10 9 8 7 6 5 4 3 2 1 10 NF2 NF1 e A B E 1.00 E1 7 NF4 NF3 1.00 SD B TOP VIEW SE C D φb 7 6 φ 0.05 M C φ 0.15 M C A B 0.10 C A2 A A1 SIDE VIEW SEATING PLANE C BOTTOM VIEW 0.08 C NOTES: PACKAGE VDE 044 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 7.70 mm x 6.20 mm NOM PACKAGE 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). SYMBOL MIN NOM MAX NOTE A 0.86 --- 1.00 A1 0.20 --- --- A2 0.66 0.71 0.76 BODY THICKNESS D 7.6 7.7 7.8 BODY SIZE E 6.1 6.2 6.3 BODY SIZE OVERALL THICKNESS BALL HEIGHT D1 4.50 BALL FOOTPRINT E1 1.50 BALL FOOTPRINT MD 10 ROW MATRIX SIZE D DIRECTION ME 4 ROW MATRIX SIZE E DIRECTION N 44 TOTAL BALL COUNT φb 0.25 0.30 0.35 BALL DIAMETER e 0.50 BSC. BALL PITCH SD / SE 0.25 BSC. SOLDER BALL PLACEMENT ? DEPOPULATED SOLDER BALLS 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN ? THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3308.2 \ 16-038.9L Document Number: 002-01103 Rev. *A Page 10 of 93 S29NS512P S29NS256P, S29NS128P 6. Product Overview The S29NS-P family consists of 512, 256, and 128 Mb, 1.8 volts-only, simultaneous read/write burst mode, multiplexed Flash device optimized for today’s wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 32, 16, or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-word, 16-word, or 32-word aligned group) with or without wrap around. These flash devices multiplex the data and addresses for reduced I/O count. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: 6.1  Advanced Sector Protection methods for protecting sectors as required  256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable. Memory Map The S29NS512/256/128P devices consist of 16 banks organized as shown in Tables 6.1 – 6.3. Document Number: 002-01103 Rev. *A Page 11 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 1 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA0 64 Kwords 000000h–00FFFFh Bank SA32 64 Kwords 200000h–20FFFFh SA1 64 Kwords 010000h–01FFFFh SA33 64 Kwords 210000h–21FFFFh SA2 64 Kwords 020000h–02FFFFh SA34 64 Kwords 220000h–22FFFFh SA3 64 Kwords 030000h–03FFFFh SA35 64 Kwords 230000h–23FFFFh SA4 64 Kwords 040000h–04FFFFh SA36 64 Kwords 240000h–24FFFFh SA5 64 Kwords 050000h–05FFFFh SA37 64 Kwords 250000h–25FFFFh SA6 64 Kwords 060000h–06FFFFh SA38 64 Kwords 260000h–26FFFFh SA7 64 Kwords 070000h–07FFFFh SA39 64 Kwords 270000h–27FFFFh SA8 64 Kwords 080000h–08FFFFh SA40 64 Kwords 280000h–28FFFFh SA9 64 Kwords 090000h–09FFFFh SA41 64 Kwords 290000h–29FFFFh 2A0000h–2AFFFFh SA10 64 Kwords 0A0000h–0AFFFFh SA42 64 Kwords SA11 64 Kwords 0B0000h–0BFFFFh SA43 64 Kwords 2B0000h–2BFFFFh SA12 64 Kwords 0C0000h–0CFFFFh SA44 64 Kwords 2C0000h–2CFFFFh SA13 64 Kwords 0D0000h–0DFFFFh SA45 64 Kwords 2D0000h–2DFFFFh SA14 64 Kwords 0E0000h–0EFFFFh SA15 64 Kwords 0F0000h–0FFFFFh SA16 64 Kwords 100000h–10FFFFh SA17 64 Kwords SA18 SA19 SA46 64 Kwords 2E0000h–2EFFFFh SA47 64 Kwords 2F0000h–2FFFFFh SA48 64 Kwords 300000h–30FFFFh 110000h–11FFFFh SA49 64 Kwords 310000h–31FFFFh 64 Kwords 120000h–12FFFFh SA50 64 Kwords 320000h–32FFFFh 64 Kwords 130000h–13FFFFh SA51 64 Kwords 330000h–33FFFFh SA20 64 Kwords 140000h–14FFFFh SA52 64 Kwords 340000h–34FFFFh SA21 64 Kwords 150000h–15FFFFh SA53 64 Kwords 350000h–35FFFFh SA22 64 Kwords 160000h–16FFFFh SA54 64 Kwords 360000h–36FFFFh SA23 64 Kwords 170000h–17FFFFh SA55 64 Kwords 370000h–37FFFFh SA24 64 Kwords 180000h–18FFFFh SA56 64 Kwords 380000h–38FFFFh SA25 64 Kwords 190000h–19FFFFh SA57 64 Kwords 390000h–39FFFFh SA26 64 Kwords 1A0000h–1AFFFFh SA58 64 Kwords 3A0000h–3AFFFFh SA27 64 Kwords 1B0000h–1BFFFFh SA59 64 Kwords 3B0000h–3BFFFFh SA28 64 Kwords 1C0000h–1CFFFFh SA60 64 Kwords 3C0000h–3CFFFFh SA29 64 Kwords 1D0000h–1DFFFFh SA61 64 Kwords 3D0000h–3DFFFFh SA30 64 Kwords 1E0000h–1EFFFFh SA62 64 Kwords 3E0000h–3EFFFFh SA31 64 Kwords 1F0000h–1FFFFFh SA63 64 Kwords 3F0000h–3FFFFFh Document Number: 002-01103 Rev. *A Bank 1 Bank 0 Bank Page 12 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 2 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA64 64 Kwords 400000h–40FFFFh SA96 64 K words 600000h–60FFFFh SA65 64 Kwords 410000h–41FFFFh SA97 64 K words 610000h–61FFFFh SA66 64 Kwords 420000h–42FFFFh SA98 64 K words 620000h–62FFFFh SA67 64 Kwords 430000h–43FFFFh SA99 64 K words 630000h–63FFFFh SA68 64 Kwords 440000h–44FFFFh SA100 64 K words 640000h–64FFFFh SA69 64 Kwords 450000h–45FFFFh SA101 64 K words 650000h–65FFFFh SA70 64 Kwords 460000h–46FFFFh SA102 64 K words 660000h–66FFFFh SA71 64 Kwords 470000h–47FFFFh SA103 64 K words 670000h–67FFFFh SA72 64 Kwords 480000h–48FFFFh SA104 64 K words 680000h–68FFFFh SA73 64 Kwords 490000h–49FFFFh SA105 64 K words 690000h–69FFFFh SA74 64 Kwords 4A0000h–4AFFFFh SA106 64 K words 6A0000h–6AFFFFh SA75 64 Kwords 4B0000h–4BFFFFh SA107 64 K words 6B0000h–6BFFFFh SA76 64 Kwords 4C0000h–4CFFFFh SA108 64 K words 6C0000h–6CFFFFh SA77 64 Kwords 4D0000h–4DFFFFh SA109 64 K words 6D0000h–6DFFFFh SA78 64 Kwords 4E0000h–4EFFFFh SA110 64 K words 6E0000h–6EFFFFh SA79 64 Kwords 4F0000h–4FFFFFh SA111 64 K words 6F0000h–6FFFFFh SA80 64 Kwords 500000h–50FFFFh SA112 64 K words 700000h–70FFFFh SA81 64 Kwords 510000h–51FFFFh SA113 64 K words 710000h–71FFFFh SA82 64 Kwords 520000h–52FFFFh SA114 64 K words 720000h–72FFFFh SA83 64 Kwords 530000h–53FFFFh SA115 64 K words 730000h–73FFFFh SA84 64 Kwords 540000h–54FFFFh SA116 64 K words 740000h–74FFFFh SA85 64 Kwords 550000h–55FFFFh SA117 64 K words 750000h–75FFFFh SA86 64 Kwords 560000h–56FFFFh SA118 64 K words 760000h–76FFFFh SA87 64 Kwords 570000h–57FFFFh SA119 64 K words 770000h–77FFFFh SA88 64 Kwords 580000h–58FFFFh SA120 64 K words 780000h–78FFFFh SA89 64 Kwords 590000h–59FFFFh SA121 64 K words 790000h–79FFFFh SA90 64 Kwords 5A0000h–5AFFFFh SA122 64 K words 7A0000h–7AFFFFh SA91 64 Kwords 5B0000h–5BFFFFh SA123 64 K words 7B0000h–7BFFFFh SA92 64 Kwords 5C0000h–5CFFFFh SA124 64 K words 7C0000h–7CFFFFh SA93 64 Kwords 5D0000h–5DFFFFh SA125 64 K words 7D0000h–7DFFFFh SA94 64 Kwords 5E0000h–5EFFFFh SA126 64 K words 7E0000h–7EFFFFh SA95 64 Kwords 5F0000h–5FFFFFh SA127 64 K words 7F0000h–7FFFFFh Document Number: 002-01103 Rev. *A Bank Bank 3 Bank 2 Bank Page 13 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 3 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA128 64 Kwords 800000h–80FFFFh Bank SA160 64 Kwords A00000h–A0FFFFh SA129 64 Kwords 810000h–81FFFFh SA161 64 Kwords A10000h–A1FFFFh SA130 64 Kwords 820000h–82FFFFh SA162 64 Kwords A20000h–A2FFFFh SA131 64 Kwords 830000h–83FFFFh SA163 64 Kwords A30000h–A3FFFFh SA132 64 Kwords 840000h–84FFFFh SA164 64 Kwords A40000h–A4FFFFh SA133 64 Kwords 850000h–85FFFFh SA165 64 Kwords A50000h–A5FFFFh SA134 64 Kwords 860000h–86FFFFh SA166 64 Kwords A60000h–A6FFFFh SA135 64 Kwords 870000h–87FFFFh SA167 64 Kwords A70000h–A7FFFFh SA136 64 Kwords 880000h–88FFFFh SA168 64 Kwords A80000h–A8FFFFh SA137 64 Kwords 890000h–89FFFFh SA169 64 Kwords A90000h–A9FFFFh SA138 64 Kwords 8A0000h–8AFFFFh SA170 64 Kwords AA0000h–AAFFFFh SA139 64 Kwords 8B0000h–8BFFFFh SA171 64 Kwords AB0000h–ABFFFFh SA140 64 Kwords 8C0000h–8CFFFFh SA172 64 Kwords AC0000h–ACFFFFh SA141 64 Kwords 8D0000h–8DFFFFh SA173 64 Kwords AD0000h–ADFFFFh SA142 64 Kwords 8E0000h–8EFFFFh SA143 64 Kwords 8F0000h–8FFFFFh SA144 64 Kwords 900000h–90FFFFh SA145 64 Kwords SA146 SA147 SA174 64 Kwords AE0000h–AEFFFFh SA175 64 Kwords AF0000h–AFFFFFh SA176 64 Kwords B00000h–B0FFFFh 910000h–91FFFFh SA177 64 Kwords B10000h–B1FFFFh 64 Kwords 920000h–92FFFFh SA178 64 Kwords B20000h–B2FFFFh 64 Kwords 930000h–93FFFFh SA179 64 Kwords B30000h–B3FFFFh SA148 64 Kwords 940000h–94FFFFh SA180 64 Kwords B40000h–B4FFFFh SA149 64 Kwords 950000h–95FFFFh SA181 64 Kwords B50000h–B5FFFFh SA150 64 Kwords 960000h–96FFFFh SA182 64 Kwords B60000h–B6FFFFh SA151 64 Kwords 970000h–97FFFFh SA183 64 Kwords B70000h–B7FFFFh SA152 64 Kwords 980000h–98FFFFh SA184 64 Kwords B80000h–B8FFFFh SA153 64 Kwords 990000h–99FFFFh SA185 64 Kwords B90000h–B9FFFFh SA154 64 Kwords 9A0000h–9AFFFFh SA186 64 Kwords BA0000h–BAFFFFh SA155 64 Kwords 9B0000h–9BFFFFh SA187 64 Kwords BB0000h–BBFFFFh SA156 64 Kwords 9C0000h–9CFFFFh SA188 64 Kwords BC0000h–BCFFFFh SA157 64 Kwords 9D0000h–9DFFFFh SA189 64 Kwords BD0000h–BDFFFFh SA158 64 Kwords 9E0000h–9EFFFFh SA190 64 Kwords BE0000h–BEFFFFh SA159 64 Kwords 9F0000h–9FFFFFh SA191 64 Kwords BF0000h–BFFFFFh Document Number: 002-01103 Rev. *A Bank 5 Bank 4 Bank Page 14 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 4 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA192 64 Kwords C00000h–C0FFFFh Bank SA224 64 K words E00000h–E0FFFFh SA193 64 Kwords C10000h–C1FFFFh SA225 64 K words E10000h–E1FFFFh SA194 64 Kwords C20000h–C2FFFFh SA226 64 K words E20000h–E2FFFFh SA195 64 Kwords C30000h–C3FFFFh SA227 64 K words E30000h–E3FFFFh SA196 64 Kwords C40000h–C4FFFFh SA228 64 K words E40000h–E4FFFFh SA197 64 Kwords C50000h–C5FFFFh SA229 64 K words E50000h–E5FFFFh SA198 64 Kwords C60000h–C6FFFFh SA230 64 K words E60000h–E6FFFFh SA199 64 Kwords C70000h–C7FFFFh SA231 64 K words E70000h–E7FFFFh SA200 64 Kwords C80000h–C8FFFFh SA232 64 K words E80000h–E8FFFFh SA201 64 Kwords C90000h–C9FFFFh SA233 64 K words E90000h–E9FFFFh SA202 64 Kwords CA0000h–CAFFFFh SA234 64 K words EA0000h–EAFFFFh SA203 64 Kwords CB0000h–CBFFFFh SA235 64 K words EB0000h–EBFFFFh SA204 64 Kwords CC0000h–CCFFFFh SA236 64 K words EC0000h–ECFFFFh SA205 64 Kwords CD0000h–CDFFFFh SA237 64 K words ED0000h–EDFFFFh SA206 64 Kwords CE0000h–CEFFFFh SA207 64 Kwords CF0000h–CFFFFFh SA208 64 Kwords D00000h–D0FFFFh SA209 64 Kwords SA238 64 K words EE0000h–EEFFFFh SA239 64 K words EF0000h–EFFFFFh SA240 64 K words F00000h–F0FFFFh D10000h–D1FFFFh SA241 64 K words F10000h–F1FFFFh F20000h–F2FFFFh Bank 7 Bank 6 Bank SA210 64 Kwords D20000h–D2FFFFh SA242 64 K words SA211 64 Kwords D30000h–D3FFFFh SA243 64 K words F30000h–F3FFFFh SA212 64 Kwords D40000h–D4FFFFh SA244 64 K words F40000h–F4FFFFh SA213 64 Kwords D50000h–D5FFFFh SA245 64 K words F50000h–F5FFFFh SA214 64 Kwords D60000h–D6FFFFh SA246 64 K words F60000h–F6FFFFh SA215 64 Kwords D70000h–D7FFFFh SA247 64 K words F70000h–F7FFFFh SA216 64 Kwords D80000h–D8FFFFh SA248 64 K words F80000h–F8FFFFh SA217 64 Kwords D90000h–D9FFFFh SA249 64 K words F90000h–F9FFFFh SA218 64 Kwords DA0000h–DAFFFFh SA250 64 K words FA0000h–FAFFFFh SA219 64 Kwords DB0000h–DBFFFFh SA251 64 K words FB0000h–FBFFFFh SA220 64 Kwords DC0000h–DCFFFFh SA252 64 K words FC0000h–FCFFFFh SA221 64 Kwords DD0000h–DDFFFFh SA253 64 K words FD0000h–FDFFFFh SA222 64 Kwords DE0000h–DEFFFFh SA254 64 K words FE0000h–FEFFFFh SA223 64 Kwords DF0000h–DFFFFFh SA255 64 K words FF0000h–FFFFFFh Document Number: 002-01103 Rev. *A Page 15 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 5 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA256 64 Kwords 1000000h-100FFFFh SA288 64 Kwords 1200000h-120FFFFh SA257 64 Kwords 1010000h-101FFFFh SA289 64 Kwords 1210000h-121FFFFh SA258 64 Kwords 1020000h-102FFFFh SA290 64 Kwords 1220000h-122FFFFh SA259 64 Kwords 1030000h-103FFFFh SA291 64 Kwords 1230000h-123FFFFh SA260 64 Kwords 1040000h-104FFFFh SA292 64 Kwords 1240000h-124FFFFh SA261 64 Kwords 1050000h-105FFFFh SA293 64 Kwords 1250000h-125FFFFh SA262 64 Kwords 1060000h-106FFFFh SA294 64 Kwords 1260000h-126FFFFh SA263 64 Kwords 1070000h-107FFFFh SA295 64 Kwords 1270000h-127FFFFh SA264 64 Kwords 1030000h-108FFFFh SA296 64 Kwords 1230000h-128FFFFh SA265 64 Kwords 1090000h-109FFFFh SA297 64 Kwords 1290000h-129FFFFh SA266 64 Kwords 10A0000h-10AFFFFh SA298 64 Kwords 12A0000h-12AFFFFh SA267 64 Kwords 10B0000h-10BFFFFh SA299 64 Kwords 12B0000h-12BFFFFh SA268 64 Kwords 10C0000h-10CFFFFh SA300 64 Kwords 12C0000h-12CFFFFh SA269 64 Kwords 10D0000h-10DFFFFh SA301 64 Kwords 12D0000h-12DFFFFh SA270 64 Kwords 10E0000h-10EFFFFh SA302 64 Kwords 12E0000h-12EFFFFh SA271 64 Kwords 10F0000h-10FFFFFh SA303 64 Kwords 12F0000h-12FFFFFh SA272 64 Kwords 1100000h-110FFFFh SA304 64 Kwords 1300000h-130FFFFh SA273 64 Kwords 1110000h-111FFFFh SA305 64 Kwords 1310000h-131FFFFh SA274 64 Kwords 1120000h-112FFFFh SA306 64 Kwords 1320000h-132FFFFh SA275 64 Kwords 1130000h-113FFFFh SA307 64 Kwords 1330000h-133FFFFh SA276 64 Kwords 1140000h-114FFFFh SA308 64 Kwords 1340000h-134FFFFh SA277 64 Kwords 1150000h-115FFFFh SA309 64 Kwords 1350000h-135FFFFh SA278 64 Kwords 1160000h-116FFFFh SA310 64 Kwords 1360000h-136FFFFh SA279 64 Kwords 1170000h-117FFFFh SA311 64 Kwords 1370000h-137FFFFh SA280 64 Kwords 1180000h-118FFFFh SA312 64 Kwords 1380000h-138FFFFh SA281 64 Kwords 1190000h-119FFFFh SA313 64 Kwords 1390000h-139FFFFh SA282 64 Kwords 11A0000h-11AFFFFh SA314 64 Kwords 13A0000h-13AFFFFh SA283 64 Kwords 11B0000h-11BFFFFh SA315 64 Kwords 13B0000h-13BFFFFh SA284 64 Kwords 11C0000h-11CFFFFh SA316 64 Kwords 13C0000h-13CFFFFh SA285 64 Kwords 11D0000h-11DFFFFh SA317 64 Kwords 13D0000h-13DFFFFh SA286 64 Kwords 11E0000h-11EFFFFh SA318 64 Kwords 13E0000h-13EFFFFh SA287 64 Kwords 11F0000h-11FFFFFh SA319 64 Kwords 13F0000h-13FFFFFh Document Number: 002-01103 Rev. *A Bank Bank 9 Bank 8 Bank Page 16 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 6 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA320 64 Kwords 1400000h-140FFFFh SA352 64 K words 1600000h-160FFFFh SA321 64 Kwords 1410000h-141FFFFh SA353 64 K words 1610000h-161FFFFh SA322 64 Kwords 1420000h-142FFFFh SA354 64 K words 1620000h-162FFFFh SA323 64 Kwords 1430000h-143FFFFh SA355 64 K words 1630000h-163FFFFh SA324 64 Kwords 1440000h-144FFFFh SA356 64 K words 1640000h-164FFFFh SA325 64 Kwords 1450000h-145FFFFh SA357 64 K words 1650000h-165FFFFh SA326 64 Kwords 1460000h-146FFFFh SA358 64 K words 1660000h-166FFFFh SA327 64 Kwords 1470000h-147FFFFh SA359 64 K words 1670000h-167FFFFh SA328 64 Kwords 1430000h-148FFFFh SA360 64 K words 1630000h-168FFFFh SA329 64 Kwords 1490000h-149FFFFh SA361 64 K words 1690000h-169FFFFh SA330 64 Kwords 14A0000h-14AFFFFh SA362 64 K words 16A0000h-16AFFFFh SA331 64 Kwords 14B0000h-14BFFFFh SA363 64 K words 16B0000h-16BFFFFh SA332 64 Kwords 14C0000h-14CFFFFh SA364 64 K words 16C0000h-16CFFFFh SA333 64 Kwords 14D0000h-14DFFFFh SA365 64 K words 16D0000h-16DFFFFh SA334 64 Kwords 14E0000h-14EFFFFh SA366 64 K words 16E0000h-16EFFFFh SA335 64 Kwords 14F0000h-14FFFFFh SA367 64 K words 16F0000h-16FFFFFh SA336 64 Kwords 1500000h-150FFFFh SA368 64 K words 1700000h-170FFFFh SA337 64 Kwords 1510000h-151FFFFh SA369 64 K words 1710000h-171FFFFh SA338 64 Kwords 1520000h-152FFFFh SA370 64 K words 1720000h-172FFFFh SA339 64 Kwords 1530000h-153FFFFh SA371 64 K words 1730000h-173FFFFh SA340 64 Kwords 1540000h-154FFFFh SA372 64 K words 1740000h-174FFFFh SA341 64 Kwords 1550000h-155FFFFh SA373 64 K words 1750000h-175FFFFh SA342 64 Kwords 1560000h-156FFFFh SA374 64 K words 1760000h-176FFFFh SA343 64 Kwords 1570000h-157FFFFh SA375 64 K words 1770000h-177FFFFh SA344 64 Kwords 1580000h-158FFFFh SA376 64 K words 1780000h-178FFFFh SA345 64 Kwords 1590000h-159FFFFh SA377 64 K words 1790000h-179FFFFh SA346 64 Kwords 15A0000h-15AFFFFh SA378 64 K words 17A0000h-17AFFFFh SA347 64 Kwords 15B0000h-15BFFFFh SA379 64 K words 17B0000h-17BFFFFh SA348 64 Kwords 15C0000h-15CFFFFh SA380 64 K words 15C0000h-17CFFFFh SA349 64 Kwords 15D0000h-15DFFFFh SA381 64 K words 17D0000h-17DFFFFh SA350 64 Kwords 15E0000h-15EFFFFh SA382 64 K words 17E0000h-17EFFFFh SA351 64 Kwords 15F0000h-15FFFFFh SA383 64 K words 17F0000h-17FFFFFh Document Number: 002-01103 Rev. *A Bank Bank 11 Bank 10 Bank Page 17 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 7 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA384 64 Kwords 1800000h-180FFFFh Bank SA416 64 Kwords 1A00000h-1A0FFFFh SA385 64 Kwords 1810000h-181FFFFh SA417 64 Kwords 1A10000h-1A1FFFFh SA386 64 Kwords 1820000h-182FFFFh SA418 64 Kwords 1A20000h-1A2FFFFh SA387 64 Kwords 1830000h-183FFFFh SA419 64 Kwords 1A30000h-1A3FFFFh SA388 64 Kwords 1840000h-184FFFFh SA420 64 Kwords 1A40000h-1A4FFFFh SA389 64 Kwords 1850000h-185FFFFh SA421 64 Kwords 1A50000h-1A5FFFFh SA390 64 Kwords 1860000h-186FFFFh SA422 64 Kwords 1A60000h-1A6FFFFh SA391 64 Kwords 1870000h-187FFFFh SA423 64 Kwords 1A70000h-1A7FFFFh SA392 64 Kwords 1830000h-188FFFFh SA424 64 Kwords 1A30000h-1A8FFFFh SA393 64 Kwords 1890000h-189FFFFh SA425 64 Kwords 1A90000h-1A9FFFFh SA394 64 Kwords 18A0000h-18AFFFFh SA426 64 Kwords 1AA0000h-1AAFFFFh SA395 64 Kwords 18B0000h-18BFFFFh SA427 64 Kwords 1AB0000h-1ABFFFFh SA396 64 Kwords 18C0000h-18CFFFFh SA428 64 Kwords 1AC0000h-1ACFFFFh SA397 64 Kwords 18D0000h-18DFFFFh SA429 64 Kwords 1AD0000h-1ADFFFFh SA398 64 Kwords 18E0000h-18EFFFFh SA430 64 Kwords 1AE0000h-1AEFFFFh SA399 64 Kwords 18F0000h-18FFFFFh SA431 64 Kwords 1AF0000h-1AFFFFFh SA400 64 Kwords 1900000h-190FFFFh SA432 64 Kwords 1B00000h-1B0FFFFh SA401 64 Kwords 1910000h-191FFFFh SA433 64 Kwords 1B10000h-1B1FFFFh SA402 64 Kwords 1920000h-192FFFFh SA434 64 Kwords 1B20000h-1B2FFFFh SA403 64 Kwords 1930000h-193FFFFh SA435 64 Kwords 1B30000h-1B3FFFFh SA404 64 Kwords 1940000h-194FFFFh SA436 64 Kwords 1B40000h-1B4FFFFh SA405 64 Kwords 1950000h-195FFFFh SA437 64 Kwords 1B50000h-1B5FFFFh SA406 64 Kwords 1960000h-196FFFFh SA438 64 Kwords 1B60000h-1B6FFFFh SA407 64 Kwords 1970000h-197FFFFh SA439 64 Kwords 1B70000h-1B7FFFFh SA408 64 Kwords 1980000h-198FFFFh SA440 64 Kwords 1B80000h-1B8FFFFh SA409 64 Kwords 1990000h-199FFFFh SA441 64 Kwords 1B90000h-1B9FFFFh Bank 13 Bank 12 Bank SA410 64 Kwords 19A0000h-19AFFFFh SA442 64 Kwords 1BA0000h-1BAFFFFh SA411 64 Kwords 19B0000h-19BFFFFh SA443 64 Kwords 1BB0000h-1BBFFFFh SA412 64 Kwords 19C0000h-19CFFFFh SA444 64 Kwords 1BC0000h-1BCFFFFh SA413 64 Kwords 19D0000h-19DFFFFh SA445 64 Kwords 1BD0000h-1BDFFFFh SA414 64 Kwords 19E0000h-19EFFFFh SA446 64 Kwords 1BE0000h-1BEFFFFh SA415 64 Kwords 19F0000h-19FFFFFh SA447 64 Kwords 1BF0000h-1BFFFFFh Document Number: 002-01103 Rev. *A Page 18 of 93 S29NS512P S29NS256P, S29NS128P Table 6.1 S29NS512P Sector and Memory Address Map (Sheet 8 of 8) Sector Sector Size Address Range Sector Sector Size Address Range SA448 64 Kwords 1C00000h-1C0FFFFh Bank SA480 64 K words 1E00000h-1E0FFFFh SA449 64 Kwords 1C10000h-1C1FFFFh SA481 64 K words 1E10000h-1E1FFFFh SA450 64 Kwords 1C20000h-1C2FFFFh SA482 64 K words 1E20000h-1E2FFFFh SA451 64 Kwords 1C30000h-1C3FFFFh SA483 64 K words 1E30000h-1E3FFFFh SA452 64 Kwords 1C40000h-1C4FFFFh SA484 64 K words 1E40000h-1E4FFFFh SA453 64 Kwords 1C50000h-1C5FFFFh SA485 64 K words 1E50000h-1E5FFFFh SA454 64 Kwords 1C60000h-1C6FFFFh SA486 64 K words 1E60000h-1E6FFFFh SA455 64 Kwords 1C70000h-1C7FFFFh SA487 64 K words 1E70000h-1E7FFFFh SA456 64 Kwords 1C30000h-1C8FFFFh SA488 64 K words 1E30000h-1E8FFFFh SA457 64 Kwords 1C90000h-1C9FFFFh SA489 64 K words 1E90000h-1E9FFFFh SA458 64 Kwords 1CA0000h-1CAFFFFh SA490 64 K words 1EA0000h-1EAFFFFh SA459 64 Kwords 1CB0000h-1CBFFFFh SA491 64 K words 1EB0000h-1EBFFFFh SA460 64 Kwords 1CC0000h-1CCFFFFh SA492 64 K words 1EC0000h-1ECFFFFh SA461 64 Kwords 1CD0000h-1CDFFFFh SA493 64 K words 1ED0000h-1EDFFFFh SA462 64 Kwords 1CE0000h-1CEFFFFh SA463 64 Kwords 1CF0000h-1CFFFFFh SA464 64 Kwords 1D00000h-1D0FFFFh SA465 64 Kwords SA466 SA467 SA494 64 K words 1EE0000h-1EEFFFFh SA495 64 K words 1EF0000h-1EFFFFFh SA496 64 K words 1F00000h-1F0FFFFh 1D10000h-1D1FFFFh SA497 64 K words 1F10000h-1F1FFFFh 64 Kwords 1D20000h-1D2FFFFh SA498 64 K words 1F20000h-1F2FFFFh 64 Kwords 1D30000h-1D3FFFFh SA499 64 K words 1F30000h-1F3FFFFh SA468 64 Kwords 1D40000h-1D4FFFFh SA500 64 K words 1F40000h-1F4FFFFh SA469 64 Kwords 1D50000h-1D5FFFFh SA501 64 K words 1F50000h-1F5FFFFh SA470 64 Kwords 1D60000h-1D6FFFFh SA502 64 K words 1F60000h-1F6FFFFh SA471 64 Kwords 1D70000h-1D7FFFFh SA503 64 K words 1F70000h-1F7FFFFh SA472 64 Kwords 1D80000h-1D8FFFFh SA504 64 K words 1F80000h-1F8FFFFh SA473 64 Kwords 1D90000h-1D9FFFFh SA505 64 K words 1F90000h-1F9FFFFh Bank 15 Bank 14 Bank SA474 64 Kwords 1DA0000h-1DAFFFFh SA506 64 K words 1FA0000h-1FAFFFFh SA475 64 Kwords 1DB0000h-1DBFFFFh SA507 64 K words 1FB0000h-1FBFFFFh SA476 64 Kwords 1DC0000h-1DCFFFFh SA508 64 K words 1FC0000h-1FCFFFFh SA477 64 Kwords 1DD0000h-1DDFFFFh SA509 64 K words 1FD0000h-1FDFFFFh SA478 64 Kwords 1DE0000h-1DEFFFFh SA510 64 K words 1FE0000h-1FEFFFFh SA479 64 Kwords 1DF0000h-1DFFFFFh SA511 64 K words 1FF0000h-1FFFFFFh Document Number: 002-01103 Rev. *A Page 19 of 93 S29NS512P S29NS256P, S29NS128P Table 6.2 S29NS256P Sector and Memory Address Map (Sheet 1 of 4) Sector Size Address Range Sector Sector Size Address Range SA0 64 Kwords 000000h–00FFFFh Bank SA32 64 Kwords 200000h–20FFFFh SA1 64 Kwords 010000h–01FFFFh SA33 64 Kwords 210000h–21FFFFh SA2 64 Kwords 020000h–02FFFFh SA34 64 Kwords 220000h–22FFFFh SA3 64 Kwords 030000h–03FFFFh SA35 64 Kwords 230000h–23FFFFh SA4 64 Kwords 040000h–04FFFFh SA36 64 Kwords 240000h–24FFFFh SA5 64 Kwords 050000h–05FFFFh SA37 64 Kwords 250000h–25FFFFh SA6 64 Kwords 060000h–06FFFFh SA38 64 Kwords 260000h–26FFFFh SA7 64 Kwords 070000h–07FFFFh SA39 64 Kwords 270000h–27FFFFh SA8 64 Kwords 080000h–08FFFFh SA40 64 Kwords 280000h–28FFFFh SA9 64 Kwords 090000h–09FFFFh SA41 64 Kwords 290000h–29FFFFh 2A0000h–2AFFFFh Bank 2 Sector SA10 64 Kwords 0A0000h–0AFFFFh SA42 64 Kwords SA11 64 Kwords 0B0000h–0BFFFFh SA43 64 Kwords 2B0000h–2BFFFFh SA12 64 Kwords 0C0000h–0CFFFFh SA44 64 Kwords 2C0000h–2CFFFFh SA13 64 Kwords 0D0000h–0DFFFFh SA45 64 Kwords 2D0000h–2DFFFFh SA14 64 Kwords 0E0000h–0EFFFFh SA46 64 Kwords 2E0000h–2EFFFFh SA15 64 Kwords 0F0000h–0FFFFFh SA47 64 Kwords 2F0000h–2FFFFFh SA16 64 Kwords 100000h–10FFFFh SA48 64 Kwords 300000h–30FFFFh SA17 64 Kwords 110000h–11FFFFh SA49 64 Kwords 310000h–31FFFFh SA18 64 Kwords 120000h–12FFFFh SA50 64 Kwords 320000h–32FFFFh SA19 64 Kwords 130000h–13FFFFh SA51 64 Kwords 330000h–33FFFFh SA20 64 Kwords 140000h–14FFFFh SA52 64 Kwords 340000h–34FFFFh SA21 64 Kwords 150000h–15FFFFh SA53 64 Kwords 350000h–35FFFFh SA22 64 Kwords 160000h–16FFFFh SA54 64 Kwords 360000h–36FFFFh SA23 64 Kwords 170000h–17FFFFh SA55 64 Kwords 370000h–37FFFFh SA24 64 Kwords 180000h–18FFFFh SA56 64 Kwords 380000h–38FFFFh SA25 64 Kwords 190000h–19FFFFh SA57 64 Kwords 390000h–39FFFFh SA26 64 Kwords 1A0000h–1AFFFFh SA58 64 Kwords 3A0000h–3AFFFFh SA27 64 Kwords 1B0000h–1BFFFFh SA59 64 Kwords 3B0000h–3BFFFFh SA28 64 Kwords 1C0000h–1CFFFFh SA60 64 Kwords 3C0000h–3CFFFFh SA29 64 Kwords 1D0000h–1DFFFFh SA61 64 Kwords 3D0000h–3DFFFFh SA30 64 Kwords 1E0000h–1EFFFFh SA62 64 Kwords 3E0000h–3EFFFFh SA31 64 Kwords 1F0000h–1FFFFFh SA63 64 Kwords 3F0000h–3FFFFFh Document Number: 002-01103 Rev. *A Bank 3 Bank 1 Bank 0 Bank Page 20 of 93 S29NS512P S29NS256P, S29NS128P Table 6.2 S29NS256P Sector and Memory Address Map (Sheet 2 of 4) Sector Size Address Range Sector Sector Size Address Range SA64 64 Kwords 400000h–40FFFFh SA96 64 K words 600000h–60FFFFh SA65 64 Kwords 410000h–41FFFFh SA97 64 K words 610000h–61FFFFh SA66 64 Kwords 420000h–42FFFFh SA98 64 K words 620000h–62FFFFh SA67 64 Kwords 430000h–43FFFFh SA99 64 K words 630000h–63FFFFh SA68 64 Kwords 440000h–44FFFFh SA100 64 K words 640000h–64FFFFh SA69 64 Kwords 450000h–45FFFFh SA101 64 K words 650000h–65FFFFh SA70 64 Kwords 460000h–46FFFFh SA102 64 K words 660000h–66FFFFh SA71 64 Kwords 470000h–47FFFFh SA103 64 K words 670000h–67FFFFh SA72 64 Kwords 480000h–48FFFFh SA104 64 K words 680000h–68FFFFh SA73 64 Kwords 490000h–49FFFFh SA105 64 K words 690000h–69FFFFh SA74 64 Kwords 4A0000h–4AFFFFh SA106 64 K words 6A0000h–6AFFFFh SA75 64 Kwords 4B0000h–4BFFFFh SA107 64 K words 6B0000h–6BFFFFh SA76 64 Kwords 4C0000h–4CFFFFh SA108 64 K words 6C0000h–6CFFFFh SA77 64 Kwords 4D0000h–4DFFFFh SA109 64 K words 6D0000h–6DFFFFh SA78 64 Kwords 4E0000h–4EFFFFh SA110 64 K words 6E0000h–6EFFFFh SA79 64 Kwords 4F0000h–4FFFFFh SA111 64 K words 6F0000h–6FFFFFh SA80 64 Kwords 500000h–50FFFFh SA112 64 K words 700000h–70FFFFh SA81 64 Kwords 510000h–51FFFFh SA113 64 K words 710000h–71FFFFh SA82 64 Kwords 520000h–52FFFFh SA114 64 K words 720000h–72FFFFh SA83 64 Kwords 530000h–53FFFFh SA115 64 K words 730000h–73FFFFh SA84 64 Kwords 540000h–54FFFFh SA116 64 K words 740000h–74FFFFh SA85 64 Kwords 550000h–55FFFFh SA117 64 K words 750000h–75FFFFh SA86 64 Kwords 560000h–56FFFFh SA118 64 K words 760000h–76FFFFh SA87 64 Kwords 570000h–57FFFFh SA119 64 K words 770000h–77FFFFh SA88 64 Kwords 580000h–58FFFFh SA120 64 K words 780000h–78FFFFh SA89 64 Kwords 590000h–59FFFFh SA121 64 K words 790000h–79FFFFh SA90 64 Kwords 5A0000h–5AFFFFh SA122 64 K words 7A0000h–7AFFFFh SA91 64 Kwords 5B0000h–5BFFFFh SA123 64 K words 7B0000h–7BFFFFh SA92 64 Kwords 5C0000h–5CFFFFh SA124 64 K words 7C0000h–7CFFFFh SA93 64 Kwords 5D0000h–5DFFFFh SA125 64 K words 7D0000h–7DFFFFh SA94 64 Kwords 5E0000h–5EFFFFh SA126 64 K words 7E0000h–7EFFFFh SA95 64 Kwords 5F0000h–5FFFFFh SA127 64 K words 7F0000h–7FFFFFh Document Number: 002-01103 Rev. *A Bank Bank 6 Sector Bank 7 Bank 5 Bank 4 Bank Page 21 of 93 S29NS512P S29NS256P, S29NS128P Table 6.2 S29NS256P Sector and Memory Address Map (Sheet 3 of 4) Sector Size Address Range Sector Sector Size Address Range SA128 64 Kwords 800000h–80FFFFh SA160 64 Kwords A00000h–A0FFFFh SA129 64 Kwords 810000h–81FFFFh SA161 64 Kwords A10000h–A1FFFFh SA130 64 Kwords 820000h–82FFFFh SA162 64 Kwords A20000h–A2FFFFh SA131 64 Kwords 830000h–83FFFFh SA163 64 Kwords A30000h–A3FFFFh SA132 64 Kwords 840000h–84FFFFh SA164 64 Kwords A40000h–A4FFFFh SA133 64 Kwords 850000h–85FFFFh SA165 64 Kwords A50000h–A5FFFFh SA134 64 Kwords 860000h–86FFFFh SA166 64 Kwords A60000h–A6FFFFh SA135 64 Kwords 870000h–87FFFFh SA167 64 Kwords A70000h–A7FFFFh SA136 64 Kwords 880000h–88FFFFh SA168 64 Kwords A80000h–A8FFFFh SA137 64 Kwords 890000h–89FFFFh SA169 64 Kwords A90000h–A9FFFFh SA138 64 Kwords 8A0000h–8AFFFFh SA170 64 Kwords AA0000h–AAFFFFh SA139 64 Kwords 8B0000h–8BFFFFh SA171 64 Kwords AB0000h–ABFFFFh SA140 64 Kwords 8C0000h–8CFFFFh SA172 64 Kwords AC0000h–ACFFFFh SA141 64 Kwords 8D0000h–8DFFFFh SA173 64 Kwords AD0000h–ADFFFFh SA142 64 Kwords 8E0000h–8EFFFFh SA174 64 Kwords AE0000h–AEFFFFh SA143 64 Kwords 8F0000h–8FFFFFh SA175 64 Kwords AF0000h–AFFFFFh SA144 64 Kwords 900000h–90FFFFh SA176 64 Kwords B00000h–B0FFFFh SA145 64 Kwords 910000h–91FFFFh SA177 64 Kwords B10000h–B1FFFFh SA146 64 Kwords 920000h–92FFFFh SA178 64 Kwords B20000h–B2FFFFh SA147 64 Kwords 930000h–93FFFFh SA179 64 Kwords B30000h–B3FFFFh SA148 64 Kwords 940000h–94FFFFh SA180 64 Kwords B40000h–B4FFFFh SA149 64 Kwords 950000h–95FFFFh SA181 64 Kwords B50000h–B5FFFFh SA150 64 Kwords 960000h–96FFFFh SA182 64 Kwords B60000h–B6FFFFh SA151 64 Kwords 970000h–97FFFFh SA183 64 Kwords B70000h–B7FFFFh SA152 64 Kwords 980000h–98FFFFh SA184 64 Kwords B80000h–B8FFFFh SA153 64 Kwords 990000h–99FFFFh SA185 64 Kwords B90000h–B9FFFFh SA154 64 Kwords 9A0000h–9AFFFFh SA186 64 Kwords BA0000h–BAFFFFh SA155 64 Kwords 9B0000h–9BFFFFh SA187 64 Kwords BB0000h–BBFFFFh SA156 64 Kwords 9C0000h–9CFFFFh SA188 64 Kwords BC0000h–BCFFFFh SA157 64 Kwords 9D0000h–9DFFFFh SA189 64 Kwords BD0000h–BDFFFFh SA158 64 Kwords 9E0000h–9EFFFFh SA190 64 Kwords BE0000h–BEFFFFh SA159 64 Kwords 9F0000h–9FFFFFh SA191 64 Kwords BF0000h–BFFFFFh Document Number: 002-01103 Rev. *A Bank Bank 10 Sector Bank 11 Bank 9 Bank 8 Bank Page 22 of 93 S29NS512P S29NS256P, S29NS128P Table 6.2 S29NS256P Sector and Memory Address Map (Sheet 4 of 4) Sector Size Address Range Sector Sector Size Address Range SA192 64 Kwords C00000h–C0FFFFh Bank SA224 64 K words E00000h–E0FFFFh SA193 64 Kwords C10000h–C1FFFFh SA225 64 K words E10000h–E1FFFFh SA194 64 Kwords C20000h–C2FFFFh SA226 64 K words E20000h–E2FFFFh SA195 64 Kwords C30000h–C3FFFFh SA227 64 K words E30000h–E3FFFFh SA196 64 Kwords C40000h–C4FFFFh SA228 64 K words E40000h–E4FFFFh SA197 64 Kwords C50000h–C5FFFFh SA229 64 K words E50000h–E5FFFFh SA198 64 Kwords C60000h–C6FFFFh SA230 64 K words E60000h–E6FFFFh SA199 64 Kwords C70000h–C7FFFFh SA231 64 K words E70000h–E7FFFFh SA200 64 Kwords C80000h–C8FFFFh SA232 64 K words E80000h–E8FFFFh SA201 64 Kwords C90000h–C9FFFFh SA233 64 K words E90000h–E9FFFFh SA202 64 Kwords CA0000h–CAFFFFh SA234 64 K words EA0000h–EAFFFFh SA203 64 Kwords CB0000h–CBFFFFh SA235 64 K words EB0000h–EBFFFFh SA204 64 Kwords CC0000h–CCFFFFh SA236 64 K words EC0000h–ECFFFFh SA205 64 Kwords CD0000h–CDFFFFh SA237 64 K words ED0000h–EDFFFFh SA206 64 Kwords CE0000h–CEFFFFh SA238 64 K words EE0000h–EEFFFFh SA207 64 Kwords CF0000h–CFFFFFh SA239 64 K words EF0000h–EFFFFFh SA208 64 Kwords D00000h–D0FFFFh SA240 64 K words F00000h–F0FFFFh SA209 64 Kwords D10000h–D1FFFFh SA241 64 K words F10000h–F1FFFFh F20000h–F2FFFFh Bank 14 Sector SA210 64 Kwords D20000h–D2FFFFh SA242 64 K words SA211 64 Kwords D30000h–D3FFFFh SA243 64 K words F30000h–F3FFFFh SA212 64 Kwords D40000h–D4FFFFh SA244 64 K words F40000h–F4FFFFh SA213 64 Kwords D50000h–D5FFFFh SA245 64 K words F50000h–F5FFFFh SA214 64 Kwords D60000h–D6FFFFh SA246 64 K words F60000h–F6FFFFh SA215 64 Kwords D70000h–D7FFFFh SA247 64 K words F70000h–F7FFFFh SA216 64 Kwords D80000h–D8FFFFh SA248 64 K words F80000h–F8FFFFh SA217 64 Kwords D90000h–D9FFFFh SA249 64 K words F90000h–F9FFFFh Bank 15 Bank 13 Bank 12 Bank SA218 64 Kwords DA0000h–DAFFFFh SA250 64 K words FA0000h–FAFFFFh SA219 64 Kwords DB0000h–DBFFFFh SA251 64 K words FB0000h–FBFFFFh SA220 64 Kwords DC0000h–DCFFFFh SA252 64 K words FC0000h–FCFFFFh SA221 64 Kwords DD0000h–DDFFFFh SA253 64 K words FD0000h–FDFFFFh SA222 64 Kwords DE0000h–DEFFFFh SA254 64 K words FE0000h–FEFFFFh SA223 64 Kwords DF0000h–DFFFFFh SA255 16 K words FF0000h–FF3FFFh SA256 16 K words FF4000h–FF7FFFh SA257 16 K words FF8000h–FFBFFFh SA258 16 K words FFC000h–FFFFFFh Document Number: 002-01103 Rev. *A Page 23 of 93 S29NS512P S29NS256P, S29NS128P Table 6.3 S29NS128P Sector & Memory Address Map (Sheet 1 of 2) Sector Size Address Range Sector Sector Size Address Range SA0 64 Kwords 000000h–00FFFFh Bank SA32 64 Kwords 200000h–20FFFFh SA1 64 Kwords 010000h–01FFFFh SA33 64 Kwords 210000h–21FFFFh SA2 64 Kwords 020000h–02FFFFh SA34 64 Kwords 220000h–22FFFFh SA3 64 Kwords 030000h–03FFFFh SA35 64 Kwords 230000h–23FFFFh SA4 64 Kwords 040000h–04FFFFh SA36 64 Kwords 240000h–24FFFFh SA5 64 Kwords 050000h–05FFFFh SA37 64 Kwords 250000h–25FFFFh SA6 64 Kwords 060000h–06FFFFh SA38 64 Kwords 260000h–26FFFFh SA7 64 Kwords 070000h–07FFFFh SA39 64 Kwords 270000h–27FFFFh SA8 64 Kwords 080000h–08FFFFh SA40 64 Kwords 280000h–28FFFFh SA9 64 Kwords 090000h–09FFFFh SA41 64 Kwords 290000h–29FFFFh SA42 64 Kwords 2A0000h–2AFFFFh SA43 64 Kwords 2B0000h–2BFFFFh SA44 64 Kwords 2C0000h–2CFFFFh SA45 64 Kwords 2D0000h–2DFFFFh Bank 4 Sector 64 Kwords 0A0000h–0AFFFFh SA11 64 Kwords 0B0000h–0BFFFFh SA12 64 Kwords 0C0000h–0CFFFFh SA13 64 Kwords 0D0000h–0DFFFFh SA14 64 Kwords 0E0000h–0EFFFFh SA46 64 Kwords 2E0000h–2EFFFFh SA15 64 Kwords 0F0000h–0FFFFFh SA47 64 Kwords 2F0000h–2FFFFFh SA16 64 Kwords 100000h–10FFFFh SA48 64 Kwords 300000h–30FFFFh SA17 64 Kwords 110000h–11FFFFh SA49 64 Kwords 310000h–31FFFFh SA18 64 Kwords 120000h–12FFFFh SA50 64 Kwords 320000h–32FFFFh SA19 64 Kwords 130000h–13FFFFh SA51 64 Kwords 330000h–33FFFFh SA20 64 Kwords 140000h–14FFFFh SA52 64 Kwords 340000h–34FFFFh SA21 64 Kwords 150000h–15FFFFh SA53 64 Kwords 350000h–35FFFFh SA22 64 Kwords 160000h–16FFFFh SA54 64 Kwords 360000h–36FFFFh SA23 64 Kwords 170000h–17FFFFh SA55 64 Kwords 370000h–37FFFFh SA24 64 Kwords 180000h–18FFFFh SA56 64 Kwords 380000h–38FFFFh SA25 64 Kwords 190000h–19FFFFh SA57 64 Kwords 390000h–39FFFFh SA26 64 Kwords 1A0000h–1AFFFFh SA58 64 Kwords 3A0000h–3AFFFFh SA27 64 Kwords 1B0000h–1BFFFFh SA59 64 Kwords 3B0000h–3BFFFFh SA28 64 Kwords 1C0000h–1CFFFFh SA60 64 Kwords 3C0000h–3CFFFFh SA29 64 Kwords 1D0000h–1DFFFFh SA61 64 Kwords 3D0000h–3DFFFFh SA30 64 Kwords 1E0000h–1EFFFFh SA62 64 Kwords 3E0000h–3EFFFFh SA31 64 Kwords 1F0000h–1FFFFFh SA63 64 Kwords 3F0000h–3FFFFFh SA64 64 Kwords 400000h–40FFFFh SA96 64 K words 600000h–60FFFFh SA65 64 Kwords 410000h–41FFFFh SA97 64 K words 610000h–61FFFFh SA66 64 Kwords 420000h–42FFFFh SA98 64 K words 620000h–62FFFFh SA67 64 Kwords 430000h–43FFFFh SA99 64 K words 630000h–63FFFFh SA68 64 Kwords 440000h–44FFFFh SA100 64 K words 640000h–64FFFFh SA69 64 Kwords 450000h–45FFFFh SA101 64 K words 650000h–65FFFFh SA70 64 Kwords 460000h–46FFFFh SA102 64 K words 660000h–66FFFFh SA71 64 Kwords 470000h–47FFFFh SA103 64 K words 670000h–67FFFFh Document Number: 002-01103 Rev. *A Bank 7 Bank 6 Bank 5 SA10 Bank 12 Bank 8 Bank 3 Bank 2 Bank 1 Bank 0 Bank Page 24 of 93 S29NS512P S29NS256P, S29NS128P Table 6.3 S29NS128P Sector & Memory Address Map (Sheet 2 of 2) Sector Size Address Range Sector Sector Size Address Range SA72 64 Kwords 480000h–48FFFFh SA104 64 K words 680000h–68FFFFh SA73 64 Kwords 490000h–49FFFFh SA105 64 K words 690000h–69FFFFh SA74 64 Kwords 4A0000h–4AFFFFh SA106 64 K words 6A0000h–6AFFFFh SA75 64 Kwords 4B0000h–4BFFFFh SA107 64 K words 6B0000h–6BFFFFh SA76 64 Kwords 4C0000h–4CFFFFh SA108 64 K words 6C0000h–6CFFFFh SA77 64 Kwords 4D0000h–4DFFFFh SA109 64 K words 6D0000h–6DFFFFh SA78 64 Kwords 4E0000h–4EFFFFh SA110 64 K words 6E0000h–6EFFFFh SA79 64 Kwords 4F0000h–4FFFFFh SA111 64 K words 6F0000h–6FFFFFh SA80 64 Kwords 500000h–50FFFFh SA112 64 K words 700000h–70FFFFh SA81 64 Kwords 510000h–51FFFFh SA113 64 K words 710000h–71FFFFh SA82 64 Kwords 520000h–52FFFFh SA114 64 K words 720000h–72FFFFh SA83 64 Kwords 530000h–53FFFFh SA115 64 K words 730000h–73FFFFh SA84 64 Kwords 540000h–54FFFFh SA116 64 K words 740000h–74FFFFh SA85 64 Kwords 550000h–55FFFFh SA117 64 K words 750000h–75FFFFh SA86 64 Kwords 560000h–56FFFFh SA118 64 K words 760000h–76FFFFh SA87 64 Kwords 570000h–57FFFFh SA119 64 K words 770000h–77FFFFh SA88 64 Kwords 580000h–58FFFFh SA120 64 K words 780000h–78FFFFh SA89 64 Kwords 590000h–59FFFFh SA121 64 K words 790000h–79FFFFh SA90 64 Kwords 5A0000h–5AFFFFh SA122 64 K words 7A0000h–7AFFFFh SA91 64 Kwords 5B0000h–5BFFFFh SA123 64 K words 7B0000h–7BFFFFh SA92 64 Kwords 5C0000h–5CFFFFh SA124 64 K words 7C0000h–7CFFFFh SA93 64 Kwords 5D0000h–5DFFFFh SA125 64 K words 7D0000h–7DFFFFh SA94 64 Kwords 5E0000h–5EFFFFh SA95 64 Kwords 5F0000h–5FFFFFh Document Number: 002-01103 Rev. *A Bank Bank 14 Bank 13 Sector Bank 15 Bank 11 Bank 10 Bank 9 Bank SA126 64 K words 7E0000h–7EFFFFh SA127 16 K words 7F0000h–7F3FFFh SA128 16 K words 7F4000h–7F7FFFh SA129 16 K words 7F8000h–7FBFFFh SA130 16 K words 7FC000h–7FFFFFh Page 25 of 93 S29NS512P S29NS256P, S29NS128P 7. Device Operations This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Tables 12.1 and 12.2). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 7.1 Device Operation Table The device must be setup appropriately for each operation. Table 7.1 describes the required state of each control pin for any particular operation. Table 7.1 Device Operations Amax– A16 A/DQ15– A/DQ0 RDY RESET# X Addr In I/O H H X Addr In I/O H H X X High-Z High-Z H X X High-Z High-Z H L Addr In Addr In X H L H H X I/O H H H X H X X X High-Z High-Z H Terminate current Burst read cycle via RESET# X X H X X X High-Z High-Z L Terminate current Burst read cycle and start new Burst read cycle L X H Addr In Addr In X H Operation CE# OE# WE# CLK Asynchronous Read – Addresses Latched L L H Asynchronous Write L H Standby (CE#) H X X X Hardware Reset X X X X Latch Starting Burst Address by CLK L H Advance Burst read to next address L Terminate current Burst read cycle AVD# Burst Read Operations Legend L = Logic 0, H = Logic 1, X = can be either VIL or VIH., = rising edge, = high to low, = toggle. Notes 1. Address is latched on the rising edge of clock. 2. CLK must stay low or high after CE# goes low when device in Asynchronous Read mode. 7.2 Asynchronous Read All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. To read data from the memory array, the system must first assert a valid address while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. The data is output on A/DQ15 – A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#. Document Number: 002-01103 Rev. *A Page 26 of 93 S29NS512P S29NS256P, S29NS128P 7.3 Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for Asynchronous read and can be automatically enabled for burst mode and the address is latched on the first rising edge of CLK input, while AVD# is held low for one clock cycle. Prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal transitions with valid data. The system would then write the configuration register command sequence. At startup the system writes the Set Configuration Register command sequence to optimize the system performance. The data is output tIACC after the rising edge of the first CLK. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that data is output only at the rising edge of the clock. RDY indicates the initial latency. Note that the device has a fixed internal address boundary that occurs every 128 words. No boundary crossing latency is required when the device operates with wait states set from 2 to 9. 7.3.1 Latency Tables for Variable Wait State Tables 7.2 – 7.9 show the latency for variable wait state in a normal Burst operation. Table 7.2 Address Latency for 9 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 1 ws D8 2 D2 D3 D4 D5 D6 D7 1 ws 1 ws D8 3 D3 D4 D5 D6 D7 1 ws 1 ws 1 ws D8 4 D4 D5 D6 D7 1 ws 1 ws 1 ws 1 ws D8 5 D5 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws D8 6 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 7 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 9 ws Table 7.3 Address Latency for 8 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 1 ws D8 D9 D9 3 D3 D4 D5 D6 D7 1 ws 1 ws D8 4 D4 D5 D6 D7 1 ws 1 ws 1 ws D8 D9 5 D5 D6 D7 1 ws 1 ws 1 ws 1 ws D8 D9 6 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws D8 D9 7 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D9 8 ws Document Number: 002-01103 Rev. *A Page 27 of 93 S29NS512P S29NS256P, S29NS128P Table 7.4 Address Latency for 7 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 D8 D9 D10 3 D3 D4 D5 D6 D7 1 ws D8 D9 D10 4 D4 D5 D6 D7 1 ws 1 ws D8 D9 D10 5 D5 D6 D7 1 ws 1 ws 1 ws D8 D9 D10 6 D6 D7 1 ws 1 ws 1 ws 1 ws D8 D9 D10 7 D7 1 ws 1 ws 1 ws 1 ws 1 ws D8 D9 D10 7 ws Table 7.5 Address Latency for 6 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 3 D3 D4 D5 D6 D7 D8 D9 D10 4 D4 D5 D6 D7 1 ws D8 D9 D10 D11 5 D5 D6 D7 1 ws 1 ws D8 D9 D10 D11 6 D6 D7 1 ws 1 ws 1 ws D8 D9 D10 D11 7 D7 1 ws 1 ws 1 ws 1 ws D8 D9 D10 D11 6 ws Table 7.6 Address Latency for 5 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 D8 D9 D10 3 D3 D4 D5 D6 D7 D8 D9 D10 D11 5 ws 4 D4 D5 D6 D7 D8 D9 D10 D11 D12 5 D5 D6 D7 1 ws D8 D9 D10 D11 D12 6 D6 D7 1 ws 1 ws D8 D9 D10 D11 D12 7 D7 1 ws 1 ws 1 ws D8 D9 D10 D11 D12 D8 Table 7.7 Address Latency for 4 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 D8 D9 D10 3 D3 D4 D5 D6 D7 D8 D9 D10 D11 4 D4 D5 D6 D7 D8 D9 D10 D11 D12 5 D5 D6 D7 D8 D9 D10 D11 D12 D13 6 D6 D7 1 ws D8 D9 D10 D11 D12 D13 7 D7 1 ws 1 ws D8 D9 D10 D11 D12 D13 4 ws Document Number: 002-01103 Rev. *A Page 28 of 93 S29NS512P S29NS256P, S29NS128P Table 7.8 Address Latency for 3 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 D8 D9 D10 3 D3 D4 D5 D6 D7 D8 D9 D10 D11 4 D4 D5 D6 D7 D8 D9 D10 D11 D12 5 D5 D6 D7 D8 D9 D10 D11 D12 D13 6 D6 D7 D8 D9 D10 D11 D12 D13 D14 7 D7 1 ws D8 D9 D10 D11 D12 D13 D14 3 ws Table 7.9 Address Latency for 2 Wait States Word Initial Wait 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 D2 D3 D4 D5 D6 D7 D8 D9 D10 3 D3 D4 D5 D6 D7 D8 D9 D10 D11 4 D4 D5 D6 D7 D8 D9 D10 D11 D12 5 D5 D6 D7 D8 D9 D10 D11 D12 D13 6 D6 D7 D8 D9 D10 D11 D12 D13 D14 7 D7 D8 D9 D10 D11 D12 D13 D14 D15 2 ws Document Number: 002-01103 Rev. *A Page 29 of 93 S29NS512P S29NS256P, S29NS128P Figure 7.1 Synchronous Read Flow Chart Note: Setup Configuration Register parameters Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Set Configuration Registers Command and Settings: Address 555h, Data D0h Address X00h, Data CR0-CR1 Load Initial Address Address = RA Wait tIACC + Programmable Wait State Setting Read Initial Data RD = DQ[15:0] Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing Unlock Cycle 1 Unlock Cycle 2 Command Cycle CR = Configuration Registers RA = Read Address CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles RD = Read Data Refer to the Latency tables. Read Next Data RD = DQ[15:0] Delay X Clocks Yes Crossing Boundary? No End of Data? Yes Completed 7.3.2 Continuous Burst Read Mode In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wraps around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the device. If the address being read crosses a 128-word line boundary within the same bank, but not into a program or erase suspended sector, as mentioned above, additional latency cycles are required as reflected by the configuration register table (Table 7.11) and Tables 7.2 – 7.9. If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse. Document Number: 002-01103 Rev. *A Page 30 of 93 S29NS512P S29NS256P, S29NS128P 7.3.3 8-Word, 16-Word, and 32-Word Linear Burst Read with Wrap Around In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 7.10). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 38-3Fh, and the burst sequence is 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. Table 7.10 Burst Address Groups Mode Group Size Group Address Ranges 8-word 8 words 0 – 7h, 8 – Fh, 10 – 17h,... 16-word 16 words 0 – Fh, 10 – 1Fh, 20 – 2Fh,... 32-word 32 words 00 – 1Fh, 20 – 3Fh, 40 – 5Fh,... 7.3.4 8-Word, 16-Word, and 32-Word Linear Burst without Wrap Around If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 3C-43h, and the burst sequence is 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which incurs the additional boundary crossing wait state. 7.3.5 Configuration Registers This device uses two 16-bit configuration registers to set various operational parameters. Upon power-up or hardware reset, the device is capable of the asynchronous read mode and synchronous read, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence before attempting burst operations. The Configuration Register can also be read using a command sequence (see Table 12.1). The following list describes the register settings. Table 7.11 Configuration Register CR Bit Function CR0.15 Reserved (Not used) 0 = Reserved (Default) 1 = Reserved Settings (Binary) CR0.14 Reserved (Not used) 0 = Reserved (Default) 1 = Reserved Document Number: 002-01103 Rev. *A Page 31 of 93 S29NS512P S29NS256P, S29NS128P Table 7.11 Configuration Register CR Bit Function Settings (Binary) 0000 2nd 0001 3rd CR1.0 0010 = CR0.13 0011 initial data is valid on the 4th 5th 0100 6th 0101 7th rising CLK edge AVD# transition to VIH CR0.12 Programmable Wait State (Note 1) 0110 = 1000 = 1001 initial data is valid on the 8th 9th rising CLK edge AVD# transition to VIH rising CLK edge AVD# transition to VIH (Default) … CR0.11 Reserved 0111 1101 = initial data is valid on the 13th 1110 = Reserved 1111 0 = RDY signal is active low 1 = RDY signal is active high (Default) CR0.10 RDY Polarity CR0.9 Reserved (Not used) CR0.8 RDY CR0.7 Reserved (Not used) 0 = Reserved 1 = Reserved (Default) CR0.6 Reserved (Not used) 0 = Reserved 1 = Reserved (Default) CR0.5 Reserved (Not used) 0 = Reserved (Default) 1 = Reserved CR1.4 Output Drive Strength CR0.4 RDY Function CR0.3 Burst Wrap Around 0 = Reserved 1 = Reserved (Default) 0 = RDY active one clock cycle before data 1 = RDY active with data (Default) 0 = Full Drive= Current Driver Strength (Default) 1 = Half Drive 0 = RDY (Default) 1 = Reserved 0 = No Wrap Around Burst 1 = Wrap Around Burst (Default) 000 = Continuous (Default) CR0.2 010 = 8-Word Linear Burst CR0.1 CR0.0 Burst Length 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes 1. The addresses are latched by rising edge of CLK. 2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default). 3. A software reset command is required after read command. 4. CR0.3 is ignored if in continuous read mode (no wrap around). Document Number: 002-01103 Rev. *A Page 32 of 93 S29NS512P S29NS256P, S29NS128P 7.4 Autoselect The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in the system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 7.12). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle select the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode.  To access the Autoselect codes, the host system must issue the Autoselect command.  The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspendread mode.  The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode.  The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). See Table 12.1 for command sequence details. Table 7.12 Autoselect Addresses Description Address Read Data Manufacturer ID Byte 00 (BA) + 00h 0001h Device ID, Byte 01 (BA) + 01h 307Eh (NS512P) 317Eh (NS256P) 327Eh (NS128P) Sector Lock/Unlock Byte 02 (SA) + 02h 0001h = Locked, 0000h = Unlocked DQ15 – DQ8 = reserved DQ7 – Factory Lock Bit; 1 = Locked, 0 = Not Locked DQ6 – Customer Lock Bit; 1 = Locked, 0 = Not Locked Indicator Bits Byte 07 (BA) + 07h DQ5 – Handshake Bit; 1 = Reserved, 0 = Standard Handshake DQ4 and DQ3 – WP# Protection Boot Code; 01 = WP# Protects Top Boot Sectors, DQ2 – DQ0 = reserved Device ID, Byte 0E (BA) + 0Eh 303Fh (NS512P) 3141h (NS256P) 3243h (NS128P) Device ID, Byte 0F (BA) + 0Fh 3000h (NS512P) 3100h (NS256P) 3200h (NS128P) Document Number: 002-01103 Rev. *A Page 33 of 93 S29NS512P S29NS256P, S29NS128P Software Functions and Sample Code Table 7.13 Autoselect Entry (LLD Function = lld_AutoselectEntryCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write BA+AAAh BA+555h 0x00AAh Unlock Cycle 2 Write BA+555h BA+2AAh 0x0055h Autoselect Command Write BA+AAAh BA+555h 0x0090h Table 7.14 Autoselect Exit (LLD Function = lld_AutoselectExitCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write base + xxxxh base + xxxxh 0x00F0h Notes 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address. The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ Document Number: 002-01103 Rev. *A Page 34 of 93 S29NS512P S29NS256P, S29NS128P 7.5 Program/Erase Operations These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices can be setup appropriately as outlined in the configuration register (Table 7.11). For any program and or erase operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. All addresses are latched on the rising edge of AVD# or falling edge of WE#, and all data is latched on the first rising edge of WE#. Note the following:  When the Embedded Program/Erase algorithm is complete, the device returns to the read mode.  The system can determine the status of the Program/Erase operation. Refer to the Write Operation Status section for further information.  While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt is ignored as only an erase operation can covert a 0 to a 1.  Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except the Program/ Erase Suspend command.  Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress.  A hardware reset or power removal immediately terminates the Program/Erase operation and the Program/Erase command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity.  Programming is allowed in any sequence and across sector boundaries only for single word programming operation. See Section 7.5.2, Write Buffer Programming on page 37 when using the write buffer. Note: The system may also lock or unlock any sector while the erase operation is suspended. 7.5.1 Single Word Programming Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. While the single word programming method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 12.1 for the required bus cycles and Figure 7.2 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Document Number: 002-01103 Rev. *A Page 35 of 93 S29NS512P S29NS256P, S29NS128P Figure 7.2 Single Word Program Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Program Command: Address 555h, Data A0h Setup Command Program Address (PA), Program Data (PD) Program Data to Address: PA, PD Perform Polling Algorithm (see Write Operation Status flowchart) Polling Status = Busy? Yes No Yes Polling Status = Complete? Error condition (Exceeded Timing Limits) No Operation successfully completed Operation failed Software Functions and Sample Code Table 7.15 Single Word Program (LLD Function = lld_ProgramCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h Program Setup Write Base + AAAh Base + 555h 00A0h Program Write Word Address Word Address Data Word Note Base = Base Address. The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. Document Number: 002-01103 Rev. *A Page 36 of 93 S29NS512P S29NS256P, S29NS128P /* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ 7.5.2 = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */ Write Buffer Programming Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of word locations minus 1 that is loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Note: the size of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must be in sequential order. The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer. It is to be noted that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after the Write to Buffer command is executed. Also, the starting address must be the least significant address and must be incremental and that the write buffer data cannot be in different sectors. After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations must be loaded in sequential order starting with the lowest address in the page. Note that if the number of address/ data pairs do not match the word count, the program buffer to flash command is ignored. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter decrements for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command is programmed into the device. It is the software’s responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED in the following ways:  Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is not valid in this condition).  Write to an address in a sector different than the one specified during the Write-Buffer-Load command.  Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation.  Write data other than the Confirm Command after the specified number of data load cycles. Software Functions and Sample Code Document Number: 002-01103 Rev. *A Page 37 of 93 S29NS512P S29NS256P, S29NS128P Table 7.16 Write Buffer Program (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle Description Operation Byte Address Word Address Data 1 Unlock Write Base + AAAh Base + 555h 00AAh Base + 554h Base + 2AAh 2 Unlock Write 3 Write Buffer Load Command Write Program Address 0025h 0055h 4 Write Word Count Write Program Address Word Count (N–1)h Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Load Buffer Word N Write Program Address, Word N Word N Last Write Buffer to Flash Write Sector Address 0029h Notes 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same write buffer. */ /* A write buffer begins at addresses evenly divisible */ /* by 0x20. UINT16 i; */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)dst ) = wc; /* write word count (minus 1) */ for (i=0;i n=14) 54h 0014h Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns (for example, 10 µs => n=14) 55h 0005h Erase Suspend Time-out Maximum 2N s 56h 0005h Program Suspend Time-out Maximum 2N s 57h 0010h Bank Organization: X = Number of banks 58h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 0 Region Information. X = Number of sectors in bank 59h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 1 Region Information. X = Number of sectors in bank 5Ah 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 2 Region Information. X = Number of sectors in bank 5Bh 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 3 Region Information. X = Number of sectors in bank 5Ch 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 4 Region Information. X = Number of sectors in bank 5Dh 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 5 Region Information. X = Number of sectors in bank 5Eh 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 6 Region Information. X = Number of sectors in bank 5Fh 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 7 Region Information. X = Number of sectors in bank 60h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 8 Region Information. X = Number of sectors in bank 61h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 9 Region Information. X = Number of sectors in bank 62h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 10 Region Information. X = Number of sectors in bank 63h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 11 Region Information. X = Number of sectors in bank 64h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 12 Region Information. X = Number of sectors in bank 65h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 13 Region Information. X = Number of sectors in bank 66h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) Bank 14 Region Information. X = Number of sectors in bank 67h 000Bh (NS128P) 0013h (NS256P) 0020h (NS512P) Bank 15 Region Information. X = Number of sectors in bank Document Number: 002-01103 Rev. *A Page 88 of 93 S29NS512P S29NS256P, S29NS128P 13. Revision History Spansion Publication Number: 002-01103 Section Description Revision A (June 29, 2006) Initial release Revision A1 (February 20, 2007) The tAVDS specification is changed from 4 ns to 5 ns The wait state for 83 MHz is changed to 8 ICC3(Max) is changed to 70 µA and ICC6(Max) is changed to 40 µA VIL (Min) is changed to -0.2 V tOE (Max) in both Asynchronous & Synchronous modes is changed to 9 ns across all frequencies tCEZ (Max) is changed to 10 ns across all frequencies Global tOEZ (Max) in both Asynchronous & Synchronous modes is changed to 10 ns across all frequencies tACH(Min) is changed to 6 ns (66 MHz) and 5 ns (83 MHz and 108 MHz) tRDY(Max) is changed to 10 ns tRACC(Max) is changed to 7.6 ns for 108 MHz tOEH(Min) in Asynchronous mode is changed to 10 ns for 108 MHz Erase and Programing Performance table is updated tCE in Asynchronous mode is changed to 83ns Revision A2 (June 6, 2007) Timing Diagrams Revised Fig 10.13 Chip/Sector Erase Command Sequence to include tAVHW parameter Revision A3 (June 14, 2007) AC Characteristics Revised tBACC @ 108 MHz to 7.0 ns instead of 7.6 ns Revision A4 (December 13, 2007) Global Removed 108 MHz speed offering and corresponding details such as OPN, Valid combination, Product Selector Guide and specifications Revision A5 (February 13, 2008) Capacitance Added Section 10.4 for product capacitance Revision A6 (March 19, 2008) AC Characteristics Revised Figure 10.9 to correct the starting edge of tAAVDS Revision A7 (September 22, 2009) Performance Characteristics Revised Typical Program & Erase Times values Revision A8 (September 8, 2011) Input/Output Descriptions Updated table: NC, DNU, RFU descriptions Special Handling Instructions for FBGA Package Updated figure 64-Ball Fine-Pitch Grid Array, S29NS512P: Revised ball labels to be consistent with Input/Output descriptions Document Number: 002-01103 Rev. *A Page 89 of 91 S29NS512P S29NS256P, S29NS128P Document History Page Document Title: S29NS512P, S29NS256P, S29NS128P 512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V MirrorBit Flash Memory Document Number: 002-01103 Rev. ECN No. Orig. of Change Submission Date Description of Change **  WIOB 06/29/2006 to 09/08/2011 Spansion revision A: Initial release Spansion revision A1: The tAVDS specification is changed from 4 ns to 5 ns The wait state for 83 MHz is changed to 8 ICC3(Max) is changed to 70 µA and ICC6(Max) is changed to 40 µA VIL (Min) is changed to -0.2 V tOE (Max) in both Asynchronous & Synchronous modes is changed to 9 ns across all frequencies tCEZ (Max) is changed to 10 ns across all frequencies tOEZ (Max) in both Asynchronous & Synchronous modes is changed to 10 ns across all frequencies tACH(Min) is changed to 6 ns (66 MHz) and 5 ns (83 MHz and 108 MHz) tRDY(Max) is changed to 10 ns tRACC(Max) is changed to 7.6 ns for 108 MHz tOEH(Min) in Asynchronous mode is changed to 10 ns for 108 MHz Erase and Programing Performance table is updated tCE in Asynchronous mode is changed to 83ns Spansion revision A2: Revised Fig 10.13 Chip/Sector Erase Command Sequence to include tAVHW parameter Spansion revision A3: Revised tBACC @ 108 MHz to 7.0 ns instead of 7.6 ns Spansion revision A4: Removed 108 MHz speed offering and corresponding details such as OPN, Valid combination, Product Selector Guide and specifications Spansion revision A5: Added Section 10.4 for product capacitance Spansion revision A6: Revised Figure 10.9 to correct the starting edge of tAAVDS Spansion revison A7: Revised Typical Program & Erase Times values Spansion revision A8: Updated table: NC, DNU, RFU descriptions Updated figure 64-Ball Fine-Pitch Grid Array, S29NS512P: Revised ball labels to be consistent with Input/Output descriptions *A 4959017 WIOB 10/13/2015 Updated to Cypress template. Document Number: 002-01103 Rev. *A Page 90 of 91 S29NS512P S29NS256P, S29NS128P Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. 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