S29PL127J70BAW020

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com S29PL-J 128-/64-/32-Mbit (8/4/2M × 16-Bit), 3 V, Flash with Enhanced VersatileIO™ S29PL-J, 128-/64-/32-Mbit (8/4/2M × 16-Bit), 3 V, Flash with Enhanced VersatileIO™ Distinctive Characteristics Architectural Advantages Performance Characteristics ■ 128-/64-/32-Mbit Page Mode devices ❐ Page size of 8 words: Fast page read access from random locations within the page ■ Single power supply operation ❐ Full Voltage range: 2.7 to 3.6 V read, erase, and program operations for battery-powered applications ■ Simultaneous Read/Write Operation ❐ Data can be continuously read from one bank while executing erase/program functions in another bank ❐ Zero latency switching from write to read operations ■ ■ ■ FlexBank Architecture (PL127J/PL064J/PL032J) ❐ 4 separate banks, with up to two simultaneous operations per device ❐ Bank A: PL127J -16 Mbit (4 Kw  8 and 32 Kw  31) PL064J - 8 Mbit (4 Kw  8 and 32 Kw  15) PL032J - 4 Mbit (4 Kw  8 and 32 Kw  7) ❐ Bank B: PL127J - 48 Mbit (32 Kw  96) PL064J - 24 Mbit (32 Kw  48) PL032J - 12 Mbit (32 Kw  24) ❐ Bank C: PL127J - 48 Mbit (32 Kw  96) PL064J - 24 Mbit (32 Kw  48) PL032J - 12 Mbit (32 Kw  24) ❐ Bank D: PL127J -16 Mbit (4 Kw  8 and 32 Kw  31) PL064J - 8 Mbit (4 Kw  8 and 32 Kw  15) PL032J - 4 Mbit (4 Kw  8 and 32 Kw  7) Enhanced VersatileI/O (VIO) Control ❐ Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin ❐ VIO options at 1.8 V and 3 V I/O for PL127J devices ❐ 3V VIO for PL064J and PL032J devices Secured Silicon Sector region ❐ Up to 128 words accessible through a command sequence ❐ Up to 64 factory-locked words ❐ Up to 64 customer-lockable words ■ Both top and bottom boot blocks in one device ■ Manufactured on 110-nm process technology ■ Data Retention: 20 years typical ■ Cycling Endurance: 1 million cycles per sector typical Cypress Semiconductor Corporation Document Number: 002-00615 Rev. *F • ■ High Performance ❐ Page access times as fast as 20 ns ❐ Random access times as fast as 55 ns ■ Power consumption (typical values at 10 MHz) ❐ 45 mA active read current ❐ 17 mA program/erase current ❐ 0.2 A typical standby mode current Software Features ■ Software command-set compatible with JEDEC 42.4 standard – Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL families and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families ■ CFI (Common Flash Interface) compliant ❐ Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Erase Suspend / Erase Resume ❐ Suspends an erase operation to allow read or program operations in other sectors of same bank ■ Program Suspend / Program Resume ❐ Suspends a program operation to allow read operation from sectors other than the one being programmed ■ Unlock Bypass Program command ■ Reduces overall programming time when issuing multiple program command sequences Hardware Features ■ Ready/Busy# pin (RY/BY#) ❐ Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) ❐ Hardware method to reset the device to reading array data ■ WP#/ ACC (Write Protect/Acceleration) input ❐ At VIL, hardware level protection for the first and last two 4K word sectors. ❐ At VIH, allows removal of sector protection ❐ At VHH, provides accelerated programming in a factory setting ■ Persistent Sector Protection ❐ A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ❐ Sectors can be locked and unlocked in-system at VCC level 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 20, 2019 S29PL-J ■ Password Sector Protection ❐ A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password Document Number: 002-00615 Rev. *F ■ Package Options ❐ 11  8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080) 8.15  6.15 mm, 48-ball Fine pitch BGA (PL064J/PL032J) (VBK048) ❐ 20  14 mm, 56-pin TSOP (PL127J) (TS056) Page 2 of 80 S29PL-J Contents 1. General Description..................................................... 4 2. Simultaneous Read/Write Operation with Zero Latency ........................................................ 4 Page Mode Features ..................................................... 5 Standard Flash Memory Features ................................. 5 2.1 2.2 3. 3.1 3.2 Ordering Information ................................................... 6 Valid Combinations - Standard ...................................... 7 Valid Combinations - Automotive Grade / AEC-Q100.................................................................... 8 4. Product Selector Guide ............................................... 9 5. Block Diagram.............................................................. 9 6. Simultaneous Read/Write Block Diagram ............... 10 7. 7.1 7.2 7.3 7.4 7.5 7.6 Connection Diagrams................................................ Special Package Handling Instructions........................ 80-Ball Fine-Pitch BGA—PL127J ................................ 64-Ball Fine-Pitch BGA—PL127J ................................ 48-Ball Fine-Pitch BGA, PL064J and PL032J .............. 56-Pin TSOP 20 x 14 mm ............................................ 56-Ball Fine-Pitch Ball Grid Array, PL064J and PL032J..................................................... 11 11 11 12 13 14 15 8. Pin Description........................................................... 16 9. Logic Symbol ............................................................. 17 10. 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Device Bus Operations.............................................. Requirements for Reading Array Data......................... Simultaneous Read/Write Operation ........................... Writing Commands/Command Sequences.................. Standby Mode.............................................................. Automatic Sleep Mode................................................. RESET#: Hardware Reset Pin..................................... Output Disable Mode ................................................... Autoselect Mode .......................................................... Selecting a Sector Protection Mode............................. 18 18 19 19 20 20 20 20 27 29 11. 11.1 11.2 11.3 11.4 Sector Protection ....................................................... Persistent Sector Protection ........................................ Password Sector Protection......................................... WP# Hardware Protection ........................................... Selecting a Sector Protection Mode............................. 31 31 31 31 31 12. 12.1 12.2 12.3 12.4 Persistent Sector Protection..................................... Persistent Protection Bit (PPB) .................................... Persistent Protection Bit Lock (PPB Lock)................... Dynamic Protection Bit (DYB)...................................... Persistent Sector Protection Mode Locking Bit............ 32 32 32 32 33 13. 13.1 13.2 13.3 13.4 Password Protection Mode....................................... Password and Password Mode Locking Bit................. 64-bit Password ........................................................... Write Protect (WP#) ..................................................... High Voltage Sector Protection.................................... 34 34 34 35 35 Document Number: 002-00615 Rev. *F 13.5 Temporary Sector Unprotect......................................... 37 13.6 Secured Silicon Sector Flash Memory Region ............. 37 13.7 Hardware Data Protection............................................. 39 14. Common Flash Memory Interface (CFI) .................... 40 15. 15.1 15.2 15.3 15.4 Command Definitions................................................. 43 Reading Array Data ...................................................... 43 Reset Command ........................................................... 43 Autoselect Command Sequence .................................. 43 Enter/Exit Secured Silicon Sector Command Sequence .................................................... 44 15.5 Word Program Command Sequence............................ 44 15.6 Chip Erase Command Sequence ................................. 46 15.7 Sector Erase Command Sequence .............................. 46 15.8 Erase Suspend/Erase Resume Commands ................. 47 15.9 Program Suspend/Program Resume Commands ........ 48 15.10Command Definitions Tables ....................................... 49 16. 16.1 16.2 16.3 16.4 16.5 16.6 16.7 Write Operation Status ............................................... 52 DQ7: Data# Polling ....................................................... 52 RY/BY#: Ready/Busy#.................................................. 53 DQ6: Toggle Bit I .......................................................... 53 DQ2: Toggle Bit II ......................................................... 55 Reading Toggle Bits DQ6/DQ2..................................... 55 DQ5: Exceeded Timing Limits ...................................... 55 DQ3: Sector Erase Timer.............................................. 56 17. Absolute Maximum Ratings....................................... 57 18. Operating Ranges ....................................................... 58 19. DC Characteristics...................................................... 59 20. 20.1 20.2 20.3 20.4 20.5 20.6 AC Characteristics...................................................... 60 Test Conditions ............................................................. 60 Switching Waveforms ................................................... 61 Read Operations........................................................... 61 Reset ............................................................................ 63 Erase/Program Operations ........................................... 64 Timing Diagrams........................................................... 65 21. Protect/Unprotect........................................................ 68 21.1 Controlled Erase Operations......................................... 69 22. Pin Capacitance .......................................................... 72 22.1 BGA Pin Capacitance ................................................... 72 22.2 TSOP Pin Capacitance ................................................. 72 23. Physical Dimensions .................................................. 73 22. Document History Page ............................................. 78 Sales, Solutions, and Legal Information ...........................80 Worldwide Sales and Design Support ............................80 Products .........................................................................80 PSoC® Solutions ...........................................................80 Cypress Developer Community ......................................80 Technical Support ..........................................................80 Page 3 of 80 S29PL-J 1. General Description The PL127J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 V-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are offered in the following packages: ■ 11 mm  8 mm, 80-ball Fine-pitch BGA standalone (PL127J) ■ 8 mm  11.6 mm, 64-ball Fine-pitch BGA multi-chip compatible (PL127J) ■ 8.15 mm  6.15 mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J) ■ 7 mm  9 mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and PL032J) ■ 20 mm  14 mm, 56-pin TSOP (PL127J) The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. 2. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as shown in Table 1. Table 1. Bank Organization Bank PL127J Sectors PL064J Sectors PL032J Sectors A 16 Mbit (4 Kw  8 and 32 Kw  31) 8 Mbit (4 Kw  8 and 32 Kw  15) 4 Mbit (4 Kw  8 and 32 Kw  7) B 48 Mbit (32 Kw  96) 24 Mbit (32 Kw  48) 12 Mbit (32 Kw  24) C 48 Mbit (32 Kw  96) 24 Mbit (32 Kw  48) 12 Mbit (32 Kw  24) D 16 Mbit (4 Kw x 8 and 32 Kw  31) 8 Mbit (4 Kw  8 and 32 Kw  15) 4 Mbit (4 Kw  8 and 32 Kw  7) Document Number: 002-00615 Rev. *F Page 4 of 80 S29PL-J 2.1 Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. 2.2 Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The Program Suspend/Program Resume feature enables the user to hold the program operation to read data from any sector that is not selected for programming. If a read is needed from the Secured Silicon Sector area, Persistent Protection area, Dynamic Protection area, or the CFI area, after a program suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Document Number: 002-00615 Rev. *F Page 5 of 80 S29PL-J 3. Ordering Information The order number (Valid Combination) is formed by a valid combinations of the following: S29PL-J XX XX X XX X Packing Type: X = 0 or 1 or 2 or 3 0 = Tray 1 = Tube 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel Model Number (Additional Ordering Options): XX = 04 or 05 or 06 or 07 or 08 or 09 or 10 04 = 3.0V VIO, 80-ball 11 x 8 mm FBGA (VBG080) 05 = 1.8V VIO, 80-ball 11 x 8 mm FBGA (VBG080) 06 = 3.0V VIO, 64-ball 8 x 11.6 mm FBGA (VBH064) 07 = 3.0V VIO, 48-ball 8 x 6 mm FBGA (VBK048) 08 = 3.0V VIO, 56-pin 20 x 14 mm TSOP (TS056) 09 = 1.8V VIO, 56-pin 20 x 14 mm TSOP (TS056) 10 = 3.0V VIO, 56-ball 7 x 9 mm FBGA (VBU056) Temperature Range: X = W or I W = Wireless (–25°C to +85°C) I = Industrial (–40°C to +85°C) A = Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C) Package Type: XX = BF or TF BF = Fine-Pitch Grid Array (FBGA) Lead (Pb)-free TF = Thin Small Outline Package (TSOP) Standard Pinout Lead (Pb)-free Clock Speed: XX = 55 or 60 or 65 or 70 or 80 55 = 55 ns (Contact factory for availability) 60 = 60 ns 65 = 65 ns 70 = 70 ns 80 = 80 ns Device Number/Description 128 Mbit (8M x 16-Bit), 64 Megabit (4M x 16-Bit), 32 Megabit (2M x 16-Bit) CMOS Flash Memory, Simultaneous-Read/Write, Page-Mode Flash Memory, 3.0 V-only Read, Program, and Erase Document Number: 002-00615 Rev. *F Page 6 of 80 S29PL-J 3.1 Valid Combinations - Standard Valid Combinations list configurations planned to be supported in volume for this device. Contact your local sales office to confirm availability of specific valid combinations. Table 2. Standard 128 Mb Products Based on 110 nm Floating Gate Technology Device Number/ Description Speed (ns) Package Type Temperature Range Additional Ordering Options S29PL127J 60, 65, 70 BF, TF W, I 04, 06, 08 S29PL127J 80 BF W, I 05 S29PL127J 80 TF W, I 09 Table 3. Standard 64 Mb Products Based on 110 nm Floating Gate Technology Device Number /Description Speed (ns) Package Type S29PL064J 55, 60, 70 BF Temperature Range Additional Ordering Options W, I 07, 10 Table 4. Standard 32 Mb Products Based on 110 nm Floating Gate Technology Device Number /Description Speed (ns) Package Type S29PL032J 55, 60, 70 BF Temperature Range Additional Ordering Options W, I 07, 10 Table 5. Standard Valid Combinations for BGA Packages[1] Order Number Speed (ns) PL127J,PL064J, PL032J 55, 60, 65, 70 PL127J 80 VIO Range [2] 2.7–3.6 1.65–1.95 Notes 1. BGA package marking omits leading S29 and packing type designator from ordering part number. 2. 55 ns speed only supported for PL032J and PL127J. Table 6. Standard Valid Combinations for TSOP Packages[3] Order Number Speed (ns) VIO Range S29PL127J 60, 70 2.7–3.6 Note 3. TSOP package markings omit packing type designator from ordering part number. Document Number: 002-00615 Rev. *F Page 7 of 80 S29PL-J 3.2 Valid Combinations - Automotive Grade / AEC-Q100 The table below lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table will be updated as new combinations are released. Contact your local sales representative to confirm availability of specific combinations and to check on newly released combinations. Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products. Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/TS-16949 requirements. AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949 compliance. Table 7. Automotive 128 Mb Products Based on 110 nm Floating Gate Technology Device Number/ Description Speed (ns) Package Type Temperature Range Additional Ordering Options S29PL127J 60, 65, 70 BF, TF A 04, 06, 08 S29PL127J 80 BF A 05 S29PL127J 80 TF A 09 Table 8. Automotive 64 Mb Products Based on 110 nm Floating Gate Technology Device Number /Description Speed (ns) Package Type S29PL064J 55, 60, 70 BF Temperature Range Additional Ordering Options A 07, 10 Table 9. Automotive 32 Mb Products Based on 110 nm Floating Gate Technology Device Number /Description Speed (ns) Package Type S29PL032J 55, 60, 70 BF Temperature Range Additional Ordering Options A 07, 10 Table 10. Automotive Valid Combinations for BGA Packages[4] Order Number Speed (ns) PL127J,PL064J, PL032J 55, 60, 65, 70 PL127J 80 VIO Range [5] 2.7–3.6 1.65–1.95 Notes 4. BGA package marking omits leading S29 and packing type designator from ordering part number. 5. 55 ns speed only supported for PL032J and PL127J. Table 11. Automotive Valid Combinations for TSOP Packages[6] Order Number Speed (ns) VIO Range S29PL127J 60, 70 2.7–3.6 Note 6. TSOP package markings omit packing type designator from ordering part number. Document Number: 002-00615 Rev. *F Page 8 of 80 S29PL-J 4. Product Selector Guide Part Number  S29PL032J/S29PL064J/S29PL0127J VCC,VIO = 2.7 V – 3.6 V VCC = 2.7 V – 3.6 V, VIO = 1.65 V – 1.95 V (PL127J) Speed Option Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) 55[7] 60 65 — 70 — — — 80 — 55[7] 60 65 80 70 20[7] 25 30 30 Note 7. 55 ns speed bin only supported for PL032J and PL064J. 5. Block Diagram DQ15–DQ0 RY/BY# VCC VSS Sector Switches VIO RESET# Input/Output Buffers Erase Voltage Generator WE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# Amax–A3 Timer Y-Decoder Address Latch VCC Detector X-Decoder Data Latch Y-Gating Cell Matrix A2–A0 Notes 8. RY/BY# is an open drain output. 9. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J). Document Number: 002-00615 Rev. *F Page 9 of 80 S29PL-J 6. Simultaneous Read/Write Block Diagram VCC VSS OE# Mux Bank A Bank B X-Decoder Amax–A0 Status DQ15–DQ0 Control Mux DQ15–DQ0 CE# WP#/ACC STATE CONTROL & COMMAND REGISTER X-Decoder A22–A0 DQ0–DQ15 Bank C Address Bank C X-Decoder Amax–A0 Bank D Address Y-gate RESET# WE# DQ15–DQ0 Bank B Address DQ15–DQ0 RY/BY# DQ15–DQ0 A22–A0 X-Decoder Y-gate Bank A Address Amax–A0 Bank D Mux Note 10. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J). Document Number: 002-00615 Rev. *F Page 10 of 80 S29PL-J 7. Connection Diagrams 7.1 Special Package Handling Instructions 7.1.1 TSOP, BGA, PDIP, SSOP, and PLCC Packages Special handling is required for Flash Memory products in molded packages. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 7.1.2 FBGA Packages Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 7.2 80-Ball Fine-Pitch BGA—PL127J Figure 1. 80-Ball Fine-Pitch BGA, Top View, Balls Facing Down—PL127J A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 L8 M8 NC NC NC A22 NC VIO VSS NC NC NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 NC NC A13 A12 A14 A15 A16 NC DQ15 VSS NC NC C6 D6 E6 F6 G6 H6 J6 K6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 C5 D5 E5 F5 G5 H5 J5 K5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 C4 D4 E4 F4 G4 H4 J4 K4 A18 A20 DQ2 DQ10 DQ11 DQ3 RY/BY# WP#/ACC C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 NC NC A3 A4 A2 A1 A0 CE# OE# VSS NC NC A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 NC NC NC NC NC NC NC VIO NC NC NC NC Document Number: 002-00615 Rev. *F Page 11 of 80 S29PL-J 7.3 64-Ball Fine-Pitch BGA—PL127J Figure 2. 64-Ball Fine-Pitch BGA, Top View, Balls Facing Down—PL127J A1 A10 NC NC D2 A3 C3 C4 A7 RFU D3 D4 A6 RFU E4 E2 E3 A2 A5 A18 F2 F3 F4 A1 A4 A17 B5 B6 RFU RFU C5 C6 WP#/ACC WE# D5 D6 RESET# RFU E5 E6 RY/BY # A20 C7 C8 A8 A11 D7 D8 D9 A19 A12 A15 E7 E8 E9 A13 A21 F7 F8 F9 A10 A14 A22 A9 G2 G3 G4 G7 G8 A0 VSS DQ1 DQ6 RFU G9 H2 H3 H4 H5 H6 H7 H8 H9 CE# OE# DQ9 DQ3 DQ4 DQ13 DQ15 VCC A16 J2 J3 J4 J5 J6 J7 J8 J9 RFU DQ0 DQ10 VCC RFU DQ12 DQ7 VSS K3 K4 K5 K6 K7 K8 DQ8 DQ2 DQ11 RFU DQ5 DQ14 L5 L6 RFU RFU M1 M10 NC NC Document Number: 002-00615 Rev. *F Page 12 of 80 S29PL-J 7.4 48-Ball Fine-Pitch BGA, PL064J and PL032J Figure 3. 48-Ball Fine-Pitch BGA, Top View, Balls Facing Down—PL064J—PL032J: C4(A21)=NC A6 B6 C6 D6 E6 F6 G6 H6 A13 A12 A14 A15 A16 NC DQ15 VSS A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 A3 B3 C3 D3 E3 F3 G3 H3 A18 A20 DQ2 DQ10 DQ11 DQ3 RY/BY# WP#/ACC A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE# OE# VSS Document Number: 002-00615 Rev. *F Page 13 of 80 S29PL-J 7.5 56-Pin TSOP 20 x 14 mm Figure 4. 56-Pin TSOP 20 x 14 mm Configuration—PL127J RESET# RY/BY# A0 A1 A2 A3 A4 A5 VCC DQ0 DQ1 DQ2 DQ3 VSS VCC DQ4 DQ5 DQ6 DQ7 VSS NC A6 A7 A8 A9 A10 A11 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP#/ACC WE# NC A22 A21 A20 OE# NC CE# VSS DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCC A19 A18 A17 A16 A15 A14 A13 For this family of products, a single multi-chip compatible package (TSOP) is offered for each density to allow both standalone and multi-chip qualification using a single, adaptable package. This new methodology allows package standardization resulting in faster development. The multi-chip compatible package includes all the pins required for standalone device operation and verification. In addition, extra pins are included for insertion of common data storage or logic devices to be used for multi-chip products. If a standalone device is required, the extra multi-chip specific pins are not connected and the standalone device operates normally. The multi-chip compatible package sizes were chosen to serve the largest number of combinations possible. There are only a few cases where a larger package size would be required to accommodate the multi-chip combination. This multi-chip compatible package set does not allow for direct package migration from the Am29BDS128H, Am29BDS128G, Am29BDS640G products, which use legacy standalone packages. Document Number: 002-00615 Rev. *F Page 14 of 80 S29PL-J 7.6 56-Ball Fine-Pitch Ball Grid Array, PL064J and PL032J Figure 5. 56-ball Fine-Pitch BGA, Top View, Balls Facing Down—PL064J and PL032J A2 A3 A4 A5 A6 A7 A7 RFU WP/ACC WE# A8 A11 B1 B2 B3 B4 B5 B6 B7 B8 A3 A6 RFU RST# RFU A19 A12 A15 C1 C2 C3 C4 C5 C6 C7 C8 A2 A5 A18 RY/BY# A20 A9 A13 A21 D1 D2 D3 D6 D7 D8 A1 A4 A17 A10 A14 RFU E1 E2 E3 E6 E7 E8 A0 VSS DQ1 DQ6 RFU A16 F1 F2 F3 F4 F5 F6 F7 F8 CE1#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU G1 G2 G3 G4 G5 G6 G7 G8 RFU DQ0 DQ10 VCCf RFU DQ12 DQ7 VSS H2 H3 H4 H5 H6 H7 DQ8 DQ2 DQ11 RFU DQ5 DQ14 Document Number: 002-00615 Rev. *F Page 15 of 80 S29PL-J 8. Pin Description Table 12. Pin Description Pin Name Amax–A0 DQ15–DQ0 CE# Description Address bus 16-bit data inputs/outputs/float Chip Enable Inputs OE# Output Enable Input WE# Write Enable VSS Device Ground NC Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). RFU Reserved for Future Use. Not currently connected internally but the pin/ball location should be left unconnected and unused by PCB routing channel for future compatibility. The pin/ball may be used by a signal in the future. RY/BY# Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. WP#/ACC Write Protect/Acceleration Input. When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP#/ACC= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP#/ACC= VHH, program and erase operations are accelerated. VIO VCC RESET# Input/Output Buffer Power Supply (1.65 V to 1.95 V (for PL127J) or 2.7 V to 3.6 V (for all PLxxxJ devices)) Chip Power Supply (2.7 V to 3.6 V or 2.7 to 3.3 V) Hardware Reset Pin Note 11. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J). Document Number: 002-00615 Rev. *F Page 16 of 80 S29PL-J 9. Logic Symbol max+1 Amax–A0 16 DQ15–DQ0 CE# OE# WE# WP#/ACC RESET# RY/BY# VIO (VCCQ) Document Number: 002-00615 Rev. *F Page 17 of 80 S29PL-J 10. Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 13 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 13. PL127J Device Bus Operations Operation CE# OE# WE# RESET# WP#/ACC Addresses (Amax–A0) DQ15–DQ0 Read L L H H X AIN DOUT Write L H L H X[13] AIN DIN X High-Z VIO0.3 V X X VIO 0.3 V X[13] Output Disable L H H H X X High-Z Reset X X X L X X High-Z Temporary Sector Unprotect (High Voltage) X X X VID X AIN DIN Standby Legend L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out 10.1 Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appropriate CE# pins to VIL. CE# is the power control. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to Table 34 on page 61 for timing specifications and to Figure 16 on page 62 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. 10.1.1 Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE time). 10.1.2 Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted (=VIH), the reassertion of CE# for subsequent access has access time of tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping Amax–A3 constant and changing A2–A0 to select the specific word within that page. Notes 12. The sector protect and sector unprotect functions may also be implemented via programming equipment. See High Voltage Sector Protection on page 35. 13. WP#/ACC must be high when writing to upper two and lower two sectors. Document Number: 002-00615 Rev. *F Page 18 of 80 S29PL-J Table 14. Page Select 10.2 Word A2 A1 A0 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 Simultaneous Read/Write Operation In addition to the conventional features (read, program, erase-suspend read, erase-suspend program, and program-suspend read), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (PL127J: A22–A20, PL064J: A21–A19, PL032J: A20–A18) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 15. Bank Select Bank 10.3 PL127J: A22–A20, PL064J: A21–A19, PL032J: A20–A18 Bank A 000 Bank B 001, 010, 011 Bank C 100, 101, 110 Bank D 111 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. Section 15.5 Word Program Command Sequence on page 44 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 15 indicates the set of address space that each sector occupies. A “bank address” is the set of address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. Section 15. Command Definitions on page 43 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the Section 19. DC Characteristics on page 59 represents the active current specification for the write mode. See the timing specification tables and timing diagrams in section Section 20.4 Reset on page 63 for write operations. 10.3.1 Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result. Document Number: 002-00615 Rev. *F Page 19 of 80 S29PL-J 10.3.2 Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Table 19 on page 27 and Section 15.3 Autoselect Command Sequence on page 43 for more information. 10.4 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in Section 19. DC Characteristics on page 59 represents the CMOS standby current specification. 10.5 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in Section 19. DC Characteristics on page 59 represents the automatic sleep mode current specification. 10.6 RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the tables in Section 20. AC Characteristics on page 60 for RESET# parameters and to Figure 18 on page 63 for the timing diagram. 10.7 Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state. Document Number: 002-00615 Rev. *F Page 20 of 80 S29PL-J Table 16. PL127J Sector Architecture (Continued) Table 16. PL127J Sector Architecture Bank B Sector Sector Address Sector Size (A22-A12) (Kwords) Bank SA45 SA0 00000000000 4 000000h–000FFFh SA1 00000000001 4 001000h–001FFFh SA2 00000000010 4 002000h–002FFFh SA3 00000000011 4 003000h–003FFFh SA4 00000000100 4 004000h–004FFFh SA5 00000000101 4 005000h–005FFFh SA6 00000000110 4 006000h–006FFFh SA7 00000000111 4 007000h–007FFFh SA8 00000001XXX 32 008000h–00FFFFh SA9 00000010XXX 32 010000h–017FFFh SA10 00000011XXX 32 018000h–01FFFFh SA11 00000100XXX 32 020000h–027FFFh SA12 00000101XXX 32 028000h–02FFFFh SA13 00000110XXX 32 030000h–037FFFh SA14 00000111XXX 32 038000h–03FFFFh SA15 00001000XXX 32 040000h–047FFFh SA16 00001001XXX 32 048000h–04FFFFh SA17 00001010XXX 32 050000h–057FFFh SA18 00001011XXX 32 058000h–05FFFFh SA19 00001100XXX 32 060000h–067FFFh SA20 00001101XXX 32 068000h–06FFFFh SA21 00001110XXX 32 070000h–077FFFh SA22 00001111XXX 32 078000h–07FFFFh SA23 00010000XXX 32 080000h–087FFFh SA24 00010001XXX 32 088000h–08FFFFh SA25 00010010XXX 32 090000h–097FFFh SA26 00010011XXX 32 098000h–09FFFFh SA27 00010100XXX 32 0A0000h–0A7FFFh SA28 00010101XXX 32 0A8000h–0AFFFFh SA29 00010110XXX 32 0B0000h–0B7FFFh SA30 00010111XXX 32 0B8000h–0BFFFFh SA31 00011000XXX 32 0C0000h–0C7FFFh SA32 00011001XXX 32 0C8000h–0CFFFFh SA33 00011010XXX 32 0D0000h–0D7FFFh SA34 00011011XXX 32 0D8000h–0DFFFFh SA35 00011100XXX 32 0E0000h–0E7FFFh SA36 00011101XXX 32 0E8000h–0EFFFFh SA37 00011110XXX 32 0F0000h–0F7FFFh SA38 00011111XXX 32 0F8000h–0FFFFFh SA39 00100000XXX 32 100000h–107FFFh SA40 00100001XXX 32 108000h–10FFFFh SA41 00100010XXX 32 110000h–117FFFh SA42 00100011XXX 32 118000h–11FFFFh SA43 00100100XXX 32 120000h–127FFFh SA44 00100101XXX 32 128000h–12FFFFh Document Number: 002-00615 Rev. *F Sector Address Range (x16) Bank B Bank A Bank Sector Address Sector Size (A22-A12) (Kwords) Address Range (x16) 00100110XXX 32 130000h–137FFFh SA46 00100111XXX 32 138000h–13FFFFh SA47 00101000XXX 32 140000h–147FFFh SA48 00101001XXX 32 148000h–14FFFFh SA49 00101010XXX 32 150000h–157FFFh SA50 00101011XXX 32 158000h–15FFFFh SA51 00101100XXX 32 160000h–167FFFh SA52 00101101XXX 32 168000h–16FFFFh SA53 00101110XXX 32 170000h–177FFFh 178000h–17FFFFh SA54 00101111XXX 32 SA55 00110000XXX 32 180000h–187FFFh SA56 00110001XXX 32 188000h–18FFFFh SA57 00110010XXX 32 190000h–197FFFh SA58 00110011XXX 32 198000h–19FFFFh SA59 00110100XXX 32 1A0000h–1A7FFFh SA60 00110101XXX 32 1A8000h–1AFFFFh SA61 00110110XXX 32 1B0000h–1B7FFFh SA62 00110111XXX 32 1B8000h–1BFFFFh SA63 00111000XXX 32 1C0000h–1C7FFFh SA64 00111001XXX 32 1C8000h–1CFFFFh SA65 00111010XXX 32 1D0000h–1D7FFFh SA66 00111011XXX 32 1D8000h–1DFFFFh SA67 00111100XXX 32 1E0000h–1E7FFFh SA68 00111101XXX 32 1E8000h–1EFFFFh SA69 00111110XXX 32 1F0000h–1F7FFFh 1F8000h–1FFFFFh SA70 00111111XXX 32 SA71 01000000XXX 32 200000h–207FFFh SA72 01000001XXX 32 208000h–20FFFFh SA73 01000010XXX 32 210000h–217FFFh 218000h–21FFFFh SA74 01000011XXX 32 SA75 01000100XXX 32 220000h–227FFFh SA76 01000101XXX 32 228000h–22FFFFh SA77 01000110XXX 32 230000h–237FFFh SA78 01000111XXX 32 238000h–23FFFFh SA79 01001000XXX 32 240000h–247FFFh SA80 01001001XXX 32 248000h–24FFFFh SA81 01001010XXX 32 250000h–257FFFh SA82 01001011XXX 32 258000h–25FFFFh SA83 01001100XXX 32 260000h–267FFFh SA84 01001101XXX 32 268000h–26FFFFh SA85 01001110XXX 32 270000h–277FFFh 278000h–27FFFFh SA86 01001111XXX 32 SA87 01010000XXX 32 280000h–287FFFh SA88 01010001XXX 32 288000h–28FFFFh SA89 01010010XXX 32 290000h–297FFFh Page 21 of 80 S29PL-J Table 16. PL127J Sector Architecture (Continued) Sector Bank B SA90 Sector Address Sector Size (A22-A12) (Kwords) 01010011XXX 32 Address Range (x16) Bank Sector Sector Address Sector Size (A22-A12) (Kwords) Address Range (x16) 298000h–29FFFFh SA135 10000000XXX 32 400000h–407FFFh 408000h–40FFFFh SA91 01010100XXX 32 2A0000h–2A7FFFh SA136 10000001XXX 32 SA92 01010101XXX 32 2A8000h–2AFFFFh SA137 10000010XXX 32 410000h–417FFFh SA93 01010110XXX 32 2B0000h–2B7FFFh SA138 10000011XXX 32 418000h–41FFFFh SA94 01010111XXX 32 2B8000h–2BFFFFh SA139 10000100XXX 32 420000h–427FFFh SA95 01011000XXX 32 2C0000h–2C7FFFh SA140 10000101XXX 32 428000h–42FFFFh SA96 01011001XXX 32 2C8000h–2CFFFFh SA141 10000110XXX 32 430000h–437FFFh SA97 01011010XXX 32 2D0000h–2D7FFFh SA142 10000111XXX 32 438000h–43FFFFh SA98 01011011XXX 32 2D8000h–2DFFFFh SA143 10001000XXX 32 440000h–447FFFh 448000h–44FFFFh SA99 01011100XXX 32 2E0000h–2E7FFFh SA144 10001001XXX 32 SA100 01011101XXX 32 2E8000h–2EFFFFh SA145 10001010XXX 32 450000h–457FFFh SA101 01011110XXX 32 2F0000h–2F7FFFh SA146 10001011XXX 32 458000h–45FFFFh SA102 01011111XXX 32 2F8000h–2FFFFFh SA147 10001100XXX 32 460000h–467FFFh SA103 01100000XXX 32 300000h–307FFFh SA148 10001101XXX 32 468000h–46FFFFh SA104 01100001XXX 32 308000h–30FFFFh SA149 10001110XXX 32 470000h–477FFFh SA105 01100010XXX 32 310000h–317FFFh SA150 10001111XXX 32 478000h–47FFFFh SA106 01100011XXX 32 318000h–31FFFFh SA151 10010000XXX 32 480000h–487FFFh SA107 01100100XXX 32 320000h–327FFFh SA152 10010001XXX 32 488000h–48FFFFh SA108 01100101XXX 32 328000h–32FFFFh SA153 10010010XXX 32 490000h–497FFFh SA109 01100110XXX 32 330000h–337FFFh SA154 10010011XXX 32 498000h–49FFFFh SA110 01100111XXX 32 338000h–33FFFFh SA155 10010100XXX 32 4A0000h–4A7FFFh SA156 10010101XXX 32 4A8000h–4AFFFFh SA157 10010110XXX 32 4B0000h–4B7FFFh SA158 10010111XXX 32 4B8000h–4BFFFFh SA111 01101000XXX 32 340000h–347FFFh SA112 01101001XXX 32 348000h–34FFFFh SA113 01101010XXX 32 350000h–357FFFh SA114 01101011XXX 32 358000h–35FFFFh SA159 10011000XXX 32 4C0000h–4C7FFFh SA115 01101100XXX 32 360000h–367FFFh SA160 10011001XXX 32 4C8000h–4CFFFFh SA116 01101101XXX 32 368000h–36FFFFh SA161 10011010XXX 32 4D0000h–4D7FFFh SA117 01101110XXX 32 370000h–377FFFh SA162 10011011XXX 32 4D8000h–4DFFFFh SA118 01101111XXX 32 378000h–37FFFFh SA163 10011100XXX 32 4E0000h–4E7FFFh 4E8000h–4EFFFFh Bank C Bank Table 16. PL127J Sector Architecture (Continued) SA119 01110000XXX 32 380000h–387FFFh SA164 10011101XXX 32 SA120 01110001XXX 32 388000h–38FFFFh SA165 10011110XXX 32 4F0000h–4F7FFFh SA121 01110010XXX 32 390000h–397FFFh SA166 10011111XXX 32 4F8000h–4FFFFFh SA122 01110011XXX 32 398000h–39FFFFh SA167 10100000XXX 32 500000h–507FFFh SA123 01110100XXX 32 3A0000h–3A7FFFh SA168 10100001XXX 32 508000h–50FFFFh SA124 01110101XXX 32 3A8000h–3AFFFFh SA169 10100010XXX 32 510000h–517FFFh SA125 01110110XXX 32 3B0000h–3B7FFFh SA170 10100011XXX 32 518000h–51FFFFh SA126 01110111XXX 32 3B8000h–3BFFFFh SA171 10100100XXX 32 520000h–527FFFh 528000h–52FFFFh SA127 01111000XXX 32 3C0000h–3C7FFFh SA172 10100101XXX 32 SA128 01111001XXX 32 3C8000h–3CFFFFh SA173 10100110XXX 32 530000h–537FFFh SA129 01111010XXX 32 3D0000h–3D7FFFh SA174 10100111XXX 32 538000h–53FFFFh SA130 01111011XXX 32 3D8000h–3DFFFFh SA175 10101000XXX 32 540000h–547FFFh SA131 01111100XXX 32 3E0000h–3E7FFFh SA176 10101001XXX 32 548000h–54FFFFh SA132 01111101XXX 32 3E8000h–3EFFFFh SA177 10101010XXX 32 550000h–557FFFh SA133 01111110XXX 32 3F0000h–3F7FFFh SA178 10101011XXX 32 558000h–15FFFFh SA134 01111111XXX 32 3F8000h–3FFFFFh SA179 10101100XXX 32 560000h–567FFFh Document Number: 002-00615 Rev. *F Page 22 of 80 S29PL-J Table 16. PL127J Sector Architecture (Continued) Sector Sector Address Sector Size (A22-A12) (Kwords) 10101101XXX 32 SA181 10101110XXX SA182 10101111XXX SA183 Bank Sector Sector Address Sector Size (A22-A12) (Kwords) Address Range (x16) 568000h–56FFFFh SA225 11011010XXX 32 6D0000h–6D7FFFh 32 570000h–577FFFh SA226 11011011XXX 32 6D8000h–6DFFFFh 32 578000h–57FFFFh SA227 11011100XXX 32 6E0000h–6E7FFFh 10110000XXX 32 580000h–587FFFh SA228 11011101XXX 32 6E8000h–6EFFFFh SA184 10110001XXX 32 588000h–58FFFFh SA229 11011110XXX 32 6F0000h–6F7FFFh SA185 10110010XXX 32 590000h–597FFFh SA230 11011111XXX 32 6F8000h–6FFFFFh SA186 10110011XXX 32 598000h–59FFFFh SA231 11100000XXX 32 700000h–707FFFh SA187 10110100XXX 32 5A0000h–5A7FFFh SA232 11100001XXX 32 708000h–70FFFFh SA188 10110101XXX 32 5A8000h–5AFFFFh SA233 11100010XXX 32 710000h–717FFFh SA189 10110110XXX 32 5B0000h–5B7FFFh SA234 11100011XXX 32 718000h–71FFFFh SA190 10110111XXX 32 5B8000h–5BFFFFh SA235 11100100XXX 32 720000h–727FFFh SA191 10111000XXX 32 5C0000h–5C7FFFh SA236 11100101XXX 32 728000h–72FFFFh SA192 10111001XXX 32 5C8000h–5CFFFFh SA237 11100110XXX 32 730000h–737FFFh SA193 10111010XXX 32 5D0000h–5D7FFFh SA238 11100111XXX 32 738000h–73FFFFh SA194 10111011XXX 32 5D8000h–5DFFFFh SA239 11101000XXX 32 740000h–747FFFh SA195 10111100XXX 32 5E0000h–5E7FFFh SA240 11101001XXX 32 748000h–74FFFFh SA196 10111101XXX 32 5E8000h–5EFFFFh SA241 11101010XXX 32 750000h–757FFFh SA197 10111110XXX 32 5F0000h–5F7FFFh SA242 11101011XXX 32 758000h–75FFFFh SA198 10111111XXX 32 5F8000h–5FFFFFh SA243 11101100XXX 32 760000h–767FFFh SA199 11000000XXX 32 600000h–607FFFh SA244 11101101XXX 32 768000h–76FFFFh SA200 11000001XXX 32 608000h–60FFFFh SA245 11101110XXX 32 770000h–777FFFh SA201 11000010XXX 32 610000h–617FFFh SA246 11101111XXX 32 778000h–77FFFFh SA202 11000011XXX 32 618000h–61FFFFh SA247 11110000XXX 32 780000h–787FFFh SA203 11000100XXX 32 620000h–627FFFh SA248 11110001XXX 32 788000h–78FFFFh SA204 11000101XXX 32 628000h–62FFFFh SA249 11110010XXX 32 790000h–797FFFh SA205 11000110XXX 32 630000h–637FFFh SA206 11000111XXX 32 638000h–63FFFFh SA207 11001000XXX 32 SA208 11001001XXX 32 SA209 11001010XXX 32 650000h–657FFFh SA210 11001011XXX 32 658000h–65FFFFh Bank C SA180 Address Range (x16) Bank D Bank C Bank Table 16. PL127J Sector Architecture (Continued) SA250 11110011XXX 32 798000h–79FFFFh SA251 11110100XXX 32 7A0000h–7A7FFFh 640000h–647FFFh SA252 11110101XXX 32 7A8000h–7AFFFFh 648000h–64FFFFh SA253 11110110XXX 32 7B0000h–7B7FFFh SA254 11110111XXX 32 7B8000h–7BFFFFh SA255 11111000XXX 32 7C0000h–7C7FFFh SA211 11001100XXX 32 660000h–667FFFh SA256 11111001XXX 32 7C8000h–7CFFFFh SA212 11001101XXX 32 668000h–66FFFFh SA257 11111010XXX 32 7D0000h–7D7FFFh SA213 11001110XXX 32 670000h–677FFFh SA258 11111011XXX 32 7D8000h–7DFFFFh SA214 11001111XXX 32 678000h–67FFFFh SA259 11111100XXX 32 7E0000h–7E7FFFh SA215 11010000XXX 32 680000h–687FFFh SA260 11111101XXX 32 7E8000h–7EFFFFh SA216 11010001XXX 32 688000h–68FFFFh SA261 11111110XXX 32 7F0000h–7F7FFFh SA217 11010010XXX 32 690000h–697FFFh SA262 11111111000 4 7F8000h–7F8FFFh SA218 11010011XXX 32 698000h–69FFFFh SA263 11111111001 4 7F9000h–7F9FFFh SA219 11010100XXX 32 6A0000h–6A7FFFh SA264 11111111010 4 7FA000h–7FAFFFh SA220 11010101XXX 32 6A8000h–6AFFFFh SA265 11111111011 4 7FB000h–7FBFFFh SA221 11010110XXX 32 6B0000h–6B7FFFh SA266 11111111100 4 7FC000h–7FCFFFh SA222 11010111XXX 32 6B8000h–6BFFFFh SA267 11111111101 4 7FD000h–7FDFFFh SA223 11011000XXX 32 6C0000h–6C7FFFh SA268 11111111110 4 7FE000h–7FEFFFh SA224 11011001XXX 32 6C8000h–6CFFFFh SA269 11111111111 4 7FF000h–7FFFFFh Document Number: 002-00615 Rev. *F Page 23 of 80 S29PL-J Table 17. PL064J Sector Architecture (Continued) Table 17. PL064J Sector Architecture Sector Bank Sector Sector Address (A22-A12) Sector Size Address Range (x16) (Kwords) SA43 0100100XXX 32 120000h–127FFFh SA0 0000000000 4 000000h–000FFFh SA44 0100101XXX 32 128000h–12FFFFh SA1 0000000001 4 001000h–001FFFh SA45 0100110XXX 32 130000h–137FFFh SA2 0000000010 4 002000h–002FFFh SA46 0100111XXX 32 138000h–13FFFFh SA3 0000000011 4 003000h–003FFFh SA47 0101000XXX 32 140000h–147FFFh SA4 0000000100 4 004000h–004FFFh SA48 0101001XXX 32 148000h–14FFFFh SA5 0000000101 4 005000h–005FFFh SA49 0101010XXX 32 150000h–157FFFh SA6 0000000110 4 006000h–006FFFh SA50 0101011XXX 32 158000h–15FFFFh SA7 0000000111 4 007000h–007FFFh SA51 0101100XXX 32 160000h–167FFFh SA8 0000001XXX 32 008000h–00FFFFh SA52 0101101XXX 32 168000h–16FFFFh 0000010XXX 32 010000h–017FFFh SA53 0101110XXX 32 170000h–177FFFh 0000011XXX 32 018000h–01FFFFh SA54 0101111XXX 32 178000h–17FFFFh SA11 0000100XXX 32 020000h–027FFFh SA55 0110000XXX 32 180000h–187FFFh SA12 0000101XXX 32 028000h–02FFFFh SA56 0110001XXX 32 188000h–18FFFFh SA13 0000110XXX 32 030000h–037FFFh SA57 0110010XXX 32 190000h–197FFFh SA14 0000111XXX 32 038000h–03FFFFh SA58 0110011XXX 32 198000h–19FFFFh SA15 0001000XXX 32 040000h–047FFFh SA59 0110100XXX 32 1A0000h–1A7FFFh SA16 0001001XXX 32 048000h–04FFFFh SA60 0110101XXX 32 1A8000h–1AFFFFh SA17 0001010XXX 32 050000h–057FFFh SA61 0110110XXX 32 1B0000h–1B7FFFh SA18 0001011XXX 32 058000h–05FFFFh SA62 0110111XXX 32 1B8000h–1BFFFFh SA19 0001100XXX 32 060000h–067FFFh SA63 0111000XXX 32 1C0000h–1C7FFFh SA20 0001101XXX 32 068000h–06FFFFh SA64 0111001XXX 32 1C8000h–1CFFFFh SA21 0001110XXX 32 070000h–077FFFh SA65 0111010XXX 32 1D0000h–1D7FFFh SA22 0001111XXX 32 078000h–07FFFFh SA66 0111011XXX 32 1D8000h–1DFFFFh SA23 0010000XXX 32 080000h–087FFFh SA67 0111100XXX 32 1E0000h–1E7FFFh SA24 0010001XXX 32 088000h–08FFFFh SA68 0111101XXX 32 1E8000h–1EFFFFh SA25 0010010XXX 32 090000h–097FFFh SA69 0111110XXX 32 1F0000h–1F7FFFh SA26 0010011XXX 32 098000h–09FFFFh SA70 0111111XXX 32 1F8000h–1FFFFFh SA27 0010100XXX 32 0A0000h–0A7FFFh SA71 1000000XXX 32 200000h–207FFFh SA28 0010101XXX 32 0A8000h–0AFFFFh SA72 1000001XXX 32 208000h–20FFFFh SA29 0010110XXX 32 0B0000h–0B7FFFh SA73 1000010XXX 32 210000h–217FFFh SA30 0010111XXX 32 0B8000h–0BFFFFh SA74 1000011XXX 32 218000h–21FFFFh SA31 0011000XXX 32 0C0000h–0C7FFFh SA75 1000100XXX 32 220000h–227FFFh SA32 0011001XXX 32 0C8000h–0CFFFFh SA76 1000101XXX 32 228000h–22FFFFh SA33 0011010XXX 32 0D0000h–0D7FFFh SA77 1000110XXX 32 230000h–237FFFh SA34 0011011XXX 32 0D8000h–0DFFFFh SA78 1000111XXX 32 238000h–23FFFFh SA35 0011100XXX 32 0E0000h–0E7FFFh SA79 1001000XXX 32 240000h–247FFFh SA36 0011101XXX 32 0E8000h–0EFFFFh SA80 1001001XXX 32 248000h–24FFFFh SA37 0011110XXX 32 0F0000h–0F7FFFh SA81 1001010XXX 32 250000h–257FFFh SA38 0011111XXX 32 0F8000h–0FFFFFh SA82 1001011XXX 32 258000h–25FFFFh SA39 0100000XXX 32 100000h–107FFFh SA83 1001100XXX 32 260000h–267FFFh SA40 0100001XXX 32 108000h–10FFFFh SA84 1001101XXX 32 268000h–26FFFFh SA41 0100010XXX 32 110000h–117FFFh SA85 1001110XXX 32 270000h–277FFFh SA42 0100011XXX 32 118000h–11FFFFh Document Number: 002-00615 Rev. *F Bank B SA9 SA10 Bank C Bank B Bank A Bank Sector Sector Address Size Address Range (x16) (A22-A12) (Kwords) Page 24 of 80 S29PL-J Table 17. PL064J Sector Architecture (Continued) Bank C Sector Sector Address (A22-A12) Sector Size Address Range (x16) (Kwords) Bank Sector Sector Address (A22-A12) Sector Size Address Range (x16) (Kwords) SA86 1001111XXX 32 278000h–27FFFFh SA119 1110000XXX 32 380000h–387FFFh SA87 1010000XXX 32 280000h–287FFFh SA120 1110001XXX 32 388000h–38FFFFh SA88 1010001XXX 32 288000h–28FFFFh SA121 1110010XXX 32 390000h–397FFFh SA89 1010010XXX 32 290000h–297FFFh SA122 1110011XXX 32 398000h–39FFFFh SA90 1010011XXX 32 298000h–29FFFFh SA123 1110100XXX 32 3A0000h–3A7FFFh SA91 1010100XXX 32 2A0000h–2A7FFFh SA124 1110101XXX 32 3A8000h–3AFFFFh SA92 1010101XXX 32 2A8000h–2AFFFFh SA125 1110110XXX 32 3B0000h–3B7FFFh SA93 1010110XXX 32 2B0000h–2B7FFFh SA126 1110111XXX 32 3B8000h–3BFFFFh SA94 1010111XXX 32 2B8000h–2BFFFFh SA127 1111000XXX 32 3C0000h–3C7FFFh SA95 1011000XXX 32 2C0000h–2C7FFFh SA128 1111001XXX 32 3C8000h–3CFFFFh SA96 1011001XXX 32 2C8000h–2CFFFFh SA129 1111010XXX 32 3D0000h–3D7FFFh SA97 1011010XXX 32 2D0000h–2D7FFFh SA130 1111011XXX 32 3D8000h–3DFFFFh SA98 1011011XXX 32 2D8000h–2DFFFFh SA131 1111100XXX 32 3E0000h–3E7FFFh SA99 1011100XXX 32 2E0000h–2E7FFFh SA132 1111101XXX 32 3E8000h–3EFFFFh SA100 1011101XXX 32 2E8000h–2EFFFFh SA133 1111110XXX 32 3F0000h–3F7FFFh SA101 1011110XXX 32 2F0000h–2F7FFFh SA134 1111111000 4 3F8000h–3F8FFFh Bank D Bank Table 17. PL064J Sector Architecture (Continued) SA102 1011111XXX 32 2F8000h–2FFFFFh SA135 1111111001 4 3F9000h–3F9FFFh SA103 1100000XXX 32 300000h–307FFFh SA136 1111111010 4 3FA000h–3FAFFFh SA104 1100001XXX 32 308000h–30FFFFh SA137 1111111011 4 3FB000h–3FBFFFh SA105 1100010XXX 32 310000h–317FFFh SA138 1111111100 4 3FC000h–3FCFFFh SA106 1100011XXX 32 318000h–31FFFFh SA139 1111111101 4 3FD000h–3FDFFFh SA107 1100100XXX 32 320000h–327FFFh SA140 1111111110 4 3FE000h–3FEFFFh SA108 1100101XXX 32 328000h–32FFFFh SA141 1111111111 4 3FF000h–3FFFFFh SA109 1100110XXX 32 330000h–337FFFh SA110 1100111XXX 32 338000h–33FFFFh SA111 1101000XXX 32 340000h–347FFFh SA112 1101001XXX 32 348000h–34FFFFh SA113 1101010XXX 32 350000h–357FFFh SA114 1101011XXX 32 358000h–35FFFFh SA115 1101100XXX 32 360000h–367FFFh SA116 1101101XXX 32 368000h–36FFFFh SA117 1101110XXX 32 370000h–377FFFh SA118 1101111XXX 32 378000h–37FFFFh Document Number: 002-00615 Rev. *F Page 25 of 80 S29PL-J Table 18. PL032J Sector Architecture (Continued) Table 18. PL032J Sector Architecture Bank C Sector Sector Size (Kwords) Address Range (x16) SA0 000000000 4 000000h–000FFFh SA1 000000001 4 001000h–001FFFh SA2 000000010 4 002000h–002FFFh SA3 000000011 4 003000h–003FFFh SA4 000000100 4 004000h–004FFFh SA5 000000101 4 005000h–005FFFh SA6 000000110 4 006000h–006FFFh SA7 000000111 4 007000h–007FFFh SA8 000001XXX 32 008000h–00FFFFh SA9 000010XXX 32 010000h–017FFFh SA10 000011XXX 32 018000h–01FFFFh SA11 000100XXX 32 020000h–027FFFh SA12 000101XXX 32 028000h–02FFFFh SA13 000110XXX 32 030000h–037FFFh SA14 000111XXX 32 038000h–03FFFFh SA15 001000XXX 32 040000h–047FFFh SA16 001001XXX 32 048000h–04FFFFh SA17 001010XXX 32 050000h–057FFFh SA18 001011XXX 32 058000h–05FFFFh SA19 001100XXX 32 060000h–067FFFh SA20 001101XXX 32 068000h–06FFFFh SA21 001110XXX 32 070000h–077FFFh SA22 001111XXX 32 078000h–07FFFFh SA23 010000XXX 32 080000h–087FFFh SA24 010001XXX 32 088000h–08FFFFh SA25 010010XXX 32 090000h–097FFFh SA26 010011XXX 32 098000h–09FFFFh SA27 010100XXX 32 0A0000h–0A7FFFh SA28 010101XXX 32 0A8000h–0AFFFFh SA29 010110XXX 32 0B0000h–0B7FFFh SA30 010111XXX 32 0B8000h–0BFFFFh SA31 011000XXX 32 0C0000h–0C7FFFh SA32 011001XXX 32 0C8000h–0CFFFFh SA33 011010XXX 32 0D0000h–0D7FFFh SA34 011011XXX 32 0D8000h–0DFFFFh SA35 011100XXX 32 0E0000h–0E7FFFh SA36 011101XXX 32 0E8000h–0EFFFFh SA37 011110XXX 32 0F0000h–0F7FFFh 0F8000h–0FFFFFh SA38 011111XXX 32 SA39 100000XXX 32 100000h–107FFFh SA40 100001XXX 32 108000h–10FFFFh SA41 100010XXX 32 110000h–117FFFh SA42 100011XXX 32 118000h–11FFFFh SA43 100100XXX 32 120000h–127FFFh Document Number: 002-00615 Rev. *F Bank C Bank D Bank B Bank A Bank Bank Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) 100101XXX 32 128000h–12FFFFh 100110XXX 32 130000h–137FFFh SA46 100111XXX 32 138000h–13FFFFh SA47 101000XXX 32 140000h–147FFFh SA48 101001XXX 32 148000h–14FFFFh SA49 101010XXX 32 150000h–157FFFh SA50 101011XXX 32 158000h–15FFFFh SA51 101100XXX 32 160000h–167FFFh SA52 101101XXX 32 168000h–16FFFFh SA53 101110XXX 32 170000h–177FFFh 178000h–17FFFFh Sector Sector Address (A22-A12) SA44 SA45 SA54 101111XXX 32 SA55 110000XXX 32 180000h–187FFFh SA56 110001XXX 32 188000h–18FFFFh SA57 110010XXX 32 190000h–197FFFh SA58 110011XXX 32 198000h–19FFFFh SA59 110100XXX 32 1A0000h–1A7FFFh SA60 110101XXX 32 1A8000h–1AFFFFh SA61 110110XXX 32 1B0000h–1B7FFFh SA62 110111XXX 32 1B8000h–1BFFFFh SA63 111000XXX 32 1C0000h–1C7FFFh SA64 111001XXX 32 1C8000h–1CFFFFh SA65 111010XXX 32 1D0000h–1D7FFFh SA66 111011XXX 32 1D8000h–1DFFFFh SA67 111100XXX 32 1E0000h–1E7FFFh SA68 111101XXX 32 1E8000h–1EFFFFh SA69 111110XXX 32 1F0000h–1F7FFFh SA70 111111000 4 1F8000h–1F8FFFh SA71 111111001 4 1F9000h–1F9FFFh SA72 111111010 4 1FA000h–1FAFFFh SA73 111111011 4 1FB000h–1FBFFFh SA74 111111100 4 1FC000h–1FCFFFh SA75 111111101 4 1FD000h–1FDFFFh SA76 111111110 4 1FE000h–1FEFFFh SA77 111111111 4 1FF000h–1FFFFFh Page 26 of 80 S29PL-J Table 19. Secured Silicon Sector Addresses Sector Size 10.8 Address Range Factory-Locked Area 64 words 000000h-00003Fh Customer-Lockable Area 64 words 000040h-00007Fh Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 20 on page 27. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 15 on page 19). Table 20 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 28 on page 49. Note that if a Bank Address (BA) (on address bits PL127J: A22–A20, PL064J: A21–A19, PL032J: A20–A18) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 28. This method does not require VID. Refer to the Section 15.3 Autoselect Command Sequence on page 43 for more information. Table 20. Autoselect Codes (High Voltage Method) Description Device ID Manufacturer ID: Cypress products CE# OE# L L WE# Amax to A12 A10 H BA X A9 A8 A7 VID X L A6 A5 to A4 A3 L X A2 A1 A0 DQ15 to DQ0 L L L L 0001h Read Cycle 1 L L L L H 227Eh Read Cycle 2 L H H H L 2220h (PL127J) 2202h (PL064J) 220Ah (PL032J) Read Cycle 3 L H H H H 2200h (PL127J) 2201h (PL064J) 2201h (PL032J) L L H L 0001h (protected), 0000h (unprotected) H DQ7=1 (factory locked), DQ6=1 (factory and customer locked) Sector Protection Verification Secured Silicon Indicator Bit (DQ7, DQ6) L L L L L H BA H SA H BA[14] X X X VID VID VID X X X L L X L L L L L X L L H Note 14. When Polling the Secured Silicon indicator bit the Bank Address (BA) should be set within the address range 004000h-03FFFFh. Legend L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Document Number: 002-00615 Rev. *F Page 27 of 80 S29PL-J Table 21. PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A22-A12 Sector/Sector Block Size Sector A22-A12 Sector/Sector Block Size SA0 00000000000 4 Kwords SA131-SA134 011111XXXXX 128 (4x32) Kwords SA1 00000000001 4 Kwords SA135-SA138 100000XXXXX 128 (4x32) Kwords SA2 00000000010 4 Kwords SA139-SA142 100001XXXXX 128 (4x32) Kwords SA3 00000000011 4 Kwords SA143-SA146 100010XXXXX 128 (4x32) Kwords SA4 00000000100 4 Kwords SA147-SA150 100011XXXXX 128 (4x32) Kwords SA5 00000000101 4 Kwords SA151-SA154 100100XXXXX 128 (4x32) Kwords SA6 00000000110 4 Kwords SA155-SA158 100101XXXXX 128 (4x32) Kwords SA7 00000000111 4 Kwords SA159-SA162 100110XXXXX 128 (4x32) Kwords SA8 00000001XXX 32 Kwords SA163-SA166 100111XXXXX 128 (4x32) Kwords SA9 00000010XXX 32 Kwords SA167-SA170 101000XXXXX 128 (4x32) Kwords SA10 00000011XXX 32 Kwords SA171-SA174 101001XXXXX 128 (4x32) Kwords SA11-SA14 000001XXXXX 128 (4x32) Kwords SA175-SA178 101010XXXXX 128 (4x32) Kwords SA15-SA18 000010XXXXX 128 (4x32) Kwords SA179-SA182 101011XXXXX 128 (4x32) Kwords SA19-SA22 000011XXXXX 128 (4x32) Kwords SA183-SA186 101100XXXXX 128 (4x32) Kwords SA23-SA26 000100XXXXX 128 (4x32) Kwords SA187-SA190 101101XXXXX 128 (4x32) Kwords SA27-SA30 000101XXXXX 128 (4x32) Kwords SA191-SA194 101110XXXXX 128 (4x32) Kwords SA31-SA34 000110XXXXX 128 (4x32) Kwords SA195-SA198 101111XXXXX 128 (4x32) Kwords SA35-SA38 000111XXXXX 128 (4x32) Kwords SA199-SA202 110000XXXXX 128 (4x32) Kwords SA39-SA42 001000XXXXX 128 (4x32) Kwords SA203-SA206 110001XXXXX 128 (4x32) Kwords SA43-SA46 001001XXXXX 128 (4x32) Kwords SA207-SA210 110010XXXXX 128 (4x32) Kwords SA47-SA50 001010XXXXX 128 (4x32) Kwords SA211-SA214 110011XXXXX 128 (4x32) Kwords SA51-SA54 001011XXXXX 128 (4x32) Kwords SA215-SA218 110100XXXXX 128 (4x32) Kwords SA55-SA58 001100XXXXX 128 (4x32) Kwords SA219-SA222 110101XXXXX 128 (4x32) Kwords SA59-SA62 001101XXXXX 128 (4x32) Kwords SA223-SA226 110110XXXXX 128 (4x32) Kwords SA63-SA66 001110XXXXX 128 (4x32) Kwords SA227-SA230 110111XXXXX 128 (4x32) Kwords SA67-SA70 001111XXXXX 128 (4x32) Kwords SA231-SA234 111000XXXXX 128 (4x32) Kwords SA71-SA74 010000XXXXX 128 (4x32) Kwords SA235-SA238 111001XXXXX 128 (4x32) Kwords SA75-SA78 010001XXXXX 128 (4x32) Kwords SA239-SA242 111010XXXXX 128 (4x32) Kwords SA79-SA82 010010XXXXX 128 (4x32) Kwords SA243-SA246 111011XXXXX 128 (4x32) Kwords SA83-SA86 010011XXXXX 128 (4x32) Kwords SA247-SA250 111100XXXXX 128 (4x32) Kwords SA87-SA90 010100XXXXX 128 (4x32) Kwords SA251-SA254 111101XXXXX 128 (4x32) Kwords SA91-SA94 010101XXXXX 128 (4x32) Kwords SA255-SA258 111110XXXXX 128 (4x32) Kwords SA95-SA98 010110XXXXX 128 (4x32) Kwords SA259 11111100XXX 32 Kwords SA99-SA102 010111XXXXX 128 (4x32) Kwords SA260 11111101XXX 32 Kwords SA103-SA106 011000XXXXX 128 (4x32) Kwords SA261 11111110XXX 32 Kwords SA107-SA110 011001XXXXX 128 (4x32) Kwords SA262 11111111000 4 Kwords SA111-SA114 011010XXXXX 128 (4x32) Kwords SA263 11111111001 4 Kwords SA115-SA118 011011XXXXX 128 (4x32) Kwords SA264 11111111010 4 Kwords SA119-SA122 011100XXXXX 128 (4x32) Kwords SA265 11111111011 4 Kwords SA123-SA126 011101XXXXX 128 (4x32) Kwords SA127-SA130 011110XXXXX 128 (4x32) Kwords The device is shipped with all sectors unprotected. Optional Cypress programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See Table 19 on page 27 for details. Document Number: 002-00615 Rev. *F Page 28 of 80 S29PL-J 10.9 Selecting a Sector Protection Mode Table 22. PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21-A12 Sector/Sector Block Size Sector A21-A12 Sector/Sector Block Size SA0 0000000000 SA1 0000000001 4 Kwords SA115-SA118 11011XXXXX 128 (4x32) Kwords 4 Kwords SA119-SA122 11100XXXXX 128 (4x32) Kwords SA2 0000000010 SA3 0000000011 4 Kwords SA123-SA126 11101XXXXX 128 (4x32) Kwords 4 Kwords SA127-SA130 11110XXXXX 128 (4x32) Kwords SA4 0000000100 4 Kwords SA131 1111100XXX 32 Kwords SA5 0000000101 4 Kwords SA132 1111101XXX 32 Kwords SA6 0000000110 4 Kwords SA133 1111110XXX 32 Kwords SA7 0000000111 4 Kwords SA134 1111111000 4 Kwords SA8 0000001XXX 32 Kwords SA135 1111111001 4 Kwords SA9 0000010XXX 32 Kwords SA136 1111111010 4 Kwords SA10 0000011XXX 32 Kwords SA137 1111111011 4 Kwords SA11-SA14 00001XXXXX 128 (4x32) Kwords SA138 1111111100 4 Kwords SA15-SA18 00010XXXXX 128 (4x32) Kwords SA19-SA22 00011XXXXX 128 (4x32) Kwords SA23-SA26 00100XXXXX 128 (4x32) Kwords SA27-SA30 00101XXXXX 128 (4x32) Kwords SA31-SA34 00110XXXXX 128 (4x32) Kwords SA35-SA38 00111XXXXX 128 (4x32) Kwords SA39-SA42 01000XXXXX 128 (4x32) Kwords SA43-SA46 01001XXXXX 128 (4x32) Kwords SA47-SA50 01010XXXXX 128 (4x32) Kwords SA51-SA54 01011XXXXX 128 (4x32) Kwords SA55-SA58 01100XXXXX 128 (4x32) Kwords SA59-SA62 01101XXXXX 128 (4x32) Kwords SA63-SA66 01110XXXXX 128 (4x32) Kwords SA67-SA70 01111XXXXX 128 (4x32) Kwords SA71-SA74 10000XXXXX 128 (4x32) Kwords SA75-SA78 10001XXXXX 128 (4x32) Kwords SA79-SA82 10010XXXXX 128 (4x32) Kwords SA83-SA86 10011XXXXX 128 (4x32) Kwords SA87-SA90 10100XXXXX 128 (4x32) Kwords SA91-SA94 10101XXXXX 128 (4x32) Kwords SA95-SA98 10110XXXXX 128 (4x32) Kwords SA99-SA102 10111XXXXX 128 (4x32) Kwords SA103-SA106 11000XXXXX 128 (4x32) Kwords SA107-SA110 11001XXXXX 128 (4x32) Kwords SA111-SA114 11010XXXXX 128 (4x32) Kwords Document Number: 002-00615 Rev. *F Page 29 of 80 S29PL-J Table 23. Sector Protection Schemes DYB PPB PPB Lock 0 0 0 Unprotected—PPB and DYB are changeable 0 0 1 Unprotected—PPB not changeable, DYB is changeable 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Document Number: 002-00615 Rev. *F Sector State Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable Page 30 of 80 S29PL-J 11. Sector Protection The PL127J, PL064J, and PL032J features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: 11.1 Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. 11.2 Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted 11.3 WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors SA1-133, SA1-134, SA2-0 and SA2-1. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. 11.4 Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. Optional Cypress programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 27 for details. Document Number: 002-00615 Rev. *F Page 31 of 80 S29PL-J 12. Persistent Sector Protection The Persistent Sector Protection method replaces the 12 V controlled protection method in previous flash devices. This new method provides three different sector protection states: ■ Persistently Locked—The sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command. ■ Unlocked—The sector is unprotected and can be changed by a simple command. To achieve these states, three types of “bits” are used: ■ Persistent Protection Bit ■ Persistent Protection Bit Lock ■ Persistent Sector Protection Mode Locking Bit 12.1 Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. 12.2 Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. 12.3 Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. Document Number: 002-00615 Rev. *F Page 32 of 80 S29PL-J For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persistently protect a given sector or sector group, the PPBs associated with that sector need to be set to “1”. Once all PPBs are programmed to the desired settings, the PPB Lock should be set to “1”. Setting the PPB Lock automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. Table 23 on page 30 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. There is an alternative means of reading the protection status. Take RESET# to VIL and hold WE# at VIH. (The high voltage A9 Autoselect Mode also works for reading the status of the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) will produce a logical ‘1” code at device output DQ0 for a protected sector or a “0” for an unprotected sector. In this mode, the other addresses are don’t cares. Address location with A1 = VIL are reserved for autoselect manufacturer and device codes. 12.4 Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Document Number: 002-00615 Rev. *F Page 33 of 80 S29PL-J 13. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 13.1 Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 13.2 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Document Number: 002-00615 Rev. *F Page 34 of 80 S29PL-J 13.3 Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the upper two and lower two sectors without using VID. This function is provided by the WP# pin and overrides the previously discussed Section 13.4 High Voltage Sector Protection on page 35 method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two sectors to whether they were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in the Section 13.4 High Voltage Sector Protection on page 35. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 13.3.1 Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. 13.4 High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 6 on page 36 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. Document Number: 002-00615 Rev. *F Page 35 of 80 S29PL-J Figure 6. In-System Sector Protection/Sector Unprotection Algorithms START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 μs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 μs First Write Cycle = 60h? First Write Cycle = 60h? Temporary Sector Unprotect Mode Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Wait 150 µs Increment PLSCNT No Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Reset PLSCNT = 1 Read from sector address with A7-A0 = 00000010 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Increment PLSCNT No No PLSCNT = 25? Yes Yes No Yes Remove VID from RESET# Protect another sector? No Write reset command Sector Protect complete Device failed Read from sector address with A7-A0 = 00000010 Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Sector Protect Algorithm PLSCNT = 1000? Yes Remove VID from RESET# Set up next sector address No Data = 00h? Yes Last sector verified? No Yes Write reset command Sector Protect complete Device failed Remove VID from RESET# Write reset command Sector Unprotect complete Sector Unprotect Algorithm Document Number: 002-00615 Rev. *F Page 36 of 80 S29PL-J 13.5 Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 7 on page 37 shows the algorithm, and Figure 26 on page 68 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode. Figure 7. Temporary Sector Unprotect Operation[15, 16] START RESET# = VID Note 15 Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed Note 16 13.6 Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word Secured Silicon sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The Secured Silicon sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the factory-locked and customer locked status of the part. The system accesses the Secured Silicon Sector through a command sequence (see Section 15.4 Enter/Exit Secured Silicon Sector Command Sequence on page 44). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. Once the Enter SecSi Sector Command sequence has been entered, the standard array cannot be accessed until the Exit SecSi Sector command has been entered or the device has been reset. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. 13.6.1 Factory-Locked Area (64 words) The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. Optional Cypress programming services can program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only Cypress can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact your local sales office for details on using Cypress’s programming services. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon sector is enabled. Notes 15. All protected sectors unprotected (If WP#/ACC = VIL, upper two and lower two sectors will remain protected). 16. All previously protected sectors are protected once again. Document Number: 002-00615 Rev. *F Page 37 of 80 S29PL-J 13.6.2 Customer-Lockable Area (64 words) The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The Secured Silicon Sector Customer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the Secured Silicon Protection Bit Program Command. The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector. The Customer-lockable Secured Silicon Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 6 on page 36, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. ■ To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 8 on page 38. ■ Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. The Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. 13.6.3 Secured Silicon Sector Protection Bits The Secured Silicon Sector Protection Bits prevent programming of the Secured Silicon Sector memory area. Once set, the Secured Silicon Sector memory area contents are non-modifiable. Figure 8. Secured Silicon Sector Protect Verify START RESET# = VIH or VID Wait 1 µs Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Document Number: 002-00615 Rev. *F If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write reset command SecSi Sector Protect Verify complete Page 38 of 80 S29PL-J 13.7 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. 13.7.1 Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. 13.7.2 Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle. 13.7.3 Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. 13.7.4 Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Document Number: 002-00615 Rev. *F Page 39 of 80 S29PL-J 14. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 24 on page 40 to Table 27 on page 42. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 24 through Table 27. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of these documents. Table 24. CFI Query Identification String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Table 25. System Interface String Addresses Data Description 1Bh 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0003h Typical timeout per single byte/word write 2N µs 20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0004h Max. timeout for byte/word write 2N times typical 24h 0000h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Document Number: 002-00615 Rev. *F Page 40 of 80 S29PL-J Table 26. Device Geometry Definition Addresses Data 27h 0018h (PL127J) 0017h (PL064J) 0016h (PL032J) 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 00FDh (PL127J) 007Dh (PL064J) 003Dh (PL032J) 32h 33h 34h 0000h 0000h 0001h 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Document Number: 002-00615 Rev. *F Description Device Size = 2N byte Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Page 41 of 80 S29PL-J Table 27. Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 0033h Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 45h TBD 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0007h (PLxxxJ) Sector Protect/Unprotect scheme 07 = Advanced Sector Protection 4Ah 00E7h (PL127J) 0077h (PL064J) 003Fh (PL032J) Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 4Bh 0000h 4Ch 0002h (PLxxxJ) 4Dh 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 0001h Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = Both top and bottom boot with write protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom 50h 0001h Program Suspend 0 = Not supported, 1 = Supported 57h 0004h Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks 58h 0027h (PL127J) 0017h (PL064J) 000Fh (PL032J) Bank 1 Region Information X = Number of Sectors in Bank 1 59h 0060h (PL127J) 0030h (PL064J) 0018h (PL032J) Bank 2 Region Information X = Number of Sectors in Bank 2 5Ah 0060h (PL127J) 0030h (PL064J) 0018h (PL032J) Bank 3 Region Information X = Number of Sectors in Bank 3 5Bh 0027h (PL127J) 0017h (PL064J) 000Fh (PL032J) Bank 4 Region Information X = Number of Sectors in Bank 4 Document Number: 002-00615 Rev. *F Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page Page 42 of 80 S29PL-J 15. Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 28 on page 49 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to Section 20. AC Characteristics on page 60 for timing diagrams. 15.1 Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Section 15.8 Erase Suspend/Erase Resume Commands on page 47 for more information. After the device accepts a Program Suspend command, the corresponding bank enters the program-suspend-read mode, after which the system can read data from any non-program-suspended sector within the same bank. See Section 15.9 Program Suspend/Program Resume Commands on page 48 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See Section 15.2 Reset Command on page 43 for more information. See also Section 10.1 Requirements for Reading Array Data on page 18 for more information. Section 20. AC Characteristics on page 60 provides the read parameters, and Figure 12 on page 54 shows the timing diagram. 15.2 Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend and program-suspend-read mode if that bank was in Program Suspend). 15.3 Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 28 on page 49 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 15 on page 19 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Document Number: 002-00615 Rev. *F Page 43 of 80 S29PL-J 15.4 Enter/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 28 on page 49 shows the address and data requirements for both command sequences. See also Section 13.6 Secured Silicon Sector Flash Memory Region on page 37 for further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. 15.5 Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 28 on page 49 shows the address and data requirements for the program command sequence. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to Section 16. Write Operation Status on page 52 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the Secured Silicon Sector, autoselect and CFI functions are unavailable when the Secured Silicon Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Document Number: 002-00615 Rev. *F Page 44 of 80 S29PL-J 15.5.1 Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 28 on page 49 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 29 on page 50) The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 9 on page 45 illustrates the algorithm for the program operation. Refer to the table Section 20.5 Erase/Program Operations on page 64 for parameters, and Figure 19 on page 65 for timing diagrams. Figure 9. Program Operation[17] START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note 17. See Table 28 on page 49 for program command sequence. Document Number: 002-00615 Rev. *F Page 45 of 80 S29PL-J 15.6 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 28 on page 49 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Section 16. Write Operation Status on page 52 for information on these status bits. Any commands written during the chip erase operation are ignored. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 10 on page 47 illustrates the algorithm for the erase operation. Refer to the tables in Section 20.5 Erase/Program Operations on page 64 for parameters, and Figure 21 on page 66 for timing diagrams. 15.7 Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 28 on page 49 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input during the time-out period, the normal operation will not be guaranteed. The system must rewrite the command sequence and any additional addresses and commands. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to Section 16. Write Operation Status on page 52 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 2 on page 12 illustrates the algorithm for the erase operation. Refer to the tables in Section 20.5 Erase/Program Operations on page 64 for parameters, and Figure 21 on page 66 for timing diagrams. Document Number: 002-00615 Rev. *F Page 46 of 80 S29PL-J Figure 10. Erase Operation START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed 15.8 Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Section 16. Write Operation Status on page 52 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to Section 16. Write Operation Status on page 52 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to Table 19 on page 27 and Section 15.3 Autoselect Command Sequence on page 43 for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Notes 18. See Table 28 on page 49 for erase command sequence. 19. See the section on DQ3 for information on the sector erase timer. Document Number: 002-00615 Rev. *F Page 47 of 80 S29PL-J If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. If the Secured Silicon Sector Protection Bit is verified as programmed without margin, the Secured Silicon Sector Protection Bit Program Command should be reissued to improve program margin. µµAfter programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. 15.9 Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the status bits. Addresses are “don’t-cares” when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in Program Suspend mode. The device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Section 15.3 Autoselect Command Sequence on page 43 for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Section 16. Write Operation Status on page 52 for more information. The system must write the Program Resume command (address bits are “don’t care”) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. Document Number: 002-00615 Rev. *F Page 48 of 80 S29PL-J 15.10 Command Definitions Tables Table 28 contains the Memory Array Command Definitions. Command (Notes) Cycles Table 28. Memory Array Command Definitions Bus Cycles (Notes 20–23) Addr Data Addr Data Addr Data Addr Data [24] 1 RA RD Reset[25] 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 (BA) 555 90 (BA) X00 01 Device ID[29] 6 555 AA 2AA 55 (BA) 555 90 (BA) X01 227E Secured Silicon Sector Factory Protect[27] 4 555 AA 2AA 55 (BA) 555 90 X03 Note [27] Sector Group Protect Verify[28] 4 555 AAA 2AA 55 (BA) 555 90 (SA) X02 XX00/ XX01 4 555 AA 2AA 55 555 A0 PA PD Autoselect[26] Read Program Addr Data Addr Data (BA) X0E Note [29] (BA) X0F Note [29] Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend[30] 1 BA B0 Program/Erase Resume[31] 1 BA 30 PD 555 20 [32] 1 55 98 Accelerated Program[33] 2 XX A0 PA Unlock Bypass Entry[33] 3 555 AA 2AA 55 Unlock Bypass Program[33] 2 XX A0 PA PD Unlock Bypass Erase[33] 2 XX 80 XX 10 Unlock Bypass CFI[32, 33] 1 XX 98 Unlock Bypass Reset[33] 2 XXX 90 XXX 00 CFI Query Legend BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by PL127J: Amax:A20, PL064J: Amax:A19, PL032J: Amax:A18. PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. RA = Read Address (Amax:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care Notes 20. See Table 13 for description of bus operations. 21. All values are in hexadecimal. 22. Shaded cells in table denote read cycles. All other cycles are write operations. 23. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 24. No unlock or command cycles required when bank is reading array data. 25. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 26. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Section 15.3 Autoselect Command Sequence on page 43 for more information. 27. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked. 28. The data is 00h for an unprotected sector group and 01h for a protected sector group. 29. Device ID must be read across cycles 4, 5, and 6. PL127J (X0Eh = 2220h, X0Fh = 2200h), PL064J (X0Eh = 2202h, X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h). 30. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 31. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 32. Command is valid when device is ready to read array data or when device is in autoselect mode. 33. WP#/ACC must be at VID during the entire operation of command. Document Number: 002-00615 Rev. *F Page 49 of 80 S29PL-J Cycles Table 29. Sector Protection Command Definitions Addr Data Reset 1 XXX F0 Secured Silicon Sector Entry[49] 3 555 Secured Silicon Sector Exit[49] 4 Secured Silicon Protection Bit Program[38, 39] Command (Notes) Bus Cycles (Notes 34-37) Addr Data Addr Data Addr Data Addr Data Addr Data AA 2AA 55 555 88 555 AA 2AA 55 555 90 XX 00 6 555 AA 2AA 55 555 60 OW 68 OW 48 OW RD (0) Secured Silicon Protection Bit Status 5 555 AA 2AA 55 555 60 OW 48 OW RD (0) Password Program[38, 40, 41] 4 555 AA 2AA 55 555 38 XX [0-3] PD [0-3] Password Verify[39, 41, 42] 4 555 AA 2AA 55 555 C8 PWA [0-3] PWD [0-3] Password Unlock[40, 43, 44] 7 555 AA 2AA 55 555 28 PWA [0] PWD [0] PWA [1] PWD [1] PWA [2] PWD [2] PPB Program[38, 39, 44] 6 555 AA 2AA 55 555 60 (SA) WP 68 (SA) WP 48 (SA) WP RD(0) PPB Status 4 555 AA 2AA 55 BA+55 5 90 (SA) WP RD (0) All PPB Erase[38, 39, 46, 47] 6 555 AA 2AA 55 555 60 WP 60 (SA) 40 (SA) WP RD(0) PPB Lock Bit Set 3 555 AA 2AA 55 555 78 58 SA RD (1) X1 PL 48 PL RD(0) RD (0) SL RD(0) PPB Lock Bit Status 4 555 AA 2AA 55 BA+55 5 DYB Write[40] 4 555 AA 2AA 55 555 48 SA 4 555 AA 2AA 55 555 48 SA X0 58 SA RD (0) 60 PL 68 [48] DYB Erase [40] DYB Status [39] PPMLB Program PPMLB Status [38] SPMLB Program SPMLB Status [38, 39, 45] [38, 39, 45] [38] 4 555 AA 2AA 55 BA+55 5 6 555 AA 2AA 55 555 5 555 AA 2AA 55 555 60 PL 48 PL 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD (0) 5 555 AA 2AA 55 555 60 SL 48 Addr Data PWA [3] PWD [3] Legend DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit Document Number: 002-00615 Rev. *F Page 50 of 80 S29PL-J Notes 34. See Table 13 on page 18 for description of bus operations. 35. All values are in hexadecimal. 36. Shaded cells in table denote read cycles. All other cycles are write operations. 37. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 38. The reset command returns device to reading array. 39. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 40. Data is latched on the rising edge of WE#. 41. Entire command sequence must be entered for each portion of password. 42. Command sequence returns FFh if PPMLB is set. 43. The password is written over four consecutive cycles, at addresses 0-3. 44. A 2 µs timeout is required between any two portions of password. 45. A 100 µs timeout is required between cycles 4 and 5. 46. A 1.2 ms timeout is required between cycles 4 and 5. 47. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 48. DQ1 = 1 if PPB locked, 0 if unlocked. 49. Once the Secured Silicon Sector Entry Command sequence has been entered, the standard array cannot be accessed until the Exit SecSi Sector command has been entered or the device has been reset. Document Number: 002-00615 Rev. *F Page 51 of 80 S29PL-J 16. Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 30 on page 56 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. 16.1 DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15– DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15– DQ0 will appear on successive read cycles. Table 30 on page 56 shows the outputs for Data# Polling on DQ7. Figure 11 on page 52 shows the Data# Polling algorithm. Figure 23 on page 67 shows the Data# Polling timing diagram. Figure 11. Data# Polling Algorithm[50, 51] START Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes 50. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 51. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Document Number: 002-00615 Rev. *F Page 52 of 80 S29PL-J 16.2 RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 30 on page 56 shows the outputs for RY/BY#. 16.3 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the Section 16.1 DQ7: Data# Polling on page 52). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 30 on page 56 shows the outputs for Toggle Bit I on DQ6. Figure 12 on page 54 shows the toggle bit algorithm. Figure 24 on page 67 in shows the toggle bit timing diagrams. Figure 25 on page 68 shows the differences between DQ2 and DQ6 in graphical form. See also Section 16.4 DQ2: Toggle Bit II on page 55. Document Number: 002-00615 Rev. *F Page 53 of 80 S29PL-J Figure 12. Toggle Bit Algorithm[52] START Read Byte (DQ7–DQ0) Address =VA Read Byte (DQ7–DQ0) Address =VA Toggle Bit = Toggle? No Yes No DQ5 = 1? Yes Read Byte Twice (DQ7–DQ0) Address = VA Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note 52. The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the Section 16.3 DQ6: Toggle Bit I on page 53 and Section 16.4 DQ2: Toggle Bit II on page 55 for more information. Document Number: 002-00615 Rev. *F Page 54 of 80 S29PL-J 16.4 DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 30 on page 56 to compare outputs for DQ2 and DQ6. Figure 12 on page 54 shows the toggle bit algorithm in flowchart form, and the Section 16.4 DQ2: Toggle Bit II on page 55 explains the algorithm. See also the Section 16.3 DQ6: Toggle Bit I on page 53. Figure 24 on page 67 shows the toggle bit timing diagram. Figure 25 on page 68 shows the differences between DQ2 and DQ6 in graphical form. 16.5 Reading Toggle Bits DQ6/DQ2 Refer to Figure 12 on page 54 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7– DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the devic did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 12). 16.6 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). Document Number: 002-00615 Rev. *F Page 55 of 80 S29PL-J 16.7 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also Section 15.7 Sector Erase Command Sequence on page 46. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 30 shows the status of DQ3 relative to the other status bits. Table 30. Write Operation Status DQ7[54] DQ6 DQ5[53] DQ3 DQ2[54] RY/BY# DQ7# Toggle 0 N/A No toggle 0 0 Toggle 0 1 Toggle 0 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 DQ7# Toggle 0 N/A N/A 0 Invalid (Not Allowed) Invalid (Not Allowed) Invalid (Not Allowed) Invalid (Not Allowed) Invalid (Not Allowed) 1 Data Data Data Data Data 1 Status Embedded Program Standard Algorithm Mode Embedded Erase Algorithm Erase Suspend Mode Erase Erase Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend -Program Reading within Program Program Suspended Sector Suspend Reading within Mode[55] Non-program Suspended Sector Notes 53. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to Section 16.6 DQ5: Exceeded Timing Limits on page 55 for more information. 54. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 55. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Document Number: 002-00615 Rev. *F Page 56 of 80 S29PL-J 17. Absolute Maximum Ratings Storage Temperature Plastic Packages –65°C to +150°C Ambient Temperature with Power Applied –65°C to +125°C Voltage with Respect to Ground VCC[56] –0.5 V to +4.0 V [57] A9, OE#, and RESET# –0.5 V to +12.5 V WP#/ACC[57] –0.5 V to +10.5 V All other pins [56] –0.5 V to VCC +0.5 V [58] 200 mA Output Short Circuit Current Figure 13. Maximum Overshoot Waveforms 20 ns 20 ns 20 ns VCC +2.0 V VCC +0.5 V +0.8 V –0.5 V –2.0 V 2.0 V 20 ns Maximum Negative Overshoot Waveform 20 ns 20 ns Maximum Positive Overshoot Waveform Notes 56. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 13 on page 57. 57. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 13 on page 57. Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 58. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 59. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 002-00615 Rev. *F Page 57 of 80 S29PL-J 18. Operating Ranges Operating ranges define those limits between which the functionality of the device is guaranteed. Industrial (I) Devices Ambient Temperature (TA)............................ –40°C to +85°C Wireless (W) Devices Ambient Temperature (TA)............................ –25°C to +85°C Supply Voltages VCC ........................................................................ 2.7–3.6 V VIO (see Note)1.65–1.95 V (for PL127J) or 2.7–3.6 V (for all PLxxxJ devices) Note 60. For all AC and DC specifications, VIO = VCC; contact your local sales office for other VIO options. Document Number: 002-00615 Rev. *F Page 58 of 80 S29PL-J 19. DC Characteristics Table 31. CMOS Compatible Parameter Parameter Description (notes) Test Conditions Min Typ Max Unit 1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9, OE#, RESET# Input Load Current VCC = VCC max; VID= 12.5 V 35 µA ILR Reset Leakage Current VCC = VCC max; VID= 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH VCC = VCC max 1.0 µA ICC1 VCC Active Read Current[61, 62] OE# = VIH, VCC = VCC max ICC2 VCC Active Write Current[62, 63] ICC3 VCC Standby Current[62] Current[62] 5 MHz 20 30 10 MHz 45 55 OE# = VIH, WE# = VIL 15 25 mA CE#, RESET#, WP#/ACC = VIO 0.3 V 0.2 5 µA mA ICC4 VCC Reset RESET# = VSS 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode[62, 64] VIH = VIO  0.3 V; VIL = VSS 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current[61, 62] OE# = VIH, 5 MHz 21 45 10 MHz 46 70 ICC7 VCC Active Read-While-Erase Current[61, 62] OE# = VIH, 5 MHz 21 45 10 MHz 46 70 ICC8 VCC Active Program-While-EraseSuspended Current[62, 65] OE# = VIH 17 25 mA ICC9 VCC Active Page Read Current[62] OE# = VIH, 8 word Page Read 10 15 mA VIL Input Low Voltage VIO = 1.65–1.95 V (PL127J) –0.4 0.4 V VIO = 2.7–3.6 V –0.5 0.8 V VIO–0.4 VIO+0.4 V VIO = 2.7–3.6 V 2.0 VCC+0.3 V VIH VIO = 1.65–1.95 V (PL127J) Input High Voltage mA mA VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V  10% 11.5 12.5 V 0.1 V Output Low Voltage IOL = 100 µA, VCC = VCC min, VIO = 1.65–1.95 V (PL127J) IOL = 2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V 0.4 V VOL VOH VLKO Output High Voltage Low VCC Lock-Out Voltage [65] IOH = –100 µA, VCC = VCC min, VIO = 1.65–1.95 V (PL127J) VIO–0.1 V IOH = ––100 µA, VIO = VCC min VCC–0.2V V 2.3 2.5 V Notes 61. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. 62. Maximum ICC specifications are tested with VCC = VCCmax. 63. ICC active while Embedded Erase or Embedded Program is in progress. 64. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 2 µA. 65. Not 100% tested. Document Number: 002-00615 Rev. *F Page 59 of 80 S29PL-J 20. AC Characteristics 20.1 Test Conditions Figure 14. Test Setups[66] 3.6 V 2.7 k Device Under Test Device Under Test CL CL 6.2 k VIO = 3.0 V VIO = 1.8 V (PL127J) Table 32. Test Specifications Test Conditions Output Load Input Pulse Levels Unit 1 TTL gate Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times All Speeds VIO = 1.8 V (PL127J) VIO = 3.0 V 30 pF 5 ns VIO = 1.8 V (PL127J) 0.0 - 1.8 VIO = 3.0 V 0.0–3.0 V Input timing measurement reference levels VIO/2 V Output timing measurement reference levels VIO/2 V Note 66. Diodes are IN3064 or equivalent. Document Number: 002-00615 Rev. *F Page 60 of 80 S29PL-J 20.2 Switching Waveforms Table 33. Key To Switching Waveforms Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) Figure 15. Input Waveforms and Measurement Levels VIO VIO/2 Input VIO/2 Measurement Level Output 0.0 V 20.3 Read Operations Table 34. Read-Only Operations Parameter Description (Notes) JEDEC Std. tAVAV tRC Read Cycle Time[67] tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tPACC Speed Options Test Setup 55 60 65 70 80 Unit Min 55 60 65 70 80 ns CE#, OE# = VIL Max 55 60 65 70 80 ns OE# = VIL Max 55 60 65 70 80 ns Page Access Time Max 20 25 25 30 30 ns 20 25 35 ns tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z[69] Max 16 ns [67, 69] 30 tGHQZ tDF Output Enable to Output High Z Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First[69] Min 5 ns Output Enable Hold Time[67] Read Min 0 ns tOEH Toggle and Data# Polling Min 10 ns Notes 67. Not 100% tested. 68. See Figure 14 on page 60 and Table 32 on page 60 for test specifications 69. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE# high to the data bus driven to VCC /2 is taken as tDF. 70. For 70 pF Output Load Capacitance, 2 ns will be added to the above tACC,tCE,tPACC,tOE values for all speed grades Document Number: 002-00615 Rev. *F Page 61 of 80 S29PL-J Figure 16. Read Operation Timings tRC Addresses Stable Addresses tACC CE# tRH tRH tD tOE OE# tOEH WE tCE tOH High Z Data High Z Valid Data RESET# RY/BY# 0V Figure 17. Page Read Operation Timings Same Page Amax-A3 A2-A0 Aa tACC Data Ab tPACC Qa Ad Ac tPACC Qb tPACC Qc Qd CE# OE# Document Number: 002-00615 Rev. *F Page 62 of 80 S29PL-J 20.4 Reset Table 35. Hardware Reset (RESET#) Parameter JEDEC tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode[71] tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode tRP All Speed Options Unit Max 20 µs Max 500 ns Min 500 ns Min 50 ns Description Std [71] RESET# Pulse Width [71] tRH Reset High Time Before Read tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note 71. Not 100% tested. Figure 18. Reset Timings RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Document Number: 002-00615 Rev. *F Page 63 of 80 S29PL-J 20.5 Erase/Program Operations Table 36. Erase and Program Operations Parameter Speed Options (ns) Description JEDEC Std tAVAV tWC Write Cycle Time[72] tAS Min 55 60 65 70 80 55 60 65 70 80 Unit Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min tDVWH tDS Data Setup Time Min tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tAVWL tWLAX 30 35 0 25 ns ns 30 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min tSR/W Latency Between Read and Write Operations Min 0 ns Typ 6 µs Typ 4 µs Typ 0.5 sec Min 50 µs Operation[73] tWHWH1 tWHWH1 Programming tWHWH1 tWHWH1 Accelerated Programming Operation[73] tWHWH2 tWHWH2 Sector Erase Operation[73] Time[72] 20 25 ns tVCS VCC Setup tRB Write Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Max 90 ns Min 35 ns tBUSY tPSL Program Suspend Latency Max 35 µs tESL Erase Suspend Latency Max 35 µs Notes 72. Not 100% tested. 73. See Table 39 on page 71 for more information. Document Number: 002-00615 Rev. *F Page 64 of 80 S29PL-J 20.6 Timing Diagrams Figure 19. Program Operation Timings[74] Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# VCC tVCS Figure 20. Accelerated Program Timing Diagram VHH WP#/ACC VIL or VIH VIL or VIH tVHH tVHH Note 74. PA = program address, PD = program data, DOUT is the true data at the program address. Document Number: 002-00615 Rev. *F Page 65 of 80 S29PL-J Figure 21. Chip/Sector Erase Operation Timings[75] Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h 30h Status DOUT 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Figure 22. Back-to-back Read/Write Cycle Timings Addresses tWC tWC tRC Valid PA Valid RA tWC tAS Valid PA Valid PA tAH tAS tCPH tACC tAH tCE CE# tCP tOE OE# tOEH tGHWL tWP WE# tWPH tDF tDS tOH tDH Data Valid Out Valid In Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles Note 75. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Section 16. Write Operation Status on page 52). Document Number: 002-00615 Rev. *F Page 66 of 80 S29PL-J Figure 23. Data# Polling Timings (During Embedded Algorithms)[76] tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ6–DQ0 Status Data Status Data Valid Data True High Z Valid Data True tBUSY RY/BY# Figure 24. Toggle Bit Timings (During Embedded Algorithms)[77] tAHT tAS Addresses tAHT tASO CE# tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data tOE Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data RY/BY# Notes 76. VA = Valid address. The illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 77. VA = Valid address; not required for DQ6. The illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Document Number: 002-00615 Rev. *F Page 67 of 80 S29PL-J Figure 25. DQ2 vs. DQ6[78] Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Read Erase Complete Erase DQ6 DQ2 21. Protect/Unprotect Table 37. Temporary Sector Unprotect[79] Parameter JEDEC Description Std All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min 4 µs Note 79. Not 100% tested. Figure 26. Temporary Sector Unprotect Timing Diagram VID VID RESET# VIL or VIH VIL or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP tRRB RY/BY# Note 78. DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Document Number: 002-00615 Rev. *F Page 68 of 80 S29PL-J Figure 27. Sector/Sector Block Protect and Unprotect Timing Diagram[80] VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Group Protect/Unprotect Data 60h Valid* Verify 60h 40h Status 1 µs Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms CE# WE# OE# 21.1 Controlled Erase Operations Table 38. Alternate CE# Controlled Erase and Program Operations Parameter Speed Options Description (Notes) Std tAVAV tWC Write Cycle Time[81, 82] Min tAVWL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 30 35 ns tDVEH tDS Data Setup Time Min 25 30 ns tEHDX tDH Data Hold Time Min 0 ns Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tGHEL tGHEL 55 60 65 70 80 55 60 65 70 80 Unit JEDEC 0 ns ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 40 ns tEHEL tCPH CE# Pulse Width High Min 20 25 ns [82] tWHWH1 tWHWH1 Programming Operation tWHWH1 tWHWH1 Accelerated Programming Operation[82] tWHWH2 [82] tWHWH2 Sector Erase Operation Typ 6 µs Typ 4 µs Typ 0.5 sec Notes 81. Not 100% tested. 82. See Section 39 Erase And Programming Performance on page 71 for more information. Note 80. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Document Number: 002-00615 Rev. *F Page 69 of 80 S29PL-J Figure 28. Alternate CE# Controlled Write (Erase/Program) Operation Timings[83, 84, 85] 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Figure 29. Timing Diagram for Alternating Between CE1# and CE2# Control CE1# tCCR tCCR CE2# Notes 83. Figure indicates last two bus cycles of a program or erase operation. 84. PA = program address, SA = sector address, PD = program data. 85. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. Document Number: 002-00615 Rev. *F Page 70 of 80 S29PL-J Table 39. Erase And Programming Performance Typ[86] Max[87] Unit 0.5 5 sec PL127J 135 216 sec PL064J 71 113.6 sec PL032J Parameter Sector Erase Time Chip Erase Time 39 62.4 sec Word Program Time 6 100 µs Accelerated Word Program 4 60 µs PL127J 50.4 200 sec PL064J 25.2 50.4 sec PL032J 12.6 25.2 sec Chip Program Time[88] Comments Excludes 00h programming prior to erasure[89] Excludes system level overhead[90] Notes 86. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 87. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 88. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 89. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 90. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 28 on page 49 for further information on command definitions. 91. The device has a minimum erase and program cycle endurance of 100,000 cycles. Document Number: 002-00615 Rev. *F Page 71 of 80 S29PL-J 22. Pin Capacitance 22.1 BGA Pin Capacitance Parameter Symbol CIN Parameter Description Input Capacitance Test Setup Typ Max Unit VIN = 0 6.3 7 pF COUT Output Capacitance VOUT = 0 7.0 8 pF CIN2 Control Pin Capacitance VIN = 0 5.5 8 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 11 12 pF Test Setup Typ Max Unit VIN = 0 10 10.5 pF Notes 92. Sampled, not 100% tested. 93. Test conditions TA = 25°C, f = 1.0 MHz. 22.2 TSOP Pin Capacitance Parameter Symbol CIN Parameter Description Input Capacitance COUT Output Capacitance VOUT = 0 5.5 6.5 pF CIN2 Control Pin Capacitance VIN = 0 8 10 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 9.5 10 pF Notes 94. Sampled, not 100% tested. 95. Test conditions TA = 25°C, f = 1.0 MHz. Document Number: 002-00615 Rev. *F Page 72 of 80 S29PL-J 23. Physical Dimensions Figure 30. VBG080—80-Ball Fine-pitch Ball Grid Array 8 × 11 mm Package (PL127J) 002-25352 Rev. ** Document Number: 002-00615 Rev. *F Page 73 of 80 S29PL-J Figure 31. VBH064—64-Ball Fine-pitch Ball Grid Array 8 × 11.6 mm package (PL127J) 002-28179 Rev. ** Document Number: 002-00615 Rev. *F Page 74 of 80 S29PL-J Figure 32. VBK048—48-Ball Fine-pitch Ball Grid Array 8.15 × 6.15 mm package (PL032J and PL064J) 002-19063 Rev. ** Document Number: 002-00615 Rev. *F Page 75 of 80 S29PL-J Figure 33. VBU056—56-Ball Fine-pitch BGA 7 × 9mm package (PL064J and PL032J) NOTES: DIMENSIONS SYMBOL A A1 MIN. NOM. - - 1.00 0.17 - - D 9.00 BSC. E 7.00 BSC. D1 5.60 BSC. E1 5.60 BSC. MD 8 ME 8 n 56 Øb 0.33 - eD/eE 0.80 BSC. SD/SE 0.40 BSC. 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 . 2. ALL DIMENSIONS ARE IN MILLIMETERS . 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010/020. 4. e 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. MAX. REPRESENTS THE SOLDER BALL GRID PITCH . SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. n IS THE TOTAL NUMBER OF POPULATED SOLDER BALLS FOR MATRIX SIZE MD AND ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. 0.45 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 and "SE" = eE/2. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 002-15551 Rev. ** Document Number: 002-00615 Rev. *F Page 76 of 80 S29PL-J Figure 34. TS056—20 × 14 mm, 56-pin TSOP (PL127J) SYMBOL DIMENSIONS MIN. NOM. MAX. 2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). 3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK. 1.00 1.05 4. TO BE DETERMINED AT THE SEATING PLANE 0.20 0.23 A2 0.95 b1 0.17 b 0.17 0.22 c1 0.10 0.16 c 0.10 0.21 20.00 BASIC D1 18.40 BASIC E 14.00 BASIC 5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE. 6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm . 7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. 8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE SEATING PLANE. 0.50 BASIC 0.50 0 0° R 0.08 0.60 0.70 8 0.20 56 -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 0.27 D L DIMENSIONS ARE IN MILLIMETERS (mm). 0.15 0.05 N 1. 1.20 A A1 e NOTES: 9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 10. JEDEC SPECIFICATION NO. REF: MO-142(D)EC. 002-15549 Rev. *B Document Number: 002-00615 Rev. *F Page 77 of 80 S29PL-J 22. Document History Page Document Title: S29PL-J, 128-/64-/32-Mbit (8/4/2M × 16-Bit), 3 V, Flash with Enhanced VersatileIO™ Document Number: 002-00615 Rev. ** ECN No.  Orig. of Change Submission Date RYSU 01/29/2004 to 04/18/2013 Description of Change Initial release Included backward compatibility with MBM29xx families. 48-ball BGA package is not supported and was removed. Model numbers for the 48-ball BGA configurations were removed. An illustration was added to show the pin-out configuration. Added the description of 01h for address 4Fh and removed the 0004 data. Provided the time units of measure for the erase and programming performances. Corrected typo in device ID. Added 3V VIO for PL064J and PL032J devices. Corrected the voltage rating, ball configuration, and physical dimensions for model numbers 12 and 13. Removed the 64-ball, 8x9 mm diagram. Clarified the supply voltages that apply to the PL127J/PL129J and all other PLxxxJ products. Added information applicable to the CIN3 symbol. Removed the 9x8 mm package drawing. Added the 56-ball 7x9 mm pinout diagram. Updated to include the 8 x 6 mm, 48-ball Fine pitch BGA and 7 x 9 mm, 56-ball Fine-pitch BGA options. Added the VBK048 package drawing. Changed names. Updated specs in this table. Updated the Model Number offerings. Corrected the Package Markings for the 64-ball FBGA packages. Added combinations for the TLC056 package on the PL064J and PL032J devices. Valid Combinations for BGA Packages (128Mb) Package Options Added the 7 x 9mm 56-ball package. 56-ball connection diagram Notes 1 and 2 corrected to reflect accurate temperature ranges and cycling. Updated the Model Number offerings Updated the Package Types information. Figure 6, In-System Sector Protection/Sector Unprotection Algorithms Program Suspend/Program Resume Commands New section added. Made global changes to include program suspend/resume commands. Added Erase Suspend Latency. Updated table and added a notes section. Added the VBU056 package Added note: When Polling the SecSi indicator bit the A21 to A12 should be set within the address range 004000h-03FFFFh. Added sentence: Once the Enter Secured Silicon Sector Command sequence has been entered, the standard array cannot be accessed until the Exit Secured Silicon Sector command has been entered or the device has been reset. Added note 16: Once the Secured Silicon Sector Entry Command sequence has been entered, the standard array cannot be accessed until the Exit Secured Silicon Sector command has been entered or the device has been reset. Content the same, tables consolidated to match Ordering Information Descriptions Consolidated Special Package Handling Instructions and put the information before the package/pinout descriptions. Added Figure numbers to the connection diagram graphics. Updated operating temperatures. Updated VOH parameter. Added tESL parameter Updated the product that uses this package from PL127J to PL064J and PL032J 64-Ball Fine-Pitch BGA—MCP Compatible—PL127JChanged ball F9 to A22 Pin DescriptionCorrected WP#/ACC description. GlobalChanged data sheet status from Advanced Information to Full Production Ordering InformationModified/Added note to the Valid Combinations to be Supported for this Device tables VCC Ramp RateRemoved Section Connection DiagramCorrected 64-Ball Fine-Pitch BGA ball description (H9 and L5) Ordering InformationUnder Package Type, changed wording of “Lead (Pb)-free compliant” material type to “Standard”. GlobalRemoved 55 ns as a valid speed supported by PL127J. Product Selector GuideCorrected the 55 ns Speed Option's Max Page Access and Max OE# Access time from 2 to 20 ns. Corrected the 65 ns Speed Option's Max Access and Max CE# Access time from 25 to 65 ns. Dynamic Protection Bit (DYB)Corrected reference to Table 17 to Table 10.15. Erase Suspend/Erase Resume CommandsCorrected “This command is valid only during the sector erase operation, including the 80 µs time-out period...” to “This command is valid only during the sector erase operation, including the 50 µs time-out period...”. Command Definitions TablesIn Table 15.2, corrected the value of the third bus cycle of the “PPB Status”, “PPB Lock Bit Status” and “DYB Status” commands from 555 to BA+555. Document Number: 002-00615 Rev. *F Page 78 of 80 S29PL-J Document Title: S29PL-J, 128-/64-/32-Mbit (8/4/2M × 16-Bit), 3 V, Flash with Enhanced VersatileIO™ Document Number: 002-00615 Rev. ECN No. Orig. of Change Submission Date Description of Change Absolute Maximum RatingsCorrected the A9, OE# and RESET# “Voltage with Respect to Ground” maximum range value from +13.0V to +12.5V. DQ6: Toggle Bit ICorrected Figure 16.2: Toggle Bit Algorithm. Pin CapacitanceAdded TSOP package pin capacitance values. Ordering InformationFor model number 13, corrected “56-ball” TSOP package description to “56-pin”. GlobalChanged 65 ns and 70 ns initial access time for VIO=1.8V to 80 ns. ** (cont'd) - RYSU 01/29/2004 to 04/18/2013 *A 4959015 RYSU 10/13/2015 Updated to Cypress template. 08/10/2016 Updated Section 3. Ordering Information on page 6: Added 1.8V VIO TSOP package. Updated Valid Combinations - Standard: Added 14 in “Additional Ordering Options” column in “128 Mb Products Based on 110 nm Floating Gate Technology”. Updated to new template. *B 5398456 NFB *C 5644215 SZZX 02/27/2017 Updated Section 3. Ordering Information on page 6: Removed “BA” and “TA” details under “Package Type”. Updated Valid Combinations - Standard: Removed “BA” and “TA” related information. Updated to new template. Completing Sunset Review. *D 5755150 NIBK 05/31/2017 Updated Cypress Logo and Copyright. *E 6381371 PRIT 12/05/2018 Updated Section 3. Ordering Information on page 6. Updated Max Sector Erase Time. Updated Section 23. Physical Dimensions on page 73. *F 6654238 BWHA 08/20/2019 Document Number: 002-00615 Rev. *F Removed S29PL129J MCP Device. Added Automotive Device: A = Automotive, AEC-Q100 Grade 3 (-40°C to +85°C). Updated Cypress template. Page 79 of 80 S29PL-J Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-00615 Rev. *F Revised August 20, 2019 Page 80 of 80