S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V,
Simultaneous Read/Write Flash
Features
Single 1.8 V read/program/erase (1.70–1.95 V)
90 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero latency
Random page read access mode of 8 words with 20 ns intra
page access time
32 Word / 64 Byte Write Buffer
Sixteen-bank architecture consisting of
32/16/8 Mwords for 512/256/128P, respectively
Four 16 Kword sectors at both top and bottom of memory
array
510/254/126 64Kword sectors (WS512/256/128P)
Programmable linear (8/16/32) with or without wrap around
and continuous burst read modes
Secured Silicon Sector region consisting of 128 words each
for factory and 128 words for customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
Command set compatible with JEDEC (42.4) standard
Hardware (WP#) protection of top and bottom sectors
Dual boot sector configuration (top and bottom)
Handshaking by monitoring RDY
Offered Packages
– WS512P/WS256P/WS128P: 84-ball FBGA
(11.6 mm x 8 mm)
Low VCC write inhibit
Persistent and Password methods of Advanced Sector
Protection
Write operation status bits indicate program and erase
operation completion
Suspend and Resume commands for Program and Erase
operations
Unlock Bypass program command to reduce programming
time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
General Description
The Cypress S29WS512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These burst mode Flash
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate
data and address pins. These products can operate up to 104 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal
for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch Access Time (tIACC)
Max. Synch. Burst Access, ns (tBACC)
Max OE# Access Time, ns (tOE)
Max. Asynch. Access Time, ns (tACC)
104
103.8
7.6
7.6
80
Current Consumption (typical values)
Continuous Burst Read @ 104 MHz
Simultaneous Operation 104 MHz
Program
Standby Mode
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (VCC) Per
Word
Effective Write Buffer Programming (VACC) Per
Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
Cypress Semiconductor Corporation
Document Number: 002-01747 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
36 mA
40 mA
20 mA
20 µA
40 µs
9.4 µs
6 µs
350 ms
600 ms
•
408-943-2600
Revised June 29, 2017
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Contents
1.
1.1
Ordering Information ................................................... 3
Valid Combinations ........................................................ 3
2.
Input/Output Descriptions & Logic Symbol .............. 4
3.
Block Diagrams............................................................ 5
4.
4.1
4.2
4.3
Physical Dimensions/Connection Diagrams.............
Related Documents .......................................................
Special Handling Instructions for FBGA Package..........
MCP Look-ahead Connection Diagram .........................
5.
Additional Resources .................................................. 8
6.
6.1
Product Overview ........................................................ 9
Memory Map .................................................................. 9
7.
7.1
7.2
7.3
7.4
7.5
13
13
14
14
15
6
6
6
7
Device Operations .....................................................
Device Operation Table ...............................................
Asynchronous Read.....................................................
Page Mode Read .........................................................
Synchronous (Burst) Read Operation..........................
Synchronous (Burst) Read Mode & Configuration
Register........................................................................
7.6 Autoselect ....................................................................
7.7 Program/Erase Operations ..........................................
7.8 Simultaneous Read/Program or Erase ........................
7.9 Writing Commands/Command Sequences..................
7.10 Handshaking ................................................................
7.11 Hardware Reset ...........................................................
7.12 Software Reset ............................................................
26
30
32
48
48
49
49
49
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Advanced Sector Protection/Unprotection .............
Advanced Sector Protection Software Examples ........
Lock Register ...............................................................
Persistent Protection Bits.............................................
Dynamic Protection Bits...............................................
Persistent Protection Bit Lock Bit.................................
Password Protection Method .......................................
Hardware Data Protection Methods.............................
51
51
52
53
54
54
54
56
9.
9.1
9.2
9.3
9.4
Power Conservation Modes......................................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
Hardware RESET# Input Operation.............................
Output Disable (OE#)...................................................
58
58
58
58
58
10.
10.1
10.2
10.3
Secured Silicon Sector Flash Memory Region .......
Factory Secured Silicon Sector....................................
Customer Secured Silicon Sector ................................
Secured Silicon Sector Entry/Exit Command
Sequences ...................................................................
59
59
60
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Operating Ranges........................................................
DC Characteristics .......................................................
Test Conditions ............................................................
Key to Switching Waveforms .......................................
Switching Waveforms ..................................................
62
62
62
63
64
65
65
11.
11.1
11.2
11.3
11.4
11.5
11.6
Document Number: 002-01747 Rev. *B
11.7 Power-up/Initialization................................................... 65
11.8 CLK Characterization.................................................... 66
11.9 AC Characteristics ........................................................ 67
11.10Erase and Programming Performance ......................... 80
12. Appendix ..................................................................... 81
12.1 Common Flash Memory Interface................................. 85
13.
Revision History.......................................................... 90
60
Page 2 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
1.
Ordering Information
The ordering part number is formed by a valid combination of the following:
S29W
S
512
P
xx
BA
W
00
0
Packing Type
0 = Tray (standard; see note 1)
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
Model Number
(Chip Enable Options)
00 = Default
Temperature Range
W = Wireless (–25C to +85C)
Package Type And Material
BA= Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package
BF= Very Thin Fine-Pitch BGA, Lead (Pb)-free Package
Speed Option (Burst Frequency)
0L = 54 MHz
0P = 66 MHz
0S = 80 MHz
AB= 104 MHz
Process Technology
P = 90 nm MirrorBit®Technology
Flash Density
512=512 Mb
256=256 Mb
128=128 Mb
Device Family
S29WS =1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
S29WS512P Valid Combinations (Notes 1, 2)
Base Ordering
Part Number
Product
Status
Speed
Option
Package Type, Material,
& Temperature Range
Packing
Type
Model
Numbers
S29WS512P
S29WS256P
Advance
0L, 0P,
0S, AB
S29WS128P
BAW (Lead (Pb)-free
Compliant),
BFW (Lead (Pb)-free)
0, 2, 3
(Note 1)
00
Package Type
(Note 2)
11.6 mm x 8 mm
84-ball
MCP-Compatible
11.6 mm x 8 mm
84-ball
MCP-Compatible
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S29 and packing type designator from ordering part number.
Document Number: 002-01747 Rev. *B
Page 3 of 91
SUPPLEMENT
2.
S29WS512P
S29WS256P
S29WS128P
Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Input/Output Descriptions
Symbol
AMAX–A0
Type
Input
Description
Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for
WS256P, and 22 for WS128P)
DQ15–DQ0
I/O
CE#
Input
Data input/output.
Chip Enable. Asynchronous relative to CLK.
OE#
Input
Output Enable. Asynchronous relative to CLK.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply
VCCQ
Supply
Device Input/Output Power Supply (Must be ramped simultaneously with VCC)
VSS
Supply
Ground.
NC
No Connect
RDY
Output
Not connected internally.
Ready. Indicates when valid burst data is ready to be read.
Input
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at VIL or VIH while in asynchronous mode.
AVD#
Input
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode,
causes starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#
Input
Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should
be at VIH for all other conditions.
ACC
Input
Acceleration Input. At VHH, accelerates programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other
conditions.
RFU
Reserved
CLK
Reserved for future use (see MCP look-ahead pinout for use with MCP).
Document Number: 002-01747 Rev. *B
Page 4 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
3. Block Diagrams
Bank Address
Bank 0
Latches and
Control Logic
VSS
VCCQ
Y-Decoder
VCC
DQ15–DQ0
AMAX–A0
X-Decoder
OE#
WP#
ACC
RESET#
WE#
CEx#
AVD#
RDY
Bank 1
Latches and
Control Logic
Y-Decoder
Bank Address
DQ15–DQ0
X-Decoder
AMAX–A0
STATE
CONTROL
&
COMMAND
REGISTER
DQ15–DQ0
Status
Control
AMAX–A0
DQ15–DQ0
Bank (n-1)
Latches and
Control Logic
Bank Address
AMAX–A0
Y-Decoder
X-Decoder
DQ15–DQ0
Bank (n)
Latches and
Control Logic
Bank Address
Y-Decoder
X-Decoder
DQ15–DQ0
Notes:
1. AMAX-A0 = A24-A0 for the WS512P, A23-A0 for the WS256P, and A22-A0 for the WS128P.
2. n = 15 for WS512P / WS256P / WS128P.
Document Number: 002-01747 Rev. *B
Page 5 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
4. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S29WS-P.
4.1
Related Documents
The following documents contain information relating to the S29WS-P devices. Click on the title or go to www.cypress.com to
download the PDF file, or request a copy from your sales office.
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Figure 4.1 84-Ball Fine-Pitch Ball Grid Array, 512, 256 & 128 Mb
(Top View, Balls Facing Down, MCP Compatible)
A10
A1
NC
NC
B2
B3
B4
B5
B6
B7
B8
B9
AVD#
VSS
CLK
RFU
VCC
RFU
RFU
RFU
C2
C3
C4
C5
C6
C7
C8
C9
WP#
A7
RFU
ACC
WE#
A8
A11
RFU
D2
D3
D4
D5
D6
D7
D8
D9
A3
A6
RFU
RESET#
RFU
A19
A12
A15
E2
E3
E4
A5
A18
E5
E6
E7
E8
E9
RDY
A20
A9
A13
A21
Legend
Reserved for
Future Use
Do Not Use
Ground
A2
F2
F3
A1
A4
F4
A17
F5
RFU
F6
F7
F8
F9
A23
A10
A14
A22
G2
G3
G4
G5
G6
G7
G8
G9
A0
VSS
DQ1
RFU
RFU
DQ6
A24
A16
H2
H3
H4
H5
H6
H7
H8
H2
F-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J2
J3
J4
J5
J6
J7
J8
J9
RFU
DQ0
DQ10
VCC
RFU
DQ12
DQ7
VSS
K2
K3
K4
K5
K6
K7
K8
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L2
L3
L4
L5
L6
L7
L8
L9
RFU
RFU
VSS
VCC
RFU
RFU
VCCQ
RFU
Power
M1
M10
NC
NC
Notes:
1. Balls F6 and G8 are RFU on the WS128P.
2. Ball G8 is RFU on the WS256P.
3. VCC pins must ramp simultaneously.
Document Number: 002-01747 Rev. *B
Page 6 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Figure 4.2 VBH084—84-ball Fine-Pitch Ball Grid Array, 11.6 x 8 mm MCP Compatible Package
0.05 C
(2X)
D
D1
A
e
10
9
e
7
8
SE
7
6
E1
E
5
4
3
2
1
M
A1 CORNER
INDEX MARK
L
K
B
10
H
G
F
E
SD
6
0.05 C
(2X)
J
D
C
B
A
A1 CORNER
7
NXφb
φ 0.08 M C
TOP VIEW
φ 0.15 M C A B
BOTTOM VIEW
0.10 C
A2
A
A1
C
0.08 C
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
VBH 084
JEDEC
N/A
11.60 mm x 8.00 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
NOTE
OVERALL THICKNESS
BODY SIZE
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
BALL FOOTPRINT
E1
7.20 BSC.
BALL FOOTPRINT
MD
12
ROW MATRIX SIZE D DIRECTION
ME
10
ROW MATRIX SIZE E DIRECTION
84
0.33
---
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4.
5.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
TOTAL BALL COUNT
0.43
BALL DIAMETER
e
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
(A2-A9, B10-L10,
M2-M9, B1-L1)
DEPOPULATED SOLDER BALLS
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
11.60 BSC.
E
N
DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2.
BALL HEIGHT
D
φb
1.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8.
NOT USED.
9.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note:
BSC is an ANSI standard for Basic Space Centering.
4.3
MCP Look-ahead Connection Diagram
Cypress Inc. provides this standard look-ahead connection diagram that supports
NOR Flash and SRAM densities up to 4 Gigabits
NOR Flash and pSRAM densities up to 4 Gigabits
NOR Flash and pSRAM and data storage densities up to 4 Gigabits
The physical package outline may vary between connection diagrams and densities. The connection diagram for any MCP,
however, is a subset of the pinout.
In some cases, outrigger balls may exist in locations outside the grid shown. These outrigger balls are reserved; do not connect
them to any other signal.
For further information about the MCP look-ahead pinout, refer to the Design-In Scalable Wireless Solutions with Cypress Products
application note (publication number: Design_Scalable_Wireless_AN), available on the web or through a Cypress sales office.
Document Number: 002-01747 Rev. *B
Page 7 of 91
SUPPLEMENT
5.
S29WS512P
S29WS256P
S29WS128P
Additional Resources
Visit www.cypress.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Cypress Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Cypress low-level drivers
True Flash File System
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD® Schematic Symbols
Technical Support
Contact your local sales office or contact Cypress Inc. directly for additional technical support:
http://www.cypress.com/flash_memory_products/support/ses/index.html
Document Number: 002-01747 Rev. *B
Page 8 of 91
SUPPLEMENT
6.
S29WS512P
S29WS256P
S29WS128P
Product Overview
The S29WS-P family consists of 512, 256, and 128 Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized
for today’s wireless designs that demand a large storage array, rich functionality, and low power consumption.
These devices are organized in 32, 16, or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or
linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a
32-word buffer for programming with program/erase and suspend functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time
Programmable.
6.1
Memory Map
The S29WS512/256/128P Mbit devices consist of 16 banks organized as shown in Tables –.
S29WS512P Sector & Memory Address Map
Bank
Size
Sector
Count
4
4 MB
Sector
Size (KB)
Bank
Address Range
32
SA000
000000h–003FFFh
32
SA001
004000h–007FFFh
32
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
SA004
010000h–01FFFFh
0
32
…
…
…
128
31
Sector/
Sector Range
128
SA034
1F0000h–1FFFFFh
200000h–3FFFFFh
128
1
SA035–SA066
4 MB
32
128
2
SA067–SA098
4 MB
32
128
3
SA099–SA130
4 MB
32
128
4
SA131–SA162
4 MB
32
128
5
SA163–SA194
4 MB
32
128
6
SA195–SA226
… … … …
32
4 MB
32
128
7
SA227–SA258
E00000h–FFFFFFh
4 MB
32
128
8
SA259–SA290
1000000-11FFFFF
4 MB
32
128
9
SA291–SA322
4 MB
32
128
10
SA323–SA354
4 MB
32
128
11
SA355–SA386
4 MB
32
128
12
SA387–SA418
4 MB
32
128
13
SA419–SA450
… … … … …
4 MB
4 MB
32
128
14
SA451–SA482
1C00000h-1DFFFFFh
Document Number: 002-01747 Rev. *B
Notes
Sector Starting Address –
Sector Ending Address
Sector Starting Address –
Sector Ending Address
(see note)
First Sector, Starting Address –
Last Sector, Ending Address
(see note)
Page 9 of 91
SUPPLEMENT
S29WS512P
S29WS256P
S29WS128P
S29WS512P Sector & Memory Address Map
Sector
Count
31
Sector
Size (KB)
Bank
128
4 MB
15
4
Sector/
Sector Range
Address Range
SA483
1E00000h-1E0FFFFh
…
Bank
Size
32
SA513
1FE0000h-1FEFFFFh
SA514
1FF0000h-1FF3FFFh
SA515
1FF4000h-1FF7FFFh
SA516
1FF8000h-1FFBFFFh
SA517
1FFC000h-1FFFFFFh
Notes
Sector Starting Address –
Sector Ending Address
(see note)
Sector Starting Address –
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA005–SA033) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
pattern xx00000h–xxFFFFh.
Document Number: 002-01747 Rev. *B
Page 10 of 91
SUPPLEMENT
S29WS512P
S29WS256P
S29WS128P
S29WS256P Sector & Memory Address Map
Bank
Size
Sector
Count
Sector
Size (KB)
4
32
15
128
2 MB
16
128
2 MB
16
2 MB
2 MB
2 MB
Bank
0
Sector/
Sector Range
Address Range
SA000
000000h–003FFFh
SA001
004000h–007FFFh
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
SA004 to SA018
010000h–01FFFFh to 0F0000h–0FFFFFh
1
SA019 to SA034
100000h–10FFFFh to 1F0000h–1FFFFFh
128
2
SA035 to SA050
200000h–20FFFFh to 2F0000h–2FFFFFh
16
128
3
SA051 to SA066
300000h–30FFFFh to 3F0000h–3FFFFFh
16
128
4
SA067 to SA082
400000h–40FFFFh to 4F0000h–4FFFFFh
2 MB
16
128
5
SA083 to SA098
500000h–50FFFFh to 5F0000h–5FFFFFh
2 MB
16
128
6
SA099 to SA114
600000h–60FFFFh to 6F0000h–6FFFFFh
2 MB
16
128
7
SA115 to SA130
700000h–70FFFFh to 7F0000h–7FFFFFh
2 MB
16
128
8
SA131 to SA146
800000h–80FFFFh to 8F0000h–8FFFFFh
2 MB
16
128
9
SA147 to SA162
900000h–90FFFFh to 9F0000h–9FFFFFh
2 MB
16
128
10
SA163 to SA178
A00000h–A0FFFFh to AF0000h–AFFFFFh
2 MB
16
128
11
SA179 to SA194
B00000h–B0FFFFh to BF0000h–BFFFFFh
2 MB
16
128
12
SA195 to SA210
C00000h–C0FFFFh to CF0000h–CFFFFFh
2 MB
16
128
13
SA211 to SA226
D00000h–D0FFFFh to DF0000h–DFFFFFh
2 MB
16
128
14
SA227 to SA242
E00000h–E0FFFFh to EF0000h–EFFFFFh
15
128
SA243 to SA257
F00000h–F0FFFFh to FE0000h–FEFFFFh
SA258
FF0000h–FF3FFFh
SA259
FF4000h–FF7FFFh
SA260
FF8000h–FFBFFFh
SA261
FFC000h–FFFFFFh
2 MB
4
32
15
Notes
Contains four smaller
sectors at bottom of
addressable memory.
All 128 KB sectors.
Pattern for sector
address range is
xx0000h–xxFFFFh.
(see note)
Contains four smaller
sectors at top of
addressable memory.
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA005–SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
pattern xx00000h–xxFFFFh.
Document Number: 002-01747 Rev. *B
Page 11 of 91
SUPPLEMENT
S29WS512P
S29WS256P
S29WS128P
S29WS128P Sector & Memory Address Map
Bank
Size
Sector
Count
Sector/
Sector Range
Address Range
32
SA000
000000h–003FFFh
32
SA001
004000h–007FFFh
SA002
008000h–00BFFFh
32
SA003
00C000h–00FFFFh
7
128
SA004 to
SA010
010000h–01FFFFh to 070000h–07FFFFh
1 MB
8
128
1
1 MB
8
128
2
SA019 to
SA026
100000h–10FFFFh to 170000h–17FFFFh
1 MB
8
128
3
SA027 to
SA034
180000h–18FFFFh to 1F0000h–1FFFFFh
1 MB
8
128
4
SA035 to
SA042
200000h–20FFFFh to 270000h–27FFFFh
1 MB
8
128
5
SA043 to
SA050
280000h–28FFFFh to 2F0000h–2FFFFFh
1 MB
8
128
6
SA051 to
SA058
300000h–30FFFFh to 370000h–37FFFFh
1 MB
8
128
7
SA059 to
SA066
380000h–38FFFFh to 3F0000h–3FFFFFh
1 MB
8
128
8
SA067 to
SA074
400000h–40FFFFh to 470000h–47FFFFh
1 MB
8
128
9
SA075 to
SA082
480000h–48FFFFh to 4F0000h–4FFFFFh
1 MB
8
128
10
SA083 to
SA090
500000h–50FFFFh to 570000h–57FFFFh
1 MB
8
128
11
SA091 to
SA098
580000h–58FFFFh to 5F0000h–5FFFFFh
1 MB
8
128
12
SA099 to
SA106
600000h–60FFFFh to 670000h–67FFFFh
1 MB
8
128
13
SA107 to SA114 680000h–68FFFFh to 6F0000h–6FFFFFh
1 MB
8
128
14
SA115 to SA122 700000h–70FFFFh to 770000h–77FFFFh
7
128
4
1 MB
Sector
Size (KB)
32
Bank
0
780000h–78FFFFh to 7E0000h–7EFFFFh
SA130
7F0000h–7F3FFFh
4
SA131
7F4000h–7F7FFFh
32
SA132
7F8000h–7FBFFFh
32
SA133
7FC000h–7FFFFFh
32
15
Contains four smaller
sectors at bottom of
addressable memory.
SA011 to SA018 080000h–08FFFFh to 0F0000h–0FFFFFh
SA123 to
SA129
32
1 MB
Notes
All 128 KB sectors.
Pattern for sector address
range is xx0000h–
xxFFFFh.
(see note)
Contains four smaller
sectors at top of
addressable memory.
Note:
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA005–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
pattern xx00000h–xxFFFFh.
Document Number: 002-01747 Rev. *B
Page 12 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
7. Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash
devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command
registers (see Table on page 81 and Table on page 83). The command register itself does not occupy any addressable memory
location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute
the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the
function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an
unknown state, in which case the system must write the reset command to return the device to the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation. Table describes the required state of each control pin for any particular
operation.
Device Operations
Operation
CE#
OE#
WE#
CLK
Amax–A0
DQ15–0
RDY
RESET#
Addr In
Output
Valid
H
H
L
Addr In
Output
Valid
H
H
L
Addr In
Input
Valid
H
H
Addr In
I/O
H
H
X
X
HIGH Z
HIGH Z
H
X
X
HIGH Z
HIGH Z
H
L
Addr In
Output
Invalid
X
H
L
H
H
X
Output
Valid
H
H
H
X
H
X
X
X
HIGH Z
HIGH Z
H
Terminate current Burst read cycle
via RESET#
X
X
H
X
X
X
HIGH Z
HIGH Z
L
Terminate current Burst read cycle
and start new Burst read cycle
L
X
H
Addr In
Output
Invalid
X
H
Asynchronous Read
- Addresses Latched
L
L
H
X
Asynchronous Read
AVD# Steady State
L
L
H
X
Asynchronous Write
L
H
X
L
H
L
H
X
X
X
X
X
X
X
Latch Starting Burst Address by CLK
L
X
Advance Burst read to next address
L
Terminate current Burst read cycle
Synchronous Write
Standby (CE#)
Hardware Reset
AVD#
Burst Read Operations
Legend:
L = Logic 0, H = Logic 1, X = can be either VIL or VIH.,
= rising edge,
= high to low,
= toggle.
Note:
Address is latched on the rising edge of clock.
Document Number: 002-01747 Rev. *B
Page 13 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
7.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at
a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its
outputs to arrive asynchronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware reset. To read data from the memory
array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The
rising edge of AVD# latches the address, preventing changes to the address lines from effecting the address being accessed.. Data
is output on DQ15-DQ0 pins after the access time (tACC) has elapsed from the falling edge of AVD#, or the last time the address
lines changed while AVD# was low.
7.3
Page Mode Read
The device is capable of fast page mode read. This mode provides fast (tPACC) random read access speed for locations within a
page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an
asynchronous operation with the microprocessor supplying the specific word location. It does not matter if AVD# stays low or
toggles. However, the address input must be always valid and stable if AVD# is low during the page read.
The random or initial page access is tACC or tCE (depending on how the device was accessed) and subsequent page read accesses
(as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted
(=VIH), the reassertion of CE# for subsequent access has access time of tCE. Here again, CE# selects the device and OE# is the
output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained
by keeping Amax–A3 constant and changing A2–A0 to select the specific word within that page.
Page Select
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Document Number: 002-01747 Rev. *B
Page 14 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
7.4
Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first
powers up, it is enabled for asynchronous read operations and can be automatically enabled for burst mode. To enter into
synchronous mode, the configuration register will need to be set.
Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst
access, what mode of burst operation is desired and how the RDY signal will transition with valid data. The system would then write
the configuration register command sequence.
Once the system has written the Set Configuration Register command sequence, the device is enabled for synchronous reads only.
The data is output tIACC after the rising edge of the first CLK. Subsequent words are output tBACC after the rising edge of each
successive clock cycle, which automatically increments the internal address counter. Note that data is output only at the rising edge
of the clock. RDY indicates the initial latency.
7.4.1
Latency Tables for Variable Wait State
The following tables show the latency for variable wait state in a continuous Burst operation
Address Latency for 11 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
1
D1
D2
D3
D4
D5
D6
D7
1
ws
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
2
D2
D3
D4
D5
D6
D7
1
ws
1
ws
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
3
D3
D4
D5
D6
D7
1
ws
1
ws
1
ws
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
4
D4
D5
D6
D7
1
ws
1
ws
1
ws
1
ws
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
5
D5
D6
D7
1
ws
1
ws
1
ws
1
ws
1
ws
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
6
D6
D7
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
7
D7
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D8
D9
D10
…
D12 D12 D12 D12
4
5
6
7
2
ws
D0
11 ws
Document Number: 002-01747 Rev. *B
Page 15 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Address Latency for 10 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
1
D1
D2
D3
D4
D5
D6
D7
1
ws
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
2
D2
D3
D4
D5
D6
D7
1
ws
1
ws
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
3
D3
D4
D5
D6
D7
1
ws
1
ws
1
ws
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
4
D4
D5
D6
D7
1
ws
1
ws
1
ws
1
ws
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
5
D5
D6
D7
1
ws
1
ws
1
ws
1
ws
1
ws
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
6
D6
D7
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
7
D7
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D8
D9
D10 …
D12 D12 D12 D12
4
5
6
7
1
ws
D0
10 ws
Address Latency for 09 Wait States
Word Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
1
D1
D2
D3
D4
D5
D6
D7
1 ws
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
2
D2
D3
D4
D5
D6
D7
1 ws 1 ws
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
3
D3
D4
D5
D6
D7
1 ws 1 ws 1 ws
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
4
D4
D5
D6
D7
1 ws 1 ws 1 ws 1 ws
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
5
D5
D6
D7
1 ws 1 ws 1 ws 1 ws 1 ws
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
6
D6
D7
1 ws 1 ws 1 ws 1 ws 1 ws 1 ws
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
7
D7
1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws
D8
D9
D10
…
D12
4
D12
5
D12
6
D12
7
D0
9 ws
Document Number: 002-01747 Rev. *B
Page 16 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Address Latency for 8 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
1
D1
D2
D3
D4
D5
2
D2
D3
D4
D5
D6
D3
D4
D5
D6
D4
D5
D6
D7
5
D5
D6
D7
1 ws
1 ws
6
D6
D7
1 ws
1 ws
1 ws
7
D7
1 ws
1 ws
1 ws
1 ws
3
4
8 ws
D6
D7
D8
D6
D7
D8
D9
D7
1 ws
D8
D9
D7
1 ws
1 ws
D8
D9
1 ws
1 ws
1 ws
D8
D9
1 ws
1 ws
D8
D9
1 ws
1 ws
D8
D9
1 ws
1 ws
D8
D9
Address Latency for 7 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
3
D3
D4
D5
D6
D7
1 ws
D8
D9
D10
D4
D5
D6
D7
1 ws
1 ws
D8
D9
D10
D5
D6
D7
1 ws
1 ws
1 ws
D8
D9
D10
4
7 ws
5
6
D6
D7
1 ws
1 ws
1 ws
1 ws
D8
D9
D10
7
D7
1 ws
1 ws
1 ws
1 ws
1 ws
D8
D9
D10
Address Latency for 6 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
D3
D4
D5
D6
D7
D8
D9
D10
D11
D4
D5
D6
D7
1 ws
D8
D9
D10
D11
5
D5
D6
D7
1 ws
1 ws
D8
D9
D10
D11
6
D6
D7
1 ws
1 ws
1 ws
D8
D9
D10
D11
7
D7
1 ws
1 ws
1 ws
1 ws
D8
D9
D10
D11
3
4
6 ws
Document Number: 002-01747 Rev. *B
Page 17 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Address Latency for 5 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
D3
D4
D5
D6
D7
D8
D9
D10
D11
D4
D5
D6
D7
D8
D9
D10
D11
D12
5
D5
D6
D7
1 ws
D8
D9
D10
D11
D12
6
D6
D7
1 ws
1 ws
D8
D9
D10
D11
D12
7
D7
1 ws
1 ws
1 ws
D8
D9
D10
D11
D12
3
4
5 ws
D8
Address Latency for 4 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
3
D3
D4
D5
D6
D7
D8
D9
D10
D11
D4
D5
D6
D7
D8
D9
D10
D11
D12
5
D5
D6
D7
D8
D9
D10
D11
D12
D13
6
D6
D7
1 ws
D8
D9
D10
D11
D12
D13
7
D7
1 ws
1 ws
D8
D9
D10
D11
D12
D13
4
4 ws
Address Latency for 3 Wait States
Word
Initial Wait
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
D3
D4
D5
D6
D7
D8
D9
D10
D11
D4
D5
D6
D7
D8
D9
D10
D11
D12
5
D5
D6
D7
D8
D9
D10
D11
D12
D13
6
D6
D7
D8
D9
D10
D11
D12
D13
D14
7
D7
1 ws
D8
D9
D10
D11
D12
D13
D14
3
4
3 ws
Document Number: 002-01747 Rev. *B
Page 18 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
7.4.2
Latency for Boundary Crossing during First Read
The following tables show the latency at End of Word Line for boundary corssing during First Read in continuous burst operation
Address Latency for 11 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
2 ws
1
D121
D122
D123
D124
D125
D126
D127
1 ws
2 ws
D0
2
D122
D123
D124
D125
D126
D127
1 ws
1 ws
2 ws
D0
D123
D124
D125
D126
D127
1 ws
1 ws
1 ws
2 ws
D0
D124
D125
D126
D127
1 ws
1 ws
1 ws
1 ws
2 ws
D0
3
4
11 ws
D0
5
D125
D126
D127
1 ws
1 ws
1 ws
1 ws
1 ws
2 ws
D0
6
D126
D127
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
2 ws
D0
7
D127
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
2 ws
D0
Address Latency for 10 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
1 ws
D0
1
D121
D122
D123
D124
D125
D126
D127
1 ws
1 ws
D0
2
D122
D123
D124
D125
D126
D127
1 ws
1 ws
1 ws
D0
3
D123
D124
D125
D126
D127
1 ws
1 ws
1 ws
1 ws
D0
D124
D125
D126
D127
1 ws
1 ws
1 ws
1 ws
1 ws
D0
5
D125
D126
D127
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D0
6
D126
D127
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D0
7
D127
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D0
4
10 ws
Address Latency for 9 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
D0
1
D121
D122
D123
D124
D125
D126
D127
1 ws
D0
2
D122
D123
D124
D125
D126
D127
1 ws
1 ws
D0
D123
D124
D125
D126
D127
1 ws
1 ws
1 ws
D0
D124
D125
D126
D127
1 ws
1 ws
1 ws
1 ws
D0
5
D125
D126
D127
1 ws
1 ws
1 ws
1 ws
1 ws
D0
6
D126
D127
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D0
7
D127
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D0
3
4
9 ws
Document Number: 002-01747 Rev. *B
Page 19 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Address Latency for 8 Wait States
Word
Initial Wait
0
D120
1
D121
D122
D123
D124
2
D122
D123
D124
D125
D123
D124
D125
D126
D124
D125
D126
D127
5
D125
D126
D127
6
D126
D127
1 ws
7
D127
1 ws
1 ws
3
4
8 ws
D121
D122
D123
D124
D125
D126
D127
D0
D125
D126
D127
D0
D1
D126
D127
1 ws
D0
D1
D127
1 ws
1 ws
D0
D1
1 ws
1 ws
1 ws
D0
D1
1 ws
1 ws
1 ws
1 ws
D0
D1
1 ws
1 ws
1 ws
1 ws
D0
D1
1 ws
1 ws
1 ws
1 ws
D0
D1
Address Latency for 7 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
D0
1
D121
D122
D123
D124
D125
D126
D127
D0
D1
2
D122
D123
D124
D125
D126
D127
D0
D1
D2
3
D123
D124
D125
D126
D127
1 ws
D0
D1
D2
D124
D125
D126
D127
1 ws
1 ws
D0
D1
D2
D125
D126
D127
1 ws
1 ws
1 ws
D0
D1
D2
6
D126
D127
1 ws
1 ws
1 ws
1 ws
D0
D1
D2
7
D127
1 ws
1 ws
1 ws
1 ws
1 ws
D0
D1
D2
4
7 ws
5
Address Latency for 6 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
D0
1
D121
D122
D123
D124
D125
D126
D127
D0
D1
2
D122
D123
D124
D125
D126
D127
D0
D1
D2
3
D123
D124
D125
D126
D127
D0
D1
D2
D3
D124
D125
D126
D127
1 ws
D0
D1
D2
D3
5
D125
D126
D127
1 ws
1 ws
D0
D1
D2
D3
6
D126
D127
1 ws
1 ws
1 ws
D0
D1
D2
D3
7
D127
1 ws
1 ws
1 ws
1 ws
D0
D1
D2
D3
4
6 ws
Document Number: 002-01747 Rev. *B
Page 20 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Address Latency for 5 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
D0
1
D121
D122
D123
D124
D125
D126
D127
D0
D1
2
D122
D123
D124
D125
D126
D127
D0
D1
D2
D123
D124
D125
D126
D127
D0
D1
D2
D3
D124
D125
D126
D127
D0
D1
D2
D3
D4
5
D125
D126
D127
1 ws
D0
D1
D2
D3
D4
6
D126
D127
1 ws
1 ws
D0
D1
D2
D3
D4
7
D127
1 ws
1 ws
1 ws
D0
D1
D2
D3
D4
3
4
5 ws
Address Latency for 4 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
D0
1
D121
D122
D123
D124
D125
D126
D127
D0
D1
2
D122
D123
D124
D125
D126
D127
D0
D1
D2
3
D123
D124
D125
D126
D127
D0
D1
D2
D3
D124
D125
D126
D127
D0
D1
D2
D3
D4
D125
D126
D127
D0
D1
D2
D3
D12
D5
6
D126
D127
1 ws
D0
D1
D2
D3
D12
D5
7
D127
1 ws
1 ws
D0
D1
D2
D3
D12
D5
4
4 ws
5
Address Latency for 3 Wait States
Word
Initial Wait
0
D120
D121
D122
D123
D124
D125
D126
D127
D0
1
D121
D122
D123
D124
D125
D126
D127
D0
D1
2
D122
D123
D124
D125
D126
D127
D0
D1
D2
D123
D124
D125
D126
D127
D0
D1
D2
D3
D124
D125
D126
D127
D0
D1
D2
D3
D4
5
D125
D126
D127
D0
D1
D2
D3
D4
D5
6
D126
D127
D0
D1
D2
D3
D4
D5
D6
7
D127
1 ws
D0
D1
D2
D3
D4
D5
D6
3
4
3 ws
Document Number: 002-01747 Rev. *B
Page 21 of 91
SUPPLEMENT
7.4.3
S29WS512P
S29WS256P
S29WS128P
Latency at End of Word Line for Boundary Crossing After Second Read in
Continuous Burst Operation
The following tables show the latency for boundary crossing after Second Read in a continuous Burst operation.
Address Latency for 11 Wait States
Word
Initial Wait
0
D11 D11 D11 D11 D11 D11 D11 D11 D12 D12 D12 D12 D12 D12 D12 D12
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
2
ws
D0
1
D11 D11 D11 D11 D11 D11 D11
3
4
5
6
7
8
9
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
2
ws
D0
2
D11 D11 D11 D11 D11 D11
4
5
6
7
8
9
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
4
5
6
7
0
1
2
3
2
ws
D0
3
D11 D11 D11 D11 D11
5
6
7
8
9
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
2
ws
D0
4
D11 D11 D11 D11
6
7
8
9
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
2
ws
D0
5
D11 D11 D11
7
8
9
1
ws
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
2
ws
D0
6
D11 D11
8
9
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
2
ws
D0
7
D11
9
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
2
ws
D0
11 ws
1
ws
Address Latency for 10 Wait States
Word
Initial
Wait
0
D11 D11 D11 D11 D11 D11 D11 D11 D12 D12 D12 D12 D12 D12 D12 D12
4
5
6
7
8
9
0
1
2
3
4
5
6
7
2
3
1
ws
D0
1
D11 D11 D11 D11 D11 D11 D11
3
4
5
6
7
8
9
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
1
ws
D0
2
D11 D11 D11 D11 D11 D11
4
5
6
7
8
9
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
1
ws
D0
3
D11 D11 D11 D11 D11
5
6
7
8
9
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
1
ws
D0
4
D11 D11 D11 D11
6
7
8
9
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
1
ws
D0
5
D11 D11 D11
7
8
9
1
ws
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
5
6
7
0
1
2
3
4
1
ws
D0
6
D11 D11
8
9
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
1
ws
D0
7
D11
9
1
ws
1
ws
1
ws
1
ws
1
ws
1
ws
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
1
ws
D0
10 ws
1
ws
Document Number: 002-01747 Rev. *B
Page 22 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Address Latency for 9 Wait States
Word Initial Wait
0
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
1
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12
1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
2
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12
1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
3
D11
5
D11
6
D11
7
D11
8
D11
D12
1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
4
D11
6
D11
7
D11
8
D11
D12
1 ws 1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
5
D11
7
D11
8
D11
D12
1 ws 1 ws 1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
6
D11
8
D11
D12
1 ws 1 ws 1 ws 1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
7
D11
D12
1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
9 ws
D11
9
Address Latency for 8 Wait States
Word
Initial Wait
0
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
1
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12
1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12
1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
4
D11
5
D11
6
D11
7
D11
8
D11
D12
1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
5
D11
6
D11
7
D11
8
D11
D12
1 ws 1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
6
D11
7
D11
8
D11
D12
1 ws 1 ws 1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
7
D11
8
D11
D12
1 ws 1 ws 1 ws 1 ws 1 ws 1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
8 ws
Document Number: 002-01747 Rev. *B
Page 23 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Address Latency for 7 Wait States
Word
Initial Wait
0
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
1
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
2
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
6
7
0
1
2
3
4
5
D0
3
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws
9
0
1
2
3
4
5
6
7
D0
4
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws 1 ws
9
0
1
2
3
4
5
6
7
D0
5
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws 1 ws 1 ws
9
0
1
2
3
4
5
6
7
D0
6
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws 1 ws 1 ws 1 ws
9
0
1
2
3
4
5
6
7
D0
7
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws 1 ws 1 ws 1 ws 1 ws
9
0
1
2
3
4
5
6
7
D0
7 ws
Address Latency for 6 Wait States
Word
Initial Wait
0
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12
0
1
D12
2
D12
3
D12 D12 D12 D12
4
5
6
7
D0
1
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12
0
1
D12
2
D12
3
D12 D12 D12 D12
4
5
6
7
D0
2
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12
0
1
D12
2
D12
3
D12 D12 D12 D12
4
5
6
7
D0
3
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12
0
1
D12
2
D12
3
D12 D12 D12 D12
4
5
6
7
D0
4
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D12 D12
D11
1 ws
0
1
9
D12
2
D12
3
D12 D12 D12 D12
4
5
6
7
D0
5
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12 D12
1 ws 1 ws
9
0
1
D12
2
D12
3
D12 D12 D12 D12
4
5
6
7
D0
6
D11
5
D11
6
D11
7
D11
8
D11
D12 D12
1 ws 1 ws 1 ws
9
0
1
D12
2
D12
3
D12 D12 D12 D12
4
5
6
7
D0
7
D11
6
D11
7
D11
8
D11
D12 D12
1 ws 1 ws 1 ws 1 ws
9
0
1
D12
2
D12
3
D12 D12 D12 D12
6
7
4
5
D0
6 ws
Document Number: 002-01747 Rev. *B
Page 24 of 91
SUPPLEMENT
S29WS512P
S29WS256P
S29WS128P
Address Latency for 5 Wait States
Word
Initial Wait
0
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
1
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
2
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
6
7
0
1
2
3
4
5
D0
3
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
4
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
5
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws
6
7
9
0
1
2
3
4
5
D0
6
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws 1 ws
9
0
1
2
3
4
5
6
7
D0
7
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws 1 ws 1 ws
9
0
1
2
3
4
5
6
7
D0
5 ws
Address Latency for 4 Wait States
Word
Initial Wait
0
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
1
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
2
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
3
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
4
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
5
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12 D12 D12 D12 D12 D12 D12 D12
0
1
2
3
4
5
6
7
D0
6
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws
9
0
1
2
3
4
5
6
7
D0
7
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12 D12 D12 D12 D12 D12 D12 D12
1 ws 1 ws
9
0
1
2
3
4
5
6
7
D0
4 ws
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SUPPLEMENT
Address Latency for 3 Wait States
Word Initial Wait
0
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
1
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
2
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
3
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
4
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
5
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
6
D11
2
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
9
D12
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
7
D11
3
D11
4
D11
5
D11
6
D11
7
D11
8
D11
D12
1 ws
9
0
D12
1
D12
2
D12
3
D12
4
D12
5
D12
6
D12
7
D0
4 ws
7.5
Synchronous (Burst) Read Mode & Configuration Register
See Configuration Registers on page 28, and Table , Memory Array Commands on page 81, for further details.
Figure 7.1 Synchronous/Asynchronous State Diagram
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
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Figure 7.2 Synchronous Read Flow Chart
Note: Setup Configuration Register parameters
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Load Initial Address
Address = RA
Wait tIACC +
Programmable Wait State Setting
Read Initial Data
RD = DQ[15:0]
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
Unlock Cycle 1
Unlock Cycle 2
Command Cycle
CR = Configuration Register Bits CR15-CR0
RA = Read Address
CR13-CR11 sets initial access time
(from address latched to
valid data) from 2 to 7 clock cycles
RD = Read Data
Refer to the Latency tables.
Read Next Data
RD = DQ[15:0]
Delay X Clocks
Yes
Crossing
Boundary?
No
End of Data?
Yes
Completed
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7.5.1
Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wraps around
to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system
drives CE# high, or RESET#= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address
to the device.
If the address being read crosses a 128-word line boundary with in the same bank, but not into a program or erase suspended
sector (as mentioned above), additional latency cycles are required as reflected by the configuration register table (Table ).
If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status
information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read
operation using a new address and AVD# pulse.
7.5.2
8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are
determined by the group within which the starting address falls. The groups are sized according to the number of words read in a
single burst sequence for a given mode (see Table ).
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 38-3Fh, and the burst
sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are
read, regardless of where the starting address occurs in the address group, and then terminates the burst read.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the
device, then wrap back to the first address in the selected address group.
Note
In this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are
inserted due to boundary crossing.
Burst Address Groups
Mode
Group Size
8-word
8 words
0-7h, 8-Fh, 10-17h,...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh,...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh,...
7.5.3
Group Address Ranges
8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum
memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first
address of the selected group.
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 3Ch-43h, and the burst
sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address
and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which
will incur the additional boundary crossing wait state.
7.5.4
Configuration Registers
This device uses two 16-bit configuration registers to set various operational parameters. Upon power-up or hardware reset, the
device defaults to the asynchronous read mode, and the configuration register settings are in their default state. The host system
should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command
sequence before attempting burst operations. The Configuration Register can also be read using a command sequence (see Table
on page 81). The following list describes the register settings.
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SUPPLEMENT
Configuration Register
CR Bit
Function
CR0.15
Set Device Read Mode
CR0.14
Reserved (Not used)
CR1.0
CR0.13
CR0.12
Programmable Wait State
CR0.11
Settings (Binary)
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (Default)
0 = Reserved
1 = Reserved (Default)
0000 = initial data is valid on the 2nd rising CLK edge after addresses are latched
0001 = initial data is valid on the 3rd rising CLK edge after addresses are latched
0010 = initial data is valid on the 4th rising CLK edge after addresses are latched
0011 = initial data is valid on the 5th rising CLK edge after addresses are latched
0100 = initial data is valid on the 6th rising CLK edge after addresses are latched
0101 = initial data is valid on the 7th rising CLK edge after addresses are latched
0110 = Reserved
0111 = Reserved
1000 = initial data is valid on the 8th rising CLK edge after addresses are latched
1001 = initial data is valid on the 9th rising CLK edge after addresses are latched
1010 = initial data is valid on the 10th rising CLK edge after addresses are latched
1011 = initial data is valid on the 11th rising CLK edge after addresses are latched
1100 = Reserved
1101 = default
1110 = Reserved
1111 = Reserved
0 = RDY signal is active low
1 = RDY signal is active high (Default)
CR0.10
RDY Polarity
CR0.9
Reserved (Not used)
CR0.8
RDY
CR0.7
Reserved (Not used)
0 = Reserved
1 = Reserved (Default)
CR0.6
Reserved
0 = Reserved
1 = Reserved (Default)
CR0.5
Reserved
0 = Reserved (Default)
1 = Reserved
CR0.4
RDY Function
CR0.3
Burst Wrap Around
CR0.2
CR0.1
Burst Length
CR0.0
0 = Reserved
1 = Reserved (Default)
0 = RDY active one clock cycle before data
1 = RDY active with data (Default)
0 = RDY (Default)
1 = Reserved
0 = No Wrap Around Burst
1 = Wrap Around Burst (Default)
000 = Continuous (Default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
Notes:
1. Device will be in the Asynchronous Mode upon power-up or hardware reset.
2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default).
3. CR0.3 is ignored if in continuous read mode (no warp around).
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SUPPLEMENT
4. A software reset command is required after reading or writing the configuration registers in order to set the device back to array read mode.
5. Refer to Table on page 81 for reading the settings and writing onto configuration registers command sequences.
6. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous
settings.
7.6
Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended
for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes
can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order
address bits (see Table on page 30). The remaining address bits are don't care. The most significant four bits of the address during
the third write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed
normally for data read without exiting the Autoselect mode.
To access the Autoselect codes, the host system must issue the Autoselect command.
The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read
mode.
The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support
simultaneous operations or burst mode.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in
Erase Suspend).
See Table on page 81 for command sequence details.
Autoselect Addresses
Description
Address
Read Data
Manufacturer ID
Word 00
(BA) + 00h
0001h
Device ID,
Word 01
(BA) + 01h
227Eh
Sector Lock/Unlock
Word 02
(SA) + 02h
0001h = Locked,
0000h = Unlocked
Indicator Bits
Word 03
(BA) + 03h
DQ15 - DQ8 = reserved
DQ7 - Factory Lock Bit;
1 = Locked, 0 = Not Locked
DQ6 -Customer Lock Bit;
1 = Locked, 0 = Not Locked
DQ5 - Handshake Bit;
1 = Reserved,
0 = Standard Handshake
DQ4 & DQ3 - WP# Protection Boot Code;
00 = WP# Protects both Top Boot and Bottom Boot
Sectors,
DQ2 - DQ0 = reserved
Device ID,
Word 0E
(BA) + 0Eh
223Dh (WS512P)-1CE#
2242h (WS256P)
2244h (WS128P)
Device ID,
Word 0F
(BA) + 0Fh
2200h
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Software Functions and Sample Code
Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Byte Address
Word Address
Data
Unlock Cycle 1
Write
Unlock Cycle 2
Write
BA+AAAh
BA+555h
0x00AAh
BA+555h
BA+2AAh
0x0055h
Autoselect Command
Write
BA+AAAh
BA+555h
0x0090h
Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Byte Address
Word Address
Data
Unlock Cycle 1
Write
xxxxh
xxxxh
0x00F0h
Notes:
1. Any offset within the device works.
2. BA = Bank Address. The bank address is required.
3. base = base address.
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Cypress Low
Level Driver User’s Guide for general information on Cypress Flash memory software development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef volatile unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/*
Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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SUPPLEMENT
7.7
S29WS512P
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Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following
sections. However, prior to any programming and or erase operation, devices must be setup appropriately as outlined in the
configuration register (Table on page 29).
During synchronous write operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE#
to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or
programming data. Addresses are latched on the rising edge of AVD# pulse or rising edge of CLK or falling edge of WE#, whichever
occurs first.
During asynchronous write operations, addresses are latched on the rising edge of AVD# or falling edge of WE# while data is
latched on the 1st rising edge of WE#, or CE# whichever comes first.
Note the following:
When the Embedded Program/Erase algorithm is complete, the device returns to the read mode.
The system can determine the status of the Program/Erase operation. Refer to Write Operation Status on page 44 for further
information.
While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt will be ignored as only an erase operation
can covert a 0 to a 1. For example:
Old Data = 0011
New Data = 0101
Result = 0001
Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except the Program/Erase
Suspend commands.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a Program/Erase operation is in progress.
A hardware reset and/or power removal immediately terminates the Program/Erase operation and the Program/Erase command
sequence should be reinitiated once the device has returned to the read mode to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries only for single word programming operation. See Write
Buffer Programming on page 34 when using the write buffer.
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7.7.1
Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to
program an individual Flash address. While the single word programming method is supported by all Cypress devices, in general it
is not recommended for devices that support Write Buffer Programming. See Table on page 81 for the required bus cycles and
Figure 7.3 for the flowchart.
When the Embedded Program algorithm is complete, the device returns to the read mode and addresses are no longer latched. The
system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for
information on these status bits.
Figure 7.3 Single Word Program
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Polling Status
= Busy?
Yes
No
Yes
Polling Status
= completed
Error condition
(Exceeded Timing Limits)
No
Operation successfully completed
Document Number: 002-01747 Rev. *B
Operation failed
Page 33 of 91
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SUPPLEMENT
Software Functions and Sample Code
Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Byte Address
Word Address
Data
Unlock Cycle 1
Write
Base + AAAh
Base + 555h
00AAh
Unlock Cycle 2
Write
Base + 554h
Base + 2AAh
0055h
Program Setup
Write
Base + AAAh
Base + 555h
00A0h
Program
Write
Word Address
Word Address
Data Word
Note:
Base = Base Address.
The following is a C source code example of using the single word program function. Refer to the Cypress Low Level Driver User’s
Guide (available on www.Cypress.com) for general information on Cypress Flash memory software development guidelines.
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 )
*( (UINT16 *)base_addr + 0x2AA )
*( (UINT16 *)base_addr + 0x555 )
*( (UINT16 *)pa )
/* Poll for program completion */
7.7.2
=
=
=
=
0x00AA;
0x0055;
0x00A0;
data;
/*
/*
/*
/*
write
write
write
write
unlock cycle 1
unlock cycle 2
program setup command
data to be programmed
*/
*/
*/
*/
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster
effective word programming time than the standard word programming algorithms. The Write Buffer Programming command
sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming will occur. At this point, the system writes the number of word
locations minus 1 that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the device
how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm
command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (NOTE: the size
of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to
program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.)
The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer. It is to be noted that
Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of
the selected write-buffer addresses, the operation aborts after the Write to Buffer command is executed. Also, the starting address
must be the least significant address. All subsequent addresses and write buffer data must be in sequential order.
The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed,
and selects the write-buffer-page address. All subsequent address/data pairs must be in sequential order.
After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write
buffer locations must be loaded in sequential order starting with the lowest address in the page. Note that if the number of address/
data pairs do no match the word count, the program buffer to flash command is ignored.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data
load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command will be programmed into
the device. It is the software’s responsibility to comprehend ramifications of loading a write-buffer location more than once. The
counter decrements for each data load operation, NOT for each unique write-buffer-address location.
Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash
command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The
device will then go busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the
write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue
the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5,
DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming.
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SUPPLEMENT
The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon
successful completion of the Write Buffer Programming operation, the device will return to READ mode.
The Write Buffer Programming Sequence is ABORTED in the following ways:
Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is not valid in this
condition).
Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer
data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
Software Functions and Sample Code
Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Unlock
Write
Base + AAAh
Base + 555h
00AAh
2
Unlock
Write
Base + 554h
Base + 2AAh
0055h
3
Write Buffer Load Command
Write
Program Address
0025h
4
Write Word Count
Write
Program Address
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Load Buffer Word N
Write
Program Address, Word N
Word N
Last
Write Buffer to Flash
Write
Sector Address
0029h
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be
from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to the Cypress Low Level Driver User’s
Guide (available on www.Cypress.com) for general information on Cypress Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */
/* NOTES: Write buffer programming limited to 16 words. */
/* All addresses to be written to the flash in */
/* one operation must be within the same write buffer. */
/* A write buffer begins at addresses evenly divisible */
/* by 0x20.
UINT16 i; */
UINT16 *src = source_of_data; /* address of source data */
UINT16 *dst = destination_of_data; /* flash destination address */
UINT16 wc = words_to_program -1; /* word count (minus 1) */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */
*( (UINT16 *)dst ) = wc; /* write word count (minus 1) */
for (i=0;i For WS128 = 2244h, WS256 = 2242h, WS512 = 223Dh. (BA) + 0Fh ----> For WS064/128/256/512 = 2200h
11. The data is 0000h for an unlocked sector and 0001h for a locked sector
12. See Table , Autoselect Addresses on page 30.
13. The Unlock Bypass command sequence is required prior to this command sequence.
14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Program/Erase Suspend command
is valid only during a program/ erase operation, and requires the bank address.
16. The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address.
17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the
command sequence is 37.
18. Write Buffer Programming can be initiated after Unlock Bypass Entry.
19. Data is always output at the rising edge of clock.
20. Must be the lowest address.
21. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous
settings
Document Number: 002-01747 Rev. *B
Page 82 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Sector Protection Commands (Sheet 1 of 2)
Command Sequence
(Notes)
Entry (5)
Secured Program
Silicon
Read
Sector
Exit (7)
Register
Command Set
Entry (5)
Cycles
Bus Cycles (Note 1 - 6)
Password
Second
Third
Fourth
Fifth
Sixth
Seventh
Data
Data
Data
Data
Data
Data
Data
Addr (10) Addr ((10) Addr ((10) Addr ((10) Addr ((10) Addr ((10) Addr ((10)
3
555
AA
2AA
55
555
88
2AA
55
555
A0
PA
PD
XX
00
4
555
AA
1
SA
data
4
555
AA
2AA
55
555
90
3
555
AA
2AA
55
555
40
XX
A0
00
data
00
data
555
60
Register Bits
2
Lock
Program (6)
Register
Register Bits Read 1
PPB
First
Register
Command Set Exit
(7)
2
XX
90
XX
00
Protection
Command Set
Entry
3
555
AA
2AA
55
PW
D0/
1/
2/
3/
Program (9)
2
XX
A0
00/
01/
02/
03
Read Password
(10)
4
00
PW
D0
01
PW
D1
02
PW
D2
03
PW
D3
Unlock (9)
7
00
25
00
03
00
PW
D0
01
PW
D1
Protection
Command Set Exit
2
XX
90
XX
00
Non-Volatile
Sector Protection
Command Set
Entry (5)
3
555
AA
2AA
55
(BA)
555
C0
Program
2
XX
A0
(BA)
SA
00
All Erase (8)
2
XX
80
XX
30
Status Read
1
(BA)
SA
RD(
0)
Non-Volatile
Sector Protection
Command Set Exit
(7)
2
XX
90
XX
00
Document Number: 002-01747 Rev. *B
02
PW
D2
03
PW
D3
00
29
Page 83 of 91
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SUPPLEMENT
Sector Protection Commands (Sheet 2 of 2)
Command Sequence
(Notes)
Cycles
Bus Cycles (Note 1 - 6)
First
Second
3
555
AA
2AA
55
Set
2
XX
A0
XX
00
Status Read
1
XX
RD(
0)
Global Volatile
Sector Protection
Freeze Command
Set Exit (7)
2
XX
90
XX
00
Volatile Sector
Protection
Command Set
Entry (5)
3
555
AA
2AA
55
Set
2
XX
A0
(BA)
SA
00
Clear
2
XX
A0
(BA)
SA
01
Status Read
1
(BA)
SA
RD(
0)
Volatile Sector
Protection
Command Set Exit
(7)
2
XX
90
XX
00
Program
2
555
A0
PA
Data
Sector Erase
2
555
80
SA
30
Chip Erase
Accelera Asynchronous
ted
Read
2
555
80
555
10
1
RA
RD
Write to Buffer
4
SA
25
SA
WC
Program Buffer to
Flash
1
SA
29
DYB
Fourth
Fifth
Sixth
Seventh
Data
Data
Data
Data
Data
Data
Data
Addr (10) Addr ((10) Addr ((10) Addr ((10) Addr ((10) Addr ((10) Addr ((10)
Global Volatile
Sector Protection
Freeze Command
Set Entry (5)
PPB
Lock Bit
Third
555
50
(BA)
555
E0
PA
PD
WBL
PD
Legend
X = Don’t care
RA = Read Address
RD = Read Data
PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.
SA = Sector Address: WS128P = A22–A14, WS256P = 23–A14
BA = Bank Address: WS128P = A22-A20, and A19; WS256P = A23-A20
CR = Configuration Register data bits D15–D0
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password.
PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.
PWD = Password Data
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Document Number: 002-01747 Rev. *B
Page 84 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Notes
1. See Table for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register
verify and password verify commands, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0.
5. Entry commands are required to enter a specific mode to enable instructions only available within that mode.
6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns
the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the
WS512P only.
7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state.
8. “All PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure.
9. Entire two bus-cycle sequence must be entered for each portion of the password.
10. Full address range is required for reading password.
12.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows
specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the
device is ready to read array data. The system can read CFI information at the addresses given in Tables – within that bank. All
reads outside of the CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed, writes are not.
To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Cypress Low Level Driver User’s
Guide (available on www.Cypress.com) for general information on Cypress Flash memory software development guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
/* write cfi exit command
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01). Please contact
your sales office for copies of these documents.
CFI Query Identification String
Addresses
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string QRY
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Document Number: 002-01747 Rev. *B
Description
Page 85 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
System Interface String
Addresses
Data
1Bh
0017h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0019h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0005h
Typical Program Time per single word write 2N µs (e.g. 30us)
20h
0009h
Typical Program Time using buffer 2N µs (e.g. 300us) (00h = not supported)
21h
000Ah
Typical time for sector erase 2N ms
22h
0000h
Typical time for full chip erase 2N ms (00h = not supported)
23h
0003h
Max. Program Time per single word [2N times typical value]
24h
0003h
Max. Program Time using buffer [2N times typical value]
25h
0003h
Max. time for sector erase [2N times typical value]
26h
0000h
Max. time for full chip erase [2N times typical value] (00h = not supported)
Document Number: 002-01747 Rev. *B
Description
Page 86 of 91
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S29WS256P
S29WS128P
SUPPLEMENT
Device Geometry Definition
Addresses
Data
Description
27h
0018h (WS128P)
0019h (WS256P)
001Ah (WS512P)
28h
29h
0001h
0000h
Flash Device Interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte]
[upper byte] (00h = not supported)
2Ah
2Bh
0006h
0000h
Max. number of bytes in multi-byte buffer write = 2N [lower byte]
[upper byte] (00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
01h = Uniform Sector; 02h = Boot + Uniform; 03h = Boot + Uniform + Boot
2Dh
2Eh
2Fh
30h
0003h
0000h
0080h
0000h
Erase Block Region 1 Information (Small Sector Section)
[lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors
[upper byte]
[lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h
[upper byte]
Device Size = 2N byte
Erase Block Region 2 Information (Large Sector Section)
31h
32h
33h
34h
007Dh (WS128P)
00FDh (WS256P)
00FDh (WS512P)
0001h
0000h
0002h
[lower byte] - Number of sectors.
[upper byte]
[lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h
[upper byte]
35h
36h
37h
38h
0003h
0000h
0080h
0000h
Erase Block Region 3 Information (Small Sector Section)
[lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors
[upper byte]
[lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h
[upper byte]
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
Document Number: 002-01747 Rev. *B
Page 87 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Addresses
Data
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string PRI
43h
0031h
Major CFI version number, ASCII
44h
0034h
Minor CFI version number, ASCII
45h
0101b
Address Sensitive Unlock (Bits 1-0)
00b = Required, 01b = Not Required
Silicon Technology (Bits 5-2) 0011b = 130nm; 0100b = 110nm; 0101b = 90nm
001010b = 000Ah
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protection per Group
0 = Not Supported, X = Number of sectors in per group
48h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0008h
Sector Protect/Unprotect scheme
08h = Advanced Sector Protection; 07h = New Sector Protection Scheme
4Ah
07Bh (WS128P)
0F3h (WS256P)
1E3h (WS512P)
4Bh
0001h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0002h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page
4Dh
0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh
0095h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh
0001h
Write Protect Function
00h = No Boot, 01h = Dual Boot, 02h = Bottom Boot, 03h = Top Boot
50h
0001h
Program Suspend. 00h = not supported
51h
0001h
Unlock Bypass
00 = Not Supported, 01=Supported
52h
0008h
Secured Silicon Sector (Customer OTP Area) Size 2N bytes
53h
0014h
Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum
2N ns (e.g. 10us => n=14)
54h
0014h
Hardware Reset Low Time-out not during an embedded algorithm to read mode
Maximum 2N ns (e.g. 10us => n=14)
55h
0005h
Erase Suspend Time-out Maximum 2N µs
56h
0005h
Program Suspend Time-out Maximum 2N µs
57h
0010h
Bank Organization: X = Number of banks
58h
0007h (WS064P)
000Bh (WS128P)
0013h (WS256P)
0023h (WS512P)
Document Number: 002-01747 Rev. *B
Description
Simultaneous Operation
Number of Sectors in all banks except boot bank
Bank 0 Region Information. X = Number of sectors in bank
Page 88 of 91
S29WS512P
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S29WS128P
SUPPLEMENT
Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses
Data
59h
0004h (WS064P)
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 1 Region Information. X = Number of sectors in bank
5Ah
0004h (WS064P)
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 2 Region Information. X = Number of sectors in bank
5Bh
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 3 Region Information. X = Number of sectors in bank
5Ch
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 4 Region Information. X = Number of sectors in bank
5Dh
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 5 Region Information. X = Number of sectors in bank
5Eh
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 6 Region Information. X = Number of sectors in bank
5Fh
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 7 Region Information. X = Number of sectors in bank
60h
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 8 Region Information. X = Number of sectors in bank
61h
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 9 Region Information. X = Number of sectors in bank
62h
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 10 Region Information. X = Number of sectors in bank
63h
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 11 Region Information. X = Number of sectors in bank
64h
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 12 Region Information. X = Number of sectors in bank
65h
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 13 Region Information. X = Number of sectors in bank
66h
0008h (WS128P)
0010h (WS256P)
0020h (WS512P)
Bank 14 Region Information. X = Number of sectors in bank
67h
000Bh (WS128P)
0013h (WS256P)
0023h (WS512P)
Bank 15 Region Information. X = Number of sectors in bank
Document Number: 002-01747 Rev. *B
Description
Page 89 of 91
S29WS512P
S29WS256P
S29WS128P
SUPPLEMENT
13. Revision History
Document Title:S29WS512P, S29WS256P, S29WS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V, Simultaneous Read/Write Flash
Document Number: 002-01747
Rev.
ECN No.
Orig. of
Change
Submission
Date
11/03/2006
11/08/2006
03/09/2007
03/27/2007
04/20/2007
**
-
WIOB
09/28/2007
01/28/2008
Description of Change
Spansion Publication Number: S30MS02GR_SP1_QDB
A6:Features: Removed Zero Hold mode
Switching Waveforms: Revised VCC Power-up diagram
Timing Diagrams: Changed tCR to tRDY in figure 11.7 and figure 11.8
A7:Features: Updated Effective Write Buffer Programming Per Word
Erase/Program Timing: tESL changed to Max
tPSL changed to Max
CMOS Compatible: Removed Note 2 from table.
A8:Asynchronous Mode Read: Changed tCR to tRDY in figures 11.9 through 11.12
Common Flash Memory Interface: Revised Device Geometry table:
Changed WS512P data to 00FDh
Address 32h - Data changed to 001h
Address 33h - Data changed to 000h
Address 34h - Data changed to 002h
Revised CFI table: removed Uniform Bottom, Uniform Top, and All sectors for Address
4Fh
DC Characteristics: Revised ICCB Burst table
A9:DC Characteristics: Revised ICCB for 108 MHz frequencies to TBA
Synchronous/Burst Read: Revised tRACC to 7.6 ns
Asynchronous Mode Read: Revised tAAVDH to 4 ns
A10:AC Characteristics:
Removed wait state below 14 MHz, wait state 2
Added additional wait state to all wait state frequency in table 11.4
Added Continuous Burst Mode Synchronous Wait State Requirement table
Revised Burst Access Time to (WS-1) * tCK + (tBACC)
A11:Data Sheet Status: Changed to Production
Global: Changed all 108 MHz to 104 MHz
Latency: Added 10 wait state and 11 wait state latency tables
Configuration Registers: Added two more configurations to CR0.11 for 10th and 11th
rising CLK edge
AC Characteristics: Revised tCES to 6 ns
Revised tAVD to tCLK
DC Characteristics: Changed description of ICC2 to VCC Active Program/Erase Current
Change descritpion of ICC5 to VCC Active Current (Read while Program/Erase)
Erase/Program Timing and Performance:
Revised:
tERS to 40 µs
tESL to 40 µs
tPSL to 40 µs
tPRS to 40 µs
Output Slew Rate:
Deleted Programmable Outuput Slew Rate Control section
A12:Configuration Registers: Changed CR0.14 default setting to 1
AC Characteristics: Added device Vcc ramp rate limit. Updated timing diagrams for
Synchronous/Burst Read, Asynchronous Program Operation, Synchronous Program
Operation, and Chip Sector Erase Command Sequence.
Program/Erase Operations: Added details to Program and Erase Suspend/Resume
operations
*A
5046533
WIOB
12/14/2015
Updated to Cypress Template
*B
5790689
NIBK
06/29/2017
Updated to Cypress Logo and Copyright.
Document Number: 002-01747 Rev. *B
Page 90 of 91
SUPPLEMENT
S29WS512P
S29WS256P
S29WS128P
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-01747 Rev. *B
Revised June 29, 2017
Page 91 of 91