"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions
at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly
interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion,
Inc." products to new and existing customers.
Continuity of Specifications
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There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future
revisions will occur when appropriate, and changes will be noted in a document history page.
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Continuity of Ordering Part Numbers
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Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed
in this document.
For More Information
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Please contact your local sales office for additional information about Cypress products and solutions.
S29WS512R, S29WS256R, S29WS128R
512/256/128 Mb (32/16/8M x 16 bit)
1.8 V S29WS-R MirrorBit® Flash
This product family has been retired and is not recommended for designs. For new and current designs, S29WS512P,
S29WS256P, and S29WS128P supersedes S29WS512R, S29WS256R, and S29WS128R respectively. This is the factoryrecommended migration path. Please refer to the S29WS-P data sheet for specifications and ordering information.
Availability of this document is retained for reference and historical purposes only.
Features
65 nm MirrorBit Technology
– 100,000 cycles per sector (typical)
– 10-year data retention (typical)
Single supply 1.8 V read/program/erase (1.70 V – 1.95 V)
Data Protection
– Low VCC write inhibit
Secured Silicon Sector
– 512 Bytes of Secured Silicon Sector region consisting of One Time
Program (OTP) area of 256 bytes each for factory and customer
– Hardware Sector Protection (via ACC pin)
Wireless Temperature range (-25°C to +85°C)
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16-bit (Word) data bus width
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Simultaneous Read/Write (SRW) operation
– Read from one bank while programming or erasing in another
bank
– Memory array is divided into 16 equal size banks
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– All sectors protected when ACC input is at VIL
Programmable linear (8/16) with wrap around and continuos burst
read modes
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– Boot code controlled sector protection
– A range of sectors may be protected to prevent program and erase
until the next hardware reset or power is removed from the device
RDY output for data transfer flow control
Sector Erase
– Four 32 Kbyte sectors at top or bottom of memory array
– All other sectors are 128 Kbytes
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– Dynamic sector protection
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Optional acceleration voltage supply (ACC) to reduce factory
programming time
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Write Buffer Programming up to 64 -byte groups
Suspend and Resume commands for Program and Erase
operations
Write operation status register bits indicate program and erase
operation completion
Common Flash Interface (CFI) data structure
Offered Packages
– 512/256/128R: 84-ball FBGA (11.6mm x 8mm) VBH084
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Program-Erase Endurance
– All sectors are unprotected at power on for simplified system
production test & programming
– A single command is used to protect all sectors from program or
erase
– A single sector at a time may be unprotected by a command to
enable programming or erase.
Cypress Semiconductor Corporation
Document Number: 002-01101 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 09, 2015
S29WS512R, S29WS256R,
S29WS128R
Performance Characteristics
Read Access Times (maximum values)
Speed Option (MHz)
104
Synch. Internal Access, ns (tIA)
75
Synch. Burst Access, ns (tBACC)
7.6
Asynch. Access Time, ns (tACC)
80
Current Consumption (typical values)
Burst Read @ 104 MHz (ICCB)
32 mA
Simultaneous Operation @ 104 MHz (ICC5)
52 mA
20 mA
20 mA
Standby Mode (ICC3)
20 µA
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Program (ICC2)
Erase (ICC2)
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Typical Program & Erase Times (typical values)
Effective Write Buffer Programming (VCC) Per Word
12.5 µs
Sector Erase (128 KByte Sector) (VCC)
0.8 s
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0.35 s
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8 µs
Sector Erase (32 KByte Sector) (VCC)
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Effective Write Buffer Programming (VACC) Per Word
Document Number: 002-01101 Rev. *I
Page 3 of 77
S29WS512R
S29WS256R, S29WS128R
Contents
2.
2.1
Ordering Information ................................................... 5
Valid Combinations ........................................................ 5
3.
Input/Output Descriptions & Logic Symbol .............. 6
4.
Block Diagrams............................................................ 7
5.
5.1
5.2
5.3
Physical Dimensions/Connection Diagrams.............
Related Documents .......................................................
Special Handling Instructions for FBGA Package..........
Connection Diagrams and Physical Dimensions ...........
6.
Product Overview ...................................................... 10
7.
7.1
7.2
7.3
Address Space Maps .................................................
Data Address & Quantity Nomenclature ......................
Flash Memory Array.....................................................
Device ID and CFI (ID-CFI)..........................................
10
11
12
21
Device Operations .....................................................
Device Bus Operations ................................................
Asynchronous Read.....................................................
Page Mode Read .........................................................
Synchronous (Burst) Read Mode and Configuration
Register........................................................................
8.5 Status Register ............................................................
8.6 Blank Check.................................................................
8.7 Simultaneous Read/Write ............................................
8.8 Writing Commands/Command Sequences..................
8.9 Program/Erase Operations ..........................................
8.10 Handshaking ................................................................
8.11 Hardware Reset ...........................................................
8.12 Software Reset ............................................................
23
24
24
25
Power Conservation Modes....................................... 46
Standby Mode............................................................... 46
Automatic Sleep Mode.................................................. 46
Output Disable (OE#).................................................... 46
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
Electrical Specifications............................................. 47
Absolute Maximum Ratings .......................................... 47
Operating Ranges......................................................... 47
DC Characteristics ........................................................ 48
Capacitance .................................................................. 49
AC Test Conditions ....................................................... 49
Key to Switching Waveforms ........................................ 50
VCC Power Up............................................................... 50
CLK Characterization.................................................... 51
AC Characteristics ........................................................ 52
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12. Appendix ..................................................................... 63
12.1 Command Definitions.................................................... 63
12.2 Device ID and Common Flash Memory Interface
Address Map................................................................. 65
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8.
8.1
8.2
8.3
8.4
7
7
7
8
10.
10.1
10.2
10.3
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General Description..................................................... 5
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1.
Sector Protection/Unprotection................................. 42
Sector Lock/Unlock Command ..................................... 43
Sector Lock Range Command...................................... 43
Hardware Data Protection Methods.............................. 44
SSR Lock...................................................................... 44
Secure Silicon Region................................................... 44
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Performance Characteristics............................................... 3
9.
9.1
9.2
9.3
9.4
9.5
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Features................................................................................. 2
13.
Revision History.......................................................... 71
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31
34
35
35
35
41
42
42
Document Number: 002-01101 Rev. *I
Page 4 of 77
S29WS512R
S29WS256R, S29WS128R
1.
General Description
The Spansion S29WS512/256/128R are Mirrorbit flash products fabricated on 65 nm process technology. These burst mode flash
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate
data and address pins. These products can operate up to 104 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal
for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.
2.
Ordering Information
This product family has been retired and is not recommended for designs. For new and current designs, S29WS512P, S29WS256P,
and S29WS128P supersedes S29WS512R, S29WS256R, and S29WS128R respectively. This is the factory-recommended
migration path. Please refer to the S29WS-P data sheet for specifications and ordering information.
Availability of this document is retained for reference and historical purposes only.
R
0P
BH
W
00
0
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Packing Type
0 = Tray (standard; see note 1)
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
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S29WS
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The order number is formed by a valid combinations of the following:
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Model Number
(Boot Configuration Options)
00 = Uniform, 1 CE
20 = Top Boot, 1 CE
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Temperature Range
W = Wireless (–25C to +85C)
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Package Type And Material
BH = Very Thin Fine-Pitch BGA, Low-Halogen Lead (Pb)-free Package
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Speed Option (Burst Frequency)
0P = 66 MHz
0S = 83 MHz
AA = 104 MHz
Flash Density
512 =512 Mb
256 =256 Mb
128 =128 Mb
Device Family
S29WS =1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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Process Technology
R = 65 nm MirrorBit Technology
2.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
S29WS-R Valid Combinations (Notes 1, 2)
Base Ordering
Part Number
Speed
Option
Package Type, Material, &
Temperature Range
Packing
Type
Model
Numbers
Package Type
(Note 2)
Product
Status
0P, 0S, AA
BHW (Low-Halogen, Lead
(Pb)-free)
0, 2, 3
(Note 1)
00, 20
11.6 mm x 8 mm
84-ball
MCP-Compatible
Advance
S29WS512R
S29WS256R
S29WS128R
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S29 and packing type designator from ordering part number.
Document Number: 002-01101 Rev. *I
Page 5 of 77
S29WS512R
S29WS256R, S29WS128R
3. Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
Type
Description
Input
Higher order address lines. Amax = A24 for WS512R, A23 for WS256R,
A22 for WS128R
DQ15 – DQ0
I/O
Data input/output
F1-CE#
Input
Flash-1 Chip Enable. Asynchronous relative to CLK. Used to select the first portion of the flash device
address space that can be directly selected by one host chip enable signal.
F2-CE#
Input
Flash-2 Chip Enable. Asynchronous relative to CLK. Used to select the first portion of the flash device
address space that can be directly selected by one host chip enable signal.
OE#
Input
Output Enable. Asynchronous relative to CLK for the Burst mode
WE#
Input
Write Enable
VCC
Supply
Device Power Supply
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Amax – A0
Supply
Input/Output Power Supply (must be ramped simultaneously with VCC)
Supply
Ground
NC
No Connect
No Connected internally
RDY
Output
Ready. Indicates when valid burst data is ready to be read
CLK
Input
The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst
mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal
address counter. CLK should remain low during asynchronous access
AVD#
Input
Address Valid input. Indicates to device that the valid address is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be
latched on rising edge of CLK.
VIH = device ignores address inputs
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
ACC
Input
Accelerated input.
At VIL,disables all program and erase functions.
Should be at VIH for all other conditions.
RFU
Reserved
Reserved for future use
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VCCQ
VSS
Document Number: 002-01101 Rev. *I
Page 6 of 77
S29WS512R
S29WS256R, S29WS128R
4.
Block Diagrams
VCC
VSS
Y-Decoder
Bank Address
VCCQ
Bank 0
Latches and
Control Logic
Figure 4.1 Simultaneous Operation Circuit
DQ15–DQ0
Amax–A0
X-Decoder
OE#
X-Decoder
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Amax–A0
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ15–DQ0
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ACC
RESET#
WE#
Fx-CE#
AVD#
RDY
DQ15–DQ0
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Bank 1
Latches and
Control Logic
Y-Decoder
Bank Address
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Control
Amax–A0
DQ15–DQ0
Latches and
Control Logic
Bank (n)
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Bank Address
DQ15–DQ0
X-Decoder
Y-Decoder
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Amax–A0
Latches and
Control Logic
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Bank (n-1)
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Bank Address
Y-Decoder
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X-Decoder
DQ15–DQ0
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2. n = 15.
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Notes:
1. Amax = A24 for WS512R, A23 for WS256R, A22 for WS128R.
5. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications.
5.1
Related Documents
The following documents contain information related to this family of flash devices. Click on the title or go to www.spansion.com to
download the PDF file, or request a copy from your sales office.
5.2
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
Special Handling Instructions for FBGA Package
Special handling is required for flash memory products in FBGA packages.
Document Number: 002-01101 Rev. *I
Page 7 of 77
S29WS512R
S29WS256R, S29WS128R
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or
data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
5.3
Connection Diagrams and Physical Dimensions
Figure 5.1 84-ball Fine-Pitch Ball Grid Array
WS512R/WS256R/WS128R
(Top View, Balls Facing Down, MCP Compatible)
1
2
3
4
5
6
7
8
9
10
Legend
DNU
Do Not Use
A
DNU
VSS
CLK
F2-CE#
VCC
RFU
RFU
RFU
RFU
A7
RFU
ACC
WE#
A8
A11
RFU
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C
A3
A6
RFU
RESET#
RFU
A19
A2
A5
A18
RDY
A20
A9
A1
A4
A17
RFU
A23
A0
VSS
DQ1
RFU
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A13
A10
Power
A15
Ground
A21
A14
A22
A24
A16
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A12
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DQ6
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
RFU
DQ0
DQ10
VCC
RFU
DQ12
DQ7
VSS
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
RFU
VSS
VCC
RFU
RFU
VCCQ
RFU
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RFU
L
Reserved for
Future Use
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AVD#
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B
N
RFU
M
DNU
DNU
Notes
1. Ball G8 is RFU on the WS256R.
2. Ball G8 is A24 on densities 256 Mbit.
3. Address signals numbered greater than Amax of a particular device are reserved for future use and only indicate where the higher order address will be in higher
density members of related or future family devices.
Document Number: 002-01101 Rev. *I
Page 8 of 77
S29WS512R
S29WS256R, S29WS128R
VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8 mm MCP Compatible Package
0.05 C
(2X)
D
D1
A
e
10
9
e
7
8
SE
7
6
E1
E
5
4
3
2
1
M
A1 CORNER
K
J
H
G
B
10
E
D
SD
6
0.05 C
(2X)
F
NXφb
φ 0.08 M C
TOP VIEW
C
B
A
A1 CORNER
7
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INDEX MARK
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φ 0.15 M C A B
BOTTOM VIEW
A1
C
D
0.10 C
A2
A
0.08 C
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SEATING PLANE
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SIDE VIEW
NOTES:
PACKAGE
VBH 084
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
d
N/A
11.60 mm x 8.00 mm NOM
PACKAGE
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
11.60 BSC.
E
8.00 BSC.
D1
8.80 BSC.
E1
7.20 BSC.
MD
12
ME
10
N
84
?
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
BALL FOOTPRINT
BALL FOOTPRINT
R
ROW MATRIX SIZE D DIRECTION
---
0.43
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
0.80 BSC.
BALL PITCH
0.40 BSC.
SOLDER BALL PLACEMENT
(A2-A9, B10-L10,
M2-M9, B1-L1)
DEPOPULATED SOLDER BALLS
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
BODY SIZE
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SD / SE
0.33
BALL HEIGHT
2. ALL DIMENSIONS ARE IN MILLIMETERS.
BODY SIZE
N
φb
OVERALL THICKNESS
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NOTE
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SYMBOL
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JEDEC
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN ?
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note:
1. BSC is an ANSI standard for Basic Space Centering.
Document Number: 002-01101 Rev. *I
Page 9 of 77
S29WS512R
S29WS256R, S29WS128R
6.
Product Overview
The S29WS-R family consists of 128 Mbit to 1 Gbit, 1.8-V only, simultaneous read/write, burst-mode, flash devices. These devices
have a 16 bit (word) wide data bus. All read accesses provide 16 bits of data on each bus transfer cycle. All writes take 16 bits of
data from each bus transfer cycle.
Device
Mbits
Mbytes
Mwords
Banks
Mbytes / Bank
S29WS128R
128
16
8
16
1
S29WS256R
256
32
16
16
2
S29WS512R
512
64
32
16
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The flash memory array is divided into banks as shown in the above table. A bank is the address range within which one program, or
erase operation may be in progress at the same time as one read operation is in progress in any other bank of the memory. This
multiple bank structure enables Simultaneous Read and Write (SRW) so that code may be executed or data read from one bank
while a group of data is programmed, or erased as a background task in one other bank.
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Each bank is divided into sectors. A sector is the minimum address range of data which can be erased to an all Ones state. There
are four 32 Kbyte sectors which are located either at the bottom or top of the memory array depending on the device model
purchased. These are called boot sectors because they are often used for holding boot code or parameters that need to be
protected or erased separately from other data in the flash array. All other sectors are a uniform size of 128 Kbytes.
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Programming is done via a 64 Byte write buffer. It is possible to program from one to 32 words (64 bytes) in each programming
operation.
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7. Address Space Maps
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The S29WS family is capable of continuous, synchronous burst read or linear read (8- or 16-word aligned group) with wrap around.
A wrapped burst begins at the initial location and continues to the end of an 8- or 16-word aligned group then “wraps-around” to
continue at the beginning of the 8, or 16-word aligned group. The burst completes with the last word before the initial location. Word
wrap around burst is generally used for processor cache line fill.
There are five address spaces within each device:
A Non-Volatile Flash Memory Array used for storage of data that may be randomly read and reprogrammed
A Read Only Memory Array used for factory programmed permanent device characteristics information. This area contains
the Device Identification (ID) and Common Flash Interface (CFI) information.
A One Time Programmable (OTP) Non-volatile flash array used for factory programmed permanent data, and customer
programmable permanent data. This is called the Secure Silicon Region (SSR).
An OTP location used to permanently protect the SSR. This is call the SSR Lock.
A volatile register used to configure device behavior options. This is called the Configuration Register.
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The main Flash Memory Array is the primary and default address space but, it may be partially overlaid by the other four address
spaces with one alternate address space available at any one time. The location where the alternate address space is overlaid is
defined by the address provided in the command that enables each overlay. The portion of the command address that is sufficient to
select a sector is used to select the sector that is overlaid by an alternate Address Space Overlay (ASO).
Any address range, within the overlaid sector, not defined by an overlay address map, is reserved for future use. All read accesses
outside of an address map within the selected sector, return non-valid data. The locations will display actively driven data but the
meaning of whatever ones or zeros appear are not defined.
There are three operation modes for each bank that determine what portions of the address space are readable at any given time:
Read Mode
Embedded Algorithm (EA) Mode
Address Space Overlay (ASO) Mode
Each bank of the device can be in any operation mode but, only one bank can be in EA or ASO mode at any one time.
Document Number: 002-01101 Rev. *I
Page 10 of 77
S29WS512R
S29WS256R, S29WS128R
In Read Mode a Flash Memory Array bank may read directly by asynchronous or synchronous accesses from the host system bus.
The Flash Control Unit (CU) puts all banks in Read mode during Power-on, a Hardware Reset, after a Command Reset, or after a
bank is returned to Read mode from EA mode. A bank with a suspended EA is considered to be returned to Read mode even
though some or all of the data in the bank may be in an invalid state and thus not useful if read.
In EA mode the flash memory array data in a bank is stable but undefined, and effectively unavailable for read access from the host
system. While in EA mode the bank is used by the CU in the execution of commands. Typical EA mode operations are programming
or erasing of data in the flash array. All other banks are available for read access while the one bank is in EA mode. This ability to
read from one bank while another bank is used in the execution of a command is called Simultaneous Read and Write (SRW) and
allows for continued operation of the system via the reading of data or execution of code from other banks while one bank is
programming or erasing data as a relatively long time frame background task.
In ASO mode, one of the overlay address spaces are overlaid in a bank (entered). That bank is in ASO mode and no other bank may
be in EA or ASO mode. All EA activity must be completed before entering any ASO mode. A command for entering an EA or ASO
mode while another bank is in EA or ASO mode will be ignored.
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While an ASO mode is active (entered) in a bank, a read for flash array data to any other bank is allowed. ASO mode selects a
specific sector for the overlaid address space. Other sectors in the ASO bank still provide flash array data and may be read during
ASO mode.
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The ASOs are functionally tied to the lowest address bank. The commands used to overlay (enter) these areas must select a sector
address within the lowest address bank.
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While SSR Lock, SSR, or Configuration Register is overlaid only the SSR Lock, SSR, or Configuration Register respectively may be
programmed in the overlaid sector. While any of these ASO areas are being programmed the ASO bank switches to EA mode. The
ID/CFI and factory portion of the SSR ASO is not customer programmable.
7.1
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The address nomenclature used in this document is a shorthand form that shows addresses are formed from a concatenation of
high order bits, sufficient to select a Sector Address (SA), with low order bits to select a location within the sector. When in Read
mode and reading from the flash array the entire address is used to select a specific word for asynchronous read or the starting word
address of a burst read. When writing a command, the address bits between SA and the command specified least significant bits
must be Zero to allow for future extension of an overlay address map.
Data Address & Quantity Nomenclature
A Bit is a single One or Zero data value. A Byte is a group of 8 bits aligned on an 8 bit address boundary. A Word is a group of 16
bits aligned on a 16 bit address boundary. A Kbyte (KB) is 1024 Bytes (not 1000 Bytes).
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Throughout this document quantities of data are generally expressed in terms of bytes. Example: most sectors have 128 Kbytes
of data and is written as 128 Kbytes or 128 KB. Addresses are also expressed in byte units. A 128 Kbyte sector has an address
range from 00000h to 1FFFFh Byte locations. Byte units are used because most host systems and software for these systems use
byte resolution addresses. Software & hardware developers most often calculate code and data sizes in terms of bytes, so this is
more familiar terminology than describing data sizes in bits or words. In general, data units will not be abbreviated if possible so that
full unit names of Byte, Word, or bit are used. However, there may be cases where capital B is used for byte units and lower case b
is used for bit units, in situations where space is limited such as in table column headers.
In some cases data quantities will also be expressed in word or bit units in addition to the quantity shown in bytes. This may be done
as an aid to readers familiar with prior device generation documentation which often provided only word or bit unit values. Word units
may also be used to emphasize that, in the memory devices described in this documentation, data is always exchanged with the
host system in word units. Each bus cycle transfer of read or write data on the host system bus is a transfer 16 bits of data. A read
bus cycle is always a 16 bit wide transfer of data to the host system whether the host system chooses to look at all the bits or not. A
write bus cycle is always a transfer of 16 bits to the memory device and the device will store all 16 bits to a register. In the case of a
program operation all 16 bits of each word to be programmed will be stored in the flash array.
Because data is always transferred in word units, the memory devices being discussed use only the address signals from the
system necessary to select words. Most host systems use address line A0 to select bytes and a1 to select words. Flash memories
with word wide data paths have traditionally started their address signal numbering with A0 being the selector for words because a
byte select input is not needed. So, system address a[max] to a1 are connected to flash A[max] to A0.
In prior generation flash documentation, address values used in commands to the flash were documented from the viewpoint of the
flash device - the bit pattern appearing on flash address inputs A10 to A0. However, most software is written with addresses
expressed in bytes. This means the address patterns shown in flash command tables have traditionally been shifted by one bit to
Document Number: 002-01101 Rev. *I
Page 11 of 77
S29WS512R
S29WS256R, S29WS128R
express them as byte address values in flash control programs. Example: a prior generation flash data sheet would show a
command write of data value xxA0h to address 555h; this is an address pattern of 10101010101b on flash address inputs A10 to A0;
but software would define this as a byte address value of AAAh since the least significant address bit is not used by the flash); which
is 101010101010b on system address bus a11 to a0. Because system a11 to a1 is connected to flash A10 to A0 the flash word
address of 555h and the system byte address of AAAh provides the same bit pattern on the same address inputs. Because all
address values are being documented as system byte addresses, that are more familiar to software writers, the command tables
have addresses that are shifted from those shown in prior generation devices.
7.2
Flash Memory Array
Table 7.1 System Versus Flash View of Address
a10
1
0
Binary Pattern
a7
a6
1
0
1
0
A
Flash Word Address Hex
a4
a3
1
0
1
A
5
A10
a5
A8
A7
A6
0
0
a1
A
5
A9
a0
a2
1
5
A5
A4
A3
A2
A1
A0
N
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fo
rN
Flash Address Signals
a8
D
System Byte Address Hex
a9
es
a11
ew
System Address Signals
ig
n
The Non-Volatile Flash Memory Array is organized as shown in the following tables. Devices have either all uniform size sectors or
four smaller sectors at either the top or bottom of the device.
Document Number: 002-01101 Rev. *I
Page 12 of 77
S29WS512R
S29WS256R, S29WS128R
Table 7.2 S29WS512R Sector and Memory Address Map (Bottom Boot)
32
0
004000h–007FFFh
008000h–00FFFFh
SA002
008000h–00BFFFh
010000h–017FFFh
SA003
00C000h–00FFFFh
018000h–01FFFFh
SA004
010000h–01FFFFh
020000h–03FFFFh
SA034
1F0000h–1FFFFFh
3E0000h–3FFFFFh
1
SA035–SA066
200000h–3FFFFFh
400000h–7FFFFFh
2
SA067–SA098
3
SA097–SA130
4
SA131–SA162
5
SA163–SA194
6
SA195–SA226
SA291–SA322
10
SA323–SA354
11
SA355–SA386
12
SA387–SA418
es
1000000h–11FFFFFh
9
D
SA259–SA290
ew
SA227–SA258
8
Sector Starting
Address to Sector
Ending Address
2000000h–23FFFFFh
… … … … …
rN
7
Notes
ig
n
…
SA001
… … … … … …
000000h–007FFFh
…
000000h–003FFFh
… … … … … …
128
Address Range (byte)
SA000
13
SA419–SA450
14
SA451–SA482
de
480
128
Address Range
(word)
1C00000h–1DFFFFFh
3800000h–3BFFFFFh
15
SA483–SA514
1E00000F–1FFFFFFh
3C00000F–3FFFFFFh
om
m
en
31
Sector
Range
fo
32
32
Bank
d
4
Sector
Size
(Kbyte)
… … … … …
Sector
Count
…
Bank Size
(Mbit)
N
ot
R
ec
Note
All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
byte address pattern x000000h–x1FFFFh.
Document Number: 002-01101 Rev. *I
Page 13 of 77
S29WS512R
S29WS256R, S29WS128R
Address
Range (byte)
0
SA000–SA031
000000h–1FFFFFh
000000h–3FFFFFh
1
SA032–SA063
200000h–3FFFFFh
400000h–7FFFFFh
2
SA064–SA095
3
SA096–SA127
4
SA128–SA159
5
SA160–SA191
6
SA192–SA223
7
SA224–SA255
… … … … … …
8
SA256–SA287
1000000h–11FFFFFh
2000000h–23FFFFFh
9
SA288–SA319
10
SA320–SA351
32
15
32
ig
n
3C00000h–3C1FFFF
SA510
1FE0000h–1FEFFFFh
3FC0000h–3FDFFFFh
SA511
1FF0000h–1FF3FFFh
3FE0000h–3FE7FFFh
SA512
1FF4000h–1FF7FFFh
3FE8000h–3FEFFFFh
SA513
1FF8000h–1FFBFFFh
3FF0000h–3FF7FFFh
SA514
1FFC000h–1FFFFFFh
3FF8000h–3FFFFFFh
Sector Starting
Address –
Sector Ending
Address
N
ot
R
ec
om
m
en
4
3800000h–3BFFFFFh
fo
128
es
1E00000h–1E0FFFF
D
1C00000h–1DFFFFFh
SA480
ew
SA448–SA479
SA384–SA415
Sector Starting
Address –
Sector Ending
Address
…
SA416–SA447
14
SA352–SA383
12
Notes
rN
13
11
… … … … …
Address
Range (word)
… … … … …
Sector
Range
d
31
128
Bank
…
480
Sector Size
(Kbyte)
de
32
Sector
Count
…
Bank
Size
(Mbit)
… … … … … …
Table 7.3 S29WS512R Sector and Memory Address Map (Top Boot)
Document Number: 002-01101 Rev. *I
Page 14 of 77
S29WS512R
S29WS256R, S29WS128R
Sector
Range
Address
Range (word)
Address
Range (byte)
0
SA000–SA031
000000h–1FFFFFh
000000h–3FFFFFh
1
SA032–SA063
200000h–3FFFFFh
400000h–7FFFFFh
2
SA064–SA095
3
SA096–SA127
4
SA128–SA159
5
SA160–SA191
6
SA192–SA223
7
SA224–SA255
… … … … … …
8
SA256–SA287
1000000h–11FFFFFh
2000000h–23FFFFFh
9
SA288–SA319
Notes
SA448–SA479
1C00000h–1DFFFFFh
3800000h–3BFFFFFh
15
SA480–SA511
1E00000h–1FFFFFFh
3C00000h–3FFFFFFh
12
SA384–SA415
D
SA352–SA383
ig
n
SA416–SA447
14
SA320–SA351
11
Sector Starting
Address –
Sector Ending
Address
es
13
10
… … … … …
128
Bank
ew
512
Sector Size
(Kbyte)
rN
32
Sector
Count
… … … … …
Bank
Size
(Mbit)
… … … … … …
Table 7.4 S29WS512R Sector and Memory Address Map (Uniform Sectors)
N
ot
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fo
Note
All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
byte address pattern x000000h–x1FFFFh.
Document Number: 002-01101 Rev. *I
Page 15 of 77
S29WS512R
S29WS256R, S29WS128R
Table 7.5 S29WS256R Sector and Memory Address Map (Bottom Boot)
0
SA000
000000h–003FFFh
000000h–007FFFh
SA001
004000h–007FFFh
008000h–00FFFFh
SA002
008000h–00BFFFh
010000h–017FFFh
SA003
00C000h–00FFFFh
018000h–01FFFFh
SA004
010000h–01FFFFh
020000h–03FFFFh
SA018
0F0000h–0FFFFFh
170000h–1FFFFFh
SA019–SA034
100000h–1FFFFFh
200000h–3FFFFFh
2
SA035–SA050
3
SA051–SA066
4
SA067–SA082
5
SA083–SA098
6
SA099–SA114
… … … … … …
SA147–SA162
10
SA163–SA178
11
SA179–SA194
12
SA195–SA210
SA211–SA226
14
SA227–SA242
15
SA243–SA258
1000000h–11FFFFFh
fo
… … … … …
13
es
800000h–8FFFFFh
9
D
SA131–SA146
ew
SA115–SA130
8
Sector Starting
Address –
Sector Ending Address
rN
7
ig
n
…
Notes
1
d
128
Address
Range (byte)
… … … … … …
240
128
Address
Range (word)
1C00000h–1DFFFFFh
F00000h–FFFFFFh
1E00000h–1FFFFFFh
E00000h–EFFFFFh
om
m
en
15
Sector
Range
…
32
16
16
Bank
… … … … …
4
Sector Size
(Kbyte)
de
Sector
Count
…
Bank
Size
(Mbit)
N
ot
R
ec
Note
All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
byte address pattern x000000h–x1FFFFh.
Document Number: 002-01101 Rev. *I
Page 16 of 77
S29WS512R
S29WS256R, S29WS128R
Table 7.6 S29WS256R Sector and Memory Address Map (Top Boot)
Address
Range (byte)
0
SA000–SA015
000000h–0FFFFFh
000000h–1FFFFFh
1
SA016–SA031
100000h–1FFFFFh
200000h–3FFFFFh
2
SA032–SA047
3
SA048–SA063
4
SA064–SA079
5
SA080–SA095
SA112–SA127
… … … … … …
8
SA128–SA143
800000h–8FFFFFh
1000000h–11FFFFFh
… … … … …
9
SA144–SA159
10
SA160–SA175
11
SA176–SA191
12
SA192–SA207
13
SA208–SA223
14
SA224–SA239
E00000h–EFFFFFh
1C00000h–1DFFFFFh
SA240
F00000h–F0FFFFh
1E00000h–1E1FFFFh
es
D
ew
…
FE0000h–FEFFFFh
SA255
FF0000h–FF3FFFh
1FE0000h–1FE7FFFh
SA256
FF4000h–FF7FFFh
1FE8000h–1FEFFFFh
SA257
FF8000h–FFBFFFh
1FF0000h–1FF7FFFh
FFC000h–FFFFFFh
1FF8000h–1FFFFFFh
fo
SA254
om
m
en
32
Sector Starting
Address –
Sector Ending Address
rN
128
SA258
ig
n
SA096–SA111
7
15
4
Notes
6
d
15
Address
Range (word)
… … … … … …
16
Sector
Range
… … … … …
128
Bank
…
240
Sector Size
(Kbyte)
de
Sector
Count
…
Bank
Size
(Mbit)
1FC0000h–1FDFFFFh
N
ot
R
ec
Note
All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
byte address pattern x000000h–x1FFFFh.
Document Number: 002-01101 Rev. *I
Page 17 of 77
S29WS512R
S29WS256R, S29WS128R
Table 7.7 S29WS256R Sector and Memory Address Map (Uniform Boot)
Sector
Range
Address
Range (word)
Address
Range (byte)
0
SA000–SA015
000000h–0FFFFFh
000000h–1FFFFFh
1
SA016–SA031
100000h–1FFFFFh
200000h–3FFFFFh
2
SA032–SA047
3
SA048–SA063
4
SA064–SA079
5
SA080–SA095
SA112–SA127
8
SA128–SA143
800000h–8FFFFFh
1000000h–11FFFFFh
9
SA144–SA159
10
SA160–SA175
11
SA176–SA191
12
SA192–SA207
SA208–SA223
14
SA224–SA239
E00000h–EFFFFFh
1C00000h–1DFFFFFh
15
SA240–SA255
F00000h–FFFFFFh
1E00000h–1FFFFFFh
ew
D
es
13
Sector Starting
Address –
Sector Ending Address
ig
n
SA096–SA111
7
… … … … …
6
… … … … … …
Notes
rN
128
Bank
N
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d
fo
256
Sector Size
(Kbyte)
… … … … … …
16
Sector
Count
… … … … …
Bank
Size
(Mbit)
Document Number: 002-01101 Rev. *I
Page 18 of 77
S29WS512R
S29WS256R, S29WS128R
Table 7.8 S29WS128R Sector and Memory Address Map (Bottom Boot)
SA000
000000h–003FFFh
000000h–007FFFh
SA001
004000h–007FFFh
008000h–00FFFFh
SA002
008000h–00BFFFh
010000h–017FFFh
SA003
00C000h–00FFFFh
018000h–01FFFFh
SA004
010000h–01FFFFh
020000h–03FFFFh
128
070000h–07FFFFh
0E0000h–FFFFFh
080000h–0FFFFFh
100000h–1FFFFFh
2
SA019–SA026
3
SA027–SA034
4
SA035–SA042
5
SA043–SA050
6
SA051–SA058
7
… … … … … …
SA083–SA090
11
SA091–SA098
12
SA099–SA106
SA107–SA114
14
SA115–SA122
15
SA123–SA130
800000h–8FFFFFh
fo
700000h–77FFFFh
780000h–7FFFFFh
… … … … …
13
es
10
D
400000h–47FFFFh
SA075–SA082
ew
SA067–SA074
9
Sector Starting
Address –
Sector Ending
Address
rN
SA059–SA066
8
ig
n
SA010
SA011–SA018
d
128
Notes
1
… … … … … …
120
Address
Range (byte)
…
7
Address
Range (word)
…
0
Sector
Range
…
32
8
8
Bank
… … … … …
4
Sector Size
(Kbyte)
de
Sector
Count
om
m
en
Bank
Size
(Mbit)
E00000h–EFFFFFh
F00000h–FFFFFFh
N
ot
R
ec
Note
All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
byte address pattern x000000h–x1FFFFh.
Document Number: 002-01101 Rev. *I
Page 19 of 77
S29WS512R
S29WS256R, S29WS128R
Address
Range (byte)
0
SA000–SA007
000000h–07FFFFh
000000h–0FFFFFh
1
SA008–SA015
080000h–0FFFFFh
100000h–1FFFFFh
2
SA016–SA023
3
SA024–SA031
4
SA032–SA039
5
SA040–SA047
6
SA048–SA055
7
SA056–SA063
… … … … … …
8
SA064–SA071
400000h–47FFFFh
800000h–8FFFFFh
… … … … …
SA072–SA079
SA080–SA087
11
SA088–SA095
12
SA096–SA103
SA104–SA111
14
SA112–SA119
700000h–77FFFFh
E00000h–EFFFFFh
SA120
780000h–78FFFFh
F00000h–F1FFFFh
15
32
D
ew
7E0000h–7EFFFFh
SA127
7F0000h–7F3FFFh
FE0000h–FE7FFFh
SA128
7F4000h–7F7FFFh
FE8000h–FEFFFFh
SA129
7F8000h–7FBFFFh
FF0000h–FF7FFFh
SA130
…
SA126
om
m
en
4
rN
128
Sector Starting
Address –
Sector Ending
Address
es
13
ig
n
9
10
Notes
fo
7
Address
Range (word)
d
8
Sector
Range
… … … … …
128
Bank
…
120
Sector Size
(Kbyte)
de
Sector
Count
…
Bank
Size
(Mbit)
… … … … … …
Table 7.9 S29WS128R Sector and Memory Address Map (Top Boot)
7FC000h–7FFFFFh
FC0000h–FDFFFFh
FF8000h–FFFFFFh
N
ot
R
ec
Note
All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
byte address pattern x000000h–x1FFFFh.
Document Number: 002-01101 Rev. *I
Page 20 of 77
S29WS512R
S29WS256R, S29WS128R
7.3
Address
Range (word)
Address
Range (byte)
0
SA000–SA007
000000h–07FFFFh
000000h–0FFFFFh
1
SA008–SA015
080000h–0FFFFFh
100000h–1FFFFFh
2
SA016–SA023
3
SA024–SA031
4
SA032–SA039
5
SA040–SA047
6
SA048–SA055
7
SA056–SA063
… … … … … …
8
SA064–SA071
400000h–47FFFFh
800000h–8FFFFFh
9
SA072–SA079
12
SA096–SA103
ig
n
SA088–SA095
Sector Starting
Address –
Sector Ending
Address
es
SA080–SA087
11
Notes
D
10
… … … … …
128
Sector
Range
13
SA104–SA111
14
SA112–SA119
700000h–77FFFFh
E00000h–EFFFFFh
15
SA120–SA127
780000h–7FFFFFh
F00000h–FFFFFFh
ew
128
Bank
rN
Sector Size
(Kbyte)
fo
16
Sector
Count
… … … … …
Bank
Size
(Mbit)
… … … … … …
Table 7.10 S29WS128R Sector and Memory Address Map (Uniform Boot)
Device ID and CFI (ID-CFI)
ot
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om
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en
de
d
There are two traditional methods for systems to identify the type of flash memory installed in the system. One has been traditionally
been called Autoselect and is now referred to as Device Identification (ID). A command is used to enable an address space overlay
where up to 16 word locations can be read to get JEDEC manufacturer identification (ID), device ID, and some configuration and
protection status information from the flash memory. The system can use the manufacturer and device IDs to select the appropriate
driver software to use with the flash device. The other method is called Common Flash Interface (CFI). It also uses a command to
enable an address space overlay where an extendable table of standard information about how the flash memory is organized and
behaves can be read. With this method the driver software does not have to be written with the specifics of each possible memory
device in mind. Instead the driver software is written in a more general way to handle many different devices but adjusts the driver
behavior based on the information in the CFI table stored in the flash memory. Traditionally these two address spaces have used
separate commands and were separate overlays. However, the mapping of these two address spaces are now non-overlapping and
so can be combined in to a single address space and appear together in a single overlay. Either of the traditional commands used to
access enter the Autoselect (ID) or CFI overlay will cause the now combined ID-CFI address map to appear.
N
A write at any sector address, in bank zero, having the least significant byte address value of AAh, with xx98h or xx90h data,
switches the addressed sector to an overlay of the ID-CFI address map. These are called ID-CFI Enter commands and are only valid
when written to the specified bank when it is in read mode. The ID-CFI address map appears within, and replaces flash array data
of, the selected sector address range. The ID-CFI enter commands use the same address and data values used on previous
generation memories to access the JEDEC Manufacturer ID (Autoselect) and Common Flash Interface (CFI) information,
respectively. While the ID-CFI address space is overlaid, any write with xxF0h data to the device will exit the overlay and return the
selected sector to showing flash memory array data. Thus, the ID-CFI address space and commands are backward compatible with
standard memory discovery algorithms.
Within the ID-CFI address map there are two subsections:
Table 7.11 ID-CFI Address Map Overview
Byte Address
Description
Size Allocated (Bytes)
Read/Write
(SA) + 00000h to 0001Fh
JEDEC ID
(traditional Autoselect values)
32
Read Only
(SA) + 00020h to CEh
CFI data structure
174
Read Only
For the complete address map in Device ID and Common Flash Memory Interface Address Map on page 65.
Document Number: 002-01101 Rev. *I
Page 21 of 77
S29WS512R
S29WS256R, S29WS128R
7.3.1
JEDEC Device ID
The Joint Electron Device Engineering Council (JEDEC) standard JEP106x defines a method for reading the manufacturer ID and
device ID of a compliant memory. This information is primarily intended for programming equipment to automatically match a device
with the corresponding programming algorithm.
The JEDEC ID information is structured to work with any memory data bus width (e.g. x8, x16, x32). The Query addressing is always
relative to the device word (largest supported) with data always presented on the lowest order byte (D7 - D0 outputs). Because the
data bus is word wide each code byte is located in the lower half of each word location and the high order byte is always zero.
7.3.2
Common Flash Memory Interface
ig
n
The Common Flash Interface (CFI) specification defines a standardized data structure that may be read from a flash memory
device, which allows vendor-specified software algorithms to be used for entire families of devices. The data structure contains
information for system configuration such as various electrical and timing parameters, and special functions supported by the
device. Software support can then be device-independent, JEDEC ID-independent, and forward-and-backward-compatible for the
specified flash device families.
D
es
The system can read CFI information at the addresses within the selected sector as shown in Section 12.2, Device ID and Common
Flash Memory Interface Address Map on page 65.
rN
ew
Like the JEDEC Device ID information, CFI information is structured to work with any memory data bus width (e.g. x8, x16, x32). The
Query addressing is always relative to the device word (largest supported) with data always presented on the lowest order byte (D7
- D0 outputs). Because the data bus is word wide each code byte is located in the lower half of each word location and the high order
byte is always zero.
Secure Silicon Region
de
7.3.3
d
fo
For further information, please refer to the Spansion CFI Version 1.4 (or later) Specification and the Spansion CFI Publication 100
(see also JEDEC publications JEP137-A and JESD68.01). Please contact JEDEC (http://www.jedec.org) for their standards.
om
m
en
The Secure Silicon Region (SSR) provides an extra flash memory area that can be programmed once and permanently protected
from further changes. The SSR is 512 bytes in length. It consists of 256 bytes for factory data and 256 bytes for customer-secured
data.
The SSR is overlaid in the sector address specified by the SSR enter command.
ec
Table 7.12 Secure Silicon Region
R
Byte Address Range
(SA) + 0000h to 00FFh
7.3.4
Size
Factory
256 Bytes
Customer
256 Bytes
N
ot
(SA) + 0100h to 01FFh
Secure Silicon Region
Configuration Register
The Configuration Register Enter command is only valid when written to a bank that is in Read mode. The configuration register
mode address map appears within, and replaces flash array data of, the selected sector address range. The meaning of the
configuration register bits is defined in Configuration Register on page 29. In configuration register mode a write of 00F0h to any
address will return the sector to Standard Read mode.
Document Number: 002-01101 Rev. *I
Page 22 of 77
S29WS512R
S29WS256R, S29WS128R
8. Device Operations
This section describes the read and write bus operations, program, erase, simultaneous read/write, handshaking, and reset features
of the flash devices.
The address space of the Flash Memory Array is divided into banks. There are three operation modes for each bank:
Read Mode
Embedded Algorithm (EA) Mode
Address Space Overlay (ASO) Mode
Each bank of the device can be in any operation mode but, only one bank can be in EA or ASO mode at any one time.
ig
n
In Read Mode a Flash Memory Array bank may be read by simply selecting the memory, supplying the address, and taking read
data when it is ready. This is done by asynchronous or burst accesses from the host system bus. The CU puts all banks in Read
mode during Power-on, a Hardware Reset, after a Command Reset, or after a bank is returned to Read mode from EA mode.
es
During a burst read access valid read data is indicated by the RDY signal being High. When RDY is Low burst read data is not valid
and wait states must be added. The use of the RDY signal to indicate when valid data is transferred on the system data bus is called
handshaking or flow control.
rN
ew
D
EA and ASO modes are initiated by writing specific address and data patterns into command registers (see Table 12.1 on page 63).
The command registers do not occupy any memory locations; they are loaded by write bus cycles with the address and data
information needed to execute a command. The contents of the registers serve as input to the Control Unit (CU) and the CU dictates
the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device
in an unknown state, in which case the system must write the reset command to return all banks to Read mode.
om
m
en
de
d
fo
The flash memory array data in a bank that is in EA mode, is stable but undefined, and effectively unavailable for read access from
the host system. While in EA mode the bank is used by the CU in the execution of commands. Typical command operations are
programming or erasing of data in the flash array. All other banks are available for read access while the one bank is in EA mode.
This ability to read from one bank while another bank is used in the execution of a command is called Simultaneous Read and Write
(SRW) and allows for continued operation of the system via the reading of data or code from other banks while one bank is
programming or erasing data as a relatively long time frame background task. Only a status register read command can be used in
a bank in EA mode to retrieve the EA status.
ec
While any one of the overlay address spaces are overlaid in a bank (entered) that bank is in ASO mode and no other bank may be
in EA or ASO mode. All EA activity must be completed or suspended before entering any ASO mode. A command for entering an EA
or ASO mode while another bank is in EA or ASO mode will be ignored.
ot
R
While an ASO mode is active (entered) in a bank, a read for flash array data to any other bank is allowed. ASO mode selects a
specific sector for the overlaid address space. Other sectors in the ASO bank still provide flash array data and may be read during
ASO mode.
N
While SSR Lock, SSR, or Configuration Register is overlaid only the SSR Lock, SSR, or Configuration Register respectively may be
programmed in the overlaid sector. While any of these ASO areas are being programmed the ASO bank switches to EA mode. The
ID/CFI and factory portion of the SSR ASO is not customer programmable. An attempt to program in these areas will fail.
Document Number: 002-01101 Rev. *I
Page 23 of 77
S29WS512R
S29WS256R, S29WS128R
8.1
Device Bus Operations
The Device Bus Operations table describes the required state of each control pin for any particular bus operation. The Control Unit
(CU) is set to the idle state for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power transition.
Table 8.1 Device Bus Operations
Operation
CE#
OE#
WE#
CLK
AVD#
Addresses
Data
RDY
RESET#
Addr In
High-Z
H
H
Asynchronous Operations
L
H
H
X
Asynchronous Read AVD# Steady State
L
L
H
X
L
Addr In
Output
Valid
H
H
Asynchronous Read - Data on bus
L
L
H
X
H
X
Output
Valid
H
H
Asynchronous Write (AVD# Latched
Addresses)
L
H
L
X
Addr In
X
Asynchronous Write (WE# Latched Data)
L
H
H
X
Input
Valid
Standby (CE#)
H
X
X
X
X
X
Hardware Reset
X
X
X
X
X
X
High-Z
High-Z
H
High-Z
High-Z
Addr In
Output
Invalid
X
H
L
H
H
X
Output
Valid
H
H
Terminate current Burst read cycle
H
X
X
Terminate current Burst read cycle
through RESET#
X
X
X
High-Z
High-Z
H
X
X
X
X
X
X
High-Z
High-Z
L
Terminate current Burst read cycle
and start new Burst read cycle
L
H
H
L
Addr In
Output
Invalid
X
H
= rising edge,
ew
= high to low.
Asynchronous Read
N
8.2
ot
R
ec
Legend
L = Logic 0, H = Logic 1, X = can be either VIL or VIH.,
rN
fo
L
d
Advance Burst read to next address
L
de
H
om
m
en
H
es
H
Synchronous Operations
L
H
H
Non-Operations
Latch Starting Burst Address by CLK
H
D
X
ig
n
Asynchronous Read - Addresses Latched
To read data from the memory array, the system must first assert a valid address while driving AVD# and CE# to VIL. WE# must
remain at VIH. CLK may toggle or remain at VIL or VIH. The rising edge of AVD# will latch the address. The data appears on DQ15–
DQ0 when CE# is Low, OE# is Low, AVD# is High, and the asynchronous access times are satisfied.
In order to use Asynchronous Read Mode the configuration register bit 15 must be set to 1.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the
delay from stable CE# to valid data at the outputs. See 11.9.2, AC Characteristics–Asynchronous Read on page 53.
Document Number: 002-01101 Rev. *I
Page 24 of 77
S29WS512R
S29WS256R, S29WS128R
8.3
Page Mode Read
The device is capable of fast page mode read. This mode provides random read access speed for locations within a page. Address
bits Amax–A3 select a 8-word page, and address bits A2 – A0 select a specific word within that page. This is an asynchronous
operation with the microprocessor supplying the specific word location.
The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified falls within
that page) is equivalent to tPACC. When CE# is deasserted (=VIH), the re-assertion of CE# for subsequent access has access time of
tACC or tCE. See Figure 11.13 on page 55.
Table 8.2 Word Select
A2
A1
A0
0
0
0
0
0
1
0
1
0
Word 5
1
0
Word 6
1
1
Word 7
1
1
1
0
es
1
0
1
D
0
1
ew
Word 3
Word 4
ig
n
Word 1
Word 2
0
1
rN
8.4
Word
Word 0
Synchronous (Burst) Read Mode and Configuration Register
fo
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
d
In order to use Synchronous (Burst) Read Mode the configuration register bit 15 must be set to 0.
om
m
en
de
Prior to entering burst mode, the system should determine how many wait states are needed for the initial word of each burst access
(see table below), what mode of burst operation is desired, how the RDY signal transitions with valid data, and output drive strength.
The system would then write the configuration register command sequence. See Configuration Register on page 29 for further
details.
R
ec
When the appropriate number of initial Wait States have occurred, data is output after the rising edge of the CLK. Subsequent
words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address
counter. RDY indicates the initial latency and any subsequent wait states. The device has 3 burst options: Continuous Burst, 16Word Burst with Wrap Around, and 8-Word Burst with Wrap Around. If the device is operated in Continuous Burst mode or 16-word
Burst mode,
N
ot
The device has 3 burst options: Continuous Burst, 16-Word Burst with Wrap Around, and 8-Word Burst with Wrap Around. If the
device is operated in Continuous Burst mode or 16-word Burst mode, 0 to 7 wait states may be inserted at 8 word boundary
crossings. Wait states are inserted between the last word below the boundary and the first word above the boundary. The number of
wait states inserted are based on the initial address and the initial number of wait states. See the Address Latency tables for the
number of wait states inserted.
The device also has a fixed internal address boundary that occurs every 128 words (256 Bytes). When a 128 word boundary is
crossed, 0 to 2 additional wait states are inserted. The 128-word boundary can only be crossed when the device is operated in
continuous burst mode. See Table 8.1 on page 24 for the number of wait states inserted at the 128-word boundary.
The following table shows the number of initial wait states needed at different burst frequencies.
Document Number: 002-01101 Rev. *I
Page 25 of 77
S29WS512R
S29WS256R, S29WS128R
Table 8.3 Initial Wait States vs. Frequency
Frequency
Wait State Requirement
Frequency 27 MHz
3
27 MHz < Frequency 40 MHz
4
40 MHz < Frequency 54 MHz
5
54 MHz < Frequency 66 MHz
6
66 MHz < Frequency 79 MHz
7
79 MHz < Frequency 95 MHz
8
95 MHz < Frequency 104 MHz
9
104 MHz < Frequency 120 MHz
10
ig
n
The following tables show the address related latency (note that ws = wait state).
Wait States Inserted at 8 Word (16 byte) Boundaries After Initial Wait States
D1
D2
D3
D4
1
D1
D2
D3
D4
D5
2
D2
D3
D4
D5
D6
D7
D5
D6
D6
D7
5
D5
D6
D7
6
D6
D7
7
D7
D6
de
D6
D7
D7
1 ws
D7
fo
D4
D5
d
D3
D4
8 to 13 wait
states
2 ws
D8
D8
D8
3 ws
D8
4 ws
D8
5 ws
D8
6 ws
D8
7 ws
om
m
en
3
D5
rN
D0
4
D
Initial Wait
0
ew
Word
es
Table 8.4 Address Latency for 8 to13 Wait States
D8
Table 8.5 Address Latency for 7 Wait States
Word
Initial Wait
Wait States Inserted at 8 Word (16 byte) Boundaries After Initial Wait States
D0
D1
1
D1
D2
2
D2
D3
4
D4
D5
6
N
5
D3
7
D7
D6
D4
D5
D6
D7
D4
D5
D6
D7
0 ws
D4
D5
D6
D7
D4
D5
D6
D7
D5
D6
D7
D6
D7
R
7 wait
states
D3
D3
ot
3
D2
ec
0
1 ws
D8
D8
2 ws
D8
3 ws
D8
4 ws
D7
D8
D8
5 ws
D8
6 ws
D8
Table 8.6 Address Latency for 6 Wait States
Word
Initial Wait
Wait States Inserted at 8 Word (16 byte) Boundaries After Initial Wait States
0
D0
D1
D2
D3
D4
D5
D6
1
D1
D2
D3
D4
D5
D6
D7
2
D2
D3
D4
D5
D6
D7
D7
3
D3
D4
D5
D6
D4
D5
D6
D7
5
D5
D6
D7
6
D6
D7
7
D7
4
6 wait
states
Document Number: 002-01101 Rev. *I
1 ws
3 ws
5 ws
0 ws
0 ws
2 ws
4 ws
D7
D8
D8
D8
D8
D8
D8
D8
D8
Page 26 of 77
S29WS512R
S29WS256R, S29WS128R
Table 8.7 Address Latency for 5 Wait States
Word
Initial Wait
Wait States Inserted at 8 Word (16 byte) Boundaries After Initial Wait States
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
0 ws
D8
D2
D3
D4
D5
D6
D7
D3
D4
D5
D6
D7
D7
2
3
D4
D5
D6
5
D5
D6
D7
6
D6
D7
7
D7
0 ws
1 ws
D8
3 ws
D8
D8
D3
D4
D5
1
D1
D2
D3
D4
D5
D6
2
D2
D3
D4
D5
D6
D7
D7
D4
D5
D6
D5
D6
D7
5
D5
D6
D7
6
D6
D7
7
D7
0 ws
D8
0 ws
D8
fo
D8
D8
D8
de
d
D1
D2
2
D2
D3
D2
D3
D4
D5
D6
D7
D3
D4
D5
D6
D7
0 ws
D4
D5
D6
D7
D7
D3
D6
D5
D4
D6
D7
5
D5
D6
D7
6
D6
N
ot
D5
D4
R
ec
1
7
D8
Wait States Inserted at 8 Word (16 byte) Boundaries After Initial Wait States
D1
3 wait
states
D8
D8
1 ws
om
m
en
Initial Wait
D0
3
0 ws
0 ws
3 ws
0
4
D7
D7
2 ws
Table 8.9 Address Latency for 3 Wait States
Word
rN
D3
D4
4 wait
states
D6
ew
D2
es
Wait States Inserted at 8 Word (16 byte) Boundaries After Initial Wait States
D1
D
Initial Wait
D0
3
D8
4 ws
0
4
D8
2 ws
Table 8.8 Address Latency for 4 Wait States
Word
D8
0 ws
ig
n
4
5 wait
states
0 ws
0 ws
0 ws
D7
D7
0 ws
D8
D8
D8
D8
D8
D8
1 ws
D8
2 ws
D8
Table 8.10 256 Byte Boundary Crossing Latency - Additional Wait States
Initial Wait States
Boundary Crossing Latency
3
4
5
6
0 ws
7
8
9
1 ws
10 to 13
2 ws
Document Number: 002-01101 Rev. *I
Page 27 of 77
S29WS512R
S29WS256R, S29WS128R
8.4.1
Continuous Burst
The device continues to output sequential burst data from the memory array, wrapping around to address 0000000h after it reaches
the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new
address. See Table 8.1, Device Bus Operations on page 24.
If the host system crosses a bank boundary while reading in burst mode, and the subsequent bank is not programming or erasing,
an address boundary crossing latency is required. If the host system crosses the bank boundary while the subsequent bank is
programming or erasing, continuous burst halts (RDY will be disabled and data will continue to be driven).
8.4.2
8-, 16-Word Linear Burst with Wrap Around
ig
n
Table 8.11 Burst Address Groups
Group Size
16 bytes
Group Byte Address Ranges
0-Fh, 10-1Fh, 20-2Fh,...
16-word
32 bytes
0-1Fh, 20-3Fh, 30-4Fh,...
D
es
Mode
8-word
rN
ew
The remaining two modes are fixed length linear burst with wrap around, in which a fixed number of words are read from consecutive
addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls.
The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 8.11).
N
ot
R
ec
om
m
en
de
d
fo
As an example: if the starting address in the 8-word mode is system byte address 3Ch, the address range to be read would be byte
address 30-3Fh, and the burst sequence would be 3C-3E-30-32-34-36-38-3Ah. The burst sequence begins with the starting address
written to the device, wraps back to the first address in the selected group, and outputs a maximum of 8 words. No additional wait
states will be required within the 8-word burst. The 8th word will continue to be driven until the burst operation is aborted (CE# goes
to VIH, a new address is latched in for a new burst operation, or a hardware reset). In a similar fashion, the 16-word Linear Wrap
modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the
selected address group. Additional wait states could be added the first time the device crosses from one to the other group of 8
words in a 16-word burst. The number will depend on the starting address and the wait state set within the configuration register.
See Table 8.4 on page 26 to Table 8.9 on page 27. Note that in these two burst read modes the address pointer does not
cross the boundary that occurs every 128 words; thus, no address boundary crossing wait states are inserted for linear
burst with wrap.
Document Number: 002-01101 Rev. *I
Page 28 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 8.1 Synchronous Read
Load Initial Address
Address = RA
RA = Read Address
Wait Programmable
Wait State Setting
CR0.14 - CR0.11 sets initial access time
(from address latched to
valid data) from 3 to 13 clock cycles
Read Initial Data
RD = DQ[15:0]
RD = Read Data
es
ig
n
Wait X Clocks (if required):
Additional Latency Due to Starting
Address and Clock Frequency
ew
D
Read Next Data
RD = DQ[15:0]
No
End of Data?
de
d
Yes
fo
Crossing
Boundary?
(Note 1)
Yes
rN
No
om
m
en
Completed
Note
1. Required only if device is performing a Continuous Burst operation.
8.4.3
Configuration Register
N
ot
R
ec
Configuration register (CR) sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the
device defaults to the idle state, and the configuration register settings are in their default state. The host system should determine
the proper settings for the configuration register, and then execute the Set Configuration Register command sequence, before
attempting burst operations. The Configuration Register can also be read using a command sequence (see Table 12.1 on page 63).
The table below describes the register settings and indicates the default state of each bit after power-on or a hardware reset. The
configuration register bits are not affected by a command reset.
Document Number: 002-01101 Rev. *I
Page 29 of 77
S29WS512R
S29WS256R, S29WS128R
Table 8.12 Configuration Register
CR BIt
CR.15
Function
Settings (Binary)
0 = Synchronous Read Mode
Device Read Mode
1 = Asynchronous Read Mode (Default)
0000 = Reserved
0001 =
3rd
0010 =
4th
0011 =
CR.14
CR.13
CR.12
..
.
Programmable
Read Wait States
..
.
13th
(Default)
1011 =
CR.11
rising CLK edge after
addresses are latched
5th
Initial data is valid on the
ig
n
1100 = Reserved
1101 = Reserved
es
1110 = Reserved
RDY Polarity
CR.9
Reserved
CR.8
RDY Timing
CR.7
Output Drive Strength
CR.6
Reserved
CR.5
Reserved
CR.4
Reserved
CR.3
Reserved
1 = RDY signal is active high (Default)
rN
0 = Reserved
1 = Reserved (Default)
fo
0 = RDY active one clock cycle before data
1 = RDY active with data (Default)
de
d
0 = Full Drive= Current Driver Strength (Default)
1 = Half Drive
om
m
en
0 = Reserved
1 = Reserved (Default)
0 = Reserved (Default)
1 = Reserved
0 = Reserved (Default)
ec
1 = Reserved
R
0 = Reserved
1 = Reserved (Default)
ot
000 = Continuous (Default)
010 = 8-Word (16-Byte) Linear Burst with wrap around
N
CR.1
ew
0 = RDY signal is active low
CR.10
CR.2
D
1111 = Reserved
Burst Length
011 = 16-Word (32-Byte) Linear Burst with wrap around
CR.0
(All other bit settings are reserved)
8.4.3.1
Device Read Mode
Configuration Register bit 15 (CR.15) controls whether read accesses via the bus interface are in asynchronous or burst mode.
Asynchronous mode is the default after power-on or hardware reset. Write accesses are always conducted with asynchronous mode
timing, independent of the read mode.
8.4.3.2
Wait States
Configuration Register bits 14 to 11 (CR.[14..11]) define the number of CLK cycles after the AVD# Low cycle that captures the initial
address until the device presents valid data on the data bus. The bits from 14 to 11 are in most to least significant order.
When the corresponding number of Wait States have occurred, data is presented on the data bus after the rising edge of the CLK.
Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal
address counter. Prior to setting the device into synchronous read mode, the system should set CR[14..11] according to the CLK
frequency. Appropriate settings are indicated in Table 8.3 on page 26
Document Number: 002-01101 Rev. *I
Page 30 of 77
S29WS512R
S29WS256R, S29WS128R
8.4.3.3
RDY Polarity
Configuration Register bit 10 (CR.10) controls whether the RDY signal indicates valid data when High or when Low. When this bit is
zero the RDY signal indicates data is valid when the signal is Low. When this bit is one the RDY signal indicates data is valid when
the signal is High. The default for this bit is set to one after power-on or a hardware reset.
8.4.3.4
RDY Timing
Configuration Register bit 8 (CR.8) controls whether the RDY signal indicates valid data on the same cycle that data is valid or one
cycle before data is valid. When this bit is zero, the RDY signal indicates data is valid in the same cycle the data is valid. When this
bit is one the RDY signal indicates data is valid one cycle before data is valid. The default for this bit is set to one after power-on or a
hardware reset.
8.4.3.5
Output Drive Strength
Burst Length
D
8.4.3.6
es
ig
n
Configuration Register bit 7 (CR.7) controls whether the data outputs drive with full or half strength. When this bit is zero the data
outputs drive with full strength. When this bit is one the data outputs drive with half strength. The default for this bit is cleared to zero
after power-on or a hardware reset.
Status Register
fo
8.5
rN
ew
Configuration Register bits 2 to 0 (CR.[2..0]) define the length of burst read and write accesses. The bits from 2 to 0 are in most to
least significant order. See Table 8.13 for code meaning & default value.
Table 8.13 Status Register Reset State
Device Ready
Bit.
Overall status
Bit 6
Bit 5
Erase Suspend
Status Bit
Erase Status
Bit
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Program Status
Bit
RFU
Program
Suspend
Status Bit
Sector Lock
Status Bit
Bank Status Bit
ec
Bit 7
om
m
en
de
d
The status of program and erase operations is provided by a single 16 bit status register. The status register read command is
written followed by a read of the status register for each access of the status register information. The status register can be read in
synchronous or asynchronous bus access mode. If read in synchronous (burst) mode for more than access cycle the same status
results will appear in each of the read cycles of the burst access until the burst is terminated.
ESSB
ESB
0 at Reset
0 at Reset
PSB
RFU
PSSB
SLSB
BSB
0 at Reset
0 at Reset
0 at Reset
0 at Reset
0 at Reset
ot
R
DRB
1 at Reset
N
Notes
1. Status bits 15 to 8 always return the current progress code.
2. Bit 7 reflects the device status.
3. If the device is busy, Bit 0 is used to check whether the addressed bank is busy or some other bank is busy.
4. All the other bits reflect the status of the device.
Document Number: 002-01101 Rev. *I
Page 31 of 77
S29WS512R
S29WS256R, S29WS128R
Table 8.14 Status Register - Bit 7
Bit 7
Device Ready
Bit.
Overall status
DRB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sector Lock
Status Bit
Bank Status Bit
Erase Suspend
Status Bit
Erase Status
Bit
Program Status
Bit
RFU
Program
Suspend
Status Bit
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
0
Device busy
programming
or erasing
1
Device ready
ig
n
Notes
1. Bit 7 is set when there is no erase or program operation in progress in the device.
Bits 6:1 only
valid when Bit
7=1
1
Bit 6:1 only
valid when Bit
7=1
Erase Suspend
Status Bit
Erase Status
Bit
Program Status
Bit
RFU
Program
Suspend
Status Bit
ESSB
ESB
PSB
RFU
X
X
X
X
X
0
No Erase in
Suspension
1
Erase in
Suspension
Bit 1
Bit 0
Sector Lock
Status Bit
Bank Status Bit
SLSB
BSB
X
X
X
X
X
X
D
Bit 2
ew
Bit 3
PSSB
fo
1
Bit 4
d
DRB
Bit 5
de
Overall status
Bit 6
X
om
m
en
Bit 7
Device Ready
Bit.
rN
Table 8.15 Status Register - Bit 6
es
2. Bits 1 through 6 are valid if and only if Bit 7 is set.
Notes
1. Upon issuing the “Erase Suspend” Command, the user must continue to read status until DRB becomes 1 before accessing another sector within the same bank.
R
Table 8.16 Status Register - Bit 5
ec
2. Cleared by “Erase Resume” Command.
Overall status
DRB
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Erase Status
Bit
Program Status
Bit
RFU
Program
Suspend
Status Bit
Sector Lock
Status Bit
Bank Status Bit
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
X
Erase
successful
X
X
X
X
X
X
X
X
X
X
Erase Suspend
Status Bit
1
Bits 6:1 only
valid when Bit
7=1
ot
Device Ready
Bit.
Bit 6
N
Bit 7
0
1
Bit 6:1 only
valid when Bit
7=1
X
1
Erase error
Notes
1. ESB bit reflects “success” or “failure” of the most recent erase operation.
2. Cleared by “Clear Status Register” Command as well as by hardware reset.
Document Number: 002-01101 Rev. *I
Page 32 of 77
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S29WS256R, S29WS128R
Table 8.17 Status Register - Bit 4
Bit 7
Device Ready
Bit.
Overall status
DRB
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Sector Lock
Status Bit
Bank Status Bit
Erase Suspend
Status Bit
Erase Status
Bit
Program Status
Bit
RFU
Program
Suspend
Status Bit
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
X
X
Program
successful
X
X
X
X
X
X
X
X
X
X
1
Bits 6:1 only
valid when Bit
7=1
Bit 3
0
1
Program fail
ig
n
1
Bit 6:1 only
valid when Bit
7=1
es
Notes
1. PSB bit reflects “success” or “failure” of the most recent program operation.
2. Cleared by “Clear Status Register” Command as well as by hardware reset.
Overall status
DRB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Erase Suspend
Status Bit
Erase Status
Bit
Program Status
Bit
RFU
Program
Suspend
Status Bit
Sector Lock
Status Bit
Bank Status Bit
ESSB
ESB
PSB
RFU
PSSB
SLSB
BSB
X
X
X
X
X
X
X
de
om
m
en
Bits 6:1 only
valid when Bit
7=1
d
1
ew
Bit 5
rN
Device Ready
Bit.
Bit 6
fo
Bit 7
D
Table 8.18 Status Register - Bit 3
Notes
1. This Register is reserved for future use.
2. Cleared by “Clear Status Register” Command as well as by hardware reset.
DRB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Erase Suspend
Status Bit
Erase Status
Bit
Program Status
Bit
RFU
Program
Suspend
Status Bit
Sector Lock
Status Bit
Bank Status Bit
ESB
PSB
RFU
PSSB
SLSB
BSB
X
X
X
X
No Program in
suspension
X
X
X
X
X
X
Program in
suspension
X
X
ESSB
R
Bit 5
ot
Overall status
Bit 6
N
Bit 7
Device Ready
Bit.
ec
Table 8.19 Status Register - Bit 2
1
Bits 6:1 only
valid when Bit
7=1
0
1
Bit 6:1 only
valid when Bit
7=1
1
Notes
1. Upon issuing the “Program Suspend” Command, the user must continue to read status until DRB becomes 1 before accessing another sector within the same bank.
2. Cleared by “Program Resume” Command.
Document Number: 002-01101 Rev. *I
Page 33 of 77
S29WS512R
S29WS256R, S29WS128R
Table 8.20 Status Register - Bit 1
Bit 7
Bit 6
Device Ready
Bit.
Overall status
DRB
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sector Lock
Status Bit
Bank Status Bit
BSB
Erase Suspend
Status Bit
Erase Status
Bit
Program Status
Bit
RFU
Program
Suspend
Status Bit
ESSB
ESB
PSB
RFU
PSSB
SLSB
X
X
X
X
X
Sector not
locked during
operation
X
X
X
X
X
Sector locked
error
1
0
Bits 6:1 only
valid when Bit
7=1
1
1
X
ig
n
Bit 6:1 only
valid when Bit
7=1
X
es
Notes
1. SLSB indicates that a program or erase operation failed to program or erase because the sector was locked or the operation was attempted on the protected Secure
Silicon Region.
D
2. SLSB reflects the status of the most recent program or erase operation.
3. SLSB is cleared by “Clear Status Register” or by hardware reset.
DRB
Bit 3
Erase Suspend
Status Bit
Erase Status
Bit
Program Status
Bit
RFU
ESSB
ESB
PSB
RFU
0
X
X
X
X
X
1
Sector Lock
Status Bit
Bank Status Bit
PSSB
SLSB
BSB
X
0
X
X
1
X
X
X
X
X
X
X
No active
Program or
Erase op.
X
X
X
X
X
X
X
X
Program or
Erase op. in
addressed
Bank
Program or
Erase op. in
other Bank
0
N
1
Bit 6:1 only
valid when Bit
7=1
Program
Suspend
Status Bit
ot
Bit 6:1 only
valid when Bit
7=1
Bit 0
ec
X
R
0
Bits 6:1 only
valid when Bit
7=1
Bit 1
om
m
en
Bits 6:1 only
valid when Bit
7=1
Bit 2
rN
Bit 4
fo
Bit 5
d
Overall status
Bit 6
de
Bit 7
Device Ready
Bit.
ew
Table 8.21 Status Register - Bit 0
1
invalid
Notes
BSB is used to check if a program or erase operation in progress in the current bank.
8.6
Blank Check
The Blank Check command will confirm if the selected sector is erased.
The Blank Check command does not allow for reads to the array during the Blank Check. Reads to the array while this command is
executing will return unknown data.
Blank Check is only functional in Asynchronous Read mode (Configuration Register - CR[15] = 1).
To initiate a Blank Check on Sector X, write 33h to address AAAh in Sector X. while the device is in the Idle state (not
during program suspend, not during erase suspend,...).
Document Number: 002-01101 Rev. *I
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S29WS256R, S29WS128R
The Blank Check command may not be written while the device is actively programming or erasing. Blank Check does not
support simultaneous operations.
Use the Status Register read to confirm if the device is still busy and when compete if the sector is blank or not.
Bit 5 of the Status Register will be cleared to zero if the sector is erased and set to one if not erased.
Bit 7 & Bit 0 of the Status Register will show if the device is performing a Blank Check (similar to an erase operation).
As soon as any bit is found to not be erased, the device will halt the operation and report the results.
Once the Blank Check is completed, the device will to return to the Idle State.
8.7
Simultaneous Read/Write
Writing Commands/Command Sequences
ew
8.8
D
es
ig
n
The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing
another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank
(note: programming to the sector being erased is not allowed). Figure 11.19, Back-to-Back Read/Write Cycle Timings on page 61
shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics
on page 48 table for read-while-program and read-while-erase current specification.
om
m
en
de
d
fo
rN
The device accepts Asynchronous write bus operations. During an asynchronous write bus operation, the system must drive CE#
and WE# to VIL and OE# to VIH when providing an address and data. When latching an address, AVD# must be driven to VIL.
Addresses are latched on the rising edge of AVD#, while data is latched on the rising edge of WE#. See the Table 8.1, Device Bus
Operations on page 24 for the signal combinations that define each phase of a write bus operation to the device. Each write is a
command or part of a command sequence to the device. The address provided in each write operation may be a bit pattern used to
help identify the write as a command to the device. The upper portion of the address may also select the bank or sector the
command operation is to be performed. A Bank Address (BA) is the set of address bits required to uniquely select a bank. Similarly,
a Sector Address (SA) is the address bits required to uniquely select a sector. The data in each write identifies the command
operation to be performed or supplies information needed to perform the operation. See Table 12.1, Command Definitions
on page 63 for a listing of the commands accepted by the device. ICC2 in DC Characteristics on page 48 represents the active
current specification for a write (Embedded Algorithm) operation.
Program/Erase Operations
ec
8.9
ot
R
For all program and/or erase operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and
OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or
programming data.
N
Addresses are latched on the rising edge of AVD# during asynchronous writes. Data is latched on the rising edge of WE# during
asynchronous writes.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the calling routing (Erase Suspend, SSR Lock,
Secure Silicon Region, or Idle State).
The system can determine the status of the program operation by reading the Status Register. Refer to Status Register
on page 31 for information on these status bits.
A 0 cannot be programmed back to a 1. A succeeding read shows that the data is still 0. Only erase operations can convert
a 0 to a 1.
old data
new data
results
0011
0101
0001
Any commands written to the device during the Embedded Program Algorithm are ignored except the Reads from the nonProgramming Bank, Program Suspend, and Status Read command. Any commands written to the device during the
Embedded Erase Algorithm are ignored except Reads from the non-Erasing Bank, Erase Suspend and Status Read
command.
Document Number: 002-01101 Rev. *I
Page 35 of 77
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S29WS256R, S29WS128R
8.9.1
A hardware reset immediately terminates the program/erase operation and the program command sequence should be
reinitiated once the device has returned to the idle state, to ensure data integrity.
Write Buffer Programming
Write Buffer Programming allows the system to write 1 to 32 words in one programming operation. The Write Buffer Programming
command sequence is initiated by first writing the Write Buffer Load command written at the Sector Address + AAAh in which
programming occurs. Next, the system writes the number of word locations minus 1 at the Sector Address + 555h. This tells the
device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash command.
The Sector Address must match during the Write Buffer Load command and during the Write Word Count command and the Sector
must be unlocked or the operation will abort and return to the initiating state.
ig
n
The write buffer is used to program data within a 64 byte page aligned on a 64 byte boundary.Thus, a full page Write Buffer
programming operation must be aligned on a page boundary. Programming operations of less than a full page may start on any
word boundary but may not cross a page boundary.
ew
D
es
The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed,
and selects the write-buffer-page address. The Sector address must match the Write Buffer Load Sector Address or the operation
will abort and return to the initiating state. All subsequent address/data pairs must be in sequential order. All write buffer addresses
must be within the same page. If the system attempts to load data outside this range, the operation aborts after the Write to Buffer
command is executed and the device will indicate a Program Fail in the Status Register at bit location 4 (PSB). A “Clear Status
Register” must be issued to clear the PSB status bit.
rN
The counter decrements for each data load operation.
om
m
en
de
d
fo
Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash
command at the Sector Address + AAAh. The device then goes busy. The Embedded Program algorithm automatically programs
and verifies the data for the correct data pattern. The system is not required to provide any controls or timings during these
operations. If the incorrect number of write buffer locations have been loaded and the Program Buffer to Flash command is issued,
the Status Register will indicate a program fail at bit location 4 (PSB). A “Clear Status Register” must be issued to clear the PSB
status bit.
The write-buffer embedded programming operation can be suspended using the Program Suspend command. When the Embedded
Program algorithm is complete, the device then returns to Erase Suspend, SSR Lock, Secure Silicon Region, or Idle state. The
system can determine the status of the program operation by reading the Status Register. Refer to Status Register on page 31 for
information on these status bits.
ec
The Write Buffer Programming Sequence will be Aborted under the following conditions:
Load a value greater than the buffer size during the Number of Locations step.
Write an address that is outside the Page of the Starting Address during the write buffer data loading stage of the operation.
Or, have a sector address not matching the one used in the initial command cycle of the write buffer operation.
The sector to be programmed is locked.
The Program Buffer to flash command is not issued after the Write Word Count number of data words is loaded.
N
ot
R
When any of the conditions that cause an abort of write buffer command occur the abort is immediate and will indicate a Program
Fail in the Status Register at bit location 4 (PSB). The next successful program operation will clear the failure status or a “Clear
Status Register” may be issued to clear the PSB status bit.
The Write Buffer Programming Sequence can be stopped and reset by the following: Hardware Reset or Power cycle.
Document Number: 002-01101 Rev. *I
Page 36 of 77
S29WS512R
S29WS256R, S29WS128R
Software Functions and Sample Code
Table 8.22 Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Operation
Word Address
Data
1
Write Buffer Load Command
Write
Program Address + 555h
0025h
2
Write Word Count
Write
Program Address + AAAh
Word Count (N–1)h
3 to 34
Load Buffer Word N
Write
Program Address, Word N
Word N
Last
Write Buffer to Flash
Write
Sector Address + 555h
0029h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.
ig
n
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
d
fo
rN
ew
*/
*/
*/
*/
*/
*/ /*Addresses are given as word addresses.*/
/* address of source data
*/
/* flash destination address
*/
/* word count (minus 1)
*/
/* write write buffer load command */
/* write word count (minus 1)
*/
1 address/data pairs have been entered.
om
m
en
de
/* Example: Write Buffer Programming Command
/* NOTES: Write buffer programming limited to 16 words.
/*
All addresses to be written to the flash in
/*
one operation must be within the same flash
/*
page. A flash page begins at addresses
/*
evenly divisible by 0x20.
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
UINT16 wc
= words_to_program -1;
*( (UINT16 *)sector_address + 0x555 )
= 0x0025;
*( (UINT16 *)sector_address + 0xAAA)
= wc;
for(x = wc + 1; x>0; x--)
// Loop until wc +
D
es
The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
{
/* write source data to destination
/* increment destination pointer
/* increment source pointer
/* do it again
/* write confirm command
*/
*/
*/
*/
*/
N
ot
R
ec
*dst = *src; /* ALL dst MUST BE SAME PAGE */
dst++;
src++;
} ;
*( (UINT16 *)sector_address + 0x555)
= 0x0029;
/* poll for completion */
do
{
*((UNIT16 *)sector_address + 0x555)
= 0x0070;
reg
= *(dst-1);
} while (reg & 0x80) !=0x80);
/* Example: Write Buffer Abort Reset
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
8.9.2
/* enter the Read Status Register command.*/
/* Read the Status Register.*/
/* Loop until bit 7 is 1.*/
*/
/* write buffer abort reset
*/
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer
programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the
status bits. Addresses are don't-cares when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array data from any non-suspended sector and page.
The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case,
data may be read from any addresses not in Erase Suspend or Program Suspend.
Document Number: 002-01101 Rev. *I
Page 37 of 77
S29WS512R
S29WS256R, S29WS128R
After the Program Resume command is written, the device reverts to programming and the status bits are updated. The system can
determine the status of the program operation by reading the Status Register, just as in the standard program operation. See Status
Register on page 31 for more information.
The system must write the Program Resume command to exit the Program Suspend mode and continue the programming
operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after
the device has resumed programming.
Software Functions and Sample Code
Table 8.23 Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0051h
es
ig
n
The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.spansion.com) for general information on Spansion flash memory software development guidelines.
/* Example: Program suspend command */
D
/* write suspend command
*/
ew
*( (UINT16 *)base_addr + 0x000 ) = 0x0051;
Table 8.24 Program Resume
rN
(LLD Function = lld_ProgramResumeCmd)
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0050h
fo
Cycle
om
m
en
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0050;
8.9.3
de
d
The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.spansion.com) for general information on Spansion flash memory software development guidelines.
Sector Erase
/* write resume command
*/
N
ot
R
ec
The sector erase function erases one sector in the memory array. (See Table 12.1 on page 63) The device does not require the
system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an
all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh.
The system is not required to provide any controls or timings during these operations. Sector Erase requires 2 commands. Each of
the Sector Addresses must match, the lower addresses must be correct, and the sector must be unlocked previously by executing
the Sector Unlock command and must not be locked by the Sector Lock Range command.
When the Embedded Erase algorithm is complete, the bank returns to idle state and addresses are no longer latched. Note that
while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can
determine the status of the erase operation by reading the Status Register. See Status Register on page 31 for information on these
status bits.
Once the sector erase operation has begun, only reading from outside the erase bank, read of Status Register, and the Erase
Suspend command are valid. All other commands are ignored. However, note that a hardware reset immediately terminates the
erase operation. If that occurs, the sector erase command sequence must be reinitiated once the device has returned to idle state,
to ensure data integrity.
See Program/Erase Operations on page 35 for parameters and timing diagrams.
Document Number: 002-01101 Rev. *I
Page 38 of 77
S29WS512R
S29WS256R, S29WS128R
Software Functions and Sample Code
Table 8.25 Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Setup Command
Write
Sector Address + AAAh
Sector Address + 555h
0080h
2
Sector Erase Command
Write
Sector Address + 555h
Sector Address + AAAh
0030h
Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA.
The following is a C source code example of using the sector erase function. Byte address space is used. Refer to the Spansion
Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion flash memory software
development guidelines.
/* Example: Sector Erase Command */
/* write setup command
= 0x0030;
*/
/* write sector erase command
*/
8.9.4
D
es
*( (UINT16 *)sector_address + 0x2AA)
ig
n
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
Chip Erase
de
d
fo
rN
ew
The chip erase function erases the complete memory array. (See Table 12.1 on page 63). The device does not require the
system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. After a successful chip erase, all locations within the device contain FFFFh. The
system is not required to provide any controls or timings during these operations. Chip Erase requires 2 commands. Each of the
Sector Addresses must match, the lower addresses must be correct, and Sector 0 must be unlocked previously by executing
the Sector Unlock command. If any sector has been locked by the Sector Lock Range command, the Chip Erase command will
not start.
om
m
en
When the Embedded Erase algorithm is complete, the device returns to idle state and addresses are no longer latched. Note
that while the Embedded Erase operation is in progress, the system can not read data from the device. The system can
determine the status of the erase operation by reading the Status Register. See Status Register on page 31 for information on
these status bits.
ec
Once the chip erase operation has begun, only a Status Read, Hardware RESET or Power cycle are valid. All other commands
are ignored. However, note that a Hardware Reset or Power Cycle immediately terminates the erase operation. If that occurs,
the chip erase command sequence must be reinitiated once the device has returned to idle state, to ensure data integrity.
R
See Program/Erase Operations on page 35 for parameters and timing diagrams.
N
Table 8.26 Chip Erase
ot
Software Functions and Sample Code
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Setup Command
Write
Base + AAAh
Base + 555h
0080h
2
Chip Erase Command
Write
Base + 555h
Base + AAAh
0010h
The following is a C source code example of using the chip erase function. Byte address space is used. Refer to the Spansion
Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion flash memory software
development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
/* write setup command
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0010;
/* write chip erase command
*/
Document Number: 002-01101 Rev. *I
Page 39 of 77
S29WS512R
S29WS256R, S29WS128R
8.9.5
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,
the device. This command is valid only during the sector erase operation. The Erase Suspend command is ignored if written during
the chip erase operation.
When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL (erase
suspend latency) to suspend the erase operation and update the status bits.
After the erase operation has been suspended, the bank enters the erase-suspend mode. The system can read data from or
program data to the device. Reading at any address within erase-suspended sectors produces undetermined data. The system can
read the Status Register to determine if a sector is actively erasing or is erase-suspended. Refer to Status Register on page 31 for
information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend mode. The system can determine
the status of the program operation by reading the Status Register, just as in the standard program operation.
es
ig
n
To resume the sector erase operation, the system must write the Erase Resume command. The device will revert to erasing and the
status bits will be updated. Further writes of the Resume command are ignored. Another Erase Suspend command can be written
after the chip has resumed erasing.
D
Software Functions and Sample Code
ew
Table 8.27 Erase Suspend
rN
(LLD Function = lld_EraseSuspendCmd)
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
fo
Cycle
/* Example: Erase suspend command */
/* write suspend command
*/
N
ot
R
ec
om
m
en
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
de
d
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion flash memory software development guidelines.
Document Number: 002-01101 Rev. *I
Page 40 of 77
S29WS512R
S29WS256R, S29WS128R
Table 8.28 Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion flash memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
Accelerated Program/Sector Erase
ig
n
8.9.6
es
Accelerated write buffer programming, and sector erase operations are enabled through the ACC function. This method is faster
than the standard chip program and sector erase command sequences.
ew
D
The accelerated write buffer program and sector erase functions must not be used more than 50 times per sector. In
addition, accelerated write buffer program and sector erase should be performed at room temperature (30°C 10°C).
rN
If the system asserts VHH on ACC, the device automatically uses the higher voltage on the input to reduce the time required for
program and erase operations. Removing VHH from the ACC input, upon completion of the embedded program or erase operation,
returns the device to normal operation.
Simultaneous operations are not supported while ACC is at VHH. The ACC pin must not be at VHH for operations other than
accelerated write buffer programming, accelerated sector erase, and status register read or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
There is a minimum of 100 ms required between accelerated write buffer programming and a subsequent accelerated
sector erase.
d
de
om
m
en
8.10
fo
Handshaking
ec
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin,
which is a dedicated output controlled by CE#.
N
ot
R
When either CE# input is Low, the RDY output signal is actively driven. When both of the CE# inputs are High the RDY output is
high-impedance. When either CE# input and OE# input is Low, the DQ15-DQ0 output signals are actively driven. When both of the
CE# inputs are High, or the OE# input is High, the DQ15DQ0 outputs are high-impedance.
When the device is operated in synchronous mode, and OE# is low (active), the initial word of burst data becomes available after the
rising edge of the RDY. CR.8 in the Configuration Register allows the host to specify whether RDY is active at the same time that
data is ready, or one cycle before data is ready (see Table 8.12 on page 30).
When the device is operated in asynchronous mode, RDY will be high when CE# is low (active).
Document Number: 002-01101 Rev. *I
Page 41 of 77
S29WS512R
S29WS256R, S29WS128R
8.11
Hardware Reset
The RESET# input provides a hardware method of resetting the device to idle state. When RESET# is driven low for at least a period
of tRP, the device immediately terminates any operation in progress, in the high-impedance state all outputs, resets the configuration
register, and ignores all read/write commands for the duration of the reset operation. The device also resets the internal state
machine to idle state.
To ensure data integrity, the operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence.
When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby
current is greater.
See Figure 11.6 for timing diagrams
Software Reset
ig
n
8.12
es
Software reset is part of the command set (see Table 12.1 on page 63) that also returns the device to idle state and must be used for
the following conditions:
D
1. Exit ID/CFI mode
ew
2. Exit Secure Silicon Region mode
3. Exit Configuration Register mode
rN
4. Exit SSR Lock mode
fo
Reset commands are ignored once programming/erasure has begun until the operation is complete.
d
Software Functions and Sample Code
de
Table 8.29 Reset
om
m
en
(LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Note:
Base = Base Address.
R
ec
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion flash memory software development guidelines.
ot
/* Example: Reset (software reset of Flash state machine) */
N
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
9. Sector Protection/Unprotection
The Sector Protection/Unprotection feature disables or enables programming or erase operations in one or multiple sectors and can
be implemented through software and/or hardware methods, which are independent of each other. This section describes the
various methods of protecting data stored in the memory array.
Document Number: 002-01101 Rev. *I
Page 42 of 77
S29WS512R
S29WS256R, S29WS128R
9.1
Sector Lock/Unlock Command
The Sector Lock/Unlock command sequence allows the system to protect all sectors from accidental writes or, unprotect one sector
to allow programming or erasing of the sector. When the device is first powered up, all sectors are unlocked. To lock all sectors
(enter protected mode), a Sector Lock/Unlock command must be issued to any Sector Address. Once this command is issued, only
one sector at a time can be unlocked until power is cycled. To unlock a sector, the system must write the Sector Lock/Unlock
command sequence. Two cycles are first written: addresses are xAAAh and x555 with data 60h. During the third cycle, the sector
address (SLA) and unlock command (60h) are written, while specifying with address A6 whether that sector should be locked (A6 =
VIL) or unlocked (A6 = VIH).
A Program or Erase operation will check the unlocked Sector Address only at the beginning of the Program or Erase operation. It is
not necessary to keep the sector being Programmed or Erased locked during the operation. The system can change the unlocked
Sector after programming or erasing the sector has begun. An Erase Resume or Program Resume command does not check the
value of the unlocked Sector.
ig
n
If A6 is set to VIL,then all sectors in the array will be locked. Only one sector at a time can be unlocked.
Sector Lock Range Command
ew
9.2
D
es
If a Sector Lock/Unlock command is issued to a sector that is protected by the Sector Lock Range command, all sectors in the part
will be locked.
fo
rN
This command allows a range of sectors to be protected from program or erase (locked) until a hardware reset or power is removed
from the device. Once this command is issued, all sectors are protected and the Sector Lock/Unlock command is ignored for the
selected the range of sectors. Sectors outside of the selected range must be unlocked one sector at a time using the Sector Unlock
command in order to be erased/programmed.
om
m
en
de
d
Two cycles are first written: addresses are xAAAh and data is 60h. During the third cycle, the sector address (SLA) and load sector
address command (61h) is written. This cycle sets the lower sector address of the range. During the fourth cycle, the sector address
(SLA) and load sector address command (61h) is written. This cycle sets the upper sector address of the range. The addresses
reference a large sector address range (128 KB). If a sector address matches the location of the four small sectors, all of the small
sectors will be protected as a group. The sectors selected by the lower and upper address, as well as all sectors between these
sectors, are protected from program and erase until a hardware reset or power is removed. If the lower and upper sector addresses
are for the same sector then only that one sector is locked. flash address input A6 (system byte address bit a7) during both address
cycles must be zero (A6 = VIL) for the addresses to be accepted as valid.
R
ec
If the first sector address cycle contains an address which is higher than the second sector address cycle, then the command
sequence will be invalid. If A6 is set to one (A6 = VIH) on either address cycle, the command sequence will disable subsequent
Sector Lock Range commands.
ot
A valid Sector Lock Range command sequence is accepted only once after a Hardware Reset or initial power up. Additional Sector
Lock Range commands will be ignored.
N
If a Sector Unlock command tries to unlock a Sector within the Sector Lock Range, the Sector will remain in locked state. Similarly, if
a Sector that is currently unlocked by the Sector Unlock command is overlapped by a subsequent Sector Lock Range, that sector
will be locked and program erase operations to that region will be ignored.
This command is generally used by trusted boot code. After power on reset boot code has the option to check for any need to
update sectors before locking them for the remainder of power on time. Once boot code is satisfied with the content of sectors to be
protected the Sector Lock Range command is used to lock sectors against any program or erase during normal system operation.
This adds an extra layer of protection for critical data that must be protected against accidental or malicious corruption. Yet,
maintains flexibility for trusted boot code to perform occasional updates of the data. It is important to issue the Sector Lock Range
command even if no sectors are to be protected so that sectors that should remain available for update cannot be later locked by
accidental or malicious code behavior.
Document Number: 002-01101 Rev. *I
Page 43 of 77
S29WS512R
S29WS256R, S29WS128R
9.3
Hardware Data Protection Methods
There are additional hardware methods by which intended or accidental erasure of any sectors can be prevented via hardware
means. The following subsections describes these methods:
9.3.1
ACC Method
Once the ACC input is set to VIL, all program and erase functions are disabled and hence all Sectors (including the Secure Silicon
Region and SSR Lock) are protected. ACC does not prevent programming (writing) of the configuration register.
9.3.2
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
Write Pulse Glitch Protection
D
9.3.3
es
ig
n
The command register and all internal program/erase circuits are disabled. Subsequent writes are ignored until VCC is greater than
VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than
VLKO.
Power-Up Write Inhibit
rN
9.3.4
ew
Noise pulses of less than 3 ns (typical) on OE#, WE#, or CE# do not initiate a write cycle.
SSR Lock
de
9.4
d
fo
If CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept write commands. The internal state machine is
automatically reset to the idle state on power-up.
om
m
en
The SSR Lock consists of two bits. The Customer Secure Silicon Region Protection Bit is in location 0. The Factory Secure Silicon
Region Protection Bit is in location 1. All other bits in this location return “1.”
If the Secure Silicon Region Protection Bit is set to “0,” the Customer Secure Silicon Region is protected and can not be
programmed. If this bit is set to “1,” the Customer Secure Silicon Region is available for programming. Once this area has been
programmed, the SSR Lock bit 0 should be programmed to “0.”
ot
R
ec
Similarly the Factory Secure Silicon Region Protection Bit is set to “0” when protected. This area is always programmed and
protected at the Spansion factory.
Secure Silicon Region
N
9.5
The Secure Silicon Region provides an extra flash memory region that may be programmed once and permanently protected from
further programming or erase.
Reads can be performed in the Asynchronous or Synchronous mode.
Sector address supplied during the Secure Silicon Entry command selects the flash memory array sector that is overlaid by
the Secure Silicon Region address map.
Continuous burst mode reads within Secure Silicon Region wrap from address FFh back to address 00h.
Reads outside of the overlaid sector return memory array data.
The Secure Silicon Region is not accessible when the device is executing an Embedded Algorithm (nor during Program
Suspend, Erase Suspend, or while another AOS is active).
See the Secure Silicon address map for address range of this area.
Document Number: 002-01101 Rev. *I
Page 44 of 77
S29WS512R
S29WS256R, S29WS128R
9.5.1
Factory Secure Silicon Region
The Factory Secure Silicon Region is always protected when shipped from the factory and has the Factory SSR Lock Bit (bit 1)
permanently set to a Zero. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code
once the product is shipped to the field.
9.5.2
Customer Secure Silicon Region
The Customer Secure Silicon Region is shipped unprotected, Customer SSR Lock Bit (bit 0) set to a One. allowing customers to
utilize that sector in any manner they choose.
The Customer Secure Silicon Region can be read any number of times, but each word can be programmed only once and the region
locked only once. The Customer Secure Silicon Region lock must be used with caution as once locked, there is no procedure
available for unlocking the Customer Secure Silicon Region area and none of the bits in the Customer Secure Silicon Region
memory space can be modified in any way. The Customer Indicator Bit is located in the SSR Lock at bit location 0.
Secure Silicon Region Entry and Exit Command Sequences
D
9.5.3
es
ig
n
Once the Customer Secure Silicon Region area is protected, any further attempts to program in the area will fail with status
indicating the area being programmed is protected.
rN
ew
The system can access the Secure Silicon Region region by issuing the one-cycle Enter Secure Silicon Region Entry command
sequence from the IDLE State. The device continues to have access to the Secure Silicon Region region until the system issues the
Exit Secure Silicon Region command sequence, performs a Hardware RESET, or until power is removed from the device.
fo
See Command Definition Table [Secure Silicon Region Command Table, Appendix
Table 12.1 on page 63 for address and data requirements for both command sequences.
d
The Secure Silicon Region Entry Command allows the following commands to be executed
Read customer and factory Secure Silicon Regions
Program the customer Secure Silicon Region
Read data out of all sectors not re-mapped to Secure Silicon Region
Secure Silicon Region Exit
om
m
en
de
Software Functions and Sample Code
R
ec
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands.
Refer to the Spansion Low Level Driver User’s Guide (available soon on www.spansion.com) for general information on Spansion
flash memory software development guidelines.
ot
Table 9.1 Secured Silicon Region Entry
N
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Byte Address
Word Address
Data
Entry Cycle
Write
Base + AAAh
Base + 555h
0088h
Note:
Base = Base Address.
/* Example: SecSi Sector Entry Command Byte Address*/
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write Secsi Sector Entry Cmd
*/
Table 9.2 Secured Silicon Region Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Byte Address
Word Address
Data
Program Setup
Write
Base + AAAh
Sector Address + 555h
0025h
Write Word Count
Write
Program Address + 555h
Sector Address + 2AA
Word Count (N–
1)h
Document Number: 002-01101 Rev. *I
Page 45 of 77
S29WS512R
S29WS256R, S29WS128R
Table 9.2 Secured Silicon Region Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Byte Address
Word Address
Data
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
Load Buffer Word N
Write
Program Address, Word
N
Write Buffer to Flash
Write
Sector Address + AAAh
Word N
Sector Address + 555h
0029h
Note:
Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm.
*/
ig
n
Table 9.3 Secured Silicon Region Exit
es
(LLD Function = lld_SecSiSectorExitCmd)
Operation
Byte Address
Word Address
Data
Exit Cycle
Write
Any Address
Any Address
00F0h
D
Cycle
ew
Note:
Base = Base Address.
Standby Mode
om
m
en
10.1
de
10. Power Conservation Modes
fo
/* write SecSi Sector Exit cycle */
d
*( (UINT16 *)XXX ) = 0x00F0;
rN
/* Example: SecSi Sector Exit Command */
Automatic Sleep Mode
ot
10.2
R
ec
In the standby mode current consumption is greatly reduced, and the outputs (DQ15-DQ0) are placed in the high impedance state,
independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC
± 0.2 V. The device requires standard access time (tCE or tIA) for read access, before it is ready to read data. If the device is
deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in DC
Characteristics on page 48 represents the standby current specification
N
The automatic sleep mode minimizes flash device energy consumption while in asynchronous mode and while the device is not in a
suspended state. The device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep
mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings (tACC or tPACC) provide new data
when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous
mode, the automatic sleep mode is disabled. ICC6 in DC Characteristics on page 48 represents the automatic sleep mode current
specification.
10.3
Output Disable (OE#)
When the OE# input is at VIH, output (DQ15-DQ0) from the device is disabled and placed in the high impedance state. RDY is not
controlled by OE#.
Document Number: 002-01101 Rev. *I
Page 46 of 77
S29WS512R
S29WS256R, S29WS128R
11. Electrical Specifications
11.1
Absolute Maximum Ratings
Table 11.1
Storage Temperature
Plastic Packages
–65°C to +150°C
Ambient Temperature with Power Applied
–65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except as noted below
(Note 1)
–0.5 V to +2.5 V
VIO
–0.5 V to +2.5 V
ACC (Note 2)
–0.5 V to +9.5 V
es
VCC (Note 1)
ig
n
–0.5 V to VIO + 0.5 V
100 mA
D
Output Short Circuit Current (Note 3)
ew
Notes
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1.
Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2.
rN
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC
voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
de
d
fo
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
Figure 11.1 Maximum Negative Overshoot Waveform
20 ns
om
m
en
20 ns
+0.8 V
ec
–0.5 V
–2.0 V
ot
R
20 ns
N
Figure 11.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
1.0 V
11.2
20 ns
20 ns
Operating Ranges
Table 11.2
Wireless (I) Devices
Ambient Temperature (TA)
–25°C to +85°C
Supply Voltages
VCC Supply Voltages
Document Number: 002-01101 Rev. *I
+1.70 V to +1.95 V
Page 47 of 77
S29WS512R
S29WS256R, S29WS128R
Table 11.2
+1.70 V to +1.95 V
VIO Supply Voltages
VCC(min) VIO(min) - 200 mV
Notes
Operating ranges define those limits between which the functionality of the device is guaranteed.
CMOS Compatible
Description
Test Conditions (Notes 1 & 2)
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCCmax
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCCmax
Min
26
36
mA
104 MHz
33
44
mA
66 MHz
24
35
mA
83 MHz
26
38
mA
104 MHz
30
40
mA
66 MHz
28
39
mA
83 MHz
30
42
mA
104 MHz
32
44
mA
20
30
µA
D
83 MHz
rN
fo
d
IIO2
VIO Standby
CE# = RESET# = VCC ± 0.2V
om
m
en
VCC Active Asynchronous
Read Current
ICC3
VCC Standby Current
ICC4
VCC Reset Current
CE# = VIL, OE# = VIH,
ACC = VIH
ec
VCC Active Write Current
(3) (7)
CE# = RESET# = VCC ± 0.2 V
ICC5
VCC Active Current Simultaneous
Operation
(Read While Write) (6)
2
3
µA
10 MHz
40
80
mA
5 MHz
20
40
mA
1 MHz
10
20
mA
VACC
1
5
µA
VCC
20
40
mA
VACC
1
5
µA
VCC
20
50
µA
RESET# = VIL, CLK = VIL
N
ot
ICC2
CE# = VIL, OE# = VIH,
WE# = VIH
R
ICC1
µA
µA
de
OE# = VIH , RDY = Tri-State
±1
mA
CE# = VIL, OE# = VIH, WE# = VIH,
burst length = Continuous
VIO Non-active Output
Unit
33
CE# = VIL, OE# = VIH, WE# = VIH, burst
length = 16
IIO1
Max
24
CE# = VIL, OE# = VIH, WE# = VIH, burst
length = 8
VCC Active burst Read Current
Typ
±1
66 MHz
ICCB
ig
n
Parameter
es
11.3.1
DC Characteristics
ew
11.3
CE# = VIL, OE# = VIH, ACC = VIH
150
250
µA
66 MHz,
Continuous Burst
50
60
mA
83 MHz,
Continuous Burst
50
60
mA
104 MHz,
Continuous Burst
52
60
mA
ICC6
VCC Sleep Current (4)
CE# = VIL, OE# = VIH
20
50
µA
ICC7
VCC Active Page Read Current
OE# = VIH, 8 word Page Read @ 10 MHz
10
15
mA
IACC
Accelerated Program Current
(5)
CE# = VIL, OE# = VIH,
VACC = 9.5 V
7
10
mA
20
mA
VIL
Input Low Voltage
VIO = 1.8 V
–0.2
0.4
V
VIH
Input High Voltage
VIO = 1.8 V
VIO – 0.4
VIO + 0.4
VOL
Output Low Voltage
IOL = 100 µA, VCC = VCC min = VIO
VOH
Output High Voltage
IOH = –100 µA, VCC = VCC min = VIO
VHH
Voltage for Accelerated Program
8.5
9.5
V
VLKO
Low VCC Lock-out Voltage
1.0
1.1
V
Document Number: 002-01101 Rev. *I
VACC
15
VCC
0.1
VIO – 0.1
V
V
Page 48 of 77
S29WS512R
S29WS256R, S29WS128R
Notes
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. VCC= VIO
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3.
5. Total current during accelerated programming is the sum of VACC and VCC currents.
6. ICC5 apples while reading the status register during program and erase operations
7. Effect of status register polling during write not included.
Capacitance
Description
CIN
Input Capacitance
(Address, CE#, OE#, WE#,
AVD#, WE#, CLK, RESET#)
Test Condition
VIN = 0
COUT
Output Capacitance
(DQ, RDY)
VOUT = 0
Min.
Typ.
Max.
Unit
Single CE
2.0
4.5
6.0
pF
Dual CE
4.0
9.0
12.0
pF
6.0
pF
12.0
pF
Single CE
2.0
4.5
Dual CE
4.0
9.0
D
Notes
1. Test conditions TA = 25°C, f = 1.0 MHz
ew
2. Sampled, not 100% tested.
AC Test Conditions
rN
11.5
ig
n
Symbol
es
11.4
fo
Operating Range
0.0 to VIO
d
Input level
VIO/2
de
Input comparison level
Output data comparison level
om
m
en
Load capacitance (CL)
ec
Transition time (tT) (input rise and fall times)
66 MHz
3.00 ns
83 MHz
2.40 ns
104 MHz
1.85 ns
66 MHz
3.00 ns
83 MHz
2.40 ns
104 MHz
1.85 ns
N
ot
R
Transition time (tT) (CLK input rise and fall times)
VIO/2
30 pF
Figure 11.3 Input Pulse and Test Point
VIO
VIO /2
Input and Output
Test Point
VIO /2
0V
Figure 11.4 Output Load
Device
Under
Test
*CL = 30 pF including scope
and Jig capacitance
Output Load
Document Number: 002-01101 Rev. *I
Page 49 of 77
S29WS512R
S29WS256R, S29WS128R
11.6
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
VCC Power Up
ig
n
11.7
Don’t Care, Any Change Permitted
Table 11.3 VCC Power-up
Description
Test Setup
tVCS
VCC Setup Time
Min
tVIOS
VIO Setup Time
D
es
Parameter
Unit
300
µs
300
µs
ew
Min
Speed
Notes
1. RESET# must be high after VCC and VIO are higher than VCC minimum.
rN
2. VCC VIO – 200 mV during power-up.
fo
3. VCC and VIO ramp rate could be non-linear.
4. VCC and VIO are recommended to be ramped up simultaneously.
d
5. Time between a short power off to power on should be >10 ms when system is at 0°C or below.
om
m
en
de
Figure 11.5 VCC Power-up Diagram
VCC min
tVIOS
VIO min
ec
VCC
tRP
R
VIO
tVCS
VIH
tRPH
ot
RESET#
N
tRH
CE#
11.7.1
Hardware Reset (Reset#)
Table 11.4 Warm-Reset
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tRP
RESET# Pulse Width
Min
50
ns
tRH
Reset High Time
Before Read
Min
200
ns
tRPH
RESET# Low to CE#
Low
Min
10
us
Document Number: 002-01101 Rev. *I
Page 50 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 11.6 Reset Timings
CE#, OE#
tRH
RESET#
tRP
tRPH
Description
104 MHz
CLK Frequency
fCLK
Max
104
Min
DC (Note 1)
CLK Period
Min
CLK Low/High Time
Min
Unit
MHz
9.6
ns
0.45 tCLK
ns
ew
tCLK
tCL/tCH
es
Parameter
ig
n
CLK Characterization
D
11.8
rN
Note
1. DC for operations other than continuous and 16 word (32 byte) synchronous burst read. See Section 11.9.1, AC Characteristics–Synchronous Burst Read on page 52.
fo
2. Clock jitter of +/- 5% is permitted.
om
m
en
tCH
de
d
Figure 11.7 CLK Characterization
tCL
N
ot
R
ec
CLK
tCLK
Document Number: 002-01101 Rev. *I
Page 51 of 77
S29WS512R
S29WS256R, S29WS128R
11.9
AC Characteristics
11.9.1
AC Characteristics–Synchronous Burst Read
Parameter (Notes)
Symbol
66
Clock Frequency
CLK
Min
Clock Cycle
tCLK
Min
83
104
Unit
DC (0) for operations other than continuous and
32 byte synchronous burst.
KHz
120 in 32 Byte burst
1000 in continuous burst
12.0
9.62
ns
Min
tIA
Max
75
75
75
ns
tBACC
Max
11.2
9
7.6
ns
AVD# Setup Time to CLK
tAVDS
Min
5
5
5
ns
AVD# Hold Time from CLK
tAVDH
Min
3
3
3
ns
Address Setup Time to CLK
tACS
Min
4
4
4
ns
Address Hold Time from CLK
tACH
Min
6
5
5
ns
Data Hold Time from Next Clock Cycle
tBDH
Min
3
Output Enable to Data
tOE
Max
15
CE# Disable to Output High-Z (2)
tCEZ
Max
10
OE# Disable to Output High-Z (2)
tOEZ
Max
10
CE# low to RDY valid
AVD# Pulse
tCES
Min
tRACC
Max
tCR
Max
tAVDP
Min
Notes
1. Not 100% tested.
4
ns
D
ew
3
2
ns
15
15
ns
10
10
ns
10
10
ns
rN
fo
CE# Setup Time to CLK
CLK to RDY valid
4
4
ns
9
7.6
ns
10
10
10
ns
6
6
6
ns
d
Burst Access Time Valid Clock to Output
Delay
0.45 tCLK
11.2
de
Internal Access Time
om
m
en
CLK High or Low Time
ig
n
tCLKH/L
es
15
ec
2. If OE# is disabled before CE# is disabled, the output goes to High-Z by tOEZ.
If CE# is disabled before OE# is disabled, the output goes to High-Z by tCEZ.
If CE# and OE# are disabled at the same time, the output goes to High-Z by tOEZ.
3. Synchronous Access Time is calculated using the formula (# of WS - 1)*(clock period) + (tBACC).
R
4. AVD can not be low for 2 subsequent CLK cycles
ot
2
3
N
1
CLK
Figure 11.8 Synchronous Read Mode
tCES
4
5
6
7
7? cycles for initial access is shown as an illustration.
CE#
tCLKH tCLKL
tAVDS
AVD#
tCEZ
tCLK
tAVDP
tACS
tBACC
tAVDH
tOEZ
High-Z
Data
tIA
tACH
Address
DC
DE
DB
AC
tBDH
OE#
tCR
RDY
DD
tOE
Hi-Z
Document Number: 002-01101 Rev. *I
tRACC
tCEZ
High-Z
Page 52 of 77
S29WS512R
S29WS256R, S29WS128R
11.9.2
AC Characteristics–Asynchronous Read
Symbol
Min
Max
Access Time from CE# Low
tCE
–
80
Asynchronous Access Time from address valid
tACC
–
80
Read Cycle Time
tRC
80
–
AVD# Low Time
tAVDP
6
–
Address Setup to rising edge of AVD#
tAAVDS
5
–
Address Hold from rising edge of AVD#
tAAVDH
3.5
–
15
Output Enable to Output Valid
tOE
–
CE# Setup to AVD# falling edge
tCAS
4
–
CE# Disable to Output & RDY High-Z (Note 1)
tCEZ
–
10
OE# Disable to Output High-Z (Note 1)
tOEZ
–
10
AVD# High to OE# Low
tAVDO
0
–
tCR
–
10
CE# low to RDY valid
tWEA
tCLK
–
tOEH
4
–
Intra Page Access Time
tPACC
–
ns
es
WE# Disable to AVD# Enable
WE# Disable to OE# Enable
Unit
ig
n
Parameter
D
15
rN
2. If OE# is disabled before CE# is disabled, the output goes to High-Z by tOEZ.
If CE# is disabled before OE# is disabled, the output goes to High-Z by tCEZ.
If CE# and OE# are disabled at the same time, the output goes to High-Z by tOEZ.
ew
Notes
1. Not 100% tested.
de
CLK
d
fo
Figure 11.9 Asynchronous Read Mode (AVD# Toggling - Case 1)
CLK may be at Vil or Vih or Toggle
tAVDP
AVD#
N
ot
WE#
R
tWEA
tOEH
ec
OE#
om
m
en
Address valid before AVD# Low before CE# Low
CE#
tAAVHD
tAAVDS
A-max - A0
tOE
tCE
tACC
tOEZ
tCEZ
DQ15-DQ0
tCR
tCEZ
RDY
Document Number: 002-01101 Rev. *I
Page 53 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 11.10 Asynchronous Read Mode (AVD# Toggling - Case 2)
CLK may be at Vil or Vih or Toggle
CLK
CE# & Address valid before AVD#
CE#
tAVDP
AVD#
OE#
tWEA
tOEH
tAAVDS
ig
n
WE#
tAAVHD
es
A-Max - A0
rN
DQ15 - DQ0
ew
tCE
tACC
D
tOE
tCEZ
fo
tCR
tCEZ
tOEZ
om
m
en
de
d
RDY
Figure 11.11 Asynchronous Read Mode (AVD# Toggling - Case 3)
CLK may be at Vil or Vih or Toggle
CLK
ec
CE# before AVD# before Address
R
CE#
N
OE#
ot
tAVDP
AVD#
tWEA
tOEH
WE#
tAAVHD
tAAVDS
A-max - A0
tOE
tCE
tACC
tCEZ
tOEZ
DQ15 - DQ0
tCR
tCEZ
RDY
Document Number: 002-01101 Rev. *I
Page 54 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 11.12 Asynchronous Read Mode (AVD# tied to CE#)
CLK
VIL or VIH
tRC
CE#
tCEZ
AVD#
tOE
OE#
tOEH
WE#
tOEZ
tCE
tWEA
RD
ig
n
DQ15-DQ0
tACC
Amax-A0
D
es
VA
tCR
tCEZ
Hi-Z
ew
RDY Hi-Z
rN
Notes
1. AVD# is tied to CE#
de
d
fo
2. VA = Valid Read Address, RD = Read Data.
om
m
en
Figure 11.13 Asynchronous Page Mode Read
Page
Amax-A3
A2-A0
R
ec
A0
D0
Ax
A2
tPACC
D1
tPACC
Dx
D7
CE#
N
ot
Data Bus
tACC
A1
tPACC
OE#
AVD#
Note
RA = Read Address, RD = Read Data.
Document Number: 002-01101 Rev. *I
Page 55 of 77
S29WS512R
S29WS256R, S29WS128R
11.9.3
AC Characteristics–Asynchronous Write Operation
Parameter
WE# Cycle Time
Symbol
Min
Typ
Max
Unit
tWC
60
–
–
ns
tAVDP
6
–
–
ns
tAAVDS
5
–
–
ns
Address Setup to falling edge of WE#
tAWES
5
–
–
ns
Address Hold from rising edge of AVD#
tAAVDH
3.5
–
–
ns
Address Hold from falling edge of WE#
tAWEH
3.5
–
–
ns
Read Recovery time before Write
tGHWL
0
–
–
ns
Data Setup to rising edge of WE#
tDS
20
–
–
ns
Data Hold from rising edge of WE#
tDH
0
–
–
ns
ns
4
–
–
AVD# toggled
tCH1
0
–
–
CE# Hold from rising edge of WE#
AVD# = CE#
tCH2
0
–
–
tWP
25
–
WE# Pulse Width
es
tCS
CE# Hold from rising edge of WE#
–
D
CE# Setup to falling edge of WE#
ig
n
AVD# low pulse width
Address Setup to rising edge of AVD#
ns
ns
tWPH
20
–
tVLWH
23.5
–
–
ns
WE# Disable to AVD# Enable
tWEA
7.5
–
–
ns
tCR
–
–
10
ns
CE# Disable to Output High Z
tCEZ
–
–
10
ns
OE# Disable to WE# Enable
tWEH
4
–
–
ns
Erase Suspend Latency
tESL
–
–
30
µs
Program Suspend Latency
tPSL
–
–
30
µs
Latency between Read and Write Operations
tSRW
rN
fo
d
de
0
–
–
ns
30
–
–
µs
tPRS
30
–
–
µs
N
ot
R
ec
Program Resume to Program Suspend
ns
tERS
om
m
en
Erase Resume to Erase Suspend
ew
WE# Pulse Width High
AVD# Disable to WE# Disable
CE# low to RDY valid
–
ns
Document Number: 002-01101 Rev. *I
Page 56 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 11.14 Latched Asynchronous Write Mode (AVD# Toggling)
Case 1 : AVD# is toggled every write cycle
CL
K
VIL or VIH
tCH1
tCS
CE#
tAVDP
AVD#
tVLWH
tWEA
OE#
tWPH
ig
n
tWP
es
WE#
tWC
D
tDH
WD
DQ15-DQ0
tAH
VA2
fo
VA1
VA
Amax-A0
d
tCR
Notes
1. VA = Valid Read Address, WD = Write Data.
Hi-Z
N
ot
R
ec
2. Addresses latched by rising edge of AVD#.
de
Hi-Z
tCEZ
om
m
en
RDY
rN
tAS
WD
ew
tDS
Document Number: 002-01101 Rev. *I
Page 57 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 11.15 Asynchronous Write Mode (AVD# Tied to CE#)
Case 2 : AVD# is synchronized with CE#
CLK
VIL or VIH
tCH2
tCS
CE#
AVD#
OE#
tWPH
ig
n
tWP
WE#
tDH
WD
D
WD
DQ15-DQ0
es
tDS
tAHEH
tAWES
VA
rN
VA
Amax-A0
Hi-Z
Hi-Z
de
d
Notes
1. VA = Valid Read Address, WD = Write Data.
om
m
en
2. Addresses latched by falling edge of WE#.
11.9.4
tCEZ
fo
tCR
RDY
ew
tWC
Wait State Configuration Register Setup
Figure 11.16 Example of Programmable Wait States
ec
Data
D1
Rising edge of next
clock cycle following
last wait state triggers
next burst data
N
AVD#
ot
R
D0
Total number of clock cycles
following addresses being latched
OE#
1
2
3
4
5
7
6
CLK
0
1
2
3
4
5
6
7
Total number of clock edges following addresses being latched
Document Number: 002-01101 Rev. *I
Page 58 of 77
S29WS512R
S29WS256R, S29WS128R
Configuration
Register
Programmable Wait States
0000 =
0001 =
3rd
0010 =
4th
0011 =
5th
CR.13
0100 =
6th
CR.12
0101 =
CR.11
0110 =
7th
initial data is valid on the
10th
.
.
.
.
.
.
1011 =
13th
Reserved
ew
1111 =
ig
n
1000 =
es
9th
1100 =
rising CLK edge after addresses are latched
8th
0111 =
D
CR.14
rN
Figure 11.17 Latency with Boundary Crossing
AVD#
7E
7F
7F
d
7D
80
(stays high)
OE#,
CE#
83
ec
D124
D125
latency
tRACC
tRACC
latency
R
ot
N
Data
82
tRACC
tRACC
RDY
(Note 1)
RDY
(Note 2)
81
de
7C
om
m
en
Address
(hex)
CLK
fo
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
D126
D127
D128
D129
D130
(stays low)
Notes
1. RDY active with data (CR.8 = 1 in the Configuration Register).
2. RDY active one clock cycle before data (CR.8 = 0 in the Configuration Register).
3. Figure shows the device not crossing a bank in the process of performing an erase or program.
Document Number: 002-01101 Rev. *I
Page 59 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 11.18 Latency with Boundary Crossing into Bank Performing Embedded Operation
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
Address
(hex)
CLK
AVD#
7C
7D
7E
7F
7F
80
D127
00h
81
82
83
(stays high)
tRACC
RDY
(Note 1)
ig
n
tRACC
D126
00h
00h
00h
ew
D125
(stays low)
rN
OE#,
CE#
D124
D
Data
es
RDY
(Note 2)
2. RDY active one clock cycle before data (CR.8 = 0 in the Configuration Register).
fo
Notes
1. RDY active with data (CR.8 = 1 in the Configuration Register).
N
ot
R
ec
om
m
en
de
d
3. Figure shows the device crossing a bank in the process of performing an erase or program.
Document Number: 002-01101 Rev. *I
Page 60 of 77
S29WS512R
S29WS256R, S29WS128R
Figure 11.19 Back-to-Back Read/Write Cycle Timings
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank
tWC
tRC
Begin another
write or program
command sequence
tRC
tWC
CE#
OE#
tOE
tOEH
ig
n
tGHWL
WE#
tWP
tACC
tDS
tOEZ
WD
rN
WA
25h
RD
ew
RD
tSR/W
RA
RA
SA555h
fo
Addresses
D
tDH
Data
es
tWPH
AVD#
om
m
en
tAAVDH
de
d
tAAVDS
N
ot
R
ec
Note
Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or
erase operation in the busy bank.
Document Number: 002-01101 Rev. *I
Page 61 of 77
S29WS512R
S29WS256R, S29WS128R
Erase and Programming Performance
128 Kbyte
Sector Erase Time (7)
VCC
Typ (Note 1)
Max (Note 2)
0.8/1.3 (6)
3.5
32 Kbyte
VCC
0.35/0.6 (6)
2
128 Kbyte
ACC
0.8 / 1.3 (6)
3.5
32 Kbyte
ACC
VCC
(6)
Chip Erase Time (7)
ACC
0.35 / 0.6 (6)
2
78/126 (128 Mbit)
154/250 (128 Mbit)
155/251 (256 Mbit)
308/500 (256 Mbit)
308/500 (512 Mbit)
612/998 (512 Mbit)
78/126 (128 Mbit)
154/250 (128 Mbit)
155/251 (256 Mbit)
308/500 (256 Mbit)
308/500 (512 Mbit)
612/998 (512 Mbit)
VCC
130
400
Effective Word Programming Time using Program
Write Buffer
VCC
12.5
94
ACC
8
60
VCC
400
3000
ACC
256
1920
105 (128 Mbit)
210 (128 Mbit)
210 (256 Mbit)
420 (256 Mbit)
420 (512 Mbit)
840 (512 Mbit)
68 (128 Mbit)
136 (128 Mbit)
ACC
Blank Check
D
ew
om
m
en
Program Suspend/Program Resume (tPSL)
Excludes system level
overhead (Note 4)
s
Excludes system level
overhead (Note 4)
270 (256 Mbit)
538 (512 Mbit)
de
Erase Suspend/Erase Resume (tESL)
µs
rN
135 (256 Mbit)
269 (512 Mbit)
s
fo
Chip Programming Time
(using 32 word buffer)
d
VCC
Comments
(Note 3)
Single Word Program Time
Total 32-Word Buffer Programming Time
Unit
ig
n
Parameter
es
11.9.5
30
µs
30
µs
1
ms
Notes
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 10,000 cycles. Additionally, programming typically assumes a checkerboard
pattern.
2. Under worst case conditions of 90°C, VCC = 1.70 V, 100,000 cycles.
ec
3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
R
4. System-level overhead is the time required to execute the bus-cycle sequence for the program command. See Table 12.1 on page 63 for further information on
command definitions.
ot
5. The device has a minimum erase and program cycle endurance of 100,000 cycles.
N
6. The first value is excluding pre-programming time, while the second value is inclusive of pre-programming time for the FFFFh pattern, with status polling rate as 400
ns.
7. The erase time is calculated from the time of issuing erase command to the completion of erase operation (indicated by status register).
Document Number: 002-01101 Rev. *I
Page 62 of 77
S29WS512R
S29WS256R, S29WS128R
12. Appendix
This section contains information relating to software control or interfacing with the flash device.
12.1
Command Definitions
Where appropriate, addresses are listed in both 16-bit word mode for the flash device address space and byte mode for the system
address space. The byte address is listed above the word address.
Table 12.1 Command Definitions (Sheet 1 of 2)
Bus Cycles (Notes 1–5)
4-35
(SA) AAA
Buffer to Flash
1
Chip Erase
2
Sector Erase
2
Status Register Read
2
Status Register Clear
1
Program Suspend (6)
1
XXX
Program Resume (6)
1
XXX
Erase Suspend (7)
1
XXX
Erase Resume (7)
1
Blank Check (14)
1
Sector Lock Range
(SA) AAA
4
(SA) 555
80
(SA) 555
(SA) AAA
(SA) AAA
(SA) PA (12)
ig
n
WC
Data
(SA) PA (13)
PD
SLA
61
es
(SA) 555
80
(SA) 555
(SA) AAA
(SA) AAA
70
(SA) 555
(SA) AAA
PD
10
30
(SA)
RR
71
(SA) 555
51
50
ec
XXX
R
(SA) AAA
(SA) 555
ot
3
(SA) AAA
29
(SA) 555
N
Sector Lock/Unlock
(SA) 555
25
(SA) 555
D
F0
Data
ew
Write Buffer Load (9)
XX
(SA) AAA
Data
Fourth
Addr
Byte
Word
rN
1
RD
Third
Addr
Byte
Word
d
Reset
Data
RA
Addr
Byte
Word
om
m
en
1
Addr
Byte
Word
fo
Command Sequence
Read
Second
de
Cycles
First
AAA
555
AAA
555
B0
30
33
555
60
AAA
555
60
AAA
60
SLA
60
60
SLA
61
ID/CFI
ID/CFI Command Definitions
(SA) XAA
ID/CFI Entry (8) (11)
1
ID/CFI Read
1
(SA) RA
ID/CFI Exit
1
XXX
(SA) X55
90 or 98
data
F0
Configuration Command Definitions
Document Number: 002-01101 Rev. *I
Page 63 of 77
S29WS512R
S29WS256R, S29WS128R
Table 12.1 Command Definitions (Sheet 2 of 2)
Bus Cycles (Notes 1–5)
Addr
Byte
Word
Data
(SA) AAA
Configuration Register
Entry (8) (11)
1
Write Buffer Load
3
Buffer to Flash
(Configuration Register)
1
Configuration Register
Read
1
(SA)
X00(SA) X00
RR
Configuration Register Exit
1
XXX
F0
Addr
Byte
Word
Third
Addr
Byte
Word
Data
(SA) AAA
25
(SA) 555
(SA) AAA
(SA) 555
(SA) AAA
(SA)
X00(SA) X00
0
40
(SA) 555
(SA) AAA
25
(SA) 555
(SA) AAA
1
(SA) XXX
SSR Lock Exit
1
XXX
(SA) 555
(SA) AAA
29
(SA) 555
SSR Lock Read
PD
D
1
(SA) AAA
RR
F0
0
ew
Buffer to Flash
(SA) PA (13)
29
(SA) 555
(SA) 00
FE
(SA) PA (12)
PD
rN
3
PD
fo
Write Buffer Load (9)
Data
d
SSR Lock
1
Data
D0
(SA) 555
SSR Lock Command Definitions
SSR Lock Entry (8) (11)
Fourth
Addr
Byte
Word
ig
n
Configuration Register
Command Sequence
Second
es
Cycles
First
Write Buffer Load (9)
88
de
(SA) AAA
1
om
m
en
Secure Silicon Region Entry
(8) (11)
(SA) 555
(SA) AAA
4-35
(SA) 555
(SA) AAA
25
1
Secure Silicon Region Read
1
(SA) RA
RD
Secure Silicon Region Exit
1
XXX
F0
ec
(SA) 555
(SA) 555
(SA) AAA
WC
29
Buffer to Flash
R
Secure Silicon Region
Secure Silicon Region Command Definitions
N
ot
Legend
X = Don’t care
RA = Address of the location to be read.
RD = Read Data from location RA during read operation.
RR = Read Register value
PA = Address of the memory location to be programmed.
PD = Data to be programmed at location PA.
BA = Address bits sufficient to select a bank
SA = Address bits sufficient to select a sector
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes
1. See Section 8., Device Operations on page 23 for description of bus operations.
2. All values are in hexadecimal. All addresses are shown both in terms of system viewpoint byte address above the flash viewpoint word address where system address
a-max to a1 is connected to flash A-max to A0. Low order address bit patterns in commands, that are below the bits that specify (BA) or (SA), are relevant only on
system address signals a11 to a1 i.e. flash address signals A10 to A0. In commands using address bit patterns as part of the command recognition the address bits
above system a11 (flash A10) and below (BA) or (SA) are don’t care. System a0 is also don’t care because it is not connected to the flash address inputs.
3. Except for the following, all bus cycles are write cycle: read cycle during Read, ID/CFI Read (Manufacturing ID, Device ID, Indicator Bits), Configuration Register read,
Secure Silicon Region Read, SSR Lock Read, and 2nd cycle of Status Register Read
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, and WD.
5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset
command to return the device to reading array data
Document Number: 002-01101 Rev. *I
Page 64 of 77
S29WS512R
S29WS256R, S29WS128R
6. The Program Resume command is valid only during the Program Suspend mode/state.
7. The Erase Resume command is valid only during the Erase Suspend mode/state.
8. Command is valid when all banks are ready to read array data.
9. The total number of cycles in the command sequence is determined by the number of words written to the write buffer.
10. ACC must be at VHH during the entire operation of this command
11. Entry commands are needed to enter a specific mode to enable instructions only available within that mode.
12. Must be the lowest word address of the words being programmed within the 32 word write buffer page. This is not necessarily the lowest address of the page. Data
words are loaded into the write page buffer in sequential order from lowest to highest address.
13. Subsequent addresses must fall within the same Sector and Page as the initial starting address.
14. Blank Check is only functional in Asynchronous Read mode (Configuration Register - CR[15] = 1).
12.2
Device ID and Common Flash Memory Interface Address Map
es
ig
n
The Device ID fields occupy the first 32 bytes of address space followed by the Common Flash Interface data structure. The
Common Flash Interface (CFI) specification defines a standardized data structure containing device specific parameter, structure,
and feature set information, which allows vendor-specified software algorithms to be used for entire families of devices. Software
support can then be device-independent, JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash
device families. Flash driver software can be standardized for long-term compatibility.
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
This device enters the ID/CFI mode when the system writes the ID/CFI Query command, 90h or 98h, to address (SA)55h any time
all banks are in read mode (the CU is in Idle State). The system can then read ID and CFI information at the addresses, within the
selected sector, given in the following tables. To terminate reading ID/CFI, the system must write the reset command.
Document Number: 002-01101 Rev. *I
Page 65 of 77
S29WS512R
S29WS256R, S29WS128R
(SA) + 00h
(SA) + 01h
(SA) + 02h
WS256R
WS128R
Description
0001h
(WS) 007Eh
Spansion Manufacturer ID
Device ID, Word 1 Extended ID address code. Indicates
(WS) 007Eh (WS) 007Eh an extended two byte device ID is located at byte
address 1Ch and 1Eh.
(SA) + 02h
(SA) + 04h
00FFh
Reserved
(SA) + 03h
(SA) + 06h
00FFh
Revision ID
Reserved
(SA) + 04h
(SA) + 08h
00FFh
(SA) + 05h
(SA) + 0Ah
00FFh
Reserved
(SA) + 06h
(SA) + 0Ch
00FFh
ID Version
(SA) + 07h
(SA) + 0Eh
00BFh
Reserved
(SA) + 08h
(SA) + 10h
00FFh
Reserved
(SA) + 09h
(SA) + 12h
00FFh
Reserved
(SA) + 0Ah
(SA) + 14h
00FFh
Reserved
(SA) + 0Bh
(SA) + 16h
00FFh
Reserved
ew
00FF
Lower Software Bits
om
m
en
Bit 3-2 - Command Set Support
11 = Reserved
10 = Reserved
01 = Reduced Command Set
00 = Old Command Set
fo
Bit 1 - DQ Polling Support
1 = DQ bits polling supported
0 = DQ bits polling not supported
d
(SA) + 18h
rN
Bit 0 - Status Register Support
1 = Status Register Supported
0 = Status register not Supported
(SA) + 0Ch
ig
n
(SA) + 00h
DATA
WS512R
es
Byte Offset
Address
D
Word Offset
Address
de
Device Identification
Table 12.2 ID/CFI Data (Sheet 1 of 5)
Bit 4-F - 00Fh - Reserved
(SA) + 1Ah
00FFh
(SA) + 0Eh
(SA) + 1Ch
0025h
(SA) + 0Fh
(SA) + 1Eh
0003h
R
CFI
0027h
High Order Device ID, Word 2
0003h
0003h
Low Order Device ID, Word 3
CFI Query Identification String
(SA) + 20h
(SA) + 11h
(SA) + 22h
(SA) + 12h
(SA) + 24h
0059h
(SA) + 13h
(SA) + 26h
0002h
(SA) + 14h
(SA) + 28h
0000h
(SA) + 15h
(SA) + 2Ah
0040h
(SA) + 16h
(SA) + 2Ch
0000h
(SA) + 17h
(SA) + 2Eh
0000h
(SA) + 18h
(SA) + 30h
0000h
(SA) + 19h
(SA) + 32h
0000h
(SA) + 1Ah
(SA) + 34h
0000h
N
ot
(SA) + 10h
Document Number: 002-01101 Rev. *I
Upper Software Bits
Reserved
0026h
ec
(SA) + 0Dh
0051h
0052h
Query Unique ASCII string “QRY”
Primary Algorithm Command Set (Spansion = 0002h)
Address for Primary Extended Table
Alternate Algorithm Command Set (00h = none exists)
Address for Secondary Algorithm extended Query Table
(00h = none exists)
Page 66 of 77
S29WS512R
S29WS256R, S29WS128R
Table 12.2 ID/CFI Data (Sheet 2 of 5)
Word Offset
Address
Byte Offset
Address
DATA
WS512R
WS256R
WS128R
Description
System Interface String
(SA) + 36h
VCC Logic Supply Minimum Program/Erase
or Write voltage
0017h
D7-D4: Volt
D3-D0: 100 millivolt
VCC Logic Supply Maximum Program/Erase
or Write voltage
(SA) + 1Ch
(SA) + 38h
0019h
(SA) + 1Dh
(SA) + 3Ah
0085h
VPP [Programming] Supply Minimum Program/Erase
voltage (00h = no VPP pin present)
(SA) + 1Eh
(SA) + 3Ch
0095h
VPP [Programming] Supply Maximum Program/Erase
voltage (00h = no VPP pin present)
(SA) + 1Fh
(SA) + 3Eh
0008h
Typical Word Programming Time per single word 2N s
(e.g. < or = 32 s)
(SA) + 20h
(SA) + 40h
0009h
Typical Program Time for programming the complete
buffer 2N s (e.g. < or = 256 s) (00h = not supported)
(SA) + 21h
(SA) + 42h
000Ah
Typical Time for Sector Erase 2N s
(SA) + 22h
(SA) + 44h
(SA) + 23h
(SA) + 46h
0003h
Max. Program Time per single word
[2N times typical value]
(SA) + 24h
(SA) + 48h
0003h
Max. Program Time using buffer [2N times typical value]
(SA) + 25h
(SA) + 4Ah
0003h
(SA) + 26h
(SA) + 4Ch
0003h
ig
n
es
D
ew
rN
Typical Time for full chip erase 2N s
(00h = not supported)
d
fo
0011h
Max. Time for sector erase [2N times typical value]
de
0012h
om
m
en
0013h
D7-D4: Volt
D3-D0: 100 millivolt
Max. Time for full chip erase [2N times typical value]
(00h = not supported)
N
ot
R
ec
Common Flash Interface
(SA) + 1Bh
Document Number: 002-01101 Rev. *I
Page 67 of 77
S29WS512R
S29WS256R, S29WS128R
Table 12.2 ID/CFI Data (Sheet 3 of 5)
Word Offset
Address
Byte Offset
Address
DATA
WS512R
WS256R
WS128R
Description
Device Geometry Definition
(SA) + 27h
(SA) + 4Eh
001Ah
0019h
0018h
Device Size = 2N byte
Flash Device Interface
0h = x8
1h = x16
2h = x8/x16
3h = x32 [lower byte]
(SA) + 28h
(SA) + 50h
0001h
(SA) + 29h
(SA) + 52h
0000h
[upper byte] (00h = not supported)
Max. number of bytes in multi-byte buffer write = 2N
[lower byte]
(SA) + 2Bh
(SA) + 56h
0000h
0002h Top or Bottom
00FEh
007Eh
(Top Boot)
(Top Boot)
(SA) + 5Ah
0003h (Bottom Boot)
(SA) + 5Eh
(SA) + 30h
(SA) + 60h
000h
(Bottom Boot)
0000h
(Bottom Boot)
0000h (Top Boot or Uniform)
0080h (Bottom Boot)
0000h (Bottom Boot)
0002h (Top Boot or Uniform)
0003h
00FEh
R
(SA) + 62h
000h (Top
Boot)
(SA) + 64h
0003h
(Top Boot)
00FEh
007Eh
(Bottom
Boot)
(Bottom
Boot)
[lower byte] - Sector Size in bytes divided by 256
(n [bytes]h = sector size / 256)
[upper byte]
00FFh (Uniform)
N
ot
(Bottom Boot)
(SA) + 32h
0003h
(Top Boot)
ec
(Top Boot)
(SA) + 31h
[upper byte]
de
(SA) + 2Fh
0000h
(Top Boot or Uniform)
om
m
en
Common Flash Interface
(SA) + 5Ch
0001h
(Top Boot or
Uniform)
Erase Block Region 1 information
[lower byte] - Number of Erase sectors minus one, of
identical size within the Erase Block Region.
Example:
00h = 1 sector;
01h = 2 sectors
rN
007Fh
(Uniform)
00FFh (Uniform)
(SA) + 2Eh
es
0001h Uniform
(SA) + 58h
fo
(SA) + 2Dh
Number of Erase Block Regions within device
(Number of regions within the device containing one or
more contiguous Erase Blocks of the same size)
d
(SA) + 2Ch
[upper byte] (00h = not supported)
ig
n
0006h
D
(SA) + 54h
ew
(SA) + 2Ah
0000h
(Top Boot)
0001h
(Bottom Boot)
0000h
(Top Boot)
Erase block Region 2 Information
0000h (Bottom Boot)
00FFh
(Uniform)
(SA) + 33h
(SA) + 34h
(SA) + 66h
(SA) + 68h
0000h (Bottom Boot or Uniform)
0080h (Top Boot)
0002h (Bottom Boot)
0000h (Top Boot or Uniform)
Document Number: 002-01101 Rev. *I
Page 68 of 77
S29WS512R
S29WS256R, S29WS128R
Table 12.2 ID/CFI Data (Sheet 4 of 5)
Word Offset
Address
Byte Offset
Address
DATA
WS512R
WS256R
WS128R
Description
Primary Algorithm-Specific Extended Query
(SA) + 40h
(SA) + 80h
0050h
(SA) + 41h
(SA) + 82h
0052h
(SA) + 42h
(SA) + 84h
0049h
(SA) + 43h
(SA) + 86h
0031h
Major CFI version number, ASCII
(SA) + 44h
(SA) + 88h
0034h
Minor CFI version number, ASCII
0020h
Address Sensitive Unlock (Bits 1-0):
00b = Required
01b = Not required
Process Technology (Bits 5-2)
0011b = 130 nm Floating-Gate Technology
0100b = 110 nm MirrorBit Technology
0101b = 90 nm Floating-Gate Technology
0110b = 90 nm MirrorBit Technology
1000b = 65 nm MirrorBit Technology
ig
n
(SA) + 8Ah
(SA) + 8Ch
0002h
(SA) + 47h
(SA) + 8Eh
0001h
(SA) + 48h
(SA) + 90h
0000h
0= Not supported
1 = To Read Only
2 = To Read & Write
rN
(SA) + 46h
ew
Erase Suspend
D
es
(SA) + 45h
Query Unique ASCII string “PRI”
Sector Protection per Group
de
Sector Temporary Unprotect
00h = Not Supported
(SA) + 92h
(SA) + 4Ah
(SA) + 94h
(SA) + 4Bh
(SA) + 96h
0009h
0020h
0010h
0008h
ec
(SA) + 49h
om
m
en
01h = Supported
0001h
(SA) + 4Dh
(SA) + 4Eh
(SA) + 98h
0002h (WS-R)
N
(SA) + 4Ch
ot
R
Common Flash Interface
d
fo
0 = not Supported
X = number of sectors in per group
(SA) + 9Ah
(SA) + 9Ch
Sector Protect/Unprotect scheme
08h = Advanced Sector Protection
09h = Single-Sector Lock + Sector Lock Range
Simultaneous Operations
Number of Sectors in all banks except Boot Bank
Burst Mode Type
00h = Not Supported
01h = Supported
Page Mode Type
00h = Not Supported
01h = 4-Word Page
02h = 8-Word Page
04h = 16-Word Page
0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported
D7-D4: Volt
D3-D0: 100 millivolt
0095h
ACC (Acceleration) Supply Maximum
00h = Not Supported
D7-D4: Volt
D3-D0: 100 millivolt
Top/Bottom Sector Flag
0003h (Top Boot)
(SA) + 4Fh
(SA) + 9Eh
0002h (Bottom Boot)
0000h (Uniform or No Boot)
00h = No Boot
01h = Dual Boot
02h = Bottom boot
03h = Top boot
04h = Uniform Bottom Boot
05h = Uniform Top Boot;
Program Suspend
(SA) + 50h
(SA) + A0h
Document Number: 002-01101 Rev. *I
0001h
00h = Not Supported
01h= Supported
Page 69 of 77
S29WS512R
S29WS256R, S29WS128R
Table 12.2 ID/CFI Data (Sheet 5 of 5)
Word Offset
Address
(SA) + 51h
Byte Offset
Address
DATA
WS512R
WS256R
(SA) + A2h
Description
Unlock Bypass
0000h
00h = Not Supported
(SA) + A4h
0008h
(SA) + 53h
(SA) + A6h
000Eh
Hardware Reset Low Time-out until reset is completed
during an embedded algorithm - Maximum 2N ns
(e.g. 10 s => n = E)
(SA) + 54h
(SA) + A8h
000Eh
Hardware Reset Low Time-out until reset is completed
not during an embedded algorithm - Maximum 2N ns
(e.g. 10 s => n = E)
(SA) + 55h
(SA) + AAh
0005h
Erase Suspend Time-out Maximum 2N µs
(SA) + 56h
(SA) + ACh
0005h
Program Suspend Time-out Maximum 2N µs
(SA) + 57h
(SA) + AEh
0010h
Bank Organization: X= Number of banks
000Bh
(Bottom
Boot)
(SA) + B0h
0020h
0010h
0008h
(Top Boot or
Uniform)
(Top Boot or
Uniform)
(Top Boot or
Uniform)
Bank 0 Region Information.
X= Number of sectors in bank
ew
(SA) + 58h
es
(Bottom
Boot)
D
(Bottom Boot)
rN
0013h
ig
n
(SA) + 52h
Secure Silicon Region (Customer SSR Area) Size 2N
bytes
0023h
(SA) + B2h
0020h
0010h
0008h
Bank 1 Region Information.
X= Number of sectors in bank
(SA) + 5Ah
(SA) + B4h
0020h
0010h
0008h
Bank 2 Region Information.
X= Number of sectors in bank
(SA) + 5Bh
(SA) + B6h
0020h
0010h
0008h
(SA) + 5Ch
(SA) + B8h
0020h
(SA) + 5Dh
(SA) + BAh
0020h
(SA) + 5Eh
(SA) + BCh
0020h
(SA) + 5Fh
(SA) + BEh
0020h
(SA) + 60h
(SA) + C0h
0020h
(SA) + 61h
(SA) + C2h
(SA) + 62h
om
m
en
de
d
fo
(SA) + 59h
Bank 3 Region Information.
X= Number of sectors in bank
0008h
Bank 4 Region Information.
X= Number of sectors in bank
0010h
0008h
Bank 5 Region Information.
X= Number of sectors in bank
0010h
0008h
Bank 6 Region Information.
X= Number of sectors in bank
0010h
0008h
Bank 7 Region Information.
X= Number of sectors in bank
0010h
0008h
Bank 8 Region Information.
X= Number of sectors in bank
0020h
0010h
0008h
Bank 9 Region Information.
X= Number of sectors in bank
(SA) + C4h
0020h
0010h
0008h
Bank 10 Region Information.
X= Number of sectors in bank
(SA) + 63h
(SA) + C6h
0020h
0010h
0008h
Bank 11 Region Information.
X= Number of sectors in bank
(SA) + 64h
(SA) + C8h
0020h
0010h
0008h
Bank 12 Region Information.
X= Number of sectors in bank
(SA) + 65h
(SA) + CAh
0020h
0010h
0008h
Bank 13 Region Information.
X= Number of sectors in bank
(SA) + 66h
(SA) + CCh
0020h
0010h
0008h
Bank 14 Region Information.
X= Number of sectors in bank
(SA) + 67h
ot
R
ec
0010h
N
Common Flash Interface
WS128R
(SA) + CEh
0023h
0013h
000Bh
(Top Boot)
(Top Boot)
(Top Boot)
0020h
(Bottom Boot
or Uniform)
Document Number: 002-01101 Rev. *I
0010h
0008h
(Bottom
Boot or
Uniform)
(Bottom
Boot or
Uniform)
Bank 15 Region Information.
X= Number of sectors in bank
Page 70 of 77
S29WS512R
S29WS256R, S29WS128R
13. Revision History
Section
Description
Revision 01 (March 28, 2007)
Initial release
Revision 02 (April 24, 2007)
Device ID and Common Flash Memory
Interface Address Map
Updated device ID for word offset 03H to 00FFh
Revision 03 (March 19, 2008)
Changed Typical value from 4.7µs to 9.6 µs
Effective Write Buffer Programming
(VACC) Per Byte
Changed Typical value from 2.5 µs to 6 µs
Typical Program & Erase Time
Change Sector Erase (32 KByte Sector) from 0.3s to 0.355s
Product Ordering Information
Added package, boot configuration and frequency information to ordering information
es
ig
n
Effective Write Buffer Programming
(VCC) Per Byte
Removed WS2901GR
D
Valid Combination Table
Added model # 00 and 02 for boot configuration
Renamed VPP to ACC
Input/Output Descriptions & Logic
Symbol
Removed A/D mux from I/O description
Pin Out Diagram
Removed WP# pin
Synchronous Read Wait State Table
Reformatted the frequency description
rN
ew
Block Diagram
fo
Removed Address multiplexing wording from AVD#
de
d
Added 83 MHz value for ICCB and ICC5
DC Characterization
Changed all 108 MHz to 104 MHz
om
m
en
Changed VLKO Min/Max from 1.3V/1.4V to 1.0V/1.1V
Synchronous Burst: Changed tBDH min from 5 ns for 66 MHz/83 MHz to 3 ns, 2.5 ns for 108 MHz/
133 Mhz to 2 ns for 104 Mhz/133 MHz
Asynchronous Read: Changed tWEA from 4 ns to tCLK
AC Characterization
Asyncronous Write: Change tESL and tPSL from 20 µs to 30 µs
ec
Added note 3 on AVD requirement to subsequent CLK cycle
Corrected Secure Silicon Region size to 512 Bytes
VCC Power Up
N
ot
Synchronous Burst Read Mode
R
Product Overview
Deleted wait state 2 from Wait State Tables Figure 7.1
Changed 256 Byte Boundary Crossing Latency additional wait states up to 2
Changed tVCS value to 300 µs
Changed VIOS value to 300 µs
Added tRPH to timing diagram
Wait State Configuration Register Setup
Corrected typo in table to wait state 13
Device ID and CFI Table
General update CFI values
Revision 04 (March 25, 2008)
Device ID and Common Flash Memory
Interface Table
Corrected CFI setting for 4Ah
Revision 05 (October 27, 2008)
Global
Removed 133 MHz speed option
Ordering Information & Valid
Combination Table
Added Low-Halogen Lead Free package option
Flash Memory Array
Updated table 6.6 to correct sector range for bank 16 of S29WS512R
Table 7.1 Device Bus Operation
Deleted Asynchronous Write (WE# latched Address)
Document Number: 002-01101 Rev. *I
Removed Standard Lead Free package option
Page 71 of 77
S29WS512R
S29WS256R, S29WS128R
Section
Description
Write Buffer Programming Command
Changed to word offset
AC Characterization
Changed Clock High or Low time (tCLK H/L) to .45 tCLK
Program/Erase Operation
Deleted 7.9.2 Programming of a previously programmed location
Deleted ACC mode from single word programming
Changed 32-word buffer programming performance VCC mode 400 µs, ACC mode to 256 µs
Change Chip Programming Time for VCC mode as below:
• 128 Mbit 105s typical 210s max
• 256 Mbit 210s typical 420s max
• 512 Mbit 420s typical 840s max
Changed sector erase time as follows:
• 128 Kbyte VCC: 0.8/1.3 (Note 6) (typ), 3.5/5.5 (max)
• 32 Kbyte VCC: 0.35/0.6 (Note 6) (typ), 2.0/3.5 (max)
• 128 Kbyte ACC: 0.8/1.3 (Note 6) (typ), 3.5/5.5 (max)
• 32 Kbyte ACC: 0.35/0.6 (Note 6) (typ), 2.0/3.5 (max)
Updated chip erase time (both VCC and VPP) as follows:
es
ig
n
Program and Erase Performance
rN
ew
D
• WS128R: 78/126 s (typ), 154/250 s (max)
• WS256R: 155/251 s (typ), 308/500 s (max)
• WS512R: 308/500 s (typ), 612/998 s (max)
Added Note 6 to state, The first value is excluding pre-programming time, while the second value is
inclusive of pre-programming for the FFFFh pattern, with status polling rate as 400 ns (typ).
fo
Added Note 7 to state, The erase time is calculated from the time of issuing erase command to the
completion of erase operation (indicated by status register).
Revision 06 (February 27, 2009)
Remove 1G product option
Ordering Information and Valid
Combinations
Add additional model numbers for uniform boot, 1 and 2CEs
om
m
en
de
d
Global
Device Operation
Blank Check Command functional in Asynchronous Read Mode only
DC Characteristics
Change ICCB for 83 MHz 16word burst to 26 mA
Effect Word Programming time using Write Buffer change to 12.5 µs for VCC mode and 8 µs for ACC
mode
Programming Performance
R
Ordering Information and Valid
Combinations
ec
Revision 07 (May 7, 2009)
VCC Power Up
N
ot
Input/Output Descriptions & Logic
Symbol
Device ID and Common Flash Memory
Interface Address Map
Removed model numbers 10, 30, 50
Input/Output Descriptions table – Updated ACC description
Removed tRH from table
ID/CFI Data table – Updated (SA) + 51h description
Revision 08 (June 1, 2010)
Sector Lock Range Command
Clarified Sector Lock Range command behavior
Revision 09 (September 19, 2011)
Global
Document Number: 002-01101 Rev. *I
Added product obsolescence information
Page 72 of 77
S29WS512R
S29WS256R, S29WS128R
Document History Page
Document Title: S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb (32/16/8M x 16 bit), 1.8 V, S29WS-R MirrorBit® Flash
Document Number: 002-01101
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
WIOB
03/28/2007
Initial release
*A
WIOB
04/24/2007
Device ID and Common Flash Memory Interface Address Map: Updated
device ID for word offset 03H to 00FFh
Description of Change
es
ig
n
Effective Write Buffer Programming (VCC) Per Byte: Changed Typical value
from 4.7µs to 9.6 µs
Effective Write Buffer Programming (VACC) Per Byte: Changed Typical value
from 2.5 µs to 6 µs
Typical Program & Erase Time: Change Sector Erase (32 KByte Sector) from
0.3s to 0.355s
Product Ordering Information: Added package, boot configuration and frequency information to ordering information
D
Valid Combination Table: Removed WS2901GR
ew
Added model # 00 and 02 for boot configuration
Block Diagram: Renamed VPP to ACC
fo
rN
Input/Output Descriptions & Logic Symbol: Removed A/D mux from I/O
description
Removed Address multiplexing wording from AVD#
̶
*B
om
m
en
de
d
Pin Out Diagram: Removed WP# pin
Synchronous Read Wait State Table: Reformatted the frequency description
DC Characterization: Added 83 MHz value for ICCB and ICC5 Changed all
108 MHz to 104 MHz
Changed VLKO Min/Max from 1.3V/1.4V to 1.0V/1.1V
03/19/2008
R
ec
WIOB
AC Characterization: Synchronous Burst: Changed tBDH min from 5 ns for 66
MHz/83 MHz to 3 ns, 2.5 ns for 108 MHz/133 Mhz to 2 ns for 104 Mhz/133
MHz
Asynchronous Read: Changed tWEA from 4 ns to tCLK
Asyncronous Write: Change tESL and tPSL from 20 µs to 30 µs
ot
Added note 3 on AVD requirement to subsequent CLK cycle
N
Product Overview: Corrected Secure Silicon Region size to 512 Bytes
Synchronous Burst Read Mode: Deleted wait state 2 from Wait State Tables
Figure 7.1Changed 256 Byte Boundary Crossing Latency additional wait
states up to 2
VCC Power Up: Changed tVCS value to 300 µs
Changed VIOS value to 300 µs
Added tRPH to timing diagram
Wait State Configuration Register Set-up: Corrected typo in table to wait state
13
*C
̶
WIOB
Document Number: 002-01101 Rev. *I
03/25/2008
Device ID and Common Flash Memory Interface Table: Corrected CFI setting
for 4Ah
Page 73 of 77
S29WS512R
S29WS256R, S29WS128R
Document History Page (Continued)
Document Title: S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb (32/16/8M x 16 bit), 1.8 V, S29WS-R MirrorBit® Flash
Document Number: 002-01101
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
̶
WIOB
10/27/2008
Change Chip Programming Time for VCC mode as below:
• 128 Mbit 105s typical 210s max
• 256 Mbit 210s typical 420s max
• 512 Mbit 420s typical 840s max
Changed sector erase time as follows:
de
d
fo
*D
rN
ew
D
es
ig
n
Global: Removed 133 MHz speed option
Ordering Information & Valid Combination Table: Added Low-Halogen Lead
Free package option
Removed Standard Lead Free package option
Flash Memory Array: Updated table 6.6 to correct sector range for bank 16 of
S29WS512R
Table 7.1 Device Bus Operation: Deleted Asynchronous Write (WE# latched
Address)
Write Buffer Programming Command: Changed to word offset
AC Characterization: Changed Clock High or Low time (tCLK H/L) to .45 tCLK
Program/Erase Operation: Deleted 7.9.2 Programming of a previously programmed location
Program and Erase Performance: Deleted ACC mode from single word programming
Changed 32-word buffer programming performance VCC mode 400 µs, ACC
mode to 256 µs
N
ot
R
ec
om
m
en
• 128 Kbyte VCC: 0.8/1.3 (Note 6) (typ), 3.5/5.5 (max)
• 32 Kbyte VCC: 0.35/0.6 (Note 6) (typ), 2.0/3.5 (max)
• 128 Kbyte ACC: 0.8/1.3 (Note 6) (typ), 3.5/5.5 (max)
• 32 Kbyte ACC: 0.35/0.6 (Note 6) (typ), 2.0/3.5 (max)
Updated chip erase time (both VCC and VPP) as follows:
̶
WIOB
*E
*F
̶
WIOB
Document Number: 002-01101 Rev. *I
• WS128R: 78/126 s (typ), 154/250 s (max)
• WS256R: 155/251 s (typ), 308/500 s (max)
• WS512R: 308/500 s (typ), 612/998 s (max)
Added Note 6 to state, The first value is excluding pre-programming time,
while the second value is inclusive of pre-programming for the FFFFh pattern,
with status polling rate as 400 ns (typ).
Added Note 7 to state, The erase time is calculated from the time of issuing
erase command to the completion of erase operation (indicated by status register).
02/27/2009
Global: Remove 1G product option
Ordering Information and Valid Combinations: Add additional model numbers
for uniform boot, 1 and 2CEs
Device Operation: Blank Check Command functional in Asynchronous Read
Mode only
DC Characteristics: Change ICCB for 83 MHz 16word burst to 26 mA
Programming Performance: Effect Word Programming time using Write Buffer
change to 12.5 µs for VCC mode and 8 µs for ACC mode
05/07/2009
Ordering Information and Valid Combinations: Removed model numbers 10,
30, 50
Input/Output Descriptions & Logic Symbol: Input/Output Descriptions table –
Updated ACC description
VCC Power Up: Removed tRH from table
Device ID and Common Flash Memory Interface Address Map: ID/CFI Data
table – Updated (SA) + 51h description
Page 74 of 77
S29WS512R
S29WS256R, S29WS128R
Document History Page (Continued)
Document Title: S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb (32/16/8M x 16 bit), 1.8 V, S29WS-R MirrorBit® Flash
Document Number: 002-01101
Rev.
ECN No.
Orig. of
Change
*G
̶
Submission
Date
Description of Change
06/01/2011
Sector Lock Range Command: Clarified Sector Lock Range command behavior
̶
WIOB
18/19/2011
Global: Added product obsolescence information
*I
4953774
WIOB
10/09/2015
Updated to Cypress template.
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WIOB
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Document Number: 002-01101 Rev. *I
Page 75 of 77
S29WS512R
S29WS256R, S29WS128R
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
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psoc.cypress.com/solutions
Clocks & Buffers ................................ cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface......................................... cypress.com/go/interface
Cypress Developer Community
Lighting & Power Control............ cypress.com/go/powerpsoc
Community | Forums | Blogs | Video | Training
Memory........................................... cypress.com/go/memory
Technical Support
PSoC ....................................................cypress.com/go/psoc
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cypress.com/go/support
Touch Sensing .................................... cypress.com/go/touch
es
USB Controllers....................................cypress.com/go/USB
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Wireless/RF .................................... cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-01101 Rev. *I
®
®
®
®
Revised October 09, 2015
Page 76 of 76
Cypress , Spansion , MirrorBit , MirrorBit Eclipse™, ORNAND™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp.
All products and company names mentioned in this document may be the trademarks of their respective holders.
