S34ML02G200BHI000

S34ML01G2 S34ML02G2 S34ML04G2 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded Distinctive Characteristics ■ Density ❐ 1 Gb / 2 Gb / 4 Gb ❐ ■ Architecture ❐ Input / Output Bus Width: 8 bits / 16 bits ❐ Page size: • ×8: 1 Gb: (2048 + 64) bytes; 64-byte spare area 2 Gb / 4 Gb: (2048 + 128) bytes; 128-byte spare area • ×16: 1 Gb: (1024 + 32) words; 32-word spare area 2 Gb / 4 Gb (1024 + 64) words; 64-word spare area ❐ Block size: 64 Pages • ×8: 1 Gb: 128 KB+ 4 KB 2 Gb / 4 Gb: 128 KB + 8 KB • ×16 1 Gb: 64k + 2k words 2 Gb / 4 Gb: 64k + 4k words ❐ Plane size • ×8 1 Gb: 1024 blocks per plane or (128 MB + 4 MB 2 Gb: 1024 blocks per plane or (128 MB + 8 MB 4 Gb: 2048 blocks per plane or (256 MB + 16 MB • ×16 1 Gb: 1024 blocks per plane or (64M + 2M) words 2 Gb: 1024 Blocks per Plane or (64M + 4M) words 4 Gb: 2048 Blocks per Plane or (128M + 8M) words Device Size • 1 Gb: 1 plane per device or 128 Mbyte • 2 Gb: 2 planes per device or 256 Mbyte • 4 Gb: 2 planes per device or 512 Mbyte ■ NAND Flash interface ❐ Open NAND Flash Interface (ONFI) 1.0 compliant ❐ Address, Data, and Commands multiplexed ■ Supply Voltage ❐ 3.3-V device: VCC = 2.7 V ~ 3.6 V ■ Security ❐ One Time Programmable (OTP) area ❐ Serial number (unique ID) (Contact factory for support) ❐ Hardware program/erase disabled during power transition ■ Additional features ❐ 2 Gb and 4 Gb parts support Multiplane Program and Erase commands ❐ Supports Copy Back Program ❐ 2 Gb and 4 Gb parts support Multiplane Copy Back Program ❐ Supports Read Cache ■ Electronic signature ❐ Manufacturer ID: 01h ■ Operating temperature ❐ Industrial: –40 °C to 85 °C ❐ Industrial Plus: –40 °C to 105 °C Performance ■ ❐ Page Read / Program ❐ Random access: 25 µs (Max) (S34ML01G2) ❐ Random access: 30 µs (Max) (S34ML02G2, S34ML04G2) ❐ Sequential access: 25 ns (Min) ❐ Program time / Multiplane Program time: 300 µs (Typ) ■ Block Erase (S34ML01G2) ❐ Block Erase time: 3 ms (Typ) ■ Block Erase / Multiplane Erase (S34ML02G2, S34ML04G2) ❐ Block Erase time: 3.5 ms (Typ) ■ Reliability ❐ 100,000 Program / Erase cycles (Typ) (with 4-bit ECC per 528 bytes (×8) or 264 words (×16)) Cypress Semiconductor Corporation Document Number: 002-00499 Rev. *Q • 10 Year Data retention (Typ) For one plane structure (1-Gb density) • Block zero is valid and will be valid for at least 1,000 program-erase cycles with ECC ❐ For two plane structures (2-Gb and 4-Gb densities) • Blocks zero and one are valid and will be valid for at least 1,000 program-erase cycles with ECC ❐ ■ 198 Champion Court Package options ❐ Pb-free and low halogen ❐ 48-Pin TSOP 12 × 20 × 1.2 mm ❐ 63-Ball BGA 9 × 11 × 1 mm ❐ 67-Ball BGA 8 × 6.5 × 1 mm (S34ML01G2, S34ML02G2) • San Jose, CA 95134-1709 • 408-943-2600 Revised April 13, 2018 S34ML01G2 S34ML02G2 S34ML04G2 Contents 1. 1.1 1.2 1.3 1.4 1.5 1.6 1.7 General Description..................................................... 4 Logic Diagram................................................................ 5 Connection Diagram ...................................................... 6 Pin Description............................................................... 8 Block Diagram................................................................ 9 Array Organization ......................................................... 9 Addressing ................................................................... 11 Mode Selection ............................................................ 14 2. 2.1 2.2 2.3 2.4 2.5 2.6 Bus Operation ............................................................ Command Input ........................................................... Address Input............................................................... Data Input .................................................................... Data Output.................................................................. Write Protect ................................................................ Standby........................................................................ 15 15 15 15 15 15 15 3. 3.1 3.2 3.3 16 17 17 3.15 3.16 3.17 3.18 3.19 3.20 Command Set............................................................. Page Read ................................................................... Page Program.............................................................. Multiplane Program — S34ML02G2 and S34ML04G2..................................... Page Reprogram.......................................................... Block Erase.................................................................. Multiplane Block Erase — S34ML02G2 and S34ML04G2..................................... Copy Back Program..................................................... Read Status Register................................................... Read Status Enhanced — S34ML02G2 and S34ML04G2..................................... Read Status Register Field Definition .......................... Reset............................................................................ Read Cache ................................................................. Cache Program............................................................ Multiplane Cache Program — S34ML02G2 and S34ML04G2..................................... Read ID........................................................................ Read ID2...................................................................... Read ONFI Signature .................................................. Read Parameter Page ................................................. Read Unique ID (Contact Factory)............................... One-Time Programmable (OTP) Entry ........................ 25 26 28 28 29 31 32 4. 4.1 4.2 4.3 Signal Descriptions ................................................... Data Protection and Power On / Off Sequence ........... Ready/Busy.................................................................. Write Protect Operation ............................................... 33 33 33 34 5. 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Electrical Characteristics .......................................... Valid Blocks ................................................................. Absolute Maximum Ratings ......................................... Recommended Operating Conditions.......................... AC Test Conditions ...................................................... AC Characteristics ....................................................... DC Characteristics ....................................................... Pin Capacitance........................................................... Thermal Resistance ..................................................... 35 35 35 35 35 36 37 38 38 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 Document Number: 002-00499 Rev. *Q 18 18 20 20 21 22 22 22 23 23 24 5.9 Program / Erase Characteristics ................................... 38 6. 6.1 6.2 6.3 6.4 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 Timing Diagrams......................................................... 39 Command Latch Cycle.................................................. 39 Address Latch Cycle ..................................................... 39 Data Input Cycle Timing................................................ 40 Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H)............................... 40 Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L) .......................... 41 Page Read Operation ................................................... 41 Page Read Operation (Interrupted by CE#) ..................................................... 42 Page Read Operation Timing with CE# Don’t Care ..................................................... 42 Page Program Operation .............................................. 43 Page Program Operation Timing with CE# Don’t Care ..................................................... 43 Page Program Operation with Random Data Input ............................................... 44 Random Data Output In a Page ................................... 44 Multiplane Page Program Operation — S34ML02G2 and S34ML04G2 ..................................... 45 Block Erase Operation .................................................. 46 Multiplane Block Erase — S34ML02G2 and S34ML04G2 ..................................... 46 Copy Back Read with Optional Data Readout .............. 47 Copy Back Program Operation With Random Data Input............................................... 47 Multiplane Copy Back Program — S34ML02G2 and S34ML04G2 ..................................... 48 Read Status Register Timing ........................................ 49 Read Status Enhanced Timing ..................................... 49 Reset Operation Timing ................................................ 49 Read Cache .................................................................. 50 Cache Program............................................................. 52 Multiplane Cache Program — S34ML02G2 and S34ML04G2 ..................................... 53 Read ID Operation Timing ............................................ 55 Read ID2 Operation Timing .......................................... 55 Read ONFI Signature Timing........................................ 56 Read Parameter Page Timing ...................................... 56 Read Unique ID Timing (Contact Factory).................... 56 OTP Entry Timing ......................................................... 57 Power On and Data Protection Timing ......................... 57 WP# Handling............................................................... 57 7. 7.1 Physical Interface ....................................................... 58 Physical Diagram .......................................................... 58 8. System Interface ......................................................... 61 9. 9.1 9.2 Error Management ...................................................... 62 System Bad Block Replacement................................... 62 Bad Block Management................................................ 63 10. Ordering Information .................................................. 64 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 Page 2 of 71 S34ML01G2 S34ML02G2 S34ML04G2 11. Document History ...................................................... 65 Sales, Solutions, and Legal Information ...........................71 Worldwide Sales and Design Support ........................... 71 Products ........................................................................ 71 Document Number: 002-00499 Rev. *Q PSoC® Solutions .......................................................... 71 Cypress Developer Community ..................................... 71 Technical Support ......................................................... 71 Page 3 of 71 S34ML01G2 S34ML02G2 S34ML04G2 1. General Description The S34ML01G2, S34ML02G2, and S34ML04G2 series is offered with a 3.3-V VCC power supply, and with x8 or x16 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for x8 is (2048 + spare) bytes; for x16 (1024 + spare) words. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory. The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device by a microcontroller, since the CE# transitions do not stop the read operation. The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load the data in a cache register while the previous data is transferred to the I/O buffers to be read. Like all other 2-kB page NAND flash devices, a program operation typically writes 2 KB (×8) or 1 kword (×16) in 300 µs and an erase operation can typically be performed in 3 ms (S34ML01G2) on a 128-kB block (×8) or 64k-word block (×16). In addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%. In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of the footprint. Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins. The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required, and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase operations. The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a single pull-up resistor. In a system with multiple memories the R/B# pins can be connected all together to provide a global status signal. The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed. In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data using the cache register. The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-program operations. The devices are available in the TSOP48 (12 x 20 mm) package and come with the following security features:  OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently.  Serial number (unique identifier), which allows the devices to be uniquely identified. Contact factory for support of this feature. These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the datasheet. For more details about them, contact your nearest sales office. Document Number: 002-00499 Rev. *Q Page 4 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Table 1. Product List Density (bits) Number of Planes Number of Blocks per Plane 4M x 8 2M x 16 1 1024 256M x 8 128M x 16 16M x 8 8M x 16 2 1024 512M x 8 256M x 16 32M x 8 16M x 16 2 2048 Device 1.1 Main Spare S34ML01G2 128M x 8 64M x 16 S34ML02G2 S34ML04G2 Logic Diagram Figure 1. Logic Diagram VCC I/O0~I/O7 CE# WE# R/B# RE# ALE CLE WP# VSS Table 2. Signal Names Signal I/O7 - I/O0 (×8) I/O8 - I/O15 (×16) Description Data Input / Outputs CLE Command Latch Enable ALE Address Latch Enable CE# Chip Enable RE# Read Enable WE# Write Enable WP# Write Protect R/B# Read/Busy VCC Power Supply VSS Ground NC Not Connected Document Number: 002-00499 Rev. *Q Page 5 of 71 S34ML01G2 S34ML02G2 S34ML04G2 1.2 Connection Diagram Figure 2. 48-Pin TSOP1 Contact ×8, ×16 Device x16 x8 NC NC NC NC NC NC R/B# RE# CE# NC NC VCC VSS NC NC CLE ALE WE# WP# NC NC NC NC NC NC NC NC NC NC NC R/B# RE# CE# NC NC VCC VSS NC NC CLE ALE WE# WP# NC NC NC NC NC x8 1 48 NAND Flash TSOP1 12 13 VSS I/O15 I/O14 I/O13 I/O7 I/O6 I/O5 I/O4 I/O12 VCC NC VCC VSS NC VCC I/011 NC I/O3 I/O3 I/O2 I/O2 I/O1 I/O1 I/O0 I/O0 I/O10 NC I/O9 NC I/O8 NC (1) VSS VSS 37 36 25 24 x16 VSS (1) NC NC NC I/O7 I/O6 I/O5 I/O4 NC VCC(1) NC VCC VSS NC VCC(1) Note 1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally. Figure 3. 63-BGA Contact, ×8 Device (Balls Down, Top View) A1 A2 A9 NC NC NC NC B1 B9 B10 NC NC NC C3 C4 C5 C6 C7 C8 WP# ALE VSS CE# WE# RB# D3 D4 D5 D6 D7 D8 VCC (1) RE# CLE NC NC NC E3 E4 E5 E6 E7 E8 NC NC NC NC NC NC F3 F4 F5 F6 F7 F8 NC NC NC NC VSS (1) NC G3 G4 G5 G6 G7 G8 NC VCC (1) NC NC NC NC H3 H4 H5 H6 H7 H8 NC I/O0 NC NC NC Vcc J3 J4 J5 J6 J7 J8 NC I/O1 NC VCC I/O5 I/O7 K3 K4 K5 K6 K7 K8 VSS I/O2 I/O3 I/O4 I/O6 VSS A10 L1 L2 L9 L10 NC NC NC NC M1 M2 M9 M10 NC NC NC NC Note 2. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally. Document Number: 002-00499 Rev. *Q Page 6 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Figure 4. 63-BGA Contact, x16 Device (Balls Down, Top View) A1 A2 A9 A10 NC NC NC NC B1 B9 B10 NC NC NC C3 C4 C5 C6 C7 C8 WP# ALE VSS CE# WE# RB# D3 D4 D5 D6 D7 D8 VCC RE# CLE NC NC NC E3 E4 E5 E6 E7 E8 NC NC NC NC NC NC F3 F4 F5 F6 F7 F8 NC NC NC NC VSS NC G3 G4 G5 G6 G7 G8 NC VCC NC I/O13 I/O15 NC H3 H4 H5 H6 H7 H8 I/O8 I/O0 I/O10 I/O12 I/O14 Vcc J3 J4 J5 J6 J7 J8 I/O9 I/O1 I/O11 VCC I/O5 I/O7 K3 K4 K5 K6 K7 K8 VSS I/O2 I/O3 I/O4 I/O6 VSS L1 L2 L9 L10 NC NC NC NC M1 M2 M9 M10 NC NC NC NC Figure 5. 67-BGA Contact (Balls Down, Top View) A2 A3 A6 A7 A8 NC NC NC NC NC B1 B2 B3 B4 B5 B6 B7 B8 NC WP# ALE VSS CE# WE# RY/BY# NC C1 C2 C3 C4 C5 C6 C7 C8 NC NC RE# CLE NC NC NC NC D2 D3 D4 D5 D6 D7 NC NC NC NC NC NC E2 E3 E4 E5 E6 E7 NC NC NC NC NC NC F2 F3 F4 F5 F6 F7 NC NC NC NC NC NC G2 G3 G4 G5 G6 G7 NC I/O0 NC NC NC VCC H1 H2 H3 H4 H5 H6 H7 H8 NC NC I/O1 NC VCC I/O5 I/O7 NC J1 J2 J3 J4 J5 J6 J7 J8 NC VSS I/O2 I/O3 I/O4 I/O6 VSS NC K1 K2 K3 K6 K7 K8 NC NC NC NC NC NC Document Number: 002-00499 Rev. *Q Page 7 of 71 S34ML01G2 S34ML02G2 S34ML04G2 1.3 Pin Description Table 3. Pin Description Pin Name I/O0 - I/O7 (×8) I/O8 - I/O15 (×16) Description Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The I/O pins float to High-Z when the device is deselected or the outputs are disabled. CLE Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising edge of Write Enable (WE#). ALE Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising edge of Write Enable (WE#). CE# Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory. WE# Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#. RE# Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE# which also increments the internal column address counter by one. WP# Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification (program / erase). R/B# Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory. VCC Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit prevents the insertion of Commands when VCC is less than VLKO. VSS Ground. NC Not Connected. Notes 3. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. 4. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions. Document Number: 002-00499 Rev. *Q Page 8 of 71 S34ML01G2 S34ML02G2 S34ML04G2 1.4 Block Diagram Figure 6. Functional Block Diagram Address Register/ Counter Program Erase Controller HV Generation 1024 Mbit + 32 Mbit (1 Gb Device) X 2048 Mbit + 128 Mbit (2 Gb Device) D E C O D E R 4096 Mbit + 256 Mbit (4 Gb Device) ALE CLE NAND Flash Memory Array WE# CE# WP# Command Interface Logic RE# PAGE Buffer Y Decoder Command Register I/O Buffer Data Register I/O0~I/O7 (x8) I/O0~I/O15 (x16) 1.5 Array Organization Figure 7. Array Organization — S34ML01G2 (×8) 1 Page = (2k + 64) Bytes Plane(s) 1024 Blocks per Plane 0 1 Block = (2k + 64) Bytes x 64 Pages = (128k + 4k) Bytes 1 1 Plane = (128k + 4k) Bytes x 1024 Blocks 2 1022 1023 I/O [7:0] Page Buffer 2048 Bytes 64 Bytes Array Organization (x8) Document Number: 002-00499 Rev. *Q Page 9 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Figure 8. Array Organization — S34ML01G2 (x16) 1 Page = (1k + 32) Words Plane(s) 1024 Blocks per Plane 0 1 Block = (1k + 32) Words x 64 Pages = (64k + 2k) Words 1 1 Plane = (64k + 2k) Words x 1024 Blocks 2 1022 1023 I/O0~I/O15 Page Buffer 1024 Words 32 Words Array Organization (x16) Figure 9. Array Organization — S34ML02G2 and S34ML04G2 (×8) 2176 Bytes 2176 Bytes I/O 7 Cache Register Data Register 2048 128 2048 128 2048 128 2048 128 I/O 0 1 Page = (2K+128) Bytes 1 Block = (2K+128) Bytes x 64 Pages S34ML02G2 has 1024 Blocks per Plane = (128K+8K) Bytes 1 Block 1 Block S34ML02G2 Device = (128K+8K) x 2048 Blocks S34ML04G2 has 2048 Blocks per Plane S34ML04G2 Device = (128K+8K) x 4096 Blocks Plane 0 Plane 1 Array Organization (x8) Document Number: 002-00499 Rev. *Q Page 10 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Figure 10. Array Organization — S34ML02G2 and S34ML04G2 (x16) 1088 Words 1088 Words I/O 15 Cache Register Data Register 1024 64 1024 64 1024 64 1024 64 I/O 0 1 Page = (1K+64) Words 1 Block = (1K+64) Words x 64 Pages S34ML02G2 has 1024 Blocks per Plane = (64K+4K) Words 1 Block S34ML04G2 has 2048 Blocks per Plane 1 Block S34ML02G2 Device = (64K+4K) x 2048 Blocks S34ML04G2 Device = (64K+4K) x 4096 Blocks Plane 1 Plane 0 Array Organization (x16) 1.6 Addressing 1.6.1 S34ML01G2 Table 4. Address Cycle Map — 1 Gb Device Bus Cycle I/O [15:8] (9) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) Low Low Low Low ×8 1st / Col. Add.1 — A0 (CA0) A1 (CA1) 2nd / Col. Add. 2 — A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) A2 (CA2) 3rd / Row Add. 1 — A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) 4th / Row Add. 2 — A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8) A27 (BA9) 1st / Col. Add.1 Low A0 (CA0) A1 (CA1) 2nd / Col. Add. 2 Low A8 (CA8) A9 (CA9) A10 (CA10) 3rd / Row Add. 1 Low A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) 4th / Row Add. 2 Low A19 (BA2) A20 (BA3) A21 (BA4) A22 (BA5) A23 (BA6) A24 (BA7) A25 (BA8) A26 (BA9) A16 (PA4) A17 (PA5) A18 (BA0) A19 (BA1) ×16 A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) Low Low Low Low Low A15 (PA4) A16 (PA5) A17 (BA0) A18 (BA1) Notes 5. CAx = Column Address bit. 6. PAx = Page Address bit. 7. BAx = Block Address bit. 8. Block address concatenated with page address = actual page address, also known as the row address. 9. I/O[15:8] are not used during the addressing sequence and should be driven Low. Document Number: 002-00499 Rev. *Q Page 11 of 71 S34ML01G2 S34ML02G2 S34ML04G2 For the ×8 address bits, the following rules apply: ■ A0 - A11: column address in the page ■ A12 - A17: page address in the block ■ A18 - A27: block address For the x16 address bits, the following rules apply:  A0 - A10: column address in the page  A11 - A16: page address in the block  A17 - A26: block address 1.6.2 S34ML02G2 Table 5. Address Cycle Map — 2 Gb Device Bus Cycle I/O [15:8] (15) I/O0 I/O1 I/O2 1st / Col. Add.1 — A0 (CA0) A1 (CA1) A2 (CA2) 2nd / Col. Add. 2 — A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) 3rd / Row Add. 1 — A12 (PA0) A13 (PA1) 4th / Row Add. 2 — A20 (BA1) A21 (BA2) A22 (BA3) 5th / Row Add. 3 — A28 (BA9) Low Low 1st / Col. Add.1 Low A0 (CA0) A1 (CA1) A2 (CA2) 2nd / Col. Add. 2 Low A8 (CA8) A9 (CA9) A10 (CA10) 3rd / Row Add. 1 Low A11 (PA0) A12 (PA1) 4th / Row Add. 2 Low A19 (BA1) A20 (BA2) A21 (BA3) 5th / Row Add. 3 Low A27 (BA9) I/O3 I/O4 I/O5 I/O6 I/O7 A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) Low Low Low Low A18 (PLA0) A19 (BA0) ×8 A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5) A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8) Low Low Low Low Low A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) Low Low Low Low Low A17 (PLA0) A18 (BA0) ×16 Low A13 (PA2) Low A14 (PA3) A15 (PA4) A16 (PA5) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8) Low Low Low Low Low Notes 10. CAx = Column Address bit. 11. PAx = Page Address bit. 12. PLA0 = Plane Address bit zero. 13. BAx = Block Address bit. 14. Block address concatenated with page address and plane address = actual page address, also known as the row address. 15. I/O[15:8] are not used during the addressing sequence and should be driven Low. For the ×8 address bits, the following rules apply: ■ A0 - A11: column address in the page ■ A12 - A17: page address in the block ■ A18: plane address (for multiplane operations) / block address (for normal operations) ■ A19 - A28: block address Document Number: 002-00499 Rev. *Q Page 12 of 71 S34ML01G2 S34ML02G2 S34ML04G2 For the x16 address bits, the following rules apply: ■ A0 - A10: column address in the page ■ A11 - A16: page address in the block ■ A17: plane address (for multiplane operations) / block address (for normal operations) ■ A18 - A27: block address 1.6.3 S34ML04G2 Table 6. Address Cycle Map — 4 Gb Device Bus Cycle I/O [15:8] (21) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) Low Low Low Low A18 (PLA0) A19 (BA0) ×8 1st / Col. Add.1 — A0 (CA0) A1 (CA1) 2nd / Col. Add. 2 — A8 (CA8) A9 (CA9) A2 (CA2) 3rd / Row Add. 1 — A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) 4th / Row Add. 2 — A20 (BA1) A21 (BA2) A22 (BA3) A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8) 5th / Row Add. 3 — A28 (BA9) A29 (BA10) Low A10 (CA10) A11 (CA11) A16 (PA4) A17 (PA5) Low Low Low Low Low ×16 1st / Col. Add.1 Low A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7) 2nd / Col. Add. 2 Low A8 (CA8) A9 (CA9) A10 (CA10) Low Low Low Low Low 3rd / Row Add. 1 Low A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A17 (PLA0) A18 (BA0) 4th / Row Add. 2 Low A19 (BA1) A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8) 5th / Row Add. 3 Low A27 (BA9) A28 (BA10) Low Low A15 (PA4) A16 (PA5) Low Low Low Low Notes 16. CAx = Column Address bit. 17. PAx = Page Address bit. 18. PLA0 = Plane Address bit zero. 19. BAx = Block Address bit. 20. Block address concatenated with page address and plane address = actual page address, also known as the row address. 21. I/O[15:8] are not used during the addressing sequence and should be driven Low. For the ×8 address bits, the following rules apply: ■ A0 - A11: column address in the page ■ A12 - A17: page address in the block ■ A18: plane address (for multiplane operations) / block address (for normal operations) ■ A19 - A29: block address For the x16 address bits, the following rules apply: ■ A0 - A10: column address in the page ■ A11 - A16: page address in the block ■ A17: plane address (for multiplane operations) / block address (for normal operations) ■ A18 - A28: block address Document Number: 002-00499 Rev. *Q Page 13 of 71 S34ML01G2 S34ML02G2 S34ML04G2 1.7 Mode Selection Table 7. Mode Selection Mode CLE ALE CE# WE# RE# WP# Command Input High Low Low Rising High X Address Input Low High Low Rising High X Command Input High Low Low Rising High High Address Input Low High Low Rising High High Data Input Low Low Low Rising High High Data Output (on going) Low Low Low High Falling X Read Mode Program or Erase Mode Data Output (suspended) X X X High High X Busy Time in Read X X X High High (24) X Busy Time in Program X X X X X High Busy Time in Erase X X X X X High Write Protect X X X X X Low X 0V / VCC (23) Stand By X X High X Notes 22. X can be VIL or VIH. High = Logic level high, Low = Logic level low. 23. WP# should be biased to CMOS high or CMOS low for stand-by mode. 24. During Busy Time in Read, RE# must be held high to prevent unintended data out. Document Number: 002-00499 Rev. *Q Page 14 of 71 S34ML01G2 S34ML02G2 S34ML04G2 2. Bus Operation There are six standard bus operations that control the device: Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. (See Table 7.) Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus operations. 2.1 Command Input The Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 15 and Figure 23 for details of the timing requirements. Command codes are always applied on I/O7:0 regardless of the bus configuration (×8 or ×16). 2.2 Address Input The Address Input bus operation allows the insertion of the memory address. For the S34ML02G2 and S34ML04G2 devices, five write cycles are needed to input the addresses. For the S34ML01G2, four write cycles are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to S34ML01G2, which will be ignored by the NAND device without causing problems. Addresses are accepted with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 16 and Table 23 for details of the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (×8 or ×16). Refer to Table 4 through Table 6 on page 13 for more detailed information. 2.3 Data Input The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and latched on the rising edge of Write Enable. See Figure 17 on page 40 and Table 23 on page 36 for details of the timing requirements. 2.4 Data Output The Data Output bus operation allows data to be read from the memory array and to check the Status Register content, and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write Enable high, Address Latch Enable low, and Command Latch Enable low. See Figure 18 on page 40 and Table 23 on page 36 for details of the timings requirements. 2.5 Write Protect The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify operations do not start and the content of the memory is not altered. The Write Protect pin is not latched by Write Enable to ensure the protection even during power up. 2.6 Standby In Standby, the device is deselected, outputs are disabled, and power consumption is reduced. Document Number: 002-00499 Rev. *Q Page 15 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3. Command Set Table 8. Command Set Command 3rd Cycle 2nd Cycle Page Read 00h 30h No Yes Page Program 80h 10h No Yes Random Data Input 85h No Yes Random Data Output 05h E0h No Yes Multiplane Program 80h 11h 81h 10h No No ONFI Multiplane Program 80h 11h 80h 10h No No Page Reprogram 8Bh 10h No Yes Multiplane Page Reprogram 8Bh 11h Block Erase 60h D0h Multiplane Block Erase 60h 60h D0h ONFI Multiplane Block Erase 60h D1h 60h Copy Back Read 00h Copy Back Program 85h Multiplane Copy Back Program 85h 11h 81h ONFI Multiplane Copy Back Program 85h 11h 85h Special Read For Copy Back 00h 36h No No Read Status Register 70h Yes Yes Read Status Enhanced 78h Yes No Reset FFh Yes Yes Read Cache 31h Read Cache Enhanced 00h Read Cache End 3Fh Cache Program (End) 80h Cache Program (Start) / (Continue) Multiplane Cache Program (Start/Continue) 8Bh 4th Cycle Acceptable Supported Command on during Busy S34ML01G2 1st Cycle 10h No No No Yes No No No No 35h No Yes 10h No Yes 10h No No 10h No No D0h No Yes No Yes No Yes 10h No Yes 80h 15h No Yes 80h 11h 81h 15h No No ONFI Multiplane Cache Program (Start/Continue) 80h 11h 80h 15h No No Multiplane Cache Program (End) 80h 11h 81h 10h No No ONFI Multiplane Cache Program (End) 80h 11h 80h 10h No No Read ID 90h No Yes Read ID2 30h-65h-00h No Yes 31h 30h Read ONFI Signature 90h No Yes Read Parameter Page ECh No Yes Read Unique ID (Contact Factory) EDh No Yes 29h-17h-04h-1 9h No Yes One-time Programmable (OTP) Area Entry Document Number: 002-00499 Rev. *Q Page 16 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.1 Page Read Page Read is initiated by writing 00h and 30h to the command register along with five address cycles (four or five cycles for S34ML01G2). Two types of operations are available: random read and serial page read. Random read mode is enabled when the page address is changed. All data within the selected page are transferred to the data registers. The system controller may detect the completion of this data transfer (tR) by analyzing the output of the R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25 ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE# signal makes the device output the data, starting from the selected column address up to the last column address. The device may output random data in a page instead of the sequential data by writing Random Data Output command. The column address of next data, which is going to be out, may be changed to the address that follows Random Data Output command. Random Data Output can be performed as many times as needed. After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation. Any operation other than read or Random Data Output causes the device to exit read mode. See Figure 20 on page 41 and Figure 26 on page 44 as references. 3.2 Page Program A page program cycle consists of a serial data loading period in which up to 2 KB (×8) or 1 kword (×16) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs (four cycles for S34ML01G2) and then serial data. The words other than those to be programmed do not need to be loaded. The device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to the address that follows the Random Data Input command (85h). Random Data Input may be performed as many times as needed. The Page Program confirm command (10h) initiates the programming process. The internal write state controller automatically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 23 on page 43 and Figure 25 on page 44 detail the sequence. The device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2 KB (×8) or 1 kword (×16) in a single page program cycle. The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number indicated in Table 27 on page 38. Pages may be programmed in any order within a block. If a Page Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete. Document Number: 002-00499 Rev. *Q Page 17 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.3 Multiplane Program — S34ML02G2 and S34ML04G2 The S34ML02G2 and S34ML04G2 devices support Multiplane Program, making it possible to program two pages in parallel, one page per plane. A Multiplane Program cycle consists of a double serial data loading period in which up to 4352 bytes (×8) or 2176 words (x16) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins with inputting the Serial Data Input command (80h), followed by the five cycle address inputs and serial data for the 1st page. The address for this page must be in the 1st plane (PLA0 = 0). The device supports Random Data Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its serial data input. The address for this page must be in the 2nd plane (PLA0 = 1). The Program Confirm command (10h) starts parallel programming of both pages. Figure 27 on page 45 describes the sequences using the legacy protocol. In this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 28 on page 45 describes the sequences using the ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status Register command is also available during Dummy Busy time (tDBSY). In case of failure in either page program, the fail bit of the Status Register will be set. Refer to Section 3.8 on page 22 for further info. The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number indicated in Table 27 on page 38. Pages may be programmed in any order within a block. If a Multiplane Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks. 3.4 Page Reprogram Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host may call Page Reprogram. This command allows the reprogramming of the same pattern of the last (failed) page into another memory location. The command sequence initiates with reprogram setup (8Bh), followed by the five cycle address inputs of the target page. If the target pattern for the destination page is not changed compared to the last page, the program confirm can be issued (10h) without any data input cycle, as described in Figure 11. Figure 11. Page Reprogram As defined for Page Program CMD Cycle Type ADDR A ADDR ADDR ADDR ADDR Din Din Din Din CMD D0 D1 ... Dn 10h tADL I/Ox 00h C1 C2 R1 R2 R3 tWB tPROG SR[6] Page N A Cycle Type CMD Dout CMD ADDR ADDR ADDR ADDR ADDR CMD I/Ox 70h E1 8Bh C1 C2 R1 R2 R3 10h tWB tPROG SR[6] FAIL ! Document Number: 002-00499 Rev. *Q Page M Page 18 of 71 S34ML01G2 S34ML02G2 S34ML04G2 On the other hand, if the pattern bound for the target page is different from that of the previous page, data in cycles can be issued before program confirm ‘10h’, as described in Figure 12. Figure 12. Page Reprogram with Data Manipulation As defined for Page Program CMD Cycle Type ADDR A ADDR ADDR ADDR ADDR Din Din Din Din CMD CMD Dout D0 D1 ... Dn 10h 70h E1 tADL IOx 80h C1 C2 R1 R2 R3 tWB tPROG SR[6] Cycle Type FAIL ! Page N A CMD ADDR ADDR ADDR ADDR ADDR Din Din Din Din CMD D0 D1 ... Dn 10h tADL I/Ox 8Bh C1 C2 R1 R2 R3 tWB tPROG SR[6] Page M The device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to the address which follows the Random Data Input command (85h). Random Data Input may be operated multiple times regardless of how many times it is done in a page. The Program Confirm command (10h) initiates the re-programming process. The internal write state controller automatically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be issued to read the Status Register. The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status command and Reset command are valid when programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read Status command mode until another valid command is written to the command register. The Page Reprogram must be issued in the same plane as the Page Program that failed. In order to program the data to a different plane, use the Page Program operation instead. The Multiplane Page Reprogram can re-program two pages in parallel, one per plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The command sequence is very similar to Figure 27 on page 45, except that it requires the Page Reprogram Command (8Bh) instead of 80h and 81h. If a Page Reprogram operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete. Document Number: 002-00499 Rev. *Q Page 19 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.5 Block Erase The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles (two cycles for S34ML01G2) initiated by an Erase Setup command (60h). Only the block address bits are valid while the page address bits are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by the execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase verify. Once the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 29 on page 46 details the sequence. If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted block is erased under continuous power conditions before that block can be trusted for further programming and reading operations. 3.6 Multiplane Block Erase — S34ML02G2 and S34ML04G2 Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane. The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. In this case, multiplane erase does not need any Dummy Busy Time between 1st and 2nd block insertion. See Table 27 on page 38 for performance information. For the Multiplane Block Erase operation, the address of the first block must be within the first plane (PLA0 = 0) and the address of the second block in the second plane (PLA0 = 1). See Figure 30 on page 46 for a description of the legacy protocol. In this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 31 on page 47 describes the sequences using the ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status Register command is also available during Dummy Busy time (tDBSY). In case of failure in either erase, the fail bit of the Status Register will be set. Refer to Section 3.7.2 on page 21 for further information. If a Multiplane Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted blocks are erased under continuous power conditions before those blocks can be trusted for further programming and reading operations. Document Number: 002-00499 Rev. *Q Page 20 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.7 Copy Back Program The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved. The benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copied to the newly assigned free block. The operation for performing a copy back is a sequential execution of page-read (without mandatory serial access) and Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the address of the source page moves the whole page of data into the internal data register. As soon as the device returns to the Ready state, optional data read-out is allowed by toggling RE# (see Figure 32 on page 47), or the Copy Back Program command (85h) with the address cycles of the destination page may be written. The Program Confirm command (10h) is required to actually begin programming. The source and the destination pages in the Copy Back Program sequence must belong to the same device plane (same PLA0 for S34ML02G2 and S34ML04G2). Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program time (tPROG) specification. Copy Back Program may not meet this specification when copying from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as shown in Figure 6.17 on page 47. If a Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete. 3.7.1 Multiplane Copy Back Program — S34ML02G2 and S34ML04G2 The device supports Multiplane Copy Back Program with exactly the same sequence and limitations as the Page Program. Multiplane Copy Back Program must be preceded by two single page Copy Back Read command sequences (1st page must be read from the 1st plane and 2nd page from the 2nd plane). Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane can be copied only to a destination page of the same plane. The Multiplane Copy Back Program sequence represented in Figure 34 on page 48 shows the legacy protocol. In this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 35 on page 48 describes the sequence using the ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. If a Multiplane Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks. 3.7.2 Special Read for Copy Back — S34ML02G2 and S34ML04G2 The S34ML02G2 and S34ML04G2 devices support Special Read for Copy Back. If Copy Back Read (described in Section 3.7 and Section 3.7.1 on page 21) is triggered with confirm command ‘36h’ instead ‘35h’, Copy Back Read from target page(s) will be executed with an increased internal (VPASS) voltage. This special feature is used in order to minimize the number of read errors due to over-program or read disturb — it shall be used only if ECC read errors have occurred in the source page using Page Read or Copy Back Read sequences. Excluding the Copy Back Read confirm command, all other features described in Section 3.7 and Section 3.7.1 for standard copy back remain valid (including the figures referred to in those sections). Document Number: 002-00499 Rev. *Q Page 21 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.8 Read Status Register The Status Register is used to retrieve the status value for the last operation issued. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last. This two-line control allows the system to poll the progress of each device in multiple memory connections even when R/B# pins are common-wired. Refer to Section 10 on page 22 for specific Status Register definition, and to Figure 36 on page 49 for timings. If the Read Status Register command is issued during multiplane operations then Status Register polling will return the combined status value related to the outcome of the operation in the two planes according to the following table: Table 9. Read Status Definition Status Register Bit Composite Status Value Bit 0, Pass/Fail OR Bit 1, Cache Pass/Fail OR In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it. The command register remains in Status Read mode until further commands are issued. Therefore, if the Status Register is read during a random read cycle, the read command (00h) must be issued before starting read cycles. Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack configurations (single CE#). “Read Status Enhanced” shall be used instead. 3.9 Read Status Enhanced — S34ML02G2 and S34ML04G2 Read Status Enhanced is used to retrieve the status value for a previous operation in the specified plane. Figure 37 on page 49 defines the Read Status Enhanced behavior and timings. The plane and die address must be specified in the command sequence in order to retrieve the status of the die and the plane of interest. Refer to Table 10 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued. The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it. 3.10 Read Status Register Field Definition Table 10 below lists the meaning of each bit of the Read Status Register and Read Status Enhanced (S34ML02G2 and S34ML04G2). Table 10. Status Register Coding ID Page Program / Page Reprogram Block Erase Read Read Cache Cache Program / Cache Reprogram Coding 0 Pass / Fail Pass / Fail NA NA Pass / Fail N Page Pass: 0 Fail: 1 1 NA NA NA NA Pass / Fail N - 1 Page Pass: 0 Fail: 1 2 NA NA NA NA NA — 3 NA NA NA NA NA — 4 NA NA NA NA NA — 5 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Internal Data Operation Active: 0 Idle: 1 6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Busy: 0 Ready: 1 7 Write Protect Write Protect NA NA Write Protect Protected: 0 Not Protected: 1 Document Number: 002-00499 Rev. *Q Page 22 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.11 Reset The Reset feature is executed by writing FFh to the command register. If the device is in the Busy state during random read, program, or erase mode, the Reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data may be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP# is high or value 60h when WP# is low. If the device is already in reset state a new Reset command will not be accepted by the command register. The R/B# pin transitions to low for tRST after the Reset command is written. Refer to Figure 38 on page 49 for further details. The Status Register can also be read to determine the status of a Reset operation. 3.12 Read Cache Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 17, and it cannot cross a block boundary. As soon as the user starts to read one page, the device automatically loads the next page into the cache register. Serial data output may be executed while data in the memory is read into the cache register. Read Cache is initiated by the Page Read sequence (00-30h) on a page M. After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6 switches to high), two command sequences can be used to continue read cache:  Read Cache (command ‘31h’ only): once the command is latched into the command register (see Figure 40 on page 50), device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the cache register. At the end of this phase, the cache register data can be output by toggling RE# while the next page (page address M+1) is read from the memory array into the data register.  Read Cache Enhanced (sequence ‘00h’ ‘31’): once the command is latched into the command register (see Figure 41 on page 51), device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the cache register. At the end of this phase, cache register data can be output by toggling RE# while page N is read from the memory array into the data register. Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command sequences. If serial data output time of one page exceeds random access time (tR), the random access time of the next page is hidden by data downloading of the previous page. On the other hand, if 31h is issued prior to completing the random access to the next page, the device will stay busy as long as needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the following page. To terminate the Read Cache operation, 3Fh command should be issued (see Figure 42 on page 51). This command transfers data from the data register to the cache register without issuing next page read. During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh, Read SR, or Reset (FFh). To carry out other operations, Read Cache must be terminated by the Read Cache End command (3Fh) or the device must be reset by issuing FFh. Read Status command (70h) may be issued to check the status of the different registers and the busy/ready status of the cached read operations. ■ The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data. ■ The status bit I/O5 can be used to determine when the cell reading of the current data register contents is complete. Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is toggled to output the data of a given page, the first output data is related to the first byte of the page (column address 00h). Random Data Output command can be used to switch column address. Document Number: 002-00499 Rev. *Q Page 23 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.13 Cache Program Cache Program can improve the program throughput by using the cache register. The Cache Program operation cannot cross a block boundary. The cache register allows new data to be input while the previous data that was transferred to the data register is programmed into the memory array. After the serial data input command (80h) is loaded to the command register, followed by five cycles of address, a full or partial page of data is latched into the cache register. Once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data register for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data of the cache register is transferred into the data register, the device returns to the Ready state and allows loading the next data into the cache register through another Cache Program command sequence (80h-15h). The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data register. Cell programming the data of the data register and loading of the next data into the cache register is consequently processed through a pipeline model. In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming of current data register contents is complete; till this moment the device will stay in a busy state (tCBSYW). Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the cached program operations.  The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.  The status bit I/O5 can be used to determine when the cell programming of the current data register contents is complete.  The Cache Program error bit I/O1 can be used to identify if the previous page (page N-1) has been successfully programmed or not in a Cache Program operation. The status bit is valid upon I/O6 status bit changing to 1.  The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while programming page N. The status bit is valid upon I/O5 status bit changing to 1. I/O1 may be read together with I/O0. If the system monitors the progress of the operation only with R/B#, the last page of the target program sequence must be programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is finished before starting any other operation. See Table 10 on page 22 and Figure 43 on page 52 for more details. If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks. Document Number: 002-00499 Rev. *Q Page 24 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.14 Multiplane Cache Program — S34ML02G2 and S34ML04G2 The Multiplane Cache Program enables high program throughput by programming two pages in parallel, while exploiting the data and cache registers of both planes to implement cache. The command sequence can be summarized as follows:  Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to be programmed do not need to be loaded. The device supports Random Data Input exactly like Page Program operation.  The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY).  Once device returns to ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of 2nd page other than those to be programmed do not need to be loaded.  Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command register, the data in the cache registers is transferred into the data registers for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data from the cache registers are transferred into the data registers, the device returns to the Ready state, and allows loading the next data into the cache register through another Cache Program command sequence. The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the tCBSYW time needed to complete programming the current data register contents, and transferring the new data from the cache registers. The sequence to end Multiplane Cache Program is 80h-...- 11h...-...81h...-...10h. The Multiplane Cache Program is available only within two paired blocks in separate planes. Figure 44 on page 53 shows the legacy protocol for the Multiplane Cache Program operation. In this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 45 on page 54 shows the ONFI protocol for the Multiplane Cache Program operation. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user opts for 70h, Read Status Register will provide “global” information about the operation in the two planes.  I/O6 indicates when both cache registers are ready to accept new data.  I/O5 indicates when the cell programming of the current data registers is complete.  I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not. This status bit is valid upon I/O6 status bit changing to 1.  I/O0 identifies if any error has been detected by the program/erase controller while programming the two pages N. This status bit is valid upon I/O5 status bit changing to 1. See Table 10 on page 22 for more details. If the system monitors the progress of the operation only with R/B#, the last pages of the target program sequence must be programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is finished before starting any other operation. Refer to Section 3.8 on page 22 for further information. If a Multiplane Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks. Document Number: 002-00499 Rev. *Q Page 25 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.15 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00) before Read Status command (0x70). For the S34ML02G2 and S34ML04G2 devices, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and 5th cycle ID, respectively. For the S34ML01G2 device, four read cycles sequentially output the manufacturer code (01h), and the device code and 80h, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 46 on page 55 shows the operation sequence, while Table 11 to Table 16 explain the byte meaning. Table 11. Read ID for Supported Configurations Density Org VCC 1 Gb 2 Gb ×8 4 Gb 3.3 V 1 Gb 2 Gb ×16 4 Gb 1st 2nd 3rd 4th 5th 01h F1h 80h 1Dh — 01h DAh 90h 95h 46h 01h DCh 90h 95h 56h 01h C1h 80h 5Dh — 01h CAh 90h D5h 46h 01h CCh 90h D5h 56h Table 12. Read ID Bytes Device Identifier Byte Description 1st Manufacturer Code 2nd Device Identifier 3rd Internal chip number, cell type, etc. 4th Page Size, Block Size, Spare Size, Serial Access Time, Organization 5th (S34ML02G2, S34ML04G2) ECC, Multiplane information 3rd ID Data Table 13. Read ID Byte 3 Description Description Internal Chip Number Cell type Number of simultaneously programmed pages I/O6 I/O5 I/O4 I/O3 I/O2 00 01 10 11 00 01 10 11 1 2 4 8 Not supported Supported Cache Program Not supported Supported I/O1 I/O0 00 01 10 11 2-level cell 4-level cell 8-level cell 16-level cell Interleave program Between multiple chips Document Number: 002-00499 Rev. *Q I/O7 1 2 4 8 0 1 0 1 Page 26 of 71 S34ML01G2 S34ML02G2 S34ML04G2 4th ID Data Table 14. Read ID Byte 4 Description — S34ML01G2 Description Page Size (without spare area) 1 kB 2 kB 4 kB 8 kB Block Size (without spare area) 64 kB 128 kB 256 kB 512 kB Spare Area Size (byte / 512 byte) Serial Access Time Organization I/O7 I/O6 I/O5 I/O4 I/O3 I/O1 I/O0 00 01 10 11 00 01 10 11 8 16 45 ns 25 ns Reserved Reserved I/O2 0 1 0 0 1 1 0 1 0 1 ×8 0 ×16 1 Table 15. Read ID Byte 4 Description — S34ML02G2 and S34ML04G2 Description Page Size (without spare area) 1 kB 2 kB 4 kB 8 kB Block Size (without spare area) 64 kB 128 kB 256 kB 512 kB Spare Area Size (byte / 512 byte) Serial Access Time Organization I/O7 I/O6 I/O5 I/O4 I/O3 00 01 10 11 0 1 0 1 0 1 0 0 1 1 ×8 0 ×16 1 Document Number: 002-00499 Rev. *Q I/O1 I/O0 00 01 10 11 16 32 50 ns / 30 ns 25 ns Reserved Reserved I/O2 Page 27 of 71 S34ML01G2 S34ML02G2 S34ML04G2 5th ID Data Table 16. Read ID Byte 5 Description — S34ML02G2 and S34ML04G2 Description ECC Level I/O6 I/O5 I/O4 I/O3 I/O2 Plane Size (without spare area) 00 01 10 11 64 Mb 128 Mb 256 Mb 512 Mb 1 Gb 2 Gb 4 Gb Reserved I/O1 I/O0 00 01 10 11 1 2 4 8 Plane Number 3.16 I/O7 1 bit / 512 bytes 2 bit / 512 bytes 4 bit / 512 bytes 8 bit / 512 bytes 000 001 010 011 100 101 110 0 Read ID2 The device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command register, followed by address inputs, followed by command 30h. The address for S34ML01G2 will be 00h-02h-02h-00h. The address for S34ML02G2 and S34ML04G2 will be 00h-02h-02h-00h-00h. The ID2 data can then be read from the device by pulsing RE#. The command register remains in Read ID2 mode until further commands are issued to it. Figure 47 on page 55 shows the Read ID2 command sequence. Read ID2 values are all 0xFs, unless specific values are requested when ordering. 3.17 Read ONFI Signature To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the ASCII encoding of 'ONFI' where 'O' = 4Fh, 'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields indeterminate values. Figure 48 on page 56 shows the operation sequence. Document Number: 002-00499 Rev. *Q Page 28 of 71 S34ML01G2 S34ML02G2 S34ML04G2 3.18 Read Parameter Page The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an address input of 00h. The host may monitor the R/B# pin or wait for the maximum data transfer time (t R) before reading the Parameter Page data. The command register remains in Parameter Page mode until further commands are issued to it. If the Status Register is read to determine when the data is ready, the Read Command (00h) must be issued before starting read cycles. Figure 49 on page 56 shows the operation sequence, while Table 17 explains the parameter fields. For x16 devices, the upper eight I/Os are not used and are 0xFF. Note: For 32 nm Cypress NAND, for a particular condition, the Read Parameter Page command does not give the correct values. To overcome this issue, the host must issue a Reset command before the Read Parameter Page command. Issuance of Reset before the Read Parameter Page command will provide the correct values and will not output 00h values. Table 17. Parameter Page Description Byte O/M Description Values Revision Information and Features Block 0-3 4-5 6-7 8-9 M Parameter page signature Byte 0: 4Fh, “O” Byte 1: 4Eh, “N” Byte 2: 46h, “F” Byte 3: 49h, “I” 4Fh, 4Eh, 46h, 49h M Revision number 2-15 Reserved (0) 1 1 = supports ONFI version 1.0 0 Reserved (0) 02h, 00h M Features supported 5-15 Reserved (0) 4 1 = supports odd to even page Copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple LUN operations 0 1 = supports 16-bit data bus width S34ML01G200 (×8): 14h, 00h S34ML02G200 (×8): 1Ch, 00h S34ML04G200 (×8): 1Ch, 00h S34ML01G204 (×16): 15h, 00h S34ML02G204 (×16): 1Dh, 00h S34ML04G204 (×16): 1Dh, 00h M Optional commands supported 6-15 Reserved (0) 5 1 = supports Read Unique ID (contact factory) 4 1 = supports Copyback 3 1 = supports Read Status Enhanced 2 1 = supports Get Features and Set Features 1 1 = supports Read Cache commands 0 1 = supports Page Cache Program command S34ML01G2: 33h, 00h S34ML02G2: 3Bh, 00h S34ML04G2: 3Bh, 00h Reserved (0) 00h 10-31 Manufacturer Information Block 32-43 M Device manufacturer (12 ASCII characters) 53h, 50h, 41h, 4Eh, 53h, 49h, 4Fh, 4Eh, 20h, 20h, 20h, 20h S34ML01G2: 53h, 33h, 34h, 4Dh, 4Ch, 30h, 31h, 47h, 32h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 44-63 M S34ML02G2: 53h, 33h, 34h, 4Dh, 4Ch, 30h, 32h, 47h, 32h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h Device model (20 ASCII characters) S34ML04G2: 53h, 33h, 34h, 4Dh, 4Ch, 30h, 34h, 47h, 32h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 M JEDEC manufacturer ID 01h 65-66 O Date code 00h 67-79 Reserved (0) 00h Memory Organization Block 80-83 M Number of data bytes per page Document Number: 002-00499 Rev. *Q 00h, 08h, 00h, 00h Page 29 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Table 17. Parameter Page Description (Continued) Byte O/M 84-85 M Description Values S34ML01G2: 40h, 00h S34ML02G2: 80h, 00h S34ML04G2: 80h, 00h Number of spare bytes per page 86-89 M Number of data bytes per partial page 00h, 00h, 00h, 00h 90-91 M Number of spare bytes per partial page 00h, 00h 92-95 M Number of pages per block 40h, 00h, 00h, 00h 96-99 M Number of blocks per logical unit (LUN) S34ML01G2: 00h, 04h, 00h, 00h S34ML02G2: 00h, 08h, 00h, 00h S34ML04G2: 00h, 10h, 00h, 00h 100 M Number of logical units (LUNs) 01h 101 M Number of address cycles 4-7 Column address cycles 0-3 Row address cycles S34ML01G2: 22h S34ML02G2: 23h S34ML04G2: 23h 102 M Number of bits per cell 01h 103-104 M Bad blocks maximum per LUN S34ML01G2: 14h, 00h S34ML02G2: 28h, 00h S34ML04G2: 50h, 00h 105-106 M Block endurance 01h, 05h 107 M Guaranteed valid blocks at beginning of target 01h 108-109 M Block endurance for guaranteed valid blocks 01h, 03h 110 M Number of programs per page 04h 111 M Partial programming attributes 5-7 Reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 Reserved 0 1 = partial page programming has constraints 00h 112 M Number of bits ECC correctability 04h M Number of interleaved address bits 4-7 Reserved (0) 0-3 Number of interleaved address bits S34ML01G2: 00h S34ML02G2: 01h S34ML04G2: 01h O Interleaved operation attributes 4-7 Reserved (0) 3 Address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 Overlapped / concurrent interleaving support S34ML01G2: 00h S34ML02G2: 04h S34ML04G2: 04h Reserved (0) 00h 113 114 115-127 Electrical Parameters Block 128 M I/O pin capacitance 0Ah M Timing mode support 6-15 Reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 1Fh, 00h 131-132 O Program cache timing mode support 6-15 Reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 1Fh, 00h 133-134 M tPROG Maximum page program time (µs) BCh, 02h 129-130 Document Number: 002-00499 Rev. *Q Page 30 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Table 17. Parameter Page Description (Continued) Byte O/M 135-136 M 137-138 M 139-140 M 141-163 Description Values tBERS Maximum block erase time (µs) 10h, 27h tR Maximum page read time (µs) S34ML01G2: 19h, 00h S34ML02G2: 1Eh, 00h S34ML04G2: 1Eh, 00h tCCS Minimum Change Column setup time (ns) C8h, 00h Reserved (0) 00h Vendor Block 164-165 M 166-253 Vendor specific Revision number 00h Vendor specific 00h S34ML01G200 (×8): 68h, 4Eh S34ML02G200 (×8): 56h, EAh S34ML04G200 (×8): 28h, A1h S34ML01G204 (×16): 1Ah, 38h S34ML02G204 (×16): 24h, 9Ch S34ML04G204 (×16): 5Ah, D7h 254-255 M Integrity CRC 256-511 M Value of bytes 0-255 512-767 M Value of bytes 0-255 Repeat Value of bytes 0-255 768+ O Additional redundant parameter pages FFh Redundant Parameter Pages Repeat Value of bytes 0-255 Note: 1. O” Stands for Optional, “M” for Mandatory. 3.19 Read Unique ID (Contact Factory) The device supports the ONFI Read Unique ID function, initiated by writing EDh to the command register, followed by an address input of 00h. The host must monitor the R/B# pin or wait for the maximum data transfer time (tR) before reading the Unique ID data. The first sixteen bytes returned by the flash is a unique value. The next sixteen bytes returned are the bit-wise complement of the unique value. The host can verify the Unique ID was read correctly by performing an XOR of the two values. The result should be all ones. The command register remains in Unique ID mode until further commands are issued to it. Figure 50 on page 56 shows the operation sequence, while Table 18 shows the Unique ID data contents. Cypress guarantees unique id support feature with a special model number shown in the OPN combination in Section 10. Ordering Information on page 64. Note: For 32nm Cypress NAND, for a particular condition, the Read Unique ID command does not give the correct values. To overcome this issue, the host must issue a Reset command before the Read Unique ID command. Issuance of Reset before the Read Unique ID command will provide the correct values and will not output 00h values. Table 18. Unique ID Data Description (Contact Factory) Byte Description 0-15 Unique ID 16-31 ID Complement 32-47 Unique ID 48-63 ID Complement 64-79 Unique ID 80-95 ID Complement 96-111 Unique ID 112-127 ID Complement 128-143 Unique ID 144-159 ID Complement 160-175 Unique ID 176-191 ID Complement Document Number: 002-00499 Rev. *Q Page 31 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Table 18. Unique ID Data Description (Contact Factory) (Continued) Byte Description 192-207 Unique ID 208-223 ID Complement 224-239 Unique ID 240-255 ID Complement 256-271 Unique ID 272-287 ID Complement 288-303 Unique ID 304-319 ID Complement 320-335 Unique ID 336-351 ID Complement 352-367 Unique ID 368-383 ID Complement 384-399 Unique ID 400-415 ID Complement 416-431 Unique ID 432-447 ID Complement 448-463 Unique ID 464-479 ID Complement 480-495 Unique ID 496-511 ID Complement Note 25. For 32 nm NAND, for a particular condition, if read unique id does not give the correct values, the host must issue a Reset command before the read unique id command. Issuance of Reset before the read unique id command will provide the correct values and will not output false values. 3.20 One-Time Programmable (OTP) Entry The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to the command register. The device is then ready to accept Page Read and Page Program commands (refer to Section 3.1 Page Read on page 17 and Section 3.2 Page Program on page 17). The OTP area is of a single erase block size (64 pages), and hence only row addresses between 00h and 3Fh are allowed. The host must issue the Reset command (refer to Section 3.11 Reset on page 23) to exit the OTP area and access the normal flash array. The Block Erase command is not allowed in the OTP area. Refer to Figure 51 on page 57 for more detail on the OTP Entry command sequence. Document Number: 002-00499 Rev. *Q Page 32 of 71 S34ML01G2 S34ML02G2 S34ML04G2 4. Signal Descriptions 4.1 Data Protection and Power On / Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever VCC is below about 1.8V. The power-up and power-down sequence is shown in Figure 52 on page 57. The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum values (as specified on), and shall return to one within 5 ms (max). During this busy time, the device executes the initialization process (cam reading), and dissipates a current ICC0 (30 mA max), in addition, it disregards all commands excluding Read Status Register (70h). At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page read command, the 00h command may be skipped. The WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100 µs is required before the internal circuit gets ready for any command sequences as shown in Figure 52 on page 57. The two-step command sequence for program/erase provides additional software protection. 4.2 Ready/Busy The Ready/Busy output provides a method of indicating the completion of a page program, erase, copyback, or read completion. The R/B# pin is normally high and goes to low when the device is busy (after a reset, read, program, or erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because the pull-up resistor value is related to tr (R/B#) and the current drain during busy (ibusy), and output load capacitance is related to tf, an appropriate value can be obtained with the reference chart shown in Figure 13. For example, for a particular system with 20 pF of output load, tf from VCC to VOL at 10% to 90% will be 10 ns, whereas for a particular load of 50 pF, Cypress measured it to be 20 ns as shown in Figure 13. Figure 13. Ready/Busy Pin Electrical Application Rp VCC ibusy Ready VCC R/B# open drain output VOH VOL : 0.4V, VOH : 2.4V CL VOL Busy tf tr GND Device Rp vs. tr, tf and Rp vs. ibusy @VCC = 3.3V, Ta = 25°C, CL=50 pF ibusy [A] 300n 3m 200 200n 2m 1.2 100n Legend = tr (ns) 2.4 100 = ibusy (mA) = tf (ns) 150 0.8 50 1m 0.6 20 20 1k 2k 20 20 tr,tf [s] 3k 4k Rp (ohm) Rp value guidence Rp (min.) = Vcc (Max.) - VOL (Max.) I OL + ∑I L = 3.2V 8mA + ∑I L where I L is the sum of the input currents of all devices tied to the R/B# pin. Rp(max) is determined by maximum permissible limit of tr. Document Number: 002-00499 Rev. *Q Page 33 of 71 S34ML01G2 S34ML02G2 S34ML04G2 4.3 Write Protect Operation Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about 100 ns. Switching WP# low during this time is equivalent to issuing a Reset command (FFh). The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The R/B# pin will stay low for tRST (similarly to Figure 38 on page 49). At the end of this time, the command register is ready to process the next command, and the Status Register bit I/O6 will be cleared to 1, while I/O7 value will be related to the WP# value. Refer to Table 10 on page 22 for more information on device status. Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to issuing the setup commands (80h or 60h). The level of WP# shall be set tWW ns prior to raising the WE# pin for the set up command, as explained in Figure 53 and Figure 54 on page 57. Figure 14. WP# Low Timing Requirements during Program/Erase Command Sequence WE# I/O[7:0] Valid WP# > 100 ns Document Number: 002-00499 Rev. *Q Sequence Aborted Page 34 of 71 S34ML01G2 S34ML02G2 S34ML04G2 5. Electrical Characteristics 5.1 Valid Blocks Table 19. Valid Blocks Device Symbol Min Typ Max Unit S34ML01G2 NVB 1004 — 1024 Blocks S34ML02G2 NVB 2008 — 2048 Blocks S34ML04G2 NVB 4016 — 4096 Blocks 5.2 Absolute Maximum Ratings Table 20. Absolute Maximum Ratings Parameter Symbol Value Unit Ambient Operating Temperature (Industrial Temperature Range) TA -40 to +85 °C TBIAS -50 to +125 °C Temperature under Bias Storage Temperature Input or Output Voltage Supply Voltage TSTG -65 to +150 °C VIO (2) -0.6 to +4.6 V VCC -0.6 to +4.6 V Notes: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the table Absolute Maximum Ratings “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions. 3. Maximum Voltage may overshoot to VCC +2.0V during transition and for less than 20 ns during transitions. 5.3 Recommended Operating Conditions Table 21. Recommended Operating Conditions Symbol Min Typ Max Units Vcc Supply Voltage Parameter Vcc 2.7 3.3 3.6 V Ground Supply Voltage Vss 0 0 0 V 5.4 AC Test Conditions Table 22. AC Test Conditions Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (2.7V - 3.6V) Document Number: 002-00499 Rev. *Q Value 0.0 V to VCC 5 ns VCC / 2 1 TTL Gate and CL = 50 pF Page 35 of 71 S34ML01G2 S34ML02G2 S34ML04G2 5.5 AC Characteristics Table 23. AC Characteristics Symbol Min Max Unit ALE to RE# delay Parameter tAR 10 — ns ALE hold time tALH 5 — ns ALE setup time tALS 10 — ns Address to data loading time tADL 70 — ns CE# low to RE# low tCR 10 — ns CE# hold time tCH 5 — ns CE# high to output High-Z tCHZ — 30 ns CLE hold time tCLH 5 — ns CLE to RE# delay tCLR 10 — ns ns tCLS 10 — CE# access time tCEA (29) — 25 ns CE# high to output hold tCOH (28) 15 — ns tCSD 10 — ns CE# setup time tCS 20 — ns Data hold time tDH 5 — ns Data setup time tDS 10 — ns Data transfer from cell to register (S34ML01G2) tR — 25 µs Data transfer from cell to register (S34ML02G2, S34ML04G2) tR — 30 µs Output High-Z to RE# low tIR 0 — ns Read cycle time tRC 25 — ns RE# access time tREA — 20 ns CLE setup time CE# high to ALE or CLE don't care tREH 10 — ns tRHOH (28) 15 — ns RE# high to WE# low tRHW 100 — ns RE# high to output High-Z tRHZ — 100 ns RE# low to output hold tRLOH 5 — ns tRP 12 — ns Ready to RE# low tRR 20 — ns Device resetting time (Read/Program/Erase) tRST — 5/10/500 µs RE# high hold time RE# high to output hold RE# pulse width WE# high to busy tWB — 100 ns Write cycle time tWC 25 — ns WE# high hold time tWH 10 — ns WE# high to RE# low tWHR 60 — ns WE# high to RE# low for Random Data Output ns tWHR2 200 — WE# pulse width tWP 12 — ns Write protect time tWW 100 — ns Notes 26. The time to Ready depends on the value of the pull-up resistor tied to R/B# pin. 27. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5 µs. 28. CE# low to high or RE# low to high can be at different times and produce three cases. Depending on which signal comes high first, either tCOH or tRHOH will be met. 29. During data output, tCEA depends partly on tCR (CE# low to RE# low). If tCR exceeds the minimum value specified, then the maximum time for tCEA may also be exceeded (tCEA = tCR + tREA). Document Number: 002-00499 Rev. *Q Page 36 of 71 S34ML01G2 S34ML02G2 S34ML04G2 5.6 DC Characteristics Table 24. DC Characteristics and Operating Conditions Parameter Symbol Test Conditions Min Typ Max Units ICC0 FFh command input after power on — — 50 per device mA Sequential Read ICC1 tRC = tRC (min) CE# = VIL, Iout = 0 mA — 15 30 mA Program ICC2 Normal — 15 30 mA Cache — 15 30 mA Erase ICC3 — — 15 30 mA Standby Current, (TTL) ICC4 CE#=VIH, WP#=0V/Vcc — — 1 mA Standby Current, (CMOS) ICC5 CE# = VCC-0.2, WP# = 0/VCC — 10 50 µA Power On Current Operating Current Input Leakage Current ILI VIN = 0 to VCC(max) — — ±10 µA Output Leakage Current ILO VOUT = 0 to VCC(max) — — ±10 µA Input High Voltage VIH — VCC x 0.8 — VCC + 0.3 V Input Low Voltage VIL — -0.3 — VCC x 0.2 V Output High Voltage VOH IOH = -400 µA 2.4 — — V Output Low Voltage VOL IOL = 2.1 mA — — 0.4 V IOL(R/B#) VOL = 0.4V 8 10 — mA VLKO — — 1.8 — V Output Low Current (R/B#) Erase and Program Lockout Voltage Notes 30. All VCC pins, and VSS pins respectively, are shorted together. 31. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking. 32. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin. 33. Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to Section 4.1 for more details. Document Number: 002-00499 Rev. *Q Page 37 of 71 S34ML01G2 S34ML02G2 S34ML04G2 5.7 Pin Capacitance Table 25. Pin Capacitance (TA = 25°C, f = 1.0 MHz) Parameter Symbol Test Condition Min Max Unit Input CIN VIN = 0V — 10 pF Input / Output CIO VIL = 0V — 10 pF Note 34. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips]. 5.8 Thermal Resistance Table 26. Thermal Resistance Parameter Theta JA Symbol TS048 VBM063 VBT067 Unit Thermal Resistance (Junction to Ambient) 40 39 39 °C/W Note 35. Test conditions follow standard methods and procedures for measuring thermal impedance in accordance with EIA/JESD51. 5.9 Program / Erase Characteristics Table 27. Program / Erase Characteristics Parameter Description Min Typ Max Unit Program Time / Multiplane Program Time (37) tPROG — 300 700 µs Dummy Busy Time for Multiplane Program (S34ML02G2, S34ML04G2) tDBSY — 0.5 1 µs tCBSYW — 5 tPROG µs NOP — — 4 Cycle Block Erase Time / Multiplane Erase Time (S34ML02G2, S34ML04G2) tBERS — 3.5 10 ms Block Erase Time (S34ML01G2) tBERS — 3 10 ms Read Cache busy time (S34ML01G2) tCBSYR — 3 tR µs Read Cache busy time (S34ML02G2, S34ML04G2) tCBSYR — 5 tR µs Cache Program short busy time Number of partial Program Cycles in the same page Main + Spare Notes 36. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (VCC = 3.3V, 25°C). 37. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program time (tPROG) specification. Copy Back Program may not meet this specification when copying from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). Document Number: 002-00499 Rev. *Q Page 38 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6. Timing Diagrams 6.1 Command Latch Cycle Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low, and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/ erase) the Write Protect pin must be high. Figure 15. Command Latch Cycle CLE tCLS tCLH tCS tCH CE# tWP WE# tALS tALH ALE tDS I/Ox tDH Command = Don’t Care 6.2 Address Latch Cycle Address Input bus operation allows the insertion of the memory address. To insert the 27 (×8 Device) addresses needed to access the 1 Gb, four write cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low, and Read Enable High and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (write/ erase) the Write Protect pin must be high. Figure 16. Address Latch Cycle tCLS CLE tCS tWC tWC tWC tWC CE# tWP tWP tWP tWP WE# tWH tALH tALS tALS tWH tALH tALS tWH tALH tWH tALS tALH tALS tALH ALE tDH tDS I/Ox Col. Add1 tDH tDS Col. Add2 tDH tDS Row. Add1 tDH tDS Row. Add2 tDH tDS Row. Add3 = Don’t Care Document Number: 002-00499 Rev. *Q Page 39 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.3 Data Input Cycle Timing Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serially, and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. Figure 17. Input Data Latch Cycle tCLH CLE tCH CE# tWC tALS ALE tWP tWP WE# tWH tWH tDS I/Ox tDH tWP tDS tDH tDS Din final Din Din 0 tDH = Don’t Care 6.4 Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H) Figure 18. Data Output Cycle Timing tRC tCHZ CE# tREH tREA RE# tREA tREA tCOH tRHZ tRHZ tRHOH I/Ox Dout Dout Dout tRR R/B# Notes 38. Transition is measured at ± 200 mV from steady state voltage with load. 39. This parameter is sampled and not 100% tested. 40. tRHOH starts to be valid when frequency is lower than 33 MHz. Document Number: 002-00499 Rev. *Q Page 40 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.5 Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L) Figure 19. Data Output Cycle Timing (EDO) CE# tCR tRC RE# tRP tCHZ tCOH tREH tREA I/Ox tRHZ tREA tRLOH tRHOH Dout Dout tRR R/B# = Don’t Care Notes 41. Transition is measured at ± 200 mV from steady state voltage with load. 42. This parameter is sampled and not 100% tested. 43. tRLOH is valid when frequency is higher than 33 MHz. 44. tRHOH starts to be valid when frequency is lower than 33 MHz. 6.6 Page Read Operation Figure 20. Page Read Operation (Read One Page) CLE tCLR CE# tWC WE# tCSD tWB ALE tR RE# I/Ox tAR tRC tRHZ tRR 00h Col. Add. 1 Col. Add. 2 Column Address Row Add. 1 Row Add. 2 Row Add. 3 30h Dout N Dout N +1 Dout M Row Address R/B# Busy = Don’t Care Note 45. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page buffer. Document Number: 002-00499 Rev. *Q Page 41 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.7 Page Read Operation (Interrupted by CE#) Figure 21. Page Read Operation Interrupted by CE# CLE tCLR CE# tCSD tCHZ WE# tCOH tWB tAR ALE tRC tR RE# tRR Col. Col. Add. 1 Add. 2 Column Address 00h I/Ox Row Add. 1 Row Add. 2 Row Add. 3 Dout N 30h Dout N +1 Dout N +2 Row Address R/B# Busy 6.8 = Don’t Care Page Read Operation Timing with CE# Don’t Care Figure 22. Page Read Operation Timing with CE# Don’t Care CE# don’t care CE# CLE ALE WE# tRC RE# tRR I/Ox 00h Col. Add. 1 Col. Add. 2 Row Add. 1 R/B# Row Add. 2 Row Add. 3 Dout N 30h Dout N+1 Dout N+2 Dout N+3 Dout N+4 Dout N+5 Dout M Dout M+1 Dout M+2 tR = Don’t Care (VIH or VIL) tCR CE# RE# I/Ox Document Number: 002-00499 Rev. *Q tREA Dout Page 42 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.9 Page Program Operation Figure 23. Page Program Operation CLE CE# tWC tWC tWC WE# tADL tWB tWHR tPROG ALE RE# I/Ox Col. Row. Col. Row. Row. 80h Add2 Add3 Add1 Add2 Add1 Serial Data Row Address Input Command Column Address Din N Din M 10h 70h I/O0 Read Status Command Program Command 1 up to m byte Serial Input R/B# I/O0=0 Successful Program I/O0=1 Error in Program = Don’t Care Note 46. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. 6.10 Page Program Operation Timing with CE# Don’t Care Figure 24. Page Program Operation Timing with CE# Don’t Care CE# don’t care CE# CLE ALE WE# RE# I/Ox 80h Col. Add. 1 Col. Add. 2 Row Add. 1 Row Add. 2 Row Add. 3 Din N Din M Din N+1 Din P Din P+1 Din R 10h = Don’t Care CE# WE# Document Number: 002-00499 Rev. *Q tCS tCH tWP Page 43 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.11 Page Program Operation with Random Data Input Figure 25. Random Data Input CLE CE# tWC tWC tWC WE# tADL tADL tWB tWHR tPROG ALE RE# I/Ox 80h Serial Data Input Command Col. Add1 Col. Add2 Column Address Row Add1 Row Add2 Row Add3 Din M Din N Col. Add1 85h Random Data Input Command Row Address Col. Add2 Din J Column Address Din K Serial Input 10h 70h IO0 Read Status Command Program Command R/B# = Don’t Care Note 47. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. 6.12 Random Data Output In a Page Figure 26. Random Data Output CLE tCLR CE# WE# tWB tAR tWHR2 tRHW ALE tR tRC tREA RE# tRR I/Ox 00h Col. Col. Add. 2 Add. 1 Column Address Row Row Row Add. 2 Add. 3 Add. 1 Row Address Dout N 30h Dout N +1 05h Col. Col. Add. 2 Add. 1 Column Address E0h Dout M Dout M +1 R/B# Busy Document Number: 002-00499 Rev. *Q = Don’t Care Page 44 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.13 Multiplane Page Program Operation — S34ML02G2 and S34ML04G2 Figure 27. Multiplane Page Program CLE CE# tWC WE# tDBSY tWB tWB tPROG tWHR ALE RE# I/Ox tADL tADL Col. Add1 80h Col. Add2 Row Add1 Row Add2 Row Add3 Serial Data Column Address Page Row Address Input Command Din N Din M 1 up to full page Data Serial Input Col. Add1 81h 11h Program Command (Dummy) Col. Add2 Row Add1 Row Add2 Row Add3 Din M Din N 10h 70h IO Read Staus Command Program Confirm Command (True) R/B# Ex.) Address Restriction for Multiplane Page Program I/O0~7 tPROG tDBSY R/B# 80h Address & Data Input 11h Col Add 1,2 and Row Add 1,2,3 and Data Address & Data Input 81h (Note 48) 10h 70h Col Add 1,2 and Row Add 1,2,3 and Data A0 ~ A11: Valid A12 ~ A17: Fixed ‘Low’ A18: Fixed ‘Low’ A19 ~ A28: Fixed ‘Low’ A0 ~ A11: Valid A12 ~ A17: Valid A18: Fixed ‘High’ A19 ~ A28: Valid Notes 48. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh. 49. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices. Figure 28. Multiplane Page Program (ONFI 1.0 Protocol) Cycle Type CMD ADDR ADDR ADDR ADDR ADDR DIN DIN DIN DIN CMD D0A D1A ... DnA 11h tADL DQx 80h C1A C2A R1A R2A R3A tADL tIPBSY SR[6] A Cycle Type CMD ADDR ADDR ADDR ADDR ADDR DIN DIN DIN DIN CMD D0B D1B ... DnB 10h tADL DQx 80h C1B C2B R1B R2B R3B tADL tPROG SR[6] Notes 50. C1A-C2A Column address for page A. C1A is the least significant byte. 51. R1A-R3A Row address for page A. R1A is the least significant byte. 52. D0A-DnA Data to program for page A. 53. C1B-C2B Column address for page B. C1B is the least significant byte. 54. R1B-R3B Row address for page B. R1B is the least significant byte. 55. D0B-DnB Data to program for page B. 56. The block address bits must be the same except for the bit(s) that select the plane. Document Number: 002-00499 Rev. *Q Page 45 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.14 Block Erase Operation Figure 29. Block Erase Operation (Erase One Block) CLE CE# tWC WE# tWHR tBERS tWB ALE RE# 60h I/Ox Row Add1 Row Add2 Row Add3 70h D0h I/O0 Row Address BUSY R/B# Auto Block Erase Setup Command Erase Command Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase = Don’t Care 6.15 Multiplane Block Erase — S34ML02G2 and S34ML04G2 Figure 30. Multiplane Block Erase CLE CE# tWC tWC WE# tWB tBERS tWHR ALE RE# 60h I/Ox Row Add1 Row Add2 Row Add3 60h Row Add1 Row Add2 Row Add3 D0h I/O0 70h Row Address Row Address Busy R/B# Block Erase Setup Command1 Block Erase Setup Command2 Erase Confirm Command Read Status Command I/O 1 = 0 Successful Erase I/O 1 = 1 Error in plane Ex.) Address Restriction for Multiplane Block Erase Operation R/B# I/O0~7 tBERS 60h Address 60h Address Row Add1,2,3 Row Add1,2,3 A12 ~ A17 : Fixed ‘Low’ A18 : Fixed ‘Low’ A19 ~ A28 : Fixed ‘Low’ A12 ~ A17 : Fixed ‘Low’ A18 : Fixed ‘High’ A19 ~ A28 : Valid D0h 70h Note 57. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices. Document Number: 002-00499 Rev. *Q Page 46 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Figure 31. Multiplane Block Erase (ONFI 1.0 Protocol) CLE WE# ALE RE# IOx 60h R1 A R2A R3A D1h 60h t SR[6] R1B R2B R3B D0h t BERS IEBSY Notes 58. R1A-R3A Row address for block on plane 0. R1A is the least significant byte. 59. R1B-R3B Row address for block on plane 1. R1B is the least significant byte. 60. The block address bits must be the same except for the bit(s) that select the plane. 6.16 Copy Back Read with Optional Data Readout Figure 32. Copy Back Read with Optional Data Readout I/O 00h Source Add Inputs 35h Data Outputs Target Add Inputs 85h 10h SR0 70h Read Status Register tR (Read Busy time) tPROG (Program Busy time) R/B# Busy 6.17 Busy Copy Back Program Operation With Random Data Input Figure 33. Copy Back Program with Random Data Input I/O 00h Source Add Inputs 35h 85h Target Add Inputs Data 85h 2 Cycle Add Inputs Data 70h 10h SR0 Read Status Register Unlimited number of repetitions R/B# tR (Read Busy time) tPROG (Program Busy time) Busy Document Number: 002-00499 Rev. *Q Busy Page 47 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.18 Multiplane Copy Back Program — S34ML02G2 and S34ML04G2 Figure 34. Multiplane Copy Back Program tR tR R/B# I/Ox 00h Add. (5 cycles) 35h 00h Col. Add. 1, 2 and Row Add. 1, 2, 3 Source Address on Plane 0 35h Add. (5 cycles) Col. Add. 1, 2 and Row Add. 1, 2, 3 Source Address on Plane 1 1 tDBSY tPROG R/B# I/Ox 85h Add. (5 cycles) 81h 11h Col. Add. 1, 2 and Row Add. 1, 2, 3 (Note 62) Destination Address 1 Add. (5 cycles) 10h 70h Col. Add. 1, 2 and Row Add. 1, 2, 3 Destination Address A0 ~ A11 : Fixed ‘Low’ A12 ~ A17 : Fixed ‘Low’ A18 : Fixed ‘Low’ A19 ~ A28 : Fixed ‘Low’ A0 ~ A11 : Fixed ‘Low’ A12 ~ A17 : Valid A18 : Fixed ‘High’ A19 ~ A28 : Valid Plane 0 Plane 1 Source Page Source Page Target Page (1) (2) (3) Data Field (1) : Copy Back Read on Plane 0 (2) : Copy Back Read on Plane 1 (3) : Multiplane Copy Back Program Target Page Data Field Spare Field (3) Spare Field Notes 61. Copy Back Program operation is allowed only within the same memory plane. 62. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh. 63. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices. Figure 35. Multiplane Copy Back Program (ONFI 1.0 Protocol) CLE WE# ALE RE# IOx 85h C1 A C2 A R1A R2A R3A SR[6] 85h 11h t IPBSY C1B C2B R1B R2 B R3B 10h t PROG A Notes 64. C1A-C2A Column address for page A. C1A is the least significant byte. 65. R1A-R3A Row address for page A. R1A is the least significant byte. 66. C1B-C2B Column address for page B. C1B is the least significant byte. 67. R1B-R3B Row address for page B. R1B is the least significant byte. 68. The block address bits must be the same except for the bit(s) that select the plane. Document Number: 002-00499 Rev. *Q Page 48 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.19 Read Status Register Timing Figure 36. Read Status Cycle tCLR CLE tCLS tCLH tCS CE# tCH tWP WE# tCEA tWHR tCHZ tCOH RE# tRHZ tDH tDS I/Ox tIR tREA 70h tRHOH Status Output = Don’t Care 6.20 Read Status Enhanced Timing Figure 37. Read Status Enhanced Timing CLE tWHR WE# ALE RE# tAR I/O0-7 6.21 78h R1 R2 R3 SR Reset Operation Timing Figure 38. Reset Operation Timing WE# ALE CLE RE# I/O7:0 FF t RST R/B# Document Number: 002-00499 Rev. *Q Page 49 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.22 Read Cache Figure 39. Read Cache Operation Timing A CE# CLE tWC ALE WE# tWB tWB tWB tRC RE# tRC tRR tRR I/Ox Col. Add 1 00h Col. Add 2 Row Add 1 Column Address 00h Row Add 2 Row Add 3 30h Dout 1 Dout 0 31h Col. Add. 0 Page Address N Dout 1 Page N + 1 Col. Add. 0 Page N tCBSYR tCBSYR tR R/B# Dout 0 31h Dout 5 1 2 3 A 4 CE# CLE ALE WE# tWB tWB tRC tRC RE# tRR I/Ox Dout tRR Dout 0 31h Dout 1 Dout Page N + 2 Col. Add. 0 tCBSYR 6 5 8 7 9 Page N Data Cache 2 1 Page Buffer Dout Page N + 3 Col. Add. 0 tCBSYR R/B# Dout 1 Dout 0 3Fh Page N + 1 4 3 Page N + 2 6 5 3 5 Page N + 3 8 7 9 Page N + 3 Page N + 2 Page N + 1 Page N 1 = Don’t Care 7 Cell Array Page N Page N + 1 Page N + 2 Page N + 3 Figure 40. “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation As defined for Read Cycle Type CMD CMD Dout Dout Dout CMD I/Ox 30h 31h D0 ... Dn 31h tWB SR[6] Document Number: 002-00499 Rev. *Q tWB tR tRR tCBSYR Dout D0 tWB tRR tCBSYR Page 50 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Figure 41. “Random” Read Cache Timing, Start (and Continuation) of Cache Operation As defined for Read A Cycle Type CMD CMD ADDR ADDR I/Ox 30h 00h C1 C2 ADDR ADDR ADDR CMD R3 31h Dout Dout Dout D0 ... Dn Page N R1 R2 tRR tR tWB SR[6] tWB tRR tCBSYR A Cycle Type CMD ADDR ADDR 00h C1 C2 ADDR ADDR ADDR CMD R3 31h Dout Page R I/Ox R1 R2 D0 tWB SR[6] tRR tCBSYR Figure 42. Read Cache Timing, End Of Cache Operation As defined for Read Cache (Sequential or Random) Cycle Type CMD I/Ox 31h tRR tWB SR[6] tCBSYR Document Number: 002-00499 Rev. *Q Dout Dout Dout CMD D0 ... Dn 3Fh tWB Dout Dout Dout D0 ... Dn tRR tCBSYR Page 51 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.23 Cache Program Figure 43. Cache Program CLE CE# tWC tWC WE# tWB ALE RE# 80h I/Ox Col. Add1 Col. Add2 Row. Add1 Column Address Row. Add2 Row. Add3 Din N Din M 15h 80h Row Address Col. Add1 Col. Add2 Row. Add1 Column Address Row. Add2 Row. Add3 Din N Din M 15h Row Address R/B# tCBSYW tCBSYW 1 CLE CE# tWC WE# ALE RE# tADL I/Ox 80h Col. Add1 Col. Add2 Column Address Row. Add1 Row. Add2 Row. Add3 Din N Din M 10h 70h Status Row Address R/B# 1 Document Number: 002-00499 Rev. *Q tPROG Page 52 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.24 Multiplane Cache Program — S34ML02G2 and S34ML04G2 Figure 44. Multiplane Cache Program Command Input Address Input 80h 11h Data Input A0~A11: Valid A12~A17: Fixed ‘Low’ A18: Fixed ‘Low’ A19~A28: Fixed ‘Low’ RY/BY# Data Input Address Input 81h 15h A0~A11: Valid A12~A17: Valid A18: Fixed ‘High’ A19~A28: Valid tDBSY tCBSYW 1 Return to 1 Repeat a max of 63 times Command Input Address Input 80h 11h Data Input A0~A11: Valid A12~A17: Fixed ‘Low’ A18: Fixed ‘Low’ A19~A28: Fixed ‘Low’ RY/BY# Data Input Address Input 81h 10h A0~A11: Valid A12~A17: Valid A18: Fixed ‘High’ A19~A28: Valid tDBSY tPROG 1 CLE CE# tWC tWB WE# ALE tWB RE# tADL I/Ox 80h Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 Din N tADL Din M 11h 81h Row Address Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 Din N Din M 15h Row Address R/B# tDBSY tCBSYW 1 CLE CE# tWC tWB WE# ALE RE# I/Ox 80h Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 Din N Din M 81h 11h Row Address Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 Din N Din M 10h 70h Status Row Address R/B# 1 tDBSY tPROG Notes 69. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used. 70. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices. Document Number: 002-00499 Rev. *Q Page 53 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Figure 45. Multiplane Cache Program (ONFI 1.0 Protocol) Command Input Address Input 80h 11h Data Input Data Input Address Input 80h 15h tDBSY RY/BY# tCBSYW 1 Return to 1 Repeat a max of 63 times Command Input Address Input 80h 11h Data Input Data Input Address Input 80h 10h tPROG tDBSY RY/BY# 1 CLE CE# tWC tWB WE# ALE tWB RE# tADL IOx 80h Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 tADL Din N Din M 11h 80h Row Address Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 Din N Din M 15h Row Address R/B# tDBSY tCBSYW 1 CLE CE# tWC tWB WE# ALE RE# 80h IOx Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 Din N Din M 80h 11h Row Address Col. Add1 Col. Add2 Row Add1 Column Address Row Add2 Row Add3 Din N Din M 10h 70h Status Row Address R/B# 1 tDBSY tPROG Notes 71. The block address bits must be the same except for the bit(s) that select the plane. 72. Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used. Document Number: 002-00499 Rev. *Q Page 54 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.25 Read ID Operation Timing Figure 46. Read ID Operation Timing CLE CE# WE# tWHR tAR ALE tREA RE# 1 Gb Device I/Ox 2 Gb Device I/Ox I/Ox 4 Gb Device 90h 00h 01h F1h 80h 1Dh 90h 00h 01h DAh 90h 95h 46h 09h 90 00h 01h DCh 90h 95h 56h Maker Code Device Code 4th Cycle 5th Cycle Read ID Command 6.26 Address 1 Cycle 3rd Cycle Read ID2 Operation Timing Figure 47. Read ID2 Operation Timing CLE CE# WE# tR ALE RE# I/Ox 30h 65h 00h 00h 02h 02h 00h 30h Read ID2 Commands 4 Cycle Address Read ID2 Confirm Command ID2 Data ID2 Data ID2 Data 1st Cycle 2nd Cycle 3rd Cycle ID2 Data ID2 Data 4th Cycle 5th Cycle R/B# (Note 73) Busy Notes 73. 4-cycle address is shown for the S34ML01G2. For S34ML02G2 and S34ML04G2, insert an additional address cycle of 00h. 74. If Status Register polling is used to determine completion of the Read ID2 operation, the Read Command (00h) must be issued before ID2 data can be read from the flash. Document Number: 002-00499 Rev. *Q Page 55 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.27 Read ONFI Signature Timing Figure 48. ONFI Signature Timing CLE WE# ALE RE# IO0~7 t WHR 90h 20h 4Fh 4Eh 46h 49h tREA 6.28 Read Parameter Page Timing Figure 49. Read Parameter Page Timing CLE WE# ALE RE# IO0-7 ECh 00h P00 P10 ... P01 P11 ... tR R/B# Note 75. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page buffer. 6.29 Read Unique ID Timing (Contact Factory) Figure 50. Read Unique ID Timing CLE WE# ALE RE# IO0-7 EDh R/B# Document Number: 002-00499 Rev. *Q 00h U00 U10 ... U01 U11 ... tR Page 56 of 71 S34ML01G2 S34ML02G2 S34ML04G2 6.30 OTP Entry Timing Figure 51. OTP Entry Timing CLE WE# ALE I/O0-7 6.31 29h 17h 04h 19h Power On and Data Protection Timing Figure 52. Power On and Data Protection Timing Vcc(min) VTH Vcc(min) VTH VCC 0V don’t care don’t care CE VIH Operation 5 ms max VIL WP VIL 100 µs max Invalid don’t care Ready/Busy Note 76. VTH = 1.8 Volts. 6.32 WP# Handling Figure 53. Program Enabling / Disabling Through WP# Handling WE# WE# tWW I/Ox tWW 80h 10h I/Ox WP# WP# R/B# R/B# 80h 10h Figure 54. Erase Enabling / Disabling Through WP# Handling WE# WE# tWW I/Ox tWW 60h D0h I/Ox WP# WP# R/B# R/B# Document Number: 002-00499 Rev. *Q 60h D0h Page 57 of 71 S34ML01G2 S34ML02G2 S34ML04G2 7. Physical Interface 7.1 Physical Diagram 7.1.1 48-Pin Thin Small Outline Package (TSOP1) Figure 55. TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline PACKAGE SYMBOL NOTES: TS/TSR 48 JEDEC MO-142 (D) DD MIN NOM MAX A --- --- 1.20 A1 0.05 --- 0.15 A2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 E 11.90 12.00 12.10 e L 0.50 BASIC 0.50 0.60 0˚ --- 8 R 0.08 --- 0.20 48 Document Number: 002-00499 Rev. *Q DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994). 2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). 3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK. 4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE. 6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm. 7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. 8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE SEATING PLANE. 9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 0.70 O N 1. 5006 \ f16-038 \ 6.5.13 Page 58 of 71 S34ML01G2 S34ML02G2 S34ML04G2 7.1.2 63-Ball, Ball Grid Array (BGA) Figure 56. VBM063 — 63-Pin BGA, 11 mm x 9 mm Package NOTES: PACKAGE VBM 063 JEDEC 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. M0-207(M) 2. ALL DIMENSIONS ARE IN MILLIMETERS. 11.00 mm x 9.00 mm NOM PACKAGE SYMBOL MIN NOM MAX A --- --- 1.00 A1 0.25 --- --- NOTE 4. BALL HEIGHT 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. D 11.00 BSC. E 9.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT BODY SIZE E1 7.20 BSC. MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 63 b 0.40 0.45 BALL COUNT 0.50 n IS THE TOTAL NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 0.80 BSC. BALL PITCH 0.80 BSC. BALL PITCH SD 0.40 BSC. SOLDER BALL PLACEMENT 0.40 BSC. A3-A8,B2-B8,C1,C2,C9,C10 D1,D2,D9,D10,E1,E2,E9,E10 F1,F2,F9,F10,G1,G2,G9,G10 H1,H2,H9,H10,J1,J2,J9,J10 K1,K2,K9,K10 L3-L8,M3-M8 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 “SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL DIAMETER eE SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. MATRIX FOOTPRINT eD SE 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. PROFILE WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW “SD” OR “SE” = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. g5011\ 16-038.25 \ 6.5.13 Document Number: 002-00499 Rev. *Q Page 59 of 71 S34ML01G2 S34ML02G2 S34ML04G2 7.1.3 67-Ball, Ball Grid Array (BGA) Figure 57. VBT067 — 67-Ball BGA, 8 x 6.5 mm Package NOTES: PACKAGE VBT 067 JEDEC N/A NOTE DXE SYMBOL 2. ALL DIMENSIONS ARE IN MILLIMETERS. 8.00 mm x 6.50 mm PACKAGE MIN 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. NOM MAX A --- --- 1.00 A1 0.22 --- --- 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. PROFILE 4. BALL HEIGHT 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. e REPRESENTS THE SOLDER BALL GRID PITCH. D 8.00 BSC BODY SIZE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. E 6.50 BSC BODY SIZE D1 7.20 BSC MATRIX FOOTPRINT n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. MATRIX FOOTPRINT E1 5.60 BSC MD 10 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n Øb 67 0.41 0.46 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 “SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.51 0.80 BSC BALL PITCH eD 0.80 BSC BALL PITCH SD 0.40 BSC SOLDER BALL PLACEMENT SE 0.40 BSC SOLDER BALL PLACEMENT A1,D1,E1,F1,G1 A4,K4,A5,K5 D8,E8,F8,G8 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, “SD” OR “SE” = 0. BALL DIAMETER eE DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. g5019 \ f16-038.25 \ 10.11.13 Document Number: 002-00499 Rev. *Q Page 60 of 71 S34ML01G2 S34ML02G2 S34ML04G2 8. System Interface To simplify system interface, CE# may be unasserted during data loading or sequential data reading as shown in Figure 58. By operating in this way, it is possible to connect NAND flash to a microprocessor. Figure 58. Program Operation with CE# Don't Care CLE CE# don’t care CE# WE# ALE I/Ox 80h St art Add. (5 Cycle) Dat a I nput Data Input 10h Figure 59. Read Operation with CE# Don't Care CLE CE# don’t care CE# RE# ALE R/B# tR WE# I/Ox 00h St art Add. (5 Cycle) 30h Dat a Out put ( sequent ial) Figure 60. Page Programming Within a Block Page 63 (64) Page 63 (64) Page 31 (32) Page 31 (1) Page 2 Page 1 Page 0 (3) (2) (1) From the LSB page to MSB page Document Number: 002-00499 Rev. *Q (3) Page 1 Page 0 (32) (1) Data Register Data Register DATA IN : Data (1) Page 2 Data (64) Ex.) Random page program (Optional) DATA IN : Data (1) Data (64) Page 61 of 71 S34ML01G2 S34ML02G2 S34ML04G2 9. Error Management 9.1 System Bad Block Replacement Over the lifetime of the device, additional Bad Blocks may develop. In this case, each bad block has to be replaced by copying any valid data to a new block. These additional Bad Blocks can be identified whenever a program or erase operation reports “Fail” in the Status Register. The failure of a page program operation does not affect the data in other pages in the same block, thus the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. Refer to Table 28 and Figure 61 for the recommended procedure to follow if an error occurs during an operation. Table 28. Block Failure Operation Recommended Procedure Erase Block Replacement Program Block Replacement Read ECC (4 bit / 512+16 byte) Figure 61. Bad Block Replacement Block A Block B (78) Data th N page Data th Failure (77) N page (79) FFh FFh buffer memory of the controller Notes 77. An error occurs on the Nth page of Block A during a program operation. 78. Data in Block A is copied to the same location in Block B, which is a valid block. 79. The Nth page of block A, which is in controller buffer memory, is copied into the Nth page of Block B. 80. Bad block table should be updated to prevent from erasing or programming Block A. Document Number: 002-00499 Rev. *Q Page 62 of 71 S34ML01G2 S34ML02G2 S34ML04G2 9.2 Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block where the 1st byte in the spare area of the 1st or 2nd or last page does not contain FFh is a Bad Block. That is, if the first page has an FF value and should have been a non-FF value, then the non-FF value in the second page or the last page will indicate a bad block.The Bad Block Information must be read before any erase is attempted, as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information, it is recommended to create a Bad Block table following the flowchart shown in Figure 62. The host is responsible to detect and track bad blocks, both factory bad blocks and blocks that may go bad during operation. Once a block is found to be bad, data should not be written to that block.The 1st block, which is placed on 00h block address is guaranteed to be a valid block. Figure 62. Bad Block Management Flowchart Start Block Address= Block 0 Increment Block Address (81) Data =FFh? No Update Bad Block Table Yes Last Block? No Yes End Note 81. Check for FFh at the 1st byte in the spare area of the 1st, 2nd, and last pages. Document Number: 002-00499 Rev. *Q Page 63 of 71 S34ML01G2 S34ML02G2 S34ML04G2 10. Ordering Information The ordering part number is formed by a valid combination of the following: S34ML 04G 2 00 T F I 00 0 Packing Type 0 = Tray 3 = 13” Tape and Reel Model Number 00 = Standard Interface / ONFI (×8) 00 = Standard Interface (×16) 01 = ONFI (×16) Temperature Range I = Industrial (-40°C to + 85°C) A = Industrial with AECQ-100 and GT Grade (-40˚C to +85˚C) V = Industrial Plus (-40°C to + 105°C) B = Industrial Plus with AECQ-100 and GT Grade (-40˚C to +105˚C) Materials Set F = Lead (Pb)-free H = Lead (Pb)-free and Low Halogen Package B = 63-Ball BGA G = 67-Ball BGA T = TSOP Bus Width 00 = ×8 NAND, single die 04 = ×16 NAND, single die Technology 2 = Cypress NAND Revision 2 (32 nm) Density 01G = 1 Gb 02G = 2 Gb 04G = 4 Gb Device Family S34ML Cypress SLC NAND Flash Memory for Embedded Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Contact your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Device Density Technology Family S34ML Bus Width Package Type Temperature Range 01G 04 TF I 01G 00 BH, GH, TF I, A, V, B 04 TF I 00 BH, GH, TF I, A, V, B (83) 04G 00 BH, TF I, A, V, B 04G 04 BH I 02G 02G 2 Additional Ordering Options Packing Type Package Description 00, 01 Unique ID Support guaranteed: 90 _ Standard Interface / ONFI 1.0 (×8) 91 _ ONFI 1.0 (×16) 0, 3 TSOP, BGA (82) Notes 82. BGA package marking omits the leading “S34” and the Packing Type designator from the ordering part number. 83. Contact sales regarding the availability of S34ML02G2 products in A,V and B temperature ranges. Document Number: 002-00499 Rev. *Q Page 64 of 71 S34ML01G2 S34ML02G2 S34ML04G2 11. Document History Document Title: S34ML01G2, S34ML02G2, S34ML04G2 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded Document Number: 002-00499 Rev. ECN No. Orig. of Change ** - XILA *A - Submission Date XILA Document Number: 002-00499 Rev. *Q Description of Change 08/03/2012 Initial release 11/27/2012 Global: Upgraded data sheet designation from Advance Information to Preliminary Note the S34ML02G2 is in the Advance Information designation Added x16 I/O bus width data Performance Reliability: changed “with 1 bit ECC” to “with 4 bit ECC” Connection Diagram: Added 63-VFBGA Contact, x16 Device (Balls Down, Top View) figure Array Organization: Added Array Organization — x16 figure Addressing: Address Cycle Map 1G/2G/4G Device tables: added x16 data Multiplane Program — S34ML02G2 and S34ML04G2 Added text Multiplane Block Erase — S34ML02G2 and S34ML04G2 Added text Multiplane Copy Back Program —S34ML02G2 and S34ML04G2 Added text Read ID Read ID for Supported Configurations table: corrected x8 information Added x16 information: Read ID for Supported Configurations table Read ID Byte 4 Description — S34ML01G2 table Read ID Byte 4 Description — S34ML02G2 and S34ML04G2 Read Parameter Page Parameter Page Description table: updated values for Bytes 254-255 Absolute Maximum Ratings Absolute Maximum Ratings table: updated Input or Output Voltage, and Supply Voltage values added note AC Characteristics AC Characteristics table: added CE# access time added note for tCOH and tRHOH Page 65 of 71 S34ML01G2 S34ML02G2 S34ML04G2 11. Document History (Continued) Document Title: S34ML01G2, S34ML02G2, S34ML04G2 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded Document Number: 002-00499 Rev. ECN No. Orig. of Change Submission Date Description of Change Multiplane Page Program Operation —S34ML02G2 and S34ML04G2 Added note to Multiplane Page Program figure Added note to Multiplane Page Program (ONFI 1.0 Protocol) figure Multiplane Block Erase — S34ML02G2 and S34ML04G2 Added note to Multiplane Block Erase figure Added note to Multiplane Block Erase (ONFI 1.0 Protocol) figure *A (Cont.) - XILA Multiplane Copy Back Program —S34ML02G2 and S34ML04G2 Added note to Multiplane Copy Back Program figure 11/27/2012 Multiplane Copy Back Program (ONFI 1.0 Protocol) figure: Changed IOx values Updated notes Error Management :Block Failure table: Changed ECC 1 bit to 4 bit Multiplane Cache Program —S34ML02G2 and S34ML04G2 Multiplane Cache Program figure: Removed A13-A31 Address Input values Added note Ordering Information : Added x16 Model Numbers *B - XILA Command Set Added Page Reprogram command Reorganized Command Set table Page Reprogram Moved section Added paragraph Copy Back Program :Added paragraph Reset: Updated paragraph Read ID2: Added text Read Parameter Page Parameter Page Description table: fixed Values of Bytes 6-7 and 254-255 fixed Description of Bytes 129-130 and 131-132 Absolute Maximum Ratings Fixed Value for VIO and VCC 12/19/2012 DC Characteristics DC Characteristics and Operating Conditions table: Changed Power On Current Test Conditions and Typ/Max values AC Characteristics AC Characteristics table: added note Page Read Operation Page Read Operation (Read One Page) figure: added note Read ID2 Operation Timing Read ID2 Operation Timing figure: replaced tWHR with tR and added R/B# timing signal added note Bad Block Management Added text Bad Block Management Flowchart: updated note Document Number: 002-00499 Rev. *Q Page 66 of 71 S34ML01G2 S34ML02G2 S34ML04G2 11. Document History (Continued) Document Title: S34ML01G2, S34ML02G2, S34ML04G2 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded Document Number: 002-00499 Rev. *C *D ECN No. XILA - Orig. of Change Submission Date - XILA Description of Change Distinctive Characteristics: Corrected Plane Size for x16 Page Program Added paragraph Multiplane Program — S34ML02G2 andS34ML04G2 Added paragraph Page Reprogram: Added paragraph Block Erase Added paragraph Multiplane Block Erase — S34ML02G2 and S34ML04G2 Added paragraph Copy Back Program Added paragraph Multiplane Copy Back Program —S34ML02G2 and S34ML04G2 02/14/2013 Added paragraph Multiplane Cache Program —S34ML02G2 and S34ML04G2 Added paragraph Read Parameter Page Added paragraphs Parameter Page Description table: corrected value for bytes 129-130, 131-132, and 254-255 Valid Blocks Updated table AC Characteristics AC Characteristics table: corrected Min value for tALS, tCLS, and tDS corrected Max value for tCEA Distinctive Characteristics Operating Temperature: removed Commercial and Extended temperatures Performance Updated Page Read / Program and Reliability sections General Description Updated section Block Diagram Updated Functional Block Diagram figure Array Organization Updated figures Added two figures: Array Organization — S34ML02G2 and S34ML04G2 (x8) Array Organization — S34ML02G2 and S34ML04G2 (x16) 06/19/2013 Addressing Appended Note in all Address Cycle Map tables Added text to Bus Cycle column in all Address Cycle Map tables Page Read Updated section Page Program Updated section Multiplane Program — S34ML02G2 andS34ML04G2 Updated section Page Reprogram Corrected Page Reprogram figure Corrected Page Reprogram with Data Manipulation figure Copy Back Program Updated section Read Status Register Field Definition Updated Status Register Coding table Document Number: 002-00499 Rev. *Q Page 67 of 71 S34ML01G2 S34ML02G2 S34ML04G2 11. Document History (Continued) Document Title: S34ML01G2, S34ML02G2, S34ML04G2 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded Document Number: 002-00499 Rev. ECN No. Orig. of Change Submission Date Description of Change Read ID Read ID for Supported Configurations table: corrected 2nd cycle for 1 Gb x16 Read ID Byte 5 Description — S34ML02G2 and S34ML04G2 table: corrected Description for Plane Size Read Parameter Page Parameter Page Description table: corrected value for bytes 8-9, 114, 137-138, 139-140, and 254-255 Read Unique ID Added section Ready/Busy Updated section Updated Ready/Busy Pin Electrical Application figure Electrical Characteristics Absolute Maximum Ratings table: removed Ambient Operating Temperature (Commercial Temperature Range) and Ambient Operating Temperature (Extended Temperature Range) AC Characteristics AC Characteristics table: updated ‘Data transfer from cell to register’ Parameter Program / Erase Characteristics *D (Cont.) - XILA 06/19/2013 Program / Erase Characteristics table: added Dummy Busy Time for Multiplane Program(S34MS02G2, S34MS04G2) Multiplane Page Program Operation —S34MS02G2 and S34MS04G2 Updated Multiplane Page Program figure Updated Multiplane Page Program (ONFI 1.0 Protocol) figure Copy Back Read with Optional Data Readout Corrected Copy Back Read with Optional Data Readout figure Copy Back Program Operation With Random Data Input Corrected Copy Back Program Operation With Random Data Input figure Read Status Register Timing : Removed Read Status Enhanced Cycle figure Read Status Enhanced Timing: Removed Read Status Timing figure Read Cache Corrected Read Cache Operation Timing figure Removed Cache Timing heading Cache Program: Updated Cache Program figure Read Parameter Page Timing Added Note to Read Parameter Page Timing figure Read Unique ID Timing Added section Read Parameter Page Timing Added Note to Read Parameter Page Timing figure Document Number: 002-00499 Rev. *Q Page 68 of 71 S34ML01G2 S34ML02G2 S34ML04G2 11. Document History (Continued) Document Title: S34ML01G2, S34ML02G2, S34ML04G2 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded Document Number: 002-00499 Rev. *D (Cont.) ECN No. Orig. of Change - XILA - XILA Submission Date Description of Change Read Unique ID Timing Added section Physical Interface Updated figures: TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package 06/19/2013 Outline VBM063 — 63-Pin BGA, 11 mm x 9 mm Package Ordering Information Clarified Bus Width and Technology Added Note to Valid Combinations table *E Mode Selection: Changed ‘Busy Time in Read’ WE# from X to High 08/09/2013 System Interface: Updated paragraph Updated Read Operation with CE# Don’t Care figure *F - Performance Package Options: added 67-Ball BGA 8 x 6 x 1 mm Connection Diagram :Added figure: 67-BGA Contact (Balls Down, Top View) 11/01/2013 Physical Diagram : Added figure: 67-Ball, Ball Grid Array (BGA) Ordering Information: Added to ‘Package’ Valid Combinations Added ‘GH’ to Package Type Added ‘Unique ID support guaranteed’ to Additional Ordering Options *G - *H - *I - *J - *K 5030732 XILA XILA XILA XILA XILA XILA Document Number: 002-00499 Rev. *Q Global 01/06/2014 Upgraded data sheet designation from Preliminary to Full Production Note the S34ML02G2 is in the Advance Information designation Ordering Information 07/03/2014 Added A, V, B to Temperature Range Valid Combinations table: added A to Temperature Range of 01G Density Ordering Information 09/05/2014 Valid Combinations table: added Package Type BH and TF for 01G Density corrected Package Type for 02G Density Distinctive Characteristics Operating Temperature: added Industrial Plus 04/17/2015 Read Parameter :Page Updated Note Read Unique ID (Contact Factory): Unique ID Data Description (Contact Factory) table: added Note Ordering Information: Valid Combinations table: updated table 12/02/2015 Updated to Cypress template Page 69 of 71 S34ML01G2 S34ML02G2 S34ML04G2 11. Document History (Continued) Document Title: S34ML01G2, S34ML02G2, S34ML04G2 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded Document Number: 002-00499 Rev. ECN No. Orig. of Change Submission Date Description of Change Added Recommended Operating Conditions section. Updated DC Characteristics section - updated “VCC supply Voltage (erase 04/25/2016 and program lockout)” to "Erase and Program Lockout voltage”. Updated Ordering Information. Updated “Read Parameter Page” section. Updated copyright information at the end of the document. *L 5160512 XILA *M 5290473 XILA *N 5409174 XILA *O 5962128 AESATMP8 *P 5995650 MNAD 12/21/2017 Added “Thermal Resistance” on page 38. *Q 6136889 MNAD 04/13/2018 Sunset review. No content update. Updated the part numbers under Package Options in the ‘Performance” 05/31/2016 section. Updated “Valid Combinations”. 08/30/2016 Updated Reliability features in Performance on page 1. 11/09/2017 Updated logo and Copyright. Updated template. Updated Figure 44. Document Number: 002-00499 Rev. *Q Page 70 of 71 S34ML01G2 S34ML02G2 S34ML04G2 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 002-00499 Rev. *Q Revised April 13, 2018 Page 71 of 71