S34MS16G2
16 Gb, 4-Bit ECC, ×8 I/O, and 1.8 V VCC
NAND Flash for Embedded
Distinctive Characteristics
Performance
Density
– 16 Gb (4 Gb 4)
Architecture (For each 4 Gb device)
– Input / Output Bus Width: 8-bits
– Page Size: (2048 + 128) bytes; 128-byte spare area
– Block Size: 64 Pages or (128k + 8k) bytes
– Plane Size
– 2048 Blocks per Plane or (256M + 16M) bytes
– Device Size
– 2 Planes per Device or 512 Mbyte
NAND Flash Interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply Voltage
– 1.8V device: VCC = 1.7V ~ 1.95V
Security
– One Time Programmable (OTP) area
– Serial number (unique ID)
– Hardware program/erase disabled during power transition
Additional Features
– Supports Multiplane Program and Erase commands
– Supports Copy Back Program
– Supports Multiplane Copy Back Program
– Supports Read Cache
Electronic Signature
– Manufacturer ID: 01h
Operating Temperature
– Industrial: 40°C to 85°C
Page Read / Program
– Random access: 30 µs (Max)
– Sequential access: 45 ns (Min)
– Program time / Multiplane Program time: 300 µs (Typ)
Block Erase / Multiplane Erase
– Block Erase time: 3.5 ms (Typ)
Cypress Semiconductor Corporation
Document Number: 002-00464 Rev. *F
•
Reliability
– 100,000 Program / Erase cycles (Typ) (with 4-bit ECC per
528 bytes)
– 10 Year Data retention (Typ)
– Blocks zero and one are valid and will be valid for at least
1000 program-erase cycles with ECC
Package Options
– Lead Free and Low Halogen
– 63-Ball BGA 9 11 1.2 mm
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 16, 2018
S34MS16G2
Contents
Distinctive Characteristics .................................................. 1
Performance.......................................................................... 1
8.3
8.4
Pin Capacitance............................................................ 13
Power Consumptions and Pin Capacitance for Allowed
Stacking Configurations ................................................ 13
1.
General Description..................................................... 3
2.
Connection Diagram.................................................... 3
9.
9.1
Physical Interface ....................................................... 14
63-Ball BGA Package ................................................... 14
3.
Pin Description............................................................. 4
10.
Ordering Information .................................................. 15
4.
Block Diagrams............................................................ 5
5.
Addressing ................................................................... 7
6.
Read Status Enhanced ................................................ 7
7.
7.1
Read ID.......................................................................... 7
Read Parameter Page ................................................... 9
8.
8.1
8.2
Electrical Characteristics .......................................... 12
Valid Blocks ................................................................. 12
DC Characteristics ....................................................... 12
11. Revision History.......................................................... 16
Document History Page ......................................................16
Sales, Solutions, and Legal Information ...........................17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 002-00464 Rev. *F
Page 2 of 17
S34MS16G2
1. General Description
The Cypress® S34MS16G2 16-Gb NAND is offered in 1.8V VCC with x8 I/O interface. This document contains information for the
S34MS16G2 device, which is a quad-die stack of four S34MS04G2 die. For detailed specifications, please refer to the discrete die
data sheet: S34MS01G2_04G2.
2. Connection Diagram
Figure 2.1 63-BGA Contact, x8 Device (Balls Down, Top View)
A1
A2
A9
NC
NC
NC
NC
B9
B10
NC
NC
B1
NC
Document Number: 002-00464 Rev. *F
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC (1)
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS (1)
NC
G3
G4
G5
G6
G7
G8
NC
VCC (1)
NC
NC
NC
NC
H3
H4
H5
H6
H7
H8
NC
I/O0
NC
NC
NC
Vcc
J3
J4
J5
J6
J7
J8
NC
I/O1
NC
VCC
I/O5
I/O7
K3
K4
K5
K6
K7
K8
VSS
I/O2
I/O3
I/O4
I/O6
VSS
A10
L1
L2
L9
L10
NC
NC
NC
NC
M1
M2
M9
M10
NC
NC
NC
NC
Page 3 of 17
S34MS16G2
3. Pin Description
Table 3.1 Pin Description
Pin Name
Description
I/O0 - I/O7
Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The I/O
pins float to High-Z when the device is deselected or the outputs are disabled.
CLE
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on
the rising edge of Write Enable (WE#).
ALE
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the
rising edge of Write Enable (WE#).
CE#
Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the
memory.
WE#
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of
WE#.
RE#
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus.
Data is valid tREA after the falling edge of RE# which also increments the internal column address counter by
one.
WP#
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
R/B#
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC
Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock
circuit prevents the insertion of Commands when VCC is less than VLKO.
VSS
Ground.
NC
Not Connected.
Notes:
1. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.
Document Number: 002-00464 Rev. *F
Page 4 of 17
S34MS16G2
4. Block Diagrams
Figure 4.1 Functional Block Diagram
Address
Register/
Counter
Program Erase
Controller
HV Generation
X
16 Gb Device (4 Gb x 4)
NAND Flash
Memory Array
ALE
CLE
WE#
CE#
WP#
D
E
C
O
D
E
R
Command
Interface
Logic
RE#
Page Buffer
Command
Register
Y Decoder
I/O Buffer
Data
Register
I/O0~I/O7
Document Number: 002-00464 Rev. *F
Page 5 of 17
S34MS16G2
Figure 4.2 Block Diagram — 16 Gb (4 Gb x 4) 63-Ball BGA with 1 CE# (One Chip Enable Signal)
IO0~IO7
CE#
WE#
RE#
4 Gb x8
NAND Flash
Memory#4
RB#
VSS
ALE
VCC
CLE
WP#
IO0~IO7
CE#
WE#
RE#
ALE
RB#
4 Gb x8
NAND Flash
Memory#3
VSS
VCC
CLE
WP#
IO0~IO7
CE#
WE#
RE#
4 Gb x8
NAND Flash
Memory#2
RB#
VSS
ALE
VCC
CLE
WP#
IO0~IO7
CE#
CE#
WE#
WE#
RE#
RE#
ALE
ALE
CLE
CLE
WP#
WP#
Document Number: 002-00464 Rev. *F
4 Gb x8
NAND Flash
Memory#1
IO0~IO7
RB#
RB#
VSS
VSS
VCC
VCC
Page 6 of 17
S34MS16G2
5. Addressing
Table 5.1 Address Cycle Map
Bus Cycle
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st / Col. Add. 1
A0 (CA0)
A1 (CA1)
A2 (CA2)
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
2nd / Col. Add. 2
A8 (CA8)
A9 (CA9)
A10 (CA10)
A11 (CA11)
Low
Low
Low
Low
3rd / Row Add. 1
A12 (PA0)
A13 (PA1)
A14 (PA2)
A15 (PA3)
A16 (PA4)
A17 (PA5)
A18 (PLA0)
A19 (BA0)
4th / Row Add. 2
A20 (BA1)
A21 (BA2)
A22 (BA3)
A23 (BA4)
A24 (BA5)
A25 (BA6)
A26 (BA7)
A27 (BA8)
5th / Row Add. 3 (6) A28 (BA9) A29 (BA10) A30 (BA11)
A31 (BA12)
Low
Low
Low
Low
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. A31 for 16 Gb (4 Gb x 4 – QDP).
For the address bits, the following rules apply:
A0–A11: column address in the page
A12–A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19–A31: block address
6. Read Status Enhanced
Read Status Enhanced is used to retrieve the status value for a previous operation in the following cases:
In the case of concurrent operations on a multi-die stack.
When four dies are stacked to form a quad-die package (QDP), it is possible to run one operation on the first die, then activate a
different operation on the second die, for example: Erase while Read, Read while Program, etc.
In the case of multiplane operations in the same die.
7. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00)
before Read Status command (0x70).
For the S34MS16G2 device, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th,
and 5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Table 7.1 Read ID for Supported Configurations
Density
Org
VCC
1st
2nd
3rd
4th
5th
4 Gb
x8
1.8V
01h
ACh
90h
15h
56h
16 Gb (4 Gb x 4 – QDP with
one CE#)
x8
1.8V
01h
A5h
D2h
15h
5Eh
Document Number: 002-00464 Rev. *F
Page 7 of 17
S34MS16G2
Figure 7.1 Read ID Operation Timing
CLE
CE#
WE#
tWHR
tAR
ALE
tREA
RE#
I/Ox
90h
Read ID
Command
00h
01h
Address 1
Cycle
Maker
Code
A5h
Device
Code
D2h
3rd Cycle
15h
5Eh
4th Cycle
5th Cycle
5th ID Data
Table 7.2 Read ID Byte 5 Description
Description
ECC Level
I/O7
I/O6 I/O5 I/O4
I/O3 I/O2
1 bit / 512 bytes
2 bit / 512 bytes
4 bit / 512 bytes
8 bit / 512 bytes
Plane Number
Plane Size
(without spare area)
Reserved
Document Number: 002-00464 Rev. *F
I/O1 I/O0
00
01
10
11
1
2
4
8
00
01
10
11
64 Mb
128 Mb
256 Mb
512 Mb
1 Gb
2 Gb
4 Gb
000
001
010
011
100
101
110
0
Page 8 of 17
S34MS16G2
7.1
Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an
address input of 00h. The command register remains in Parameter Page mode until further commands are issued to it. Table 7.3
explains the parameter fields.
Note: For 32nm Cypress NAND, for a particular condition, the Read Parameter Page command does not give the correct values. To
overcome this issue, the host must issue a Reset command before the Read Parameter Page command. Issuance of Reset before
the Read Parameter Page command will provide the correct values and will not output 00h values.
Table 7.3 Parameter Page Description
Byte
O/M
Description
Values
Revision Information and Features Block
0-3
4-5
6-7
8-9
M
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4Fh, 4Eh, 46h, 49h
M
Revision number
2-15 Reserved (0)
1
1 = supports ONFI version 1.0
0
Reserved (0)
02h, 00h
M
Features supported
5-15 Reserved (0)
4
1 = supports odd to even page Copyback
3
1 = supports interleaved operations
2
1 = supports non-sequential page programming
1
1 = supports multiple LUN operations
0
1 = supports 16-bit data bus width
1Eh, 00h
M
Optional commands supported
6-15 Reserved (0)
5
1 = supports Read Unique ID
4
1 = supports Copyback
3
1 = supports Read Status Enhanced
2
1 = supports Get Features and Set Features
1
1 = supports Read Cache commands
0
1 = supports Page Cache Program command
3Bh, 00h
Reserved (0)
00h
10-31
Manufacturer Information Block
32-43
M
Device manufacturer (12 ASCII characters)
53h, 50h, 41h, 4Eh, 53h, 49h,
4Fh, 4Eh, 20h, 20h, 20h, 20h
44-63
M
Device model (20 ASCII characters)
53h, 33h, 34h, 4Dh, 53h, 31h,
36h, 47h, 32h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h
64
M
JEDEC manufacturer ID
01h
65-66
O
Date code
00h
Reserved (0)
00h
67-79
Memory Organization Block
80-83
M
Number of data bytes per page
00h, 08h, 00h, 00h
84-85
M
Number of spare bytes per page
80h, 00h
86-89
M
Number of data bytes per partial page
00h, 00h, 00h, 00h
90-91
M
Number of spare bytes per partial page
00h, 00h
Document Number: 002-00464 Rev. *F
Page 9 of 17
S34MS16G2
Table 7.3 Parameter Page Description (Continued)
Byte
O/M
92-95
M
Number of pages per block
40h, 00h, 00h, 00h
96-99
M
Number of blocks per logical unit (LUN)
00h, 40h, 00h, 00h (1 CE#)
100
M
Number of logical units (LUNs)
01h (1 CE#)
101
M
Number of address cycles
4-7 Column address cycles
0-3 Row address cycles
23h
102
M
Number of bits per cell
01h
103-104
M
Bad blocks maximum per LUN
47h, 01h (1 CE#)
105-106
M
Block endurance
01h, 05h
107
M
Guaranteed valid blocks at beginning of target
01h
108-109
M
Block endurance for guaranteed valid blocks
01h, 03h
110
M
Number of programs per page
04h
111
M
Partial programming attributes
5-7 Reserved
4
1 = partial page layout is partial page data followed by
partial page spare
1-3 Reserved
0
1 = partial page programming has constraints
00h
112
M
Number of bits ECC correctability
04h
113
M
Number of interleaved address bits
4-7
Reserved (0)
0-3
Number of interleaved address bits
01h
O
Interleaved operation attributes
4-7 Reserved (0)
3
Address restrictions for program cache
2
1 = program cache supported
1
1 = no block address restrictions
0
Overlapped / concurrent interleaving support
04h
Reserved (0)
00h
114
115-127
Description
Values
Electrical Parameters Block
128
M
I/O pin capacitance
0Ah
M
Timing mode support
6-15 Reserved (0)
5
1 = supports timing mode 5
4
1 = supports timing mode 4
3
1 = supports timing mode 3
2
1 = supports timing mode 2
1
1 = supports timing mode 1
0
1 = supports timing mode 0, shall be 1
03h, 00h
131-132
O
Program cache timing mode support
6-15 Reserved (0)
5
1 = supports timing mode 5
4
1 = supports timing mode 4
3
1 = supports timing mode 3
2
1 = supports timing mode 2
1
1 = supports timing mode 1
0
1 = supports timing mode 0
03h, 00h
133-134
M
tPROG Maximum page program time (µs)
BCh, 02h
129-130
Document Number: 002-00464 Rev. *F
Page 10 of 17
S34MS16G2
Table 7.3 Parameter Page Description (Continued)
Byte
O/M
135-136
M
tBERS Maximum block erase time (µs)
10h, 27h
137-138
M
tR Maximum page read time (µs)
1Eh, 00h
139-140
M
tCCS Minimum Change Column setup time (ns)
C8h, 00h
Reserved (0)
00h
141-163
Description
Values
Vendor Block
164-165
M
166-253
254-255
M
Vendor specific Revision number
00h
Vendor specific
00h
Integrity CRC
11h, F5h (1CE#)
Redundant Parameter Pages
256-511
M
Value of bytes 0-255
Repeat Value of bytes 0-255
512-767
M
Value of bytes 0-255
Repeat Value of bytes 0-255
768+
O
Additional redundant parameter pages
FFh
Note:
1. “O” Stands for Optional, “M” for Mandatory.
Document Number: 002-00464 Rev. *F
Page 11 of 17
S34MS16G2
8. Electrical Characteristics
8.1
Valid Blocks
Table 8.1 Valid Blocks
Device
Symbol
Min
Typ
Max
Unit
S34MS04G2
NVB
4016
—
4096
Blocks
S34MS16G2
NVB
16057 (1)
—
16384
Blocks
Note:
1. Each 4 Gb can have a maximum 80 bad blocks.
8.2
DC Characteristics
Table 8.2 DC Characteristics and Operating Conditions
(Values listed are for each 4 Gb NAND, 16 Gb (4 Gb x 4) will differ accordingly)
Parameter
Symbol
Test Conditions
ICC0
FFh command input
after power on
Typ
Max
Units
—
—
50 per
device
mA
Sequential Read
ICC1
tRC = tRC (min)
CE# = VIL,
Iout = 0 mA
—
15
30
mA
Program
ICC2
Normal
—
15
30
mA
Erase
ICC3
Cache
—
15
30
mA
—
—
15
30
mA
Standby Current, (TTL)
ICC4
CE# = VIH,
WP# = 0V/Vcc
—
—
1
mA
Standby Current, (CMOS)
ICC5
CE# = VCC-0.2,
WP# = 0/VCC
—
10
50
µA
Input Leakage Current
ILI
VIN = 0 to VCC(max)
—
—
±10
µA
Output Leakage Current
ILO
VOUT = 0 to VCC(max)
—
—
±10
µA
Input High Voltage
VIH
—
VCC x 0.8
—
VCC + 0.3
V
Input Low Voltage
VIL
—
-0.3
—
VCC x 0.2
V
Output High Voltage
VOH
IOH = -100 µA
VCC -0.1
—
—
V
Output Low Voltage
VOL
IOL = 100 µA
—
—
0.1
V
IOL(R/B#)
VOL = 0.1V
3
4
—
mA
VLKO
—
—
1.1
—
V
Power On Current
Operating Current
Output Low Current (R/B#)
Erase and Program Lockout Voltage
Min
Notes:
1. All VCC pins, and VSS pins respectively, are shorted together.
2. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking.
3. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
4. Standby current measurement can be performed after the device has completed the initialization process at power up.
Document Number: 002-00464 Rev. *F
Page 12 of 17
S34MS16G2
8.3
Pin Capacitance
Table 8.3 Pin Capacitance (TA = 25°C, f=1.0 MHz)
Parameter
Symbol
Test Condition
Min
Max
Unit
Input
CIN
VIN = 0V
—
10
pF
Input / Output
CIO
VIL = 0V
—
10
pF
Note:
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
8.4
Power Consumptions and Pin Capacitance for Allowed Stacking
Configurations
When multiple dies are stacked in the same package, the power consumption of the stack will increase according to the number of
chips. As an example, the standby current is the sum of the standby currents of all the chips, while the active power consumption
depends on the number of chips concurrently executing different operations.
When multiple dies are stacked in the same package the pin/ball capacitance for the single input and the single input/output of the
combo package must be calculated based on the number of chips sharing that input or that pin/ball.
Document Number: 002-00464 Rev. *F
Page 13 of 17
S34MS16G2
9. Physical Interface
9.1
63-Ball BGA Package
Figure 9.1 63-Ball BGA 9 x 11 x 1.2 mm
PACKAGE
NOTES:
TNA 063
JEDEC
MO-207(N)
DXE
11.00mm X 9.00mm PACKAGE
SYMBOL
MIN.
NOM.
MAX.
A
---
---
1.20
A1
0.25
---
---
NOTE
1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 3, SPP-020.
PROFILE
BALL HEIGHT
D
11.00 BSC
BODY SIZE
E
9.00 BSC
BODY SIZE
D1
8.80 BSC
MATRIX FOOTPRINT
E1
7.20 BSC
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL “MD” IS THE BALL MATRIX SIZE IN THE “D” DIRECTION.
SYMBOL “ME” IS THE BALL MATRIX SIZE IN THE “E” DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
6. DIMENSION “b” IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
BALL DIAMETER
7. “SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW
“SD” OR “SE” = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW
“SD” = eD/2 AND “SE” = eE/2.
eE
0.80 BSC
BALL PITCH
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
eD
0.80 BSC
BALL PITCH
SD
0.40 BSC
SOLDER BALL PLACEMENT
0.40 BSC
SOLDER BALL PLACEMENT
n
Ob
SE
63
0.40
0.45
BALL COUNT
0.50
A3-A8,B2-B8,C1,C2,C9,C10,D1, DEPOPULATED SOLDER BALLS
D2,D9,D10,E1,E2,E9,E10,F1,F2,
F9,F10,G1,G2,G9,G10,H1,H2,H9,
H10,J1,J2,J9,J10,K1,K2,K9,K10,
L3-L8,M3-M8
Document Number: 002-00464 Rev. *F
9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
gs5038-tna063-09.05.14
Page 14 of 17
S34MS16G2
10. Ordering Information
The ordering part number is formed by a valid combination of the following:
S34MS
16G
2
02
B
H
I
00
0
Packing Type
0 = Tray
3 = 13” Tape and Reel
Model Number
00 = Standard Interface / ONFI (x8)
20 = Two Chip Enable with Standard ONFI (x8)
Temperature Range
I = Industrial (–40°C to + 85°C)
Materials Set
F = Lead (Pb)-free
H = Lead (Pb)-free and Low Halogen
Package
B = BGA
T = TSOP
Bus Width
00 = x8 NAND, single die
04 = x16 NAND, single die
01 = x8 NAND, dual die
02 = x8 NAND, quad die
05 = x16 NAND, dual die
Technology
2 = Cypress NAND Revision 2 (32 nm)
Density
01G = 1 Gb
02G = 2 Gb
04G = 4 Gb
08G = 8 Gb
16G = 16 Gb
Device Family
S34MS
Cypress SLC NAND Flash Memory for Embedded
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Valid Combinations
Device
Family
Density
Technology
Bus
Width
Package
Type
Temperature
Range
Additional
Ordering Options
Packing
Type
Package
Description
S34MS
16G
2
02
BH
I
BH – 00
0, 3
BGA
Document Number: 002-00464 Rev. *F
Page 15 of 17
S34MS16G2
11. Revision History
Document History Page
Document Title: S34MS16G2, 16 Gb, 4-Bit ECC, x8 I/O, and 1.8 V VCC NAND Flash for Embedded
Document Number: 002-00464
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
–
XILA
12/12/2014
Initial release
*A
–
XILA
04/24/2015
Performance: Corrected Package Options for 63-Ball BGA to 9 x 11 x 1.2 mm
Physical Interface: Corrected figure title to ‘63-Ball BGA 9 x 11 x 1.2 mm’
Ordering Information: Ordering Information table: corrected Model Number and
Materials Set
*B
4962771
XILA
10/14/2015
Updated to Cypress template.
*C
5244672
XILA
04/28/2016
Changed status from Advance to Final.
Updated Read ID:
Updated Read Parameter Page:
Updated description.
Updated to new template.
*D
5497766
XILA
10/27/2016
Updated Electrical Characteristics:
Updated DC Characteristics:
Updated Table 8.2.
Updated Notes 1 and 2.
Updated to new template.
*E
5962114
AESATMP8
11/09/2017
Updated logo and Copyright.
*F
6100827
MNAD
03/16/2018
Updated to new template.
Completing Sunset Review.
Document Number: 002-00464 Rev. *F
Page 16 of 17
S34MS16G2
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2014-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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Document Number: 002-00464 Rev. *F
Revised March 16, 2018
Page 17 of 17
