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S6BT112A01/S6BT112A02
ASSP CXPI Transceiver IC for
Automotive Network
The S6BT112A01 and S6BT112A02 are integrated transceiver ICs for automotive communication network with Clock Extension
Peripheral Interface (CXPI). It has a flexible bit rate ranging from 2.4 kbps to 20 kbps and is JASO and ISO CXPI compliant. This
CXPI transceiver IC connects the CXPI data link controller and the CXPI Bus line, and enables direct connection to the vehicle
battery with a high surge protection. Additionally, S6BT112A01 have an optional Spread Spectrum Clock Generator (SSCG)
function, which is effective at master node. During Sleep mode, S6BT112A01 and S6BT112A02 reduce power consumption. The
CXPI transceiver IC supports master node and slave node, which is set by SELMS pins.
Features
◼ Compliant with the JASO CXPI (JASO D 015-3: 2015)
standard
◼ Compliant with the SAE CXPI (J3076_201510) standard
◼ Compliant with the ISO CXPI (ISO 20794-4: 2020) standard
◼ Supports 2.4 kbps to 20 kbps bitrate
◼ Waveshaping for low Electromagnetic Interference (EMI)
◼ Operating voltage range: 5.3 V to 18 V
◼ Overtemperature protection
◼ Low-voltage detection
◼ Supports Sleep and Wakeup modes
◼ Sleep mode current: 6 µA (typical at Slave)
◼ Halogen-free 8-pin SOIC package
◼ ESD protection HBM (1.5 kΩ, 100 pF) ±8 kV (BUS pin, BAT
pin)
◼ Direct battery operation with protection against load dump,
jump start, and transients
◼ Voltage tolerance ±40 V (BUS pin)
◼ S6BT112A01: With SSCG
◼ BUS short to VBAT overcurrent protection
S6BT112A02: Without SSCG
◼ Loss of ground protection; BUS pin leakage is lower than
±1 mA
◼ Easy selection of master node or slave node
◼ AEC-Q100 compliant (Grade-1)
◼ Application Notes: AN227376 - Getting Started with CXPI
Transceiver S6BT112A
S6BT112A Block Diagram
Cypress Semiconductor Corporation
Document Number: 002-10203 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 3, 2021
S6BT112A01/S6BT112A02
Table of Contents
1. Applications
............................................................................................................................................................. 3
2. Pin Assignment
............................................................................................................................................................. 4
3. Pin Descriptions
............................................................................................................................................................. 5
4. Block Diagram
............................................................................................................................................................. 6
5. Function Description .......................................................................................................................................................... 7
5.1 Operation Modes ........................................................................................................................................................... 7
5.2 Master Node .................................................................................................................................................................. 8
5.3 Slave Node .................................................................................................................................................................. 11
5.4 Common Functions ..................................................................................................................................................... 15
6. Absolute Maximum Ratings ............................................................................................................................................. 21
7. Recommended Operating Conditions ............................................................................................................................ 22
8. Electrical Characteristics ................................................................................................................................................. 23
9. Ordering Information ........................................................................................................................................................ 34
10. Package Dimensions ...................................................................................................................................................... 34
Document History
........................................................................................................................................................... 35
Sales, Solutions, and Legal Information............................................................................................................................. 37
Document Number: 002-10203 Rev. *H
Page 2 of 37
S6BT112A01/S6BT112A02
1. Applications
Figure 1-1 and Figure 1-2 illustrate the typical applications of S6BT112A01 or S6BT112A02.
Figure 1-1 Typical Application as Master
S6BT112A AS MASTER
12V Battery
CXPI BUS LINE
BAT
S6BT112A: CXPI Transceiver IC
Regulator
RC
OSC
5V
VCC
SELMS
MCU
LDO Regulator
Thermal Shutdown
Low Voltage Detection
Over Current Protection
CLK
TXD
RXD
NSLP
UART
CXPI
Control
Logic
VSS
CXPI
PHY
BUS
GND
Figure 1-2 Typical Application as Slave
S6BT112A AS SLAVE
12V Battery
CXPI BUS LINE
BAT
S6BT112A: CXPI Transceiver IC
Regulator
RC
OSC
5V
VCC
SELMS
MCU
CLK
TXD
RXD
NSLP
UART
LDO Regulator
Thermal Shutdown
Low Voltage Detection
Over Current Protection
CXPI
Control
Logic
VSS
CXPI
PHY
BUS
GND
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Page 3 of 37
S6BT112A01/S6BT112A02
2. Pin Assignment
Figure 2-1. Pin Assignment
(TOP VIEW)
RXD 1
8 SELMS
7
BAT
3
6
BUS
TXD 4
5
GND
NSLP 2
CLK
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S6BT112A01/S6BT112A02
3. Pin Descriptions
Table 3-1. Pin Descriptions
Pin
Symbol
Number
1
RXD
Direction
Output
Description
Receive data output (open-drain)
Requires external pull-up resistor (refer to Table 7-1)
Sleep control input
2
NSLP
Input
Low: Sleep mode
High: Normal mode or Standby mode
Refer to section 5.2.2 or section 5.3.2
When the SELMS pin is low level, the CLK pin is the baud rate clock input
Input clock signal with baud rate frequency
(When the input clock frequency is 20 kHz, the bit rate is 20 kbps)
3
CLK
I/O
When the SELMS pin is high level, the CLK pin is baud rate clock output
Outputs clock signal with baud rate frequency
(When the output clock frequency is 20 kHz , the bit rate is 20 kbps)
Open drain output
Requires external pull-up resistor (refer to Table 7-1)
4
TXD
Input
5
GND
-
6
BUS
I/O
7
BAT
-
Transmit data input
Ground
CXPI BUS line Input/Output
Battery (voltage source) supply
Master / slave node select input
8
SELMS
Input
Low: Master
High: Slave
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S6BT112A01/S6BT112A02
4. Block Diagram
Figure 4-1. Block Diagram
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Page 6 of 37
S6BT112A01/S6BT112A02
5. Function Description
5.1
Operation Modes
Figure 5-1. State Transition Diagram
Notes
[1] : “Hi-z” means high-impedance.
[2] : Switching of the master / slave during transmitting is prohibited. Refer to section 5.4.5.
[3] : The operation mode, after the transceiver powers on, has to start from sleep mode.
[4] : If TXD is low level when releasing the thermal shutdown, TXD has to toggle "High" before transmitting TXD.
For details, refer to section 5.4.7.
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Page 7 of 37
S6BT112A01/S6BT112A02
5.2
Master Node
◼ There is only one node in a system, which functions as a schedule manager and a primary clock master.
◼ The transceiver works in Master mode when low-level is applied on SELMS. See Table 5-1.
◼ The baud rate clock is applied on the CLK pin in the Master state. See Figure 5-2.
◼ The transceiver is usually used as the "Master" or "Slave", except for the “Secondary Clock master function”.
◼ The SELMS input should not be changed in normal mode.
◼ The SELMS input should not be changed during wakeup pulse transmission in Sleep mode.
◼ The CLK pin inputs for the baud rate clock in Master state.
Table 5-1. SELMS Pin State for Master
Pin
Input Signal
Master/Slave
SELMS
Low
Master
Figure 5-2. CLK Input -> BUS Signal (Master)
5.2.1
Normal Mode
The Normal mode denotes the state to which communication is possible. The master node transmits the clock to the CXPI BUS,
which means that the clock is the master. During the Normal mode, the transmitted signal is encoded and the received signal is
decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after converting the data to a UART
format by 1 byte. The data is transmitted to the CXPI BUS as LSB first.
When the receiving node receives data from the CXPI BUS, it receives from the RXD pin in the UART format by 1 byte. The UART
format is listed in Table 5-2. Refer to the JASO or ISO CXPI (JASO D 015-3: 2015, ISO 20794-4: 2020) standard for details of the
operation.
Table 5-2. UART Format
Start bit
bit 0 (LSB)
bit 1
bit 2
Document Number: 002-10203 Rev. *H
bit 3
bit 4
bit 5
bit 6
bit 7(MSB)
Stop bit
Page 8 of 37
S6BT112A01/S6BT112A02
5.2.2
Sleep Mode
The Sleep mode denotes a power-saving state during which each node stops transmitting and receiving data. All nodes transitions
to Sleep mode immediately after power-on. The nodes also transition to Sleep mode after the Sleep processing is executed from the
Normal mode and transition from Standby mode or Normal mode due to CXPI BUS error.
When each node receives the Wakeup condition during the Sleep mode, it transitions to the Standby mode. The Wakeup condition
(for example, detecting that the ignition has been turned on) of each node is different for each application and the external factor that
receives the Wakeup pulse from the CXPI BUS. During the Sleep mode, the reception signal is received without decoding. The MCU
can detect a wakeup pulse width by monitoring the RXD signal.
The sleep mode is initiated by a falling edge on the NSLP pin while TXD is already set high level. The CXPI BUS transmitter output
driver is immediately disabled when the NSLP pin goes low level. The transceiver becomes the normal mode with input high level.
When the input level is switched from low to high, the BUS pin and RXD pin output Hi-Z level during the mode transition time
(TMODE_CHG in Table 8-7).
Stopping the clock input at high level of CLK is recommended. Then turn the NSLP pin to low level after TSLP_WT as shown in Figure
5-3.
The “Pin State” of Table 5-3 indicates before the falling edge in the NSLP pin.
Table 5-3. Transition from Normal to Sleep mode
Pin
Pin State
Description
TXD
High
No data transmitting
CLK
High
No clock receiving
NSLP
High to Low
-
RXD
High impedance
High level with external pull-up resistor.
BUS
High impedance
High level with external pull-up resistor.
SELMS
Low
-
The “Pin State” of Table 5-4 indicates the state before the rising edge in the NSLP pin.
Table 5-4. Transition from Sleep to Normal mode
Pin
Pin State
Description
TXD
High
No data transmitting
CLK
High
No clock receiving
NSLP
Low to High
-
RXD
High impedance
High level with external pull-up resistor.
BUS
High impedance
High level with external pull-up resistor.
SELMS
Low
-
Figure 5-3. Transition Sequence Between Sleep and Normal Mode
TXD High
SELMS
CLK Hi-Z
NSLP Low
NSLP High
Low
TXD
CLK
TSLP_WT
NSLP
TMODE_CHG
BUS
RXD
Note:
[1] “Hi-Z” means high-impedance.
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S6BT112A01/S6BT112A02
5.2.3
Standby Mode
The Standby mode denotes the state of standing by the transition to the Normal mode. The standby mode shall transit only from the
sleep mode. The standby mode is not allowed message transition and reception after releasing the Sleep mode. During this mode,
the RXD pin and the BUS pin are in a high-impedance state. After TMODE_CHG, the state changes to the Normal mode. Then, the BUS
pin activates after a clock input of 33 periods.
5.2.4
Power-on Sequence
The power-on sequence occurs at power-up while setting up Sleep mode. When VBAT is above 5.3 V, the NSLP pin can be set to
high level. After the transition to the normal mode, the BUS pin activates after a clock input of 33 periods. See Figure 5-4.
Figure 5-4. Power-on Sequence of Master Node
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S6BT112A01/S6BT112A02
5.3
Slave Node
All the nodes, except the master node, are connected as slave in the system. The transceiver works as Slave when high level is
applied on SELMS pin. See Table 5-5. The CLK pin outputs the baud rate clock during the Slave state.
The transceiver is usually used as the "Master" or "Slave", except for the “Secondary Clock master function”.
Table 5-5. SELMS Pin State for Slave
Pin
SELMS
Input Signal
High
Master/Slave
Slave
The SELMS input should not be changed during the Normal mode or during wakeup pulse transmission in the Sleep mode. The
CLK pin outputs the baud rate clock in Slave node. See Figure 5-5.
Figure 5-5. CLK Pin Clock Output (Slave)
5.3.1
Normal Mode
The Normal mode can perform data transmit and receive. During the Normal mode, the signal that is transmitted is encoded and the
signal that is received is decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after
converting the data to a UART format by 1 byte. The data is transmitted to the CXPI BUS by LSB first. When the receiving node
receives data from the CXPI BUS, it revises from the RXD pin in the UART format by 1 byte. The UART format is shown in Table 5-6.
Refer to the JASO or ISO CXPI (JASO D 015-3: 2015, ISO 20794-4: 2020) standard for details of the operation.
Table 5-6. UART Format
Start bit
bit 0 (LSB)
bit 1
bit 2
Document Number: 002-10203 Rev. *H
bit 3
bit 4
bit 5
bit 6
bit 7(MSB)
Stop bit
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S6BT112A01/S6BT112A02
5.3.2
Sleep Mode
The Sleep mode denotes a state of power saving during which each node stops transmitting and receive data. All nodes transitions
to the Sleep mode immediately after power-on. They are also transitioning to the Sleep mode after the sleep processing is executed
from the Normal mode and transition from the Standby mode or the Normal mode due to CXPI BUS error.
During the Sleep mode, when each node receives the Wakeup factor, it transitions to the Standby mode. The Wakeup factor is
different from each application and is composed of the internal factor (for example, detecting that the ignition has been turned on)
and the external factor that receives the Wakeup pulse from the CXPI BUS.
During the Sleep mode, the reception signal is received without decoding. The sleep mode is initiated by a falling edge on the NSLP
pin while the TXD pin is already set high level. See Figure 5-6. The CXPI BUS transmits path is immediately disabled when the NSLP
pin goes low level.
All wake-up events must be maintained for a specific period (refer to TMODE_CHG in Table 8-7).
Figure 5-6. Transition Sequence Between Sleep and Normal Mode
SELMS
High
TXD
High
NSLP High
NSLP Low
T MODE_CHG
CLK
NSLP
Wakeup pulse
BUS
RXD
The “Pin State” of Table 5-7 indicates the state before the falling edge of the NSLP pin.
Table 5-7. Transition from Normal to Sleep Mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
High level with external pull-up resistor.
NSLP
High to Low
-
RXD
High impedance
High level with external pull-up resistor.
BUS
High impedance
High level with external pull-up resistor.
SELMS
High
-
The “Pin State” of Table 5-8 indicates the state before the rising edge of the NSLP pin.
Table 5-8. Transition from Sleep to Normal Mode
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
High level with external pull-up resistor.
NSLP
Low to High
-
RXD
High impedance
High level with external pull-up resistor.
BUS
High impedance
High level with external pull-up resistor.
SELMS
High
-
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S6BT112A01/S6BT112A02
◼ Receiver Function in Sleep Mode
During the Sleep mode, the received signal will be output from the CLK pin without decoding a received signal. The RXD pin outputs
at a high level. When the Master node wake-up, it transmits clock signal to the CXPI BUS. During a wake-up sequence, the slave
transceiver does not decode the received signal. So, if the transceiver outputs this signal to RXD, slave MCUs receive shorter lowlevel width signals than the UART communication period and it possibly gets errors. This is because the Slave node is received
without decoding. To avoid these errors, S6BT112A01 or S6BT112A02 CXPI transceiver IC outputs receive signals on the CLK pin
in the Sleep mode.
The MCU can detect a wake-up pulse width by monitoring the CLK signal. (Figure 5-7).
Figure 5-7. CLK Output of Receive Signal, RXD Stays High (for Slave Node)
◼ Wakeup Function
The WakeupPulseOutput state transmits out the wakeup pulse in the Slave node. When the slave device returns from the Sleep
mode, it must transmit a wake-up pulse. As the NSLP pin is in a low level, the TXD pin transmits a low level. The TXD signal is
transmitted to the BUS pin without encode. The TXD pin outputs the signal width, which is a value obtained by subtracting the TTXD_BT:
Signal width
TXD signal (“L”) – TTXD_BT(“L”)
See Figure 5-8. Refer to Table 8-7 for TTXD_BT(“L”).
Figure 5-8. Wake-Up Pulse Transmission
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S6BT112A01/S6BT112A02
As shown in Table 5-9, in case of 19.2 kbps bitrate, 9 bits (start bit plus 8 bits data) of low level in the TXD signal transmites a 402
µs (min) width wakeup pulse to the BUS. In case of 20 kbps bitrate (50 µs/Bit), to transmit over 400 µs wakeup pulse, over 466 µs
TXD low signal is needed, which can be output by a GPIO port with a timer.
Table 5-9. Bitrate of 19.2 kbps (52 µs/Bit)
UART Transmission Data
FCH
Number of Bits of L Level
3-bit
TXD signal (“L”)
156 µs
Wakeup Pulse Width (min)
90 µs
F8H
4-bit
208 µs
142 µs
F0H
5-bit
260 µs
194 µs
5.3.3
E0H
6-bit
312 µs
246 µs
C0H
7-bit
364 µs
298 µs
80H
8-bit
416 µs
350 µs
00H
9-bit
468 µs
402 µs
Standby Mode
The Standby mode denotes the state of standing by the transition to the Normal mode. The standby mode shall transit only from the
sleep mode. The standby mode is not allowed message transition and reception after releasing the Sleep mode. During this mode,
the CLK pin, the RXD pin and the BUS pin are in a high-impedance state. After TMODE_CHG, the state changes to the Normal mode.
5.3.4
Power-on Sequence
This transceiver should be powered up from Sleep mode with the NSLP pin being set to low level. Sleep mode must be released
after VBAT is above 5.3 V with the NSLP pin being set to high level. See Figure 5-9.
Figure 5-9. Power-on Sequence of Slave Node
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S6BT112A01/S6BT112A02
5.4
Common Functions
Overtemperature Protection
5.4.1
The overtemperature protection (OTP) monitors the die temperature. If the junction temperature exceeds the shutdown junction
temperature, TSD_H, the thermal protection circuit disables the output driver.
The driver is enabled again when the junction temperature falls below TSD_L and theTXD pin is toggled. (see Table 5-10 and
Figure 5-10).
WP_ThermalShutdown
5.4.2
The WP_ThermalShutdown state detects the "shutdown temperature" during the WakeupPulseOutput mode. See Table 5-11. The
overtemperature protection is inactive during the Sleep mode.
Table 5-10. Input Signal Change after Recovery from Thermal Shutdown
Master/Slave
Pin
Master
TXD
Required
Toggle of Input Signal
Slave
TXD
Required
Table 5-11. State Under Thermal Shutdown
Master/Slave
Pin
TXD
NSLP
Master
Description
Normal function
High: Normal mode / Low: Sleep mode (Thermal protection inactive)
CLK(input)
Normal function
RXD
Normal function
BUS
High impedance
TXD
Normal function
NSLP
Slave
High: Normal mode / Low: Sleep mode (Thermal protection inactive)
CLK
Normal function
RXD
Normal function
BUS
High impedance
Figure 5-10. Sequence of Thermal Shutdown
Detect
over-temperature
Release
over-temperature detection
temperature
SELMS
NSLP
CLK(in)
TXD
Low
High
BUS
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Page 15 of 37
S6BT112A01/S6BT112A02
Low-voltage Reset
5.4.3
The low-voltage reset state denotes detecting the low voltage of the BAT pin. See Figure 5-11, Table 5-12, and Table 5-13.This device
has an integrated power-on reset and low-voltage detection at the supply BAT.
If the supply voltage, VBAT, is dropping below the power-on reset level (that is, VBAT VPOR_H, then transceiver changes to the Standby
mode (the NSLP pin is high level) or Sleep mode (the NSLP pin is low level).
After releasing LowVoltageRest mode, transceiver starts the Power-on sequence.
Table 5-12. Input Signal Change after Recovery from Low Voltage Reset
Toggle of Input
Master/Slave
Pin
Signal
Required
Master
TXD
Slave
TXD
Required
Table 5-13. State Under Low Voltage Reset
Master/Slave
Master
Slave
Pin
Description
SELMS
Reset
TXD
Reset
NSLP
Reset
CLK
Reset(High impedance)
RXD
High impedance
BUS
High impedance
SELMS
Reset
TXD
Reset
NSLP
Reset
CLK
Reset(High impedance)
RXD
High impedance
BUS
High impedance
Figure 5-11. Low-Voltage Detection
Detect
Low voltage reset
Release
low voltage reset
BAT
SELMS
NSLP
CLK(in)
TXD
Low
High
BUS
33 periods
After releasing the low-voltage reset mode, the logical value high is output to the BUS pin after a clock input of 33 periods. The
TXD data is valid from the falling edge on the TXD pin.
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Page 16 of 37
S6BT112A01/S6BT112A02
Overcurrent Protection
5.4.4
The current in the transmitter output driver is limited to protect the transmitter against short-circuit to BAT or GND pins. See
Table 5-14.
Table 5-14. State Under Overcurrent Protection
Master/Slave
Pin
TXD
Master
Slave
5.4.5
Description
Normal function
NSLP
Normal function
CLK
Normal function
RXD
Normal function
BUS
Output current limited by IBUS_LIM
TXD
Normal function
NSLP
Normal function
CLK
Normal function
RXD
Normal function
BUS
Output current limited by IBUS_LIM
Secondary Clock Master
The node that detects the wakeup event transmits the wakeup pulse on to the CXPI BUS. If the primary clock master cannot transmit
the clock to the CXPI BUS due to failure, the wakeup pulse is retransmitted. If the clock is not transmitted to the CXPI BUS, each
node detects the CXPI BUS error.
The secondary clock master may transmit the clock to the CXPI BUS instead of the primary clock master if it detects that the clock
does not exist, for a certain period after it transitions from the Sleep mode.
■Operation sequence from master to slave
After setting the TXD input pin to high level and the CLK pin is high-impedance, set the transceiver to sleep mode by setting the
NSLP pin to low level. After confirming no data receiving (the RXD pin is high level), set the SELMS pin from low level to high level.
Table 5-15 shows the pin states just before the SELMS pin input signal change. See Figure 5-12 for an application example secondary
clock master, and see Figure 5-13 for transition sequence from master to slave.
Table 5-15. Pin State Table (from Master to Slave)
Pin
Pin State
Description
TXD
High
No data transmitting
CLK
High impedance
High level with external pull-up resistor.
NSLP
Low
Sleep mode
SELMS
Low to High
-
RXD
High
No data receiving
BUS
High
No wakeup signal receiving preferred
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S6BT112A01/S6BT112A02
Figure 5-12. Application Example Secondary Clock Master
S6BT112A AS SLAVE (SECONDARY CLOCK MASTER )
12V Battery
CXPI BUS LINE
BAT
S6BT112A: CXPI Transceiver IC
Regulator
RC
OSC
5V
VCC
SELMS
MCU
CLK
TXD
RXD
NSLP
UART
LDO Regulator
Thermal Shutdown
Low Voltage Detection
Over Current Protection
CXPI
Control
Logic
VSS
BUS
CXPI
PHY
GND
Figure 5-13. Transition Sequence from Master to Slave
SELMS
TXD High
CLK Hi-Z
NSLP Low
Slave
TXD
CLK
T SLP_WT
NSLP
BUS
RXD
RXD High
■Operation sequence from slave to master
After setting the TXD pin to high level and the CLK pin is high level, set the transceiver to the Sleep mode by setting NSLP tpin to
low level. After confirming no data receiving (the CLK pin is high level), set the SELMS pin from high level to low level.
See Table 5-16 and Figure 5-14.
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S6BT112A01/S6BT112A02
Table 5-16. Pin State Table (from Slave to Master)
Pin
TXD
Pin State
High
Description
No data transmitting
CLK
High impedance
No wakeup signal receiving
NSLP
Low
Sleep mode
SELMS
High to Low
-
RXD
High
-
BUS
High
No wakeup signal receiving preferred
Note: The pin states just before the SELMS input signal change.
Figure 5-14. Transition Sequence from Slave to Master
SELMS
Master
NSLP Low
TXD High
TXD
CLK High
CLK
NSLP
Master node stops transmitting
BUS
RXD
5.4.6
Arbitration
Transceivers arbitrate bit-by-bit. Arbitration in bytes is done in the MCU.
In the Normal mode, each node always compares the received bit from the CXPI BUS with the transmitted bit to the CXPI BUS.
When the value of the bit is corresponding, the node may continuously transmit to the CXPI BUS. When the value of the bit is not
corresponding, the loss of arbitration is detected, and the transmission of the bit after that shall discontinue. If the transmitting node
detects the arbitration loss, it behaves as the receiving node. The data of each bit transmitted on the CXPI BUS performs arbitration
from the start by the bit. Moreover, arbitration is targeted at the entire field of the frame. When two or more nodes begin transmitting
at the same time, by arbitration only the node that transmits the highest priority frame can complete the transmission.
The MCU compares between the transmitted data (TXD) and received data (RXD). If the data difference is detected, MCU has to
stop data transmission until finding IFS.
5.4.7
TXD Toggle
The TXD toggle is an operation in which the TXD pin is first raised to high level and then lowered to low level.
The toggle function of the transceiver initiates a TXD dominant check after the transition to the Normal mode. If the TXD pin is
forced permanently low level by a hardware and/or software application failure, transceiver doesn't recognize the TXD pin as low
level. See Figure 5-15 and Figure 5-16.
As a result, even if the TXD pin is stuck to low level, the BUS pin does not continue to output a logical value of 0 in normal mode.
Therefore, even if the TXD pin is fixed to low level, it does not interfere with the communication of other devices on the BUS.
If the TXD pin is low level, the transmitter output driver remains disabled and is only enabled once the TXD pin goes high level.
A TXD toggle is required in the following cases.
Data
Data
First
First
transmission after recovery from low-voltage reset. See Figure 5-17.
transmission after recovery from thermal shutdown.
TXD data transmission in the Normal mode.
wake-up pulse transmission in sleep mode.
Document Number: 002-10203 Rev. *H
Page 19 of 37
S6BT112A01/S6BT112A02
Figure 5-15. Normal Transmission Sequence of Master
Figure 5-16. TXD Toggle of Master after Transition to Normal mode
Figure 5-17. Slave TXD Toggle after Recovery from Low voltage State
5.4.8
Short-circuit from the TXD pin to ground.(failure detect)
In Normal mode, If the low level input to TXD pin continues for over 10Tbit, the low level TXD input after the 10th Tbit will not be
output to the bus.
Document Number: 002-10203 Rev. *H
Page 20 of 37
S6BT112A01/S6BT112A02
6. Absolute Maximum Ratings
Semiconductor devices may be permanently damaged by an application of stress (including, without limitation, voltage, current or
temperature) in excess of the absolute maximum ratings. Do not exceed any of these ratings.
Parameters
Power supply voltage
Symbol
Conditions
Min
Max
Unit
VBAT
BAT pin
-0.3
40
V
VNSLP
NSLP pin
-0.3
6.9
V
VSELMS
SELMS pin
-0.3
18
V
VCLK
CLK pin
-0.3
6.9
V
VTXD
TXD pin
-0.3
6.9
V
VRXD
RXD pin
-0.3
6.9
V
VCLK
CLK pin
-0.3
6.9
V
VBUS
BUS pin
-40
40
V
VESDBUS
BUS pin
-8
8
kV
VESDBAT
BAT pin
-8
8
kV
-2
2
kV
Input voltage
Output voltage
BUS pin voltage
Rating
BUS pin ESD
(1.5 kΩ, 100 pF)
BAT pin ESD
(1.5 kΩ, 100 pF)
NSLP pin
SELMS pin
ESD
VESD
CLK pin
(1.5 kΩ, 100 pF)
TXD pin
RXD pin
Storage temperature
TSTG
-
-55
150
°C
TJMAX
-
-40
150
°C
Maximum
junction temperature
Document Number: 002-10203 Rev. *H
Page 21 of 37
S6BT112A01/S6BT112A02
7. Recommended Operating Conditions
Table 7-1. Recommended Condition
Parameters
Power supply voltage
Operating ambient temperature
Min
Value
Typ
Max
5.3
-
18
V
－40
+25
+125
°C
BUS pin (Master node：VSELMS 0V)
900
1000
1100
Ω
Symbol
VBAT
Conditions
BAT pin [1]
TA
-
Unit
BUS pin pull-up resistance
RMASTER
RXD pin pull-up resistance
RRXD
RXD pin
2.4
10
-
kΩ
CLK pin pull-up resistance
RCLK
CLK pin (VSELMS 5V)
2.4
10
-
kΩ
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
WARNING:
1.
The recommended operating conditions are required to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device operates under these conditions.
2.
Any use of semiconductor devices will be under their recommended operating condition.
3.
Operation under any conditions other than these conditions may adversely affect the reliability of the device and could result in
device failure.
4.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-10203 Rev. *H
Page 22 of 37
S6BT112A01/S6BT112A02
8. Electrical Characteristics
Table 8-1. DC Characteristics
VBAT
5.3 V~27 V[1], TA
-40~125 °C; All voltages are referenced to Pin 8 (GND); Positive currents flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin
Name
Conditions
Min
Typ
Max
Unit
-
1.4
2.9
mA
-
2.0
4.0
mA
-
6
10
µA
-
16
-
µA
-
-
50
µA
-
-
60
µA
Normal mode
VTXD 5 V
fCLK 20 kHz, Duty 50%
Normal mode
VTXD 0 V
fCLK 20 kHz, Duty 50%
Sleep mode
VBAT 12 V
VTXD 5 V
VSELMS 5 V
VBUS VBAT
TA 25 °C
Sleep mode
Power supply current
IBAT
BAT
VBAT 12 V
VTXD 5 V
VSELMS 0 V
VBUS
VBAT
TA 25 °C
Sleep mode
VBAT 12 V
VTXD 5 V
VSELMS 5 V
VBUS
VBAT
Sleep mode
VBAT 12 V
VTXD 5 V
VSELMS 0 V
VBUS
VBAT
BUS pin pull-up resistance
RBUSpu
BUS
-
20
30
47
kΩ
BUS short circuit current
IBUS_LIM
BUS
VBUS 18 V
40
-
200
mA
Document Number: 002-10203 Rev. *H
Page 23 of 37
S6BT112A01/S6BT112A02
Parameters
Symbol
Pin
Name
Conditions
Min
Typ
Max
Unit
-
-
20
µA
-1
-
-
mA
VBUS 18 V
BUS input leak current (HIGH)
IBUS_PAS_rec
BUS
VBAT 5.3 V
VTXD 5 V
TA 25 °C
VBUS 0 V
BUS input leak current (LOW)
IBUS_PAS_dom
BUS
VBAT 12 V
VTXD 5 V
loss of ground BUS leak current
IBUS_NO_GND
BUS
VBAT GND 18 V
VBUS 0 V
-1
-
1
mA
loss of battery BUS leak current
IBUS_NO_BAT
BUS
VBAT 0 V
VBUS 18 V
TA 25 °C
-
-
30
µA
VBUSDR
BUS
VBAT 13.5 V
IBUSsource -100 µA
2.4
-
5.7
V
BUS
VTXD 0 V
VBAT 7 V
BUS pull-up
resistance 500 Ω
-
-
1.4
V
VO_dom
BUS
VTXD 0 V
VBAT 18 V
BUS pull-up
resistance 500 Ω
-
-
2
V
Receiver low level threshold voltage
VBUSdom
BUS
VBAT 12V, TA 25 °C
-
-
0.423
VBAT
V
Receiver high level threshold voltage
VBUSrec
BUS
VBAT 12V, TA 25 °C
0.556
VBAT
-
-
V
VHYS
BUS
VBAT 12V, TA 25°C
-
-
0.133
VBAT
V
Low level power-on reset threshold voltage
VPOR_L
BAT
-
3.1
3.8
4.7
V
High level power-on reset threshold voltage
VPOR_H
BAT
-
3.3
4.1
4.9
V
VPOR_HYS
BAT
-
0.2
0.3
0.5
V
TSD_H
-
[2]
156
165
174
°C
TSD_L
-
[2]
151
159
168
°C
BUS drop voltage
VO_dom
BUS low level output voltage
Receiver hysteresis voltage
power-on reset hysteresis voltage
Temperature shutdown
threshold
Temperature shutdown release threshold
Notes:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
[2]: Guaranteed by design.
Document Number: 002-10203 Rev. *H
Page 24 of 37
S6BT112A01/S6BT112A02
Table 8-2. DC Characteristics CLK Pin
(If SELMS
VBAT
5 V, this pin operates as Open Drain Output Pin. If SELMS
5.3 V~27 V[1], TA
0 V, this pin operates as an input pin).
-40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
High level input voltage
VIH_CLK
CLK
VSELMS
Low level input voltage
VIL_CLK
CLK
Hysteresis range of input voltage
VHYS_CLK
CLK
Low level output voltage
VOL_CLK
CLK
IOL_CLK
Low level current
Conditions
Min
Typ
Max
Unit
0V
2
-
6
V
VSELMS
0V
-0.3
-
0.8
V
VSELMS
0V
0.03
-
0.5
V
-
-
0.6
V
1.3
3
-
mA
-3
-
3
µA
-3
-
3
µA
ICLK
CLK
2.2 mA
VSELMS
5V
VSELMS
5 V,
VCLK
IILH_CLK
High level leak current
VSELMS
CLK
VCLK
IILL_CLK
Low level leak current
VSELMS
CLK
VCLK
0.4 V
5V
5V
5V
0V
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
Table 8-3. DC Characteristics NSLP Pin
VBAT
5.3 V~27 V[1], TA
-40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
High level input voltage
VIH_NSLP
NSLP
Low level input voltage
VIL_NSLP
Hysteresis range of input voltage
VHYS_NSLP
Internal pull-down resistance
RPD_NSLP
Low level leak current
IILL_NSLP
NSLP
NSLP
NSLP
NSLP
Conditions
Min
Typ
Max
Unit
-
2
-
6
V
-
-0.3
-
0.8
V
-
0.03
-
0.5
V
VNSLP
5V
100
250
650
kΩ
VNSLP
0V
-3
-
3
µA
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
Document Number: 002-10203 Rev. *H
Page 25 of 37
S6BT112A01/S6BT112A02
Table 8-4. TXD Pin
VBAT
5.3 V~27 V[1], TA
-40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
High level input voltage
VIH_TXD
TXD
-
2
-
6
V
Low level input voltage
VIL_TXD
TXD
-
-0.3
-
0.8
V
Hysteresis range of input voltage
VHYS_TXD
TXD
-
0.03
-
0.5
V
Internal pull-up resistance
RPU_TXD
TXD
VTXD
0V
50
125
325
kΩ
High level leak current
IILH_TXD
TXD
VTXD
5V
-3
-
3
µA
Note:
[1]: (18V < VBAT ≤ 27V) less than 2 minutes.
Table 8-5. SELMS Pin
VBAT
5.3 V~27 V[1], TA
-40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
High level input voltage
VIH_SELMS
SELMS
Low level input voltage
VIL_SELMS
Hysteresis range of input voltage
VHYS_SELMS
Internal pull-up resistance
RPU_SELMS
High level leak current
IILH_SELMS
SELMS
SELMS
SELMS
SELMS
Conditions
Min
Typ
Max
Unit
-
2
-
6
V
-
-0.3
-
0.8
V
-
0.03
-
0.5
V
VSELMS
0V
200
500
1300
kΩ
VSELMS
5V
-3
-
3
µA
Note:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
Document Number: 002-10203 Rev. *H
Page 26 of 37
S6BT112A01/S6BT112A02
Table 8-6. RXD Pin (Open Drain Output)
VBAT
5.3 V~27 V[1], TA
-40~125 °C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless
otherwise specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
Low level output voltage
VOL_RXD
RXD
IRXD
2.2 mA
-
-
0.6
V
Low level current
IOL_RXD
RXD
RXD
0.4 V
1.3
3
-
mA
High level leak current
IOLH_RXD
RXD
RXD
5V
-3
-
3
µA
Low level leak current
IOLL_RXD
RXD
RXD
0V
-3
-
3
µA
Note:
[1]: (18 V < VBAT≦ 27 V) less than 2 minutes.
Table 8-7. AC Characteristics
VBAT
5.3 V~27 V[1], TA
Parameters
Bitrate (see Figure
8-1)
-40~125 °C BUS Load 1 kΩ /1 nF; unless otherwise specified.
Symbol
Pin Name
Conditions
TBUAD
BUS
VTH(BUS) [3]
TMODE_CHG
NSLP
VTH(5 V)[4]
NSLP
VTH(5 V) [4]
NSLP
-
Min
Typ
Max
Unit
2.4
-
20
kbps
50%
-
-
1
ms
50%
100
-
-
µs
1
-
-
ms
-
-
66
µs
-
-
0.9
Tbit[5]
0.5VBAT
Mode transition time
(Sleep to Normal or
Normal to Sleep.) (see
Figure 8-2)
NSLP wait time (see
Figure 8-3)
TSLP_WT
Minimum sleep time
(see Figure 8-4)
TSLP_MN
CLK
VBUT
Driver boot time under
sleep mode. [2] (see
Figure 8-5)
VNSLP
TTXD_BT
TXD
VSELMS
7V~27V
0V
5V
VTH(5 V)[4] 50%
VTH(BUS)[3] 0.3VBAT
VNSLP
CLK transmission
delay time (see Figure
8-6)
VSELMS
TCLK_PD
CLK
5V
0V
CLK input clock
VTXD 5 V
VTH(5 V)[4] 50%
VTH(BUS)[3] 0.3VBAT
Document Number: 002-10203 Rev. *H
Page 27 of 37
S6BT112A01/S6BT112A02
Parameters
Symbol
Pin Name
Conditions
VNSLP
Time of Low level of
logic value '1' (see
Figure 8-7)
BUS
CLK input clock
Unit
-
-
0.39Tbit
+0.6τ
-
0.11
-
-
Tbit
-
-
-
-
-
-
0.06
-
-
Tbit
-
-
1.0
Tbit
-
-
2.0
Tbit
30
-
70
%
14
-
50
%
30
-
150
µs
VTXD 5 V
VNSLP
5V
VSELMS
Ttx_1_lo_dom
BUS
0.7VBAT
0V
CLK input clock
VTXD 5 V
VTH(BUS)[3]
VNSLP
Time of Low level of
logic value '0' (see
Figure 8-7)
Ttx_0_lo_rec
Time of Low level of
logic value '0' (see
Figure 8-7)
Ttx_0_lo_dom
High level time at
receiving node. (see
Figure 8-7)
Max
0V
VTH(BUS)[3]
Time of Low level of
logic value '1' (see
Figure 8-7)
Typ
5V
VSELMS
Ttx_1_lo_rec
Min
BUS
0.3 VBAT
5V
VTXD
Ttx_1_lo_rec
0V
+0.06Tbit
VTH(BUS) [3]
VNSLP
BUS
0.7 VBAT
5V
Ttx_1_lo_dom
VTXD 0 V
+0.06Tbit
VTH(BUS) [3]
VNSLP
Ttx_0_hi
BUS
0.3 VBAT
5V
VTXD
0V
VTH(BUS)[3]
0.556
VBAT
Receiver delay time
(see Figure 8-8)
VNSLP
TRXD_PD
RXD
5V
VTH(BUS)[3]
VBUSdom
Delay time of
transmission if logic
value '0'. (see Figure
8-9)
TTXD_PD
TXD
VNSLP
Input clock duty
TICLK_DY
CLK
VSELMS
VTH(5
Output clock duty[6]
TOCLK_DY
CLK
Trx_wakeup_mast
er
Document Number: 002-10203 Rev. *H
VSELMS
50%
5V
V)[4]
VNSLP
BUS
0V
V)[4]
VSELMS
VTH(5
Wakeup pulse filter
constant(Master)[7]
(see Figure 8-10)
5V
VTH(BUS) [3] 0.3 VBAT
50%
0V
0V
VTH(BUS) [3] 42.3%
Page 28 of 37
S6BT112A01/S6BT112A02
Parameters
Wakeup pulse filter
constant(Slave) [7]
(see Figure 8-10)
Time of bus slope from
minimum (see Figure
8-7)
Symbol
Pin Name
Trx_wakeup_slave
BUS
Conditions
VNSLP
VSELMS
Ttx_1_dom_m
BUS
VSELMS
VBAT
5V
V_rec_0
BUS
VNSLP
Max
Unit
0.5
-
5
µs
-
-
0.16
Tbit
0.93
-
-
V_rec_1
42.3%
5V
0V
7V
VTH(BUS) [3]
Recessive level of
logical value ‘0’.
Typ
0V
VTH(BUS) [3]
VNSLP
Min
0.3 VBAT
5V
Notes:
[1]: (18 V < VBAT ≤ 27 V) less than 2 minutes.
RXD pin load: 20 pF.
[2]: CXPI BUS load (Figure 8-11) : 10 nF/500 Ω.
[3]: VTH(BUS)：threshold of BUS pin.
[4]: VTH(5 V)：threshold of NSLP,CLK,TXD,SELMS,RXD pins.
[5]: Tbit stands for 1bit time.(Figure 8-1)
[6]: logic '0/1' threshold clock.
[7]: Pulse widths greater than Max are output to RXD, pulse widths less than Min are excluded.
Figure 8-1. Definition of Tbit
Figure 8-2. Mode Transition Time
Document Number: 002-10203 Rev. *H
Page 29 of 37
S6BT112A01/S6BT112A02
Figure 8-3. NSLP Wait Time
Figure 8-4. Minimum Sleep Time
Figure 8-5. Driver Boot Time Under Sleep Mode
Figure 8-6. CLK Transmission Delay Time
Document Number: 002-10203 Rev. *H
Page 30 of 37
S6BT112A01/S6BT112A02
Figure 8-7. Logic Low and High CXPI BUS Waveform
Figure 8-8. Receiver Delay Time
Document Number: 002-10203 Rev. *H
Page 31 of 37
S6BT112A01/S6BT112A02
Figure 8-9. Logic Low Transmission Delay Time
Figure 8-10. Wakeup Pulse Waveform
Document Number: 002-10203 Rev. *H
Page 32 of 37
S6BT112A01/S6BT112A02
Figure 8-11. CXPI BUS Load Connection
Document Number: 002-10203 Rev. *H
Page 33 of 37
S6BT112A01/S6BT112A02
9. Ordering Information
Part Number
S6BT112A01SSBB002
Package
8-pin 150-mil SOIC Tape and Reel (SOA008)
S6BT112A02SSBB002
8-pin 150-mil SOIC Tape and Reel (SOA008)
10. Package Dimensions
Package Type
Package Code
SOP 8
SOA 008
NOTES:
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
0.89
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
0.50
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
A
-
-
1.75
A1
0.10
-
0.25
A2
1.32
-
-
b
0.31
-
0.51
b1
0.28
-
0.48
c
0.17
-
0.25
c1
0.17
-
0.23
D
4.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
L
1.27 BSC
-
0.40
L1
1.04 REF
L2
0.25 BSC
8
N
h
0.25
-
0
0°
-
8°
01
5°
-
15°
02
1. ALL DIMENSIONS ARE IN MILLIMETERS.
002-18754 **
0° REF
Document Number: 002-10203 Rev. *H
Page 34 of 37
S6BT112A01/S6BT112A02
Document History
Document Title: S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network
Document Number: 002-10203
Revision
ECN
Submission Date
**
5046456
12/11/2015
Description of Change
Initial release
New Spec.
Revised the sentence style of the cover page
Changed all section 5 for easy to understand.
*A
5208207
04/06/2016
Changed figure of application.
Changed Figure 4-1 and Figure 5-1.
Removed “Driver recovery time when over-temperature detection is released.”
Changed figure of application.
Changed Figure 4-1 Block Diagram
Changed Figure 5-12 Application example Secondary clock master
*B
5528948
11/24/2016
Added the conditions of VBUSdom/VBUSrec/ VHYS/Ttx_1_dom_m.
Removed the prameter of Receiver center level voltage (V BUS_CNT).
Changed Figure 8-11 CXPI BUS Load Connection
Changed Ordering Information.
Changed Package Dimensions.
Updated Introduction.
*C
5547736
12/09/2016
Updated Note [3] (Page 8).
Updated 5.2 Master Node.
Updated 5.2.2 Sleep Mode.
*D
5757034
06/20/2017
*E
6397891
12/04/2018
Changed figure of 1. Applications
Changed Figure 5-12 Application example Secondary Clock Master
Changed SOA 008 figure in Package Demensions
Added recommendation when stopping clock (Page 9).
Corrected Figure 5-2, 5-3, 5-5, 5-6, 5-7, 5-10, 5-11, 5-13, 5-14
Changed Table 5-5 to Table 5-9, 20 kbps to 19.2 kbps. Added explanation (Page 10, 13).
*F
6748976
12/23/2019
Added max. value for IBAT at Sleep mode, SELMS=5V, and TA=25 °C (Page 23).
Changed max. value of TTXD_BT to 66 (Page 27).
Changed max. value of Ttx_1_lo_rec to 0.39Tbit+0.6τ (Page 28).
Changed max. value of TRXD_PD to 1.0 (Page 28).
Changed max. value of TTXD_PD to 2.0 (Page 28).
Document Number: 002-10203 Rev. *H
Page 35 of 37
S6BT112A01/S6BT112A02
Document Title: S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network
Document Number: 002-10203
Revision
ECN
Submission Date
Description of Change
Updated Introduction.
Updated Features.
Added title of Figure 1-1 and Figure 1-2.
Changed NSLP pin description of Table 3-1.
Updated block diagram of figure 4-1.
Updated State Transition Diagram of Figure 5-1 and Notes.
*G
6906561
06/28/2020
Updated 5.2 Master Node.
Updated 5.3 Slave Node.
Updated 5.4 Common functions.
Updated style of 7 Recommended Operating Conditions.
Updated style of 8 Electrical Characteristics.
Added conditons of IOL_CLK ; VCLK = 0.4 V.
Added conditons of IILH_CLK ; VCLK = 5 V.
Added conditons of IILL_CLK ; VCLK = 0 V.
*H
7097866
03/03/2021
Document Number: 002-10203 Rev. *H
Added ISO compliance in the Features.
Updated the Short-circuit from the TXD pin to ground.(failure detect) in 5.4.8.
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S6BT112A01/S6BT112A02
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Document Number: 002-10203 Rev. *H
March 3, 2021
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