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S6E1C31B0AGN20000

S6E1C31B0AGN20000

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    WFQFN32

  • 描述:

    IC MCU 32BIT 64KB FLASH 32QFN

  • 数据手册
  • 价格&库存
S6E1C31B0AGN20000 数据手册
The following document contains information on Cypress products. The document has the ordering part numbering with the prefix “S”. Cypress will offer these products to new and existing customers with the updated ordering part number (updated last digit). How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. S6E1C Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller The FM0+ family of Flexible Microcontrollers is the industry’s most energy-efficient 32-bit ARM® Cortex®-M0+ based MCUs. This family of MCUs is designed for ultra-low-power and cost-sensitive applications such as white goods, sensors, meters, HMI systems, power tools and Internet of Things (IoT) battery-powered or wearable devices. This family of ultra-low-power MCUs features an industry-leading 35 µA/CoreMark® score and 40µA/MHz Active Power consumption. The S6E1C Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I2C, I2S, Smart Card, and USB). The products which are described in this data sheet are placed into TYPE3-M0+ product categories in "FM0+ Family Peripheral Manual". Features Ultra Low Power MCU Subsystem Analog Subsystem  40 MHz ARM Cortex-M0+ CPU with 1.65 V to 3.6 V  1x 12-bit, 1-Msps ADCs with an 8-channel multiplexer input operating voltage  1% high precision internal oscillator  Maximum operating frequency: 40.8 MHz  Nested Vectored Interrupt Controller (NVIC): 1 non-maskable interrupt (NMI) and 24 peripheral interrupt with 4 selectable interrupt priority levels  24-bit System timer (Sys Tick): System timer for OS task management  Up to 128 KB Flash, 16 KB SRAM Package Options  32-/48-/64-pin LQFP  32-/48-/64-pin QFN  30-pin WLCSP Low-Power Consumption Modes  Descriptor System Transfer Controller (DSTC)  Industry's most efficient 35 µA/CoreMark Score  This series has six low-power consumption modes:  Ultra-low-power consumption: Active – 40 µA/MHz and Standby – 0.6 µA  Fast wake-up from standby mode (execute from Flash): 20 µs (Typ)       Digital Subsystem Sleep Timer RTC Stop Deep standby RTC (selectable between keeping the value of RAM and not) Deep standby Stop (selectable between keeping the value of RAM and not)  Up to 8x Base Timers  1x Dual Timer, 1x Watch Counter  Up to 6x Multi-Function Serial (MFS) interfaces configurable as SPI, UART, I2C  Up to 1x USB, up to 2x I2S, up to 2x HDMI-CEC, up to 1x Smart Card interfaces Cypress Semiconductor Corporation Document Number: 002-00233 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 13, 2017 S6E1C Series Ecosystem for Cypress FM0+ MCUs Cypress provides a wealth of data at www.cypress.com to help you to select the right MCU for your design, and to help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for FM0+ MCUs:  Overview: Product Portfolio, Product Roadmap  Product Selectors: FM0+ MCUs  AN205411 – FM0+ IEC60730 Class B Self-Test Library : This document covers how to use and implement the library functions provided. It will first show the requirement of IEC60730 Class B, and then explain how it can be implemented. At last an example is given to show how to integrate test functions into a real system.  AN202487 - Differences Among FM0+, FM3, and FM4 32-Bit Microcontrollers: Highlights the peripheral differences in Cypress’s FM family MCUs. It provides dedicated sections for each peripheral and contains lists, tables, and descriptions of peripheral feature and register differences.  AN204438 - How to Setup Flash Security for FM0+, FM3 and FM4 Families: This application note describes how to setup the Flash Security for FM0+, FM3, and FM4 devices  Application notes: Cypress offers a large number of FM0+ application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with FM0+ family of MCUs are:   AN210985 – FM0+ Getting Started with FM0+ Development: AN210985 introduces you to the FM0+ family of 32-bit general-purpose microcontrollers. The FM0+ family is based on the ARM® Cortex®-M0+ processor core, ideal for ultra-low-power designs. This note provides an overview of hardware features and capabilities, firmware development, and the multitude of technical resources available to you. This application note uses the FM0+ S6E1B8-Series Starter Kit as an example. AN203277 - FM 32-Bit Microcontroller Family Hardware Design Considerations: This application note reviews several topics for designing a hardware system around FM0+, FM3, and FM4 family MCUs. Subjects include power system, reset, crystal, and other pin connections, and programming and debugging interfaces.  Development kits:  FM0-V48-S6E1A1 ARM® Cortex®-M0+ FM0+ MCU Evaluation Board  FM0-64L-S6E1C3 - ARM® Cortex®-M0+ MCU Starter Kit with USB and Digital Audio Interface  Peripheral Manuals Document Number: 002-00233 Rev. *D Page 2 of 109 S6E1C Series Table of Contents Features............................................................................... 1 1. Block Diagram ............................................................... 4 2. Product Lineup .............................................................. 5 2.1 Package Dependent Features ................................... 6 2.2 Packages................................................................... 6 3. Product Features in Detail ............................................ 7 4. Pin Assignment ........................................................... 10 5. List of Pin Functions................................................... 17 6. I/O Circuit Type............................................................ 26 7. Handling Precautions ................................................. 31 7.1 Precautions for Product Design ............................... 31 7.2 Precautions for Package Mounting .......................... 32 7.3 Precautions for Use Environment ............................ 34 8. Handling Devices ........................................................ 35 9. Memory Map ................................................................ 38 10. Pin Status in Each CPU State .................................... 41 11. Electrical Characteristics ........................................... 44 11.1 Absolute Maximum Ratings ..................................... 44 11.2 Recommended Operating Conditions...................... 45 11.3 DC Characteristics................................................... 46 11.3.1 Current Rating .......................................................... 46 11.3.2 Pin Characteristics ................................................... 51 11.4 AC Characteristics ................................................... 52 11.4.1 Main Clock Input Characteristics .............................. 52 11.4.2 Sub Clock Input Characteristics ............................... 53 11.4.3 Built-in CR Oscillation Characteristics ...................... 54 11.4.4 Operating Conditions of Main PLL (In the Case of Using the Main Clock as the Input Clock of the PLL) 55 11.4.5 Operating Conditions of Main PLL (In the Case of Using the Built-in High-Speed CR Clock as the Input Clock of the Main PLL) ............................................. 55 11.4.6 Reset Input Characteristics ...................................... 56 11.4.7 Power-on Reset Timing............................................ 56 11.4.8 Base Timer Input Timing .......................................... 57 11.4.9 CSIO/SPI/UART Timing ........................................... 58 11.4.10 External Input Timing ............................................ 75 11.4.11 I2C Timing ............................................................. 76 11.4.12 I2S Timing (MFS-I2S Timing) ................................ 77 11.4.13 Smart Card Interface Characteristics .................... 79 11.4.14 SW-DP Timing ...................................................... 80 11.5 12-bit A/D Converter ................................................ 81 11.6 USB Characteristics ................................................ 84 11.7 Low-Voltage Detection Characteristics .................... 89 11.7.1 Low-Voltage Detection Reset ................................... 89 11.7.2 Low-Voltage Detection Interrupt ............................... 90 11.8 Flash Memory Write/Erase Characteristics ............. 91 11.9 Return Time from Low-Power Consumption Mode .. 92 11.9.1 Return Factor: Interrupt/WKUP ................................ 92 Document Number: 002-00233 Rev. *D 11.9.2 Return Factor: Reset ................................................ 94 12. Ordering Information................................................... 96 13. Acronyms ..................................................................... 97 14. Package Dimensions................................................... 99 15. Errata .......................................................................... 106 15.1 Part Numbers Affected .......................................... 106 15.2 Qualification Status ................................................ 106 15.3 Errata Summary..................................................... 106 Document History ........................................................... 108 Sales, Solutions, and Legal Information ....................... 109 Page 3 of 109 S6E1C Series 1. Block Diagram SWCLK SWDIO SW-DP Fast GPIO Cortex-M0+Core MTB On-Chip SRAM 12/16Kbyte Flash I/F On-Chip FLASH 64/128Kbyte Bit Band Wrapper NVIC System ROM table WatchDog Timer (Software) INITX Clock Reset Generator Multi-layer AHB AHB-APB Bridge APB0 Security Dual-Timer WatchDog Timer (Hardware) DSTC 64ch. WatchDog Timer (CVS) Main Osc Sub Osc AHB-AHB Bridge Source Clock X0 X1 X0A X1A PLL CR 8MHz CR 100KHz CROUT AVRH AVRL USB2.0 (Host/Device) PHY UDP0, UDM0 UHCONX0 Power-On LVD Ctrl 12-bit A/D Converter ANxx ADTG Unit 0 TIOAx Base Timer 16-bit 8 ch. 32-bit 4 ch. LVD Regulator C IRQ-Monitor Watch Counter CRC Accelarator NMIX MODE-Ctrl MD0, MD1 Low-Speed CR Peripheral Clock Gating Multi-function Serial I/F 6 ch. (Max) Deep Standby Ctrl Document Number: 002-00233 Rev. *D INTx External Interrupt Controller 12 pin(Max) + NMI GPIO WKUPx RTCCO Real-Time Clock AHB-APB Bridge : APB1 TIOBx Smart Card I/F PIN-Function-Ctrl P0x, P1x, : PEx SCKx SINx SOTx SCSx MI2SCKx MI2SDIx MI2SDOx MI2SMCKx MI2SWSx IC1_CLKx IC1_VCCx IC1_VPENx IC1_CINx IC1_DATAx Page 4 of 109 S6E1C Series 2. Product Lineup Memory Size Product name S6E1C11 S6E1C31 S6E1C12 S6E1C32 On-chip Flash memory 64 Kbytes 128 Kbytes On-chip SRAM 12 Kbytes 16 Kbytes S6E1C1 S6E1C3 Function Function Name Cortex-M0+ CPU Frequency 40.8 MHz Power supply voltage range USB2.0 (Device/Host) DSTC 1.65 V to 3.6 V - 1 unit 64 ch. Base Timer (PWC/Reload timer/PWM/PPG) 8 ch. (Max) Dual Timer 1 unit Real-time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1 ch. (SW) + 1 ch. (HW) CSV (Clock Supervisor) Yes LVD (Low-voltage Detection) 2 ch. High-speed 8 MHz (Typ) Low-speed 100 kHz (Typ) Built-in CR Debug Function Unique ID SW-DP Yes Note: − Because of package pin limitations, not all functions within the device can be brought out to external pins. You must carefully work out the pin allocation needed for your design. You must use the port relocate function of the I/O port according to your function use. − See "11. Electrical Characteristics 11.4 AC Characteristics 11.4.3 Built-in CR Oscillation Characteristics" for accuracy of built-in CR. Document Number: 002-00233 Rev. *D Page 5 of 109 S6E1C Series 2.1 Package Dependent Features Package Feature Pin count Multi-function Serial Interface (UART/CSIO/I2C/I2S) 30 WLCSP 32 LQFP 32 QFN 48 LQFP 48 QFN 64 LQFP 64 QFN 30 32 48 64 4 ch. (Max) 4 ch. (Max) 6 ch. (Max) 6 ch. (Max) Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO Ch. 6 with FIFO Ch. 6 with FIFO Ch.4/6/7 with FIFO Ch.4/6/7 with FIFO I2S: No I2S: 1 ch (Max) Ch. 6 with FIFO I2S: 2 ch (Max) Ch. 4/6 with FIFO External Interrupt 7 pins (Max), NMI x 1 9 pins (Max), NMI x 1 12 pins (Max), NMI x 1 I/O port 24 pins (Max) 38 pins (Max) 54 pins (Max) 12-bit A/D converter 6 ch. (1 unit) 8 ch. (1 unit) 8 ch. (1 unit) Smart Card Interface No HDMI-CEC/ Remote Control Receiver 2.2 1 ch (Max) 1 ch.(Max) Ch.1 2 ch (Max) Ch.0/1 Packages Package Suffix Package B0A C0A D0A LQFP: LQB032 (0.80 mm pitch)  - - QFN: WNU032 (0.50 mm pitch)  - - WLCSP: U4M030 (0.40 mm pitch)  LQFP: LQA048 (0.50 mm pitch) -  - QFN: WNY048 (0.50 mm pitch) -  - LQFP: LQD064 (0.50 mm pitch) - -  QFN: WNS064 (0.50 mm pitch) : Available - -  Note: − See "14. Package Dimensions" for detailed information on each package. Document Number: 002-00233 Rev. *D Page 6 of 109 S6E1C Series 3. Product Features in Detail Multi-Function Serial Interface (Max 6channels) 32-bit ARM Cortex-M0+ Core  3 channels with 64Byte FIFO (Ch.4, 6 and 7), 3 channels  Maximum operating frequency: 40.8 MHz  Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels  24-bit System timer (Sys Tick): System timer for OS task management without FIFO (Ch.0, 1 and 3)  The operation mode of each channel can be selected from one of the following. UART  CSIO (CSIO is known to many customers as SPI)  I2 C   UART  Bit Band Operation  Compatible with Cortex-M3 bit band operation.   On-Chip Memory   Flash memory    Up to 128 Kbytes Read cycle: 0 wait-cycle Security function for code protection  SRAM The on-chip SRAM of this series has one independent SRAM.  Up to 16 Kbytes  4Kbytes: can retain value in Deep standby Mode USB Interface USB interface is composed of Device and Host With Main PLL, USB clock can be generated by multiplication of Main clock.  USB Device USB 2.0 Full-Speed supported  Max 6 EndPoint supported • EndPoint 0 is control transfer • EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer • EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer • EndPoint 1 to 5 comprise Double Buffer • The size of each EndPoint is according to the follows • EndPoint 0, 2 to 5 : 64 bytes • EndPoint 1 : 256 bytes   USB host       USB 2.0 Full/Low-Speed supported Bulk-transfer, Interrupt-transfer and Isochronous-transfer support USB Device connected/disconnected automatically detect IN/OUT token handshake packet automatically Max 256-byte packet-length supported Wake-up function supported Document Number: 002-00233 Rev. *D  Full duplex double buffer Parity can be enabled or disabled. Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4) * : S6E1C32B0A/S6E1C31B0A and S6E1C32C0A/S6E1C31C0A do not support Hardware Flow control. Various error detection functions (parity errors, framing errors, and overrun errors)  CSIO (also known as SPI)      Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function Serial chip select function (ch1 and ch6 only) Data length: 5 to 16 bits  I2 C  Standard-mode (Max: 100 kbps) supported / Fast-mode (Max 400 kbps) supported.  I2S (MFS-I2S) Using CSIO (Max 2 ch: ch.4, ch.6) and I2S clock generator  Supports two transfer protocol • I2 S • MSB-justified  Master mode only  Descriptor System Data Transfer Controller (DSTC) (64 Channels)  The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor that has already been constructed on the memory, can access directly the memory / peripheral device and performs the data transfer operation.  It supports the software activation, the hardware activation, and the chain activation functions Page 7 of 109 S6E1C Series A/D Converter (Max: 8 Channels)  It can count leap years automatically.  12-bit A/D Converter Watch Counter      Successive approximation type Conversion time: 2.0 μs @ 2.7 V to 3.6 V Priority conversion available (2 levels of priority) Scan conversion mode Built-in FIFO for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4 steps) The Watch Counter wakes up the microcontroller from the low power consumption mode. The clock source can be selected from the main clock, the sub clock, the built-in high-speed CR clock or the built-in low-speed CR clock. Interval timer: up to 64 s (sub clock: 32.768 kHz) Base Timer (Max: 8 Channels) External Interrupt Controller Unit The operation mode of each channel can be selected from one of the following.  Up to 12 external interrupt input pins  16-bit PWM timer  16-bit PPG timer  16/32-bit reload timer  16/32-bit PWC timer General-Purpose I/O Port This series can use its pin as a general-purpose I/O port when it is not used for an external bus or a peripheral function. All ports can be set to fast general-purpose I/O ports or slow general-purpose I/O ports. In addition, this series has a port relocate function that can set to which I/O port a peripheral function can be allocated.  All ports are Fast GPIO which can be accessed by 1cycle  Capable of controlling the pull-up of each pin  Capable of reading pin level directly  Port relocate function  Up to 54 fast general-purpose I/O ports @64-pin package  Certain ports are 5 V tolerant. See 5.List of Pin Functions and 6.I/O Circuit Type for the corresponding pins.  Non-maskable interrupt (NMI) input pin: 1 Watchdog Timer (2 Channels) The watchdog timer generates an interrupt or a reset when the counter reaches a time-out value. This series consists of two different watchdogs, hardware watchdog and software watchdog. The hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the hardware watchdog is active in any low-power consumption modes except RTC, Stop, Deep standby RTC and Deep standby Stop mode. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage.  CCITT CRC16 and IEEE-802.3 CRC32 are supported.   HDMI-CEC/Remote Control Receiver (Up to 2 Channels)  HDMI-CEC transmitter  Dual Timer (32-/16-bit Down Counter)  The Dual Timer consists of two programmable 32-/16-bit down counters. The operation mode of each timer channel can be selected from one of the following.   Free-running mode  Periodic mode (= Reload mode)  One-shot mode Real-Time Clock The Real-time Clock counts year/month/day/hour/minute/second/day of the week from year 00 to year 99.  The RTC can generate an interrupt at a specific time (year/month/day/hour/minute) and can also generate an interrupt in a specific year, in a specific month, on a specific day, at a specific hour or at a specific minute.  It has a timer interrupt function generating an interrupt upon a specific time or at specific intervals.  It can keep counting while rewriting the time. Document Number: 002-00233 Rev. *D CCITT CRC16 Generator Polynomial: 0x1021 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7  Header block automatic transmission by judging Signal free Generating status interrupt by detecting Arbitration lost Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)  HDMI-CEC receiver   Automatic ACK reply function available Line error detection function available  Remote control receiver   4 bytes reception buffer Repeat code detection function available Smart Card Interface (Max 1 Channel)  Compliant with ISO7816-3 specification  Card Reader only/B class card only  Available protocols    Transmitter: 8E2, 8O2, 8N2 Receiver: 8E1, 8O1, 8N2, 8N1, 9N1 Inverse mode  TX/RX FIFO integrated (RX: 16-bytes, TX:16-bytes) Page 8 of 109 S6E1C Series Clock and Reset  Clocks A clock can be selected from five clock sources (two external oscillators, two built-in CR oscillator, and main PLL).  Main clock: 8 MHz to 48 MHz  Sub clock: 32.768 kHz  Built-in high-speed CR clock: 8 MHz  Built-in low-speed CR clock: 100 kHz  Main PLL clock 8MHz to 16MHz (Input), 75MHz to 150MHz (Output)  Resets       Reset request from the INITX pin Power on reset Software reset Watchdog timer reset Low-voltage detection reset Clock supervisor reset Low Power Consumption Mode This series has six low power consumption modes.  Sleep  Timer  RTC  Stop  Deep standby RTC (selectable between keeping the value of RAM and not)  Deep standby Stop (selectable between keeping the value of RAM and not) Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. Clock Supervisor (CSV) Debug The Clock Supervisor monitors the failure of external clocks with a clock generated by a built-in CR oscillator.  Serial Wire Debug Port (SW-DP)  If an external clock failure (clock stop) is detected, a reset is asserted.  If an external frequency anomaly is detected, an interrupt or  Micro Trace Buffer (MTB) Unique ID A 41-bit unique value of the device has been set. a reset is asserted. Power Supply Low-Voltage Detector (LVD) This series monitors the voltage on the VCC pin with a 2-stage mechanism. When the voltage falls below a designated voltage, the Low-voltage Detector generates an interrupt or a reset.  Wide voltage range: VCC = 1.65V to 3.6 V VCC = 3.0V to 3.6V (when USB is used)  LVD1: monitor VCC and error reporting via an interrupt  LVD2: auto-reset operation Document Number: 002-00233 Rev. *D Page 9 of 109 S6E1C Series 4. Pin Assignment LQD064 (TOP VIEW) Document Number: 002-00233 Rev. *D Page 10 of 109 S6E1C Series WNS064 (TOP VIEW) Document Number: 002-00233 Rev. *D Page 11 of 109 S6E1C Series LQA048 (TOP VIEW) Document Number: 002-00233 Rev. *D Page 12 of 109 S6E1C Series WNY048 (TOP VIEW) Document Number: 002-00233 Rev. *D Page 13 of 109 S6E1C Series LQB032 (TOP VIEW) Document Number: 002-00233 Rev. *D Page 14 of 109 S6E1C Series WNU032 (TOP VIEW) Document Number: 002-00233 Rev. *D Page 15 of 109 S6E1C Series U4M030 (BOTTOM VIEW) 1 2 3 4 5 A P50 P81 P80 P01 AVRH B P51 P05 P21 P22 P23 C P52 P03 P13 P12 P11 D P32 P0F P10 P60 X0A E P33 P31 X1 VSS X1A F MD0 X0 VCC C INITX Document Number: 002-00233 Rev. *D Page 16 of 109 S6E1C Series 5. List of Pin Functions List of Pin Numbers The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. A1 B1 C1 E2 D1 E1 F1 F2 E3 F3 F4 E4 D5 Document Number: 002-00233 Rev. *D P50 P51 P52 P53 P30 P31 P31 P32 P32 P33 P33 P34 P34 P35 P3A P3A P3B P3B P3C P3C P3D P3E P3F MD0 PE2 PE3 P40 P41 P42 P43 P4C P4C P4D P4E VCC C VSS P46 SIN3_1 SOT3_1 SCK3_1 TIOA1_2 SCS60_1 SCK6_1 SCK6_1 SOT6_1 SOT6_1 ADTG_6 ADTG_6 SCS61_1 SCS61_1 SCS62_1 TIOA0_1 TIOA0_1 TIOA1_1 TIOA1_1 TIOA2_1 TIOA2_1 TIOA3_1 TIOA4_1 TIOA5_1 X0 X1 TIOA0_0 TIOA1_0 TIOA2_0 ADTG_7 SCK7_1 SCK7_1 SOT7_1 SIN7_1 X0A INT00_0 INT01_0 INT02_0 INT07_2 TIOB0_1 INT03_2 INT04_2 MI2SCK6_1 INT04_2 TIOB2_1 INT05_2 TIOB2_1 INT05_2 SIN6_1 INT04_0 SIN6_1 INT04_0 TIOB4_1 MI2SMCK6_1 MI2SMCK6_1 TIOB5_1 INT08_1 INT03_0 RTCCO_2 INT03_0 RTCCO_2 IC1_DATA_0 IC1_RST_0 IC1_VPEN_0 IC1_VCC_0 IC1_CLK_0 INT12_1 INT13_1 TIOA3_0 TIOB3_0 INT06_2 MI2SWS6_1 MI2SDO6_1 MI2SDI6_1 SUBOUT_2 SUBOUT_2 IC1_CIN_0 Pin State Type 2 3 4 5 6 7 8 9 10 11 12 13 14 Alternate Functions I/O Circuit Type LQFP-32 QFN-32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name LQFP-48 QFN-48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 WLCSP-30 LQFP-64 QFN-64 Pin No. D D D D D H H H H H H D D D D D D D D D D D D I A A D D D D D D D D C K K K K K K K K K K K K K K K K K K K K K K K F A B K K K K K K K K C Page 17 of 109 S6E1C Series 1 Pin State Type TIOB2_2 C B H D D D D D H H D F G F F F F F F E E D E D E J J H D E K K K K K K K K K J J J J J J J J K K K K K K G G K WKUP6 E K E E K I LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP-30 Pin Name I/O Circuit Type Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 - E5 F5 D4 D3 C5 C4 C3 B5 B4 A5 B3 A4 C2 B2 A3 A2 - P47 INITX P60 P1E P1D P1C P1B P1B P1A P1A P1F P10 P11 P12 P13 P14 P15 P23 P22 VCC AVRH1 AVRL P21 P00 P01 P02 P03 P05 VCC P80 P81 VSS P61 UHCONX0 62 - - - P0B TIOB6_1 63 64 48 1 D2 P0C P0F TIOA6_1 NMIX WKUP7 WKUP0 Alternate Functions X1A TIOA2_2 RTS4_1 CTS4_1 SCK4_1 SOT4_1 SOT4_1 SIN4_1 SIN4_1 ADTG_5 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 INT15_1 MI2SMCK4_1 MI2SWS4_1 MI2SCK4_1 MI2SDO4_1 CEC1_0 INT05_1 INT05_1 CEC0_0 CEC0_0 MI2SDI4_1 SIN1_1 SOT1_1 SCK1_1 SIN0_1 SOT0_1 SCK0_0 TIOB7_1 INT02_1 WKUP1 RTCCO_1 SCS10_1 SCS11_1 TIOA7_1 SUBOUT_1 INT03_1 INT06_1 WKUP4 SWCLK WKUP5 SWDIO MD1 WKUP2 SOT0_0 SIN0_0 TIOA5_2 TIOB7_0 INT00_1 WKUP3 UDM0 UDP0 RTCCO_0 SUBOUT_0 CROUT_1 In a 32-pin package, the AVRH pin is internally connected to the VCC pin. Document Number: 002-00233 Rev. *D Page 18 of 109 S6E1C Series List of Pin Functions The number after the underscore ("_") in a function name such as XXX_1 and XXX_2 indicates one of the relocate options to route that function to a different pin. Use the Extended Port Function Register (EPFR) to disable or select the desired relocate option. Pin No. Pin Function Pin Name ADC ADTG_5 ADTG_6 ADC Base Timer 0 Base Timer 1 Function Description LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP30 39 8 8 7 E1 ADTG_7 AN00 23 40 28 18 D3 AN01 AN02 41 42 29 30 19 20 C5 C4 43 44 31 32 21 - C3 - AN05 AN06 45 46 33 34 22 B5 AN07 TIOA0_0 47 20 35 - 23 - B4 - Base timer ch.0 TIOB pin 11 5 10 5 - - Base timer ch.1 TIOA pin 21 12 11 - - 4 22 4 - - - 13 33 12 25 17 D4 AN03 AN04 TIOA0_1 TIOB0_1 TIOA1_0 TIOA1_1 A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin TIOA1_2 TIOA2_0 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 TIOA2_1 TIOA2_2 TIOB2_1 TIOB2_2 Base timer ch.2 TIOB pin 7 61 7 47 6 - D1 - TIOA3_0 TIOA3_1 Base timer ch.3 TIOA pin 23 14 - - - TIOB3_0 TIOA4_1 Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin 24 15 - - - TIOB4_1 TIOA5_1 Base timer ch.4 TIOB pin 9 16 - - - 42 - 29 - B2 - TIOA5_2 TIOB5_1 Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin 56 10 TIOA6_1 TIOB6_1 Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin 63 62 - - - TIOA7_1 TIOB7_0 Base timer ch.7 TIOA pin 46 55 34 41 22 28 B5 C2 47 53 35 40 23 27 B4 A4 55 41 28 C2 TIOB7_1 SWCLK Debugger Base timer ch.2 TIOA pin SWDIO Document Number: 002-00233 Rev. *D Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Page 19 of 109 S6E1C Series Pin No. Pin Function Pin Name INT00_0 INT00_1 INT01_0 INT02_0 INT02_1 INT03_0 INT03_1 INT03_2 External Interrupt GPIO GPIO GPIO Function Description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP30 1 56 1 42 2 29 A1 B2 2 3 2 3 3 4 B1 C1 41 11 29 10 19 - C5 - 44 5 32 5 - - INT04_0 INT04_2 External interrupt request 04 input pin 8 6 8 6 7 5 E1 E2 INT05_1 INT05_2 External interrupt request 05 input pin 38 7 27 7 6 D1 INT06_1 INT06_2 External interrupt request 06 input pin 51 26 39 18 26 - B3 - INT07_2 INT08_1 External interrupt request 07 input pin External interrupt request 08 input pin 4 10 4 - - - INT12_1 INT13_1 External interrupt request 12 input pin External interrupt request 13 input pin 20 21 - - - INT15_1 NMIX External interrupt request 15 input pin Non-Maskable Interrupt input pin 33 64 25 48 17 1 D4 D2 P00 P01 52 53 40 27 A4 P02 P03 54 55 41 28 C2 56 62 42 - 29 - B2 - P0C P0F 63 64 48 1 D2 P10 P11 40 41 28 29 18 19 D3 C5 P12 P13 42 43 30 31 20 21 C4 C3 P14 P15 44 45 32 33 - - 38 37 27 26 - - P1C P1D 36 35 - - - P1E P1F 34 39 - - - 51 47 39 35 26 23 B3 B4 46 34 22 B5 P05 P0B P1A P1B P21 P22 P23 Document Number: 002-00233 Rev. *D General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 Page 20 of 109 S6E1C Series Pin No. Pin Function GPIO GPIO GPIO GPIO GPIO GPIO Pin Name LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP30 P30 P31 5 6 5 6 5 E2 P32 P33 7 8 7 8 6 7 D1 E1 P34 P35 9 10 9 - - - 11 12 10 11 - - P3C P3D 13 14 12 - - - P3E P3F 15 16 - - - P40 P41 20 21 - - - P42 P43 22 23 - - - 30 31 22 23 14 15 D5 E5 P4C P4D 24 25 16 17 - - P4E P50 26 1 18 1 2 A1 2 3 2 3 3 4 B1 C1 4 33 4 25 17 D4 61 58 47 44 30 A3 59 18 45 14 31 9 A2 F2 19 55 15 41 10 28 E3 C2 44 32 - - 53 40 27 A4 45 33 - - 46 34 22 B5 P3A P3B P46 P47 P51 P52 P53 P60 P61 P80 P81 PE2 PE3 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) Multi-function Serial 0 Function Description SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Document Number: 002-00233 Rev. *D General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA0 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when used as a CSIO pin (operation mode 2) and as SCL0 when used as an I2C pin (operation mode 4). Page 21 of 109 S6E1C Series Pin No. Pin Function Pin Name LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP30 Multi-function serial interface ch.1 input pin 41 29 19 C5 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA1 when used as an I2C pin (operation mode 4). 42 30 20 C4 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when used as a CSIO pin (operation mode 2) and as SCL1 when used as an I2C pin (operation mode 4). 43 31 21 C3 SCS10_1 Multi-function serial interface ch.1 serial chip select 0 input/output pin. 44 32 - - 45 33 - - 1 1 2 A1 2 2 3 B1 3 3 4 C1 38 27 - - 37 26 - - 36 - - - 35 - - - 34 - - - SIN1_1 Multi-function Serial 1 SCS11_1 SIN3_1 Multi-function Serial 3 SOT3_1 (SDA3_1) SCK3_1 (SCL3_1) SIN4_1 SOT4_1 (SDA4_1) Multi-function Serial 4 Function Description SCK4_1 (SCL4_1) CTS4_1 RTS4_1 Document Number: 002-00233 Rev. *D Multi-function serial interface ch.1 serial chip select 1 output pin. Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA3 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when used as a CSIO (operation mode 2) and as SCL3 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA4 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when used as a CSIO (operation mode 2) and as SCL4 when used as an I2C pin (operation mode 4). Multi-function serial interface ch4 CTS input pin Multi-function serial interface ch4 RTS output pin Page 22 of 109 S6E1C Series Pin No. Pin Function Pin Name SIN6_1 SOT6_1 (SDA6_1) Multi-function Serial 6 SCK6_1 (SCL6_1) SCS60_1 Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA6 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when used as a CSIO (operation mode 2) and as SCL6 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.6 serial chip select 0 input/output pin. LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP30 8 8 7 E1 7 7 6 D1 6 6 5 E2 5 5 - - SCS61_1 Multi-function serial interface ch.6 serial chip select 1 output pin. 9 9 - - SCS62_1 Multi-function serial interface ch.6 serial chip select 2 output pin. 10 - - - 26 18 - - 25 17 - - 24 16 - - SIN7_1 Multi-function Serial 7 Function Description SOT7_1 (SDA7_1) SCK7_1 (SCL7_1) Document Number: 002-00233 Rev. *D Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA7 when used as an I2C pin (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when used as a CSIO (operation mode 2) and as SCL7 when used as an I2C pin (operation mode 4). Page 23 of 109 S6E1C Series Pin No. Pin Function Pin Name LQFP-64 QFN-64 LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP30 38 - - - 37 - - - 36 - - - 35 - - - I2S Master Clock Input/output pin (operation mode 2). 34 - - - I2S Serial Data Input pin (operation mode 2). 8 8 - - 7 7 - - 6 6 - - 5 5 - - 9 9 - - 11 - - - 16 - - - IC1_DATA_0 Smart Card insert detection output pin Smart Card serial interface clock output pin Smart Card serial interface data input pin 12 - - - IC1_RST_0 IC1_VCC_0 Smart Card reset output pin Smart Card power enable output pin 13 15 - - - IC1_VPEN_0 UDM0 Smart Card programming output pin USB function/host D – pin 14 58 44 30 A3 USB function/host D + pin USB external pull-up control pin 59 61 45 47 31 - A2 - 64 43 48 31 1 21 D2 C3 11 64 10 48 1 D2 43 11 31 10 21 - C3 - MI2SDI4_1 MI2SDO4_1 MI2SCK4_1 MI2SWS4_1 MI2SMCK4_1 I2S(MFS) MI2SDI6_1 MI2SDO6_1 MI2SCK6_1 MI2SWS6_1 MI2SMCK6_1 IC1_CIN_0 IC1_CLK_0 Smart Card Interface USB UDP0 UHCONX0 RTCCO_0 RTCCO_1 Real-time Clock RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 HDMI-CEC/Re mote Control Reception Function Description I2S Serial Data Input pin (operation mode 2). I2S Serial Data Output pin (operation mode 2). I2S Serial Clock Output pin (operation mode 2). I2S Word Select Output pin (operation mode 2). I2S Serial Data Output pin (operation mode 2). I2S Serial Clock Output pin (operation mode 2). I2S Word Select Output pin (operation mode 2). I2S Master Clock Input/output pin (operation mode 2). 0.5 seconds pulse output pin of real-time clock Sub clock output pin CEC0_0 HDMI-CEC/Remote Control Reception ch.0 input/output pin 38 27 - - CEC1_0 HDMI-CEC/Remote Control Reception ch.1 input/output pin 33 25 17 D4 Document Number: 002-00233 Rev. *D Page 24 of 109 S6E1C Series Pin No. Pin Function Pin Name WKUP0 WKUP1 WKUP2 Low Power Consumption Mode WKUP3 WKUP4 WKUP5 WKUP6 WKUP7 RESET INITX MD0 MODE GND Analog Reference C pin 2 Mode 0 pin. During normal operation, input MD0="L". During serial programming to Flash memory, input MD0="H". LQFP-48 QFN-48 LQFP-32 QFN-32 WLCSP30 64 48 1 D2 41 29 19 C5 51 39 26 B3 56 42 29 B2 52 - - - 54 - - - 62 - - - 63 - - - 32 24 16 F5 17 13 8 F1 56 42 29 B2 18 30 14 22 9 14 F2 D5 X0 X0A X1 X1A Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin 19 31 15 23 10 15 E3 E5 Built-in high-speed CR oscillation clock output port 64 48 1 D2 27 48 19 36 11 24 F3 A5 57 29 43 21 13 E4 60 46 32 - 49 37 - - 50 38 25 - 28 20 12 F4 CROUT_1 POWER Deep Standby mode return signal input pin 0 Deep Standby mode return signal input pin 1 Deep Standby mode return signal input pin 2 Deep Standby mode return signal input pin 3 Deep Standby mode return signal input pin 4 Deep Standby mode return signal input pin 5 Deep Standby mode return signal input pin 6 Deep Standby mode return signal input pin 7 External Reset Input pin. A reset is valid when INITX="L". LQFP-64 QFN-64 Mode 1 pin. During normal operation, input is not needed. During serial programming to Flash memory, MD1 = "L" must be input. Main clock (oscillation) input pin Sub clock (oscillation) input pin MD1 CLOCK Function Description VCC VCC VCC VSS VSS AVRH2 AVRL C Power supply pin GND pin A/D converter analog reference voltage input pin A/D converter analog reference voltage input pin Power supply stabilization capacitance pin In case of 32-pin package, AVRH pin is internally connected to the VCC pin. Document Number: 002-00233 Rev. *D Page 25 of 109 S6E1C Series 6. I/O Circuit Type Type Circuit P-ch P-ch Digital output N-ch Digital output Remarks X1 R Pull-up resistor control Digital input Standby mode Control Clock input It is possible to select the main oscillation / GPIO function When the main oscillation is selected. ・Oscillation feedback resistor Approximately 1 MΩ ・With standby mode control A Standby mode Control Digital input Standby mode Control R P-ch P-ch Digital output N-ch Digital output X0 When the GPIO is selected. ・CMOS level output. ・CMOS level hysteresis input ・With pull-up resistor control ・With standby mode control ・Pull-up resistor Approximately 33 kΩ ・IOH= -4 mA, IOL= 4 mA Pull-up resistor control B Pull-up resistor Digital input Document Number: 002-00233 Rev. *D CMOS level hysteresis input Pull-up resistor Approximately 33 kΩ Page 26 of 109 S6E1C Series Type Circuit P-ch P-ch Digital output N-ch Digital output Remarks X1A R Pull-up resistor control Digital input Standby mode Control Clock input C Standby mode Control Digital input Standby mode Control R P-ch P-ch Digital output N-ch Digital output It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.  Oscillation feedback resistor Approximately 5 MΩ  With Standby mode control When the GPIO is selected.  CMOS level output.  CMOS level hysteresis input  With pull-up resistor control  With standby mode control  Pull-up resistor Approximately 33 kΩ IOH= -4 mA, IOL= 4 mA X0A Pull-up resistor control Document Number: 002-00233 Rev. *D Page 27 of 109 S6E1C Series Type Circuit P-ch D P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Remarks ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor Approximately 33 kΩ ・ IOH= -4mA, IOL= 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Standby mode Control P-ch E P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode Control ・ CMOS level output ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor Approximately 33 kΩ ・ IOH= -4 mA, IOL= 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Wake up request Wake up control Document Number: 002-00233 Rev. *D Page 28 of 109 S6E1C Series Type Circuit P-ch P-ch Digital output N-ch Digital output R F Pull-up resistor control Digital input Standby mode Control Analog input Remarks ・ CMOS level output ・ CMOS level hysteresis input ・ With input control ・ Analog input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor Approximately 33 kΩ ・ IOH= -4 mA, IOL= 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Input control P-ch P-ch N-ch Digital output Digital output R G Pull-up resistor control Digital input Standby mode Control Wake up request Wake up Control ・ CMOS level output ・ CMOS level hysteresis input ・ With input control ・ Analog input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 33 kΩ ・ IOH= -4 mA, IOL= 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Analog input Input control Document Number: 002-00233 Rev. *D Page 29 of 109 S6E1C Series Type Circuit P-ch H Remarks P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode Control ・ CMOS level hysteresis input Mode input I ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor Approximately 33 kΩ ・ IOH= -4 mA, IOL= 4 mA ・ Available to control PZR registers ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output UDP0/P81 USB Full-speed/Low-speed control UDP input Differential J UDM0/P80 Differential input It is possible to select the USB I/O / GPIO function. When the USB I/O is selected.  Full-speed, Low-speed control USB/GPIO select UDM input UDM output When the GPIO is selected.  CMOS level output  CMOS level hysteresis input  With standby mode control USB Digital input/output direction GPIO Digital input GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: 002-00233 Rev. *D Page 30 of 109 S6E1C Series 7. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 7.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Document Number: 002-00233 Rev. *D Page 31 of 109 S6E1C Series Latch-Up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 7.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should mount only under Cypress’ recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Document Number: 002-00233 Rev. *D Page 32 of 109 S6E1C Series Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C and 30 ˚C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-00233 Rev. *D Page 33 of 109 S6E1C Series 7.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-00233 Rev. *D Page 34 of 109 S6E1C Series 8. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVRH pin and AVRL pin near this device. Stabilizing Supply Voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF  Lead type Load capacitance: Approximately 6 pF to 7 pF Document Number: 002-00233 Rev. *D Page 35 of 109 S6E1C Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. However in the Deep Standby mode, an external clock as an input of the sub clock cannot be used. Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. Set as External clock input X1(PE3), X1A (P47) Handling when Using Multi-Function Serial Pin as I2C Pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. Incidentally, the C pin becomes floating in Deep standby mode. C Device CS VSS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Document Number: 002-00233 Rev. *D Page 36 of 109 S6E1C Series Notes on Power-on Turn power on/off in the following order or at the same time. Turning on : VCC →AVRH Turning off : AVRH →VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise; perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features Among the Products with Different Memory Sizes and Between Flash Memory Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Handling when Using Debug Pins When debug pins (SWDIO/SWCLK) are set to GPIO or other peripheral functions, set them as output only; do not set them as input. Document Number: 002-00233 Rev. *D Page 37 of 109 S6E1C Series 9. Memory Map Memory Map (1) 0x41FF_FFFF Reserved 0xFFFF_FFFF 0xF802_0000 0xF800_0180 0xF800_0100 0xF800_0000 0xF000_2000 0xF000_1000 0xF000_0000 0xE000_0000 Reserved FAST GPIO (Single-cycle I/O port) VIR (Vector Indicate reg.) (Single-cycle I/O port) FAST GPIO (Single-cycle I/O port) Reserved MTB_DWT CM0+ Coresight-MTB(SFR) CM0+ Private Peripherals Reserved 0x4006_2000 0x4006_1000 0x4005_0000 0x4004_0000 0x4003_CB00 0x4003_CA00 0x4003_C900 0x4003_C200 0x4003_C100 0x4003_C000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4200_0000 0x4000_0000 Peripherals Reserved Reserved MFS-I2S Clock Gen. Smart Card I/F Reserved Peripheral Clock Gating Low Speed CR Prescaler RTC Watch Counter CRC Accelerator MFS Reserved 0x4003_7000 0x4003_6000 0x4003_5000 0x4400_0000 32 Mbytes Bit band alias 0x40000000 ~ 0x40100000 DSTC Reserved USB 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 USB Clock ctrl LVD/DS mode HDMI-CEC/ Remote Control Receiver GPIO Reserved Int-Req.Read EXTI Reserved HCR Trimming 0x2400_0000 32 Mbytes Bit band alias 0x20000000 ~ 0x20100000 0x2200_0000 Reserved Reserved 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 A/D Converter Reserved Base Timer 0x2000_4000 Reserved SRAM 0x2000_0000 0x0010_0008 0x0010_0004 0x0010_0000 0x0001_FFF0 Reserved CR Trim Security Reserved 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 FLASH Dual timer Reserved SW-Watchdog HW-Watchdog Clock/Reset Reserved 0x0000_0000 0x4000_1000 See "Memory map (2)" for the memory size details. Document Number: 002-00233 Rev. *D 0x4000_0000 Flash-IF Page 38 of 109 S6E1C Series Memory Map (2) S6E1C11/S6E1C31 S6E1C12/S6E1C32 *: See "S6E1C1/C3 Series Flash Programming Manual" to check details of the flash memory. Document Number: 002-00233 Rev. *D Page 39 of 109 S6E1C Series Peripheral Address Map Start Address 0x4000_0000 End Address 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog Timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Reserved 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF Reserved 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Reserved 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_5000 0x4003_6000 0x4003_7000 0x4003_4FFF 0x4003_5FFF 0x4003_6FFF 0x4003_77FF 0x4003_7800 0x4003_79FF Reserved 0x4003_7A00 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function Serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_C0FF Low-speed CR Prescaler 0x4003_C100 0x4003_C800 0x4003_C900 0x4003_CA00 0x4003_CB00 0x4004_0000 0x4005_0000 0x4006_1000 0x4006_2000 0x4003_C7FF 0x4003_C8FF 0x4003_C9FF 0x4003_CAFF 0x4003_FFFF 0x4004_FFFF 0x4006_0FFF 0x4006_1FFF 0x41FF_FFFF Peripheral Clock Gating Reserved Smart Card Interface MFS-I2S Clock Generator Reserved USB ch.0 Reserved DSTC Reserved Document Number: 002-00233 Rev. *D Bus AHB APB0 APB1 AHB Peripheral Flash memory I/F register Reserved Software Watchdog Timer Reserved HDMI-CEC/Remote Control Receiver Low-Voltage Detection / DS mode / Vref Calibration USB Clock Generator Reserved Page 40 of 109 S6E1C Series 10. Pin Status in Each CPU State The following table shows pin status in each CPU state. Type A B Selected Pin Function Main oscillation circuit selected3 Digital I/O selected4 Main oscillation circuit selected3 Digital I/O selected4 Sub oscillation circuit selected3 C Digital I/O selected4 CPU State (1) (2) (3) (4) (5) (6) (7) (8) OS OS OE OE OE GS IS OS - - IE/IS PC IE/IS HC IE/IS IS IS HS IS IS IS HS OS OS OE OE OE GS IS OS - - PC HC IS GS IS GS OS OE OE OE OE OE OE OE Sub clock external input selected - - IE/IS IE/IS IE/IS IS IS IS GPIO selected - - PC HC IS HS IS HS OS OE OE OE OE OE OE OE - - PC HC IS HS IS HS Main oscillation circuit selected Main clock external input selected GPIO selected Main oscillation circuit selected GPIO selected Sub oscillation circuit selected Sub oscillation circuit selected 3 Sub oscillation circuit selected Digital I/O selected4 GPIO selected E Digital I/O selected INITX input This pin is digital input pin, pull up resistor is on, and digital input is not shut off in all CPU states. F Digital I/O selected MD0 input This pin is digital input pin, pull up resistor is none, digital input is not shut off in all CPU states. G USB I/O selected5 Digital I/O selected6 D USB port selected GPIO selected SW selected H Digital I/O selected I Digital I/O selected NMI selected WKUP0 enable and input selected GPIO selected Analog input selected8 Analog input selected J Digital I/O selected9 K Digital I/O selected GPIO selected WKUP enable and input selected External interrupt enable and input selected GPIO selected Resource other than above selected CEC pin selected WKUP enable and input selected External interrupt enable and input selected GPIO selected Resource other than above selected - - UE US US US US US IS IE CP HC IS HS IS HS 7 IS - IP PC IP IP IP IP IP - PC HC IS HS IS HS IS IE IP IP PC IP IP HC IP IP IS IP - IP - IP - IP IS IS IS CP IP IS IS IS IP GS HS GS CP IP GS HS GS Analog input is enabled in all CPU state IS - IE - IP IP PC PC CP IP PC PC PC IP IP HC HC CP IP HC HC HC IP IP IS IS CP IP IP IS IS IP GS HS GS CP IP GS HS GS Terms in the table above have the following meanings. 3 4 5 6 7 8 9 In this type, when internal oscillation function is selected, digital output is disabled. (Hi-Z) pull up resistor is off, digital input is shut off by fixed 0. In this type, when Digital I/O function is selected, internal oscillation function is disabled. In this type, when USB I/O function is selected, digital output is disabled. (Hi-Z), digital input is shut off by fixed 0. In this type, when Digital I/O function is selected, USB I/O function is disabled.This pin does not have pull up resistor. In this case, PCR register is initialized to “1”. Pull up resistor is on. In this type, when analog input function is selected, digital output is disabled, (Hi-Z). pull up resistor is off, digital input is shut off by fixed 0. In this type, when Digital I/O function is selected, analog input function is not available. Document Number: 002-00233 Rev. *D Page 41 of 109 S6E1C Series Type This indicates a pin status type that is shown in “pin list table” in “5. List of Pin Functions” Selected Pin function This indicates a pin function that is selected by user program. CPU state This indicates a state of the CPU that is shown below. (1) Reset state. CPU is initialized by Power-on reset or a reset due to low Power voltage supply. (2) Reset state. CPU is initialized by INITX input signal or system initialization after power on reset. (3) Run mode or SLEEP mode state. (4) (5) (6) Timer mode, RTC mode or STOP mode state. The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0". Timer mode, RTC mode or STOP mode state. The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1". Deep standby STOP mode or Deep standby RTC mode state, The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0" (7) (8) Deep standby STOP mode or Deep standby RTC mode state, The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1" Run mode state after returning from Deep Standby mode. (I/O state hold function(CONTX) is fixed at 1) Document Number: 002-00233 Rev. *D Page 42 of 109 S6E1C Series Each pin status The meaning of the symbols in the pin status table is as follows. IS Digital output is disabled. (Hi-Z) Pull up resistor is off. Digital input is shut off by fixed 0. IE Digital output is disabled. (Hi-Z) Pull up resistor is off. Digital input is not shut off. IP Digital output is disabled. (Hi-Z) Pull up resistor is defined by the value of the PCR register. Digital input is not shut off. IE/IS Digital output is disabled. (Hi-Z) Pull up resistor is off. Digital input is shut off in case of the OSC stop. Digital input is not shut off in case of the OSC operation. OE The OSC is in operation state. However, it may be stopped in some operation mode of the CPU. For detail, see chapter “Low Power Consumption Mode” in peripheral manual. OS The OSC is in stop state. (Hi-Z) UE USB I/O function is controlled by USB controller. US USB I/O function is disabled(Hi-Z) PC Digital output and pull up resistor is controlled by the register in the GPIO or peripheral function. Digital input is not shut off CP Digital output is controlled by the register in the GPIO or peripheral function. Pull up resistor is off. Digital input is not shut off. HC Digital output and pull up resistor is maintained the status that is immediately prior to entering the current CPU state. Digital input is not shut off HS Digital output and pull up resistor is maintained the status that is immediately prior to entering the current CPU state. Digital input is shut off GS Digital output and pull up resistor is copied the GPIO status that is immediately prior to entering the current CPU state and the status is maintained. Digital input is shut off. Document Number: 002-00233 Rev. *D Page 43 of 109 S6E1C Series 11. Electrical Characteristics 11.1 Absolute Maximum Ratings Parameter Power supply voltage10, 11 Analog reference voltage10, 12 Input voltage10 Symbol VCC AVRH VI Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 Analog pin input voltage10 Output voltage10 L level maximum output current13 L level average output current14 L level total maximum output current L level total average output current15 H level maximum output current13 H level average output current14 H level total maximum output current H level total average output current15 Power consumption Storage temperature VIA VSS - 0.5 VO VSS - 0.5 IOL IOLAV ∑IOL ∑IOLAV IOH IOHAV ∑IOH ∑IOHAV PD TSTG - 55 Max VSS + 4.6 VSS + 4.6 VCC + 0.5 (≤ 4.6 V) VSS + 6.5 VCC + 0.5 (≤ 4.6 V) Vcc + 0.5 (≤ 4.6 V) 10 4 100 50 - 10 -4 - 100 - 50 200 + 150 Unit Remarks V V V V 5 V tolerant V V mA mA mA mA mA mA mA mA mW °C 4 mA type 4 mA type 4 mA type 4 mA type − Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 10 11 12 13 14 15 These parameters are based on the condition that VSS= 0 V. VCC must not drop below VSS - 0.5 V. Ensure that the voltage does not to exceed VCC + 0.5 V at power-on. The maximum output current is the peak value for a single pin. The average output is the average current for a single pin over a period of 100 ms. The total average output current is the average current for all pins over a period of 100 ms. Document Number: 002-00233 Rev. *D Page 44 of 109 S6E1C Series 11.2 Recommended Operating Conditions (VSS= 0.0 V) Parameter Power supply voltage Analog reference voltage Smoothing capacitor Operating temperature Symbol Conditions VCC - AVRH - AVRL CS Ta - Value Unit Remarks Min 1.6516 Max 3.6 3.0 3.6 V 17 2.7 VCC V VCC ≥ 2.7 V VCC VSS 1 - 40 VCC VSS 10 + 105 V V μF °C VCC < 2.7 V V For regulator18 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 16 In between less than the minimum power supply voltage reset / interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. 17 When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). 18 See "C Pin" in "8. Handling Devices" for the connection of the smoothing capacitor. Document Number: 002-00233 Rev. *D Page 45 of 109 S6E1C Series 11.3 DC Characteristics 11.3.1 Current Rating Symbol HCLK Conditions (Pin Name) 22 Run mode, code executed from Flash Run mode, Icc (VCC) code executed from RAM Run mode, code executed from Flash Run mode, code executed from Flash 8 MHz external clock input, PLL ON NOP code executed Built-in high speed CR stopped All peripheral clock stopped by CKENx 8 MHz external clock input, PLL ON22 Benchmark code executed Built-in high speed CR stopped PCLK1 stopped 8 MHz crystal oscillation, PLL ON22 NOP code executed Built-in high speed CR stopped All peripheral clock stopped by CKENx 8 MHz external clock input, PLL ON22 NOP code executed Built-in high speed CR stopped All peripheral clock stopped by CKENx 8 MHz external clock input, PLL ON NOP code executed Built-in high speed CR stopped PCLK1 stopped Built-in high speed CR27 NOP code executed All peripheral clock stopped by CKENx 32 kHz crystal oscillation NOP code executed All peripheral clock stopped by CKENx Built-in low speed CR NOP code executed All peripheral clock stopped by CKENx Value Frequency19 8 MHz Typ20 Max21 1.4 2.7 20 MHz 2.6 4.1 40 MHz 3.9 5.6 8 MHz 1.3 2.6 20 MHz 2.3 3.8 40 MHz 3.4 5.1 8 MHz 1.6 3.0 20 MHz 2.8 4.4 40 MHz 4.1 5.9 Unit Remarks mA 23 mA 23 mA 23 mA 23 , 8 MHz 1.0 2.1 20 MHz 1.7 2.9 40 MHz 2.7 4.0 40 MHz 1.6 3.1 mA 23 8 MHz 1.1 2.4 mA 23 32 kHz 240 1264 μA 23 100 kHz 246 1271 μA 23 mA 23 , 8 MHz 0.8 1.9 20 MHz 1.3 2.4 40 MHz 1.8 3.0 Built-in high speed CR All peripheral clock stopped by CKENx 8 MHz 0.6 1.7 mA 23 32 kHz crystal oscillation All peripheral clock stopped by CKENx 32 kHz 237 1261 μA 23 Built-in low speed CR All peripheral clock stopped by CKENx 100 kHz 238 1262 μA 23 8 MHz external clock input, PLL ON22 All peripheral clock stopped by CKENx 24 , 25 , 26 27 19 20 21 22 23 24 25 26 27 Iccs Sleep (VCC) operation PCLK0 is set to divided rate 8. TA=+25°C,VCC=3.3 V TA=+105°C,VCC=3.6 V When HCLK=8, PLL is off. All ports are fixed When IMAINSEL bit (MOSC_CTL:IMAINSEL) is “10” (default). Flash sync down is set to FRWTR.RWT=111 and FSYNDN.SD=1111 VCC=1.65 V The frequency is set to 8 MHz by trimming Document Number: 002-00233 Rev. *D Page 46 of 109 S6E1C Series Parameter Symbol (Pin Name) Value Conditions ICCH (VCC) Power supply current ICCT (VCC) Stop mode Sub timer mode ICCR (VCC) 28 29 RTC mode Unit Remarks Typ Max Ta=25℃ Vcc=3.3 V 12.4 52.4 μA 28, 29 Ta=25℃ Vcc=1.65 V 12.0 52.0 μA 28, 29 Ta=105℃ Vcc=3.6 V - 597 μA 28, 29 15.6 55.6 μA 28, 29 15.0 55.0 μA 28, 29 - 601 μA 28, 29 13.2 53.2 μA 28, 29 12.7 52.7 μA 28, 29 - 598 μA 28, 29 Ta=25℃ Vcc=3.3 V 32 kHz Crystal oscillation Ta=25℃ Vcc=1.65 V 32 kHz Crystal oscillation Ta=105℃ Vcc=3.6 V 32 kHz Crystal oscillation Ta=25℃ Vcc=3.3 V 32 kHz Crystal oscillation Ta=25℃ Vcc=1.65 V 32 kHz Crystal oscillation Ta=105℃ Vcc=3.6 V 32 kHz Crystal oscillation All ports are fixed. LVD off. Flash off. When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added. Document Number: 002-00233 Rev. *D Page 47 of 109 S6E1C Series Parameter Symbol (Pin Name) Value Conditions RAM off ICCHD (VCC) Deep standby Stop mode RAM on Power supply current RAM off ICCRD (VCC) Deep standby RTC mode RAM on 30 31 Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta=105°C Vcc=3.6 V Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta=105°C Vcc=3.6 V Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta=105°C Vcc=3.6 V Ta=25°C Vcc=3.3 V Ta=25°C Vcc=1.65 V Ta=105°C Vcc=3.6 V Unit Remarks Typ Max 0.58 1.85 μA 30, 31 0.56 1.83 μA 30, 31 - 46 μA 30, 31 0.78 6.6 μA 30, 31 0.76 6.6 μA 30, 31 - 88 μA 30, 31 1.16 2.4 μA 30, 31 1.15 2.4 μA 30, 31 - 46 μA 30, 31 1.37 7.2 μA 30, 31 1.35 7.2 μA 30, 31 - 88 μA 30, 31 All ports are fixed. LVD off. When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added. Document Number: 002-00233 Rev. *D Page 48 of 109 S6E1C Series LVD Current (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Low-Voltage detection circuit (LVD) power supply current Symbol ICCLVD Pin Name VCC Conditions At operation Value Typ 0.15 Max 0.3 0.10 0.3 Unit Remarks μA For occurrence of reset μA For occurrence of interrupt Bipolar Vref Current (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Bipolar Vref Current Symbol Pin Name Conditions ICCBGR VCC At operation Value Typ Max 100 200 Unit Remarks μA Flash Memory Current (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Flash memory write/erase current Symbol Pin Name Conditions ICCFLASH VCC At Write/Erase Value Typ Max 4.4 5.6 Unit Remarks mA A/D converter Current (VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Symbol Pin Name Conditions Power supply current ICCAD VCC Reference power supply current (AVRH) ICCAVRH AVRH Parameter Document Number: 002-00233 Rev. *D Value Unit Typ Max At operation 0.5 0.75 mA At operation 0.69 1.3 mA At stop 0.1 1.3 μA Remarks AVRH=3.6 V Page 49 of 109 S6E1C Series Peripheral Current Dissipation (VCC=1.65 V to 3.6 V, VSS=0 V, TA=- 40°C to +105°C) Clock System Peripheral Conditions GPIO At all ports operation 0.05 0.12 0.23 DSTC At 2ch operation 0.02 0.06 0.10 USB At 1ch operation 0.13 0.13 0.13 Base timer At 4ch operation 0.02 0.05 0.10 ADC At 1 unit operation 0.04 0.10 0.21 Multi-function serial At 1ch operation 0.01 0.03 0.06 MFS-I2S At 1ch operation 0.02 0.05 0.08 Smart Card I/F At 1ch operation 0.04 0.08 0.18 HCLK PCLK1 32 Frequency (MHz) 20 8 40 Unit Remarks mA mA 32 mA USB itself uses 48 MHz clock Document Number: 002-00233 Rev. *D Page 50 of 109 S6E1C Series 11.3.2 Pin Characteristics (VCC = 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) H level output voltage L level output voltage Input leak current Pull-up resistance value Input capacitance Value Typ Max - VCC +0.3 V VCC × 0.8 VCC × 0.7 - VSS +5.5 V VSS - 0.3 - Symbol Pin Name Conditions VCC ≥ 2.7 V VCC × 0.8 VIHS CMOS hysteresis input pin, MD0 VCC < 2.7 V VCC × 0.7 5 V tolerant input pin VCC ≥ 2.7 V VCC < 2.7 V CMOS hysteresis input pin, MD0 VCC ≥ 2.7 V VILS 5 V tolerant input pin VOH 4 mA type Min VCC < 2.7 V V VCC × 0.3 VCC ≥ 2.7 V - VCC × 0.2 - VCC × 0.3 - VCC V VSS - 0.3 VCC < 2.7 V V VCC ≥ 2.7 V, IOH = - 4 mA VCC - 0.5 VCC < 2.7 V, IOH = - 2 mA VCC - 0.45 VSS - 0.4 V μA VOL 4 mA type IIL - - -5 - +5 VCC ≥ 2.7 V 21 33 48 RPU Pull-up pin VCC < 2.7 V - - 88 - - 5 15 Other than VCC, VSS, AVRH Document Number: 002-00233 Rev. *D Remarks VCC × 0.2 VCC ≥ 2.7 V, IOL 4 mA VCC < 2.7 V, IOL=2 mA CIN Unit kΩ pF Page 51 of 109 S6E1C Series 11.4 AC Characteristics 11.4.1 Main Clock Input Characteristics (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time Internal operating clock33 frequency Internal operating clock33 cycle time Symbol Pin name FCH X0, X1 Conditions Value Unit Remarks Min Max VCC ≥ 2.7V VCC < 2.7V 8 8 48 20 MHz When the crystal oscillator is connected - 8 48 MHz When the external clock is used - 20.83 125 ns PWH/tCYLH, PWL/tCYLH 45 55 % - - 5 ns tCF, tCR FCM - - - 40.8 MHz When the external clock is used When the external clock is used When the external clock is used Master clock FCC FCP0 FCP1 - - - 40.8 40.8 40.8 MHz MHz MHz Base clock (HCLK/FCLK) APB0 bus clock34 APB1 bus clock34 tCYCCM tCYCC tCYCP0 tCYCP1 - - 24.5 - ns Master clock - - 24.5 24.5 24.5 - ns ns ns Base clock (HCLK/FCLK) APB0 bus clock34 APB1 bus clock34 tCYLH - X0 33 34 For details of each internal operating clock, refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual". For details of the APB bus to which a peripheral is connected, see the Peripheral Address Map. Document Number: 002-00233 Rev. *D Page 52 of 109 S6E1C Series 11.4.2 Sub Clock Input Characteristics35 (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Input frequency Symbol Pin Name Conditions Value Unit Min Typ Max - - 32.768 - kHz - 32 - 100 kHz fCL X0A, X1A Input clock cycle tCYLL - 10 - 31.25 μs Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % Remarks When the crystal oscillator is connected When the external clock is used When the external clock is used When the external clock is used X0A 35 See "Sub crystal oscillator" in "11. Handling Devices" for the crystal oscillator used. Document Number: 002-00233 Rev. *D Page 53 of 109 S6E1C Series 11.4.3 Built-in CR Oscillation Characteristics Built-in High-Speed CR (VCC= 1.65 V to 3.6 V, VSS = 0 V, TA=- 40°C to +105°C) Parameter Symbol Value Conditions Ta = - 10°C to + 105°C, Clock frequency Frequency stabilization time Min Typ Max 7.92 8 8.08 Unit MHz After trimming36 FCRH tCRWT Remarks Ta = - 40°C to + 105°C, 7.84 8 8.16 MHz - - - 300 μs 37 Built-in Low-Speed CR (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Clock frequency 36 37 Symbol Conditions fCRL - Value Min Typ Max 50 100 150 Unit Remarks kHz In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming. This is time from the trim value setting to stable of the frequency of the High-speed CR clock. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Document Number: 002-00233 Rev. *D Page 54 of 109 S6E1C Series 11.4.4 Operating Conditions of Main PLL (In the Case of Using the Main Clock as the Input Clock of the PLL) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Value Min Typ Max Unit PLL oscillation stabilization wait time38 (LOCK UP time) tLOCK 50 - - μs PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency39 USB clock frequency40 FPLLI FPLLO FCLKPLL FCLKSPLL 8 5 75 - - 16 18 150 40 48 MHz multiple MHz MHz MHz Remarks Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock PLL macro oscillation clock Main PLL M divider Main PLL clock (CLKPLL) N divider USB clock divider USB clock 11.4.5 Operating Conditions of Main PLL (In the Case of Using the Built-in High-Speed CR Clock as the Input Clock of the Main PLL) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Value Min Typ Max Unit PLL oscillation stabilization wait time41 (LOCK UP time) tLOCK 50 - - μs PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency42 FPLLI FPLLO FCLKPLL 7.84 9 75 - 8 - 8.16 18 150 40.8 MHz multiple MHz MHz Remarks Note: − For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency and temperature have been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. 38 39 40 41 42 The wait time is the time it takes for PLL oscillation to stabilize. For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual". For more information about USB clock, see "Chapter: USB Clock Generation" in "FM0+ Family Peripheral Manual Communication Macro Part”. The wait time is the time it takes for PLL oscillation to stabilize. For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual". Document Number: 002-00233 Rev. *D Page 55 of 109 S6E1C Series 11.4.6 Reset Input Characteristics (VCC = 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Pin Name Conditions tINITX INITX - Reset input time Value Min Max 500 - Unit Remarks ns 11.4.7 Power-on Reset Timing (VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Power supply shut down time Pin Name Condition tOFF Value Min Typ Unit Max - 2 - - ms dV/dt Vcc: 0.2V to 1.65V 0.6 - 1000 mV/μs tPRT - 0.43 - 3.4 ms VCC Power ramp rate Time until releasing Power-on reset Remarks VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met. This dV/dt characteristic is applied at the power-on of cold start (tOFF>2ms). 1.65V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST CPU Operation RST Active 0.2V tOFF release start Glossary  VDH: detection voltage of Low-Voltage detection reset. See "11.7 Low-Voltage Detection Characteristics". Document Number: 002-00233 Rev. *D Page 56 of 109 S6E1C Series 11.4.8 Base Timer Input Timing Timer Input Timing (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Input pulse width Symbol Pin Name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2 tCYCP - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger Input Timing (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Input pulse width Symbol Pin Name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2 tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map − ". Document Number: 002-00233 Rev. *D Page 57 of 109 S6E1C Series 11.4.9 CSIO/SPI/UART Timing CSIO (SPI=0, SCINV=0) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock "L" pulse width tSLSH Serial clock "H" pulse width tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx Conditions - VCC < 2.7 V Min Max 8 4 tCYCP - VCC ≥ 2.7 V Min Max 8 4 tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns SCKx 2 tCYCP 10 - - ns SCKx tCYCP + 10 - - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Master mode 2 tCYCP 10 tCYCP + 10 Slave mode Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − The characteristics are applicable only when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00233 Rev. *D Page 58 of 109 S6E1C Series tSCYC VOH SCK VOL VOL tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Master mode tSLSH SCK tSHSL VIH VIH tF VIL VIL VIH tR tSLOVE SOT VOH VOL tIVSHE SIN VIH VIL tSHIXE VIH VIL Slave mode Document Number: 002-00233 Rev. *D Page 59 of 109 S6E1C Series CSIO (SPI=0, SCINV=1) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx Baud rate Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCK falling time SCK rising time tF tR Conditions - Master mode VCC < 2.7V Min Max 8 4 tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns - ns - ns 2 tCYCP 10 tCYCP + 10 Slave mode VCC ≥ 2.7V Min Max 8 4 tCYCP - - 2 tCYCP 10 tCYCP + 10 - 50 - 33 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns - Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − The characteristics are applicable only when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00233 Rev. *D Page 60 of 109 S6E1C Series tSCYC SCK VOH VOH VOL tSHOVI VOH SOT VOL tIVSLI VIH SIN tSLIXI VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-00233 Rev. *D Page 61 of 109 S6E1C Series SPI (SPI=1, SCINV=0) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Baud rate Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓→ SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓→ SIN hold time tSLIXE SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCK falling time SCK rising time tF tR Conditions - Master mode VCC < 2.7 V Min Max 8 4 tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns - ns - ns - ns 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 Slave mode VCC ≥ 2.7 V Min Max 8 4 tCYCP - - 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 - 50 - 33 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns - Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − The characteristics are applicable only when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00233 Rev. *D Page 62 of 109 S6E1C Series tSCYC VOH SCK VOL SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH VIH SCK VIL tF * SOT VIL tSHSL tR VOH VOL tIVSLE SIN VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register Document Number: 002-00233 Rev. *D Page 63 of 109 S6E1C Series SPI (SPI=1, SCINV=1) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Pin name SCKx Baud rate Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI SOT → SCK ↑ delay time tSOVHI Serial clock "L" pulse width tSLSH SCKx Serial clock "H" pulse width tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCK falling time SCK rising time tF tR Conditions - SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Master mode VCC < 2.7 V Min Max 8 4 tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 0 - ns - ns - ns - ns 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 Slave mode VCC ≥ 2.7 V Min Max 8 4 tCYCP - - 2 tCYCP 30 2 tCYCP 10 tCYCP + 10 - 50 - 33 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns - Notes: − The above AC characteristics are for clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − The characteristics are applicable only when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCKx_0 and SOTx_1. − External load capacitance CL=30 pF Document Number: 002-00233 Rev. *D Page 64 of 109 S6E1C Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL Master mode tR SCK VIL tF tSHSL VIH VIH tSLSH VIL VIL tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL Slave mode Document Number: 002-00233 Rev. *D Page 65 of 109 S6E1C Series When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=1) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Conditions VCC ≥ 2.7 V VCC < 2.7 V Unit Min Max Min Max -5043 +043 -5043 +043 ns +044 +5044 +044 +5044 ns tCSDI -5045 +5044 -5044 +5044 ns SCS↓→SCK↓ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 55 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time Master mode Slave mode Notes: − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − − For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − When the external load capacitance CL=30 pF. These characteristics guarantee only the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. 43 CSSU bit value × serial chip select timing operating clock cycle. CSHD bit value × serial chip select timing operating clock cycle. 45 CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. 44 Document Number: 002-00233 Rev. *D Page 66 of 109 S6E1C Series SCSO tCSSI tCSHI tCSDI tCSHE tCSDE SCK SOT (SPI=0) SOT (SPI=1) Master mode SCSI tCSSE SCK tDEE SOT (SPI=0) tDSE SOT (SPI=1) Slave mode Document Number: 002-00233 Rev. *D Page 67 of 109 S6E1C Series When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=1) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter SCS↓→SCK↑ setup time SCK↓→SCS↑ hold time Symbol Conditions VCC ≥ 2.7 V VCC < 2.7 V Unit Min Max Min Max tCSSI -5046 +046 -5046 +046 ns tCSHI +047 +5047 +047 +5047 ns +5048 -5048 +5048 ns Master mode SCS deselect time tCSDI -5048 SCS↓→SCK↑ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 55 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns Slave mode Notes: − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − − For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − When the external load capacitance CL=30 pF. These characteristics guarantee only the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. 46 CSSU bit value × serial chip select timing operating clock cycle. CSHD bit value × serial chip select timing operating clock cycle. 48 CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. 47 Document Number: 002-00233 Rev. *D Page 68 of 109 S6E1C Series SCSO tCSSI tCSHI tCSDI tCSHE tCSDE SCK SOT (SPI=0) SOT (SPI=1) Master mode SCSI tCSSE SCK tDEE SOT (SPI=0) tDSE SOT (SPI=1) Slave mode Document Number: 002-00233 Rev. *D Page 69 of 109 S6E1C Series When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=0) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Conditions VCC ≥ 2.7 V VCC < 2.7 V Unit Min Max Min Max tCSSI -5049 +049 -5049 +049 ns SCK↑→SCS↓ hold time tCSHI +050 +5050 +050 +5050 ns SCS deselect time tCSDI -5051 +5051 -5051 +5051 ns SCS↑→SCK↓ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time SCS↓→SOT delay time SCS↑→SCK↓ setup time Master mode 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns tDSE - 55 - 40 ns tDEE 0 - 0 - ns Slave mode Notes: − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − − For information About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − When the external load capacitance CL=30 pF. These characteristics guarantee only the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. 49 CSSU bit value × serial chip select timing operating clock cycle. CSHD bit value × serial chip select timing operating clock cycle. 51 CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. 50 Document Number: 002-00233 Rev. *D Page 70 of 109 S6E1C Series tCSDI SCSO tCSSI tCSHI SCK SOT (SPI=0) SOT (SPI=1) Master mode tCSDE SCSI tCSSE tCSHE SCK tDEE SOT (SPI=0) tDSE SOT (SPI=1) Slave mode Document Number: 002-00233 Rev. *D Page 71 of 109 S6E1C Series When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=0) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Conditions VCC ≥ 2.7 V VCC < 2.7 V Unit Min Max Min Max tCSSI -5052 +052 -5052 +052 ns SCK↓→SCS↓ hold time tCSHI +053 +5053 +053 +5053 ns SCS deselect time tCSDI -5054 +5054 -5054 +5054 ns SCS↑→SCK↑ setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time SCS↓→SOT delay time SCS↑→SCK↑ setup time Master mode 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns tDSE - 55 - 40 ns tDEE 0 - 0 - ns Slave mode Notes: − tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. − − For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual". − When the external load capacitance CL=30 pF. These characteristics guarantee only the same relocate port number. For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed. 52 CSSU bit value × serial chip select timing operating clock cycle. CSHD bit value × serial chip select timing operating clock cycle. 54 CSDS bit value × serial chip select timing operating clock cycle. Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip select pin becomes active again. 53 Document Number: 002-00233 Rev. *D Page 72 of 109 S6E1C Series tCSDI SCSO tCSSI tCSHI SCK SOT (SPI=0) SOT (SPI=1) Master mode tCSDE SCSI tCSSE tCSHE SCK tDEE SOT (SPI=0) tDSE SOT (SPI=1) Slave mode Document Number: 002-00233 Rev. *D Page 73 of 109 S6E1C Series UART external clock input (EXT=1) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time Symbol tSLSH tSHSL tF tR Value Conditions Min tCYCP +10 tCYCP +10 - CL=30 pF tR Document Number: 002-00233 Rev. *D VIL Unit Remarks ns ns ns ns tF tSHSL SCK Max 5 5 VIH tSLSH VIH VIL VIL Page 74 of 109 S6E1C Series 11.4.10 External Input Timing (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Input pulse width 55 56 57 58 Symbol Value Min Pin Name Conditions ADTGx - 2 tCYCP55 - ns INT00 to INT08, INT12, INT13, INT15, NMIX 56 2 tCYCP +10055 - ns 57 500 - ns WKUPx 58 500 - ns Max Unit Remarks A/D converter trigger input tINH, tINL External interrupt, NMI Deep standby wake up tCYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. In Run mode and Sleep mode In Timer mode, RTC mode and Stop mode In Deep Standby RTC mode and Deep Standby Stop mode Document Number: 002-00233 Rev. *D Page 75 of 109 S6E1C Series 11.4.11 I2C Timing (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol SCL clock frequency (Repeated) Start condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width (Repeated) Start setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between Stop condition and Start condition FSCL Noise filter Conditions Standard-Mode Min Max 0 100 Fast-Mode Min Max 0 400 Unit kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs tSUSTA 4.7 - 0.6 - μs 0 3.4560 0 0.961 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP62 - 2 tCYCP62 - ns tHDDAT tSP CL=30 pF, R=(Vp/IOL)59 - Remarks ". To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL 59 R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL and SDA lines. VP represents the power supply voltage of the pull-up resistance, and IOL the VOL guaranteed current. 60 The maximum tHDDAT must satisfy at least the condition that the period during which the device is holding the SCL signal at L (t LOW ) does not extend. 61 A Fast-mode I2C bus device can be used in a Standard-mode I2C bus system, provided that the condition of tSUDAT ≥ 250 ns is fulfilled. 62 tCYCP represents the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map. Document Number: 002-00233 Rev. *D Page 76 of 109 S6E1C Series 11.4.12 I2S Timing (MFS-I2S Timing) Master Mode Timing (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter frequency63 MI2SCK max I2S clock cycle time63 I2S clock Duty cycle MI2SCK↓ → MI2SWS delay time MI2SCK↓ → MI2SDO delay time MI2SDI → MI2SCK ↑ setup time MI2SCK ↑ → MI2SDI hold time MI2SCK falling time MI2SCK rising time Symbo l FMI2SCK tICYC ∆ tSWDT tSDDT tDSST tSDHT tF tR Pin Name MI2SCKx MI2SCKx MI2SCKx MI2SCKx, MI2SWSx MI2SCKx, MI2SDOx MI2SCKx, MI2SDIx MI2SCKx, MI2SDIx MI2SCKx MI2SCKx VIH MI2SCK CL=30 pF VCC < 2.7 V Min Max 6.144 4 tCYCP 45% 55% VCC ≥ 2.7 V Min Max 6.144 4 tCYCP 45% 55% Unit MHz ns -30 +30 -20 +20 ns -30 +30 -20 +20 ns 50 - 36 - ns 0 - 0 - ns - 5 5 - 5 5 ns ns VIH VIL VIL tF Condition s tR tSWDT, tSDDT MI2SWS and MI2SDO MI2SDI VOH VOL tDSST tSDHT VIH VIH VIL VIL 63 I2S clock should meet the multiple of PCLK(tICYC) and the frequency less than FMI2SCK meantime. The detail information please refer to Chapter I2S of Communication Macro Part of the Peripheral Manual. Document Number: 002-00233 Rev. *D Page 77 of 109 S6E1C Series MI2SMCK Input Characteristics (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Pin Name Conditions Input frequency fCHS MI2SMCK Input clock cycle tCYLHS - - - tCFS tCRS - Input clock pulse width Input clock rise time and fall time Value Unit Min Max - - 12.288 MHz PWHS/tCYLHS PWLS/tCYLHS 81.3 - ns 45 55 % - - 5 ns Remarks When using external clock When using external clock MI2SMCK Output Characteristics (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Output frequency Symbol Pin Name Conditions fCHS MI2SMCK - Document Number: 002-00233 Rev. *D Value Unit Remarks 25 MHz VCC ≥ 2.7 V 20 MHz VCC < 2.7 V Min Max - Page 78 of 109 S6E1C Series 11.4.13 Smart Card Interface Characteristics (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Output rising time tR Output falling time tF Pin Name ICx_VCC, ICx_RST, ICx_CLK, Output clock frequency Duty cycle fCLK ∆ Conditions ICx_DATA ICx_CLK CL=30 pF Value Unit Min Max 4 20 ns 4 20 ns - 20 MHz 45% 55% Remarks  External pull-up resistor (20 kΩ to 50 kΩ) must be applied to ICx_CIN pin when it’s used as smart card reader function. Document Number: 002-00233 Rev. *D Page 79 of 109 S6E1C Series 11.4.14 SW-DP Timing (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter Symbol Pin Name Conditions SWDIO setup time tSWS SWCLK, SWDIO SWDIO hold time tSWH SWDIO delay time tSWD Value Unit Min Max - 15 - ns SWCLK, SWDIO - 15 - ns SWCLK, SWDIO - - 45 ns Remarks Note: − External load capacitance CL=30 pF SWCLK SWDIO (When input) SWD SWDIO (When output) Document Number: 002-00233 Rev. *D Page 80 of 109 S6E1C Series 11.5 12-bit A/D Converter Electrical Characteristics of A/D Converter (Preliminary Values) (VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C) Parameter ANxx Min - 4.5 - 2.5 - 15 Value Typ - Max 12 4.5 + 2.5 + 15 ANxx AVRH - 15 - AVRH + 15 1.0 - - 4.0 - - 10 - - 0.3 - 1.2 - 3.0 - 1.65 ≤ VCC < 1.8 V 50 - VCC ≥ 2.7 V 200 - 500 - Symbol Pin Name Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage VZT Full-scale transition voltage VFST Conversion time64 Sampling time65 Compare clock cycle66 - Ts Tcck - - - Unit bit LSB LSB mV mV VCC ≥ 2.7 V μs VCC ≥ 2.7 V 10 1000 μs ns 1.8 ≤ VCC < 2.7 V 1.8 ≤ VCC < 2.7 V 1.65 ≤ VCC < 1.8 V Tstt - - - 1.0 μs CAIN - - - pF Analog input resistance RAIN - - - - - - - 7.5 2.2 5.5 10.5 4 LSB - ANxx - - 5 μA - ANxx - AVRH V - AVRH - VCC V - AVRL VSS 2.7 VCC VSS - VSS V Reference voltage 1.8 ≤ VCC < 2.7 V 1.65 ≤ VCC < 1.8 V State transition time to operation permission Analog input capacity Interchannel disparity Analog port input leak current Analog input voltage Remarks kΩ VCC ≥ 2.7 V 1.8 ≤ VCC < 2.7 V 1.65 ≤ VCC < 1.8 V VCC ≥ 2.7V VCC < 2.7V 64 The conversion time is the value of sampling time (tS) + compare time (tC). The minimum conversion time is computed according to the following conditions: VCC ≥ 2.7 V sampling time=0.3 μs, compare time=0.7 μs 1.8 ≤ VCC < 2.7 V sampling time=1.2 μs, compare time=2.8 μs 1.65 ≤ VCC < 1.8 V sampling time=3.0 μs, compare time=7.0 μs Ensure that the conversion time satisfies the specifications of the sampling time (tS) and compare clock cycle (tCCK). For details of the settings of the sampling time and compare clock cycle, refer to "Chapter: A/D Converter" in "FM0+ Family Peripheral Manual Analog Macro Part". The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see the Peripheral Address Map. The base clock (HCLK) is used to generate the sampling time and the compare clock cycle. 65 The required sampling time varies according to the external impedance. Set a sampling time that satisfies (Equation 1). 66 The compare time (tC) is the result of (Equation 2). Document Number: 002-00233 Rev. *D Page 81 of 109 S6E1C Series ANxx Analog input pins REXT Comparator RAIN Analog signal source CAIN (Equation 1) tS ≥ (RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D Converter = 2.2 kΩ with 2.7 < VCC < 3.6 Input resistance of A/D Converter = 5.5 kΩ with 1.8 < VCC < 2.7 Input resistance of A/D Converter = 10.5 kΩ with 1.65 < VCC < 1.8 CAIN: Input capacitance of A/D Converter = 7.5 pF with 1.65 < VCC < 3.6 REXT: Output impedance of external circuit (Equation 2) tC=tCCK × 14 tC: Compare time tCCK : Compare clock cycle Document Number: 002-00233 Rev. *D Page 82 of 109 S6E1C Series Definitions of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Actual conversion characteristics Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) VSS Actual conversion characteristics AVRH VSS Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N VZT VFST VNT : : : : AVRH Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST – VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-00233 Rev. *D Page 83 of 109 S6E1C Series 11.6 USB Characteristics (VCC=3.0 V to 3.6 V, VSS=0 V, TA=- 40°C to +105°C) Parameter Input characteristics Symbol Pin Name Conditions Input H level voltage VIH - Input L level voltage VIL - Differential input sensitivity VDI - Differential common mode range VCM - Value Min 2.0 VSS – VCC + 0.3 Unit V Schematic Reference 1 1 0.8 V 0.2 - V 2 0.8 2.5 V 2 2.8 3.6 V 0.0 0.3 V 0.3 External pull-down Max 3 Output H level voltage VOH Output L level voltage VOL Crossover voltage VCRS - 1.3 2.0 V 4 resistance = 15 kΩ UDP0, External pull-up UDM0 resistance = 1.5 kΩ 3 Output Rising time tFR Full-speed 4 20 ns 5 characteristic Falling time tFF Full-speed 4 20 ns 5 Rising/Falling time matching tFRFM Full-speed 90 111.11 % 5 Output impedance ZDRV Full-speed 28 44 Ω 6 tLR Low-speed 75 300 ns 7 tLF Low-speed 75 300 ns 7 tLRFM Low-speed 80 125 % 7 Rising time Falling time Rising/Falling time matching Minimum differential input sensitivity [V] 1. The switching threshold voltage of single-end-receiver of USB I/O buffer is set as within VIL(Max)=0.8 V, VIH(Min)=2.0 V (TTL input standard). There is some hysteresis to lower noise sensitivity. 2. Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. 1.0 0.2 0.8 2.5 Common mode input voltage [V] Document Number: 002-00233 Rev. *D Page 84 of 109 S6E1C Series 3. The output drive capability of the driver is below 0.3 V at Low-state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 1.5 kΩ load) at high-state (VOH) 4. The cross voltage of the external differential output signal (D+ / D-) of USB I/O buffer is within 1.3 V to 2.0 V. D+ Max 2.0V VCRS specified range Min 1.3V D- 5. They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ±10% to minimize RFI emission. D+ 90% 90% 10% 10% DTrise Rising time Tfall Falling time Full-speed buffer Rs=27 Ω TxD+ CL=50 pF Rs=27 Ω TxDCL=50 pF 3-state enable 6. USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 33 Ω (recommendation value: 27 Ω) series resistor Rs. Document Number: 002-00233 Rev. *D Page 85 of 109 S6E1C Series Full-speed buffer Rs 28 Ω to 44 Ω equivalent impedance TxD+ Rs 28 Ω to 44 Ω equivalent impedance TxD- Mount it as external resistance. 3-state enable Rs series resistor 25 Ω to 30 Ω Series resistor of 27 Ω (recommendation value) must be added. And, use “resistance with an uncertainty of 5% by E24 sequence”. 7. They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. D+ 90% 90% 10% 10% DTrise Rising time Tfall Falling time See “Low-speed load (Compliance Load)” for conditions of external load. Document Number: 002-00233 Rev. *D Page 86 of 109 S6E1C Series ・ Low-Speed Load (Upstream Port Load) – Reference 1 Low-speed buffer Rs=27 Ω TxD+ Rpd CL=50 pF to 150 pF Rs=27 Ω TxDRpd 3-state enable CL=50 pF to 150 pF Rpd=15 kΩ ・ Low-Speed Load (Downstream Port Load) – Reference 2 Low-speed buffer Rs=27 Ω VTERM TxD+ CL=200 pF to 600 pF Rs=27 Ω TxD- CL=50 pF to 150 pF 3-state enable Document Number: 002-00233 Rev. *D Rpu=1.5 kΩ VTERM=3.6 V Page 87 of 109 S6E1C Series ・ Low-Speed Load (Compliance Load) Low-speed buffer Rs=27 Ω TxD+ CL=200 pF to 450 pF Rs=27 Ω TxDCL=200 pF to 450 pF 3-state enable Document Number: 002-00233 Rev. *D Page 88 of 109 S6E1C Series 11.7 Low-Voltage Detection Characteristics 11.7.1 Low-Voltage Detection Reset (TA=-40°C to +105°C) Parameter 67 68 Min 1.38 1.43 Value Typ 1.50 1.55 - - - 8160× tCYCP68 μs - - - 200 μs Symbol Conditions Detected voltage Released voltage VDL VDH Fixed67 LVD stabilization wait time TLVDW LVD detection delay time TLVDDL Max 1.60 1.65 Unit V V Remarks When voltage drops When voltage rises The value of low voltage detection reset is always fixed. tCYCP indicates the APB1 bus clock cycle time. Document Number: 002-00233 Rev. *D Page 89 of 109 S6E1C Series 11.7.2 Low-Voltage Detection Interrupt (TA=-40°C to +105°C) Parameter 69 Symbol Conditions Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH SVHI=00100 LVD stabilization wait time TLVDW - LVD detection delay time TLVDDL SVHI=00101 SVHI=00110 SVHI=00111 SVHI=01000 SVHI=01001 SVHI=01010 SVHI=01011 SVHI=01100 SVHI=01101 SVHI=01110 SVHI=01111 SVHI=10000 SVHI=10001 SVHI=10010 SVHI=10011 Min 1.56 1.61 1.61 1.66 1.66 1.70 1.70 1.75 1.75 1.79 1.79 1.84 1.84 1.89 1.89 1.93 2.30 2.39 2.39 2.48 2.48 2.58 2.58 2.67 2.67 2.76 2.76 2.85 2.85 2.94 2.94 3.04 Value Typ 1.70 1.75 1.75 1.80 1.80 1.85 1.85 1.90 1.90 1.95 1.95 2.00 2.00 2.05 2.05 2.10 2.50 2.60 2.60 2.70 2.70 2.80 2.80 2.90 2.90 3.00 3.00 3.10 3.10 3.20 3.20 3.30 - - Max 1.84 1.89 1.89 1.94 1.94 2.00 2.00 2.05 2.05 2.11 2.11 2.16 2.16 2.21 2.21 2.27 2.70 2.81 2.81 2.92 2.92 3.02 3.02 3.13 3.13 3.24 3.24 3.35 3.35 3.46 3.46 3.56 8160 × Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises μs tCYCP69 - - - 200 μs tCYCP represents the APB1 bus clock cycle time. Document Number: 002-00233 Rev. *D Page 90 of 109 S6E1C Series 11.8 Flash Memory Write/Erase Characteristics (VCC=1.65 V to 3.6 V, TA=- 40°C to +105°C) Value70 Parameter Sector erase time Large sector Small sector Min Typ Max - 1.1 2.7 Unit s - 0.3 0.9 Halfword (16-bit) write time - 30 528 μs Chip erase time - 4.5 11.7 s Remarks The sector erase time includes the time of writing prior to internal erase. The halfword (16-bit) write time excludes the system-level overhead. The chip erase time includes the time of writing prior to internal erase. Write/Erase Cycle and Data Hold Time 70 Write/Erase Cycle Data Hold Time (Year) 1,000 20 10,000 10 Remarks These values come from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at +85°C). The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write. Document Number: 002-00233 Rev. *D Page 91 of 109 S6E1C Series 11.9 Return Time from Low-Power Consumption Mode 11.9.1 Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC=1.65 V to 3.6 V, TA=-40°C to +105°C) Parameter Current Mode Mode to return Sleep mode Symbol Value each Run Mode High-speed CR Run mode Main Run mode PLL Run mode Low-speed CR Run mode Sub Run mode High-speed CR Run mode Low-speed CR Run mode Main Run mode Sub Run mode PLL Run mode High-speed CR Run mode Low-speed CR Run mode Sub Run mode Main Run mode PLL Run mode Timer mode Stop Mode RTC mode Deep Standby RTC mode Deep Standby Stop mode Max71 Typ Unit Remarks When High-speed CR is enabled When High-speed CR is enabled μs 4*HCLK 12*HCLK 13*HCLK μs 34+12*HCLK 72+13*HCLK μs 34+12*HCLK 72+13*HCLK μs 34+12*HCLK +tOSCWT 72+13*HCLK +tOSCWT μs 34+12*HCLK 72+13*HCLK μs 34+12*HCLK +tOSCWT 72+13*HCLK +tOSCWT μs 43 281 μs tICNT High-speed CR Run mode 72 72 Operation Example of Return from Low-Power Consumption Mode (by External Interrupt73) External interrupt Interrupt factor accept Active tICNT CPU Operation 71 72 73 Interrupt factor clear by CPU Start The maximum value depends on the condition of environment. tOSCWT: Oscillator stabilization time. External interrupt is set to detecting fall edge. Document Number: 002-00233 Rev. *D Page 92 of 109 S6E1C Series Operation Example of Return from Low-Power Consumption Mode (by Internal Resource Interrupt74) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start Notes: − The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual. − 74 When interrupt recovers, the operation mode that CPU recovers depends on the state before the Low-Power consumption mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual". Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Document Number: 002-00233 Rev. *D Page 93 of 109 S6E1C Series 11.9.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC=1.65 V to 3.6 V, TA=-40°C to +105°C) Parameter Current Mode High-speed CR Sleep mode Main Sleep mode PLL Sleep mode Max75 Unit 20 22 μs Low-speed CR Sleep mode 50 106 μs Sub Sleep mode 112 137 μs 20 22 μs Low-speed CR Timer mode 87 159 μs Sub Timer mode 148 209 μs 45 68 μs 43 281 μs High-speed CR Timer mode Main Timer mode PLL Timer mode Symbol Value Typ Mode to return High-speed CR Run mode Stop mode RTC mode Deep Standby RTC mode Deep Standby Stop mode tRCNT Remarks When High-speed CR is enabled When High-speed CR is enabled When High-speed CR is enabled When High-speed CR is enabled Operation Example of Return from Low-Power Consumption Mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation 75 Start The maximum value depends on the accuracy of built-in CR. Document Number: 002-00233 Rev. *D Page 94 of 109 S6E1C Series Operation Example of Return from Low Power Consumption Mode (by Internal Resource Reset76) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start Notes: − The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual. − When interrupt recovers, the operation mode that CPU recovery depends on the state before the Low-Power consumption mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual". − The time during the power-on reset/low-voltage detection reset is excluded. See "11.4.7 Power-on Reset Timing in 11.4 AC Characteristics in 11. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. 76 Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Document Number: 002-00233 Rev. *D Page 95 of 109 S6E1C Series 12. Ordering Information Package-Specific Features (see next table) Part number Flash [Kbyte] SRAM [Kbyte] USB2.0 I2 S S6E1C32D0AGV20000 S6E1C31D0AGV20000 128 16   64 12   128 16   64 12   128 16  64 12  128 16   64 12   128 16   64 12   128 16  64 12  32-pin 128 16  30-pin 128 16  64 12  128 16  64 12  128 16 64 12 128 16  64 12  128 16  64 12  128 16 64 12 S6E1C32C0AGV20000 S6E1C31C0AGV20000 S6E1C32B0AGP20000 S6E1C31B0AGP20000 S6E1C32D0AGN20000 S6E1C31D0AGN20000 S6E1C32C0AGN20000 S6E1C31C0AGN20000 S6E1C32B0AGN20000 S6E1C31B0AGN20000 64-pin 48-pin 32-pin 64-pin 48-pin S6E1C32B0AGU1H000 S6E1C12D0AGV20000 S6E1C11D0AGV20000 S6E1C12C0AGV20000 S6E1C11C0AGV20000 S6E1C12B0AGP20000 S6E1C11B0AGP20000 S6E1C12D0AGN20000 S6E1C11D0AGN20000 S6E1C12C0AGN20000 S6E1C11C0AGN20000 S6E1C12B0AGN20000 S6E1C11B0AGN20000 Document Number: 002-00233 Rev. *D 64-pin 48-pin 32-pin 64-pin 48-pin 32-pin Package (Tray) Plastic  LQFP (0.50 mm pitch), 64 pins (LQD064) Plastic  LQFP (0.50 mm pitch), 48 pins (LQA048) Plastic  LQFP (0.80 mm pitch), 32 pins (LQB032) Plastic  QFN64 (0.50 mm pitch), 64 pins (WNS064) Plastic  QFN48 (0.50 mm pitch), 48 pins (WNY048) Plastic  QFN32 (0.50 mm pitch), 32 pins (WNU032) Plastic  WLCSP30 (0.40 mm pitch), 30 pins (U4M030) * 7 inch reel only for this MPN Plastic  LQFP (0.50 mm pitch), 64 pins (LQD064) Plastic  LQFP (0.50 mm pitch), 48 pins (LQA048) Plastic  LQFP (0.80 mm pitch), 32 pins (LQB032) Plastic  QFN64 (0.50 mm pitch), 64 pins (WNS064) Plastic  QFN48 (0.50 mm pitch), 48 pins (WNY048) Plastic  QFN32 (0.50 mm pitch), 32 pins (WNU032) Page 96 of 109 S6E1C Series Package Feature Pin count Multi-function Serial Interface (UART/CSIO/I2C/I2S) 30 WLCSP 32 LQFP 32 QFN 48 LQFP 48 QFN 64 LQFP 64 QFN 30 32 48 64 4 ch. (Max) Ch.0/1/3 without FIFO Ch. 6 with FIFO 6 ch. (Max) 6 ch. (Max) Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO Ch.4/6/7 with FIFO Ch.4/6/7 with FIFO I2S: No I2S: 1 ch (Max) Ch. 6 with FIFO I2S: 2 ch (Max) Ch. 4/6 with FIFO External Interrupt 7 pins (Max), NMI x 1 9 pins (Max), NMI x 1 12 pins (Max), NMI x 1 I/O port 24 pins (Max) 38 pins (Max) 54 pins (Max) 12-bit A/D converter 6 ch. (1 unit) 8 ch. (1 unit) 8 ch. (1 unit) Smart Card Interface HDMI-CEC/ Remote Control Receiver No 1 ch.(Max) Ch.1 1 ch (Max) 2 ch (Max) Ch.0/1 13. Acronyms Acronym ADC ACK AHB ARM® CEC CMOS CPU CR CRC CSIO CSV CTS DTSC EOM FIFO GPIO HDMI HDMI-CEC I/F I2C, or IIC I2S, or IIS I/O IRQ LIN LVD MFS MSB MTB NMI Description analog-to-digital converter acknowledge AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus Advanced RISC Machine, a CPU architecture Consumer Electronics Control, a command and control interface over HDMI (High Definition Multimedia Interface) complementary metal oxide semiconductor central processing unit clock and reset cyclic redundancy check, an error-checking protocol clock synchronous serial interface clock supervisor clear to send, a flow control signal in some data communication interfaces descriptor system data transfer controller end of message first in, first out general-purpose input/output High Definition Multimedia Interface High Definition Multimedia Interface - Consumer Electronics Control, see CEC interface Inter-Integrated Circuit, a communications protocol Inter-IC (integrated circuit) Sound, a communications protocol input/output, see also GPIO interrupt request Local Interconnect Network, a communications protocol low-voltage detect multi-function serial most significant byte micro trace buffer non-maskable interrupt Document Number: 002-00233 Rev. *D Page 97 of 109 S6E1C Series Acronym NVIC OS OSC PLL PPG PWC PWM RAM RX RTS SPI SRAM SW-DP TX UART USB Description nested vectored interrupt controller operating system oscillator phase-locked loop programmable pulse generator pulse-width counter pulse-width modulator random access memory receive request to send, a flow control signal in some data communication interfaces Serial Peripheral Interface, a communications protocol static random access memory serial wire debug port transmit universal asynchronous receiver transmitter Universal Serial Bus Document Number: 002-00233 Rev. *D Page 98 of 109 S6E1C Series 14. Package Dimensions Package Type LQFP-32 Package Code LQB032 4 D D1 24 5 7 17 17 25 16 E1 6 32 8 e b 0.20 C A-B TOP VIEW 9 32 8 2 5 7 1 BOTTOM VIEW 0.10 C A-B D 3 0.20 C A-B D 25 4 9 1 16 E 5 7 3 24 D 8 2 9 θ A A' 0.10 C SEATING PLANE c b SECTION A-A' 0.25 10 SIDE VIEW SYM BOL DIM ENSIONS M IN . NOM . M AX. 1.60 A A1 0.05 b 0.32 c 0.13 0.15 0.35 0.43 0.18 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 32 LEAD LQFP 7.0X7.0X1.6 M M LQB032 REV*.* 002-13879 ** Document Number: 002-00233 Rev. *D Page 99 of 109 S6E1C Series Package Type LQFP-48 Package Code LQA048 4 D 5 7 D1 36 25 37 24 E1 24 37 13 48 E 5 7 3 36 25 4 6 48 13 1 12 e 1 12 2 5 7 0.10 C A-B D 3 0.20 C A-B D b 0.80 C A-B D 8 2 A θ A A' 0.80 C SYM BOL L1 0.25 L A1 c b 10 SECTION A-A' D IM EN SIONS M IN . N OM . M AX. 0.00 0.20 1.70 A A1 9 SEATING PLANE b 0.15 0.27 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC e 0.50 BSC E 9.00 BSC E1 7.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 48 LEAD LQFP 7.0X7.0X1.7 M M LQA048 REV** 002-13731 ** Document Number: 002-00233 Rev. *D Page 100 of 109 S6E1C Series Package Type LQFP-64 Package Code LQD064 4 D D1 48 5 7 33 33 32 49 48 32 49 17 64 5 7 E1 E 4 3 6 17 64 1 16 e 1 16 2 5 7 3 BOTTOM VIEW 0.1 0 C A-B D 0.2 0 C A-B D b 0.0 8 C A-B D 8 TOP VIEW A 2 9 A A' 0.0 8 C SEATING PLAN E L1 0.25 L A1 c b SECTION A-A' 10 SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. A 1. 70 A1 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E 12.00 BSC. E1 10.00 BSC. L 0.45 0.60 0.75 L1 0.30 0.50 0.70 PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 M M LQD064 Rev** 002-11499 ** Document Number: 002-00233 Rev. *D Page 101 of 109 S6E1C Series Package Type QFN-32 Package Code WNU032 C A B 0.10 D D2 A 24 17 0.10 C 2X 16 (ND-1)× e E C A B 0.10 25 E2 5 9 9 IND EX M A RK 8 32 8 b e B 0.10 C TOP VIEW BOTTOM VIEW 2X c 1 L 0.10 C A B 0.05 C 4 0.10 C A 0.08 C A1 C SEATING PLAN E 9 SID E VIEW DIM ENSIONS SYM BOL M IN. NOM . 0.80 A A1 0.05 0.00 D 5.00 BSC E 5.00 BSC b 0.20 0.25 D2 3.20 BSC E2 3.20 BSC e 0.50 BSC c 0.25 REF L M AX. 0.35 0.40 NOTE 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DIM ENSIONING AND TOLERANCIN 3. N IS THE TOTAL NU M BER OF TERM INALS. LLIZED TERM INAL AND IS M EASURED 4. DIM ENSION "b "APPLIES TO M ETA BETW EEN 0.15 AND 0.30m m FROM TERM INAL TIP.IF THE TERM INAL HAS THE OPTION AL RADIUS ON THE OTHER END OF THE TERM INAL. THE DIM ENSION "b "SHOULD NOT BE M EASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUM BER OF 0.30 C CONFORM S TO ASM E Y14.5-1994. TERM INALS ON D OR E SIDE. 6. M AX. PACKAGE W ARPAGE IS 0.05m m . 7. M AXIM UM ALLOW ABL E BURRS IS 0.076m m IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP W ILL BE LOCATED W ITHIN INDICATED ZONE. 9. BILATERAL COPLAN ARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS W ELL AS THE TERM INALS. 0.45 10. JEDEC SPEC IFICATION NO. REF : N/A PACKAGE OUTLINE, 32 LEAD QFN 5.00X5.00X0.80 M M WNU032 3.20X3.20 M M EPAD (SAWN) REV** 002-15907 ** Document Number: 002-00233 Rev. *D Page 102 of 109 S6E1C Series Package Type QFN-48 Package Code WNY048 0.15 D A D2 25 C A B 36 0.10 C 24 2X 37 0.15 (ND-1)× e E C A B E2 5 13 9 INDEX M ARK 8 48 12 B L b 0.10 C TOP VIEW 0.10 0.05 C A B C 4 BOTTOM VIEW 2X A 0.05 C A1 c 1 e SEATING PLANE 9 C SIDE VIEW NOTE DIMENSIONS SYMBOL M IN. NOM. MAX. 1. ALL DIMENSIONS ARE IN M ILLIMETERS. 2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTALNUM BER OF TERMINALS. A A1 0.80 0.00 D 7.00 BSC E b 0.05 7.00 BSC 0.18 0.25 D2 4.65 BSC E2 4.65 BSC e 0.50 BSC c 0.30 REF L 0.45 0.50 4. DIMENSION "b"APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETW EEN 0.15 AND 0.30m m FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALSON D OR E SIDE. 0.30 6. MAX. PACKAGE W ARPAGE IS 0.05m m. 7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP W ILLBE LOCATED W ITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT SINK SLUG AS W ELL AS THE TERMINALS. 0.55 10. JEDEC SPECIFICATION NO. REF : N/A PACKAGE OUTLINE, 48 LEAD QFN 7.00X7.00X0.80 M M WNY048 4.65X4.65 M M EPAD (SAWN) REV** 002-16422 ** Document Number: 002-00233 Rev. *D Page 103 of 109 S6E1C Series Package Type QFN-64 Package Code WNS064 D D2 A 33 0.15 C A B 49 0.15 48 0.10 C 32 2X (ND-1)× e E C A B E2 5 64 17 16 INDEX MARK 8 9 B e L b 0.10 C TOP VIEW 0.10 0.05 C A B C 4 BOTTOM VIEW 2X A 0.05 C A1 c 1 SEATING PLANE 9 C SIDE VIEW NOTE DIMENSIONS SYMBOL M IN. NOM. MAX. 1. ALL DIMENSIONS ARE IN M ILLIMETERS. 2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTALNUM BER OF TERMINALS. A A1 0.80 0.00 D 9.00 BSC E b 0.05 9.00 BSC 0.20 0.25 4. DIMENSION "b"APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETW EEN 0.15 AND 0.30m m FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALSON D OR E SIDE. 0.30 6. MAX. PACKAGE W ARPAGE IS 0.05m m. D2 7.20 BSC E2 7.20 BSC 8. PIN #1 ID ON TOP W ILLBE LOCATED W ITHIN INDICATED ZONE. e 0.50 BSC c 0.50 REF 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT SINK SLUG AS W ELL AS THE TERMINALS. L 0.35 0.40 7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS. 0.45 10. JEDEC SPECIFICATION NO. REF : N/A PACKAGE OUTLINE, 64 LEAD QFN 9.00X9.00X0.80 M M WNS064 7.20X7.20 M M EPAD (SAWN) REV** 002-16424 ** Document Number: 002-00233 Rev. *D Page 104 of 109 S6E1C Series Package Type Package Code WLCSP 30 U4M030 A D1 D eD INDEX M ARK 7 8 1 PIN A1 CORNER SE 2 eE E E1 3 4 5 0.03 C F B 2X E D C SD 0.03 C TOP VIEW B 30×φ b 2X A 7 0.05 C A B 6 BOTTOM VIEW A A2 DETAIL A 0.05 C A1 DETAIL A SIDE VIEW DIM ENSIONS NOTES SYM BOL M IN. NOM . A A1 0.164 2.690 BSC E 2.310 BSC D1 2.000 BSC E1 1.600 BSC MD 6 ME 5 n 30 φb 0.24 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 0.534 2. DIM ENSIONS AND TOLERANCES M ETHODS PER ASM E Y14.5-2009. THIS OUTLINE CONFORM S TO JEP95, SECTION 4.5. 0.224 D eD M AX. 0.27 0.400 BSC eE 0.40 BSC SD / SE 0.20 / 0 BSC 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010. 4. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYM BOL "M D"IS THE BALL M ATRIX SIZE IN THE "D" DIRECTION. SYM BOL "M E"IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. n IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX SIZE M D X M E. 6. DIM ENSION "b " IS M EASURED AT THE M AXIM UM BALL DIAM ETER IN A PLANE PARALLEL TO DATUM C. 0.30 7. "SD" AND "SE" ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . W HEN THERE IS AN ODD NUM BER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE"= 0. W HEN THERE IS AN EVEN NUM BER OF SOLDER BALLS IN THE OUTER ROW , "SD"= eD/2 AND "SE" = eE/2. 8. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK. M ETALLIZED M ARK IN DENTATION OR OTHER M EANS. 9. "+ "INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10. JEDEC SPECIFICATION NO. REF: N/A. PACKAGE OUTLINE, 30 BALL W LCSP 2.31X2.69X0.534 M M U4M 030 Rev** 002-18455 ** Document Number: 002-00233 Rev. *D Page 105 of 109 S6E1C Series 15. Errata This chapter describes the errata for S6E1C product family. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. 15.1 Part Numbers Affected Part Number S6E1C32D0AGV20000, S6E1C32C0AGV20000, S6E1C32B0AGP20000, S6E1C32D0AGN20000, S6E1C32C0AGN20000, S6E1C32B0AGN20000 S6E1C32B0AGU1H000 S6E1C31D0AGV20000, S6E1C31C0AGV20000, S6E1C31B0AGP20000, S6E1C31D0AGN20000, S6E1C31C0AGN20000, S6E1C31B0AGN20000 S6E1C12D0AGV20000, S6E1C12C0AGV20000, S6E1C12B0AGP20000, S6E1C12D0AGN20000, S6E1C12C0AGN20000, S6E1C12B0AGN20000 S6E1C11D0AGV20000, S6E1C11C0AGV20000, S6E1C11B0AGP20000, S6E1C11D0AGN20000, S6E1C11C0AGN20000, S6E1C11B0AGN20000 15.2 Qualification Status Product Status: In Production − Qual. 15.3 Errata Summary This table defines the errata applicability to available devices. Items Part Number Silicon Revision Fix Status [1] AHB Bus Matrix issue Refer to 15.1 Rev B Fixed in Rev C [2] Deep Standby Mode current consumption issue Refer to 15.1 Rev B, Rev C Next silicon is not planned. 15.4 Errata Detail 15.4.1 AHB Bus Matrix issue  PROBLEM DEFINITION The AHB Bus Matrix logic has two master interfaces (CPU and DSTC) and four slave interfaces (RAM, FLASH, AHB and APB). When two master interfaces (CPU and DSTC) access the same slave interface at the same time, and when the CPU is in wait cycle, an unnecessary access occurs during the wait cycle and the expected access occurs again after the unnecessary access.  PARAMETERS AFFECTED N/A  TRIGGER CONDITION(S) CPU and DSTC access the same slave interface at the same time.  SCOPE OF IMPACT DSTC cannot be used.  WORKAROUND DSTC must not use. Document Number: 002-00233 Rev. *D Page 106 of 109 S6E1C Series  FIX STATUS This issue is fixed in Rev C. 15.4.2 Deep Standby Mode current consumption issue  PROBLEM DEFINITION The current consumption does not decrease in Deep Standby Mode (Deep Standby RTC Mode and Deep Standby Stop Mode)  PARAMETERS AFFECTED N/A  TRIGGER CONDITION(S) MCU is in Deep Standby Mode and both MAINXC bits in SPSR and SUBXC bits in SUBOSC_CTL has not been cleared with 0b00 since power-on.  SCOPE OF IMPACT The current consumption does not decrease.  WORKAROUND Clear both MAINXC bits in SPSR and SUBXC bits in SUBOSC_CTL with 0b00. Please note: - Output pins become unstable state in a moment right after clearing these register bits with 0b00. - You can set these register bits to any value after they are cleared with 0b00.  FIX STATUS The user uses the workaround to prevent this issue. The next silicon fixing this issue is not planned. Document Number: 002-00233 Rev. *D Page 107 of 109 S6E1C Series Document History Document Title: S6E1C Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller Document Number: 002-00233 Revision ECN Orig. of Submission Change Date Description of Change ** 4896074 TEKA 08/31/2015 New Spec. *A 4955136 TEKA 10/9/2015 AC/DC characteristics updated. Typo fixed in “List of Pin Functions”. Added the frequency value of “Ta = - 10°C to + 105°C” on “11.4.3 Built-in CR Oscillation Characteristics”. Added the remark of “VCC < 0.2V” on “11.4.7 Power-on Reset Timing”. *B 5158709 YUKT 03/04/2016 Added the measure condition of ICC on “11.3.1 Current Rating”. Changed the package outlines to cypress format on “13. Package Dimensions”. Changed the package codes to cypress codes on “3. Pin Assignment” and “12. Ordering Information”. Consolidated the C Series of Cypress MCUs into one data sheet. Minor updates to grammar. Made table footnotes consectutive. Corrected navigational aids (cross reference link colors). Added front matter to data sheet to match Cypress corporate style. Added tables to differentiate parts in 2 Product Lineup and 2.1 Package Dependent Features. Removed full multiplexed signal names from 4 Pin Assignment drawings. Added hyperlinks to 5 List of Pin Functions. *C 5220682 MBGR 09/07/2016 10 Pin Status in Each CPU State: Changed several instances of pullup register to pull up resistor. Expanded 12 Ordering Information. Fixed typo in Memory Map. Updated logo. Removed WLCSP information. Updated 11.4.7 Power-on Reset Timing. Added 15 Erratta. Added 13 Acronyms. Updated “15 Errata”(Page 106) Updated the schematic for “11.4.7 Power-on Reset Timing”(Page 56) Updated “14. Package Dimensions” (Page 99-105) Modify expressions of channel numbers for USB, I2S (Page 1) *D 5453786 YSKA 04/13/2017 Added the Baud rate spec in “11.4.9 CSIO/SPI/UART Timing”.(Page 58, 60, 62, 64) Modify typo about Main oscillation (Page 41) Modified Real-Time Clock(RTC) in “3. Product Features in Detail” Deleted “second, or day of the week” in the Interrupt function.(Page 8) Added WLCSP package information(Page 1, 6, 6, 17, 19, 96, 97, 105) Deleted I2C slave related description(Page 4, 6, 38, 41, 76, 97) Document Number: 002-00233 Rev. *D Page 108 of 109 S6E1C Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic USB Controllers Wireless/RF Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/memory Microcontrollers Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 cypress.com/touch cypress.com/usb cypress.com/wireless ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-00233 Rev. *D April 13, 2017 Page 109 of 109
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