S6E2C2AL0AGL20000

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com FM4: S6E2C Series Microcontroller Datasheet 200 MHz Arm® Cortex®-M4F High-Performance MCU The FM4 S6E2C Series provides a highly integrated single chip solution with 200 MHz of CPU power, up to 2 Mbytes of dual banked high speed on chip flash memory, up to 256 Kbytes of on chip SRAM, and integrated peripheral features including IEEE 1588 compliant 10/100 base Ethernet, CAN, CAN-FD, USB and inverter control timers. S6E2C Series Features Digital Subsystem High Performance MCU Subsystem ◼ 675 CoreMark®, 200 MHz Arm® Cortex®-M4F CPU ◼ 365 µA/MHz active current with 2.7 V to 5.5 V operating voltage ◼ 3x Multi-Function Timers (MFT) ◼ 9x Programmable Pulse Generators (PPG) ◼ 16x Base Timers, 4x Quadrature Position/Revolution Counters (QPRC) ◼ Ultra-low power 1.0 µA real-time clock (RTC) operating current ◼ 1x Dual Timer, 2x CRC, and Watch Counter ◼ Up to 2 MB flash and 256 KB SRAM with 16 KB flash accelerator ◼ 16 channels of Multi-Function Serial (MFS) interfaces configurable as SPI, UART, I2C, or LIN ◼ Error-Correcting Code (ECC) support, hardware WDT1, lowvoltage detect, and clock supervisor blocks for safety-critical applications ◼ 2x USB, 2x CAN, CAN-FD, IEEE 1588 Ethernet, HighSpeed Quad-SPI (HS-QSPI), I2S, and External Bus Interfaces Analog Subsystem ◼ 3x independent 12-bit, 2-Msps ADCs with a 32-channel multiplexer input ◼ 2x dedicated 12-bit digital-to-analog converters (DACs) Cypress Semiconductor Corporation Document Number: 002-04980 Rev. *E • 198 Champion Court S6E2C Series Datasheet • San Jose, CA 95134-1709 • 408-943-2600 Revised May 10, 2023 S6E2C Series Ecosystem for Cypress FM4 MCUs Cypress provides a wealth of data at http://www.cypress.com to help you to select the right MCU for your design, and to help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for FM4 MCUs:  AN99235 ◼ Overview: Product Portfolio, Product Roadmap ◼ Product Selectors: FM4 MCUs ◼ Application notes: Cypress offers a large number of FM4 application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with FM4 family of MCUs are:  AN204468 - FM4 I2S USB MP3 Player Application 32-Bit Microcontroller FM4 Family: This application note describes the general structure of the I²S USB MP3Player software example, its single modules in detail and how it is used.  AN204471 - FM4 S6E2CC Series External Memory Programmer: This document describes use of the MCU Universal Programmer as an off-line programmer for Quad SPI flash memory programming on the S6E2CC Series SK.  AN203277 - FM 32-Bit Microcontroller Family Hardware Design Considerations: This application note reviews several topics for designing a hardware system around FM0+, FM3, and FM4 family MCUs. Subjects include power system, reset, crystal, and other pin connections, and programming and debugging interfaces.  AN202488 - FM4 MB9BF56x and S6E2HG Series MCU Servo Motor Speed Control: This document covers servo motor speed control solution on FM4 MCU - MB9BF56x and S6E2HG. Document Number: 002-04980 Rev. *E - FM4 S6E2HG Series MCU - 16-Bit PWM Using a Base Timer: Cypress FM4 Family of 32-bit Arm® Cortex®-M4 Microcontrollers FM4 S6E2H Series Motor Control Arm® Cortex®-M4 MCU  AN202487 - Differences Among FM0+, FM3, and FM4 32Bit Microcontrollers: Highlights the peripheral differences in Cypress’s FM family MCUs. It provides dedicated sections for each peripheral and contains lists, tables, and descriptions of peripheral feature and register differences.  AN204438 - How to Setup Flash Security for FM0+, FM3 and FM4 Families: This application note describes how to setup the Flash Security for FM0+, FM3, and FM4 devices ◼ Development kits:  FM4-U120-9B560 - Arm® Cortex®-M4 MCU Starter Kit with USB and CMSIS-DAP  FM4-216-ETHERNET Arm® Cortex®-M4 MCU Development Kit with Ethernet, CAN and USB Host  FM4-176L-S6E2CC-ETH - Arm® Cortex®-M4 MCU Starter Kit with Ethernet and USB Host  FM4-176L-S6E2GM - Arm® Cortex®-M4 MCU Pioneer Kit with Ethernet and USB Host ◼ Peripheral Manuals S6E2C Series Datasheet Page 2 of 200 S6E2C Series Table of Contents S6E2C Series Features................................................... 1 1. Block Diagram ..................................................... 4 2. Product Lineup .................................................... 5 3. Detailed Device Features .................................... 7 4. Pin Assignments ............................................... 12 5. Pin Descriptions ................................................ 16 6. I/O Circuit Type .................................................. 53 7. Handling Precautions........................................ 61 7.1 Precautions for Product Design ........................ 61 7.2 Precautions for Package Mounting ................... 62 7.3 Precautions for Use Environment ..................... 64 8. Handling Devices............................................... 65 9. Memory Size ...................................................... 68 10. Memory Map ...................................................... 68 11. Pin Status in Each CPU State ........................... 74 12. Electrical Characteristics.................................. 82 12.1 Absolute Maximum Ratings .............................. 82 12.2 Recommended Operating Conditions ............... 84 12.3 DC Characteristics ............................................ 89 12.3.1 Current Rating ............................................... 89 12.3.2 Pin Characteristics ......................................... 99 12.4 AC Characteristics .......................................... 101 12.4.1 Main Clock Input Characteristics ................. 101 12.4.2 Sub Clock Input Characteristics ................... 102 12.4.3 Built-In CR Oscillation Characteristics ......... 102 12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL) .... 103 12.4.5 Operating Conditions of USB/Ethernet PLL・I2S PLL (in the Case of Using Main Clock for Input Clock of PLL) ............................................... 103 12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) ................................................ 104 12.4.7 Reset Input Characteristics .......................... 104 12.4.8 Power-On Reset Timing............................... 105 12.4.9 GPIO Output Characteristics ....................... 106 Document Number: 002-04980 Rev. *E 12.4.10 12.4.11 12.4.12 12.4.13 12.4.14 External Bus Timing ..................................... 107 Base Timer Input Timing .............................. 118 CSIO (SPI) Timing ....................................... 119 External Input Timing ................................... 152 Quadrature Position/Revolution Counter Timing ................................................................... 153 12.4.15 I2C Timing .................................................... 155 12.4.16 SD Card Interface Timing ............................. 157 12.4.17 ETM/ HTM Timing ........................................ 159 12.4.18 JTAG Timing ................................................ 160 12.4.19 Ethernet-MAC Timing ................................... 161 12.4.20 I2S Timing..................................................... 166 12.4.21 High-Speed Quad SPI Timing ...................... 171 12.5 12-bit A/D Converter ....................................... 173 12.6 12-bit D/A Converter ....................................... 176 12.7 USB Characteristics ........................................ 177 12.8 Low-Voltage Detection Characteristics ........... 181 12.8.1 Low-Voltage Detection Reset ....................... 181 12.8.2 Interrupt of Low-Voltage Detection ............... 181 12.9 MainFlash Memory Write/Erase Characteristics182 12.10 Dual Flash Memory Write/Erase Characteristics182 12.11 Standby Recovery Time .................................. 183 12.11.1 Recovery Cause: Interrupt/WKUP ................ 183 12.11.2 Recovery Cause: Reset ............................... 185 13. Ordering Information ....................................... 187 14. Acronyms ......................................................... 191 15. Package Dimensions ....................................... 192 16. Major Changes ................................................. 196 Sales, Solutions, and Legal Information ................... 200 Products ...................................................................... 200 Cypress Developer Community ................................. 200 Technical Support ....................................................... 200 S6E2C Series Datasheet Page 3 of 200 S6E2C Series 1. Block Diagram S6E2C TRSTX,TCK, TDI,TMS TDO SWJ-DP ETM/HTM* TRACEDx, TRACECLK TPIU/ETB* ROM Table SRAM0 96/144/192 Kbytes SRAM1 32 Kbytes Cortex-M4　Core I @200 MHz(Max) D FPU SRAM2 32 Kbytes MPU NVIC Multi-layer AHB (Max 200 MHz) Sys AHB-APB Bridge: APB0(Max 100 MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) CSV MainFlash I/F MainFlash/DualFlash 2 Mbytes(1M+1M)/ 1.5 Mbytes(1M+0.5M)/ 1 Mbytes(MainOnly) Trace Buffer (16 Kbytes) Security DualFlash I/F USB2.0 (Host/ Device) USB2.0 (Host/ Device) PHY USBVCC0 UDP0,UDM0 UHCONX0 PHY USBVCC1 UDP1,UDM1 UHCONX1 DMAC 8ch. CLK DSTC CR 100 kHz CR 4 MHz PLL TX1,RX1 CAN ch.2 TX2,RX2 VBAT Domain Sub Osc I2S 1unit AHB-AHB Bridge (Slave) X0A X1A Main Osc TX0,RX0 CAN ch.1 PRG-CRC Accelerator Source Clock X0 X1 CAN ch.0 GPIO MODE-Ctrl Unit 1 Unit 2 AINx BINx ZINx FRCK0 QPRC 4ch. 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x Waveform Generator 3ch. 16-bit PPG 3ch. Multi-function Timer × 3 VBAT VWAKEUP VREGCTL RTCCO, SUBOUT VBAT Domain Real-Time Clock Port Ctrl. 12-bit D/A Converter 2units Document Number: 002-04980 Rev. *E S_DATAx S_CD,S_WP Q_IOx A/D Activation Compare 6ch. IC0x SD-CARD I/F ETHVCC E_TXx, E_RXx, E_MDx S_CLK,S_CMD Hi-Speed Quad SPI AHB-APB Bridge : APB1 (Max 200 MHz) TIOBx . . . PFx MD0, MD1 Q_SCK, Q_CSx Base Timer 16-bit 32ch./ 32-bit 16ch. MADx External Bus I/F MADATAx MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX CAN Prescaler AHB-APB Bridge : APB2 (Max 100 MHz) ANxx Ethernet-MAC ch.0 AHB-AHB Bridge (Master) 12-bit A/D Converter Unit 0 ADTGx TIOAx P0x, P1x, PIN-Function-Ctrl CROUT AVCC, AVSS, AVRH, AVRL I2SMCLK, I2SWS, I2SCK I2SDI I2SDO USB Clock Ctrl PLL I2S Clock Ctrl PLL Power-On Reset LVD Ctrl LVD IRQ-Monitor Regulator C CRC Accelerator Watch Counter Deep Standby Ctrl WKUPx Peripheral Clock Gating Low-speed CR Prescaler External Interrupt Controller 32-pin + NMI INTx NMIX Multi-function Serial I/F 16ch. (with FIFO ch.0 to ch.7) HW flow control(ch.4,5) SCKx SINx SOTx CTSx RTSx S6E2C Series Datasheet Page 4 of 200 S6E2C Series 2. Product Lineup Here is the information used in the tables below: S6E2 C C 9 J0AGV 2000A Package Identifier Memory Size Product Feature Set C Series Cypress FM 4 MCU Memory Size Memory Size On-chip flash memory On-chip SRAM SRAM0 SRAM1 SRAM2 S6E2Cx8 1024 Kbytes 128 Kbytes 64 Kbytes 32 Kbytes 32 Kbytes S6E2Cx9 1536 Kbytes 192 Kbytes 128 Kbytes 32 Kbytes 32 Kbytes S6E2CxA 2048 Kbytes 256 Kbytes 192 Kbytes 32 Kbytes 32 Kbytes Package Dependent Features Feature Pin count and package type High-speed quad SPI External bus interface I2 S I/O ports 12-bit A/D converter H0AGV 144 LQFP: LQS144 (0.5 mm pitch) N/A Addr: 25-bit (Max), Data: 8-/16-bit CS: 8 (Max), SRAM, NOR flash NAND flash 4-bit ETM/HTM N/A 120 (Max) 24 ch (3 units) J0AGV 176 LQFP: LQP176 (0.5 mm pitch) J0AGB 192 BGA: LBE192 (0.8 mm pitch) 1 unit Addr: 25-bit (Max), Data: 8-/16-bit CS: 9 (Max), SRAM, NOR flash, NAND flash SDRAM 8-bit ETM/HTM 1 unit 152 (Max) 32 ch (3 units) L0AGL 216 LQFP: LQQ216 (0.4 mm pitch) Addr: 25-bit (Max), Data: 8-/16-/32-bit CS: 9 (Max), SRAM, NOR flash, NAND flash, SDRAM 16-bit ETM/HTM 190 (Max) Note: − See 15 Package Dimensions for detailed information on each package. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 5 of 200 S6E2C Series Product Feature Set Feature S6E2CC CPU Freq. Power supply voltage range USB2.0 (device/host) Ethernet-MAC S6E2C4 S6E2C3 S6E2C2 Cortex-M4F, MPU, NVIC 128 ch 200 MHz 2.7V to 5.5V 2 ch N/A 2 ch 2 ch 1ch.(Max) MII: 1 ch N/A N/A N/A /RMII: 1 ch (Max) 2 ch (Max) 2 ch (Max) N/A N/A 1 ch 1 ch N/A N/A 8ch 256 ch 16ch (Max) ch 0 to ch 7：FIFO, ch 8 to ch 15：No FIFO S6E2C1 N/A N/A N/A N/A 16 ch (Max) MF timer CAN CAN-FD (non-ISO CAN FD) DMAC DSTC Multi-function serial interface (UART/CSIO/LIN/I2C) Base timer (PWC/Reload timer/PWM/PPG) A/D activation 6 ch compare Input capture 4 ch Free-run timer 3 ch Output compare 6 ch Waveform generator 3 ch PPG 3 ch SD card interface QPRC Dual timer Real-time clock Watch counter CRC accelerator Watchdog timer External interrupts 12-bit D/A converter CSV (clock supervisor) LVD (low-voltage detector) High-speed Built-in CR Low-speed Debug function Unique ID 2 ch 1ch.(Max) MII: 1 ch /RMII: 1 ch (Max) 2 ch (Max) 1 ch S6E2C5 3 units (Max) 1 unit 4 ch (Max) 1 unit 1 unit 1 unit Yes (fixed, programmable) 1 ch (SW) + 1 ch (HW) 32 pins (Max)+ NMI × 1 2 units (Max) Yes 2 ch 4 MHz 100 kHz SWJ-DP/ETM/HTM Yes Notes: − Because of package pin limitations, not all functions within the device can be brought out to external pins. You must carefully work out the pin allocation needed for your design. You must use the port relocate function of the I/O port according to your function use. − See 12.4.3 Built-In CR Oscillation Characteristics for the accuracy of the built-in CR. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 6 of 200 S6E2C Series 3. Detailed Device Features Devices in the S6E2C Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the Arm Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that are described in this datasheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part (002-04856)." 32-bit Arm Cortex-M4F Core External Bus Interface ◼ Processor version: r0p1 ◼ Supports SRAM, NOR, NAND flash and SDRAM device ◼ Up to 200 MHz frequency operation ◼ Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) ◼ FPU built-in ◼ 8-/16-/32-bit data width ◼ Support DSP instructions ◼ Up to 25-bit address bus ◼ Memory protection unit (MPU): improves the reliability of an ◼ Maximum Access size: 256M byte embedded system ◼ Integrated nested vectored interrupt controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels ◼ 24-bit system timer (Sys Tick): system timer for OS task management ◼ Supports address/data multiplexing ◼ Supports external RDY function USB Interface (Max two channels) The USB interface is composed of a device and a host. ◼ USB device On-chip Memories  USB 2.0 Full-speed supported 6 EndPoint supported • EndPoint 0 is control transfer • EndPoint 1, 2 can be selected bulk-transfer, interrupttransfer or isochronous-transfer • EndPoint 3 to 5 can select bulk-transfer or interrupttransfer • EndPoint 1 to 5 comprise double buffer  The size of each endpoint is as follows. • Endpoint 0, 2 to 5: 64 byte • EndPoint 1: 256 byte  Max ◼ Flash memory This series is based on two independent on-chip flash memories.  Up to 2048 Kbytes flash accelerator system with 16 Kbytes trace buffer memory  Read access to flash memory that can be achieved without wait-cycle up to an operating frequency of 72 MHz. Even at the operating frequency more than 72 MHz, an equivalent single cycle access to flash memory can be obtained by the flash accelerator system.  Security function for code protection  Built-in ◼ USB host  USB2.0 ◼ SRAM Full-Speed/Low-Speed supported interrupt-transfer, and isochronous-transfer  Bulk-transfer, This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to the I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to system bus of Cortex-M4F core. support Device connected/dis-connected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet length supported  Wake-up function supported  USB  SRAM0: up to 192 Kbytes 32 Kbytes  SRAM2: 32 Kbytes  SRAM1: Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 7 of 200 S6E2C Series ◼ I2 C CAN Interface (Max two channels)  Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported  Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported ◼ Compatible with CAN specification 2.0A/B ◼ Maximum transfer rate: 1 Mbps ◼ Built-in 32-message buffer DMA Controller (Eight Channels) CAN-FD Interface (One channel) ◼ Compatible with CAN Specification 2.0A/B DMA controller has an independent bus, so the CPU and DMA controller can process simultaneously. ◼ Maximum transfer rate: 5 Mbps ◼ Eight independently configured and operated channels ◼ Message buffer for receiver: up to 192 messages ◼ Transfer can be started by software or request from the built- ◼ Message buffer for transmitter: up to 32 messages ◼ CAN with flexible data rate (non-ISO CAN FD) in peripherals ◼ Transfer address area: 32-bit (4 GB) ◼ Transfer mode: Block transfer/Burst transfer/Demand ◼ Notes:  CAN FD cannot communicate between non-ISO CAN FD and ISO CAN FD, because non-ISO CAN FD and ISO CAN FD are different frame format.  About the problem of "non-ISO CAN FD", see the White Paper from CiA(CAN in Automation). http://www.cannewsletter.org/engineering/standardization/141222_canfd-and-crc-issued_white-paper_bosch Multi-function Serial Interface (Max 16 Channels) ◼ Separate 64 byte receive and transmit FIFO buffers for channels 0 to 7. ◼ Operation mode is selectable for each channel from the following:  UART  CSIO (SPI)  LIN  I 2C transfer ◼ Transfer data type: bytes/half-word/word ◼ Transfer block count: 1 to 16 ◼ Number of transfers: 1 to 65536 DSTC (Descriptor System Data Transfer Controller; 256 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor that has already been constructed on the memory, can access directly the memory/peripheral device and perform the data-transfer operation. It supports the software activation, the hardware activation, and the chain activation functions. ◼ UART  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detect functions available (parity errors, framing errors, and overrun errors) ◼ CSIO (SPI)  Full-duplex double buffer dedicated baud rate generator  Overrun error detect function available  Serial chip select function (ch 6 and ch 7 only)  Supports high-speed SPI (ch 4 and ch 6 only)  Data length 5 to 16-bit  Built-in A/D Converter (Max 32 Channels) ◼ 12-bit A/D Converter  Successive approximation type three units  Conversion time: 0.5 μs at 5 V  Priority conversion available (priority at two levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for priority conversion: 4 steps)  Built-in D/A Converter (Max two channels) ◼ R-2R type ◼ 12-bit resolution ◼ LIN  LIN protocol Rev.2.1 supported double buffer  Master/slave mode supported  LIN break field generation (can change to 13- to 16-bit length)  LIN break delimiter generation (can change to 1- to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors)  Full-duplex Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 8 of 200 S6E2C Series Base Timer (Max 16 channels) Real-Time Clock (RTC) Operation mode is selected from the following for each channel: The real-time clock can count year, month, day, hour, minute, second, or day of the week from 00 to 99. ◼ 16-bit PWM timer ◼ Interrupt function with specifying date and time (year/month/day/hour/minute) is available. This function is also available by specifying only year, month, day, hour, or minute. ◼ 16-bit PPG timer ◼ 16-/32-bit reload timer ◼ Timer interrupt function after set time or each set time. ◼ 16-/32-bit PWC timer ◼ Capable of rewriting the time with continuing the time count. General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals; moreover, the port relocate function is built in. It can set the I/O port to which the peripheral function can be allocated. ◼ Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC; Max four channels) ◼ Capable of reading pin level directly The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. It is also possible to use up/down counter. ◼ Built-in port-relocate function ◼ The detection edge of the three external event input pins ◼ Capable of pull-up control per pin ◼ Up to 120 high-speed general-purpose I/O ports in 144-pin package AIN, BIN and ZIN is configurable. ◼ 16-bit position counter ◼ 16-bit revolution counter ◼ Some pins 5 V tolerant I/O. See "5. Pin Descriptions" and "6. I/O Circuit Type" for the corresponding pins. ◼ Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) Multi-function Timer (Max three units) ◼ 16-bit free-run timer × 3 ch/unit The dual timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the following for each channel: ◼ Input capture × 4 ch/unit ◼ Free-running ◼ Output compare × 6 ch/unit ◼ Periodic (= Reload) ◼ A/D activation compare × 6 ch/unit ◼ One shot The multi-function timer is composed of the following blocks: Minimum resolution: 5.00 ns ◼ Waveform generator × 3 ch/unit Watch Counter ◼ 16-bit PPG timer × 3 ch/unit The following functions can be used to achieve the motor control: The watch counter is used for wake up from low-power consumption mode. It is possible to select the main clock, sub clock, built-in High-speed CR clock, or built-in low-speed CR clock as the clock source. ◼ PWM signal output function ◼ Interval timer: up to 64 s (max) with a sub clock of ◼ DC chopper waveform output function 32.768 kHz ◼ Dead time function External Interrupt Controller Unit ◼ Input capture function ◼ External interrupt input pin: Max 32 pins ◼ A/D convertor activate function ◼ Include one non-maskable interrupt (NMI) ◼ DTIF (motor emergency stop) interrupt function Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 9 of 200 S6E2C Series Watchdog Timer (Two channels) ◼ Built-in dedicated descriptor-system DMAC A watchdog timer can generate interrupts or a reset when a time-out value is reached. ◼ Built-in 2 Kbytes transmit FIFO and 2 Kbytes receive FIFO. This series consists of two different watchdogs: a "hardware" watchdog and a "software" watchdog. The hardware watchdog timer is clocked by low-speed internal CR oscillator. The hardware watchdog is thus active in any power saving mode except RTC mode and Stop mode. Cyclic Redundancy Check (CRC) Accelerator The CRC accelerator helps to verify data transmission or storage integrity. ◼ Compliant IEEE1588-2008 (PTP) I2S (Inter-IC Sound Bus) Interface (TX x one channel, RX x one channel) ◼ Supports three transfer protocols  I2S17  Left justified mode  Separate clock generation block for flexible system integration options  DSP CCITT CRC16 and IEEE-802.3 CRC32 are supported. ◼ Master/slave mode selectable ◼ CCITT CRC16 generator polynomial: 0x1021 ◼ RX Only, TX Only or TX and RX simultaneous operation ◼ IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7 selectable ◼ Word length is programmable from 7-bits to 32-bits ◼ RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66 words x 32-bits) Programmable Cyclic Redundancy Check (PRGCRC) Accelerator ◼ DMA, interrupts, or polling based data transfer supported The CRC accelerator helps a verify data transmission or storage integrity. High-speed Quad SPI CCITT CRC16, IEEE-802.3 CRC32 and generating polynomial are supported. ◼ CCITT CRC16 generator polynomial: 0x1021 ◼ IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7 ◼ Generating polynomial Up to 66 MHz clock rates for very fast data transfers to and from SPI compatible devices. Up to 256 Mbytes of memory mapped address space. ◼ Single data rate (SDR) ◼ Supports single, dual, and quad data modes ◼ Built-in direct mode and command sequencer mode  Direct SD Card Interface It is possible to use the SD card that conforms to the following standards. ◼ Part 1 Physical Layer Specification version 3.01 Clock and Reset ◼ Part E1 SDIO Specification version 3.00 ◼ Part A2 SD Host Controller Standard Specification version 3.00 ◼ 1-bit or 4-bit data bus mode: Access by use of transmission FIFO/reception FIFO (up to 16 word x 32 bit)  Command sequencer mode: Automatic access assigned to external device area. ◼ Clocks Five clock sources (two external oscillators, two internal CR oscillators, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz clock: 30 kHz to 100 kHz  High-speed internal CR clock: 4 MHz  Low-speed internal CR clock: 100 kHz  Main PLL Clock  Sub Ethernet-MAC ◼ Compliant with IEEE802.3 specification ◼ 10 Mbps/100 Mbps data transfer rates supported ◼ MII/RMII for external PHY device supported. ◼ MII: Max one channel ◼ RMII: Max one channel ◼ Full-duplex and half-duplex mode supported. ◼ Resets  Reset requests from INITX pin on reset  Software reset  Watchdog timer reset  Low-voltage detector reset  Clock supervisor reset  Power ◼ Wake-ON-LAN supported Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 10 of 200 S6E2C Series Clock Supervisor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. ◼ External OSC clock failure (clock stop) is detected, reset is asserted. ◼ External OSC frequency anomaly is detected, interrupt or reset is asserted. VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used. ◼ RTC Low-Voltage Detector (LVD) This Series include two-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, the low-voltage detector function generates an interrupt or reset. ◼ 32-kHz oscillation circuit ◼ Power-on circuit ◼ Back up register: 32 bytes ◼ Port circuit ◼ LVD1: error reporting via interrupt Debug ◼ LVD2: auto-reset operation ◼ Serial wire JTAG debug port (SWJ-DP) Low-power Consumption mode ◼ Embedded trace macrocells (ETM) provide comprehensive Six low power consumption modes are supported. debug and trace facilities. ◼ Sleep ◼ AHB trace macrocells (HTM) ◼ Timer Unique ID ◼ RTC Unique value of the device (41-bit) is set. ◼ Stop ◼ Deep standby RTC (selectable from with/without RAM retention) ◼ Deep standby stop (selectable from with/without RAM retention) Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. Power Supply ◼ Five power supplies  Wide range voltage: VCC = 2.7 V to 5.5 V  Power supply for USB ch 0 I/O: USBVCC0 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for USB ch 1 I/O: USBVCC1 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for Ethernet-MAC I/O: ETHVCC = 3.0 V to 5.5 V (when Ethernet is used.) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for VBAT: VBAT = 1.65 V to 5.5 V Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 11 of 200 S6E2C Series 4. Pin Assignments LQS144 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 12 of 200 S6E2C Series LQP176 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 13 of 200 S6E2C Series LQQ216 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 14 of 200 S6E2C Series LBE192 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 15 of 200 S6E2C Series 5. Pin Descriptions List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. LQP176 LQS144 LBE192 Pin Name 1 1 1 C1 VCC Alternate Pin Functions RTO20_0 (PPG20_0) RTO21_0 (PPG20_0) RTO22_0 (PPG22_0) RTO23_0 (PPG22_0) RTO24_0 (PPG24_0) SIN1_0 2 2 2 B2 PA0 3 3 3 C2 PA1 4 4 4 C3 PA2 5 5 5 D5 PA3 6 6 6 D2 PA4 7 7 7 D1 PA5 8 8 8 D3 PA6 9 9 9 D4 PA7 10 10 - E2 P50 SCS72_0 11 11 - E3 P51 SCS73_0 12 12 - E4 P52 13 - - - P53 14 13 10 E5 PA8 15 14 11 F1 PA9 16 15 12 F2 PAA 17 18 16 17 13 14 F3 F4 PAB PAC RTO02_1 (PPG02_1) RTO03_1 (PPG02_1) SIN7_0 SOT7_0 (SDA7_0) SCK7_0 (SCL7_0) SCS70_0 SCS71_0 19 - - - P54 SIN15_1 20 - - - P55 21 - - - P56 22 - - - P57 23 18 15 F5 PAD 24 19 16 F6 PAE ADTG_0 25 26 20 - 17 - G2 - PAF P58 SIN3_0 SIN11_1 Document Number: 002-04980 Rev. *E I/O Circuit Type Pin State Type LQQ216 Pin Number SOT1_0 (SDA1_0)) SCK1_0 (SCL1_0) SOT15_1 (SDA15_1) SCK15_1 (SCL15_1) IC00_1 SCK3_0 (SCL3_0) - G K TIOA8_0 AIN2_0 INT00_0 TIOA9_0 BIN2_0 MADATA01_0 G I TIOA10_0 ZIN2_0 MADATA02_0 G I TIOA11_0 MADATA03_0 G I TIOA12_0 MADATA04_0 G I RTO25_0 (PPG24_0) TIOA13_0 G K DTTI2X_0 MADATA06_0 E I IC20_0 MADATA07_0 E I RTO00_1 (PPG00_1) RTO01_1 (PPG00_1) INT01_0 MADATA00_0 - MADATA05_0 TIOA8_2 MADATA16_0 E I TIOB8_2 MADATA17_0 E I TIOA9_2 MADATA18_0 E I TIOB9_2 MADATA19_0 E I IC21_0 INT02_0 I Q IC22_0 MADATA09_0 N I IC23_0 IC23_0 MADATA10_0 N I RX0_0 TX0_0 RTO04_1 (PPG04_1) RTO05_1 (PPG04_1) FRCK2_0 TIOB8_0 INT03_0 AIN3_0 MADATA11_0 MADATA12_0 E E K I TIOA10_2 INT00_2 MADATA20_0 E K TIOB10_2 MADATA21_0 E I DTTI0X_1 TIOB0_1 MADATA22_0 E I TIOB1_1 MADATA23_0 E I TIOB9_0 BIN3_0 MADATA13_0 N I TIOB10_0 ZIN3_0 MADATA14_0 N I INT16_0 TIOB2_1 MADATA15_0 MADATA24_0 INT02_2 I E K K SOT3_0 (SDA3_0) TIOB11_0 IC01_1 S6E2C Series Datasheet WKUP1 MADATA08_0 Page 16 of 200 S6E2C Series LQP176 LQS144 LBE192 Pin Name 27 - - - P59 28 - - - P5A 29 30 21 18 G3 P5B P08 31 22 19 G4 P09 32 23 20 G5 P0A ADTG_1 33 - - - P5C TIOA11_2 34 35 36 37 38 39 40 41 42 43 44 24 25 26 27 28 29 30 31 32 33 34 21 22 23 24 25 26 27 28 29 G6 H4 H2 J1 H3 H1 H5 H6 J5 J4 J3 P30 P31 P32 P33 P34 VCC VSS P35 P36 P37 P38 45 35 30 J2 46 36 31 47 37 48 I/O Circuit Type Pin State Type LQQ216 Pin Number Alternate Pin Functions MADATA26_0 E I TIOB5_1 TIOB12_0 MADATA27_0 INT17_0 MDQM0_0 E E I K TIOB13_0 INT18_0 MDQM1_0 E K AIN2_1 MCLKOUT_0 L I E I E E L L L L L L E K I K I K K K K I G K G K G K K RTCCO_1 SUBOUT_1 RX0_1 TX0_1 BIN2_1 FRCK0_0 IC03_0 SCK14_0 (SCL14_0) MADATA28 _0 TIOA13_2 TIOB13_2 INT19_0 ZIN2_1 INT00_1 INT03_2 MDQM3_0 S_DATA1_0 S_DATA0_0 S_CLK_0 MDQM2_0 I2SCK0_0 IC02_0 IC01_0 IC00_0 ADTG_2 INT01_1 INT02_1 INT03_1 DTTI0X_0 S_CMD_0 S_DATA3_0 S_DATA2_0 S_WP_0 P39 SIN2_1 RTO00_0 (PPG00_0) TIOA0_1 AIN3_1 S_CD_0 TIOB4_1 K1 P3A SOT2_1 (SDA2_1) RTO01_0 (PPG00_0) TIOA1_1 BIN3_1 MAD23_0 IC03_1 32 K2 P3B SCK2_1 (SCL2_1) RTO02_0 (PPG02_0) TIOA2_1 ZIN3_1 MAD22_0 I 38 33 K3 P3C SIN13_0 RTO03_0 (PPG02_0) TIOA3_1 INT19_1 MNCLE_0 E INT16_1 MADATA25_0 INT17_1 TIOB3_1 INT18_1 IC02_1 MAD21_0 SOT11_1 (SDA11_1) SCK11_1 (SCL11_1) FRCK0_1 SIN14_0 SOT14_0 (SDA14_0) G 49 39 34 K4 P3D TIOA4_1 MAD20_0 MNWEX_0 G I 50 40 35 L1 P3E TIOA5_1 MAD19_0 MNREX_0 G I 51 41 - L2 P5D INT01_2 MADATA29_0 I2SMCLK0_0 E K 52 42 - L3 P5E MADATA30_0 I2SDO0_0 E I Document Number: 002-04980 Rev. *E SOT13_0 (SDA13_0) SCK13_0 (SCL13_0) SIN10_1 SOT10_1 (SDA10_1) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) TIOB11_2 TIOA12_2 S6E2C Series Datasheet MNALE_0 MAD24_0 I2SDI0_0 Page 17 of 200 S6E2C Series M2 P5F 54 55 44 45 36 37 M1 N1 VSS VCC 56 46 38 N2 P40 57 47 39 N3 P41 58 48 40 M3 P42 59 49 41 L4 P43 60 50 42 M4 P44 61 51 43 N4 P45 62 63 64 65 52 53 54 - 44 45 46 - P2 P3 P4 - C VSS VCC P4A 66 - - - P4B 67 - - - P4C 68 69 - - - P4D P4E 70 55 47 L5 P7D 71 72 73 74 75 76 77 78 79 80 56 57 58 59 60 61 62 63 64 65 48 49 50 51 52 53 54 55 M5 N5 P5 P6 P8 N6 M6 K5 K6 L6 P7E INITX P46 P47 VBAT P48 P49 PF0 PF1 P70 81 66 56 J6 P71 82 67 57 L8 P72 83 68 58 K8 P73 84 69 59 J8 P74 85 70 - N8 PF2 Document Number: 002-04980 Rev. *E I/O Circuit Type Pin State Type - SCK10_1 (SCL10_1) SIN3_1 SOT3_1 (SDA3_1) SCK3_1 (SCL3_1) SIN15_0 SOT15_0 (SDA15_0) SCK15_0 (SCL15_0) SIN12_1 SOT12_1 (SDA12_1) SCK12_1 (SCL12_1) SCS72_1 SCS73_1 TIOB12_2 MADATA31_0 I2SWS0_0 I - - K TIOA0_0 AIN0_0 G TIOA1_0 BIN0_0 MCSX6_0 G I TIOA2_0 ZIN0_0 MCSX5_0 G I TIOA3_0 INT04_0 MCSX4_0 G K TIOA4_0 MCSX3_0 G I TIOA5_0 MCSX2_0 G I E K BIN0_1 E I ZIN0_1 E I E E K I L Q L B P Q O O E E I I C S T U U K K K E I E K RTO10_0 (PPG10_0) RTO11_0 (PPG10_0) RTO12_0 (PPG12_0) RTO13_0 (PPG12_0) RTO14_0 (PPG14_0) RTO15_0 (PPG14_0) AIN0_1 INT04_2 RX2_2 TX2_2 INT05_2 SCK1_1 (SCL1_1) RX2_0 DTTI1X_0 INT05_0 ADTG_7 TX2_0 FRCK1_0 MCSX0_0 RX2_1 TX2_1 SIN1_1 FRCK1_1 TIOB15_1 INT06_0 TIOA15_1 INT23_1 MRDY_0 X0A X1A VREGCTL VWAKEUP SCS63_0 SCS62_0 ADTG_8 SOT1_1 (SDA1_1) SIN9_0 SOT9_0 (SDA9_0) SCK9_0 (SCL9_0) RTO10_1 (PPG10_1) E MCSX7_0 LBE192 43 MCSX1_0 LQS144 53 Alternate Pin Functions INT23_0 LQP176 Pin Name WKUP2 LQQ216 Pin Number MAD00_0 TIOB0_0 INT07_0 TIOB1_0 MAD02_0 E I TIOB2_0 MAD03_0 E I TIOA6_1 MRASX_0 L I S6E2C Series Datasheet MAD01_0 INT22_1 Page 18 of 200 S6E2C Series LQP176 LQS144 LBE192 Pin Name 86 71 - M8 PF3 87 72 - N9 PF4 88 73 - P9 PF5 89 74 - M9 PF6 90 75 - L9 PF7 91 76 60 K9 P75 92 77 61 P10 P76 93 78 62 N10 P77 94 95 96 79 63 L10 PF8 PF9 P78 97 80 64 K10 P79 98 81 65 M10 P7A 99 100 82 83 66 67 N11 M11 P7B P7C 101 - - - PFA 102 - - - PFB 103 104 84 68 N13 PFC PE0 105 85 69 N12 MD0 106 107 86 87 70 71 P12 P13 PE2 PE3 108 88 72 N14 109 89 73 110 90 111 I/O Circuit Type Pin State Type LQQ216 Pin Number Alternate Pin Functions RTO11_1 (PPG10_1) RTO12_1 (PPG12_1) RTO13_1 (PPG12_1) RTO14_1 (PPG14_1) RTO15_1 (PPG14_1) SIN8_0 SOT8_0 (SDA8_0) SCK8_0 (SCL8_0) SCS70_1 SCS71_1 SIN6_0 SOT6_0 (SDA6_0) SCK6_0 (SCL6_0) DA1 DA0 SCK7_1 (SCL7_1) SOT7_1 (SDA7_1) SIN7_1 MD1 TIOB6_1 INT05_1 MCASX_0 L K TIOA7_1 INT06_1 MSDWEX_0 L K TIOB7_1 INT07_1 MCSX8_0 L K TIOA14_1 INT20_1 MSDCKE_0 L K TIOB14_1 INT21_1 MSDCLK_0 L K TIOB3_0 AIN1_0 INT20_0 E K TIOB4_0 BIN1_0 MAD05_0 E I TIOB5_0 ZIN1_0 MAD06_0 E I DTTI1X_1 IC10_1 IC10_0 AIN1_1 BIN1_1 INT21_0 MAD07_0 E E E I I K IC11_0 MAD08_0 L I IC12_0 MAD09_0 L I SCS60_0 SCS61_0 IC13_0 INT04_1 R R J J IC11_1 ZIN1_1 E I IC12_1 INT07_2 E K IC13_1 INT06_2 E C K E MAD04_0 INT22_0 J D A A A B VSS - - M14 VCC - - 74 M13 AVCC - - 91 75 M12 AVSS - - 112 92 76 L13 AVRL - - 113 93 77 L12 AVRH - - 114 94 78 L11 P10 AN00 F M 115 95 79 K13 P11 AN01 116 96 80 K12 P12 AN02 117 97 81 K14 P13 AN03 118 98 82 K11 P14 AN04 119 - - - PB8 ADTG_6 Document Number: 002-04980 Rev. *E X0 X1 SIN10_0 SOT10_0 (SDA10_0) SCK10_0 (SCL10_0) SIN6_1 SOT6_1 (SDA6_1) SCS63_1 S6E2C Series Datasheet TIOA0_2 AIN0_2 TIOB0_2 BIN0_2 F L TIOA1_2 ZIN0_2 F L RX1_1 INT25_1 F M F L E O TX1_1 INT08_2 TRACED8 INT08_0 Page 19 of 200 S6E2C Series LQP176 LQS144 LBE192 Pin Name 120 - - - PB9 121 - - - PBA 122 - - - PBB 123 99 83 J13 124 100 84 125 101 126 Alternate Pin Functions SIN9_1 SOT9_1 (SDA9_1) SCK9_1 (SCL9_1) AIN2_2 INT09_2 BIN2_2 P15 AN05 J12 P16 AN06 85 J11 P17 AN07 102 - J10 PB0 AN16 127 128 129 130 103 104 105 106 86 J9 H10 J14 H9 PB1 PB2 PB3 P18 AN17 AN18 AN19 AN08 131 107 87 H12 P19 AN09 132 108 88 H14 P1A AN10 133 109 89 G14 P1B AN11 134 110 90 H13 P1C AN12 135 111 91 H11 P1D AN13 136 - - - VSS 137 - - - VCC 138 112 - G13 PB4 AN20 139 113 - F14 PB5 AN21 140 114 - G12 PB6 AN22 141 142 143 144 115 116 117 118 92 93 94 G11 G10 G9 F10 PB7 P1E P1F P2A AN23 AN14 AN15 AN24 145 119 95 F11 P29 AN25 146 120 96 F12 P28 AN26 147 148 121 - 97 - F13 - P27 PBC 149 - - - PBD 150 - - - PBE 151 152 153 154 122 123 124 98 99 100 E10 E11 E12 PBF P26 P25 P24 AN27 TX1_2 SCK0_1 (SCL0_1) SOT0_1 (SDA0_1) SIN0_1 TX1_0 AN28 AN29 Document Number: 002-04980 Rev. *E I/O Circuit Type Pin State Type LQQ216 Pin Number E O TRACED10 E N ZIN2_2 TRACED11 E N SIN11_0 TIOB1_2 AIN1_2 F M TIOA2_2 BIN1_2 F L TIOB2_2 ZIN1_2 F L F L F F F F M M L M F O F N F O SOT11_0 (SDA11_0) SCK11_0 (SCL11_0) SCK6_1 (SCL6_1) SCS60_1 SCS61_1 SCS62_1 SIN2_0 SOT2_0 (SDA2_0) SCK2_0 (SCL2_0) SIN12_0 SOT12_0 (SDA12_0) SCK12_0 (SCL12_0) TRACED9 INT09_0 TIOA9_1 SIN8_1 SOT8_1 (SDA8_1) SCK8_1 (SCL8_1) TIOB12_1 TIOA8_1 RTS5_0 CTS5_0 SCK5_0 (SCL5_0) SOT5_0 (SDA5_0) SIN5_0 TRACED12 TIOB9_1 TIOA10_1 TIOB10_1 TIOA3_2 INT08_1 INT09_1 TIOB3_2 INT24_1 TIOA4_2 TRACED0 TIOB4_2 INT11_0 TIOA5_2 TRACED2 F N TIOB5_2 TRACED3 F N - - INT10_0 TRACED1 - - TIOA11_1 INT10_1 TRACED4 F O TIOB11_1 INT11_1 TRACED5 F O TIOA12_1 TRACED6 F N TRACED7 INT26_1 TIOB8_1 MAD12_0 MAD10_0 INT27_1 F F F F N M M L MAD13_0 F L MAD14_0 F L F E M N E O E N E E F F O I M L INT24_0 MAD15_0 RX1_2 AIN3_2 INT10_2 BIN3_2 TRACED14 ZIN3_2 MAD16_0 RX1_0 TIOA13_1 INT11_2 TRACED15 INT25_0 MAD18_0 MAD17_0 S6E2C Series Datasheet TRACECLK MAD11_0 TRACED13 Page 20 of 200 S6E2C Series LQP176 LQS144 LBE192 Pin Name 155 125 101 E13 P23 UHCONX1 156 126 102 D12 P22 AN31 157 158 127 128 103 104 D13 C13 ADTG_4 NMIX 159 129 105 E14 160 161 162 163 164 165 166 167 168 169 170 130 131 132 133 134 135 136 137 138 139 140 106 107 108 109 110 111 112 113 114 - D14 C14 B14 A13 B13 A12 C12 B12 B11 C11 D11 P21 P20 USBV CC1 P82 P83 VSS VCC P00 P01 P02 P03 P04 P90 P91 171 141 - B10 172 142 - C10 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 D10 B9 C9 B8 D9 E9 F9 C8 D8 E8 A10 F8 B7 A9 A8 A7 C7 192 160 130 A6 193 194 195 196 197 161 162 163 164 165 131 132 133 134 135 D7 E7 F7 B6 C6 198 166 136 D6 Document Number: 002-04980 Rev. *E I/O Circuit Type Pin State Type LQQ216 Pin Number Alternate Pin Functions AN30 SOT0_0 (SDA0_0) SIN0_0 WKUP0 SCK0_0 (SCL0_0) TIOB13_1 F L F M I I K F - - Q_IO2_0 H H E E E E E S S R R G G G G G K K Q_IO1_0 S K Q_IO0_0 S K S S S S K K K K K K K E K K K L K I I K K V V V V V V V W V V V W V E_TXER L W E_TX03 E_TX02 L L L L L W W W W V E W INT26_0 INT27_0 CROUT_0 UDM1 UDP1 TRSTX TCK SWCLK TDI TMS SWDIO TDO SWO INT12_1 Q_IO3_0 SIN5_1 INT13_1 SOT5_1 P92 INT14_1 (SDA5_1) SCK5_1 P93 INT15_1 (SCL5_1) P94 CTS5_1 Q_SCK_0 P95 RTS5_1 Q_CS0_0 P96 RX0_2 INT12_2 P97 TX0_2 INT13_2 PC0 E_RXER PC1 TIOB6_0 E_RX03 PC2 TIOA6_0 E_RX02 PC3 TIOB7_0 E_RX01 PC4 TIOA7_0 E_RX00 PC5 TIOB14_0 E_RXDV PC6 TIOA14_0 E_MDIO PC7 INT13_0 E_MDC PC8 E_RXCK_REFCK PC9 TIOB15_0 E_COL PCA TIOA15_0 E_CRS ETHVCC VSS PCB INT28_0 E_COUT PCC E_TCK SOT4_1 PCD INT14_0 (SDA4_1) PCE SIN4_1 INT15_0 PCF RTS4_1 INT12_0 PD0 INT30_1 E_TX01 PD1 INT31_1 E_TX00 PD2 CTS4_1 FRCK2_1 SCK4_1 P6E ADTG_5 (SCL4_1) S6E2C Series Datasheet Q_CS1_0 Q_CS2_0 CROUT_1 E_TXEN IC23_1 INT29_0 E_PPS Page 21 of 200 S6E2C Series LQP176 LQS144 LBE192 Pin Name 199 - - - P6D 200 - - - P6C 201 202 - - - P6B P6A 203 - - - P69 204 - - - P68 205 - - - P67 206 - - - P66 SIN13_1 207 167 - E6 P65 RTO24_1 (PPG24_1) 208 168 - B5 P64 CTS4_0 209 169 137 C5 P63 210 170 138 B4 P62 ADTG_3 SCK4_0 (SCL4_0) 211 171 139 C4 P61 UHCONX0 212 172 140 B3 P60 SIN4_0 213 173 141 A4 214 215 174 175 142 143 A3 A2 216 176 144 - - - I/O Circuit Type Pin State Type LQQ216 Pin Number Alternate Pin Functions SCK14_1 (SCL14_1) SOT14_1 (SDA14_1) SIN14_1 DTTI2X_1 RTO20_1 (PPG20_1) SCK13_1 (SCL13_0) SOT13_1 (SDA13_1) IC22_1 TIOB6_2 E I IC21_1 TIOA6_2 E I IC20_1 TIOA7_2 TIOB7_2 E E K I E I TIOA14_2 E I TIOB15_2 E I E K E K I K L K L I L I I Q INT14_2 TIOB14_2 RTO21_1 (PPG20_1) RTO22_1 (PPG22_1) RTO23_1 (PPG22_1) TIOA15_2 INT15_2 INT28_1 RTO25_1 (PPG24_1) RTS4_0 INT29_1 INT30_0 MOEX_0 MWEX_0 SOT4_0 (SDA4_0) INT31_0 WKUP3 RTCCO_0 SUBOUT_0 - - H H R R B1 - - - E1 - - - - G1 - - - - - P7 - - - - - P11 - - - - - L14 - - - - - A11 - - - - - A5 - - - - - N7 - - - - - M7 - - - - - L7 - - -- - - K7 J7 G7 H7 - - - - - H8 G8 - - Document Number: 002-04980 Rev. *E USBVCC0 MALE_0 P80 P81 UDM0 UDP0 VSS S6E2C Series Datasheet Page 22 of 200 S6E2C Series Signal Descriptions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module Pin Name A/D converter ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 Function A/D converter external trigger input pin A/D converter analog input pin. ANxx describes A/D converter ch xx. Document Number: 002-04980 Rev. *E LQQ 216 24 32 44 209 157 198 119 71 80 114 115 116 117 118 123 124 125 130 131 132 133 134 135 142 143 126 127 128 129 138 139 140 141 144 145 146 147 153 154 155 156 S6E2C Series Datasheet Pin Number LQP LQS 176 144 19 16 23 20 34 29 169 137 127 103 166 136 56 48 65 55 94 78 95 79 96 80 97 81 98 82 99 83 100 84 101 85 106 86 107 87 108 88 109 89 110 90 111 91 116 92 117 93 102 103 104 105 112 113 114 115 118 94 119 95 120 96 121 97 123 99 124 100 125 101 126 102 LBE 192 F6 G5 J3 C5 D13 D6 M5 L6 L11 K13 K12 K14 K11 J13 J12 J11 H9 H12 H14 G14 H13 H11 G10 G9 J10 J9 H10 J14 G13 F14 G12 G11 F10 F11 F12 F13 E11 E12 E13 D12 Page 23 of 200 S6E2C Series Module Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Pin Name TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 Base Timer 4 Function Base Timer ch 0 TIOA pin Base Timer ch 0 TIOB pin Base Timer ch 1 TIOA pin Base Timer ch 1 TIOB pin Base Timer ch 2 TIOA pin Base Timer ch 2 TIOB pin Base Timer ch 3 TIOA pin Base Timer ch 3 TIOB pin LQQ 216 56 45 114 82 21 115 57 46 116 83 22 123 58 47 124 84 26 125 59 48 130 91 27 131 60 Base Timer ch 4 TIOA pin 39 34 K4 TIOA4_2 132 108 88 H14 TIOB4_0 92 77 61 P10 28 - - - 133 109 89 G14 61 51 43 N4 50 40 35 L1 TIOA5_2 134 110 90 H13 TIOB5_0 93 78 62 N10 29 - - - TIOB5_2 135 111 91 H11 TIOA6_0 179 147 117 D9 85 70 - N8 Base Timer ch 4 TIOB pin TIOB4_2 TIOA5_0 TIOA5_1 TIOB5_1 TIOA6_1 Base Timer 6 LBE 192 N2 J2 L11 L8 K13 N3 K1 K12 K8 J13 M3 K2 J12 J8 J11 L4 K3 H9 K9 H12 M4 49 TIOB4_1 Base Timer 5 Pin Number LQP LQS 176 144 46 38 35 30 94 78 67 57 95 79 47 39 36 31 96 80 68 58 99 83 48 40 37 32 100 84 69 59 101 85 49 41 38 33 106 86 76 60 107 87 50 42 Base Timer ch 5 TIOA pin Base Timer ch 5 TIOB pin Base Timer ch 6 TIOA pin TIOA6_2 200 - - - TIOB6_0 178 146 116 B8 86 71 - M8 199 - - - TIOB6_1 Base Timer ch 6 TIOB pin TIOB6_2 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 24 of 200 S6E2C Series Module LQQ 216 Pin Number LQP LQS 176 144 181 149 119 LBE 192 F9 87 72 - N9 TIOA7_2 202 - - - TIOB7_0 180 148 118 E9 Pin Name Function TIOA7_0 TIOA7_1 Base Timer 7 TIOB7_1 Base Timer ch 7 TIOB pin 88 73 - P9 TIOB7_2 201 - - - TIOA8_0 2 2 2 B2 142 116 92 G10 TIOA8_2 10 10 - E2 TIOB8_0 18 17 14 F4 143 117 93 G9 11 11 - E3 TIOA8_1 Base Timer 8 Base Timer ch 7 TIOA pin TIOB8_1 Base Timer ch 8 TIOA pin Base Timer ch 8 TIOB pin TIOB8_2 TIOA9_0 3 3 3 C2 126 102 - J10 TIOA9_2 12 12 - E4 TIOB9_0 23 18 15 F5 127 103 - J9 TIOB9_2 13 - - - TIOA10_0 4 4 4 C3 128 104 - H10 TIOA9_1 Base Timer 9 TIOB9_1 TIOA10_1 Base Timer 10 Base Timer ch 10 TIOA pin 19 - - - TIOB10_0 24 19 16 F6 129 105 - J14 TIOB10_2 20 - - - TIOA11_0 5 5 5 D5 138 112 - G13 TIOA11_2 33 - - - TIOB11_0 25 20 17 G2 139 113 - F14 TIOB11_2 51 41 - L2 TIOA12_0 6 6 6 D2 140 114 - G12 TIOA12_2 52 42 - L3 TIOB12_0 30 21 18 G3 141 115 - G11 53 43 - M2 TIOA11_1 TIOB11_1 TIOA12_1 Base Timer 12 Base Timer ch 9 TIOB pin TIOA10_2 TIOB10_1 Base Timer 11 Base Timer ch 9 TIOA pin TIOB12_1 Base Timer ch 10 TIOB pin Base Timer ch 11 の TIOA pin Base Timer ch 11 TIOB pin Base Timer ch 12 TIOA pin Base Timer ch 12 TIOB pin TIOB12_2 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 25 of 200 S6E2C Series Module Pin Name Function LQQ 216 7 7 7 LBE 192 D1 154 124 100 E12 TIOA13_2 34 24 - G6 TIOB13_0 31 22 19 G4 155 125 101 E13 TIOA13_0 TIOA13_1 Base Timer 13 TIOB13_1 35 25 - H4 183 151 121 D8 89 74 - M9 TIOA14_2 204 - - - TIOB14_0 182 150 120 C8 90 75 - L9 TIOB14_2 203 - - - TIOA15_0 187 155 125 B7 TIOA15_1 Base Timer ch 14 TIOB pin Base Timer ch 15 TIOA pin 78 63 - K5 206 - - - TIOB15_0 186 154 124 F8 79 64 - K6 TIOB15_2 205 - - - TX0_0 18 17 14 F4 35 25 - H4 176 - - - 17 16 13 F3 TX0_1 Base timer ch 15 TIOB pin CAN interface ch 0 TX output pin TX0_2 RX0_0 RX0_1 CAN interface ch 0 RX output pin 34 24 - G6 RX0_2 175 - - - TX1_0 152 122 98 E10 118 98 82 K11 TX1_2 148 - - - RX1_0 153 123 99 E11 117 97 81 K14 149 - - - 71 56 48 M5 79 64 - K6 TX2_2 69 - - - RX2_0 70 55 47 L5 78 63 - K5 68 - - - TX1_1 CAN 1 Base Timer ch 14 TIOA pin TIOA15_2 TIOB15_1 CAN 0 Base Timer ch 13 TIOB pin TIOA14_0 TIOB14_1 Base Timer 15 Base Timer ch 13 TIOA pin TIOB13_2 TIOA14_1 Base Timer 14 RX1_1 CAN interface ch 1 TX output pin CAN interface ch 1 RX output pin RX1_2 TX2_0 TX2_1 CAN 2 (CAN-FD) Pin Number LQP LQS 176 144 RX2_1 CAN-FD interface ch 2 TX output pin CAN-FD interface ch 2 RX input pin RX2_2 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 26 of 200 S6E2C Series Module Pin Name Function LQQ 216 Pin Number LQP LQS 176 144 LBE 192 165 135 111 A12 167 137 113 B12 168 138 114 B11 SWO Serial wire debug interface clock input pin Serial wire debug interface data input/output pin Serial wire viewer output pin TCK JTAG test clock input pin 165 135 111 A12 TDI JTAG test data input pin 166 136 112 C12 TDO JTAG debug data output pin JTAG test mode state input/output pin Trace CLK output pin of ETM/HTM 168 138 114 B11 167 137 113 B12 131 107 87 H12 132 108 88 H14 133 109 89 G14 134 110 90 H13 SWCLK SWDIO TMS TRACECLK TRACED0 TRACED1 TRACED2 Debugger Trace data output pin of ETM/ Trace data output pin of HTM TRACED3 135 111 91 H11 TRACED4 138 112 - G13 TRACED5 139 113 - F14 TRACED6 140 114 - G12 TRACED7 141 115 - G11 TRACED8 119 - - - 120 - - - TRACED9 TRACED10 Trace data output pin of HTM 121 - - - TRACED11 122 - - - TRACED12 148 - - - TRACED13 149 - - - TRACED14 150 - - - TRACED15 151 - - - 164 134 110 B13 TRSTX JTAG test reset Input pin Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 27 of 200 S6E2C Series Module Pin Name LQQ 216 Pin Number LQP LQS 176 144 MAD00_0 81 66 56 LBE 192 J6 MAD01_0 82 67 57 L8 MAD02_0 83 68 58 K8 MAD03_0 84 69 59 J8 MAD04_0 91 76 60 K9 MAD05_0 92 77 61 P10 MAD06_0 93 78 62 N10 MAD07_0 96 79 63 L10 MAD08_0 97 80 64 K10 MAD09_0 98 81 65 M10 MAD10_0 142 116 92 G10 MAD11_0 143 117 93 G9 144 118 94 F10 MAD13_0 145 119 95 F11 MAD14_0 146 120 96 F12 MAD15_0 147 121 97 F13 MAD16_0 152 122 98 E10 MAD17_0 153 123 99 E11 MAD18_0 154 124 100 E12 MAD19_0 50 40 35 L1 MAD20_0 49 39 34 K4 MAD21_0 48 38 33 K3 MAD22_0 47 37 32 K2 MAD23_0 46 36 31 K1 MAD24_0 45 35 30 J2 MCSX0_0 71 56 48 M5 MCSX1_0 70 55 47 L5 MCSX2_0 61 51 43 N4 60 50 42 M4 MAD12_0 External bus Function External bus interface address bus MCSX3_0 MCSX4_0 External bus interface chip select output pin 59 49 41 L4 MCSX5_0 58 48 40 M3 MCSX6_0 57 47 39 N3 MCSX7_0 56 46 38 N2 MCSX8_0 88 73 - P9 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 28 of 200 S6E2C Series Module Pin Name LQQ 216 Pin Number LQP LQS 176 144 MADATA00_0 2 2 2 LBE 192 B2 MADATA01_0 3 3 3 C2 MADATA02_0 4 4 4 C3 MADATA03_0 5 5 5 D5 MADATA04_0 6 6 6 D2 MADATA05_0 7 7 7 D1 MADATA06_0 8 8 8 D3 MADATA07_0 9 9 9 D4 MADATA08_0 14 13 10 E5 MADATA09_0 15 14 11 F1 MADATA10_0 16 15 12 F2 MADATA11_0 17 16 13 F3 MADATA12_0 18 17 14 F4 MADATA13_0 23 18 15 F5 MADATA14_0 24 19 16 F6 25 20 17 G2 10 - - - MADATA17_0 11 - - - MADATA18_0 12 - - - MADATA19_0 13 - - - MADATA20_0 19 - - - MADATA21_0 20 - - - MADATA22_0 21 - - - MADATA23_0 22 - - - MADATA24_0 26 - - - MADATA25_0 27 - - - MADATA26_0 28 - - - MADATA27_0 29 - - - MADATA28_0 33 - - - MADATA29_0 51 - - - MADATA30_0 52 - - - MADATA31_0 MDQM0_0 MDQM1_0 53 30 31 21 22 18 19 G3 G4 34 35 - - - 211 171 139 C4 80 65 55 L6 32 23 20 G5 MADATA15_0 MADATA16_0 External bus Function MDQM2_0 MDQM3_0 MALE_0 MRDY_0 MCLKOUT_0 External bus interface data bus (address/data multiplex bus) External bus interface byte mask signal output pin External bus interface address latch enable output signal for multiplex External bus interface external RDY input signal External bus interface external clock output pin Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 29 of 200 S6E2C Series Module Pin Name MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MOEX_0 External bus MWEX_0 MSDCLK_0 MSDCKE_0 MRASX_0 MCASX_0 MSDWEX_0 Function LQQ 216 External bus interface ALE signal to control NAND flash output pin External bus interface CLE signal to control NAND flash output pin External bus interface read enable signal to control NAND flash External bus interface write enable signal to control NAND flash External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM SDRAM interface SDRAM clock output pin SDRAM interface SDRAM clock enable pin SDRAM interface SDRAM column active strobe pin SDRAM interface SDRAM row active strobe pin SDRAM interface SDRAM write enable pin INT00_0 INT00_1 External interrupt request 00 input pin INT00_2 INT01_0 INT01_1 External interrupt request 01 input pin INT01_2 INT02_0 INT02_1 External interrupt External interrupt request 02 input pin INT02_2 INT03_0 INT03_1 External interrupt request 03 input pin INT03_2 INT04_0 INT04_1 External interrupt request 04 input pin INT04_2 INT05_0 INT05_1 External interrupt request 05 input pin INT05_2 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Pin Number LQP LQS 176 144 LBE 192 47 37 32 K2 48 38 33 K3 50 40 35 L1 49 39 34 K4 209 169 137 C5 210 170 138 B4 90 75 - L9 89 74 - M9 85 70 - N8 86 71 - M8 87 72 - N9 2 2 2 B2 38 28 23 H3 19 - - - 7 7 7 D1 41 31 26 H6 51 41 - L2 14 13 10 E5 42 32 27 J5 26 - - - 17 16 13 F3 43 33 28 J4 34 24 - G6 59 49 41 L4 100 83 67 M11 65 - - - 70 55 47 L5 86 71 - M8 68 - - - Page 30 of 200 S6E2C Series Module Pin Name Function LQQ 216 INT06_0 INT06_1 External interrupt request 06 input pin INT06_2 INT07_0 INT07_1 External interrupt request 07 input pin INT07_2 INT08_0 INT08_1 External interrupt request 08 input pin INT08_2 INT09_0 INT09_1 External interrupt request 09 input pin INT09_2 INT10_0 INT10_1 External interrupt request 10 input pin INT10_2 INT11_0 INT11_1 External interrupt request 11 input pin INT11_2 INT12_0 External interrupt INT12_1 External interrupt request 12 input pin Pin Number LQP LQS 176 144 80 65 55 LBE 192 L6 87 72 - N9 103 - - - 82 67 57 L8 88 73 - P9 102 - - - 114 94 78 L11 127 103 - J9 119 - - - 123 99 83 J13 128 104 - H10 120 - - - 130 106 86 H9 138 112 - G13 149 - - - 133 109 89 G14 139 113 - F14 151 - - - 194 162 132 E7 169 139 - C11 INT12_2 175 - - - INT13_0 184 152 122 E8 170 140 - D11 176 - - - 192 160 130 A6 171 141 - B10 201 - - - 193 161 131 D7 172 142 - C10 INT13_1 External interrupt request 13 input pin INT13_2 INT14_0 INT14_1 External interrupt request 14 input pin INT14_2 INT15_0 INT15_1 External interrupt request 15 input pin INT15_2 206 - - - INT16_0 External interrupt request 16 input pin 25 20 17 G2 45 35 30 J2 External interrupt request 17 input pin 30 21 18 G3 46 36 31 K1 External interrupt request 18 input pin 31 22 19 G4 47 37 32 K2 External interrupt request 19 input pin 36 48 91 26 38 76 21 33 60 H2 K3 K9 89 74 - M9 INT16_1 INT17_0 INT17_1 INT18_0 INT18_1 INT19_0 INT19_1 INT20_0 INT20_1 External interrupt request 20 input pin Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 31 of 200 S6E2C Series Module Pin Name LQQ 216 Pin Number LQP LQS 176 144 External interrupt request 21 input pin 96 79 63 LBE 192 L10 90 75 - L9 External interrupt request 22 input pin 99 82 66 N11 78 63 - K5 External interrupt request 23 input pin 56 46 38 N2 79 64 - K6 External interrupt request 24 input pin 147 121 97 F13 131 107 87 H12 External interrupt request 25 input pin 153 123 99 E11 117 97 81 K14 External interrupt request 26 input pin 156 126 102 D12 142 116 92 G10 External interrupt request 27 input pin 157 127 103 D13 143 117 93 G9 External interrupt request 28 input pin 190 158 128 A7 207 167 - E6 External interrupt request 29 input pin 198 166 136 D6 208 168 - B5 External interrupt request 30 input pin 209 169 137 C5 195 163 133 F7 212 172 140 B3 INT31_1 External interrupt request 31 input pin 196 164 134 B6 NMIX Non-maskable interrupt input pin 158 128 104 C13 INT21_0 INT21_1 INT22_0 INT22_1 INT23_0 INT23_1 INT24_0 INT24_1 INT25_0 INT25_1 INT26_0 External interrupt Function INT26_1 INT27_0 INT27_1 INT28_0 INT28_1 INT29_0 INT29_1 INT30_0 INT30_1 INT31_0 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 32 of 200 S6E2C Series Module LQQ 216 Pin Number LQP LQS 176 144 P00 164 134 110 LBE 192 B13 P01 165 135 111 A12 P02 166 136 112 C12 167 137 113 B12 Pin Name P03 P04 General-purpose I/O port 0 168 138 114 B11 P08 30 21 18 G3 P09 31 22 19 G4 P0A 32 23 20 G5 P10 114 94 78 L11 P11 115 95 79 K13 P12 116 96 80 K12 P13 117 97 81 K14 P14 118 98 82 K11 P15 123 99 83 J13 P16 124 100 84 J12 125 101 85 J11 130 106 86 H9 P19 131 107 87 H12 P1A 132 108 88 H14 P1B 133 109 89 G14 P1C 134 110 90 H13 P1D 135 111 91 H11 P1E 142 116 92 G10 P1F 143 117 93 G9 P20 158 128 104 C13 P21 157 127 103 D13 P22 156 126 102 D12 P23 155 125 101 E13 154 124 100 E12 P17 P18 GPIO Function General-purpose I/O port 1 P24 P25 General-purpose I/O port 2 153 123 99 E11 P26 152 122 98 E10 P27 147 121 97 F13 P28 146 120 96 F12 P29 145 119 95 F11 P2A 144 118 94 F10 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 33 of 200 S6E2C Series Module Pin Name LQQ 216 Pin Number LQP LQS 176 144 P30 34 24 - LBE 192 G6 P31 35 25 - H4 P32 36 26 21 H2 P33 37 27 22 J1 P34 38 28 23 H3 P35 41 31 26 H6 P36 42 32 27 J5 43 33 28 J4 P38 44 34 29 J3 P39 45 35 30 J2 P3A 46 36 31 K1 P3B 47 37 32 K2 P3C 48 38 33 K3 P3D 49 39 34 K4 P3E 50 40 35 L1 P40 56 46 38 N2 P41 57 47 39 N3 P42 58 48 40 M3 P43 59 49 41 L4 P44 60 50 42 M4 P45 61 51 43 N4 P46 73 58 50 P5 74 59 51 P6 P48 76 61 53 N6 P49 77 62 54 M6 P4A 65 - - - P4B 66 - - - P4C 67 - - - P4D 68 - - - P4E 69 - - - P37 GPIO Function P47 General-purpose I/O port 3 General-purpose I/O port 4 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 34 of 200 S6E2C Series Module Pin Name LQQ 216 Pin Number LQP LQS 176 144 P50 10 10 - LBE 192 E2 P51 11 11 - E3 P52 12 12 - E4 P53 13 - - - P54 19 - - - P55 20 - - - P56 21 - - - 22 - - - 26 - - - P59 27 - - - P5A 28 - - - P5B 29 - - - P5C 33 - - - P5D 51 41 - L2 P5E 52 42 - L3 P5F 53 43 - M2 P60 212 172 140 B3 P61 211 171 139 C4 P62 210 170 138 B4 P63 209 169 137 C5 P64 208 168 - B5 P65 207 167 - E6 P66 206 - - - 205 - - - P68 204 - - - P69 203 - - - P6A 202 - - - P6B 201 - - - P6C 200 - - - P6D 199 - - - P6E 198 166 136 D6 P57 P58 GPIO Function P67 General-purpose I/O port 5 General-purpose I/O port 6 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 35 of 200 S6E2C Series Module Pin Name LQQ 216 Pin Number LQP LQS 176 144 P70 80 65 55 LBE 192 L6 P71 81 66 56 J6 P72 82 67 57 L8 P73 83 68 58 K8 P74 84 69 59 J8 P75 91 76 60 K9 P76 92 77 61 P10 93 78 62 N10 P78 96 79 63 L10 P79 97 80 64 K10 P7A 98 81 65 M10 P7B 99 82 66 N11 P7C 100 83 67 M11 P7D 70 55 47 L5 P7E 71 56 48 M5 P80 214 174 142 A3 215 175 143 A2 160 130 106 D14 P83 161 131 107 C14 P90 169 139 - C11 P91 170 140 - D11 P92 171 141 - B10 172 142 - C10 173 143 - D10 P95 174 144 - B9 P96 175 - - - P97 176 - - - P77 GPIO Function P81 P82 P93 P94 General-purpose I/O port 7 General-purpose I/O port 8 General-purpose I/O port 9 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 36 of 200 S6E2C Series Module Pin Name LQQ 216 Pin Number LQP LQS 176 144 PA0 2 2 2 LBE 192 B2 PA1 3 3 3 C2 PA2 4 4 4 C3 PA3 5 5 5 D5 PA4 6 6 6 D2 PA5 7 7 7 D1 PA6 8 8 8 D3 9 9 9 D4 14 13 10 E5 PA9 15 14 11 F1 PAA 16 15 12 F2 PAB 17 16 13 F3 PAC 18 17 14 F4 PAD 23 18 15 F5 PAE 24 19 16 F6 PAF 25 20 17 G2 PB0 126 102 - J10 PB1 127 103 - J9 PB2 128 104 - H10 PB3 129 105 - J14 PB4 138 112 - G13 PB5 139 113 - F14 PB6 140 114 - G12 141 115 - G11 119 - - - PB9 120 - - - PBA 121 - - - PBB 122 - - - PBC 148 - - - PBD 149 - - - PBE 150 - - - PBF 151 - - - PA7 PA8 GPIO Function PB7 PB8 General-purpose I/O port A General-purpose I/O port B Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 37 of 200 S6E2C Series Module LQQ 216 Pin Number LQP LQS 176 144 PC0 177 145 115 LBE 192 C9 PC1 178 146 116 B8 PC2 179 147 117 D9 PC3 180 148 118 E9 PC4 181 149 119 F9 PC5 182 150 120 C8 PC6 183 151 121 D8 184 152 122 E8 185 153 123 A10 PC9 186 154 124 F8 PCA 187 155 125 B7 PCB 190 158 128 A7 PCC 191 159 129 C7 PCD 192 160 130 A6 PCE 193 161 131 D7 PCF 194 162 132 E7 PD0 195 163 133 F7 196 164 134 B6 PD2 197 165 135 C6 PE0 104 84 68 N13 Pin Name PC7 PC8 GPIO PD1 PE2 Function General-purpose I/O port C General-purpose I/O port D General-purpose I/O port E 106 86 70 P12 PE3 107 87 71 P13 PF0 78 63 - K5 PF1 79 64 - K6 PF2 85 70 - N8 PF3 86 71 - M8 PF4 87 72 - N9 PF5 88 73 - P9 89 74 - M9 PF7 90 75 - L9 PF8 94 - - - PF9 95 - - - PFA 101 - - - PFB 102 - - - PFC 103 - - - PF6 General-purpose I/O port F Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 38 of 200 S6E2C Series Module Pin Name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) MultiFunction Serial 0 SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 SOT1_0 (SDA1_0) MultiFunction Serial 1 SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) SIN2_0 SIN2_1 SOT2_0 (SDA2_0) MultiFunction Serial 2 SOT2_1 (SDA2_1) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) Function LQQ 216 Pin Number LQP LQS 176 144 157 127 103 LBE 192 D13 151 - - - 156 126 102 D12 150 - - - 155 125 101 E13 149 - - - Multi-function serial interface ch 0 input pin Multi-function serial interface ch 0 output pin This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 0 clock I/O pin This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4) Multi-function serial interface ch 1 input pin Multi-function serial interface ch 1 output pin This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 1 clock I/O pin This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 2 input pin Multi-function serial interface ch 2 output pin This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 2 clock I/O pin This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and as SCL2 when it is used in an I2C (operation mode 4). Document Number: 002-04980 Rev. *E S6E2C Series Datasheet 7 7 7 D1 80 65 55 L6 8 8 8 D3 81 66 56 J6 9 9 9 D4 70 55 47 L5 130 106 86 H9 45 35 30 J2 131 107 87 H12 46 36 31 K1 132 108 88 H14 47 37 32 K2 Page 39 of 200 S6E2C Series Module Pin Name SIN3_0 SIN3_1 SOT3_0 (SDA3_0) MultiFunction Serial 3 SOT3_1 (SDA3_1) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SIN4_0 SIN4_1 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) MultiFunction Serial 4 SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) CTS4_0 CTS4_1 RTS4_0 RTS4_1 Function LQQ 216 Pin Number LQP LQS 176 144 25 20 17 LBE 192 G2 56 46 38 N2 24 19 16 F6 57 47 39 N3 23 18 15 F5 58 48 40 M3 212 172 140 B3 193 161 131 D7 211 171 139 C4 192 160 130 A6 210 170 138 B4 198 166 136 D6 Multi-function serial interface ch 4 CTS input pin 208 168 - B5 197 165 135 C6 Multi-function serial interface ch 4 RTS output pin 209 169 137 C5 194 162 132 E7 Multi-function serial interface ch 3 input pin Multi-function serial interface ch 3 output pin This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 3 clock I/O pin This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 4 input pin Multi-function serial interface ch 4 output pin This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 4 clock I/O pin This pin operates as SCK4 when it is used in a CSIO (operation mode 2) and as SCL4 when it is used in an I2C (operation mode 4). Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 40 of 200 S6E2C Series Module Pin Name SIN5_0 SIN5_1 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) MultiFunction Serial 5 SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) CTS5_0 CTS5_1 RTS5_0 RTS5_1 SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) MultiFunction Serial 6 SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) SCS60_0 SCS60_1 SCS61_0 SCS61_1 Function LQQ 216 Pin Number LQP LQS 176 144 147 121 97 LBE 192 F13 170 140 - D11 146 120 96 F12 171 141 - B10 145 119 95 F11 172 142 - C10 Multi-function serial interface ch 5 input pin Multi-function serial interface ch 5 output pin This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 5 clock I/O pin This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 5 CTS input pin 144 118 94 F10 173 143 - D10 Multi-function serial interface ch 5 RTS output pin 143 117 93 G9 174 144 - B9 Multi-function serial interface ch 6 input pin 96 79 63 L10 117 97 81 K14 97 80 64 K10 118 98 82 K11 98 81 65 M10 126 102 - J10 99 127 100 82 103 83 66 67 N11 J9 M11 128 H10 Multi-function serial interface ch 6 output pin This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 6 clock I/O pin This pin operates as SCK6 when it is used in a CSIO (operation mode 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 6 chip select 0 input/output pin Multi-function serial interface ch 6 chip select1 input/output pin 104 - 79 64 - K6 SCS62_1 Multi-function serial interface ch 6 chip select2 input/output pin 129 105 - J14 SCS63_0 SCS63_1 Multi-function serial interface ch 6 chip select3 input/output pin 78 119 63 - - K5 - SCS62_0 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 41 of 200 S6E2C Series Module Pin Name Function SIN7_0 SIN7_1 SOT7_0 (SDA7_0) Multi-function serial interface ch 7 input pin Multi-function serial interface ch 7 output pin This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 7 clock I/O pin This pin operates as SCK7 when it is used in a CSIO (operation mode 2) and as SCL7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 7 chip select 0 input/output pin SOT7_1 (SDA7_1) MultiFunction Serial 7 SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) SCS70_0 SCS70_1 SCS71_0 SCS71_1 SCS72_0 SCS72_1 SCS73_0 SCS73_1 SIN8_0 SIN8_1 SOT8_0 (SDA8_0) MultiFunction Serial 8 SOT8_1 (SDA8_1) SCK8_0 (SCL8_0) SCK8_1 (SCL8_1) SIN9_0 SIN9_1 SOT9_0 (SDA9_0) MultiFunction Serial 9 SOT9_1 (SDA9_1) SCK9_0 (SCL9_0) SCK9_1 (SCL9_1) LQQ 216 14 103 Multi-function serial interface ch 7 chip select 1 input/output pin Multi-function serial interface ch 7 chip select 2 input/output pin Multi-function serial interface ch 7 chip select 3 input/output pin Multi-function serial interface ch 8 input pin Multi-function serial interface ch 8 output pin This pin operates as SOT8 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA8 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 8 clock I/O pin This pin operates as SCK8 when it is used in a CSIO (operation mode 2) and as SCL8 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 9 input pin Multi-function serial interface ch 9 output pin This pin operates as SOT9 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA9 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 9 clock I/O pin This pin operates as SCK9 when it is used in a CSIO (operation mode 2) and as SCL9 when it is used in an I2C (operation mode 4). Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Pin Number LQP LQS 176 144 13 10 - LBE 192 E5 - 15 14 11 F1 102 - - - 16 15 12 F2 101 - - - 17 94 18 95 10 68 11 69 91 138 16 17 10 11 76 112 13 14 60 - F3 F4 E2 E3 K9 G13 92 77 61 P10 139 113 - F14 93 78 62 N10 140 114 - G12 82 120 67 - 57 - L8 - 83 68 58 K8 121 - - - 84 69 59 J8 122 - - - Page 42 of 200 S6E2C Series Module MultiFunction Serial 10 Function LQQ 216 SIN10_0 SIN10_1 SOT10_0 (SDA10_0) Multi-function serial interface ch 10 input pin Multi-function serial interface ch 10 output pin This pin operates as SOT10 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA10 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 10 clock I/O pin This pin operates as SCK10 when it is used in a CSIO (operation mode 2) and as SCL10 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 11 input pin Multi-function serial interface ch 11 output pin This pin operates as SOT11 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA11 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 11 clock I/O pin This pin operates as SCK11 when it is used in a CSIO (operation mode 2) and as SCL11 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 12 input pin Multi-function serial interface ch 12 output pin This pin operates as SOT12 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA12 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 12 clock I/O pin This pin operates as SCK12 when it is used in a CSIO (operation mode 2) and as SCL12 when it is used in an I2C (operation mode 4). 114 51 94 41 78 - LBE 192 L11 L2 115 95 79 K13 52 42 - L3 116 96 80 K12 53 43 - M2 123 26 99 - 83 - J13 - 124 100 84 J12 27 - - - 125 101 85 J11 28 - - - 133 65 109 - 89 - G14 - 134 110 90 H13 66 - - - 135 111 91 H11 67 - - - SOT10_1 (SDA10_1) SCK10_0 (SCL10_0) SCK10_1 (SCL10_1) SIN11_0 SIN11_1 SOT11_0 (SDA11_0) MultiFunction Serial 11 SOT11_1 (SDA11_1) SCK11_0 (SCL11_0) SCK11_1 (SCL11_1) SIN12_0 SIN12_1 SOT12_0 (SDA12_0) MultiFunction Serial 12 Pin Number LQP LQS 176 144 Pin Name SOT12_1 (SDA12_1) SCK12_0 (SCL12_0) SCK12_1 (SCL12_1) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 43 of 200 S6E2C Series Module MultiFunction Serial 13 Function LQQ 216 SIN13_0 SIN13_1 SOT13_0 (SDA13_0) Multi-function serial interface ch 13 input pin Multi-function serial interface ch 13 output pin This pin operates as SOT13 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA13 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 13 clock I/O pin This pin operates as SCK13 when it is used in a CSIO (operation mode 2) and as SCL13 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 14 input pin Multi-function serial interface ch 14 output pin This pin operates as SOT14 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA14 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 14 clock I/O pin This pin operates as SCK14 when it is used in a CSIO (operation mode 2) and as SCL14 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 15 input pin Multi-function serial interface ch 15 output pin This pin operates as SOT15 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA15 when it is used in an I2C (operation mode 4). Multi-function serial interface ch 15 clock I/O pin This pin operates as SCK15 when it is used in a CSIO (operation mode 2) and as SCL15 when it is used in an I2C (operation mode 4). 48 206 38 - 33 - LBE 192 K3 - 49 39 34 K4 205 - - - 50 40 35 L1 204 - - - 30 201 21 - 18 - G3 - 31 22 19 G4 200 - - - 32 23 20 G5 199 - - - 59 19 49 - 41 - L4 - 60 50 42 M4 20 - - - 61 51 43 N4 21 - - - SOT13_1 (SDA13_1) SCK13_0 (SCL13_0) SCK13_1 (SCL13_1) SIN14_0 SIN14_1 SOT14_0 (SDA14_0) MultiFunction Serial 14 SOT14_1 (SDA14_1) SCK14_0 (SCL14_0) SCK14_1 (SCL14_1) SIN15_0 SIN15_1 SOT15_0 (SDA15_0) MultiFunction Serial 15 Pin Number LQP LQS 176 144 Pin Name SOT15_1 (SDA15_1) SCK15_0 (SCL15_0) SCK15_1 (SCL15_1) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 44 of 200 S6E2C Series Module Function LQQ 216 DTTI0X_0 Input signal controlling waveform generator outputs RTO00 to RTO05 of Multi-Function Timer 0. 44 34 29 LBE 192 J3 21 - - - 16-bit free-run timer ch 0 external clock input pin 37 27 22 J1 29 - - - IC00_0 43 33 28 J4 IC00_1 22 - - - IC01_0 42 32 27 J5 26 - - - 41 31 26 H6 IC02_1 27 - - - IC03_0 38 28 23 H3 IC03_1 28 - - - Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 45 35 30 J2 10 10 - E2 Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 46 36 31 K1 11 11 - E3 Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 47 37 32 K2 12 12 - E4 Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 48 38 33 K3 13 - - - Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 49 39 34 K4 19 - - - Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 50 40 35 L1 20 - - - DTTI0X_1 FRCK0_0 FRCK0_1 IC01_1 IC02_0 RTO00_0 (PPG00_0) MultiFunction Timer 0 Pin Number LQP LQS 176 144 Pin Name RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) 16-bit input capture input pin of Multi-Function Timer 0. ICxx describes channel number. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 45 of 200 S6E2C Series Module Function LQQ 216 DTTI1X_0 Input signal controlling waveform generator outputs RTO10 to RTO15 of Multi-Function Timer 1. 70 55 47 LBE 192 L5 94 - - - 16-bit free-run timer ch 1 external clock input pin 71 56 48 M5 78 63 - K5 IC10_0 96 79 63 L10 IC10_1 95 - - - IC11_0 97 80 64 K10 101 - - - 98 81 65 M10 IC12_1 102 - - - IC13_0 99 82 66 N11 IC13_1 103 - - - Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 56 46 38 N2 85 70 - N8 Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 57 47 39 N3 86 71 - M8 Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 58 48 40 M3 87 72 - N9 Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 59 49 41 L4 88 73 - P9 Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 60 50 42 M4 89 74 - M9 Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 61 51 43 N4 90 75 - L9 DTTI1X_1 FRCK1_0 FRCK1_1 IC11_1 IC12_0 RTO10_0 (PPG10_0) MultiFunction Timer 1 Pin Number LQP LQS 176 144 Pin Name RTO10_1 (PPG10_1) RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) RTO14_1 (PPG14_1) RTO15_0 (PPG14_0) RTO15_1 (PPG14_1) 16-bit input capture input pin of Multi-Function Timer 1. ICxx describes channel number. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 46 of 200 S6E2C Series Module Function LQQ 216 DTTI2X_0 Input signal controlling waveform generator outputs RTO20 to RTO25 of Multi-Function Timer 1. 8 8 8 LBE 192 D3 202 - - - 17 16 13 F3 197 165 135 C6 IC20_0 9 9 9 D4 IC20_1 201 - - - IC21_0 14 13 10 E5 200 - - - 15 14 11 F1 IC22_1 199 - - - IC23_0 16 15 12 F2 IC23_1 198 166 136 D6 2 2 2 B2 203 - - - 3 3 3 C2 204 - - - 4 4 4 C3 205 - - - 5 5 5 D5 206 - - - 6 6 6 D2 207 167 - E6 7 7 7 D1 208 168 - B5 DTTI2X_1 FRCK2_0 FRCK2_1 IC21_1 IC22_0 RTO20_0 (PPG20_0) MultiFunction Timer 2 Pin Number LQP LQS 176 144 Pin Name RTO20_1 (PPG20_1) RTO21_0 (PPG20_0) RTO21_1 (PPG20_1) RTO22_0 (PPG22_0) RTO22_1 (PPG22_1) RTO23_0 (PPG22_0) RTO23_1 (PPG22_1) RTO24_0 (PPG24_0) RTO24_1 (PPG24_1) RTO25_0 (PPG24_0) RTO25_1 (PPG24_1) 16-bit free-run timer ch 2 external clock input pin 16-bit input capture input pin of Multi-Function Timer 2. ICxx describes channel number. Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 47 of 200 S6E2C Series Module Pin Name Function LQQ 216 56 46 38 LBE 192 N2 65 - - - AIN0_2 114 94 78 L11 BIN0_0 57 47 39 N3 AIN0_0 AIN0_1 Quadrature Position/ Revolution Counter 0 BIN0_1 QPRC ch 0 AIN input pin QPRC ch 0 BIN input pin 66 - - - BIN0_2 115 95 79 K13 ZIN0_0 58 48 40 M3 67 - - - ZIN0_2 116 96 80 K12 AIN1_0 91 76 60 K9 94 - - - 123 99 83 J13 92 77 61 P10 45 - - - BIN1_2 124 100 84 J12 ZIN1_0 93 78 62 N10 101 - - - ZIN1_2 125 101 85 J11 AIN2_0 2 2 2 B2 32 23 20 G5 ZIN0_1 AIN1_1 QPRC ch 0 ZIN input pin QPRC ch 1 AIN input pin AIN1_2 Quadrature Position/ Revolution Counter 1 BIN1_0 BIN1_1 ZIN1_1 AIN2_1 Quadrature Position/ Revolution Counter 2 QPRC ch 1 ZIN input pin QPRC ch 2 AIN input pin 120 - - - BIN2_0 3 3 3 C2 36 26 21 H2 BIN2_2 121 - - - ZIN2_0 4 4 4 C3 37 27 22 J1 ZIN2_2 122 - - - AIN3_0 18 17 14 F4 45 35 30 J2 BIN2_1 AIN3_1 Position/ Revolution Counter 3 QPRC ch 1 BIN input pin AIN2_2 ZIN2_1 Quadrature Pin Number LQP LQS 176 144 QPRC ch 2 BIN input pin QPRC ch 2 ZIN input pin QPRC ch 3 AIN input pin AIN3_2 149 - - - BIN3_0 23 18 15 F5 46 36 31 K1 BIN3_2 150 - - - ZIN3_0 24 19 16 F6 47 37 32 K2 151 - - - BIN3_1 ZIN3_1 QPRC ch 3 BIN input pin QPRC ch 3 ZIN input pin ZIN3_2 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 48 of 200 S6E2C Series Module Pin Name RTCCO_0 Real-time clock RTCCO_1 SUBOUT_0 SUBOUT_1 USB0 139 33 - - - 211 171 139 C4 33 - - - Sub-clock output pin 142 A3 UDP0 USB ch 0 device/host D + pin USB ch 0 external pull-up control pin USB ch 1 device/host D – pin 215 175 143 A2 211 171 139 C4 160 130 106 D14 USB ch 1 device/host D + pin USB ch 1 external pull-up control pin Deep Standby mode return signal input pin 0 Deep Standby mode return signal input pin 1 Deep Standby mode return signal input pin 2 Deep Standby mode return signal input pin 3 D/A converter ch 0 analog output pin D/A converter ch 1 analog output pin On-board regulator control pin The return signal input pin from a hibernation state SD memory card interface SD memory card clock output pin SD memory card interface SD memory card command output 161 131 107 C14 155 125 101 E13 158 128 104 C13 14 13 10 E5 70 55 47 L5 212 172 140 B3 100 83 67 M11 99 82 66 N11 76 61 53 N6 77 62 54 M6 38 28 23 H3 41 31 26 H6 S_DATA1_0 36 26 21 H2 S_DATA0_0 37 27 22 J1 42 32 27 J5 43 33 28 J4 45 35 30 J2 44 34 29 J3 UDP1 WKUP1 WKUP2 WKUP3 DA0 DA1 VREGCTL VWAKEUP S_CLK_0 S_CMD_0 SD I/F 171 0.5 seconds pulse output pin of real-time clock 174 WKUP0 VBAT 211 LBE 192 C4 214 UHCONX1 D/A converter Pin Number LQP LQS 176 144 USB ch 0 device/host D – pin UDM1 Low power Consumption mode LQQ 216 UDM0 UHCONX0 USB1 Function S_DATA3_0 SD memory card interface SD memory card data bus S_DATA2_0 S_CD_0 S_WP_0 SD memory card interface SD memory card detection pin SD memory card interface SD memory card write protection Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 49 of 200 S6E2C Series Module LQQ 216 Pin Number LQP LQS 176 144 Collision detection 186 154 124 LBE 192 F8 Clock output for Ethernet PHY 190 158 128 A7 E_CRS Carrier detection 187 155 125 B7 E_MDC Management clock 184 152 122 E8 E_MDIO Management data I/O 183 151 121 D8 E_PPS PTP counter monitor 198 166 136 D6 E_RX00 Received data0 181 149 119 F9 E_RX01 Received data1 180 148 118 E9 E_RX02 Received data2 179 147 117 D9 Received data3 Received clock input/ Reference clock Received data enable 178 146 116 B8 185 153 123 A10 182 150 120 C8 Received data error detection 177 145 115 C9 E_TCK Transition clock input 191 159 129 C7 E_TX00 Transition data0 196 164 134 B6 E_TX01 Transition data1 195 163 133 F7 E_TX02 Transition data2 194 162 132 E7 E_TX03 Transition data3 193 161 131 D7 E_TXEN Transition data enable 197 165 135 C6 E_TXER Transition data error detection 192 160 130 A6 I2SMCLK0_0 I2 S external clock pin 51 41 - L2 I2SDO0_0 I2 S serial transition data output pin 52 42 - L3 I2SWS0_0 I2 S frame synchronization signal pin 53 43 - M2 I2SDI0_0 I2 S serial received data input pin 34 24 - G6 I2SCK0_0 I2 S bit clock pin 35 25 - H4 Q_SCK_0 SPI clock output pin 173 143 - D10 172 142 - C10 171 141 - B10 170 140 - D11 Pin Name E_COL E_COUT Ethernet E_RX03 E_RXCK_REF CK E_RXDV E_RXER I2 S Function Q_IO0_0 Q_IO1_0 SPI data input/output pin High-speed Q_IO2_0 quad SPI Q_IO3_0 169 139 - C11 Q_CS0_0 174 144 - B9 175 - - - 176 - - - Q_CS1_0 SPI chip select output pin Q_CS2_0 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 50 of 200 S6E2C Series Module Pin Name Reset INITX MD1 Mode MD0 VCC Function LQQ 216 External reset Input pin A reset is valid when INITX = L. Mode 1 pin During serial programming to flash memory, MD1 = L must be input. Mode 0 pin During normal operation, MD0 = L must be input. During serial programming to flash memory, MD0 = H must be input. Power supply pin Power USBVCC0 USBVCC1 ETHVCC GND VSS 3.3V power supply port for USB I/O Power supply pin for Ethernet I/O GND pin Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Pin Number LQP LQS 176 144 LBE 192 72 57 49 N5 104 84 68 N13 105 85 69 N12 1 1 1 C1 39 29 24 H1 55 45 37 N1 64 54 46 P4 109 89 73 M14 137 - - - 163 133 109 A13 213 173 141 A4 159 129 105 E14 188 156 126 A9 40 30 25 H5 54 44 36 M1 63 53 45 P3 108 88 72 N14 136 - - - 162 132 108 B14 189 157 127 A8 216 176 144 B1 - - - E1 - - - G1 - - - P7 - - - P11 - - - L14 - - - A11 - - - A5 - - - N7 - - - M7 - - - K7 - - - J7 - - - G7 - - - H7 - - - H8 - - - G8 Page 51 of 200 S6E2C Series Module Clock Pin Name LQQ 216 Pin Number LQP LQS 176 144 X0 Main clock (oscillation) input pin 106 86 70 LBE 192 P12 X1 Main clock (oscillation) I/O pin 107 87 71 P13 X0A Sub clock (oscillation) input pin 73 58 50 P5 X1A Sub clock (oscillation) I/O pin 74 59 51 P6 Built-in High-speed CR-oscillation clock output port A/D converter and D/A converter analog power-supply pin A/D converter analog reference voltage input pin A/D converter analog reference voltage input pin VBAT power supply pin Backup power supply (battery etc.) and system power supply A/D converter and D/A converter GND pin Power supply stabilization capacity pin 157 184 127 152 103 122 D13 E8 110 90 74 M13 112 92 76 L13 113 93 77 L12 75 60 52 P8 111 91 75 M12 62 52 44 P2 CROUT_0 CROUT_1 AVCC Analog power Function AVRL AVRH VBAT power VBAT Analog GND AVSS C pin C Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 52 of 200 S6E2C Series 6. I/O Circuit Type Type Circuit Remarks Pull-up resistor P-ch Digital output P-ch X1 N-ch Digital output R It is possible to select the main oscillation/GPIO function. Pull-up resistor control Digital input Standby mode control Clock input Feedback A When the main oscillation is selected: ・ Oscillation feedback resistor: approximately 1 MΩ ・ Standby mode control resistor Standby mode control Digital input Standby mode control Pull-up resistor When the GPIO is selected: ・ CMOS level output. ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control Pull-up resistor B Digital input Document Number: 002-04980 Rev. *E S6E2C Series Datasheet ・ CMOS level hysteresis input ・ Pull-up resistor: approximately 50 kΩ Page 53 of 200 S6E2C Series Type Circuit Remarks Digital input C Digital output N-ch P-ch P-ch E N-ch Digital output Digital output R Pull-up resistor control ・ Open drain output ・ CMOS level hysteresis input CMOS level output CMOS level hysteresis input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. ・ ・ ・ ・ ・ Digital input Standby mode control 0 P-ch P-ch N-ch Digital output Digital output F R Pull-up resistor control Digital input Standby mode control CMOS level output CMOS level hysteresis input Input control Analog input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. ・ ・ ・ ・ ・ ・ ・ Analog input Input control Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 54 of 200 S6E2C Series Type Circuit P-ch Remarks Digital output P-ch G N-ch Digital output R Pull-up resistor control Digital input CMOS level output CMOS level hysteresis input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -12 mA, IOL = 12 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. ・ ・ ・ ・ ・ Standby mode control GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output UDP/Pxx USB Full-speed/Low-speed control UDP input H Differential UDM/Pxx It is possible to select either USB I/O or GPIO function. When the USB I/O is selected: ・ Full-speed, low-speed control Differential input USB/GPIO select UDM input UDM output When the GPIO is selected: ・ CMOS level output ・ CMOS level hysteresis input ・ Standby mode control ・ IOH = -20.5 mA, IOL = 18.5 mA USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 55 of 200 S6E2C Series Type Circuit P-ch Remarks P-ch Digital output I N-ch Digital output R Pull-up resistor control Digital input CMOS level output CMOS level hysteresis input 5 V tolerant Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ Available to control of PZR registers (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part (002-04856). ・ ・ ・ ・ ・ ・ Standby mode control J Mode input P-ch P-ch K N-ch CMOS level hysteresis input Digital output Digital output R ・ CMOS level output ・ TTL level hysteresis input ・ Pull-up resistor control ・Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA Pull-up resistor control Digital input Standby mode control Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 56 of 200 S6E2C Series Type Circuit P-ch Remarks P-ch L N-ch Digital output Digital output Pull-up resistor control R CMOS level output CMOS level hysteresis input Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kΩ ・ IOH = -8 mA, IOL = 8 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. ・ ・ ・ ・ ・ Digital input Standby mode control Pull-up resistor control P-ch P-ch N N-ch R N-ch Digital output Digital output Fast mode control Digital input Standby mode control Document Number: 002-04980 Rev. *E S6E2C Series Datasheet ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA (GPIO) ・ IOL = 20mA (Fast mode Plus) ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part (002-04857). ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Page 57 of 200 S6E2C Series Type Circuit Remarks Pull-up resistor control P-ch P-ch Digital output O N-ch Digital output R Digital input P-ch P-ch X0A P N-ch Pull-up resistor control Digital output Digital output R ・ CMOS level output ・ CMOS level hysteresis input ・ 5 V tolerant ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (MN70900001)”. ・ For I/O setting, refer to VBAT Domain in the FM4 Family Peripheral Manual Main Part (002-04856). ・ CMOS level output ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ For I/O setting, refer to VBAT Domain in the FM4 Family Peripheral Manual Main Part (002-04856). Digital input Standby mode control OSC Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 58 of 200 S6E2C Series Type Circuit Remarks Pull-up resistor control Digital output P-ch X1A P-ch Digital output N-ch Q R Digital input Standby mode control OSC RX Standby mode control It is possible to select the sub oscillation/GPIO function. When the sub oscillation is selected: ・ Oscillation feedback resistor: approximately 10 MΩ When the GPIO is selected: ・ CMOS level output. ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ For I/O setting, refer to VBAT Domain in the FM4 Family Peripheral Manual Main Part (002-04856). Clock input Pull-up resistor control Digital output P-ch P-ch N-ch R Digital output R Digital input ・ CMOS level output ・ CMOS level hysteresis input ・ Analog output ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA (4.5 V to 5.5V) ・ IOH = -2 mA, IOL = 2 mA (2.7 V to 4.5 V) Standby mode control Analog output Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 59 of 200 S6E2C Series Type Circuit P-ch Remarks Pull-up resistor control P-ch Digital output S N-ch Port Drive Select R Digital input ・ CMOS level output ・ (It is possible to select by port drive capability. Select register [PDSR]) ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -10 mA, IOL = 10 mA (PDSR = 1) ・ IOH = -4 mA, IOL = 4 mA (PDSR = 0) ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Standby mode Control Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 60 of 200 S6E2C Series 7. Handling Precautions Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 7.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins that connect semiconductor devices to power supply and I/O functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions, if present for extended periods of time, can damage the device; therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power-supply pin or ground pin. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 61 of 200 S6E2C Series Latch-Up Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred milliamps to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design As previously mentioned, all semiconductor devices have inherent rates of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 7.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason, it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 62 of 200 S6E2C Series Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent this, do the following: 1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. 3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%. 4. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in these aluminum laminate bags for storage. 5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, and the use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 63 of 200 S6E2C Series 7.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of static electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive gases, dust, or oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, including cosmic radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, flame CAUTION: Plastic molded devices are flammable and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 64 of 200 S6E2C Series 8. Handling Devices Power-Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. All of these pins should be connected externally to the power supply or ground lines, however, in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Be sure to connect the current-supply source with the power pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane, as this is expected to produce stable operation. Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board. Sub Crystal Oscillator The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize the oscillation, Cypress recommends a crystal oscillator that meets the following conditions: ◼ Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: approximately 6 pF to 7 pF ◼ Lead type Load capacitance: approximately 6 pF to 7 pF Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 65 of 200 S6E2C Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. ⚫ Example of Using an External Clock Device X0(X0A) Set as external clock input Can be used as general-purpose I/O ports. X1(PE3), X1A (P47) Handling When Using Multi-Function Serial Pin As I2C Pin If the application uses the multi-function serial pin as an I2C pin, the P-channel transistor of the digital output must be disabled. I2C pins need to conform to electrical limitations like other pins, however, and avoid connecting to live external systems with the MCU power off. C Pin Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. Some laminated ceramic capacitors have a large capacitance variation due to thermal fluctuation. Please select a capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of the device. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, the distance between the mode pins and VCC pins or VSS pins is as short as possible, and the connection impedance is low when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. This is important to prevent the device from erroneously switching to test mode as a result of noise. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 66 of 200 S6E2C Series Notes on Power-On Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turn Power-on and Hibernation control is setting and then VCC turns Poweroff. About Hibernation control, see Chapter 7-2: VBAT Domain(B) in FM4 Family Peripheral Manual Main Part (002-04856). Turning on: Turning off: VBAT → VCC → USBVCC0 VBAT → VCC → USBVCC1 VBAT →VCC →ETHVCC VCC → AVCC → AVRH AVRH → AVCC → VCC ETHVCC → VCC → VBAT USBVCC1 → VCC → VBAT USBVCC0 → VCC → VBAT Serial Communication There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial communication. Take care to design the printed circuit board to minimize noise. Consider the case of introducing error as a result of noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Characteristics within the Product Line The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among members of the product line because chip layout and memory structures are not the same; for example, different sizes, flash versus ROM, etc. If you are switching to a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Pin Doubled as Debug Function The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do not use as input. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 67 of 200 S6E2C Series 9. Memory Size See Memory size in 2. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4008_1000 0x4008_0000 0x4007_0000 0x4006_F000 0x4006_E000 0xFFFF_FFFF 0x4006_D000 Reserved 0x4006_C000 Programmable-CRC CAN ch.3 GPIO SD-Card I/F Reserved I2S 0xE010_0000 0xE000_0000 0xD000_0000 Cortex-M4 Private Peripherals Reg. Area Reserved 0x4006_7000 0x4006_6000 0x4006_4000 0x4006_3000 External Device Area 0x4006_2000 0x4006_1000 0x4006_0000 0x6000_0000 0x4005_0000 0x4004_0000 Reserved 0x4400_0000 0x4200_0000 0x4003_F000 0x4003_E000 32 Mbytes Bit band alias 0x4003_D000 0x4003_C800 Ether-Control-Reg. Ether-MAC ch.0 CAN ch.1 CAN ch.0 DSTC DMAC USB ch.1 USB ch.0 EXT-bus I/F Reserved I2S prescaler Reserved Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x4003_C100 Peripherals 0x4000_0000 0x4003_B000 0x4003_A000 Reserved 0x2400_0000 0x2200_0000 0x4003_9000 0x4003_8000 32 Mbytes Bit band alias DualFlash 0x200F_0000 0x4003_7000 0x4003_6000 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 Reserved 0x2004_8000 メモリサイズの 詳細は 次項の「●メモリマップ(2)」 を参照してください。 0x2004_0000 0x2003_8000 0x2000_0000 0x1FFF_0000 0x0050_0000 0x0040_0000 0x4003_0000 0x4002_F000 SRAM2 SRAM1 Reserved SRAM0 Reserved Security/CR Trim MainFlash 0x0000_0000 0x4003_1000 0x4002_E000 RTC/Port Ctrl Watch Counter CRC MFS CAN prescaler USB Clock ctrl LVD/DS mode Reserved D/AC Reserved Int-Req.Read EXTI Reserved CR Trim Reserved 0x4002_8000 0x4002_7000 A/DC QPRC Base Timer PPG Reserved MFT Unit2 MFT Unit1 MFT Unit0 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_3000 0x4002_2000 0x4002_1000 0x4002_0000 Reserved 0x4001_6000 Dual Timer 0x4001_5000 Reserved 0x4001_3000 SW WDT HW WDT Clock/Reset 0x4001_2000 0x4001_1000 0x4001_0000 Reserved 0x4000_1000 0x4000_0000 Document Number: 002-04980 Rev. *E MainFlash I/F S6E2C Series Datasheet Page 68 of 200 S6E2CxAH/J/L S6E2Cx9H/J/L 0x2020_0000 S6E2Cx8H/J/L 0x2020_0000 0x2020_0000 S6E2C Series Reserved Reserved Reserved Memory Map (2) *: See S6E2Cx Series Flash Programming Manual to confirm the details of flash memory. 0x2004_8000 0x2004_8000 0x2004_0000 SRAM2 32 Kbytes 0x2003_8000 SRAM1 32 Kbytes 0x2004_8000 0x2004_0000 SRAM2 32 Kbytes 0x2004_0000 SRAM2 32 Kbytes 0x2003_8000 SRAM1 32 Kbytes 0x2003_8000 SRAM1 32 Kbytes Reserved Reserved 0x2000_0000 Reserved 0x2000_0000 0x2000_0000 SRAM0 128 Kbytes SRAM0 192 Kbytes 0x1FFF_0000 SRAM0 64 Kbytes 0x1FFE_0000 0x1FFD_0000 0x0040_0000 0x0040_6000 0x0040_4000 0x0040_2000 0x0040_0000 SA0-3(#1) (8KBx4) 0x0040_8000 SA3(#0) (8KB) General purpose CR trimming Security 0x0040_6000 0x0040_4000 0x0040_2000 0x0040_0000 40 Kbytes 0x0040_2000 SA0-3(#1) (8KBx4) 0x0040_8000 0x0041_0000 MainFlash 0x0040_4000 0x0041_0000 40 Kbytes 0x0040_6000 SA3(#0) (8KB) General purpose CR trimming Security Reserved Reserved MainFlash SA0-3(#1) (8KBx4) 0x0040_8000 40 Kbytes 0x0041_0000 MainFlash Reserved SA3(#0) (8KB) General purpose CR trimming Security Reserved Reserved 0x0020_0000 Reserved 0x0018_0000 0x0000_0000 SA8(#0) (32KB) SA4-7(#0) (8KBx4) SA9-23(#0) (64KBx15) 0x0000_0000 Document Number: 002-04980 Rev. *E SA8(#0) (32KB) SA4-7(#0) (8KBx4) SA9-23(#0) (64KBx15) 0x0000_0000 S6E2C Series Datasheet 1 Mbytes SA9-23(#0) (64KBx15) 0x0010_0000 MainFlash 0x0010_0000 SA9-15(#1) (64KBx7) SA8(#1) (32KB) SA4-7(#1) (8KBx4) MainFlash 1.5 Mbytes 2 Mbytes 0x0010_0000 SA8(#1) (32KB) SA4-7(#1) (8KBx4) MainFlash SA9-23(#1) (64KBx15) SA8(#0) (32KB) SA4-7(#0) (8KBx4) Page 69 of 200 0x2018_0000 0x2010_0000 0x200F_8000 SA8(#1) (32KB) SA4-7(#1) (8KBx4) SA0-3(#1) (8KBx4) 0x2010_0000 0x200F_8000 0x2020_0000 Reserved SA9-15(#1) (64KBx7) SA8(#1) (32KB) SA4-7(#1) (8KBx4) SA0-3(#1) (8KBx4) 0x200F_8000 0x2004_0000 0x2003_8000 0x2004_0000 0x2003_8000 Reserved 0x2004_0000 0x2003_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes Reserved 0x2000_0000 0x2000_0000 SRAM0 128 Kbytes SRAM0 192 Kbytes SA0-3(#1) (8KBx4) 0x2004_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes Reserved 0x2000_0000 S6E2C Series Reserved 0x2004_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes Reserved 0x2010_0000 Reserved Memory Map (2) During Dual Flash modeReserved 0x2004_8000 S6E2Cx8H/J/L DualFlash 32 Kbytes SA9-23(#1) (64KBx15) +32 Kbytes 0x2020_0000 S6E2Cx9H/J/L DualFlash DualFlash 0x2020_0000 s +32 Kbytes S6E2CxAH/J/L 0x1FFF_0000 SRAM0 64 Kbytes 0x1FFE_0000 0x1FFD_0000 0x0040_4000 0x0040_2000 0x0040_0000 Reserved 0x0040_2000 0x0040_0000 0x0010_0000 0x0000_0000 Document Number: 002-04980 Rev. *E SA9-23(#0) (64KBx15) SA8(#0) (32KB) SA4-7(#0) (8KBx4) SA3(#0) (8KB) General purpose CR trimming / HTM Security Reserved 1 Mbytes SA8(#0) (32KB) SA4-7(#0) (8KBx4) 0x0040_4000 MainFlash 0x0000_0000 1 Mbytes SA9-23(#0) (64KBx15) 0x0040_6000 Reserved MainFlash 0x0010_0000 SA3(#0) (8KB) General purpose CR trimming / HTM Security 1 Mbytes 0x0040_0000 0x0040_6000 Reserved 0x0040_8000 MainFlash 0x0040_2000 SA3(#0) (8KB) General purpose CR trimming / HTM Security 0x0040_8000 0x0041_0000 MainFlash 0x0040_4000 Reserved 8 Kbytes 0x0040_6000 0x0041_0000 MainFlash 0x0040_8000 Reserved Reserved 8 Kbytes Reserved MainFlash 0x0041_0000 8 Kbytes Reserved 0x0010_0000 0x0000_0000 S6E2C Series Datasheet SA9-23(#0) (64KBx15) SA8(#0) (32KB) SA4-7(#0) (8KBx4) Page 70 of 200 S6E2CxAH 0xD000_0000 S6E2CxAJ 0xD000_0000 S6E2CxAL 0xD000_0000 Hi-Speed Quad SPI 256 Mbytes 0xC000_0000 0xC000_0000 MemoryReserved Map (3) 0x8000_0000 Hi-Speed Quad SPI 256 Mbytes S6E2C 0xC000_0000 Reserved 0x8000_0000 Reserved 0x8000_0000 SDRAM 256 Mbytes 0x7000_0000 0x7000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes 0x6000_0000 SDRAM 256 Mbytes 0x7000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes 0x6000_0000 Document Number: 002-04980 Rev. *E Series SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes 0x6000_0000 S6E2C Series Datasheet Page 71 of 200 S6E2C Series Peripheral Address Map Start Address End Address Bus Peripherals 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4001_0000 0x4000_FFFF 0x4001_0FFF 0x4001_1000 0x4001_2000 0x4001_1FFF 0x4001_2FFF 0x4001_3000 0x4001_5000 0x4001_4FFF 0x4001_5FFF 0x4001_6000 0x4002_0000 0x4001_FFFF 0x4002_0FFF Reserved 0x4002_1000 0x4002_2000 0x4002_3000 0x4002_4000 0x4002_1FFF 0x4002_2FFF 0x4002_3FFF 0x4002_4FFF Multi-Function Timer unit 1 0x4002_5000 0x4002_6000 0x4002_5FFF 0x4002_6FFF 0x4002_7000 0x4002_8000 0x4002_7FFF 0x4002_DFFF A/D converter 0x4002_E000 0x4002_F000 0x4002_EFFF 0x4002_FFFF Internal CR trimming 0x4003_0000 0x4003_1000 0x4003_0FFF 0x4003_1FFF External interrupt controller 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_2FFF 0x4003_3FFF 0x4003_4FFF 0x4003_57FF Reserved 0x4003_5800 0x4003_6000 0x4003_5FFF 0x4003_6FFF Deep standby mode Controller 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_B000 0x4003_C000 0x4003_BFFF 0x4003_C0FF RTC/port control 0x4003_C100 0x4003_C800 0x4003_D000 0x4003_E000 0x4003_F000 0x4003_C7FF 0x4003_CFFF 0x4003_DFFF 0x4003_EFFF 0x4003_FFFF Peripheral clock gating Document Number: 002-04980 Rev. *E AHB MainFlash I/F register Reserved Clock/reset control Hardware watchdog timer APB0 Software watchdog timer Reserved Dual-timer Multi-Function Timer unit 0 Multi-Function Timer unit 1 Reserved PPG APB1 Base timer Quadrature position/revolution counter Reserved Reserved Interrupt request batch-read function D/A converter Reserved Low voltage detector USB clock generator APB2 CAN prescaler Multi-function serial interface CRC Watch counter Low-speed CR prescaler Reserved I2S prescaler Reserved External memory interface S6E2C Series Datasheet Page 72 of 200 S6E2C Series Start Address 0x4004_0000 0x4005_0000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_3000 0x4006_4000 0x4006_6000 0x4006_7000 0x4006_C000 0x4006_D000 0x4006_E000 0x4006_F000 0x4007_0000 0x4008_0000 0x4008_1000 0x200E_0000 0xD000_0000 End Address 0x4004_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_1FFF 0x4006_2FFF 0x4006_3FFF 0x4006_5FFF 0x4006_6FFF 0x4006_BFFF 0x4006_CFFF 0x4006_DFFF 0x4006_EFFF 0x4006_FFFF 0x4007_FFFF 0x4008_0FFF 0x41FF_FFFF 0x200E_FFFF 0xDFFF_FFFF Document Number: 002-04980 Rev. *E Bus AHB Peripherals USB ch 0 USB ch 1 DMAC register DSTC register CAN ch 0 CAN ch 1 Ethernet-MAC ch 0 Ethernet-MAC setting register Reserved I2 S Reserved SD card I/F GPIO CAN-FD (CAN ch 2) Programmable-CRC Reserved Workflash I/F register High-speed quad SPI control register S6E2C Series Datasheet Page 73 of 200 S6E2C Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings: ◼ INITX = 0 This is the period when the INITX pin is at the L level. ◼ INITX = 1 This is the period when the INITX pin is at the H level. ◼ SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. ◼ SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. ◼ Input enabled Indicates that the input function can be used. ◼ Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. ◼ Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. ◼ Setting disabled Indicates that the setting is disabled. ◼ Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. ◼ Analog input is enabled Indicates that the analog input is enabled. ◼ Trace output Indicates that the trace function can be used. ◼ GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. ◼ Setting prohibition Prohibition of a setting by specification limitation Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 74 of 200 S6E2C Series Pin Status Type List of Pin Behavior by Mode State Device Internal Reset State Run mode or Sleep mode State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Power Supply Stable INITX=1 ‐ Setting Setting Setting disabled disabled disabled Maintain previous state Maintain previous state HiZ/internal input fixed at 0 Input Input enabled enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input Enabled GPIO selected Setting Setting Setting disabled disabled disabled Maintain previous state Maintain previous state HiZ/internal input fixed at 0 GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected External main clock input selected Setting Setting Setting disabled disabled disabled Maintain previous state Maintain previous state HiZ/internal input fixed at 0 Maintain previous state HiZ/internal input fixed at 0 Maintain previous State Function Group GPIO selected A B Power-On Reset or LowVoltage Detection State Main crystal oscillator input pin/ Input external enabled main clock input selected INITX Input State Timer mode, RTC mode, or Stop mode State Return from Deep Standby RTC Deep mode or Deep Standby Standby Stop mode State mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 GPIO Hiselected, Z/internal internal input fixed input fixed at 0 at 0 Power Supply Stable INITX=1 GPIO selected Main crystal oscillator output pin Hi-Z/ internal input fixed at 0/ or input enable Hi-Z/ internal input fixed at 0 C INITX input pin Pull-up/ input enabled Pull-up/ Pull-up/ Input Input enabled enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled D Mode input pin Input enabled Input Input enabled enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input Input enabled enabled Input enabled Hi-Z/ input enabled Input enabled Hi-Z/ input enabled Input enabled Setting Setting Setting disabled disabled disabled Input enabled Maintain previous state Input enabled GPIO selected Input enabled Maintain previous state E Hi-Z/ internal input fixed at 0 Maintain previous state while oscillator active/ When oscillation stops1, it will be Hi-Z/ Internal input fixed at 0 GPIO selected GPIO selected 1 Oscillation is stopped at Sub Timer mode, sub CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 75 of 200 Pin Status Type S6E2C Series Function Group NMIX selected F Power-On Reset or LowVoltage Detection State Device Internal Reset State Run mode or Sleep mode State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Power Supply Stable INITX=1 ‐ INITX Input State Setting Setting Setting disabled disabled disabled Resource other than above selected GPIO selected Hi-Z Hi-Z/ Hi-Z/ input input enabled enabled JTAG selected Hi-Z Pull-up/ Pull-up/ input input enabled enabled G GPIO selected JTAG selected H I Resource other than above selected GPIO selected Resource selected GPIO selected Setting Setting Setting disabled disabled disabled Hi-Z Maintain previous state J 2 3 Hi-Z Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 Maintain previous state Maintain previous Hi-Z/ state internal input fixed at 0 INITX=1 SPL=0 SPL=1 Maintain previous state Hi-Z/ Hi-Z/ input input enabled enabled Hi-Z/ Hi-Z/ input input enabled enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z/ internal input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/ internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state Maintain previous state Maintain previous state HiZ/Internal input fixed at 0 GPIO selected, internal input fixed at 0 HiZ/Internal input fixed at 0 GPIO selected GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state HiZ/Internal input fixed at 0 2 3 Maintain previous state Power Supply Stable INITX=1 Maintain previous state Hi-Z/ WKUP input enabled Maintain previous state Maintain previous state Return from Deep Standby mode State WKUP input enabled Maintain previous state Analog output selected External interrupt enable selected Resource other than above selected Deep Standby RTC mode or Deep Standby Stop mode State Pull-up/ Pull-up/ input input enabled enabled Setting Setting Setting disabled disabled disabled Hi-Z Maintain previous state Timer mode, RTC mode, or Stop mode State Maintain previous state HiZ/internal input fixed at 0 GPIO selected Maintain previous state at Timer mode. GPIO selected internal input fixed at 0 at RTC mode, Stop mode. Maintain previous state at Timer mode. Hi-Z/internal input fixed at 0 at RTC mode, Stop mode.. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 76 of 200 Pin Status Type S6E2C Series K Function Group GPIO selected External interrupt enable selected Resource other than above selected GPIO selected Analog input selected Power-On Reset or LowVoltage Detection State Device Internal Reset State Run mode or Sleep mode State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Power Supply Stable INITX=1 ‐ Analog input selected M External interrupt enable selected Resource other than above selected GPIO selected Timer mode, RTC mode, or Stop mode State Deep Standby RTC mode or Deep Standby Stop mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Maintain previous state Setting Setting Setting disabled disabled disabled Maintain previous state Maintain previous state HiZ/internal input fixed at 0 Return from Deep Standby mode State Power Supply Stable INITX=1 - GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected Hi-Z Hi-Z/ Hi-Z/ input input enabled enabled Hi-Z Hi-Z/ Hi-Z/ internal internal input input fixed at fixed at 0/ 0/ analog analog input input enabled enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Setting Setting Setting disabled disabled disabled Maintain previous state Maintain previous state HiZ/internal input fixed at 0 GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected Hi-Z/ Hi-Z/ internal internal input input fixed fixed at 0/ at 0/ analog analog input input enabled enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected L Resource other than above selected GPIO selected INITX Input State Hi-Z Maintain previous state Setting Setting Setting disabled disabled disabled Document Number: 002-04980 Rev. *E Maintain previous state Maintain previous state S6E2C Series Datasheet HiZ/internal input fixed at 0 Page 77 of 200 Pin Status Type S6E2C Series Function Group Analog input selected N Trace selected Resource other than above selected GPIO selected Analog input selected O Trace selected External interrupt enable selected Resource other than above selected GPIO selected Power-On Reset or LowVoltage Detection State Device Internal Reset State Run mode or Sleep mode State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Hi-Z/ Hi-Z/ internal internal input input fixed fixed Hi-Z at0/ at 0/ analog analog input input enabled enabled Power Supply Stable INITX=1 ‐ Hi-Z/ internal input fixed at 0/ analog input enabled INITX Input State Timer mode, RTC mode, or Stop mode State Deep Standby RTC mode or Deep Standby Stop mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Trace output Setting Setting Setting disabled disabled disabled Maintain previous state Maintain previous state Hi-Z/ Hi-Z/ internal internal input input fixed fixed at 0/ at 0/ analog analog input input enabled enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z HiZ/internal input fixed at 0 Hi-Z/ internal input fixed at 0/ analog input enabled Return from Deep Standby mode State Power Supply Stable INITX=1 - Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected Trace output Setting Setting Setting disabled disabled disabled Document Number: 002-04980 Rev. *E Maintain previous state Maintain previous state S6E2C Series Datasheet Maintain previous state HiZ/internal input fixed at 0 Page 78 of 200 Pin Status Type S6E2C Series Function Group Analog input selected P Power-On Reset or LowVoltage Detection State Device Internal Reset State Run mode or Sleep mode State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Hi-Z/ Hi-Z/ internal internal input input fixed at fixed at Hi-Z 0/ 0/ analog analog input input enabled enabled Power Supply Stable INITX=1 ‐ Hi-Z/ internal input fixed at 0/ analog input enabled INITX Input State Timer mode, RTC mode, or Stop mode State Deep Standby RTC mode or Deep Standby Stop mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Hi-Z/ internal input fixed at 0/ analog input enabled WKUP enabled Resource other than above selected GPIO selected Setting Setting Setting disabled disabled disabled Maintain previous state Maintain previous state WKUP enabled Q External interrupt enable selected Resource other than above selected Maintain previous state Hi-Z Hi-Z/ Hi-Z/ input input enabled enabled Hi-Z Hi-Z/ Hi-Z/ input input enabled enabled GPIO selected Hi-Z/ internal input fixed at 0/ analog input enabled Maintain previous state WKUP input enabled Hi-Z/ WKUP input enabled HiZ/internal input fixed at 0 GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 WKUP input enabled Hi-Z/ WKUP input enabled WKUP input enabled GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected HiZ/internal input fixed at 0 GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected Hi-Z at transmission/ input enabled/ internal input fixed at 0 at reception Hi-Z/ input enabled Hi-Z/ input enabled Hi-Z/ input enabled HiZ/internal input fixed at 0 Maintain previous state Maintain previous state Hi-Z at Hi-Z at transtransR mission/ mission/ input input Setting Setting Setting enabled/ USB I/O pin enabled/ disabled disabled disabled internal internal input input fixed fixed at 0 at at 0 at reception reception Document Number: 002-04980 Rev. *E Hi-Z/ internal input fixed at 0/ analog input enabled Maintain previous state GPIO selected S6E2C Series Datasheet Power Supply Stable INITX=1 - Hi-Z/ internal input fixed at 0/ analog input enabled Maintain previous state Setting Setting Setting disabled disabled disabled Return from Deep Standby mode State Hi-Z/ internal input fixed at 0/ analog input enabled GPIO selected Page 79 of 200 Pin Status Type S6E2C Series Function Group Power-On Reset or LowVoltage Detection State Device Internal Reset State Run mode or Sleep mode State Power Power Supply Supply Stable Unstable ‐ INITX=0 INITX=1 ‐ ‐ ‐ Power Supply Stable INITX=1 ‐ INITX Input State Timer mode, RTC mode, or Stop mode State Deep Standby RTC mode or Deep Standby Stop mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 V Hi-Z Hi-Z/ Hi-Z/ input input enabled enabled Maintain previous state Maintain previous state GPIO selected Ethernet input/output selected4 W 4 External interrupt enable selected Resource other than above selected GPIO selected HiZ/internal input fixed at 0 Maintain previous state Setting Setting Setting disabled disabled disabled Maintain previous state Hi-Z Power Supply Stable INITX=1 - Maintain previous state Ethernet I/O Setting Setting Setting selected4 disabled disabled disabled Resource other than above selected Return from Deep Standby mode State Maintain previous state HiZ/internal input fixed at 0 Hi-Z/ Hi-Z/ input input enabled enabled GPIO selected, internal input fixed at 0 HiZ/internal input fixed at "0 GPIO selected GPIO selected, internal input fixed at 0 HiZ/internal input fixed at 0 GPIO selected It shows the case selected by EPFR14.E_SPLC register Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 80 of 200 S6E2C Series VBAT Pin Status Type List of VBAT Domain Pin Status INITX Input State Power Supply Unstabl e Power Supply Stable Function Group ‐ ‐ INITX=0 ‐ Maintain GPIO Setting previous selected disabled state Sub crystal S oscillator input pin/ Input Input external enabled enabled sub clock input selected Maintain GPIO Setting previous selected disabled state External Maintain sub clock Setting previous input disabled state selected T Hi-Z/ Sub internal crystal input Maintain oscillator fixed at previous output 0/ state pin or input enable Resource selected U Hi-Z GPIO selected Run Device mode Internal or Reset Sleep State mode State Poweron reset5 INITX=1 ‐ Timer mode, RTC mode, or Stop mode State Return Deep Standby from VBAT RTC mode or Deep RTC Deep Standby Standby mode Stop mode state mode State State Power Supply Stable Power Supply Stable Power Supply Stable INITX=1 ‐ INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Power Power Supply Supply Stable Stable INITX=1 - - VBAT RTC mode State Power Supply Stable - Maintain Maintain Maintain Maintain Maintain Maintain Maintain Setting previous previous previous previous previous previous previous prohibitio state state state state state state state n Input Input Input Input enabled enabled enabled enabled Return from - Maintain Maintain Input Input Input previous previous enabled enabled enabled state state Maintain Maintain Maintain Maintain Maintain Maintain Maintain Setting previous previous previous previous previous previous previous prohibitio state state state state state state state n - Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous previous previous previous state state state state state state state state state Maintain Maintain Maintain Maintain previous previous previous previous Maintain Maintain state/ state/ state/ state/ Maintain Maintain Maintain previous previous When When When When previous previous previous state state oscillation oscillation oscillation oscillation state state state stops, stops, stops, stops, Hi-Z6 Hi-Z6 Hi-Z6 Hi-Z6 Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous previous previous previous previous state state state state state state state state state state 5 When VBAT and VCC power on. When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous state. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop mode. 6 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 81 of 200 S6E2C Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage7,8 Min Rating Max Unit VCC VSS - 0.5 VSS + 6.5 V Power supply voltage (for USB)7,9 USBVCC0 VSS - 0.5 VSS + 6.5 V Power supply voltage (for USB) 7, 9 USBVCC1 VSS - 0.5 VSS + 6.5 V ETHVCC VSS - 0.5 VSS + 6.5 V Power supply voltage (for Ethernet-MAC) 7, 10 Power supply voltage (VBAT) 7 ,11 VBAT VSS - 0.5 VSS + 6.5 V Analog power supply voltage 7, 12 AVCC VSS - 0.5 VSS + 6.5 V AVRH VSS - 0.5 VSS + 6.5 V Analog reference voltage 7 ,12 VSS - 0.5 VSS - 0.5 Input voltage 7 VI VSS - 0.5 VSS - 0.5 VSS - 0.5 Analog pin input voltage 7 VIA VSS - 0.5 Output voltage 7 VO VSS - 0.5 L level maximum output current13 L level average output current14 L level total maximum output current L level total maximum output current H level maximum output current 13 15 IOL - IOLAV - ∑IOL ∑IOLAV - IOH - Remarks VCC + 0.5 (≤ 6.5V) USBVCC0 + 0.5 (≤ 6.5V) USBVCC1 + 0.5 (≤ 6.5V) ETHVCC + 0.5 (≤ 6.5V) VSS + 6.5 AVCC + 0.5 (≤ 6.5V) VCC + 0.5 (≤ 6.5V) 10 20 20 20 22.4 4 8 10 12 20 100 50 - 10 V Except for USB and Ethernet-MAC pin V USB ch 0 pin V USB ch 1 pin V Ethernet-MAC Pin V 5V tolerant mA mA mA mA mA mA mA mA mA mA mA mA mA 4 mA type 8 mA type 10 mA type 12 mA type I2C Fm+ 4 mA type 8 mA type 10 mA type 12 mA type I2C Fm+ -20 mA 8 mA type - 20 - 20 mA mA 10 mA type 12 mA type V V 4 mA type 7 These parameters are based on the condition that VSS = AVSS = 0.0V. VCC must not drop below VSS - 0.5V. 9 USBVCC0, USBVCC1 must not drop below VSS - 0.5V. 10 ETHVCC must not drop below VSS - 0.5V. 11 VBAT must not drop below VSS - 0.5V. 12 Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on. 13 The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. 14 The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. 15 The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms period. 8 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 82 of 200 S6E2C Series Parameter H level average output current 14 Symbol IOHAV Min - Rating Max -4 -8 - 10 - 12 - 100 - 50 200 + 150 Unit mA mA mA mA mA mA mW °C Remarks 4 mA type 8 mA type 10 mA type 12 mA type H level total maximum output current ∑IOH H level total average output current 15 ∑IOHAV Power consumption PD Storage temperature TSTG - 55 WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 83 of 200 S6E2C Series 12.2 Recommended Operating Conditions Parameter Power supply voltage Symbol Conditions VCC - Value Min Max 5.5 2.7 16 3.0 Power supply voltage (for USB ch 0) Power supply voltage (for USB ch 1) Power supply voltage (for EthernetMAC) USBVCC0 USBVCC1 ETHVCC V 2.7 5.5 (≤VCC) 3.0 3.6 (≤VCC) - V 2.7 5.5 (≤VCC) 3.0 3.6 (≤VCC) 4.5 5.5 (≤VCC) - Analog reference voltage Operating temperature 16 17 Junction temperature Ambient temperature VBAT AVCC AVRH AVRL TJ TA - V 1.65 2.7 17 AVSS - 40 -40 5.5 (≤VCC) 5.5 5.5 AVCC AVSS + 125 18 Remarks V 3.6 (≤VCC) - 2.7 Power supply voltage (VBAT) Analog power supply voltage Unit V V V V °C °C When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0) When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80) When P83/UDP1 and P82/UDM1 pins are used as USB (UDP1, UDM1) When P83/UDP1 and P82/UDM1 pins are used as GPIO (P83, P82) When the pins in Ethernet-MAC Pins, except the P6E/ADTG_5/SCK4_1/I C23_1/INT29_0/E_PPS pin, are used as Ethernet-MAC pins When the pins in Ethernet-MAC Pins, except the P6E/ADTG_5/SCK4_1/I C23_1/INT29_0/E_PPS pin, are used as Ethernet-MAC pins AVCC = VCC For the voltage range between VCC(min) and the low voltage detection reset (VDH), the MCU must be clocked from either the High-speed CR or the low-speed CR. The minimum value of analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5 12-bit A/D Converter for the details. 18 The maximum temperature of the ambient temperature (T ) can guarantee a range that does not exceed the A junction temperature (TJ). The calculation formula of the ambient temperature (TA) is: TA (Max) = TJ(Max) - Pd(Max) × θJA Pd: θJA: Power dissipation (W) Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: IOH: L level output current H level output current VOL: VOH: L level output voltage H level output voltage Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 84 of 200 S6E2C Series Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for Package Thermal Resistance and Maximum Permissible Power Thermal Maximum Permissible Power Printed Circuit Resistance (mW) Package Board θja TA = +85 °C TA = +105 °C (°C/W) Single-layered 48 833 417 LQS144 both sides (0.5-mm pitch) 4 layers 33 1212 606 Single-layered 45 889 444 LQP176 both sides (0.5-mm pitch) 4 layers 31 1290 645 Single-layered 46 870 435 LQQ216 both sides (0.4-mm pitch) 4 layers 32 1250 625 Single-layered LBE192 both sides (0.8-mm pitch) 4 layers 35 1143 571 WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. − No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 85 of 200 S6E2C Series Ethernet-MAC Pins 19 Pin Name Ethernet-MAC Function P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS PC0/E_RXER PC1/TIOB6_0/E_RX03 PC2/TIOA6_0/E_RX02 PC3/TIOB7_0/E_RX01 PC4/TIOA7_0/E_RX00 PC5/TIOB14_0/E_RXDV PC6/TIOA14_0/E_MDIO PC7/INT13_0/E_MDC/CROUT_1 PC8/E_RXCK_REFCK PC9/TIOB15_0/E_COL PCA/TIOA15_0/E_CRS PCB/INT28_0/E_COUT PCC/E_TCK PCD/SOT4_1/INT14_0/E_TXER PCE/SIN4_1/INT15_0/E_TX03 PCF/RTS4_1/INT12_0/E_TX02 PD0/INT30_1/E_TX01 PD1/INT31_1/E_TX00 PD2/CTS4_1/FRCK2_1/E_TXEN E_PPS 19 E_RXER E_RX03 E_RX02 E_RX01 E_RX00 E_RXDV E_MDIO E_MDC E_RXCK_REFCK E_COL E_CRS E_COUT E_TCK E_TXER E_TX03 E_TX02 E_TX01 E_TX00 E_TXEN Except For Ethernet-MAC Function P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PC0 PC1/TIOB6_0 PC2/TIOA6_0 PC3/TIOB7_0 PC4/TIOA7_0 PC5/TIOB14_0 PC6/TIOA14_0 PC7/INT13_0/CROUT_1 PC8 PC9/TIOB15_0 PCA/TIOA15_0 PCB/INT28_0 PCC PCD/SOT4_1/INT14_0 PCE/SIN4_1/INT15_0 PCF/RTS4_1/INT12_0 PD0/INT30_1 PD1/INT31_1 PD2/CTS4_1/FRCK2_1 Power Supply Type VCC ETHVCC It is used to confirm the PTP counter cycle in Ethernet-MAC by waveforms. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 86 of 200 S6E2C Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage ICC is the current drawn by the device. It can be analyzed as follows. ICC = ICC (INT) + ΣICC (IO) ICC (INT): Current drawn by internal logic and memory, etc. through the regulator ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin For ICC (INT), it can be anticipated by "(1) Current Rating" in "12.3. DC Characteristics" (This rating value does not include ICC (IO) for a value at pin fixed). For ICC (IO), it depends on system used by customers. The calculation formula is shown below. ICC (IO) = (CINT + CEXT) × VCC × fSW CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Pin internal load capacitance CINT Conditions Capacitance Value 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself: Measure current value ICC (Typ) at normal temperature (+25°C). Add maximum leakage current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC (Typ) + ICC (leak_max) Parameter Symbol Maximum leakage current at operating ICC (leak_max) Document Number: 002-04980 Rev. *E Conditions TJ = +125 °C TJ = +105 °C TJ = +85 °C S6E2C Series Datasheet Current Value 79.2 mA 39.4 mA 26.5 mA Page 87 of 200 S6E2C Series Current Explanation Diagram Pd=VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC=ICC (INT)＋ΣICC (IO) VCC A ICC Chip ICC (INT) ΣICC (IO) A Regulator VOL V A ・・・ V IOL Flash VOH ・・・ Logic IOH RAM ICC (IO) CEXT ・・・ Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 88 of 200 S6E2C Series 12.3 DC Characteristics 12.3.1 Current Rating Table 12-1 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Value Pin Parameter Symbol Conditions Frequency20 Unit Remarks 21 Name Typ Max22 25 27 Power supply current ICC VCC Normal operation23 , 24 (PLL) 25 27 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 117 113 106 95 86 73 61 50 39 27 16 8.7 6.4 71 68 64 58 52 44 38 31 24 17 10 6.3 5.0 224 219 211 197 186 169 155 140 126 112 97 88.9 86.1 168 165 159 151 144 134 126 117 109 100 91 86.1 84.5 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 26 When all peripheral clocks are on 26 When all peripheral clocks are off 20 Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 TA = +25 °C, VCC = 3.3V 22 TJ = +125 °C, VCC = 5.5V 23 Firmware being executed during data collection for this table is not being accessed from the MainFlash memory. 24 When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) 25 When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1) 26 When all ports are fixed 27 When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) 21 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 89 of 200 S6E2C Series Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Value Pin Parameter Symbol Conditions Frequency28 Unit Remarks 29 Name Typ Max30 33 35 Power supply current ICC VCC Normal operation31 ,32 (PLL) 33 35 28 29 30 31 32 33 34 35 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 128 123 116 102 93 79 67 54 42 30 17 9.2 6.7 74 71 67 59 53 45 39 32 25 18 11 6.5 5.1 236 230 221 205 193 175 161 145 130 115 99 90.0 86.9 170 167 162 152 145 135 127 118 110 101 92 86.8 85.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 34 When all peripheral clocks are on 34 When all peripheral clocks are off Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK TA = +25 °C, VCC = 3.3V TJ = +125 °C, VCC = 5.5V With data access to a MainFlash memory. When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 0) When all ports are fixed When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 90 of 200 S6E2C Series Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Conditions 41 Power supply current ICC VCC Normal operation 39, 40 (PLL) 41 36 37 38 39 40 41 42 Frequency36 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz Value Typ37 Max38 71 62 51 40 29 17 13 8.4 46 41 34 27 20 12 9.4 6.5 161 150 138 125 112 98 93 88.5 132 125 118 110 102 93 89.7 86.4 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks 42 When all peripheral clocks are on 42 When all peripheral clocks are off Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK TA = +25 °C, VCC = 3.3 V TJ = +125 °C, VCC = 5.5 V With data access to a MainFlash memory. When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) When all ports are fixed Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 91 of 200 S6E2C Series Table 12-4 Typical and Maximum Current Consumption in Normal Operation (Other than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Conditions Frequency43 Value Unit Typ44 Max45 4.7 84.9 mA 3.9 83.8 mA 3.0 83.2 mA 2.1 82.0 mA 0.78 80.37 mA 0.77 80.36 mA 0.81 80.39 mA 0.78 80.38 mA Remarks 49 Normal operation 46, 47 (main oscillation) 48 4 MHz 49 Power supply current ICC VCC (built-in High-speed CR) When all peripheral clocks are off 49 Normal operation 46 When all peripheral clocks are on 48 4 MHz When all peripheral clocks are on 49 When all peripheral clocks are off 49 Normal operation 46, 50 (sub oscillation) 48 32 kHz When all peripheral clocks are on 49 When all peripheral clocks are off 49 Normal operation 46 48 100 kHz (built-in low-speed CR) 43 44 45 46 47 48 49 50 When all peripheral clocks are on 49 When all peripheral clocks are off Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 TA = +25 °C, VCC = 3.3V TJ = +125 °C, VCC = 5.5V With data access to a MainFlash memory. When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) When all ports are fixed When using a 32 kHz crystal oscillator (including the current consumption of the oscillation circuit) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 92 of 200 S6E2C Series Table 12-5 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current 51 52 53 54 55 Symbol ICCS Pin Name VCC Conditions Frequency51 Sleep operation54 (PLL) 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 200 MHz 192 MHz 180 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz Value Typ52 Max53 88 85 80 72 65 55 47 38 30 21 12 7.4 5.8 44 42 40 36 33 28 24 20 16 12 7.6 5.2 4.4 188 184 178 164 156 144 134 124 114 104 93 87.2 85.2 134 132 129 123 119 113 108 103 98 93 87.6 84.7 83.7 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks 55 When all peripheral clocks are on 55 When all peripheral clocks are off Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 TA = +25°C, VCC = 3.3V TJ = +125°C, VCC = 5.5V When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) When all ports are fixed Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 93 of 200 S6E2C Series Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Power supply current 56 57 58 59 60 Symbol ICCS Pin Name VCC Conditions Frequency56 Sleep operation59 (PLL) 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz Value Typ57 Max58 45 38 31 24 18 11 8.6 6.3 20 18 15 12 9.1 6.5 5.5 4.6 130 122 114 106 99 91 88.3 85.7 103 99 96 93 89.3 86.1 84.9 83.8 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks 60 When all peripheral clocks are on 60 When all peripheral clocks are off Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK TA = +25°C, VCC = 3.3V TJ = +125°C, VCC = 5.5V When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) When all ports are fixed Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 94 of 200 S6E2C Series Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (Other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Frequency61 Value Unit Typ62 Max63 3.4 82.6 mA 2.5 81.7 mA 2.5 81.7 mA 1.7 80.9 mA Remarks 65 Sleep operation64 (main oscillation) When all peripheral clocks are on 4 MHz 65 When all peripheral clocks are off 65 Power supply current ICCS VCC Sleep operation (built-in High-speed CR) 4 MHz When all peripheral clocks are on 65 When all peripheral clocks are off 65 Sleep operation66 (sub oscillation) 0.75 79.97 mA 0.74 79.96 mA 0.79 80.01 mA 0.76 79.98 mA 32 kHz When all peripheral clocks are on 65 When all peripheral clocks are off 65 Sleep operation (built-in low-speed CR) 61 62 63 64 65 66 100 kHz When all peripheral clocks are on 65 When all peripheral clocks are off Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 TA = +25 °C, VCC = 3.3V TJ = +125 °C, VCC = 5.5V When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) When all ports are fixed. When using a 32 kHz crystal oscillator (including the current consumption of the oscillation circuit) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 95 of 200 S6E2C Series Table 12-8 Typical and Maximum Current Consumption in Stop Mode, TIMER Mode and RTC Mode Value Pin Parameter Symbol Conditions Frequency Unit Name Typ67 Max68 Stop mode ICCH Timer mode71 (main oscillation) Power supply current Timer mode (built-in High-speed CR) ICCT Timer mode (built-in low-speed CR) ICCR 68 69 70 71 72 3.01 mA - 27.03 mA - 39.92 mA 1.40 3.85 mA - 27.87 mA - 40.76 mA 0.95 3.40 mA - 27.42 mA - 40.31 mA 0.57 3.02 mA - 27.04 mA - 39.93 mA 0.58 3.03 mA - 27.05 mA - 39.94 mA 0.57 3.02 mA - 27.04 mA - 39.93 mA - 4 MHz 4 MHz VCC Timer mode72 (sub oscillation) 67 0.56 RTC mode71 (sub oscillation) 32 kHz 100 kHz 32 kHz Remarks 69, 70 TA = +25°C 69, 70 TA = +85°C 69, 70 TA = +105°C 69, 70 TA = +25°C 69, 70 TA = +85°C 69, 70 TA = +105°C 69, 70 TA = +25°C 69, 70 TA = +85°C 69, 70 TA = +105°C 69, 70 TA = +25°C 69, 70 TA = +85°C 69, 70 TA = +105°C 69, 70 TA = +25°C 69, 70 TA = +85°C 69, 70 TA = +105°C 69, 70 TA = +25°C 69, 70 TA = +85°C 69, 70 TA = +105°C VCC = 3.3V VCC = 5.5V When all ports are fixed When LVD is off When using a 4 MHz crystal oscillator (including the current consumption of the oscillation circuit) When using a 32 kHz crystal oscillator (including the current consumption of the oscillation circuit) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 96 of 200 S6E2C Series Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT Value Pin Parameter Symbol Conditions Frequency Unit Remarks Name Typ73 Max74 Deep standby Stop mode (When RAM is off) - 96 248 μA - 3009 μA - 3889 μA 106 259 μA - 3020 μA - 3900 μA 96 248 μA - 3009 μA - 3889 μA 106 259 μA - 3020 μA - 3900 μA 0.0058 0.1 μA - 1.4 μA - 3.3 μA 1.0 1.8 μA - 3.2 μA - 5.1 μA ICCHD Deep standby Stop mode (When RAM is on) - VCC Deep standby RTC mode (When RAM is off) Power supply current 32 kHz ICCRD Deep standby RTC mode (When RAM is on) RTC stop77 ICCVBAT VBAT - RTC operation77 73 74 75 76 77 78 75, 76 TA = +25°C 75, 76 TA = +85°C 75, 76 TA = +105°C 75, 76 TA = +25°C 75, 76 TA = +85°C 75, 76 TA = +105°C 75, 76 TA = +25°C 75, 76 TA = +85°C 75, 76 TA = +105°C 75, 76 TA = +25°C 75, 76 TA = +85°C 75, 76 TA = +105°C 75, 76, 78 TA = +25°C 75, 76 , 78 TA = +85°C 75, 76 , 78 TA = +105°C 75, 76 TA = +25°C 75, 76 TA = +85°C 75, 76 TA = +105°C VCC = 3.3 V VCC = 5.5 V When all ports are fixed When LVD is off In the case of setting RTC after VCC power on. When sub oscillation is off Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 97 of 200 S6E2C Series Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/Erase Value Pin Parameter Symbol Conditions Unit Remarks Name Min Typ Max Low-voltage detection For occurrence of circuit (LVD) ICCLVD At operation 4 7 μA interrupt power supply current When programming VCC or erase in flash MainFlash memory, Flash memory Memory Write/Erase At ICCFLASH 13.4 15.9 mA write/erase current (ICCFLASH) write/erase current is added to the Power supply current (ICC). Peripheral Current Dissipation Clock System HCLK PCLK1 PCLK2 Frequency (MHz) 50 100 200 Peripheral Unit GPIO All ports 0.39 0.81 1.56 DMAC - 0.99 1.97 3.82 DSTC - 0.73 1.49 2.86 External bus I/F - 0.25 0.48 0.97 SD card I/F - 0.74 1.47 2.90 CAN 1 ch 0.06 0.08 0.16 CAN-FD 1 ch 0.77 1.50 2.95 USB 1 ch 0.48 0.95 1.89 Ethernet-MAC - 1.85 3.63 7.20 I2 S - 0.51 1.02 1.99 High-speed Quad SPI - 0.48 0.97 1.49 Programmable CRC - 0.05 0.10 0.22 Base timer 4 ch 0.21 0.42 0.83 1 unit/4 ch 0.83 1.65 3.25 1 unit 0.07 0.13 0.27 A/D converter 1 unit 0.31 0.60 1.17 Multi-function serial 1 ch 0.41 0.81 - Multi-functional timer/PPG Quadrature position/revolution counter Document Number: 002-04980 Rev. *E Unit Remarks mA mA S6E2C Series Datasheet mA Page 98 of 200 S6E2C Series 12.3.2 Pin Characteristics Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) Symbol Pin Name CMOS hysteresis input pin, MD0, MD1 MADATAxx VIHS VILS 5V tolerant input pin Input pin doubled as I2C Fm+ TTL Schmitt input pin CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I2C Fm+ TTL Schmitt input pin 4 mA type 8 mA type H level output voltage VOH 10 mA type 12 mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ Document Number: 002-04980 Rev. *E (VCC = USBVCC0 = USBVCC1 = ETHVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Value Conditions Unit Remarks Min Typ Max V VCC×0.8 VCC + 0.3 ETHVCC×0.8 ETHVCC + 0.3 V VCC > 3.0V, VCC ≤ 3.6V, - 2.4 - VCC + 0.3 V VCC×0.8 - VSS + 5.5 V - VCC×0.7 - VSS + 5.5 V - 2.0 - ETHVCC+0.3 V VSS - 0.3 - VCC×0.2 V VSS - 0.3 - ETHVCC×0.2 V - VSS - 0.3 - VCC×0.2 V - VSS - VCC×0.3 V - VSS - 0.3 - 0.8 V VCC - 0.5 - VCC V VCC - 0.5 - ETHVCC V VCC - 0.5 - VCC V ETHVCC - 0.5 - ETHVCC V VCC - 0.5 - VCC V VCC - 0.5 - VCC V - VCC ≥ 4.5V, IOH = - 4 mA VCC < 4.5V, IOH = - 2 mA ETHVCC ≥ 4.5V, IOH = - 4 mA ETHVCC < 4.5V, IOH = - 2 mA VCC ≥ 4.5V, IOH = - 8 mA VCC < 4.5V, IOH = - 4 mA ETHVCC ≥ 4.5V, IOH = - 8 mA ETHVCC < 4.5V, IOH = - 4 mA VCC ≥ 4.5V, IOH = - 10 mA VCC < 4.5V, IOH = - 8 mA VCC ≥ 4.5V, IOH = - 12 mA VCC < 4.5V, IOH = - 8 mA USBVCC ≥ 4.5V, IOH = - 20.5 mA USBVCC < 4.5V, IOH = - 13.0 mA At External Bus USBVCC 0.4 - USBVCC V USBVCC0 and USBVCC1 are described as USBVCC. VCC - 0.5 - VCC V At GPIO VCC ≥ 4.5V, IOH = - 4 mA VCC < 4.5V, IOH = - 3 mA S6E2C Series Datasheet Page 99 of 200 S6E2C Series Parameter Symbol Pin Name Conditions VCC ≥ 4.5V, IOL = 4 mA 4 mA type 8 mA type L level output voltage VOL 10 mA type 12 mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ Input leak current Pull-up resistor value Input capacitance IIL - RPU Pull-up pin CIN Other than VCC, USBVCC0, USBVCC1, ETHVCC, VBAT, VSS, AVCC, AVSS, AVRH Document Number: 002-04980 Rev. *E VCC < 4.5V, IOL = 2 mA ETHVCC ≥ 4.5V, IOL = 4 mA RTHVCC < 4.5V, IOL = 2 mA VCC ≥ 4.5V, IOL = 8 mA VCC < 4.5V, IOL = 4 mA ETHVCC ≥ 4.5V, IOL = 8 mA RTHVCC < 4.5V, IOL = 4 mA VCC ≥ 4.5V, IOL = 10 mA VCC < 4.5V, IOL = 8 mA VCC ≥ 4.5V, IOL = 12 mA VCC < 4.5V, IOL = 8 mA USBVCC ≥ 4.5V, IOL = 18.5 mA Min Value Typ Max Unit VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VCC ≥ 4.5V, IOL = 4 mA VCC < 4.5V, IOL = 3 mA VCC ≤ 4.5V, IOL = 20 mA VSS - 0.4 V - -5 - +5 VCC ≥ 4.5V 25 50 100 VCC < 4.5V 30 80 200 - - 5 15 USBVCC < 4.5V, IOL = 10.5 mA S6E2C Series Datasheet Remarks USBVCC0 and USBVCC1 are described as USBVCC. At GPIO At I2C Fm+ μA kΩ pF Page 100 of 200 S6E2C Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40C to +105C) Parameter Input frequency Input clock cycle Symbol tCYLH Internal operating clock 79 frequency Internal operating clock79 cycle time 79 80 fCP0 fCP1 fCP2 tCYCC tCYCP0 tCYCP1 tCYCP2 Value Max VCC ≥4.5V VCC < 4.5V VCC ≥4.5V VCC < 4.5V VCC ≥4.5V VCC < 4.5V PWH/tCYLH, PWL/tCYLH 4 4 4 4 20.83 50 48 20 48 20 250 250 45 - X0, X1 tCF, tCR fCC Conditions Min fCH Input clock pulse width Input clock rise time and fall time Pin Name Unit Remarks MHz When crystal oscillator is connected MHz When using external clock ns When using external clock 55 % When using external clock - 5 ns When using external clock - - 200 MHz Base clock (HCLK/FCLK) - 5 10 5 10 100 200 100 - MHz MHz MHz ns ns ns ns APB0bus clock 80 APB1bus clock80 APB2bus clock 80 Base clock (HCLK/FCLK) APB0bus clock 80 APB1bus clock 80 APB2bus clock80 For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856). For more about each APB bus to which each peripheral is connected, see 1. Block Diagram in this data sheet. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 101 of 200 S6E2C Series 12.4.2 Sub Clock Input Characteristics (VBAT = 1.65V to 5.5V, VSS = 0V) Parameter Symbol Input frequency Pin Name Conditions Value Unit Min Typ Max - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs PWH/tCYLL, PWL/tCYLL 45 - 55 % 1/tCYLL Input clock cycle tCYLL Input clock pulse width X0A, X1A - Remarks When crystal oscillator is connected81 When using external clock When using external clock When using external clock tCYLL 0.8 × VBAT 0.8 × VBAT 0.8 × VBAT 0.2 × VBAT 0.2 × VBAT X0A PWH PWL 12.4.3 Built-In CR Oscillation Characteristics Built-In High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Clock frequency Frequency stabilization time fCRH tCRWT Conditions Value Min Typ Max TJ = - 20°C to + 105°C 3.92 4 4.08 TJ = - 40°C to + 125°C 3.88 4 4.12 TJ = - 40°C to + 125°C 3 4 5 - - - 30 Unit Remarks When trimming82 MHz When not trimming μs 83 Built-In Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Clock frequency fCRL - Value Min Typ Max 50 100 150 Unit Remarks kHz 81 For more information about crystal oscillator, see Sub crystal oscillator in 8. Handling Devices In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming This is the time to stabilize the frequency of the High-speed CR clock after setting trimming value. During this period, it is able to use the High-speed CR clock as a source clock. 82 83 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 102 of 200 S6E2C Series 12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Min Value Typ tLOCK 100 - - μs fPLLI fPLLO 4 13 200 - - 16 100 400 200 MHz multiplier MHz MHz Symbol PLL oscillation stabilization wait time84 (lock up time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency85 fCLKPLL Max Unit Remarks 12.4.5 Operating Conditions of USB/Ethernet PLL・I2S PLL (in the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Min Value Typ Max tLOCK 100 - - μs fPLLI - 4 13 - fPLLO 200 - 16 100 400 384 MHz multiplier MHz MHz USB/Ethernet clock frequency87 fCLKPLL - - 50 MHz I2S clock frequency fCLKPLL - - 12.288 MHz Parameter PLL oscillation stabilization wait (lock up time) PLL input clock frequency PLL multiplication rate Symbol time86 PLL macro oscillation clock frequency 88 Unit Remarks USB/Ethernet I2 S After the M frequency division After the M frequency division 84 Time from when the PLL starts operating until the oscillation stabilizes For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856). 86 Time from when the PLL starts operating until the oscillation stabilizes 87 For more information about USB/Ethernet clock, see Chapter 2-2: USB/Ethernet Clock Generation in FM4 Family Peripheral Manual Communication Macro Part (002-04862). 88 For more information about I2S clock, see Chapter 7-1: I2S Clock Generation in FM4 Family Peripheral Manual Communication Macro Part (002-04862). 85 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 103 of 200 S6E2C Series 12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Min Value Typ Max tLOCK 100 - - μs fPLLI fPLLO 3.8 50 190 4 - 4.2 95 400 MHz multiplier MHz fCLKPLL - - 200 MHz Symbol time89 PLL oscillation stabilization wait (lock up time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency 90 Unit Remarks Note: − The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main PLL. 12.4.7 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Reset input time Symbol Pin Name Conditions tINITX INITX - Value Min Max 500 - Unit Remarks ns 89 Time from when the PLL starts operating until the oscillation stabilizes For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856). 90 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 104 of 200 S6E2C Series 12.4.8 Power-On Reset Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Power supply shut down time Symbol Pin Name Conditions tOFF - Value Min 1 Typ Max - - Unit Remarks ms VCC must be held below 0.2V for a minimum period of tOFF. Improper initializatio n may occur if this condition is not met VCC Power ramp rate Time until releasing Power-on reset dV/dt VCC: 0.2V to 2.70V 0.6 - 1000 tPRT - 0.33 - 0.60 This dV/dt characteri stic is applied at mV/µs the poweron of cold start (tOFF>1ms) . ms Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12.4.7 Reset Input Characteristics. 2.7V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST RST Active CPU Operation 0.2V tOFF release start Glossary  VDH: detection voltage of Low Voltage detection reset. See “12.8. Low-Voltage Detection Characteristics”. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 105 of 200 S6E2C Series 12.4.9 GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Symbol Pin Name tPCYCLE Pxx91 Conditions Value Unit Min Max VCC ≥ 4.5V - 50 MHz VCC < 4.5V - 32 MHz Remarks Pxx tPCYCLE 91 GPIO is a target. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 106 of 200 S6E2C Series 12.4.10 External Bus Timing External Bus Clock Output Characteristics Parameter Symbol Output frequency Pin Name tCYCLE MCLKOUT Value Conditions Min Max - 5093 92 0.80.8 × ×VVcc CC Unit Remarks MHz 0.8 VCC 0.8 × × Vcc MCLK tCYCLE External Bus Signal I/O Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Signal input characteristics Symbol Conditions VIH VIL - VOH Value Unit 0.8 × VCC V 0.2 × VCC V 0.8 × VCC V 0.2 × VCC V Remarks Signal output characteristics VOL Input signal VIH VIL VIH VIL VOH VOL VOH VOL 92 The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual Main Part (002-04856). 93 The Multi-layer AHB clock divided by the (DCLKR:MDIV) divider register, cannot exceed this specification for MCLKOUT or MSDCLK clock. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 107 of 200 S6E2C Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions tOEW MOEX MCSX↓→Address output delay time tCSL – AV MOEX↑→Address hold time tOEH - AX MCSX↓→ MOEX↓delay time tCSL - OEL MOEX↑→ MCSX↑time tOEH - CSH MOEX Minimum pulse width MCSX↓→ MDQM↓delay time Value Unit Min Max - MCLK×n-3 - ns MCSX[7: 0], MAD[24: 0] - -9 +9 ns MOEX, MAD[24: 0] - 0 MCLK×m+9 ns - MCLK×m9 MCLK×m+9 ns - 0 MCLK×m+9 ns MOEX, MCSX[7: 0] tCSL - RDQML MCSX, MDQM[3: 0] - MCLK×m9 MCLK×m+9 ns Data set up→MOEX↑ time tDS - OE MOEX, MADATA[31: 0] - 20 - ns MOEX↑→ Data hold time tDH - OE MOEX, MADATA[31: 0] - 0 - ns MWEX Minimum pulse width tWEW MWEX - MCLK×n-3 - ns MWEX↑→Address output delay time tWEH - AX MWEX, MAD[24: 0] - 0 MCLK×m+9 ns MCSX↓→ MWEX↓delay time tCSL - WEL - MCLK×n-9 MCLK×n+9 ns MWEX↑→ MCSX↑delay time tWEH - CSH - 0 MCLK×m+9 ns MCSX↓→ MDQM↓delay time tCSL-WDQML MCSX, MDQM[3: 0] - MCLK×n-9 MCLK×n+9 ns tCSL-DX MCSX, MADATA[31: 0] - MCLK-9 MCLK+9 ns tWEH - DX MWEX, MADATA[31: 0] - 0 MCLK×m+9 ns MCSX↓→ Data output time MWEX↑→ Data hold time MWEX, MCSX[7: 0] Remarks Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 108 of 200 S6E2C Series tCYCLE MCLK tOEH-CSH tWEH-CSH MCSX[7: 0] tCSL-AV tOEH-AX Address MAD[24: 0] tWEH-AX tCSL-AV Address tCSL-OEL MOEX tOEW tCSL-WDQML tCSL-RDQML MDQM[1: 0] tCSL-WEL tWEW MWEX tDS-OE tDH-OE RD MADATA[15: 0] tWEH-DX WD Invalid tCSL-DX tCYCLE MCLK tOEH-CSH tWEH-CSH MCSX[7: 0] tCSL-AV MAD[24: 0] tOEH-AX Address tWEH-AX tCSL-AV Address tCSL-OEL MOEX tOEW tCSL-WDQML tCSL-RDQML MDQM[1: 0] tCSL-WEL tWEW MWEX tDS-OE MADATA[15: 0] tDH-OE RD tWEH-DX WD Invalid tCSL-DX Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 109 of 200 S6E2C Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions tAV MCLK, MAD[24: 0] Address delay time tCSL MCSX delay time tCSH MWEX delay time MDQM[1: 0] delay time - 1 9 ns MCLK, MCSX[7: 0] - 1 9 ns - 1 9 ns MCLK, MOEX - 1 9 ns - 1 9 ns - 19 - ns - 0 - ns MCLK, MWEX - 1 9 ns - 1 9 ns MCLK, MDQM[3: 0] - 1 9 ns - 1 9 ns - MCLK+1 MCLK+18 ns - 1 18 ns tREH Data set up →MCLK↑ time MCLK↑→ Data hold time tDS tDH MCLK, MADATA[31: 0] MCLK, MADATA[31: 0] tWEL tWEH tDQML tDQMH MCLK↑→ Data output time MCLK↑→ Data hold time tODS tOD Unit Max tREL MOEX delay time Value Min MCLK, MADATA[31: 0] MCLK, MADATA[31: 0] Remark s Note: − When the external load capacitance CL = 30 pF tCYCLE MCLK tCSL MCSX[7: 0] tAV MAD[24: 0] MOEX MDQM[3: 0] tCSH tAV Address Address tREL tREH tDQML tDQMH MWEX tDS MADATA[31: 0] tDQML tDQMH tWEL tWEH tDH RD tOD WD Invalid tODS Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 110 of 200 S6E2C Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Multiplexed address delay time tALE-CHMADV Multiplexed address hold time tCHMADH Pin Name MALE, MAD[24: 0] Conditions Value Unit Min Max - 0 10 ns - MCLK×n+0 MCLK×n+10 ns Remarks Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) MCLK MCSX[7: 0] MALE MAD [24: 0] MOEX MDQM [3: 0] MWEX MADATA[31: 0] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 111 of 200 S6E2C Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MALE delay time Symbol Pin Name Conditions tCHAL MCLK, MALE tCHAH MCLK↑→Multiplexed address delay time MCLK↑→Multiplexed data output time tCHMADV tCHMADX MCLK, MADATA[31: 0] Value Unit Min Max - 1 9 - 1 9 - 1 tOD ns - 1 tOD ns Remarks Note: − When the external load capacitance CL = 30 pF MCLK MCSX[7: 0] MALE MAD [24: 0] MOEX MDQM [3: 0] MWEX MADATA[31: 0] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 112 of 200 S6E2C Series NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MNREX Min pulse width Data set up →MNREX↑time Symbol Pin Name Conditions tNREW MNREX tDS – NRE MNREX, MADATA[31: 0] MNREX, MADATA[31: 0] MNALE, MNWEX MNALE, MNWEX MNCLE, MNWEX Value Unit Min Max - MCLK×n-3 - ns - 20 - ns - 0 - ns - MCLK×m-9 MCLK×m+9 ns - MCLK×m-9 MCLK×m+9 ns - MCLK×m-9 MCLK×m+9 ns MNREX↑→ Data hold time MNALE↑→ MNWEX delay time MNALE↓→ MNWEX delay time MNCLE↑→ MNWEX delay time tCLEH - NWEL MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX - 0 MCLK×m+9 ns tNWEW MNWEX - MCLK×n-3 - ns - -9 9 ns - 0 MCLK×m+9 ns MNWEX Min pulse width MNWEX↓→ Data output time MNWEX↑→ Data hold time tDH – NRE tALEH - NWEL tALEL - NWEL tNWEL – DV tNWEH – DX MNWEX, MADATA[31: 0] MNWEX, MADATA[31: 0] Remarks Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) NAND Flash Read MCLK MNREX MADATA[31: 0] Document Number: 002-04980 Rev. *E Read S6E2C Series Datasheet Page 113 of 200 S6E2C Series NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[31: 0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[31: 0] Document Number: 002-04980 Rev. *E Write S6E2C Series Datasheet Page 114 of 200 S6E2C Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MCLK↑ MRDY input setup time Symbol Pin Name Conditions tRDYI MCLK, MRDY - Value Min Max 19 - Unit Remarks ns ◼ When RDY is input ··· MCLK Over 2cycle Original MOEX MWEX tRDYI MRDY ◼ When RDY is released MCLK ··· ··· 2 cycles Extended MOEX MWEX tRDYI 0.5×VCC MRDY Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 115 of 200 S6E2C Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Output frequency tCYCSD MSDCLK Address delay time tAOSD MSDCLK↑→ Data output delay time MSDCLK↑→ Data output Hi-Z time tDOSD tDOZSD MDQM[3: 0] delay time tWROSD MCSX delay time tMCSSD MRASX delay time tRASSD MCASX delay time tCASSD MSDWEX delay time tMWESD MSDCKE delay time tCKESD Data set up time tDSSD Data hold time tDHSD MSDCLK, MAD[15: 0] MSDCLK, MADATA[31: 0] MSDCLK, MADATA[31: 0] MSDCLK, MDQM[1: 0] MSDCLK, MCSX8 MSDCLK, MRASX MSDCLK, MCASX MSDCLK, MSDWEX MSDCLK, MSDCKE MSDCLK, MADATA[31: 0] MSDCLK, MADATA[31: 0] Unit Unit Min Max - - 50 MHz - 2 12 ns - 2 12 ns - 2 19.5 ns - 1 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 19 - ns - 0 - ns Remarks Note: − When the external load capacitance CL = 30 pF Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 116 of 200 S6E2C Series tCYCSD MSDCLK tAOSD MAD[24:0] MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE Address tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDSSD MADATA[15:0] tDOSD MADATA[15:0] Document Number: 002-04980 Rev. *E tDHSD RD tDOZSD WD S6E2C Series Datasheet Page 117 of 200 S6E2C Series 12.4.11 Base Timer Input Timing Timer Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin Name tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) Min tTIWH Value 2tCYCP Max - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin Name tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) tTRGH TGIN VIHS Min Value 2tCYCP Max - Unit Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the base timer is connected, see 1. Block Diagram in this datasheet. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 118 of 200 S6E2C Series 12.4.12 CSIO (SPI) Timing Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx Baud rate Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time Notes: - tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions Internal shift clock operation VCC < 4.5V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tCYCP 10 tCYCP + 10 External shift clock operation VCC ≥ 4.5V Min Max 8 4tCYCP - - 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 119 of 200 S6E2C Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL VIH VIL SIN MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL VIH tR tSLOVE SOT SIN VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 120 of 200 S6E2C Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx Baud rate Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation VCC < 4.5V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns 2tCYCP 10 tCYCP + 10 External shift clock operation VCC ≥ 4.5V Min Max 8 4tCYCP - - 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 121 of 200 S6E2C Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI tSLIXI VIH VIL VIH VIL SIN MS bit = 0 tSHSL VIH SCK VIL tR tSLSH VIH SIN VIL tF tSHOVE SOT VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 122 of 200 S6E2C Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Baud rate Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation VCC < 4.5V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns - ns 2tCYCP 30 2tCYCP 10 tCYCP + 10 External shift clock operation VCC ≥ 4.5V Min Max 8 4tCYCP - - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 123 of 200 S6E2C Series tSCYC VOH SCK VOL VOH VOL SOT VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK SOT VIH V VIL IH VIL tF *V tR VIH tSHOVE VOH VOL OH VOL tIVSLE SIN tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 124 of 200 S6E2C Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Baud rate Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation VCC < 4.5V Min Max 8 4tCYCP - Unit Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns - ns 2tCYCP 30 2tCYCP 10 tCYCP + 10 External shift clock operation VCC ≥ 4.5V Min Max 8 4tCYCP - - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 125 of 200 S6E2C Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL SOT VIH VIH VIL tF VIL VIH tSLOVE VOH VOL VOH VOL tIVSHE SIN tSLSH tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 126 of 200 S6E2C Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V VCC ≥ 4.5V Unit Min Max Min Max 94-50 94+0 94-50 94+0 ns 95+0 95+50 95+0 95+50 ns 96-50 96+50 96-50 96+50 +5tCYCP 3tCYCP+30 +5tCYCP - +5tCYCP 3tCYCP+30 +5tCYCP - 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns ns ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 94 95 96 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 127 of 200 S6E2C Series SCS output tCSDI tCSSI tCSHI tCSSE tCSHE SCK output SOT (SPI=0) SOT (SPI=1) SCS input tCSDE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 128 of 200 S6E2C Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V VCC ≥ 4.5V Unit Min Max Min Max 97-50 97+0 97-50 97+0 ns 98+0 98+50 98+0 98+50 ns 99-50 99+50 99-50 99+50 +5tCYCP 3tCYCP+30 +5tCYCP - +5tCYCP 3tCYCP+30 +5tCYCP - 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns ns ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 97 98 99 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 129 of 200 S6E2C Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 130 of 200 S6E2C Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↑→SCK↓ setup time SCK↑→SCS↓ hold time Symbol tCSSI tCSHI SCS deselect time tCSDI SCS↑→SCK↓ setup time tCSSE SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V Min VCC ≥ 4.5V Max Unit Max Min 100-50 100+0 100-50 100+0 ns 101+0 101+50 101+0 101+50 ns 102-50 102+50 102-50 102+50 +5tCYCP 3tCYCP+30 +5tCYCP - +5tCYCP 3tCYCP+30 +5tCYCP - ns ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 100 101 102 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 131 of 200 S6E2C Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 132 of 200 S6E2C Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↑setup time SCK↓→SCS↓hold time tCSSI tCSHI SCS deselect time tCSDI SCS↑→SCK↑setup time tCSSE SCK↓→SCS↓hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V Min VCC ≥ 4.5V Max Units Max Min 103-50 103+0 103-50 103+0 ns 104+0 104+50 104+0 104+50 ns 105-50 105+50 105-50 105+50 +5tCYCP 3tCYCP+30 +5tCYCP - +5tCYCP 3tCYCP+30 +5tCYCP - ns ns 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns - 40 - 40 ns 0 - 0 - ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 103 104 105 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 133 of 200 S6E2C Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 134 of 200 S6E2C Series High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5V Min Max 4tCYCP - Conditions - 10 VCC ≥ 4.5V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 5 tCYCP + 10 - 2tCYCP - 5 tCYCP + 10 - ns ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns Internal shift clock operation 14 12.5* External shift clock operation Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 135 of 200 S6E2C Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL VIH VIL SIN MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 136 of 200 S6E2C Series High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5V Min Max 4tCYCP - Conditions - 10 VCC ≥ 4.5V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 5 tCYCP + 10 - 2tCYCP - 5 tCYCP + 10 - ns ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns Internal shift clock operation 14 12.5* External shift clock operation Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 137 of 200 S6E2C Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK VIL tR tSLSH VIH VIH SIN VIL tF tSHOVE SOT VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 138 of 200 S6E2C Series High-Speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK fall time SCK rise time tF tR Pin Name SCKx SCKx, SOTx Conditions SCKx, SINx Internal shift clock operation SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5V Min Max 4tCYCP - 10 VCC ≥ 4.5V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns 2tCYCP - 5 tCYCP + 10 - 2tCYCP - 5 tCYCP + 10 - ns ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns 14 12.5* External shift clock operation Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 139 of 200 S6E2C Series tSCYC VOH SCK SOT VOL VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK SOT VIH VIL tSHSL VIH VIL tF *V tR VIH tSHOVE VOH VOL OH VOL tIVSLE SIN tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 140 of 200 S6E2C Series High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name SCKx SCKx, SOTx Conditions SCKx, SINx Internal shift clock operation Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH SCKx, SINx SCKx, SOTx SCKx tSHSL SCKx SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK fall time SCK rise time tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5V Min Max 4tCYCP - 10 VCC ≥ 4.5V Min Max 4tCYCP - Unit ns + 10 - 10 + 10 ns - 12.5 - ns 5 - 5 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns 14 12.5* 2tCYCP - 5 - 2tCYCP - 5 - ns tCYCP + 10 - tCYCP + 10 - ns - 15 - 15 ns 5 - 5 - ns 5 - 5 - ns - 5 5 - 5 5 ns ns External shift clock operation Notes:  − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF) Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 141 of 200 S6E2C Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL tSLSH VIH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 142 of 200 S6E2C Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V VCC ≥ 4.5V Unit Min Max Min Max 106-20 106+0 106-20 106+0 ns 107+0 107+20 107+0 107+20 ns 108-20 108+20 108-20 108+20 +5tCYCP 3tCYCP+15 +5tCYCP - +5tCYCP 3tCYCP+15 +5tCYCP - 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns ns ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 106 107 108 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 143 of 200 S6E2C Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 144 of 200 S6E2C Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↑ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V VCC ≥ 4.5V Unit Min Min Min Max 109-20 109+0 109-20 109+0 ns 110+0 110+20 110+0 110+20 ns 111-20 111+20 111-20 111+20 +5tCYCP 3tCYCP+15 +5tCYCP - +5tCYCP 3tCYCP+15 +5tCYCP - 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns ns ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 109 110 111 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 145 of 200 S6E2C Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS intpu tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 146 of 200 S6E2C Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↑→SCK↓ setup time SCK↑→SCS↓ hold time Symbol tCSSI tCSHI SCS deselect time tCSDI SCS↑→SCK↓ setup time tCSSE SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V Min VCC ≥ 4.5V Max Unit Max Min 112-20 112+0 112-20 112+0 ns 113+0 113+20 113+0 113+20 ns 114-20 114+20 114-20 114+20 +5tCYCP 3tCYCP+15 +5tCYCP - +5tCYCP 3tCYCP+15 +5tCYCP - ns ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 112 113 114 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 147 of 200 S6E2C Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 148 of 200 S6E2C Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↓→SCK↓ setup time SCK↑→SCS↓ hold time Symbol tCSSI tCSHI SCS deselect time tCSDI SCS↑→SCK↑ setup time tCSSE SCK↓→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation VCC < 4.5V Min VCC ≥ 4.5V Max Unit Max Min 115-20 115+0 115-20 115+0 ns 116+0 116+20 116+0 116+20 ns 117-20 117+20 117-20 117+20 +5tCYCP 3tCYCP+15 +5tCYCP - +5tCYCP 3tCYCP+15 +5tCYCP - ns ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 40 - 40 ns 0 - 0 - ns Notes:  − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 1. Block Diagram in this datasheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF. 115 116 117 CSSU bit value×serial chip select timing operating clock cycle [ns] CSHD bit value×serial chip select timing operating clock cycle [ns] CSDS bit value×serial chip select timing operating clock cycle [ns] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 149 of 200 S6E2C Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE MS bit = 1 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 150 of 200 S6E2C Series External Clock (EXT = 1): When in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Serial clock L pulse width Serial clock H pulse width SCK fall time SCK rise time Symbol tSLSH tSHSL tF tR Condition CL = 30 pF tR tSHSL SCK V IL Document Number: 002-04980 Rev. *E Min tCYCP + 10 tCYCP + 10 - VIH Value Max 5 5 S6E2C Series Datasheet V IL Remarks ns ns ns ns tF tSLSH VIH Unit V IL VIH Page 151 of 200 S6E2C Series 12.4.13 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Min Max Unit A/D converter trigger input ADTGx FRCKx Input pulse width ICxx DTTIxX tINH, tINL Remarks - 2tCYCP118 - ns - 2tCYCP118 - ns 2tCYCP + 100118 - ns 500119 - ns 500120 - ns INT00 to INT31, NMIX - WKUPx - Free-run timer input clock Input capture Waveform generator External interrupt, NMI Deep standby wake up 118 tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in Timer mode. For more information about the APB bus number to which the A/D converter, multi-function timer, and external interrupt are connected, see 1 Block Diagram in this data sheet. 119 When in Stop mode, in Timer mode 120 When in Deep Standby RTC mode, in Deep Standby Stop mode Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 152 of 200 S6E2C Series 12.4.14 Quadrature Position/Revolution Counter Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40°C to +105°C) Parameter Symbol Conditions AIN pin H width AIN pin L width BIN pin H width BIN pin L width BIN rise time from AIN pin H level AIN fall time from BIN pin H level BIN fall time from AIN pin L level AIN rise time from BIN pin L level AIN rise time from BIN pin H level BIN fall time from AIN pin H level AIN fall time from BIN pin L level BIN rise time from AIN pin L level ZIN pin H width ZIN pin L width AIN/BIN rise and fall time from determined ZIN level Determined ZIN level from AIN/BIN rise and fall time tAHL tALL tBHL tBLL tZHL tZLL PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 QCR: CGSC = 0 QCR: CGSC = 0 tZABE QCR: CGSC = 1 tABEZ QCR: CGSC = 1 tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU Min 2tCYCP121 Value Unit Max - ns SDA tSUSTA tSUDAT tBUF tLOW SCL tHDSTA tHDDAT tHIGH tHDSTA tSP tSUSTO 121 tCYCP indicates the APB bus clock cycle time except when in Stop mode, in Timer mode. For more information about the APB bus number to which the quadrature position/revolution counter is connected, see 1. Block Diagram in this data sheet. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 153 of 200 S6E2C Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 154 of 200 S6E2C Series 12.4.15 I2C Timing Standard-Mode, Fast-Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between "Stop condition" and "START condition" Noise filter Symbol Conditions fSCL Standard-Mode Min Max 0 100 Fast-Mode Min Max 0 400 Unit kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45123 0 0.9124 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP125 - 2 tCYCP125 - ns 4 tCYCP125 - 4 tCYCP125 - ns tSUSTA tHDDAT tSP CL = 30 pF, R = (Vp/IOL)122 2 MHz ≤ tCYCP＜40 MHz 40 MHz ≤ tCYCP ＜60 MHz 60 MHz ≤ tCYCP ＜80 MHz 80 MHz ≤ tCYCP ≤100 MHz Remarks 126 6 tCYCP125 - 6 tCYCP125 - ns 8 tCYCP125 - 8 tCYCP125 - ns 122 R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. V p indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. 123 The maximum tHDDT must not extend beyond the low period (tLOW ) of the device’s SCL signal. 124 Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns. 125 tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see 1.Block Diagram in this data sheet. When using Standard-mode, the peripheral bus clock must be set more than 2 MHz. When using Fast-mode, the peripheral bus clock must be set more than 8 MHz. 126 The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 155 of 200 S6E2C Series Fast mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between "Stop condition" and "START condition" Noise filter Conditions Fast mode Plus (Fm+)127 Unit Min Max fSCL 0 1000 kHz tHDSTA 0.26 - μs tLOW tHIGH tSUSTA 0.5 0.26 0.26 - μs μs μs tHDDAT CL = 30 pF, R = (Vp/IOL)128 0 0.45129, 130 μs tSUDAT 50 - ns tSUSTO 0.26 - μs tBUF 0.5 - μs 6 tCYCP131 - ns 8 tCYCP131 - ns tSP 60 MHz ≤ tCYCP＜80 MHz 80 MHz ≤ tCYCP ≤100 MHz Remarks 132 127 When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details. 128 R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. V p indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. 129 The maximum tHDDT must not extend beyond the low period (tLOW ) of the device’s SCL signal. 130 The Fast mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns. 131 tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see 1 Block Diagram in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. 132 The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 156 of 200 S6E2C Series 12.4.16 SD Card Interface Timing Default-Speed mode ◼ Clock CLK (All values are referenced to VIH and VIL transition points) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name fPP S_CLK fOD S_CLK tWL tWH tTLH tTHL S_CLK S_CLK S_CLK S_CLK Clock frequency Data Transfer mode Clock frequency Identification mode Clock low time Clock high time Clock rise time Clock fall time Conditions Min CCARD ≤ 10 pF (1card) Symbol Input set-up time tISU Input hold time tIH Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD ≤ 10 pF (1card) Output Delay time during Data Transfer mode Output Delay time during Identification mode Symbol tODLY tODLY Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD ≤ 40 pF (1card) MHz 0133/100 400 kHz 10 10 - 10 10 ns ns ns ns Min Max - ns 5 - ns Value Max Remarks 0 14 ns 0 50 ns VIH VIH VIH VIL VIL tTLH tTHL tIH VIH VIH VIL VIL tODLY(Min) tODLY(Max) S_CMD, S_DATA3: 0 (Card Output) Remarks tWH tISU S_CMD, S_DATA3: 0 (Card Input) Value 5 Min tWL S_CLK (SD Clock) Remarks 25 ◼ Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Max 0133 ◼ Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Value VOH VOH VOL VOL Default-Speed mode Notes: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. 133 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 157 of 200 S6E2C Series − For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part (002-04856). High-speed mode ◼ Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name fPP S_CLK Clock frequency Data Transfer mode Clock low time Clock high time Clock rise time Clock fall time tWL tWH tTLH tTHL Conditions Min CCARD ≤ 10 pF (1card) S_CLK S_CLK S_CLK S_CLK Symbol Input set-up time tISU Input hold time tIH Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD ≤ 10 pF (1card) Symbol Output delay time during data transfer mode tODLY Output hold time tOH Total system capacitance for each line134 CL Pin Name Conditions S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CL ≤ 40 pF (1card) CL ≥ 15 pF (1card) - 1card MHz 7 7 - 3 3 ns ns ns ns Min 50%VCC VIH VIH VIL VIL Remarks - ns 2 - ns Value Max Remarks 0 14 ns 2.5 - ns - 40 pF 50%VCC VIH tTLH tTHL tODLY(Max) S_CMD, S_DATA3: 0 (Card Output) Max 6 Min tIH tISU S_CMD, S_DATA3: 0 (Card Input) Value tWH tWL S_CLK (SD Clock) Remarks 50 ◼ Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Max 0 ◼ Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Value VIH VIH VIL VIL tOH(Min) VOH VOH VOL VOL High-speed mode 134 In order to satisfy severe timing, host shall drive only one card. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 158 of 200 S6E2C Series Notes: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. − For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part (002-04856). 12.4.17 ETM/ HTM Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Data hold Symbol Pin Name tETMH TRACECLK, TRACED[15: 0] TRACECLK frequency 1/tTRACE TRACECLK clock cycle tTRACE TRACECLK Conditions VCC ≥ 4.5V Min 2 VCC ＜4.5V VCC ≥ 4.5V VCC ＜4.5V 2 VCC ≥ 4.5V VCC ＜4.5V Value Max 9 Unit Remarks ns 15 50 32 MHz MHz 20 - ns 31.25 - ns Note: − When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[15: 0] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 159 of 200 S6E2C Series 12.4.18 JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5V VCC ＜4.5V TMS, TDI hold time tJTAGH TCK, TMS, TDI TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5V VCC ＜4.5V VCC ≥ 4.5V VCC ＜4.5V Min Value Max Unit 15 - ns 15 - ns - 25 45 ns Remarks Note: − When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 160 of 200 S6E2C Series 12.4.19 Ethernet-MAC Timing RMII Transmission (100 Mbps/10 Mbps) (ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V135, VSS = 0V, CL = 25 pF) Parameter Reference clock cycle time136 Reference clock High-pulse-width duty cycle Reference clock Low-pulse-width duty cycle Transmitted data → REFCK ↑ delay time Value Symbol Pin Name Conditions tREFCYC E_RXCK_REFCK 20 ns (typical) - - ns tREFCYCH E_RXCK_REFCK tREFCYCH/tREFCYC 35 65 % tREFCYCL E_RXCK_REFCK tREFCYCL/tREFCYC 35 65 % tRMIITX E_TX03, E_TX02, E_TX01, E_TX00, E_TXEN - - 12 ns Min Max Unit tREFCYC E_RXCK_REFCK VIHS VIHS VILS tREFCYCH E_TX03 E_TX02 E_TX01 E_TX00 E_TXEN tREFCYCL VOH VOL tRMIITX 135 136 When ETHV = 4.5V to 5.5V, it is recommended to add a series resistor at the output pin to suppress the output current. The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 161 of 200 S6E2C Series RMII Receiving (100 Mbps/10 Mbps) (ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF) Parameter Symbol Pin Name Conditions Min Value Max Unit Reference clock cycle time137 Reference clock High-pulse-width duty cycle Reference clock Low-pulse-width duty cycle tREFCYC E_RXCK_REFCK 20 ns (typical) - - ns tREFCYCH E_RXCK_REFCK tREFCYCH/tREFCYC 35 65 % tREFCYCL E_RXCK_REFCK tREFCYCL/tREFCYC 35 65 % Received data → REFCK↑ Setup time tRMIIRXS - 4 - ns Received data → REFCK ↑ Hold time tRMIIRXH - 2 - ns E_RX03, E_RX02, E_RX01, E_RX00, E_RXDV E_RX03, E_RX02, E_RX01, E_RX00, E_RXDV tREFCYC E_RXCK_REFCK VIHS tREFCYCH E_RX03 E_RX02 E_RX01 E_RX00 E_RXDV VIHS VIHS VILS VILS tRMIIRXS 137 VIHS VILS tREFCYCL tRMIIRXH The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 162 of 200 S6E2C Series Management Interface (ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF) Parameter Management clock cycle time138 Management clock High pulse width duty cycle Management clock Low pulse width duty cycle MDC ↓ → MDIO Delay time MDIO → MDC ↑ Setup time MDC ↑ → MDIO Hold time Value Symbol Pin Name Conditions tMDCYC E_MDC - 400 - ns tMDCYCH E_MDC tMDCYCH/tMDCYC 35 65 % tMDCYCL E_MDC tMDCYCL/tMDCYC 35 65 % tMDO E_MDIO - - 60 ns tMDIS E_MDIO - 20 - ns tMDIH E_MDIO - 0 - ns Min Max Unit tMDCYC E_MDC (output) VOL VOH tMDCYCH E_MDIO (input) VIHS VIHS VIHS VILS VILS VILS VILS tMDIS tMDIH tMDIH tMDO tMDO 138 tMDCYCL VIHS tMDIS E_MDIO (output) VOH VOL VOH VOH VOL VOL The clock time should be set to a value greater than the minimum value by setting the Ethernet-MAC setting register. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 163 of 200 S6E2C Series MII Transmission (100 Mbps/10 Mbps) (ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V139, VSS = 0V, CL = 25 pF) Parameter Transmission clock Cycle time140 Transmission clock High-pulse-width duty cycle Transmission clock Low-pulse-width duty cycle TXCK ↑ → Transmitted data delay time Symbol tTXCYC Pin Name Conditions E_TCK 100 Mbps 40 ns (typical) 100 Mbps 400 ns (typical) Min Value Max Unit - - ns - - ns tTXCYCH E_TCK tTXCYCH/tTXCYC 35 65 % tTXCYCL E_TCK tTXCYCL/tTXCYC 35 65 % tMIITX E_TX03, E_TX02, E_TX01, E_TX00, E_TXEN - - 24 ns tTXCYC E_TCK VIHS VIHS VILS tTXCYCH E_TX03 E_TX02 E_TX01 E_TX00 E_TXEN tTXCYCL VOH VOL tMIITX 139 140 When ETHV = 4.5V to 5.5V, it is recommended to add a series resistor at the output pin to suppress the output current. The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications. The clock accuracy should meet the PHY-device specifications. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 164 of 200 S6E2C Series MII Receiving (100 Mbps/10 Mbps) (ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF) Parameter Receiving clock cycle time141 Receiving clock High pulse width duty cycle Receiving clock Low pulse width duty cycle Symbol tRXCYC Pin Name Conditions E_RXCK_REFCK 100 Mbps 40 ns (typical) 100 Mbps 400 ns (typical) Min Value Max Unit - - ns - - ns tRXCYCH E_RXCK_REFCK tRXCYCH/tRXCYC 35 65 % tRXCYCL E_RXCK_REFCK tRXCYCL/tRXCYC 35 65 % - 5 - ns - 2 - ns Received data → REFCK ↑Setup time tMIIRXS REFCK ↑ → Received data Hold time tMIIRXH E_RX03, E_RX02, E_RX01, E_RX00, E_RXDV E_RX03, E_RX02, E_RX01, E_RX00, E_RXDV tRXCYC E_RXCK_REFCK VIHS tRXCYCH E_RX03 E_RX02 E_RX01 E_RX00 E_RXDV VIHS VIHS VILS VILS tMIIRXS 141 VIHS VILS tRXCYCL tMIIRXH The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device specifications. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 165 of 200 S6E2C Series 12.4.20 I2S Timing Master Mode Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions fMCYC tMHW I2SCK - I2SCK - Output frequency Output clock pulse width I2SCK→I2SWS delay time I2SCK→I2SDO delay time142 I2SDI→I2SCK setup time I2SDI→I2SCK hold time Input signal rise time tMLW tDFS tDDO tHSDI tHDJ Input signal fall time tFI tFI I2SCK, I2SWS I2SCK, I2SDO I2SCK, I2SDI I2SDI Min 45 Value Unit Max 12.288 55 MHz % 45 55 % - 0 24.0 ns - 0 24.0 ns - 25.0 - ns - 0 - ns - - 5 ns - - 5 ns Remarks Notes: − When the external load capacitance CL = 20 pF − When I2SWS = 48 kHz, I2MCLK = 256 × I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter 7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (00204862) for the details. 142 Except for the first bit of transmission frame Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 166 of 200 S6E2C Series f MCYC tMHW I2SCK (CPOL=0) tMLW I2SCK (CPOL=1) tDFS I2SWS (FSPH=0, FSLN=0) tDFS tDFS tDFS I2SWS (FSPH=1, FSLN=0) tDFS tDFS I2SWS (FSPH=0, FSLN=1) tDFS tDFS I2SWS (FSPH=1, FSLN=1) tDDO I2SDO tSDI tHDI tSDI tHDI I2SDI (SMPL=0) tSDI tHDI I2SDI (SMPL=1) Note: − See Chapter 7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (00204862) for the details of CPOL, FSPH, FSLIN, and SMPL. I2SDI 0. 8×VCC 0. 8×VCC 0.2×V CC tFI Document Number: 002-04980 Rev. *E S6E2C Series Datasheet 0. 8×VCC 0.2×V CC tRI Page 167 of 200 S6E2C Series Slave Mode Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input frequency Input clock pulse width Symbol Pin Name Conditions fSCYC tSHW I2SCK - I2SCK - I2SWS→I2SCK Setup time I2SWS→I2SCK Hold time I2SCK↑→I2SDO Delay time143 I2SCK↑→I2SDO Delay Time144 I2SDI→I2SCK↓ Setup time I2SDI→I2SCK↓ Hold time Input signal rise time Input signal fall time tSLW tSFI tHFI I2SCK, I2SWS I2SCK, I2SWS tDDO Min 45 Value Unit Max 12.288 55 MHz % 45 55 % - 8 - ns - 0 - ns - 0 32 ns - 0 32 ns - 8 - ns - 0 - ns - - 5 ns - - 5 ns Remarks I2SCK, I2SDO tDFB1 tSDI I2SCK, I2SDI tHDI tFI tFI I2SCK, I2SWS, I2SDI Notes: − When the external load capacitance CL = 20 pF − When I2SWS = 48 kHz, I2MCLK = 256×I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter 7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details. 143 144 Except for the first bit of transmission frame When FSPH bit = 1. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 168 of 200 S6E2C Series f SCYC tSHW I2SCK (CPOL=0) tSLW I2SCK (CPOL=1) tSFI t HFI I2SWS (FSPH=0, FSLN=0) tSFI tHFI I2SWS (FSPH=1, FSLN=0) tSFI I2SWS (FSPH=0, FSLN=1) tSFI I2SWS (FSPH=1, FSLN=1) t DDO t DFB1 1 I2SDO tSDI tHDI tSDI tHDI I2SDI (SMPL=0) tSDI tHDI I2SDI (SMPL=1) Notes: − See Chapter 7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (00204862) for the details of FSPH, FSLN, SMPL − I2SCK input is selectable polarity by CPOL bit of CNTREG register I2SCK I2SWS I2SDI 0.8×VCC 0.8×VCC 0.2×VCC tfi Document Number: 002-04980 Rev. *E S6E2C Series Datasheet 0.8×VCC 0.2×VCC tri Page 169 of 200 S6E2C Series I2SMCLK Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Value Symbol Pin Name Conditions Input frequency fCHS I2SMCK - - 25 MHz Input clock cycle tCYLHS - 40 - ns - - PWHS/tCYLHS PWLS/tCYLHS 45 55 % tCFS tCRS - - - 5 ns Parameter Input clock pulse width Input clock rise time and fall time Min Max Unit Remarks When using external clock When using external clock tCYLHS I2SMCLK 0.8×VCC 0.8×VCC 0.8×VCC 0.2×VCC PWHS 0.2×VCC PWLS tCFS tCRS I2SMCLK Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions fCHS I2SMCK - Output frequency Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Min - Value Max 12.288 Unit Remarks MHz Page 170 of 200 S6E2C Series 12.4.21 High-Speed Quad SPI Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Serial clock frequency Enabled CS→ CLK Starting Time (mode0/mode2) Enabled CS→ CLK Starting Time (mode1/mode3) CLK Last→ Disabled CS Time (mode0/mode2) CLK Last→ Disabled CS Time (mode1/mode3) SIO Data output time SIO Setup SIO Hold Symbol tSCYCM Pin Name Conditions tOSKSL02 Unit 66 MHz CL = 30 pF - 50 MHz 1.5×tSCYCM - 5 - ns tSCYCM - 5 - ns tSCYCM - ns 1.5×tSCYCM - ns CL = 15 pF, VCC = 3.0 to 3.6V 0 5 ns CL = 30 pF 0 5 3 - 10 - 0.5×tSCYCM - Q_SCK_0 Q_SCK_0, Q_CS0_0, Q_CS1_0, Q_CS2_0 tOSDAT tSDHOLD Max - Q_SCK_0, Q_IO0_0, Q_IO1_0, Q_IO2_0, Q_IO3_0 Remarks When RTM = 1 and mode = 0, 1, 3 When RTM = 1 and mode = 2 or RTM = 0 and mode = 0, 1, 2, 3 CL = 30 pF tOSKSL13 tDSSET Value CL = 15 pF, VCC = 3.0 to 3.6V tOSLSK02 tOSLSK13 Min ns CL = 30 pF CL = 30 pF When RTM = 1 and mode = 0, 1, 3 When RTM = 1 and mode = 2 or RTM = 0 and mode = 0, 1, 2, 3 ns Notes: − See Chapter 8-3: High-Speed Quad SPI controller in FM4 Family Peripheral Manual Communication Macro Part (00204862) for the detail of RTM mode. − When using High-Speed Quad SPI, please set PDSR register to set the pin drive capability for VCC = 3V. See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 171 of 200 S6E2C Series Q_CS0, Q_CS1, Q_CS2 tSCYCM mode0 mode2 tOSLSK02 Q_SCK tOSKSL02 mode1 mode3 tOSKSL13 tOSLSK13 input Q_IO0, Q_IO1, Q_IO2, Q_IO3 tDSSET tSDHOLD output tOSDAT Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 172 of 200 S6E2C Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Min - 4.5 - 2.5 - 15 AVRH – 15 AVCC - 15 Value Typ - Max 12 + 4.5 + 2.5 + 15 AVRH + 15 AVCC + 15 Parameter Symbol Resolution Integral nonlinearity Differential nonlinearity Zero transition voltage Full-scale transition voltage VZT Pin Name ANxx VFST ANxx Conversion time - - 0.5145 - - μs AVCC ≥ 4.5V Sampling time146 tS - 0.15 0.3 - 10 μs AVCC ≥ 4.5V AVCC < 4.5V Compare clock cycle147 tCCK - 25 - 1000 50 - 1000 State transition time to operation permission tSTT - - - 1.0 μs Power supply current (analog + digital) - AVCC - 0.69 0.92 mA - 1.3 22 μA Reference power supply current (AVRH) - - 1.1 1.97 mA - 0.3 6.3 μA pF LSB AVRH Unit bit LSB LSB mV mV mV ns Analog input capacity CAIN - - - Analog input resistance RAIN - - - Interchannel disparity Analog port input leak current - - - - 12.05 1.2 1.8 4 - ANxx - - 5 μA Analog input voltage - ANxx AVRH - AVRL - AVRH AVCC AVCC AVCC AVSS V V - AVSS AVSS 4.5 2.7 AVSS Reference voltage kΩ V Remarks AVRH = 2.7V to 5.5V AVCC ≥ 4.5V AVCC < 4.5V A/D 1 unit operation When A/D stop A/D 1 unit operation AVRH = 5.5V When A/D stop AVCC ≥ 4.5V AVCC < 4.5V Tcck ＜50 ns Tcck ≥ 50 ns V 145 The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is when the value of T s = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part (002-04860). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus number to which the A/D converter is connected, see 1 Block Diagram in this data sheet. The sampling clock and compare clock are set at base clock (HCLK). 146 A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). 147 The compare time (tC) is the value of (Equation 2). Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 173 of 200 S6E2C Series ANxx Analog input pin Rext Comparator R AIN Rin Analog signal source Cin CAIN (Equation 1) tS ≥ (RAIN + Rext) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D = 1.2 kΩ at 4.5V ≤ AVCC ≤ 5.5V Input resistance of A/D = 1.8 kΩ at 2.7V ≤ AVCC < 4.5V CAIN: Input capacity of A/D = 12.05 pF at 2.7V ≤ AVCC ≤ 5.5V Rext: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 174 of 200 S6E2C Series Definition of 12-bit A/D Converter Terms ◼ Resolution: Analog variation that is recognized by an A/D converter. ◼ Integral nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. ◼ Differential nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral nonlinearity 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD Differential nonlinearity Actual conversion characteristics Ideal characteristics 0x002 0x001 0xN Ideal characteristics VNT Actual conversion characteristics AVRH AVss Analog input Differential nonlinearity of digital output N = N: VZT: VFST: VNT: AVRH Analog input Integral nonlinearity of digital output N = 1LSB = (Actually-measured value) (Actually-measured value) 0x(N-2) VZT (Actually-measured value) AVss V(N+1)T 0x(N-1) VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 175 of 200 S6E2C Series 12.6 12-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Resolution Conversion time Integral nonlinearity148 Differential nonlinearity148 Output voltage offset Analog output impedance Power supply current148 Symbol tC20 tC100 INL DNL DAx VOFF RO IDDA IDSA 148 Pin Name AVCC Min 0.56 2.79 - 16 Value Typ 0.69 3.42 - Max 12 0.81 4.06 + 16 - 0.98 - + 1.5 LSB - 20.0 3.10 2.0 3.80 - + 10 + 1.4 4.50 - mV mV kΩ MΩ 260 330 410 μs 400 510 620 μs - - 14 μs Unit Remarks bit μs μs LSB Load 20 pF Load 100 pF When setting 0x000 When setting 0xFFF D/A operation When D/A stop D/A 1ch operation AVCC = 3.3V D/A 1ch operation AVCC = 5.0V When D/A stop During no load Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 176 of 200 S6E2C Series 12.7 USB Characteristics (VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V) Parameter Input characteristics Symbol Conditions Min Value Unit Reference V 1 V 1 Input H level voltage VIH - 2.0 Input L level voltage Differential input sensitivity Different common mode range VIL - VSS - 0.3 Max USBVCC + 0.3 0.8 VDI - 0.2 - V 2 VCM - 0.8 2.5 V 2 2.8 3.6 V 3 0.0 0.3 V 3 1.3 4 4 90 2.0 20 20 111.11 V ns ns % 4 5 5 5 Output L level voltage VOL Crossover voltage Rise time Fall time Rise/fall time matching VCRS tFR tFF tFRFM External pulldown resistance = 15 kΩ External pull-up resistance = 1.5 kΩ Full-Speed Full-Speed Full-Speed Output impedance ZDRV Full-Speed 28 44 Ω 6 Rise time Fall time Rise/fall time matching tLR tLF Low-Speed Low-Speed Low-Speed 75 75 80 300 300 125 ns ns % 7 7 7 Output H level voltage Output characteristics Pin Name VOH UDP0/ UDM0, UDP1/ UDM1 tLRFM References: 1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8V, VIH (Min) = 2.0V (TTL input standard). There is some hysteresis applied to lower noise sensitivity. 2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8V to 2.5V to the local ground reference level. Minimum differential input sensitivity [V] Above voltage range is the common mode input voltage range. Common mode input voltage [V] Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 177 of 200 S6E2C Series 3: The output drive capability of the driver is below 0.3V at low state (VOL) (to 3.6V and 1.5 kΩ load), and 2.8V or above (to the VSS and 1.5 kΩ load) at high state (VOH). 4: The cross voltage of the external differential output signal (D +/D −) of USB I/O buffer is within 1.3V to 2.0V. VCRS specified range 5: They indicate rise time (tRISE) and fall time (tFALL) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, tR/tF ratio is regulated as within ± 10% to minimize RFI emission. D+ 90% D- 90% 10% 10% TRISE TFALL Falling time Rise time Full-speed Buffer Rs=27  TxD+ CL=50 pF Rs=27  TxDCL=50 pF 3-State Enable Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 178 of 200 S6E2C Series 6: USB Full-speed connection is performed via twisted-pair cable shield with 90Ω ± 15% characteristic impedance (differential mode). USB standard defines that the output impedance of the USB driver must be in the range from 28 Ω to 44 Ω. So, a discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommended value 27 Ω) series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence.” 7: They indicate rise time (tRISE) and fall time (tFALL) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. D+ 90% D- 90% 10% 10% TRISE Rise time TFALL Falling time Note: − See Low-Speed Load (Compliance Load) for conditions of external load. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 179 of 200 S6E2C Series Low-Speed Load (Upstream Port Load) - Reference 1 CL=50pF to 150pF CL=50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL= 200pF to 600pF CL= 200pF to 600pF Low-Speed Load (Compliance Load) CL=200pF to 450pF CL=200pF to 450pF Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 180 of 200 S6E2C Series 12.8 Low-Voltage Detection Characteristics 12.8.1 Low-Voltage Detection Reset Parameter Min Value Typ Max - 2.46 2.55 2.64 V - 2.51 2.60 2.69 V Min Value Typ Max Symbol Conditions Detected voltage VDL Released voltage VDH Unit Remarks When voltage drops When voltage rises 12.8.2 Interrupt of Low-Voltage Detection Parameter Detected voltage Symbol Conditions VDL Unit 2.80 2.90 3.00 V 2.90 3.00 3.11 V 2.99 3.10 3.21 V 3.09 3.20 3.31 V 3.18 3.30 3.42 V 3.28 3.40 3.52 V 3.67 3.80 3.93 V 3.76 3.90 4.04 V 3.76 3.90 4.04 V 3.86 4.00 4.14 V 4.05 4.20 4.35 V 4.15 4.30 4.45 V 4.15 4.30 4.45 V 4.25 4.40 4.55 V 4.25 4.40 4.55 V 4.34 4.50 4.66 V - - SVHI = 00111 Released voltage VDH Detected voltage VDL SVHI = 00100 Released voltage VDH Detected voltage VDL SVHI = 01100 Released voltage VDH Detected voltage VDL SVHI = 01111 Released voltage VDH Detected voltage VDL SVHI = 01110 Released voltage VDH Detected voltage VDL SVHI = 01001 Released voltage VDH Detected voltage VDL SVHI = 01000 Released voltage VDH Detected voltage VDL SVHI = 11000 149 Released voltage VDH LVD stabilization wait time tLVDW - 6000×tCYCP 149 Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises μs tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 181 of 200 S6E2C Series 12.9 MainFlash Memory Write/Erase Characteristics (VCC = 2.7V to 5.5V) Parameter Sector erase time Half word (16bit) write time Min Value Typ Max Unit Large Sector - 0.7 3.7 s Small Sector - 0.3 1.1 s Write cycles < 100 times Write cycles > 100 times - 12 Chip erase time150 100 13.6 68 Includes write time prior to internal erase μs Not including system-level overhead time s Includes write time prior to internal erase 200 - Remarks Write Cycles and Data Retention Time Erase/Write Cycles (Cycle) Data Retention Time (Year) 1,000 20151 10,000 10151 100,000 5151 12.10 Dual Flash Memory Write/Erase Characteristics It is the same write/erase characteristics as the MainFlash memory. See 3.6 Dual flash mode in this product's Flash Programming Manual for the detail of dual flash mode. 150 It indicates the chip erase time of 1 MB MainFlash memory For devices with 1.5 MB or 2 MB of MainFlash memory, two erase cycles are required. See 3.2.2 Command Operating Explanations and 3.3.3 Flash Erase Operation in this product's Flash Programming Manual for the detail. 151 This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C). Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 182 of 200 S6E2C Series 12.11 Standby Recovery Time 12.11.1 Recovery Cause: Interrupt/WKUP The time from the interrupt occurring to the time of program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Typ Sleep mode High-speed CR Timer mode Main Timer mode PLL Timer mode Value Unit Max152 HCLK×1 μs 40 80 μs Low-speed CR Timer mode 450 900 μs Sub Timer mode 896 1136 μs 316 581 μs 270 540 μs 365 667 μs 365 667 μs RTC mode Stop mode (High-speed CR/Main/PLL Run mode return) RTC mode Stop mode (Low-speed CR/sub Run mode return) tICNT Deep Standby RTC mode with RAM retention Deep Standby Stop mode with RAM retention Remarks without RAM retention with RAM retention Example of Standby Recovery Operation (when in External Interrupt Recovery153) Ext.INT Interrupt factor accept Active tICNT CPU Operation 152 153 Interrupt factor clear by CPU Start The maximum value depends on the built-in CR accuracy. External interrupt is set to detecting fall edge. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 183 of 200 S6E2C Series Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery154) Internal Resource INT Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start Notes: − The return factor is different in each low-power consumption mode. See Chapter 6: Low Power Consumption mode and Operations of Standby modes in FM4 Family Peripheral Manual Main Part (002-04856). − The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family Peripheral Manual Main Part (002-04856). 154 Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 184 of 200 S6E2C Series 12.11.2 Recovery Cause: Reset The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Sleep mode High-speed CR Timer mode Main Timer mode PLL Timer mode Low-speed CR Timer mode Sub Timer mode tRCNT RTC mode Stop mode Deep Standby RTC mode with RAM retention Deep Standby Stop mode with RAM retention Typ 155 Value Max155 266 Unit Remarks μs 155 266 μs 315 567 μs 315 567 μs 315 567 μs 336 667 μs 336 667 μs without RAM retention with RAM retention Example of Standby Recovery Operation (when in INITX Recovery) INITX Internal RST RST Active Release tRCNT CPU Operation 155 Start The maximum value depends on the built-in CR accuracy. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 185 of 200 S6E2C Series Example of Standby Recovery Operation (when in Internal Resource Reset Recovery156) Internal Resource RST Internal RST RST Active Release tRCNT CPU Operation Start Notes: − The return factor is different in each low power consumption mode. See Chapter 6: Low Power Consumption mode and Operations of Standby modes in “FM4 Family Peripheral Manual Main Part (002-04856). − The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family Peripheral Manual Main Part (002-04856). − When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-On Reset Timing. − In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock, they need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock. − Internal resource reset indicates Watchdog reset and CSV reset. 156 Depending on the low-power consumption mode, the reset issue from the internal resource is not included in the recovery cause. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 186 of 200 S6E2C Series 13. Ordering Information S6E2 C C 9 J0AGV 2000A Package Identifier Memory Size Product Feature Set C Series Cypress FM 4 MCU Part Number Flash (MB) RAM (KB) USB 2.0 CAN/ CAN FD S6E2CC9L0AGL2000A 1.5 192 2ch 2ch/1ch S6E2CCAL0AGL2000A 2 256 2ch 2ch/1ch S6E2C58H0AGV2000A S6E2C59H0AGV2000A 1 1.5 128 192 2ch 2ch 2ch/1ch 2ch/1ch EthernetMAC 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) N/A N/A S6E2CC8H0AGV2000A 1 128 2ch 2ch/1ch S6E2C5AH0AGV2000A 2 256 2ch 2ch/1ch N/A S6E2C58J0AGV2000A S6E2C59J0AGV2000A 1 1.5 128 192 2ch 2ch 2ch/1ch 2ch/1ch N/A N/A S6E2C5AJ0AGV2000A 2 256 2ch 2ch/1ch N/A S6E2CC9H0AGV2000A 1.5 192 2ch 2ch/1ch S6E2CCAH0AGV2000A 2 256 2ch 2ch/1ch S6E2CC8J0AGV2000A 1 128 2ch 2ch/1ch S6E2CC9J0AGV2000A 1.5 192 2ch 2ch/1ch S6E2CCAJ0AGV2000A 2 256 2ch 2ch/1ch S6E2CC8J0AGB1000A 1 128 2ch 2ch/1ch S6E2CC9J0AGB1000A 1.5 192 2ch 2ch/1ch S6E2CCAJ0AGB1000A 2 256 2ch 2ch/1ch S6E2CC8L0AGL2000A 1 128 2ch 2ch/1ch Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Package Plastic LQFP (0.5 mm pitch), 144 pin (LQS144) Plastic LQFP (0.5 mm pitch), 176 pin (LQP176) Plastic FBGA (0.8 mm pitch), 192 pin (LBE192) Plastic LQFP (0.4 mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Page 187 of 200 S6E2C Series S6E2C58J0AGB1000A S6E2C59J0AGB1000A Flash (MB) 1 1.5 RAM (KB) 128 192 USB 2.0 2ch 2ch CAN/ CAN FD 2ch/1ch 2ch/1ch EthernetMAC N/A N/A S6E2C5AJ0AGB1000A 2 256 2ch 2ch/1ch N/A S6E2C58L0AGL2000A S6E2C59L0AGL2000A 1 1.5 128 192 2ch 2ch 2ch/1ch 2ch/1ch N/A N/A S6E2C5AL0AGL2000A 2 256 2ch 2ch/1ch N/A S6E2C48H0AGV2000A S6E2C49H0AGV2000A 1 1.5 128 192 N/A N/A 2ch/1ch 2ch/1ch N/A N/A S6E2C4AH0AGV2000A 2 256 N/A 2ch/1ch N/A S6E2C48J0AGV2000A S6E2C49J0AGV2000A 1 1.5 128 192 N/A N/A 2ch/1ch 2ch/1ch N/A N/A S6E2C4AJ0AGV2000A 2 256 N/A 2ch/1ch N/A S6E2C48J0AGB1000A S6E2C49J0AGB1000A 1 1.5 128 192 N/A N/A 2ch/1ch 2ch/1ch N/A N/A S6E2C4AJ0AGB1000A 2 256 N/A 2ch/1ch N/A S6E2C48L0AGL2000A S6E2C49L0AGL2000A 1 1.5 128 192 N/A N/A 2ch/1ch 2ch/1ch N/A N/A S6E2C4AL0AGL2000A 2 256 N/A 2ch/1ch N/A S6E2C38H0AGV2000A S6E2C39H0AGV2000A 1 1.5 128 192 2ch 2ch N/A N/A N/A N/A S6E2C3AH0AGV2000A 2 256 2ch N/A N/A S6E2C38J0AGV2000A S6E2C39J0AGV2000A 1 1.5 128 192 2ch 2ch N/A N/A N/A N/A S6E2C3AJ0AGV2000A 2 256 2ch N/A N/A S6E2C38J0AGB1000A S6E2C39J0AGB1000A 1 1.5 128 192 2ch 2ch N/A N/A N/A N/A S6E2C3AJ0AGB1000A 2 256 2ch N/A N/A S6E2C38L0AGL2000A S6E2C39L0AGL2000A 1 1.5 128 192 2ch 2ch N/A N/A N/A N/A S6E2C3AL0AGL2000A 2 256 2ch N/A N/A S6E2C28H0AGV2000A 1 128 2ch N/A Part Number S6E2C29H0AGV2000A 1.5 192 2ch N/A S6E2C2AH0AGV2000A 2 256 2ch N/A S6E2C28J0AGV2000A 1 128 2ch N/A S6E2C29J0AGV2000A 1.5 192 2ch N/A S6E2C2AJ0AGV2000A 2 256 2ch N/A Document Number: 002-04980 Rev. *E S6E2C Series Datasheet 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) Package Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Page 188 of 200 S6E2C Series Part Number Flash (MB) RAM (KB) USB 2.0 CAN/ CAN FD S6E2C29L0AGL2000A 1.5 192 2ch N/A S6E2C2AL0AGL2000A 2 256 2ch N/A S6E2C18H0AGV2000A S6E2C19H0AGV2000A 1 1.5 128 192 N/A N/A N/A N/A EthernetMAC 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) N/A N/A S6E2C28J0AGB1000A 1 128 2ch N/A S6E2C1AH0AGV2000A 2 256 N/A N/A N/A S6E2C18J0AGV2000A 1 128 N/A N/A N/A S6E2C19J0AGV2000A S6E2C1AJ0AGV2000A S6E2C18J0AGB1000A S6E2C19J0AGB1000A 1.5 2 1 1.5 192 256 128 192 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A S6E2C1AJ0AGB1000A 2 256 N/A N/A N/A S6E2C18L0AGL2000A S6E2C19L0AGL2000A 1 1.5 128 192 N/A N/A N/A N/A N/A N/A S6E2C1AL0AGL2000A 2 256 N/A N/A N/A S6E2C48J0AGB1000A S6E2C49J0AGB1000A 1 1.5 128 192 N/A N/A 2ch/1ch 2ch/1ch N/A N/A S6E2C4AJ0AGB1000A 2 256 N/A 2ch/1ch N/A S6E2C48L0AGL2000A S6E2C49L0AGL2000A 1 1.5 128 192 N/A N/A 2ch/1ch 2ch/1ch N/A N/A S6E2C4AL0AGL2000A 2 256 N/A 2ch/1ch N/A S6E2C38H0AGV2000A S6E2C39H0AGV2000A 1 1.5 128 192 2ch 2ch N/A N/A N/A N/A S6E2C3AH0AGV2000A 2 256 2ch N/A N/A S6E2C38J0AGV2000A S6E2C39J0AGV2000A 1 1.5 128 192 2ch 2ch N/A N/A N/A N/A S6E2C3AJ0AGV2000A 2 256 2ch N/A N/A S6E2C38J0AGB1000A S6E2C39J0AGB1000A 1 1.5 128 192 2ch 2ch N/A N/A N/A N/A S6E2C3AJ0AGB1000A 2 256 2ch N/A N/A S6E2C29J0AGB1000A 1.5 192 2ch N/A S6E2C2AJ0AGB1000A 2 256 2ch N/A S6E2C28L0AGL2000A 1 128 2ch N/A Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Package Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Page 189 of 200 S6E2C Series S6E2C38L0AGL2000A S6E2C39L0AGL2000A Flash (MB) 1 1.5 RAM (KB) 128 192 USB 2.0 2ch 2ch CAN/ CAN FD N/A N/A EthernetMAC N/A N/A S6E2C3AL0AGL2000A 2 256 2ch N/A N/A S6E2C28H0AGV2000A 1 128 2ch N/A Part Number S6E2C29L0AGL2000A 1.5 192 2ch N/A S6E2C2AL0AGL2000A 2 256 2ch N/A S6E2C18H0AGV2000A S6E2C19H0AGV2000A 1 1.5 128 192 N/A N/A N/A N/A 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) 1ch (max) MII: 1ch RII: 1ch (max) N/A N/A S6E2C1AH0AGV2000A 2 256 N/A N/A N/A S6E2C18J0AGV2000A 1 128 N/A N/A N/A S6E2C19J0AGV2000A S6E2C1AJ0AGV2000A S6E2C18J0AGB1000A S6E2C19J0AGB1000A 1.5 2 1 1.5 192 256 128 192 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A S6E2C1AJ0AGB1000A 2 256 N/A N/A N/A S6E2C18L0AGL2000A S6E2C19L0AGL2000A 1 1.5 128 192 N/A N/A N/A N/A N/A N/A S6E2C1AL0AGL2000A 2 256 N/A N/A N/A S6E2C29H0AGV2000A 1.5 192 2ch N/A S6E2C2AH0AGV2000A 2 256 2ch N/A S6E2C28J0AGV2000A 1 128 2ch N/A S6E2C29J0AGV2000A 1.5 192 2ch N/A S6E2C2AJ0AGV2000A 2 256 2ch N/A S6E2C28J0AGB1000A 1 128 2ch N/A S6E2C29J0AGB1000A 1.5 192 2ch N/A S6E2C2AJ0AGB1000A 2 256 2ch N/A S6E2C28L0AGL2000A 1 128 2ch N/A Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Package Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) Page 190 of 200 S6E2C Series 14. Acronyms Acronym ADC ACK AHB ARM® CEC CMOS CPU CR CRC CSIO CSV CTS DTSC EOM FIFO GPIO HDMI HDMI-CEC I/F I2C, or IIC I2S, or IIS I/O IRQ LIN LVD MFS MSB MTB NMI NVIC OS OSC PLL PPG PWC PWM RAM RX RTS SPI SRAM SW-DP TX UART USB Description analog-to-digital converter acknowledge AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus Advanced RISC Machine, a CPU architecture Consumer Electronics Control, a command and control interface over HDMI (High Definition Multimedia Interface) complementary metal oxide semiconductor central processing unit clock and reset cyclic redundancy check, an error-checking protocol clock synchronous serial interface clock supervisor clear to send, a flow control signal in some data communication interfaces descriptor system data transfer controller end of message first in, first out general-purpose input/output High Definition Multimedia Interface High Definition Multimedia Interface - Consumer Electronics Control, see CEC interface Inter-Integrated Circuit, a communications protocol Inter-IC (integrated circuit) Sound, a communications protocol input/output, see also GPIO interrupt request Local Interconnect Network, a communications protocol low-voltage detect multi-function serial most significant byte micro trace buffer non-maskable interrupt nested vectored interrupt controller operating system oscillator phase-locked loop programmable pulse generator pulse-width counter pulse-width modulator random access memory receive request to send, a flow control signal in some data communication interfaces Serial Peripheral Interface, a communications protocol static random access memory serial wire debug port transmit universal asynchronous receiver transmitter Universal Serial Bus Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 191 of 200 S6E2C Series 15. Package Dimensions Package Type Package Code Specification No. LQFP 144 LQS 144 002-13015 *B 4 D D1 10 8 4 5 7 7 5 73 10 9 73 72 D D1 108 10 9 72 E1 E 5 7 E 4 4 E1 5 7 3 3 6 14 4 37 1 14 4 37 36 1 36 BOTTOM VIEW 2 5 7 e 3 0.1 0 C A-B D 0.2 0 C A-B D b 0.0 8 TOP VIEW C A-B D 8 2 A 9 c A A' 0.0 8 C SEATING PLAN E L1 0.25 L A1 10 b SECTION A-A' SIDE VIEW SYMBOL DIM ENSIONS M IN. NOM. M AX. 1.70 A A1 0.05 b 0.17 c 0.09 0.15 0.22 0.27 0.20 D 22.00 BSC D1 20.00 BSC e 0.50 BSC E 22.00 BSC 20.00 BSC E1 L 0.45 0.60 0.75 L1 0.30 0.50 0.70 PACKAGE OUTLINE, 144 LEAD LQFP 20.0X20.0X1.7 M M LQS144 REV*A Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 192 of 200 S6E2C Series Package Type Package Code Specification No. LQFP 176 LQP 176 002-15150 *A D D1 132 4 5 7 89 133 89 88 132 133 88 E1 E 5 7 4 3 6 176 45 1 176 45 44 44 1 2 5 7 e 3 BOTTOM VIEW 0.10 C A-B D 0.20 C A-B D b 0.08 C A-B D 8 TOP VIEW 2 A A A' 0.08 C SIDE VIEW SYM BOL NOM . M AX. 0.05 0.15 L1 0.25 A1 10 L c b SECTION A-A' 1.70 b 0.17 c 0.09 0.22 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 0.27 0.20 D 24.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ SEA TIN G PLAN E DIM ENSIONS M IN. A A1 9 θ 0° 8° PACKAGE OUTLINE, 176 LEAD LQFP 24.0X24.0X1.7 M M LQP176 REV** Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 193 of 200 S6E2C Series Package Type Package Code Specification No. LQFP 216 LQQ 216 002-15153 ** 4 D 5 7 D1 162 109 1 09 108 163 162 108 163 55 216 E1 E 5 4 7 3 6 55 216 1 54 1 54 e 2 5 7 3 0.10 C A-B D 0.20 C A-B D b 0.07 C A-B D BOTTOM VIEW 8 TOP VIEW 2 A θ A A' SEA TIN G PLAN E L1 0.08 C 9 0.25 L A1 10 c b SECTION A-A' SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. 0.05 0.15 1.70 A A1 b 0.13 c 0.09 0.18 0.23 0.20 D 26.00 BSC. D1 24.00 BSC. e 0.40 BSC E 26.00 BSC. 24.00 BSC. E1 L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° PACKAGE OUTLINE, 216 LEAD LQFP 24.0X24.0X1.7 M M LQQ216 REV** Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 194 of 200 S6E2C Series Package Type Package Code Specification No. PFBGA 192 LBE 192 002-13493 *A A 0.20 C 14 2X 13 12 7 11 10 9 8 7 6 5 4 3 2 1 P PIN A1 CORNER INDEX M ARK 8 N M L K J H G F E B D C B A 7 192xφb 0.20 C 0.08 C A B 6 2X TOP VIEW BOTTOM VIEW DETAIL A 0.10 C C SIDE VIEW DETAIL A NOTES DIM ENSIONS SYM BOL M IN. NOM . A A1 0.25 D 0.35 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 1.45 2. DIM ENSIONS AND TOLERANCES M ETHODS PER ASM E Y14.5-2009. THIS OUTLINE CONFORM S TO JEP95, SECTION 4.5. 0.45 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010. 4. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 12.00 BSC E 12.00 BSC D1 10.40 BSC E1 10.40 BSC MD 14 ME 14 n 192 Φb M AX. 0.35 0.45 eD 0.80 BSC eE 0.80 BSC SD / SE 0.40 BSC 5. SYM BOL "M D"IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION. SYM BOL "M E"IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. n IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX SIZE M D X M E. 6. DIM ENSION "b "IS M EASURED AT THE M AXIM UM BALL DIAM ETER IN A PLANE PARALLEL TO DATUM C. 0.55 7. "SD" AND "SE" ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . W HEN THERE IS AN ODD NUM BER OF SOLDER BALLS IN THE OUTER ROW , "SD"OR "SE"= 0. W HEN THERE IS AN EVEN NUM BER OF SOLDER BALLS IN THE OUTER ROW , "SD"= eD/2 AND "SE" = eE/2. 8. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK. M ETALLIZED M ARK INDENTATION OR OTHER M EANS. 9. "+ "INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. PACKAGE OUTLINE, 192 BALL FBGA 12.00X12.00X1.45 M M LBE192 REV*A Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 195 of 200 S6E2C Series 16. Major Changes Spansion Publication Number: DS709-00009 Page Section Revision 0.1 Revision 0.2 1, 3 14 16, 17 Change Results Initial release - Added the following products. S6E2CC8HHA/S6E2CC9HHA/S6E2CCAHHA/ S6E2CC8JHA/S6E2CC9JHA/S6E2CCAJHA/ S6E2CC8LHA/S6E2CC9LHA/S6E2CCALHA Added “Crypto Assist Function” Added “Crypto Assist Function” Added the following products. S6E2CC8HHA/S6E2CC9HHA/S6E2CCAHHA/ S6E2CC8JHA/S6E2CC9JHA/S6E2CCAJHA/ S6E2CC8LHA/S6E2CC9LHA/S6E2CCALHA Added the following part numbers. S6E2CC8HHAGV20000/S6E2CC9HHAGV20000/S6E2CCAHHAGV2000/ S6E2CC8JHAGV20000/S6E2CC9JHAGV20000/S6E2CCAJHAGV20000/ S6E2CC8JHAGB10000/S6E2CC9JHAGB10000/S6E2CCAJHAGB10000/ S6E2CC8LHAGL20000/S6E2CC9LHAGL20000/S6E2CCALHAGL20000 Title 2.Feature 3.Product Lineup 18 4.Packages 212 15.ORDERING INFORMATION Revision 0.3 1, 3 Title 14 2.Features 15, 16 Added the following products. S6E2CCAJGA /S6E2CC8JGA/S6E2CC8JFA/S6E2CCAJFA Added Voice Function Added the following products. S6E2CCAJGA /S6E2CC8JGA/S6E2CC8JFA/S6E2CCAJFA Added the following products. S6E2CCAJGA /S6E2CC8JGA/S6E2CC8JFA/S6E2CCAJFA Added the following products. S6E2CCAJGAGV20000/ S6E2CC8JGAGB10000/ S6E2CC8JFAGB10000 S6E2CCAJGAGB10000/ S6E2CCAJFAGB10000 3.Product Lineup 17 4.Packages 211 15.Ordering Information Revision 1.0 7 2. Features 15 3. Product Lineup 12 2. Features 15 3. Product Lineup 90 10. Block Diagram 91 12. Memory Map 18-20 5. Pin Assignments 22-24 6. Pin Descriptions 75-82 7. I/O Circuit Type Added that CAN-FD Interface supported non-CAN FD. Deleted HDM-CEC/Remote Control Receiver. 97-105 106-107 13. Pin Status In Each CPU State 14.1. Absolute Maximum Ratings 108-112 14.2. Recommended Conditions 113-122 14.3.1. Current Rating 123-124 14.3.2. Pin Characteristics Document Number: 002-04980 Rev. *E Operating Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1) Modified the pin name of I2S. (MI2S*_0→MI2S*0_0) Deleted the pin of IGTRG0_0. Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1) Modified the pin name of I2S. (MI2S*_0→MI2S*0_0) Modified the pin number of PF7 in LQFP216.(91→90) Modified the pin number of X1. (73, 58, 50, P5→107, 87, 71, P13) Modified the pin number of X0A. (107, 87, 71, P13→73, 58, 50, P5) Modified IOH/IOL of Type S.(IOH=-12mA→-10mA, IOL=12mA→10mA) Added the case of using I2C in Type E, F, G, L, N, S. Deleted X and Y in Pin Status Type. Added 10mA type. Added AVRL in Analog reference voltage. Modified the mistake in Ethernet-MAC Pins. Modified the leakage current in Maximum leakage current at operating Modified the maximum current of each category. Added the characteristic of external bus in H level input voltage (hysteresis input). Added the characteristic of 10mA type. S6E2C Series Datasheet Page 196 of 200 S6E2C Series Page Section Change Results 127 14.4.5. Operating Conditions of USB/Ethernet PLL・I2S PLL (in the case of using main clock for input clock of PLL) Modified the maximum of I2S PLL macro oscillation clock frequency. (307.2MHz→384MHz) 196 14.5.12-bit A/D Converter Modified the minimum of Sampling time. Modified the characteristic of State transition time to operation permission Added AVRL in Analog reference voltage. 14.8.2. Interrupt of Low-Voltage Modified the SVHI values in Conditions Detection NOTE: Please see “Document History” for later revised information. 204 Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 197 of 200 S6E2C Series Document History Document Title: FM4: S6E2C Series Microcontroller Datasheet 200 MHz Arm® Cortex®-M4F High-Performance MCU Document Number: 002-04980 Revision ECN ** - Orig. of Submission Change Date AKIH 03/25/2015 Description of Change New spec. Company name and layout design change. *A 5126421 HITK 02/05/2016 Added the note of TAP pin. Updated Package Code and Dimensions (LQFP-144, LQFP-176, LQFP-216). Updated “12.4.8 Power-On Reset Timing” to change parameter from “Power Supply rise time(tVCCR)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments. Modified typos in “12.4.12 CSIO (SPI) Timing”. Deleted “SPI=1, MS=0” in the titles and added MS=0,1 in the schematic Modified Real-Time Clock(RTC) in “Features” Changed starting count value from 01 to 00. Deleted “second, or day of the week” in the Interrupt function. Modifications related to the VBAT in the following chapter. “8 Handling Devices” Notes on Power-on “11. Pin Status in Each CPU State” List of VBAT Domain Pin Status “12.3.1 Current Rating” Deleted descriptions about Voice function Deleted MPNs below from “13. Ordering Information” S6E2CCAJGAGV20000, S6E2CC8JGAGB10000, S6E2CC8JFAGB10000, S6E2CCAJGAGB10000, S6E2CCAJFAGB10000 S6E2CC8H0AGV20000, S6E2CC9H0AGV20000, S6E2CCAH0AGV20000, *B 5634625 YSKA 02/20/2017 S6E2CC8HHAGV20000, S6E2CC9HHAGV20000, S6E2CCAHHAGV20000, S6E2CC8J0AGV20000, S6E2CC9J0AGV20000, S6E2CCAJ0AGV20000, S6E2CC8JHAGV20000, S6E2CC9JHAGV20000, S6E2CCAJHAGV20000, S6E2CC8J0AGB10000, S6E2CC9J0AGB10000, S6E2CCAJ0AGB10000, S6E2CC8JHAGB10000, S6E2CC9JHAGB10000, S6E2CCAJHAGB10000, S6E2CC8L0AGL20000, S6E2CC9L0AGL20000, S6E2CCAL0AGL20000, S6E2CC8LHAGL20000, S6E2CC9LHAGL20000, S6E2CCALHAGL20000 Added MPNs below to “13. Ordering Information” S6E2CC8H0AGV2000A, S6E2CC9H0AGV2000A, S6E2CCAH0AGV2000A, S6E2CC8HHAGV2000A, S6E2CC9HHAGV2000A, S6E2CCAHHAGV2000A, S6E2CC8J0AGV2000A, S6E2CC9J0AGV2000A, S6E2CCAJ0AGV2000A, S6E2CC8JHAGV2000A, S6E2CC9JHAGV2000A, S6E2CCAJHAGV2000A, S6E2CC8J0AGB1000A, S6E2CC9J0AGB1000A, S6E2CCAJ0AGB1000A, S6E2CC8JHAGB1000A, S6E2CC9JHAGB1000A, S6E2CCAJHAGB1000A, S6E2CC8L0AGL2000A, S6E2CC9L0AGL2000A, S6E2CCAL0AGL2000A, S6E2CC8LHAGL2000A, S6E2CC9LHAGL2000A, S6E2CCALHAGL2000A Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 198 of 200 S6E2C Series Revision ECN Orig. of Submission Change Date Description of Change Deleted Baud rate spec for High-Speed Synchronous Serial in “12.4.12 CSIO (SPI) Timing” Modified the expression of the “Built-in CR” and add Note in the “2. Product Lineup” Modified typo(SCLKx_0 -> SCKx_0) Change the name from “USB Function” to “USB Device” Added Maximum Access size in “Features” Updated IO circuit (type A) Completing Sunset Review. Updated Document Title to read as “FM4: S6E2C Series Microcontroller Datasheet 200 MHz ARM Cortex-M4F High-Performance MCU”. Merged S6E2CC, S6E2C5, S6E2C4, S6E2C3, S6E2C2, and S6E2C1 datasheets. Recreated Pin Assignments drawings using only the pin names and added a pin multiplexing table that shows alternative functions. Added navigation aids to tables with hyperlinks to circuit types and pin behavior. Added part differentiation tables at the beginning of the document and reorganized the front of the datasheet to match *C 6110443 MBGR 03/26/2018 Cypress specifications. Replaced table footnotes with continuous footnote numbering (throughout). Added and expanded Ordering Information table. Added the Acronyms table. Updated Package Outlines in 15 Package Dimensions to latest. Changed Typ to Max in 12.4.7 Reset Input Characteristics, 12.4.8 Power-On Reset Timing, and 12.4.9 GPIO Output Characteristics. Removed Crypo function and part numbers that supported Crypto. Completing Sunset Review. *D 6579097 HUAL 05/22/2019 Updated to new template. Updated Block diagram. Updated Pin Description: Updated pin description of pin 25 and 26 corresponding to LQQ216 package. Updated Package Dimensions: *E 7901049 BOO 05/10/2023 Spec 002-13015 – Changed revision from *A to *B. Spec 002-15150 – Changed revision from ** to *A. Updated some format issues across the document. Updated links across the document. Completing Sunset Review. Document Number: 002-04980 Rev. *E S6E2C Series Datasheet Page 199 of 200 S6E2C Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/touch cypress.com/usb cypress.com/wireless Arm and Cortex are the registered trademarks of Arm Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2015-2023. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to di stribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress’s published datasheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04980 Rev. *E May 10, 2023 Page 200 of 200