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S6E2D35G0AGB3000A

S6E2D35G0AGB3000A

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

  • 描述:

    IC MCU 32BIT 384KB FLASH 161FBGA

  • 数据手册
  • 价格&库存
S6E2D35G0AGB3000A 数据手册
Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com S6E2D3 Series 32-bit Arm® Cortex®-M4F, FM4 Microcontroller Devices in the S6E2D3 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the Arm Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I2C, LIN). The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main Part (002-04856). Features 32-bit Arm Cortex-M4F Core External Bus Interface ◼ Processor version: r0p1 ◼ Supports SRAM, NOR, NAND Flash and SDRAM devices ◼ Up to 160 MHz frequency operation ◼ Up to two chip selects CS0 and CS8 (CS8 is only for SDRAM) ◼ Built-in FPU ◼ 8-/16-bit data width ◼ Supports DSP instructions ◼ Memory Protection Unit (MPU): improves the reliability of an embedded system ◼ Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels ◼ 24-bit system timer (Sys Tick): System timer for OS task ◼ Up to 25-bit address bit ◼ Maximum area size : Up to 256 Mbytes ◼ Supports address/data multiplexing ◼ Supports external RDY function ◼ Supports the scramble function  Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0x7FFF_FFFF in 4 Mbytes units.  Possible to set two kinds of the scramble key.  Note: It is necessary to prepare the dedicated software library to use the scramble function. management On-Chip Memories ◼ Flash memory This series has on-chip flash memory with these features:  384 Kbytes  Built-in Flash Accelerator System with 16 Kbytes trace buffer memory  Security function for code protection  Notes: • The read access to flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. • Even at the operation frequency more than 72 MHz, an equivalent access to flash memory can be obtained by Flash Accelerator System. USB Interface (One channel) A USB interface is composed of device and host. ◼ USB device  USB2.0 Full-Speed supported 6 EndPoint supported • EndPoint 0 is for control transfer • EndPoint 1, 2 can be selected for bulk-transfer, interrupttransfer or isochronous-transfer • EndPoint 3 to 5 can select bulk-transfer or interrupttransfer  EndPoint 1 to 5 comprise the double buffer  The size of each endpoint is as follows. • Endpoint 0, 2 to 5: 64 bytes • EndPoint 1: 256 bytes  Max ◼ SRAM This is composed of two independent SRAMs (SRAM0 and SRAM2). SRAM0 is connected to I-code bus and D-code bus of Cortex-M4F core. SRAM2 is connected to the system bus of Cortex-M4F core.  SRAM0: 32 Kbytes  SRAM2: 4 Kbytes ◼ USB host  USB2.0 Full-Speed / Low-Speed supported interrupt-transfer and isochronous-transfer ◼ VRAM  Bulk-transfer, This series is equipped with a SRAM for GDC.  Max 512 Kbytes  USB ◼ VFLASH S6E2D35GJA is equipped with a Flash for GDC.  2 Mbytes Cypress Semiconductor Corporation Document Number: 002-03984 Rev. *D • 198 Champion Court support device connected/disconnected automatically detect  In/out token handshake packet automatically accepted  Max 256-byte packet-length supported  Wake-up function supported • San Jose, CA 95134-1709 • 408-943-2600 Revised June 14, 2021 S6E2D3 Series Multi-function Serial Interface (Max eight channels) ◼ 64 bytes with FIFO (the FIFO step numbers vary depending on the settings of the communication mode or bit length.) ◼ Operation mode is selectable from the following for each channel.  UART  CSIO  LIN  I2 C ◼ UART  Full-duplex double buffer with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detect functions available (parity errors, framing errors, and overrun errors)  Selection ◼ CSIO  Full-duplex double buffer dedicated baud rate generator  Overrun error detect function available  Serial chip select function (ch.6 and ch.7 only)  Supports High-speed SPI (ch.6 only)  Data length 5 to 16-bit  Built-in ◼ LIN  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generation (can change to 13 to 16-bit length)  LIN break delimiter generation (can change to 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors) ◼ I2 C  Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps) supported  Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.4=ch.A) supported DSTC (Descriptor System Data Transfer Controller) (128 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor that has already been constructed on the memory, can directly access the memory/peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation, and the chain activation functions. A/D Converter (Max 24 channels) ◼ 12-bit A/D Converter  Successive Approximation type 2 units  Conversion time: 1.0 μs @ 3.3 V  Priority conversion available (priority at two levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for priority conversion: four steps)  Built-in Base Timer (Max eight channels) Operation mode is selectable from the followings for each channel. ◼ 16-bit PWM timer ◼ 16-bit PPG timer ◼ 16-/32-bit reload timer ◼ 16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set to which I/O port the peripheral function can be allocated. ◼ Capable of pull-up control per pin ◼ Capable of reading pin level directly ◼ Built-in port relocate function DMA Controller (Eight channels) The DMA controller has an independent bus for the CPU, so the CPU and the DMA controller can process simultaneously. ◼ 8 independently configured and operated channels ◼ Transfer can be started by software or requested from the built-in peripherals ◼ Up to 98 general-purpose I/O ports @ 120-pin package ◼ Some I/O pins are 5V tolerant. See "4. Pin Descriptions" and "5. I/O Circuit Type" for the corresponding pins. Multi-Function Timer (One unit) The multi-function timer is composed of the following blocks. ◼ Transfer address area: 32-bit (4 Gbytes) Minimum resolution : 6.25 ns ◼ Transfer mode: Block transfer/Burst transfer/Demand ◼ 16-bit free-run timer × 3ch. transfer ◼ Transfer data type: bytes/half-word/word ◼ Transfer block count: 1 to 16 ◼ Number of transfers: 1 to 65536 ◼ Input capture × 4ch. ◼ Output compare × 6ch. ◼ A/D activation compare × 6ch. ◼ Waveform generator × 3ch. ◼ 16-bit PPG timer × 3ch. Document Number: 002-03984 Rev. *D Page 2 of 182 S6E2D3 Series The following functions can be used to achieve motor control. External Interrupt Controller Unit ◼ PWM signal output function ◼ External interrupt input pin: Max 16 pins ◼ DC chopper waveform output function ◼ Include one non-maskable interrupt (NMI) ◼ Dead time function ◼ Input capture function ◼ A/D converter activate function Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. ◼ DTIF (motor emergency stop) interrupt function This series consists of two different watchdogs, a hardware watchdog and a software watchdog. Real-Time Clock (RTC) The hardware watchdog timer is clocked by low-speed internal CR oscillator. Therefore, the hardware watchdog is active in any power saving mode except RTC mode and stop mode. The real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. ◼ Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported. ◼ Timer interrupt function after set time or each set time. ◼ CCITT CRC16 Generator Polynomial: 0x1021 ◼ Capable of rewriting the time with continuing the time count. ◼ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 ◼ Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC) (One channel) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter. ◼ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. ◼ 16-bit position counter ◼ 16-bit revolution counter ◼ Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) PRGCRC (Programmable Cyclic Redundancy Check) Accelerator The CRC accelerator helps verify data transmission or storage integrity. CCITT CRC16, IEEE-802.3 CRC32 and a generating polynominal are supported. ◼ CCITT CRC16 Generator Polynomial: 0x1021 ◼ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 ◼ Generating polynominal I2S Interface (TX x two channels, RX x two channels) ◼ Support three transfer protocols  I2 S The dual timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. ◼ Master/Slave Mode selectable ◼ Free-running ◼ RX only, TX only or TX and RX simultaneous operation ◼ Periodic (=Reload) ◼ One-shot Watch Counter The watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in High-speed CR clock or built-in Low-speed CR clock as the clock source. Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz  Left Justified mode  DSP selectable ◼ Word length is programmable from 7 bits to 32 bits ◼ RX/TX FIFO integrated (RX: 66 words x 32 bits, TX: 66 words x 32 bits) ◼ DMA, interrupts, or polling based data transfer supported GDC Unit ◼ Controller for external graphics display ◼ Accelerator for 2D block image transfer (blit) operations ◼ Embedded SRAM video memory ◼ High-Speed Quad SPI (Serial Peripheral Interface for external memory extensions) Document Number: 002-03984 Rev. *D Page 3 of 182 S6E2D3 Series ◼ SDRAM interface for external memory extensions Peripheral Clock Gating ◼ HBI (Hyper Bus Interface) interface for external memory The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. extensions ◼ Maximum core system clock frequency : 160 MHz Clock and Reset ◼ Clocks Five clock sources (two external oscillators, two internal CR oscillator, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 20 MHz  Sub Clock : 32.768 kHz  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  Main PLL Clock ◼ Resets  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. ◼ External OSC clock failure (clock stop) is detected, reset is asserted. ◼ External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used. ◼ RTC ◼ 32 kHz oscillation circuit ◼ Power-on circuit ◼ Back up register : 32 bytes ◼ Port circuit Debug ◼ Serial Wire Debug Port (SWJ-DP) ◼ Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Unique ID Unique value of the device (41-bit) is set. Power Supply ◼ Two Power Supplies  Power supply: VCC= 2.7 V to 3.6 V (when USB or GDC unit is not used)  Power = 3.0 V to 3.6 V (when USB or GDC unit is used) supply for VBAT: VBAT= 1.65 V to 3.6 V ◼ LVD1: error reporting via interrupt ◼ LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes are supported. ◼ Sleep ◼ Timer ◼ RTC ◼ Stop ◼ Deep standby RTC (selectable from with/without RAM retention) ◼ Deep standby Stop (selectable from with/without RAM retention) Document Number: 002-03984 Rev. *D Page 4 of 182 S6E2D3 Series Table of Contents Features................................................................................................................................................................................... 1 1. Product Lineup .................................................................................................................................................................. 7 2. Packages ........................................................................................................................................................................... 8 3. Pin Assignment ................................................................................................................................................................. 9 4. Pin Descriptions .............................................................................................................................................................. 13 5. I/O Circuit Type................................................................................................................................................................ 47 6. Handling Precautions ..................................................................................................................................................... 54 6.1 Precautions for Product Design ................................................................................................................................... 54 6.2 Precautions for Package Mounting .............................................................................................................................. 55 6.3 Precautions for Use Environment ................................................................................................................................ 57 7. Handling Devices ............................................................................................................................................................ 58 8. Block Diagram ................................................................................................................................................................. 61 9. Memory Size .................................................................................................................................................................... 62 10. Memory Map .................................................................................................................................................................... 62 11. Pin Status in Each CPU State ........................................................................................................................................ 64 12. Electrical Characteristics ............................................................................................................................................... 72 12.1 Absolute Maximum Ratings ......................................................................................................................................... 72 12.2 Recommended Operating Conditions.......................................................................................................................... 73 12.3 DC Characteristics....................................................................................................................................................... 77 12.3.1 Current Rating .............................................................................................................................................................. 77 12.3.2 Pin Characteristics ....................................................................................................................................................... 87 12.4 AC Characteristics ....................................................................................................................................................... 88 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 88 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 89 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 89 12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 90 12.4.5 Operating Conditions of USB/I2S/GDC PLL (In the Case of Using Main Clock for Input Clock of PLL) ....................... 90 12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) 91 12.4.7 Reset Input Characteristics .......................................................................................................................................... 91 12.4.8 Power-on Reset Timing................................................................................................................................................ 92 12.4.9 GPIO Output Characteristics ........................................................................................................................................ 92 12.4.10 External Bus Timing.................................................................................................................................................. 93 12.4.11 Base Timer Input Timing......................................................................................................................................... 104 12.4.12 CSIO Timing ........................................................................................................................................................... 105 12.4.13 External Input Timing .............................................................................................................................................. 138 12.4.14 Quadrature Position/Revolution Counter Timing .................................................................................................... 139 12.4.15 I2C Timing ............................................................................................................................................................... 142 12.4.16 ETM Timing ............................................................................................................................................................ 143 12.4.17 JTAG Timing ........................................................................................................................................................... 145 12.4.18 I2S Timing ............................................................................................................................................................... 146 12.4.19 GDC:Panel Output Timing ...................................................................................................................................... 151 12.4.20 GDC: SDRAM-IF Timing......................................................................................................................................... 152 12.4.21 GDC: High-Speed Quad SPI Timing....................................................................................................................... 154 12.4.22 GDC: HyperBus I/F Timing ..................................................................................................................................... 156 12.5 12-bit A/D Converter .................................................................................................................................................. 158 12.6 USB Characteristics .................................................................................................................................................. 162 Document Number: 002-03984 Rev. *D Page 5 of 182 S6E2D3 Series 12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 166 12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 166 12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 166 12.8 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 167 12.9 VFLASH Memory Write/Erase Characteristics .......................................................................................................... 167 12.10 Standby Recovery Time ............................................................................................................................................ 168 12.10.1 Recovery Cause: Interrupt/WKUP .......................................................................................................................... 168 12.10.2 Recovery Cause: Reset .......................................................................................................................................... 170 13. Ordering Information .................................................................................................................................................... 172 14. Package Dimensions .................................................................................................................................................... 173 15. Errata.............................................................................................................................................................................. 177 15.1 Part Numbers Affected .............................................................................................................................................. 177 15.2 Qualification Status.................................................................................................................................................... 177 15.3 Errata Summary ........................................................................................................................................................ 177 16. Major Changes .............................................................................................................................................................. 179 Document History ............................................................................................................................................................... 180 Sales, Solutions, and Legal Information ........................................................................................................................... 182 Document Number: 002-03984 Rev. *D Page 6 of 182 S6E2D3 Series 1. Product Lineup Memory Size S6E2D35G0A S6E2D35J0A Product Name On-chip Flash memory 384 Kbytes 36 Kbytes 32 Kbytes 4 Kbytes 512 Kbytes SRAM SRAM0 SRAM2 On-chip SRAM VRAM for GDC VFLASH for GDC S6E2D35GJA - 2 Mbytes Function Product Name S6E2D35G0A 120/161 Pin count CPU Freq. Power supply voltage range USB2.0 (Device/Host) DMAC DSTC Graphics・Display controller GDC High-Speed Quad SPI unit Hyper Bus Interface SDRAM-IF External Bus Interface MF Timer Multi-function Serial Interface (UART/CSIO/LIN/I2C) Base Timer (PWC/Reload timer/PWM/PPG) A/D activation compare 6ch. Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. I2 S QPRC Dual Timer Real-Time Clock Watch Counter CRC Accelerator Watchdog Timer External Interrupts I/O ports 12-bit A/D converter CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in CR Low-speed Debug Function Unique ID S6E2D35J0A S6E2D35GJA 176 120 Cortex-M4F, MPU, NVIC 128ch. 160 MHz 2.7 V to 3.6 V 1ch. 8ch. 128ch. 1 unit 1ch. (VFLASH only) 1 unit 1ch. Addr:25-bit (Max), Data: 8-/16-bit, CS:2 (Max) SRAM, NOR Flash, NAND Flash, SDRAM 8ch. (Max) 8ch. (Max) Document Number: 002-03984 Rev. *D 1 unit 98 pins (Max) 2 units 1ch. 1 unit 1 unit 1 unit Yes(Fixed, Programmable) 1ch. (SW) + 1ch. (HW) 16 pins (Max)+ NMI × 1 154 pins (Max) 24ch. (2 units) Yes 2ch. 4 MHz 100 kHz SWJ-DP/ETM Yes 90 pins (Max) Page 7 of 182 S6E2D3 Series Notes: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. − See 12.4.3 Built-in CR Oscillation Characteristics for the accuracy of the built-in CR. 2. Packages Product Name Package LQFP: LQM120 (0.5 mm pitch) LQFP: LQP176 (0.5 mm pitch) FBGA: FDJ161 (0.5 mm pitch) Ex-LQFP(TEQFP): LEM120 (0.5 mm pitch) S6E2D35G0A S6E2D35J0A S6E2D35GJA     -  - : Supported Note: − See 14. Package Dimensions for detailed information on each package. Document Number: 002-03984 Rev. *D Page 8 of 182 S6E2D3 Series 3. Pin Assignment LQM120 / LEM120 VSS P 81/U D P 0 P 80/U D M 0 VCC P 60/S IN 4_0/IN T 15_1/W K U P 3/M A LE _0 P 61/U H C O N X 0/S O T 4_0/R T C C O _0/S U B O U T _0/M D Q M 0_0 P 62/S C K 4_0/IN T 14_1/M D Q M 1_0 P 63/A D T G _3/R T S 4_0/P N L_P D 0 P 64/C T S 4_0/P N L_P D 1 P 65/P N L_P D 2 P 66/S IN 3_1/IN T 13_1/P N L_P D 3 P 67/S O T 3_1/P N L_P D 4/M S D C K E _0 P 68/S C K 3_1/P N L_P D 5/M S D C LK _0 VSS P 0E /W K U P 2/P N L_P D 6/M C S X 8_0 P 0D /P N L_P D 7/M S D W E X _0 P 0C /S C K 5_1/P N L_P D 8/M A D 11_0 P 0B /S O T 5_1/T IO B 7_1/P N L_P D 9/M A D 12_0 P 0A /S IN 5_1/T IO A 7_1/IN T 12_1/P N L_P D 10/M A D 13_0 P 09/S C K 2_1/P N L_P D 11/M A D 14_0 P 08/S O T 2_1/P N L_P D 12/M A D 15_0 P 07/S IN 2_1/IN T 11_1/P N L_P D 13/M A D 16_0 P 06/P N L_P D 14/M A D 17_0 P 05/IN T 10_1/P N L_P D 15/M A D 18_0 P 04/T D O /S W O P 03/T M S /S W D IO P 02/T D I/M A D 24_0 P 01/T C K /S W C LK P 00/T R S T X VCC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 (TOP VIEW) VCC 1 90 VSS P 3B /T IO A 0_1/IN T 04_1/A IN 0_1/I2S M C LK 0_0/R T O 00_0/M A D 10_0 2 89 P 97/A N 23/P N L_P D 16/M C A S X _0 P 3C /S C S 70_0/T IO A 1_1/IN T 05_1/B IN 0_1/I2S D O 0_0/R T O 01_0/M A D 09_0 3 88 P 96/A N 22/P N L_T S IG 5/P N L_P D 17/M R A S X _0 P 3D /S IN 7_0/T IO A 2_1/IN T 06_1/Z IN 0_1/I2S W S 0_0/R T O 02_0/M A D 08_0 4 87 P 95/A N 21/S C K 1_1/P N L_T S IG 6/P N L_P D 18/M A D 19_0 P 3E /S O T 7_0/T IO A 3_1/IN T 07_1/I2S D I0_0/R T O 03_0/M A D 07_0 5 86 P 94/A N 20/S O T 1_1/T R A C E D 3/P N L_T S IG 7/P N L_P D 19/M A D 20_0 P 3F /S C K 7_0/T IO A 4_1/I2S C K 0_0/R T O 04_0/M A D 06_0 6 85 P 93/A N 19/S IN 1_1/T R A C E D 2/IN T 09_1/P N L_T S IG 8/P N L_P D 20/M N R E X _0/M A D 21_0 P 7C /T IO A 5_1/R T O 05_0/M W E X _0 7 84 P 92/A N 18/S C K 0_1/T R A C E D 1/P N L_T S IG 9/P N L_P D 21/M N W E X _0/M A D 22_0 P 7B /A D T G _2/M O E X _0/G E _H B C S X 1 8 83 P 91/A N 17/S O T 0_1/T R A C E D 0/P N L_T S IG 10/P N L_P D 22/M N C LE _0/M A D 23_0 P 33/S IN 6_0/IN T 00_1 9 82 P 90/A N 16/S IN 0_1/T R A C E C LK /IN T 08_1/P N L_T S IG 11/P N L_P D 23/M N A LE _0/M C LK O U T _0 P 34/S O T 6_0/F R C K 0_0 10 81 P 1F /A N 15/S C K 6_1/T IO B 7_0/M A D A T A 15_0 P 35/S C K 6_0/IC 03_0 11 80 P 1E /A N 14/S O T 6_1/T IO A 7_0/R T O 05_1/M A D A T A 14_0 P 36/S C S 60_0/IN T 01_1/IC 02_0 12 79 P 1D /A N 13/S IN 6_1/T IO B 6_0/IN T 15_0/R T O 04_1/M A D A T A 13_0 VCC 13 78 P 1C /A N 12/S C S 60_1/T IO A 6_0/IN T 14_0/R T O 03_1/M A D A T A 12_0 VSS 14 77 P 1B /A N 11/S C K 5_0/T IO B 5_0/Z IN 0_2/R T O 02_1/M A D A T A 11_0 P 37/IN T 02_1/G E _H B R E S E T X /IC 01_0 15 76 P 1A /A N 10/S O T 5_0/T IO A 5_0/B IN 0_2/R T O 01_1/M A D A T A 10_0 P 38/IN T 03_1/G E _H B IN T X /IC 00_0 16 75 P 19/A N 09/S IN 5_0/T IO B 4_0/IN T 13_0/A IN 0_2/R T O 00_1/M A D A T A 09_0 P 39/A D T G _0/G E _H B R S T O X /D T T I0X _0 17 74 P 18/A N 08/S C K 3_0/T IO A 4_0/IC 03_1/M A D A T A 08_0 P 3A /G E _H B W P X 18 73 P 17/A N 07/S O T 3_0/T IO B 3_0/IC 02_1/M A D A T A 07_0 P 7A /G E _H B R W D S 19 72 P 16/A N 06/S IN 3_0/T IO A 3_0/IN T 12_0/IC 01_1/M A D A T A 06_0 120pin P ackage 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 P 52/T IO B 1_1/P N L_D C LK P 53/T IO B 2_1/P N L_T S IG 2/P N L_D E N P 54/T IO B 3_1/P N L_T S IG 3/P N L_LE P 55/T IO B 4_1/P N L_T S IG 0/P N L_LH _S Y N C P 56/T IO B 5_1/P N L_T S IG 1/P N L_F V _S Y N C IN IT X P 46/X 0A P 47/X 1A V B A TV C C P 48/V R E G C T L P 49/V W A K E U P P E 0/M D 1 M D0 P E 2/X 0 P E 3/X 1 VSS VCC 43 61 P 50/W K U P 1/M C S X 0_0 30 P 51/T IO B 0_1/P N L_T S IG 4/P N L_P W E AVCC VCC 42 62 P 27/A D T G _1/C R O U T _1/M R D Y _0 29 41 AVSS P 79/IN T 07_0/G E _H B D Q 7 40 AVRL 63 VCC 64 28 P 26/R T C C O _1/S U B O U T _1/M A D 00_0 27 P 78/IN T 06_0/G E _H B D Q 6 39 AVRH P 77/IN T 05_0/G E _H B D Q 5 VSS 65 38 26 C P 10/A N 00/S IN 1_0/T IO A 0_0/IN T 09_0/A IN 0_0/M A D A T A 00_0 P 76/IN T 04_0/G E _H B D Q 4 P 25/I2S C K 1_0/M A D 01_0 66 37 25 36 P 11/A N 01/S O T 1_0/T IO B 0_0/B IN 0_0/M A D A T A 01_0 P 75/IN T 03_0/G E _S P D Q 2/G E _H B D Q 3 P 24/S C K 0_0/T IO B 6_1/I2S D I1_0/M A D 02_0 P 12/A N 02/S C K 1_0/T IO A 1_0/Z IN 0_0/M A D A T A 02_0 67 35 68 24 P 23/S O T 0_0/T IO A 6_1/I2S W S 1_0/M A D 03_0 23 P 74/IN T 02_0/G E _S P D Q 1/G E _H B D Q 2 34 P 13/A N 03/S IN 2_0/T IO B 1_0/IN T 10_0/F R C K 0_1/M A D A T A 03_0 P 73/IN T 01_0/G E _S P C S X 0/G E _H B D Q 1 33 69 P 21/I2S M C LK 1_0/M A D 05_0 22 P 22/S IN 0_0/IN T 08_0/I2S D O 1_0/C R O U T _0/M A D 04_0 P 14/A N 04/S O T 2_0/T IO A 2_0/D T T I0X _1/M A D A T A 04_0 P 72/IN T 00_0/G E _S P D Q 3/G E _H B D Q 0 32 P 15/A N 05/S C K 2_0/T IO B 2_0/IN T 11_0/IC 00_1/M A D A T A 05_0 70 31 71 21 VSS 20 P 20/N M IX /W K U P 0 P 70/G E _S P C K /G E _H B C K P 71/G E _S P D Q 0/G E _H B C S X 0 Note: • The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-03984 Rev. *D Page 9 of 182 S6E2D3 Series LQM120 (S6E2D35GJA) P 03/T M S /S W D IO P 02/T D I/M A D 24_0 P 01/T C K /S W C LK P 00/T R S T X VCC 95 94 93 92 91 P 06/P N L_P D 14/M A D 17_0 P 05/IN T 10_1/P N L_P D 15/M A D 18_0 P 04/T D O /S W O 98 97 99 96 P 09/S C K 2_1/P N L_P D 11/M A D 14_0 P 08/S O T 2_1/P N L_P D 12/M A D 15_0 P 07/S IN 2_1/IN T 11_1/P N L_P D 13/M A D 16_0 101 100 P 0B /S O T 5_1/T IO B 7_1/P N L_P D 9/M A D 12_0 P 0A /S IN 5_1/T IO A 7_1/IN T 12_1/P N L_P D 10/M A D 13_0 103 102 P 0E /W K U P 2/P N L_P D 6/M C S X 8_0 P 0D /P N L_P D 7/M S D W E X _0 P 0C /S C K 5_1/P N L_P D 8/M A D 11_0 106 105 104 P 67/S O T 3_1/P N L_P D 4/M S D C K E _0 P 68/S C K 3_1/P N L_P D 5/M S D C LK _0 VSS 109 108 107 P 64/C T S 4_0/P N L_P D 1 P 65/P N L_P D 2 P 66/S IN 3_1/IN T 13_1/P N L_P D 3 112 111 110 P 61/U H C O N X 0/S O T 4_0/R T C C O _0/S U B O U T _0/M D Q M 0_0 P 62/S C K 4_0/IN T 14_1/M D Q M 1_0 P 63/A D T G _3/R T S 4_0/P N L_P D 0 115 114 113 VCC P 60/S IN 4_0/IN T 15_1/W K U P 3/M A LE _0 117 116 VSS P 81/U D P 0 P 80/U D M 0 120 119 118 (TOP VIEW) VCC 1 90 VSS P 3B /T IO A 0_1/IN T 04_1/A IN 0_1/I2S M C LK 0_0/R T O 00_0/M A D 10_0 2 89 P 97/A N 23/P N L_P D 16/M C A S X _0 P 3C /S C S 70_0/T IO A 1_1/IN T 05_1/B IN 0_1/I2S D O 0_0/R T O 01_0/M A D 09_0 3 88 P 96/A N 22/P N L_T S IG 5/P N L_P D 17/M R A S X _0 P 3D /S IN 7_0/T IO A 2_1/IN T 06_1/Z IN 0_1/I2S W S 0_0/R T O 02_0/M A D 08_0 4 87 P 95/A N 21/S C K 1_1/P N L_T S IG 6/P N L_P D 18/M A D 19_0 P 3E /S O T 7_0/T IO A 3_1/IN T 07_1/I2S D I0_0/R T O 03_0/M A D 07_0 5 86 P 94/A N 20/S O T 1_1/T R A C E D 3/P N L_T S IG 7/P N L_P D 19/M A D 20_0 P 3F /S C K 7_0/T IO A 4_1/I2S C K 0_0/R T O 04_0/M A D 06_0 6 85 P 93/A N 19/S IN 1_1/T R A C E D 2/IN T 09_1/P N L_T S IG 8/P N L_P D 20/M N R E X _0/M A D 21_0 P 7C /T IO A 5_1/R T O 05_0/M W E X _0 7 84 P 92/A N 18/S C K 0_1/T R A C E D 1/P N L_T S IG 9/P N L_P D 21/M N W E X _0/M A D 22_0 P 7B /A D T G _2/M O E X _0 8 83 P 91/A N 17/S O T 0_1/T R A C E D 0/P N L_T S IG 10/P N L_P D 22/M N C LE _0/M A D 23_0 P 33/S IN 6_0/IN T 00_1 9 82 P 90/A N 16/S IN 0_1/T R A C E C LK /IN T 08_1/P N L_T S IG 11/P N L_P D 23/M N A LE _0/M C LK O U T _0 P 34/S O T 6_0/F R C K 0_0 10 81 P 1F /A N 15/S C K 6_1/T IO B 7_0/M A D A T A 15_0 P 35/S C K 6_0/IC 03_0 11 80 P 1E /A N 14/S O T 6_1/T IO A 7_0/R T O 05_1/M A D A T A 14_0 P 36/S C S 60_0/IN T 01_1/IC 02_0 12 79 P 1D /A N 13/S IN 6_1/T IO B 6_0/IN T 15_0/R T O 04_1/M A D A T A 13_0 VCC 13 78 P 1C /A N 12/S C S 60_1/T IO A 6_0/IN T 14_0/R T O 03_1/M A D A T A 12_0 VSS 14 77 P 1B /A N 11/S C K 5_0/T IO B 5_0/Z IN 0_2/R T O 02_1/M A D A T A 11_0 P 37/IN T 02_1/IC 01_0 15 76 P 1A /A N 10/S O T 5_0/T IO A 5_0/B IN 0_2/R T O 01_1/M A D A T A 10_0 120pin P ackage 56 57 58 59 60 P E 0/M D 1 M D0 P E 2/X 0 P E 3/X 1 VSS 53 54 55 V B A TV C C P 48/V R E G C T L P 49/V W A K E U P 50 51 52 IN IT X P 46/X 0A VSS P 47/X 1A VCC 48 61 49 30 P 54/T IO B 3_1/P N L_T S IG 3/P N L_LE AVCC VCC P 55/T IO B 4_1/P N L_T S IG 0/P N L_LH _S Y N C 62 P 56/T IO B 5_1/P N L_T S IG 1/P N L_F V _S Y N C 29 45 AVSS P 79/IN T 07_0 46 AVRL 63 47 64 28 P 52/T IO B 1_1/P N L_D C LK 27 P 78/IN T 06_0 P 53/T IO B 2_1/P N L_T S IG 2/P N L_D E N AVRH P 77/IN T 05_0 42 65 43 26 44 P 10/A N 00/S IN 1_0/T IO A 0_0/IN T 09_0/A IN 0_0/M A D A T A 00_0 (N .C .) P 50/W K U P 1/M C S X 0_0 66 P 27/A D T G _1/C R O U T _1/M R D Y _0 25 P 51/T IO B 0_1/P N L_T S IG 4/P N L_P W E P 11/A N 01/S O T 1_0/T IO B 0_0/B IN 0_0/M A D A T A 01_0 (N .C .) 39 P 12/A N 02/S C K 1_0/T IO A 1_0/Z IN 0_0/M A D A T A 02_0 67 40 68 24 41 23 (D N U 1)*1 VCC P 13/A N 03/S IN 2_0/T IO B 1_0/IN T 10_0/F R C K 0_1/M A D A T A 03_0 (D N U 0)*1 P 26/R T C C O _1/S U B O U T _1/M A D 00_0 69 36 22 37 P 14/A N 04/S O T 2_0/T IO A 2_0/D T T I0X _1/M A D A T A 04_0 VCC 38 P 15/A N 05/S C K 2_0/T IO B 2_0/IN T 11_0/IC 00_1/M A D A T A 05_0 70 C 71 21 P 25/I2S C K 1_0/M A D 01_0 20 (N .C .) P 24/S C K 0_0/T IO B 6_1/I2S D I1_0/M A D 02_0 P 16/A N 06/S IN 3_0/T IO A 3_0/IN T 12_0/IC 01_1/M A D A T A 06_0 (N .C .) 34 72 35 19 P 23/S O T 0_0/T IO A 6_1/I2S W S 1_0/M A D 03_0 P 17/A N 07/S O T 3_0/T IO B 3_0/IC 02_1/M A D A T A 07_0 (N .C .) P 22/S IN 0_0/IN T 08_0/I2S D O 1_0/C R O U T _0/M A D 04_0 73 31 18 32 P 18/A N 08/S C K 3_0/T IO A 4_0/IC 03_1/M A D A T A 08_0 P 3A 33 P 19/A N 09/S IN 5_0/T IO B 4_0/IN T 13_0/A IN 0_2/R T O 00_1/M A D A T A 09_0 74 VSS 75 17 P 20/N M IX /W K U P 0 16 P 21/I2S M C LK 1_0/M A D 05_0 P 38/IN T 03_1/IC 00_0 P 39/A D T G _0/D T T I0X _0 *1: The DNU0 / 1 (23 pin / 24 pin), please pull up and short-circuit on the board. For more information, please refer to the 7. Handling Devices. (N.C.): Do not connect anything. Note: • The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-03984 Rev. *D Page 10 of 182 S6E2D3 Series LQP176 P D 3/G E _S D A 2 P D 2/G E _S D A 3 P D 1/G E _S D A 4 P D 0/G E _S D A 5 VCC 137 136 135 134 133 P 01/T C K /S W C LK P 00/T R S T X P D 4/G E _S D A 1 140 139 138 P 04/T D O /S W O P 03/T M S /S W D IO P 02/T D I/M A D 24_0 143 142 141 P D 7/G E _S D D Q M 2 P D 6/G E _S D D Q M 3 P D 5/G E _S D A 0 146 145 144 P 05/IN T 10_1/P N L_P D 15/M A D 18_0 P D 9/G E _S D D Q M 0 P D 8/G E _S D D Q M 1 149 148 147 P 08/S O T 2_1/P N L_P D 12/M A D 15_0 P 07/S IN 2_1/IN T 11_1/P N L_P D 13/M A D 16_0 P 06/P N L_P D 14/M A D 17_0 152 151 150 P 0B /S O T 5_1/T IO B 7_1/P N L_P D 9/M A D 12_0 P 0A /S IN 5_1/T IO A 7_1/IN T 12_1/P N L_P D 10/M A D 13_0 P 09/S C K 2_1/P N L_P D 11/M A D 14_0 155 154 153 P 0E /W K U P 2/P N L_P D 6/M C S X 8_0 P 0D /P N L_P D 7/M S D W E X _0 P 0C /S C K 5_1/P N L_P D 8/M A D 11_0 158 157 156 P 67/S O T 3_1/P N L_P D 4/M S D C K E _0 P 68/S C K 3_1/P N L_P D 5/M S D C LK _0 VSS 161 160 159 P 64/C T S 4_0/P N L_P D 1 P 65/P N L_P D 2 P 66/S IN 3_1/IN T 13_1/P N L_P D 3 164 163 162 P D B /G E _S D R A S X P D A /G E _S D W E X P 63/A D T G _3/R T S 4_0/P N L_P D 0 167 166 165 P 62/S C K 4_0/IN T 14_1/M D Q M 1_0 P D D /G E _S D C S X P D C /G E _S D C A S X 170 169 168 VCC P 60/S IN 4_0/IN T 15_1/W K U P 3/M A LE _0 P 61/U H C O N X 0/S O T 4_0/R T C C O _0/S U B O U T _0/M D Q M 0_0 173 172 171 VSS P 81/U D P 0 P 80/U D M 0 176 175 174 (TOP VIEW) VCC 1 132 VSS P A 0/G E _S D C K E 2 131 P 97/A N 23/P N L_P D 16/M C A S X _0 P A 1/G E _S D C LK 3 130 P 96/A N 22/P N L_T S IG 5/P N L_P D 17/M R A S X _0 P A 2/G E _S D D Q 31 4 129 P C D /G E _S D A 6 P A 3/G E _S D D Q 30 5 128 P C C /G E _S D A 7 P 3B /T IO A 0_1/IN T 04_1/A IN 0_1/I2S M C LK 0_0/R T O 00_0/M A D 10_0 6 127 P C B /G E _S D A 8 P 3C /S C S 70_0/T IO A 1_1/IN T 05_1/B IN 0_1/I2S D O 0_0/R T O 01_0/M A D 09_0 7 126 P C A /G E _S D A 9 P 3D /S IN 7_0/T IO A 2_1/IN T 06_1/Z IN 0_1/I2S W S 0_0/R T O 02_0/M A D 08_0 8 125 P 95/A N 21/S C K 1_1/P N L_T S IG 6/P N L_P D 18/M A D 19_0 P 3E /S O T 7_0/T IO A 3_1/IN T 07_1/I2S D I0_0/R T O 03_0/M A D 07_0 9 124 P 94/A N 20/S O T 1_1/T R A C E D 3/P N L_T S IG 7/P N L_P D 19/M A D 20_0 P 3F /S C K 7_0/T IO A 4_1/I2S C K 0_0/R T O 04_0/M A D 06_0 10 123 P 93/A N 19/S IN 1_1/T R A C E D 2/IN T 09_1/P N L_T S IG 8/P N L_P D 20/M N R E X _0/M A D 21_0 P 7C /T IO A 5_1/R T O 05_0/M W E X _0 11 122 P 92/A N 18/S C K 0_1/T R A C E D 1/P N L_T S IG 9/P N L_P D 21/M N W E X _0/M A D 22_0 P 7B /A D T G _2/M O E X _0/G E _H B C S X 1 12 121 P 91/A N 17/S O T 0_1/T R A C E D 0/P N L_T S IG 10/P N L_P D 22/M N C LE _0/M A D 23_0 P A 8/G E _S D D Q 29 13 120 P 90/A N 16/S IN 0_1/T R A C E C LK /IN T 08_1/P N L_T S IG 11/P N L_P D 23/M N A LE _0/M C LK O U T _0 P A 9/G E _S D D Q 28 14 119 P 1F /A N 15/S C K 6_1/T IO B 7_0/M A D A T A 15_0 P A A /G E _S D D Q 27 15 118 P 1E /A N 14/S O T 6_1/T IO A 7_0/R T O 05_1/M A D A T A 14_0 P A B /G E _S D D Q 26 16 117 P 1D /A N 13/S IN 6_1/T IO B 6_0/IN T 15_0/R T O 04_1/M A D A T A 13_0 P A C /G E _S D D Q 25 17 116 P 1C /A N 12/S C S 60_1/T IO A 6_0/IN T 14_0/R T O 03_1/M A D A T A 12_0 P A D /G E _S D D Q 24 18 115 P C 9/G E _S D A 10 P 33/S IN 6_0/IN T 00_1 19 114 P C 8/G E _S D A 11 P 34/S O T 6_0/F R C K 0_0 20 113 P C 7/G E _S D B A 0 P 35/S C K 6_0/IC 03_0 21 112 P C 6/G E _S D B A 1 P 36/S C S 60_0/IN T 01_1/IC 02_0 22 111 P 1B /A N 11/S C K 5_0/T IO B 5_0/Z IN 0_2/R T O 02_1/M A D A T A 11_0 VCC 23 110 P 1A /A N 10/S O T 5_0/T IO A 5_0/B IN 0_2/R T O 01_1/M A D A T A 10_0 VSS 24 109 P 19/A N 09/S IN 5_0/T IO B 4_0/IN T 13_0/A IN 0_2/R T O 00_1/M A D A T A 09_0 P 37/IN T 02_1/G E _H B R E S E T X /IC 01_0 25 108 P 18/A N 08/S C K 3_0/T IO A 4_0/IC 03_1/M A D A T A 08_0 P 38/IN T 03_1/G E _H B IN T X /IC 00_0 26 107 P 17/A N 07/S O T 3_0/T IO B 3_0/IC 02_1/M A D A T A 07_0 P 39/A D T G _0/G E _H B R S T O X /D T T I0X _0 27 106 P 16/A N 06/S IN 3_0/T IO A 3_0/IN T 12_0/IC 01_1/M A D A T A 06_0 P 3A /G E _H B W P X 28 105 P 15/A N 05/S C K 2_0/T IO B 2_0/IN T 11_0/IC 00_1/M A D A T A 05_0 P A 4/G E _S D D Q 23 29 104 P 14/A N 04/S O T 2_0/T IO A 2_0/D T T I0X _1/M A D A T A 04_0 P A 5/G E _S D D Q 22 30 103 P 13/A N 03/S IN 2_0/T IO B 1_0/IN T 10_0/F R C K 0_1/M A D A T A 03_0 P A 6/G E _S D D Q 21 31 102 P 12/A N 02/S C K 1_0/T IO A 1_0/Z IN 0_0/M A D A T A 02_0 P A 7/G E _S D D Q 20 32 101 P 11/A N 01/S O T 1_0/T IO B 0_0/B IN 0_0/M A D A T A 01_0 P 7A /G E _H B R W D S 33 100 P 10/A N 00/S IN 1_0/T IO A 0_0/IN T 09_0/A IN 0_0/M A D A T A 00_0 P 70/G E _S P C K /G E _H B C K 34 99 P C 5/G E _S D D Q 0 P 71/G E _S P D Q 0/G E _H B C S X 0 35 98 P C 4/G E _S D D Q 1 P 72/IN T 00_0/G E _S P D Q 3/G E _H B D Q 0 36 97 P C 3/G E _S D D Q 2 P 73/IN T 01_0/G E _S P C S X 0/G E _H B D Q 1 37 96 P C 2/G E _S D D Q 3 P 74/IN T 02_0/G E _S P D Q 1/G E _H B D Q 2 38 95 P C 1/G E _S D D Q 4 P 75/IN T 03_0/G E _S P D Q 2/G E _H B D Q 3 39 94 P C 0/G E _S D D Q 5 P 76/IN T 04_0/G E _H B D Q 4 40 93 AVRH P 77/IN T 05_0/G E _H B D Q 5 41 92 AVRL P 78/IN T 06_0/G E _H B D Q 6 42 91 AVSS P 79/IN T 07_0/G E _H B D Q 7 43 90 AVCC VCC 44 89 VCC 84 85 86 87 88 P E 0/M D 1 M D0 P E 2/X 0 P E 3/X 1 VSS 81 82 83 V B A TV C C P 48/V R E G C T L P 49/V W A K E U P 78 79 80 IN IT X P 46/X 0A P 47/X 1A 75 76 77 P B B /G E _S D D Q 8 P B C /G E _S D D Q 7 P B A /G E _S D D Q 9 P B D /G E _S D D Q 6 72 73 74 P B 8/G E _S D D Q 11 P B 9/G E _S D D Q 10 69 70 71 P 54/T IO B 3_1/P N L_T S IG 3/P N L_LE P 55/T IO B 4_1/P N L_T S IG 0/P N L_LH _S Y N C P 56/T IO B 5_1/P N L_T S IG 1/P N L_F V _S Y N C 66 67 P 51/T IO B 0_1/P N L_T S IG 4/P N L_P W E 68 P 50/W K U P 1/M C S X 0_0 P 52/T IO B 1_1/P N L_D C LK P 27/A D T G _1/C R O U T _1/M R D Y _0 P 53/T IO B 2_1/P N L_T S IG 2/P N L_D E N 63 64 65 P 26/R T C C O _1/S U B O U T _1/M A D 00_0 60 61 62 C VSS VCC 57 58 59 P B 5/G E _S D D Q 14 P B 4/G E _S D D Q 15 P B 6/G E _S D D Q 13 P 25/I2S C K 1_0/M A D 01_0 P B 7/G E _S D D Q 12 54 55 56 P 24/S C K 0_0/T IO B 6_1/I2S D I1_0/M A D 02_0 51 52 53 P 21/I2S M C LK 1_0/M A D 05_0 P 23/S O T 0_0/T IO A 6_1/I2S W S 1_0/M A D 03_0 P 22/S IN 0_0/IN T 08_0/I2S D O 1_0/C R O U T _0/M A D 04_0 48 49 50 P B 1/G E _S D D Q 18 P B 2/G E _S D D Q 17 P B 0/G E _S D D Q 19 P B 3/G E _S D D Q 16 45 46 47 VSS P 20/N M IX /W K U P 0 176pin P ackage Note: • The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-03984 Rev. *D Page 11 of 182 S6E2D3 Series FDJ161 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 VCC VSS A VSS UDP0 UDM0 VCC VSS P66 VSS P0C P09 VSS TCK B VSS P60 P61 P62 P64 P67 P0E P0B P08 TDO TMS TRSTX VSS C VCC P3C P3B P63 P65 P68 P0D P0A P07 P05 TDI P96 P97 D P3F P3E P3D P7C VSS VSS VSS VSS P06 P92 P93 P94 P95 E P35 P34 P33 P7B VSS VSS VSS VSS VSS P1E P1F P90 P91 F P39 P38 P37 P36 VSS VSS VSS P1A P1B P1C P1D G VCC P7A P3A VSS VSS VSS P16 P17 P18 P19 H VSS P72 P73 VSS VSS VSS P12 P13 P14 P15 J P70 P74 P75 VSS VSS VSS VSS VSS VSS VSS P11 AVRH AVRL K P71 P76 P77 VSS P24 VSS P50 P52 P54 VSS P10 AVSS AVCC L VCC P78 P79 P22 P25 VSS P51 P53 P55 P56 P48 P49 VCC M VSS P20 P21 P23 P26 VSS VSS INITX VBAT VSS MD0 MD1 VSS N VSS C VSS VCC P27 VSS X0A VSS X0 X1 VSS X1A VSS Note: • The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-03984 Rev. *D Page 12 of 182 S6E2D3 Series 4. Pin Descriptions List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. LQFP176 LQFP120 Ex-LQFP120 1 1 2 - 3 - 4 - 5 - Pin No. LQFP120 (S6E2D35GJA) 1 - FBGA161 C1 - Pin name I/O circuit type Pin state type VCC - - K I K I L I L I G K G K G K PA0 GE_SDCKE - - PA1 GE_SDCLK - - PA2 GE_SDDQ31 - - PA3 GE_SDDQ30 P3B TIOA0_1 INT04_1 6 2 2 C3 AIN0_1 I2SMCLK0_0 RTO00_0 (PPG00_0) MAD10_0 P3C SCS70_0 TIOA1_1 INT05_1 7 3 3 C2 BIN0_1 I2SDO0_0 RTO01_0 (PPG00_0) MAD09_0 P3D SIN7_0 TIOA2_1 INT06_1 8 4 4 D3 ZIN0_1 I2SWS0_0 RTO02_0 (PPG02_0) MAD08_0 Document Number: 002-03984 Rev. *D Page 13 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type G K G I G I K I K I L I L I L I L I L I L I P3E SOT7_0 (SDA7_0) TIOA3_1 9 5 5 D2 INT07_1 I2SDI0_0 RTO03_0 (PPG02_0) MAD07_0 P3F SCK7_0 (SCL7_0) 10 6 6 D1 TIOA4_1 I2SCK0_0 RTO04_0 (PPG04_0) MAD06_0 P7C TIOA5_1 11 7 7 D4 RTO05_0 (PPG04_0) MWEX_0 P7B 12 8 - E4 ADTG_2 GE_HBCSX1 MOEX_0 P7B - - 8 - ADTG_2 MOEX_0 13 - 14 - 15 - 16 - 17 - 18 - - - PA8 GE_SDDQ29 - - PA9 GE_SDDQ28 - - PAA GE_SDDQ27 - - PAB GE_SDDQ26 - - PAC GE_SDDQ25 Document Number: 002-03984 Rev. *D - - PAD GE_SDDQ24 Page 14 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 19 9 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type D K D I D I D K P33 9 E3 SIN6_0 INT00_1 P34 20 10 10 E2 SOT6_0 (SDA6_0) FRCK0_0 P35 21 11 11 E1 SCK6_0 (SCL6_0) IC03_0 P36 22 12 12 F4 SCS60_0 INT01_1 IC02_0 23 13 13 G1 VCC - - 24 14 14 H1 VSS - - D K D K D K D K P37 25 15 - F3 GE_HBRESETX INT02_1 IC01_0 P37 - - 15 - INT02_1 IC01_0 P38 26 16 - F2 GE_HBINTX INT03_1 IC00_0 P38 - - 16 - INT03_1 IC00_0 Document Number: 002-03984 Rev. *D Page 15 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type E I E I E I E I L I L I L I L I K I - - K I - - K I - - K K - - K K - - K K P39 27 17 - F1 ADTG_0 GE_HBRSTOX DTTI0X_0 P39 - - 17 - ADTG_0 DTTI0X_0 28 18 - - - 18 - 29 - - - 30 - 31 - 32 - 33 19 - - - 19 G3 P3A GE_HBWPX P3A PA4 GE_SDDQ23 - - PA5 GE_SDDQ22 - - PA6 GE_SDDQ21 - - PA7 GE_SDDQ20 G2 - P7A GE_HBRWDS (N.C.) P70 34 20 - J1 GE_SPCK GE_HBCK - - 20 - (N.C.) P71 35 21 - K1 GE_SPDQ0 GE_HBCSX0 - - 21 - (N.C.) P72 36 22 - - - 22 H2 GE_SPDQ3 GE_HBDQ0 INT00_0 - VCC P73 37 23 - H3 GE_SPCSX0 GE_HBDQ1 INT01_0 - - 23 - (DNU0) P74 38 24 - J2 GE_SPDQ1 GE_HBDQ2 INT02_0 Document Number: 002-03984 Rev. *D Page 16 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 - - Pin No. LQFP120 (S6E2D35GJA) 24 FBGA161 - Pin name I/O circuit type Pin state type (DNU1) - - K K - - K K - - K K K K K K K K K K K K P75 GE_SPDQ2 39 25 - - - 25 - (N.C.) 40 26 - K2 GE_HBDQ4 - - 26 - (N.C.) 41 27 - K3 GE_HBDQ5 J3 GE_HBDQ3 INT03_0 P76 INT04_0 P77 INT05_0 - - 27 - P77 INT05_0 P78 42 28 - L2 GE_HBDQ6 INT06_0 - - 28 - - L3 P78 INT06_0 P79 43 29 GE_HBDQ7 INT07_0 - - 29 - P79 INT07_0 44 30 30 L1 VCC - - 45 31 31 M1 VSS - - I F L I L I L I L I P20 46 32 32 M2 NMIX WKUP0 47 - 48 - 49 - 50 - - - PB0 GE_SDDQ19 - - PB1 GE_SDDQ18 - - PB2 GE_SDDQ17 Document Number: 002-03984 Rev. *D - - PB3 GE_SDDQ16 Page 17 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 51 33 Pin No. LQFP120 (S6E2D35GJA) FBGA161 I/O circuit type Pin state type E I E K E I E I E I L I L I L I L I C - - Pin name P21 33 M3 I2SMCLK1_0 MAD05_0 P22 CROUT_0 52 34 34 L4 SIN0_0 INT08_0 I2SDO1_0 MAD04_0 P23 SOT0_0 (SDA0_0) 53 35 35 M4 TIOA6_1 I2SWS1_0 MAD03_0 P24 SCK0_0 (SCL0_0) 54 36 36 K5 TIOB6_1 I2SDI1_0 MAD02_0 P25 55 37 37 L5 I2SCK1_0 MAD01_0 - - PB4 56 - 57 - 58 - 59 - 60 38 38 N2 61 39 39 N3 VSS - - 62 40 40 N4 VCC - - E I E I GE_SDDQ15 - - PB5 GE_SDDQ14 - - PB6 GE_SDDQ13 - - PB7 GE_SDDQ12 P26 63 41 41 M5 RTCCO_1 SUBOUT_1 MAD00_0 P27 64 42 42 N5 ADTG_1 CROUT_1 MRDY_0 Document Number: 002-03984 Rev. *D Page 18 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 65 43 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type D P E I D I E I E I E I E I L I L I L I L I L I L I B C P S Q T P50 43 K7 WKUP1 MCSX0_0 P51 66 44 44 L7 TIOB0_1 PNL_PWE PNL_TSIG4 P52 67 45 45 K8 TIOB1_1 PNL_DCLK P53 68 46 46 L8 TIOB2_1 PNL_DEN PNL_TSIG2 P54 69 47 47 K9 TIOB3_1 PNL_LE PNL_TSIG3 P55 70 48 48 L9 TIOB4_1 PNL_LH_SYNC PNL_TSIG0 P56 71 49 49 L10 TIOB5_1 PNL_FV_SYNC PNL_TSIG1 72 - 73 - 74 - 75 - 76 - 77 - 78 50 - - PB8 GE_SDDQ11 - - PB9 GE_SDDQ10 - - PBA GE_SDDQ9 - - PBB GE_SDDQ8 - - PBC GE_SDDQ7 - - PBD GE_SDDQ6 50 M8 79 51 51 N7 80 52 52 N9 Document Number: 002-03984 Rev. *D INITX P46 X0A P47 X1A Page 19 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 81 53 Pin No. LQFP120 (S6E2D35GJA) 53 FBGA161 M9 Pin name I/O circuit type Pin state type VBAT - - O U O U C E J D A A A B P48 82 54 54 L11 83 55 55 L12 84 56 56 M12 85 57 57 M11 86 58 58 N11 87 59 59 N12 88 60 60 M13 VSS - - 89 61 61 L13 VCC - - 90 62 62 K13 AVCC - - 91 63 63 K12 AVSS - - 92 64 64 J13 AVRL - - 93 65 65 J12 AVRH - - 94 - - - L I 95 - L I 96 - L I 97 - L I 98 - L I 99 - L I F M VREGCTL P49 VWAKEUP PE0 MD1 MD0 PE2 X0 PE3 X1 PC0 GE_SDDQ5 - - PC1 GE_SDDQ4 - - PC2 GE_SDDQ3 - - PC3 GE_SDDQ2 - - PC4 GE_SDDQ1 - - PC5 GE_SDDQ0 P10 AN00 SIN1_0 100 66 66 K11 TIOA0_0 INT09_0 AIN0_0 MADATA00_0 Document Number: 002-03984 Rev. *D Page 20 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type F L F L F M F L F M F M P11 AN01 SOT1_0 101 67 67 J11 (SDA1_0) TIOB0_0 BIN0_0 MADATA01_0 P12 AN02 SCK1_0 102 68 68 H10 (SCL1_0) TIOA1_0 ZIN0_0 MADATA02_0 P13 AN03 SIN2_0 103 69 69 H11 TIOB1_0 INT10_0 FRCK0_1 MADATA03_0 P14 AN04 SOT2_0 104 70 70 H12 (SDA2_0) TIOA2_0 DTTI0X_1 MADATA04_0 P15 AN05 SCK2_0 (SCL2_0) 105 71 71 H13 TIOB2_0 INT11_0 IC00_1 MADATA05_0 P16 AN06 SIN3_0 106 72 72 G10 TIOA3_0 INT12_0 IC01_1 MADATA06_0 Document Number: 002-03984 Rev. *D Page 21 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type F L F L F M F L F L K I P17 AN07 SOT3_0 107 73 73 G11 (SDA3_0) TIOB3_0 IC02_1 MADATA07_0 P18 AN08 SCK3_0 108 74 74 G12 (SCL3_0) TIOA4_0 IC03_1 MADATA08_0 P19 AN09 SIN5_0 TIOB4_0 109 75 75 G13 INT13_0 AIN0_2 RTO00_1 (PPG00_1) MADATA09_0 P1A AN10 SOT5_0 (SDA5_0) 110 76 76 F10 TIOA5_0 BIN0_2 RTO01_1 (PPG00_1) MADATA10_0 P1B AN11 SCK5_0 (SCL5_0) 111 77 77 F11 TIOB5_0 ZIN0_2 RTO02_1 (PPG02_1) MADATA11_0 112 - Document Number: 002-03984 Rev. *D - - PC6 GE_SDBA1 Page 22 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 113 - 114 - 115 - Pin No. LQFP120 (S6E2D35GJA) - FBGA161 - Pin name PC7 GE_SDBA0 - - PC8 GE_SDA11 - - PC9 GE_SDA10 I/O circuit type Pin state type K I K I K I F M F M F L F L P1C AN12 SCS60_1 116 78 78 F12 TIOA6_0 INT14_0 RTO03_1 (PPG02_1) MADATA12_0 P1D AN13 SIN6_1 117 79 79 F13 TIOB6_0 INT15_0 RTO04_1 (PPG04_1) MADATA13_0 P1E AN14 SOT6_1 118 80 80 E10 (SDA6_1) TIOA7_0 RTO05_1 (PPG04_1) MADATA14_0 P1F AN15 119 81 81 E11 SCK6_1 (SCL6_1) TIOB7_0 MADATA15_0 Document Number: 002-03984 Rev. *D Page 23 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type F O F N F N F O F N P90 AN16 SIN0_1 INT08_1 120 82 82 E12 PNL_PD23 PNL_TSIG11 MCLKOUT_0 MNALE_0 TRACECLK P91 AN17 SOT0_1 (SDA0_1) 121 83 83 E13 PNL_PD22 PNL_TSIG10 MAD23_0 MNCLE_0 TRACED0 P92 AN18 SCK0_1 (SCL0_1) 122 84 84 D10 PNL_PD21 PNL_TSIG9 MAD22_0 MNWEX_0 TRACED1 P93 AN19 SIN1_1 INT09_1 123 85 85 D11 PNL_PD20 PNL_TSIG8 MAD21_0 MNREX_0 TRACED2 P94 AN20 SOT1_1 (SDA1_1) 124 86 86 D12 PNL_PD19 PNL_TSIG7 MAD20_0 TRACED3 Document Number: 002-03984 Rev. *D Page 24 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type F L K I K I K I K I F L F L P95 AN21 SCK1_1 125 87 87 D13 (SCL1_1) PNL_PD18 PNL_TSIG6 MAD19_0 126 - 127 - 128 - 129 - - - PCA GE_SDA9 - - PCB GE_SDA8 - - PCC GE_SDA7 - - PCD GE_SDA6 P96 AN22 130 88 88 C12 PNL_PD17 PNL_TSIG5 MRASX_0 P97 131 89 89 C13 AN23 PNL_PD16 MCASX_0 132 90 90 B13 VSS - - 133 91 91 A12 VCC - - 134 - - - K I 135 - K I 136 - K I 137 - K I 138 - K I 139 92 92 B12 E G 140 93 93 A11 E G PD0 GE_SDA5 - - PD1 GE_SDA4 - - PD2 GE_SDA3 - - PD3 GE_SDA2 - - PD4 GE_SDA1 P00 TRSTX P01 TCK SWCLK Document Number: 002-03984 Rev. *D Page 25 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 141 94 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type E H E G E G K I K I K I K I K I E K E I E K E I E I P02 94 C11 TDI MAD24_0 P03 142 95 95 B11 TMS SWDIO P04 143 96 96 B10 TDO SWO 144 - 145 - 146 - 147 - 148 - - - PD5 GE_SDA0 - - PD6 GE_SDDQM3 - - PD7 GE_SDDQM2 - - PD8 GE_SDDQM1 - - PD9 GE_SDDQM0 P05 149 97 97 C10 INT10_1 PNL_PD15 MAD18_0 P06 150 98 98 D9 PNL_PD14 MAD17_0 P07 SIN2_1 151 99 99 C9 INT11_1 PNL_PD13 MAD16_0 P08 SOT2_1 152 100 100 B9 (SDA2_1) PNL_PD12 MAD15_0 P09 SCK2_1 153 101 101 A9 (SCL2_1) PNL_PD11 MAD14_0 Document Number: 002-03984 Rev. *D Page 26 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type E K E I E I D I D P - - D I D I E K E I E I P0A SIN5_1 154 102 102 C8 TIOA7_1 INT12_1 PNL_PD10 MAD13_0 P0B SOT5_1 (SDA5_1) 155 103 103 B8 TIOB7_1 PNL_PD9 MAD12_0 P0C SCK5_1 156 104 104 A8 (SCL5_1) PNL_PD8 MAD11_0 P0D 157 105 105 C7 PNL_PD7 MSDWEX_0 P0E 158 106 106 B7 159 107 107 A7 WKUP2 PNL_PD6 MCSX8_0 VSS P68 SCK3_1 160 108 108 C6 (SCL3_1) PNL_PD5 MSDCLK_0 P67 SOT3_1 161 109 109 B6 (SDA3_1) PNL_PD4 MSDCKE_0 P66 162 110 110 A6 SIN3_1 INT13_1 PNL_PD3 163 111 111 C5 P65 PNL_PD2 P64 164 112 112 B5 CTS4_0 PNL_PD1 Document Number: 002-03984 Rev. *D Page 27 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type E I K I K I K I K I N K N I I Q - - H R H R - - P63 165 113 113 C4 ADTG_3 RTS4_0 PNL_PD0 166 - 167 - 168 - 169 - - - PDA GE_SDWEX - - PDB GE_SDRASX - - PDC GE_SDCASX - - PDD GE_SDCSX P62 SCK4_0 170 114 114 B4 (SCL4_0) INT14_1 MDQM1_0 P61 UHCONX0 RTCCO_0 171 115 115 B3 SUBOUT_0 SOT4_0 (SDA4_0) MDQM0_0 P60 WKUP3 172 116 116 B2 SIN4_0 INT15_1 MALE_0 173 117 117 A4 174 118 118 A3 175 119 119 A2 176 120 120 B1 Document Number: 002-03984 Rev. *D VCC P80 UDM0 P81 UDP0 VSS Page 28 of 182 S6E2D3 Series LQFP176 LQFP120 Ex-LQFP120 Pin No. LQFP120 (S6E2D35GJA) FBGA161 Pin name I/O circuit type Pin state type VSS - - A1, A5, A10, A13, D5, D6, D7, D8, E5, E6, E7, E8, E9, F5, F6, F9, G4, G5, - - - G9, H4, H5, H9, J4, J5, J6, J7, J8, J9, J10, K4, K6, K10, L6, M6, M7, M10, N1, N6, N8, N10, N13 Document Number: 002-03984 Rev. *D Page 29 of 182 S6E2D3 Series Signal Description The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Base Timer 1 Document Number: 002-03984 Rev. *D A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base Timer ch.0 TIOA Pin Base Timer ch.0 TIOB Pin Base Timer ch.1 TIOA Pin Base Timer ch.1 TIOB Pin FBGA161 Base Timer 0 ADTG_0 ADTG_1 ADTG_2 ADTG_3 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 TIOA0_0 TIOA0_1 TIOB0_0 TIOB0_1 TIOA1_0 TIOA1_1 TIOB1_0 TIOB1_1 Function LQFP120 (S6E2D35GJ A) ADC Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 27 64 12 165 100 101 102 103 104 105 106 107 108 109 110 111 116 117 118 119 120 121 122 123 124 125 130 131 100 6 101 66 102 7 103 67 17 42 8 113 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 66 2 67 44 68 3 69 45 17 42 8 113 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 66 2 67 44 68 3 69 45 F1 N5 E4 C4 K11 J11 H10 H11 H12 H13 G10 G11 G12 G13 F10 F11 F12 F13 E10 E11 E12 E13 D10 D11 D12 D13 C12 C13 K11 C3 J11 L7 H10 C2 H11 K8 Page 30 of 182 S6E2D3 Series Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Debugger Document Number: 002-03984 Rev. *D Base Timer ch.2 TIOA Pin Base Timer ch.2 TIOB Pin Base Timer ch.3 TIOA Pin Base Timer ch.3 TIOB Pin Base Timer ch.4 TIOA Pin Base Timer ch.4 TIOB Pin Base Timer ch.5 TIOA Pin Base Timer ch.5 TIOB Pin Base Timer ch.6 TIOA Pin Base Timer ch.6 TIOB Pin Base Timer ch.7 TIOA Pin Base Timer ch.7 TIOB Pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state output pin Trace CLK output pin of ETM Trace data output pin of ETM JTAG test reset Input pin FBGA161 Base Timer 3 TIOA2_0 TIOA2_1 TIOB2_0 TIOB2_1 TIOA3_0 TIOA3_1 TIOB3_0 TIOB3_1 TIOA4_0 TIOA4_1 TIOB4_0 TIOB4_1 TIOA5_0 TIOA5_1 TIOB5_0 TIOB5_1 TIOA6_0 TIOA6_1 TIOB6_0 TIOB6_1 TIOA7_0 TIOA7_1 TIOB7_0 TIOB7_1 SWCLK SWDIO SWO TCK TDI TDO TMS TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRSTX Function LQFP120 (S6E2D35GJ A) Base Timer 2 Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 104 8 105 68 106 9 107 69 108 10 109 70 110 11 111 71 116 53 117 54 118 154 119 155 140 142 143 140 141 143 142 120 121 122 123 124 139 70 4 71 46 72 5 73 47 74 6 75 48 76 7 77 49 78 35 79 36 80 102 81 103 93 95 96 93 94 96 95 82 83 84 85 86 92 70 4 71 46 72 5 73 47 74 6 75 48 76 7 77 49 78 35 79 36 80 102 81 103 93 95 96 93 94 96 95 82 83 84 85 86 92 H12 D3 H13 L8 G10 D2 G11 K9 G12 D1 G13 L9 F10 D4 F11 L10 F12 M4 F13 K5 E10 C8 E11 B8 A11 B11 B10 A11 C11 B10 B11 E12 E13 D10 D11 D12 B12 Page 31 of 182 S6E2D3 Series Document Number: 002-03984 Rev. *D External bus interface address bus External bus interface chip select output pin External bus interface data bus FBGA161 External Bus MAD00_0 MAD01_0 MAD02_0 MAD03_0 MAD04_0 MAD05_0 MAD06_0 MAD07_0 MAD08_0 MAD09_0 MAD10_0 MAD11_0 MAD12_0 MAD13_0 MAD14_0 MAD15_0 MAD16_0 MAD17_0 MAD18_0 MAD19_0 MAD20_0 MAD21_0 MAD22_0 MAD23_0 MAD24_0 MCSX0_0 MCSX8_0 MADATA00_0 MADATA01_0 MADATA02_0 MADATA03_0 MADATA04_0 MADATA05_0 MADATA06_0 MADATA07_0 MADATA08_0 MADATA09_0 MADATA10_0 MADATA11_0 MADATA12_0 MADATA13_0 MADATA14_0 MADATA15_0 Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 63 55 54 53 52 51 10 9 8 7 6 156 155 154 153 152 151 150 149 125 124 123 122 121 141 65 158 100 101 102 103 104 105 106 107 108 109 110 111 116 117 118 119 41 37 36 35 34 33 6 5 4 3 2 104 103 102 101 100 99 98 97 87 86 85 84 83 94 43 106 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 41 37 36 35 34 33 6 5 4 3 2 104 103 102 101 100 99 98 97 87 86 85 84 83 94 43 106 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 M5 L5 K5 M4 L4 M3 D1 D2 D3 C2 C3 A8 B8 C8 A9 B9 C9 D9 C10 D13 D12 D11 D10 E13 C11 K7 B7 K11 J11 H10 H11 H12 H13 G10 G11 G12 G13 F10 F11 F12 F13 E10 E11 Page 32 of 182 S6E2D3 Series MALE_0 MRDY_0 MCLKOUT_0 MNALE_0 External Bus External bus interface Address Latch enable output signal for multiplex External bus interface external RDY input signal External bus interface external clock output pin External bus interface ALE signal to control NAND Flash output pin 171 170 115 114 115 114 B3 B4 172 116 116 B2 64 120 42 82 42 82 N5 E12 120 82 82 E12 MNCLE_0 External bus interface CLE signal to control NAND Flash output pin 121 83 83 E13 MNREX_0 External bus interface read enable signal to control NAND Flash output pin 123 85 85 D11 MNWEX_0 External bus interface write enable signal to control NAND Flash output pin 122 84 84 D10 External bus interface read enable signal for SRAM 12 8 8 E4 11 7 7 D4 160 161 130 131 157 36 19 37 22 38 25 39 26 40 6 41 7 42 8 43 9 52 120 100 123 108 109 88 89 105 22 9 23 12 24 15 25 16 26 2 27 3 28 4 29 5 34 82 66 85 108 109 88 89 105 9 12 15 16 2 27 3 28 4 29 5 34 82 66 85 C6 B6 C12 C13 C7 H2 E3 H3 F4 J2 F3 J3 F2 K2 C3 K3 C2 L2 D3 L3 D2 L4 E12 K11 D11 MOEX_0 MWEX_0 External Interrupt External bus interface byte mask signal output pin FBGA161 MDQM0_0 MDQM1_0 Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. MSDCLK_0 MSDCKE_0 MRASX_0 MCASX_0 MSDWEX_0 INT00_0 INT00_1 INT01_0 INT01_1 INT02_0 INT02_1 INT03_0 INT03_1 INT04_0 INT04_1 INT05_0 INT05_1 INT06_0 INT06_1 INT07_0 INT07_1 INT08_0 INT08_1 INT09_0 INT09_1 Document Number: 002-03984 Rev. *D External bus interface write enable signal for SRAM SDRAM interface SDRAM clock output pin SDRAM interface SDRAM clock enable pin SDRAM interface SDRAM row active strobe pin SDRAM interface SDRAM column active strobe pin SDRAM interface SDRAM write enable pin External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin Page 33 of 182 S6E2D3 Series Document Number: 002-03984 Rev. *D External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin General-purpose I/O port 0 General-purpose I/O port 1 FBGA161 GPIO INT10_0 INT10_1 INT11_0 INT11_1 INT12_0 INT12_1 INT13_0 INT13_1 INT14_0 INT14_1 INT15_0 INT15_1 NMIX P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F Function LQFP120 (S6E2D35GJ A) External Interrupt Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 103 149 105 151 106 154 109 162 116 170 117 172 46 139 140 141 142 143 149 150 151 152 153 154 155 156 157 158 100 101 102 103 104 105 106 107 108 109 110 111 116 117 118 119 69 97 71 99 72 102 75 110 78 114 79 116 32 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 69 97 71 99 72 102 75 110 78 114 79 116 32 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 H11 C10 H13 C9 G10 C8 G13 A6 F12 B4 F13 B2 M2 B12 A11 C11 B11 B10 C10 D9 C9 B9 A9 C8 B8 A8 C7 B7 K11 J11 H10 H11 H12 H13 G10 G11 G12 G13 F10 F11 F12 F13 E10 E11 Page 34 of 182 S6E2D3 Series Document Number: 002-03984 Rev. *D General-purpose I/O port 2 General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 FBGA161 GPIO P20 P21 P22 P23 P24 P25 P26 P27 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66 P67 P68 Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 46 51 52 53 54 55 63 64 19 20 21 22 25 26 27 28 6 7 8 9 10 79 80 82 83 65 66 67 68 69 70 71 172 171 170 165 164 163 162 161 160 32 33 34 35 36 37 41 42 9 10 11 12 15 16 17 18 2 3 4 5 6 51 52 54 55 43 44 45 46 47 48 49 116 115 114 113 112 111 110 109 108 32 33 34 35 36 37 41 42 9 10 11 12 15 16 17 18 2 3 4 5 6 51 52 54 55 43 44 45 46 47 48 49 116 115 114 113 112 111 110 109 108 M2 M3 L4 M4 K5 L5 M5 N5 E3 E2 E1 F4 F3 F2 F1 G3 C3 C2 D3 D2 D1 N7 N9 L11 L12 K7 L7 K8 L8 K9 L9 L10 B2 B3 B4 C4 B5 C5 A6 B6 C6 Page 35 of 182 S6E2D3 Series Document Number: 002-03984 Rev. *D General-purpose I/O port 7 General-purpose I/O port 8 General-purpose I/O port 9 General-purpose I/O port A FBGA161 GPIO P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P7A P7B P7C P80 P81 P90 P91 P92 P93 P94 P95 P96 P97 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PAA PAB PAC PAD Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 34 35 36 37 38 39 40 41 42 43 33 12 11 174 175 120 121 122 123 124 125 130 131 2 3 4 5 29 30 31 32 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 19 8 7 118 119 82 83 84 85 86 87 88 89 - - - - - - - - - - - - - - - - - - - - - 27 28 29 - 8 7 118 119 82 83 84 85 86 87 88 89 - - - - - - - - - - - - - - J1 K1 H2 H3 J2 J3 K2 K3 L2 L3 G2 E4 D4 A3 A2 E12 E13 D10 D11 D12 D13 C12 C13 - - - - - - - - - - - - - - Page 36 of 182 S6E2D3 Series Document Number: 002-03984 Rev. *D General-purpose I/O port B General-purpose I/O port C General-purpose I/O port D FBGA161 GPIO PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PBA PBB PBC PBD PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PCA PCB PCC PCD PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PDA PDB PDC PDD Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 47 48 49 50 56 57 58 59 72 73 74 75 76 77 94 95 96 97 98 99 112 113 114 115 126 127 128 129 134 135 136 137 138 144 145 146 147 148 166 167 168 169 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Page 37 of 182 S6E2D3 Series SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 Multifunction serial 1 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) SIN2_0 SIN2_1 Multifunction serial 2 SOT2_0 (SDA2_0) SOT2_1 (SDA2_1) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) SIN3_0 SIN3_1 Multifunction serial 3 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) Document Number: 002-03984 Rev. *D FBGA161 Multifunction serial 0 PE0 PE2 PE3 SIN0_0 SIN0_1 LQFP120 (S6E2D35GJ A) GPIO Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 84 86 87 52 120 56 58 59 34 82 56 58 59 34 82 M12 N11 N12 L4 E12 53 35 35 M4 121 83 83 E13 54 36 36 K5 122 84 84 D10 100 123 66 85 66 85 K11 D11 Multi-function serial interface ch.1 output pin This pin operates as SOT1 when it is used in a UART/CSIO/LIN(operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 101 67 67 J11 124 86 86 D12 Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4). 102 68 68 H10 125 87 87 D13 103 151 69 99 69 99 H11 C9 Multi-function serial interface ch.2 output pin This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation mode 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). 104 70 70 H12 152 100 100 B9 Multi-function serial interface ch.2 clock I/O Pin. This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and as SCL2 when it is used in an I2C (operation mode 4). 105 71 71 H13 153 101 101 A9 106 162 72 110 72 110 G10 A6 Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). 107 73 73 G11 161 109 109 B6 Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation mode 2) and as SCL3 when it is used in an I2C (operation mode 4). 108 74 74 G12 160 108 108 C6 Function General-purpose I/O port E Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4) Multi-function serial interface ch.1 input pin Multi-function serial interface ch.2 input pin Multi-function serial interface ch.3 input pin Page 38 of 182 S6E2D3 Series LQFP120 Ex-LQFP120 LQFP120 (S6E2D35GJ A) FBGA161 Module LQFP176 Pin No. Multi-function serial interface ch.4 input pin 172 116 116 B2 SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). 171 115 115 B3 SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation mode 2) and as SCL4 when it is used in an I2C (operation mode 4). 170 114 114 B4 164 165 109 154 112 113 75 102 112 113 75 102 B5 C4 G13 C8 110 76 76 F10 155 103 103 B8 111 77 77 F11 156 104 104 A8 19 117 9 79 9 79 E3 F13 20 10 10 E2 118 80 80 E10 Pin Name SIN4_0 Multifunction serial 4 Multifunction serial 5 CTS4_0 RTS4_0 SIN5_0 SIN5_1 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SIN6_0 SIN6_1 SOT6_0 (SDA6_0) Multifunction serial 6 SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) SCS60_0 SCS60_1 Document Number: 002-03984 Rev. *D Function Multi-function serial interface ch.4 CTS input pin Multi-function serial interface ch.4 RTS output pin Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation mode 2) and as SCL6 when it is used in an I2C (operation mode 4). 21 11 11 E1 119 81 81 E11 Multi-function serial interface ch.6 chip select 0 input/output pin 22 116 12 78 12 78 F4 F12 Page 39 of 182 S6E2D3 Series LQFP120 Ex-LQFP120 LQFP120 (S6E2D35GJ A) FBGA161 Module LQFP176 Pin No. Multi-function serial interface ch.7 input pin 8 4 4 D3 SOT7_0 (SDA7_0) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). 9 5 5 D2 SCK7_0 (SCL7_0) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation mode 2) and as SCL7 when it is used in an I2C (operation mode 4). 10 6 6 D1 SCS70_0 Multi-function serial interface ch.7 chip select 0 input/output pin 7 3 3 C2 27 104 20 103 26 105 25 106 22 107 21 108 17 70 10 69 16 71 15 72 12 73 11 74 17 70 10 69 16 71 15 72 12 73 11 74 F1 H12 E2 H11 F2 H13 F3 G10 F4 G11 E1 G12 6 2 2 C3 109 75 75 G13 7 3 3 C2 110 76 76 F10 8 4 4 D3 111 77 77 F11 9 5 5 D2 116 78 78 F12 Pin Name SIN7_0 Multifunction serial 7 Multi-function Timer 0 DTTI0X_0 DTTI0X_1 FRCK0_0 FRCK0_1 IC00_0 IC00_1 IC01_0 IC01_1 IC02_0 IC02_1 IC03_0 IC03_1 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) Document Number: 002-03984 Rev. *D Function Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 16-bit input capture input pin of Multi-function timer 0. ICxx describes channel number. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Page 40 of 182 S6E2D3 Series Multi-function Timer 0 Quadrature Position/ Revolution Counter 0 Real-time clock USB0 Low-Power Consumption Mode VBAT RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 RTCCO_0 RTCCO_1 SUBOUT_0 SUBOUT_1 UDM0 UDP0 UHCONX0 WKUP0 WKUP1 WKUP2 WKUP3 VREGCTL VWAKEUP Document Number: 002-03984 Rev. *D Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin 0.5 seconds pulse output pin of Real-time clock Sub clock output pin USB ch.0 device/host D – pin USB ch.0 device/host D + pin USB ch.0 external pull-up control pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 On-board regulator control pin The return signal input pin from a hibernation state FBGA161 RTO04_0 (PPG04_0) Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 10 6 6 D1 117 79 79 F13 11 7 7 D4 118 80 80 E10 100 6 109 101 7 110 102 8 111 171 66 2 75 67 3 76 68 4 77 115 66 2 75 67 3 76 68 4 77 115 K11 C3 G13 J11 C2 F10 H10 D3 F11 B3 63 41 41 M5 171 115 115 B3 63 174 175 171 46 65 158 172 82 83 41 118 119 115 32 43 106 116 54 55 41 118 119 115 32 43 106 116 54 55 M5 A3 A2 B3 M2 K7 B7 B2 L11 L12 Page 41 of 182 S6E2D3 Series GDC High-Speed Quad SPI GDC HyperBus I/F Document Number: 002-03984 Rev. *D I2S ch.0 external clock pin I2S ch.0 serial transition data output pin I2S ch.0 frame synchronization signal pin I2S ch.0 serial received data input pin I2S ch.0 bit clock pin I2S ch.1 external clock pin I2S ch.1 serial transition data output pin I2S ch.1 frame synchronization signal pin I2S ch.1 serial received data input pin I2S ch.1 bit clock pin SPI clock output pin SPI data input / output pin SPI chip select output pin HBI clock output pin HBI data input / output pin HBI chip select output pin HBI RWDS input / output pin HBI hardware reset output pin HBI interrupt input pin HBI reset input pin HBI write protect output pin FBGA161 I2 S 1 I2SMCLK0_0 I2SDO0_0 I2SWS0_0 I2SDI0_0 I2SCK0_0 I2SMCLK1_0 I2SDO1_0 I2SWS1_0 I2SDI1_0 I2SCK1_0 GE_SPCK GE_SPDQ0 GE_SPDQ1 GE_SPDQ2 GE_SPDQ3 GE_SPCSX0 GE_HBCK GE_HBDQ0 GE_HBDQ1 GE_HBDQ2 GE_HBDQ3 GE_HBDQ4 GE_HBDQ5 GE_HBDQ6 GE_HBDQ7 GE_HBCSX0 GE_HBCSX1 GE_HBRWDS GE_HBRESETX GE_HBINTX GE_HBRSTOX GE_HBWPX Function LQFP120 (S6E2D35GJ A) I2 S 0 Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 6 7 8 9 10 51 52 53 54 55 34 35 38 39 36 37 34 36 37 38 39 40 41 42 43 35 12 33 25 26 27 28 2 3 4 5 6 33 34 35 36 37 20 21 24 25 22 23 20 22 23 24 25 26 27 28 29 21 8 19 15 16 17 18 2 3 4 5 6 33 34 35 36 37 - C3 C2 D3 D2 D1 M3 L4 M4 K5 L5 J1 K1 J2 J3 H2 H3 J1 H2 H3 J2 J3 K2 K3 L2 L3 K1 E4 G2 F3 F2 F1 G3 Page 42 of 182 S6E2D3 Series Document Number: 002-03984 Rev. *D GDC clock output pin GDC data enable output pin (blanking signal) GDC power enable control output pin GDC line end output pin GDC horizontal synchronization output pin GDC vertical synchronization output pin GDC panel data output pin GDC timing generator for panel control PNL_TSIG signals are customized synchronization signals for direct interfacing to the column and row drivers of most panel types. For more information, refer to Peripheral Manual (GDC Core part). FBGA161 GDC Panel PNL_DCLK PNL_DEN PNL_PWE PNL_LE PNL_LH_SYNC PNL_FV_SYNC PNL_PD0 PNL_PD1 PNL_PD2 PNL_PD3 PNL_PD4 PNL_PD5 PNL_PD6 PNL_PD7 PNL_PD8 PNL_PD9 PNL_PD10 PNL_PD11 PNL_PD12 PNL_PD13 PNL_PD14 PNL_PD15 PNL_PD16 PNL_PD17 PNL_PD18 PNL_PD19 PNL_PD20 PNL_PD21 PNL_PD22 PNL_PD23 PNL_TSIG0 PNL_TSIG1 PNL_TSIG2 PNL_TSIG3 PNL_TSIG4 PNL_TSIG5 PNL_TSIG6 PNL_TSIG7 PNL_TSIG8 PNL_TSIG9 PNL_TSIG10 PNL_TSIG11 Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 67 68 66 69 70 71 165 164 163 162 161 160 158 157 156 155 154 153 152 151 150 149 131 130 125 124 123 122 121 120 70 71 68 69 66 130 125 124 123 122 121 120 45 46 44 47 48 49 113 112 111 110 109 108 106 105 104 103 102 101 100 99 98 97 89 88 87 86 85 84 83 82 48 49 46 47 44 88 87 86 85 84 83 82 45 46 44 47 48 49 113 112 111 110 109 108 106 105 104 103 102 101 100 99 98 97 89 88 87 86 85 84 83 82 48 49 46 47 44 88 87 86 85 84 83 82 K8 L8 L7 K9 L9 L10 C4 B5 C5 A6 B6 C6 B7 C7 A8 B8 C8 A9 B9 C9 D9 C10 C13 C12 D13 D12 D11 D10 E13 E12 L9 L10 L8 K9 L7 C12 D13 D12 D11 D10 E13 E12 Page 43 of 182 S6E2D3 Series Document Number: 002-03984 Rev. *D SDRAM-IF address output pin SDRAM-IF bank address output pin SDRAM-IF column active output pin SDRAM-IF row active output pin SDRAM-IF write enable output pin SDRAM-IF clock enable output pin SDRAM-IF clock output pin SDRAM-IF chip select output pin SDRAM-IF data input / output pin FBGA161 GDC SDRAM-IF (176 pin only) GE_SDA0 GE_SDA1 GE_SDA2 GE_SDA3 GE_SDA4 GE_SDA5 GE_SDA6 GE_SDA7 GE_SDA8 GE_SDA9 GE_SDA10 GE_SDA11 GE_SDBA0 GE_SDBA1 GE_SDCASX GE_SDRASX GE_SDWEX GE_SDCKE GE_SDCLK GE_SDCSX GE_SDDQ0 GE_SDDQ1 GE_SDDQ2 GE_SDDQ3 GE_SDDQ4 GE_SDDQ5 GE_SDDQ6 GE_SDDQ7 GE_SDDQ8 GE_SDDQ9 GE_SDDQ10 GE_SDDQ11 GE_SDDQ12 GE_SDDQ13 GE_SDDQ14 GE_SDDQ15 GE_SDDQ16 GE_SDDQ17 GE_SDDQ18 GE_SDDQ19 GE_SDDQ20 GE_SDDQ21 GE_SDDQ22 GE_SDDQ23 Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 144 138 137 136 135 134 129 128 127 126 115 114 113 112 168 167 166 2 3 169 99 98 97 96 95 94 77 76 75 74 73 72 59 58 57 56 50 49 48 47 32 31 30 29 - - - Page 44 of 182 S6E2D3 Series Reset INITX MD1 Mode MD0 SDRAM-IF data input / output pin SDRAM-IF input / output mask pin External Reset Input pin. A reset is valid when INITX = L. Mode 1 pin. During serial programming to Flash memory, MD1 = L must be input. Mode 0 pin. During normal operation, MD0 = L must be input. During serial programming to Flash memory, MD0 = H must be input. Power VCC Power supply Pin GND VSS GND Pin Clock Analog Power X0 X0A X1 X1A CROUT_0 CROUT_1 AVCC AVRL AVRH Document Number: 002-03984 Rev. *D Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in High-speed CR-osc clock output port A/D converter analog power supply pin A/D converter analog reference voltage input pin A/D converter analog reference voltage input pin FBGA161 GDC SDRAM-IF (176 pin only) GE_SDDQ24 GE_SDDQ25 GE_SDDQ26 GE_SDDQ27 GE_SDDQ28 GE_SDDQ29 GE_SDDQ30 GE_SDDQ31 GE_SDDQM0 GE_SDDQM1 GE_SDDQM2 GE_SDDQM3 Function LQFP120 (S6E2D35GJ A) Pin Name LQFP120 Ex-LQFP120 Module LQFP176 Pin No. 18 17 16 15 14 13 5 4 148 147 146 145 - - - 78 50 50 M8 84 56 56 M12 85 57 57 M11 1 23 44 62 89 133 173 24 45 61 88 132 159 176 86 79 87 80 52 64 90 92 93 1 13 30 40 61 91 117 14 31 39 60 90 107 120 58 51 59 52 34 42 62 64 65 1 13 30 40 61 91 117 14 31 39 60 90 107 120 58 51 59 52 34 42 62 64 65 C1 G1 L1 N4 L13 A12 A4 H1 M1 N3 M13 B13 A7 B1 N11 N7 N12 N9 L4 N5 K13 J13 J12 Page 45 of 182 S6E2D3 Series Module Pin Name LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D35GJ A) FBGA161 Pin No. VBAT Power VBAT VBAT power supply pin. Backup power supply (battery etc.) and system power supply. 81 53 53 M9 AVSS A/D converter GND pin 91 63 63 K12 Power supply stabilization capacity pin 60 38 38 N2 Analog GND C Pin C Function Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-03984 Rev. *D Page 46 of 182 S6E2D3 Series 5. I/O Circuit Type Type Circuit Remarks Pull-up resistor P-ch P-ch Digital output X1 N-ch Digital output R It is possible to select the main oscillation / GPIO function Pull-up resistor control Standby mode control When the main oscillation is selected. ・Oscillation feedback resistor Clock input : Approximately 1 MΩ ・With Standby mode control Digital input Feedback A resistor Standby mode control Digital input Standby mode control Pull-up resistor When the GPIO is selected. ・ CMOS level output. ・ CMOS level hysteresis input ・ With pull-up resistor control ・ With standby mode control ・ Pull-up resistor : Approximately 80 kΩ ・ IOH = -2 mA, IOL = 2 mA R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control ・CMOS level hysteresis input ・Pull-up resistor B Pull-up resistor : Approximately 80 kΩ Digital input Document Number: 002-03984 Rev. *D Page 47 of 182 S6E2D3 Series Type Circuit Remarks Digital input ・Open drain output C ・CMOS level hysteresis input N-ch Digital output P-ch P-ch Digital output ・CMOS level output ・CMOS level hysteresis input ・With pull-up resistor control ・With standby mode control D N-ch ・Pull-up resistor Digital output R : Approximately 80 kΩ ・IOH = -4 mA, IOL = 4 mA ・When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Pull-up resistor control Digital input Standby mode control P-ch P-ch ・CMOS level output Digital output ・CMOS level hysteresis input ・With pull-up resistor control ・With standby mode control ・Pull-up resistor E N-ch Digital output R : Approximately 80 kΩ ・IOH = -2 mA, IOL = 2 mA ・When this pin is used as an I2C pin, the digital output P-ch transistor is always Pull-up resistor control off. Digital input Standby mode control Document Number: 002-03984 Rev. *D Page 48 of 182 S6E2D3 Series Type Circuit P-ch P-ch Remarks Digital output ・CMOS level output ・CMOS level hysteresis input ・With input control N-ch Digital output ・Analog input ・With pull-up resistor control ・With standby mode control F ・Pull-up resistor : Approximately 80 kΩ R Pull-up resistor control ・IOH = -2 mA, IOL = 2 mA Digital input ・When this pin is used as an I2C pin, the digital output P-ch transistor is always Standby mode control off. Analog input Input control ・CMOS level output P-ch P-ch Digital output ・CMOS level hysteresis input ・With pull-up resistor control ・With standby mode control ・Pull-up resistor G N-ch : Approximately 80 kΩ Digital output R ・IOH = -8 mA, IOL = 8 mA ・When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Pull-up resistor control Digital input Standby mode control Document Number: 002-03984 Rev. *D Page 49 of 182 S6E2D3 Series Type Circuit Remarks GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control It is possible to select the USB I/O / GPIO function. UDP output UDP/Pxx USB Full-speed/Low-speed control When the USB I/O is selected. ・Full-speed, Low-speed control UDP input H Differential Differential input UDM/Pxx USB/GPIO select When the GPIO is selected. ・CMOS level output UDM input ・CMOS level hysteresis input UDM output ・With standby mode control USB Digital input/output direction ・IOH = -20.5 mA, IOL = 18.5 mA GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control P-ch P-ch Digital output ・CMOS level output ・CMOS level hysteresis input ・5 V tolerant ・With pull-up resistor control I ・With standby mode control N-ch Digital output R ・Pull-up resistor : Approximately 80 kΩ ・IOH = -2 mA, IOL = 2 mA ・Available to control of PZR registers. Pull-up resistor control Digital input Standby mode control J Document Number: 002-03984 Rev. *D Mode input ・CMOS level hysteresis input Page 50 of 182 S6E2D3 Series Type Circuit P-ch Remarks P-ch Digital output ・CMOS level output ・CMOS level hysteresis input ・With pull-up resistor control K ・With standby mode control N-ch Digital output R ・Pull-up resistor : Approximately 33 kΩ ・IOH = -11 mA, IOL = 11 mA Pull-up resistor control Digital input Standby mode control P-ch P-ch Digital output ・CMOS level output ・CMOS level hysteresis input ・TTL level hysteresis input L N-ch Digital output R :SDRAM-IF Data Input only ・With pull-up resistor control ・With standby mode control ・Pull-up resistor Pull-up resistor control : Approximately 33 kΩ ・IOH = -11 mA, IOL = 11 mA Digital input (TTL) Digital input (CMOS) Standby mode control Document Number: 002-03984 Rev. *D Page 51 of 182 S6E2D3 Series Type Circuit Remarks P-ch P-ch Pull-up resistor control Digital output ・CMOS level output ・CMOS level hysteresis input ・5 V tolerant ・With pull-up resistor control ・With standby mode control ・Pull-up resistor N N-ch N-ch Digital output : Approximately 80 kΩ ・IOH = -3 mA, IOL = 3 mA (GPIO) ・IOL = 20 mA (Fast Mode Plus) ・Available to control of PZR registers. Fast mode control R ・When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital input Standby mode control ・CMOS level output P-ch P-ch Pull-up resistor control Digital output ・CMOS level hysteresis input ・5 V tolerant ・With pull-up resistor control ・Pull-up resistor : Approximately 80 kΩ O ・IOH = -2 mA, IOL = 2 mA N-ch Digital output ・Available to control of PZR registers. ・Please refer to the "VBAT domain" setting of the IO in the “Peripheral Manual main part (002-04856)". R Digital input X0A R Digital input P ・CMOS level hysteresis input ・Please refer to the "VBAT domain" setting Sub OSC/GPIO select of the IO in the “Peripheral Manual main part (002-04856)". OSC Document Number: 002-03984 Rev. *D Page 52 of 182 S6E2D3 Series Type Circuit Remarks X1A R Digital input Sub OSC/ GPIO select OSC Q It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. ・Oscillation feedback resistor : Approximately 12 MΩ RX When the GPIO is selected. ・CMOS level hysteresis input Sub OSC enable ・Please refer to the "VBAT domain" setting of the IO in the “Peripheral Manual Clock input P-ch P-ch main part (002-04856)". Digital output ・CMOS level output ・CMOS level hysteresis input N-ch Digital output ・With input control ・Analog input R ・With pull-up resistor control ・With standby mode control R Pull-up resistor control Digital input ・Pull-up resistor : Approximately 80 kΩ ・IOH = -4 mA, IOL = 4 mA Standby mode control Analog input Input control Document Number: 002-03984 Rev. *D Page 53 of 182 S6E2D3 Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Document Number: 002-03984 Rev. *D Page 54 of 182 S6E2D3 Series Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason, it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Document Number: 002-03984 Rev. *D Page 55 of 182 S6E2D3 Series Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-03984 Rev. *D Page 56 of 182 S6E2D3 Series 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-03984 Rev. *D Page 57 of 182 S6E2D3 Series 7. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS, between AVCC and AVSS and between AVRH and AVRL near this device. A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ◼ Surface mount type Size: Load capacitance: Load capacitance: More than 3.2 mm × 1.5 mm Approximately 6 pF to 7 pF When the Standard setting (CCS/CCB=11001110) Approximately 4 pF to 7 pF When the low power setting (CCS/CCB=00000100) ◼ Lead type Load capacitance: Load capacitance: Approximately 6 pF to 7 pF When the Standard setting (CCS/CCB=11001110) Approximately 4 pF to 7 pF When the low power setting (CCS/CCB=00000100) Document Number: 002-03984 Rev. *D Page 58 of 182 S6E2D3 Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. ⚫ Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. X1(PE3), X1A (P47) Set as External clock input Handling when Using Multi-Function Serial Pin as I2C Pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I 2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Document Number: 002-03984 Rev. *D Page 59 of 182 S6E2D3 Series Notes on Power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then turns Power-off. About Hibernation control, see Chapter 7-3: VBAT Domain(B) in FM4 Family Peripheral Manual Main Part (002-04856). Turning on : VBAT → VCC→ AVCC → AVRH Turning off : AVRH → AVCC → VCC→ VBAT Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Pin Doubled as Debug Function Please use as output only regarding the pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK. Don't use as input. S6E2D35GJA The following must correspond to S6E2D35GJA. 1. Terminal DNU0 / 1 is short-circuited, and the pull-up of about 10kΩ is done. Device R DNU0 DNU1 2. Please do not connect the open end NC terminal. 3. Please have the following port settings. PFR7: PDOR7: DDR7: bit6=0, bit10=0 bit6=0, bit10=0 bit6=1, bit10=1 See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details. 4. Please connect a bypass capacitor as close as possible to GND on the board and VCC in pin number 22. Document Number: 002-03984 Rev. *D Page 60 of 182 S6E2D3 Series 8. Block Diagram S6E2D35J0A / S6E2D35G0A / S6E2D35GJA TRSTX,TCK, TDI,TMS TDO SWJ-DP ETM* TRACEDx, TRACECLK TPIU* ROM Table SRAM0 32Kbytes SRAM2 4Kbytes Cortex-M4 Core @160MHz(Max) I Sys AHB-APB Bridge:APB0(Max:80MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardw are) MainFlash I/F Multi-layer AHB (Max:160MHz) D NVIC MPU FPU Trace Buffer (16Kbytes) MainFlash 384Kbytes Security USB2.0 PHY UDP0,UDM0 (Host/Func) UHCONX0 DMAC 8ch. CSV DSTC 1unit(128ch.) CLK Source Clock CR 4MHz VBAT Domain X0A X1A Sub OSC CROUT TIOBx Unit 0 Unit 1 Base Timer 16bit 16ch./ 32bit 8ch AIN0 BIN0 ZIN0 QPRC 1ch. A/D Activation Compare 6ch. IC0x 16bit Input Capture 4ch. FRCK0 16bit Free-run Timer 3ch. 16bit Output Compare 6ch. DTTI0X RTO0x Waveform Generator 3ch. 16bit PPG 3ch. Multi-function Timer VBAT VWAKEUP VREGCTL RTCCO,SUBOUT 1unit VBAT Domain Real-Time Clock Port Cntl. PRG-CRC Accelerator I2S 2units GPIO PIN-Function-Ctrl MODE-Cntl. External Bus I/F VRAM 512Kbytes SDRAM I/F Graphic Engine core HyperBus I/F HighSpeed Quad SPI MD0,MD1 MADx MADATAx MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX ■SDRAM I/F GE_SDCLK,GE_SDCKE,GE_SDCSX, GE_SDCASX,GE_SDRASX,GE_SDWEX, GE_SDDQM[3:0],GE_SDBA[1:0], GE_SDA[11:0],GE_SDDQ[31:0] ■HyperBus I/F GE_HBCK, GE_HBDQ[7:0], GE_HBCSX0/1, GE_HBRWDS, GE_HBRESETX, GE_HBINTX, GE_HBRSTOX, GE_HBWPX ■HighSpeed Quad SPI GE_SPCK, GE_SPDQ[3:0], GE_SPCSX0 GDC Clock Cntl. PLL USB Clock Cntl. PLL I2S Clock Cntl. PLL VFLASH 2Mbytes *S6E2D35GJA Only Power-On Reset LVD Regulator IRQ-Monitor P0x, P1x, : PFx *S6E2D35GJA Unavailable LVD Cntl. Peripheral Clock Gating Low -speed CR Prescaler I2SMCLKx, I2SWSx,I2SCKx I2SDIx I2SDOx ■Panel I/F PNL_DCLK, PNL_DEN, PNL_PWE, PNL_LE, PNL_LH_SYNC, PNL_FV_SYNC, PNL_PD[23:0], PNL_TSIG[11:0] GDC unit AHB-APB Bridge:APB2(Max:80MHz) TIOAx 12bit A/D Converter 24ch. AHB-APB Bridge:APB1(Max:160MHz) AVCC,AVSS, AVRH,AVRL ANxx ADTG AHB-AHB Bridge (Slave) CR 100kHz PLL AHB-AHB Bridge (Master) Main OSC AHB-AHB Bridge (Slave) X0 X1 Deep Standby Cntl. External Interrupt Controller 16ch + NMI C WKUPx INTxx NMIX CRC Accelerator Watch Counter Document Number: 002-03984 Rev. *D Multi-function Serial I/F 8ch. (w ith FIFO ch.0 to ch.7) HW flow control(ch.4) SCKx SINx SOTx CTS4 RTS4 SCSx Page 61 of 182 S6E2D3 Series 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map GDC Area 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M4 Private Peripherals 0xDFFF_FFFF 0xD0A0_6000 0xD0A0_5000 0xD0A0_4000 0xD0A0_3000 0xD0A0_1000 0xD0A0_0000 0xD008_0000 0xD000_0000 0xC000_0000 0xB000_0000 Reserved GDC_HBIF GDC_HSQSPI GDC_SDRAMIF Reserved GDC Reserved VRAM Memory Area for GDC_HSQSPI or GDC_HBIF External SDRAM GDC Peripherals Area 0xB000_0000 0x8000_0000 External Device Area Reserved SDRAM 256Mbytes 0x7000_0000 0x6000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256Mbytes Reserved 0x4400_0000 0x4200_0000 0x4000_0000 0x2400_0000 0x2200_0000 0x2004_1000 0x2004_0000 0x2000_0000 0x1FFF_8000 32Mbytes Bit band alias Peripherals Reserved 32Mbytes Bit band alias Reserved SRAM2 4Kbytes Reserved SRAM0 32Kbytes Reserved 0x0040_4000 0x0040_2000 0x0040_0000 CR trimming Security Reserved 0x0006_0000 Flash 384Kbytes 0x0000_0000 Document Number: 002-03984 Rev. *D 0x41FF_FFFF 0x4008_1000 0x4008_0000 0x4007_0000 0x4006_F000 0x4006_E000 0x4006_D000 0x4006_C000 0x4006_2000 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 0x4003_F000 0x4003_E000 0x4003_D100 0x4003_D000 0x4003_C800 0x4003_C100 0x4003_C000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_7000 0x4003_6000 0x4003_5000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Reserved Programable-CRC Reserved GPIO Reserved Reserved I2S Reserved DSTC DMAC Reserved USB ch.0 EXT-bus I/F Reserved GDC Prescaler I2S Prescaler Reserved Peripheral Clock Gating LowSpeed CR Prescaler RTC/Port Ctrl Watch Counter CRC MFS Reserved USB Clock Ctrl LVD/DS mode Reserved Int-Req.Read EXTI Reserved CR Trim Reserved A/DC QPRC Base Timer PPG Reserved MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F Page 62 of 182 S6E2D3 Series Peripheral Address Map Start address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_1000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_5000 0x4003_5800 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_C100 0x4003_C800 0x4003_D000 0x4003_D100 0x4003_E000 0x4003_F000 0x4004_0000 0x4005_0000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_C000 0x4006_D000 0x4006_E000 0x4006_F000 0x4007_0000 0x4008_0000 0x4008_1000 0xB000_0000 End address 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_0FFF 0x4002_3FFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_4FFF 0x4003_57FF 0x4003_5FFF 0x4003_6FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_C0FF 0x4003_C7FF 0x4003_CFFF 0x4003_D0FF 0x4003_DFFF 0x4003_EFFF 0x4003_FFFF 0x4004_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_1FFF 0x4006_BFFF 0x4006_CFFF 0x4006_DFFF 0x4006_EFFF 0x4006_FFFF 0x4007_FFFF 0x4008_0FFF 0x41FF_FFFF 0xDFFF_FFFF Document Number: 002-03984 Rev. *D Bus AHB APB0 APB1 APB2 AHB AHB Peripherals MainFlash I/F register Reserved Clock/Reset Control Hardw are Watchdog timer Softw are Watchdog timer Reserved Dual-Timer Reserved Multi-function timer unit0 Reserved PPG Base Timer Quadrature Position/Revolution Counter A/D Converter Reserved Internal CR trimming Reserved External Interrupt Controller Interrupt Request Batch-Read Function Reserved Low Voltage Detector Deep standby mode Controller USB clock generator Reserved Multi-function serial Interface CRC Watch Counter RTC/PortCtrl Low -speed CR Prescaler Peripheral Clock Gating Reserved I2S Prescaler GDC Prescaler Reserved External Memory interface USB ch.0 Reserved DMAC register DSTC register Reserved I2S Reserved Reserved GPIO Reserved Programmable-CRC Reserved GDC unit Page 63 of 182 S6E2D3 Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. ◼ INITX=0 This is the period when the INITX pin is the L level. ◼ INITX=1 This is the period when the INITX pin is the H level. ◼ SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. ◼ SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. ◼ Input enabled Indicates that the input function can be used. ◼ Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. ◼ Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. ◼ Setting disabled Indicates that the setting is disabled. ◼ Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. ◼ Analog input is enabled Indicates that the analog input is enabled. ◼ Trace output Indicates that the trace function can be used. ◼ GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. ◼ Setting prohibition Prohibition of a setting by specification limitation. Document Number: 002-03984 Rev. *D Page 64 of 182 S6E2D3 Series Pin status Type List of Pin Status Power-on Reset or Low-Voltage Detection State Function Group INITX Input State Device Run Mode Internal or Sleep Reset Mode State State Power Supply Unstable Power Supply Stable ‐ INITX=0 INITX=1 ‐ ‐ Power Supply Stable ‐ INITX=1 Timer Mode RTC Mode or Stop Mode State Power Supply Stable INITX=1 Return Deep Standby RTC from Deep Mode or Deep Standby Standby Stop Mode State Mode State Power Supply Stable Power Supply Stable INITX=1 INITX=1 ‐ SPL=0 SPL=1 SPL=0 SPL=1 - GPIO selected Setting disabled Setting Setting disabled disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input Input enabled enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting Setting disabled disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External main clock input selected Setting disabled Setting Setting disabled disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / input enabled Pull-up / Pull-up / input input enabled enabled Pull-up / input enabled Pull-up / input enabled Pull-up / input enabled Pull-up / input enabled Pull-up / input enabled Pull-up / input enabled D Mode input pin Input enabled Input Input enabled enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled A B Document Number: 002-03984 Rev. *D Hi-Z / Internal input fixed at 0 Maintain previous state/ When oscillation stops*1,Hi-Z / Internal input fixed at 0 Page 65 of 182 Pin status Type S6E2D3 Series Power-on Reset or Low-Voltage Detection State Function Group INITX Input State F Return Deep Standby RTC from Deep Mode or Deep Standby Standby Stop Mode State Mode State Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - Mode input pin Input enabled Input Input enabled enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting Setting disabled disabled Maintain previous state Maintain previous state Hi-Z / input enabled GPIO selected Hi-Z / input enabled GPIO selected NMIX selected Setting disabled Setting Setting disabled disabled Resource other than above selected Hi-Z Hi-Z / Hi-Z / input input enabled enabled Hi-Z Pull-up / Pull-up / Input Input enabled enabled GPIO selected JTAG selected G H Timer Mode RTC Mode or Stop Mode State Power Supply Unstable ‐ E Device Run Mode Internal or Sleep Reset Mode State State GPIO selected Setting disabled Setting Setting disabled disabled JTAG selected Hi-Z Pull-up / Pull-up / Input Input enabled enabled Resource other than above selected Setting disabled Setting Setting disabled disabled Hi-Z Hi-Z / Hi-Z / input input enabled enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Resource selected I GPIO selected Document Number: 002-03984 Rev. *D Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected Page 66 of 182 Pin status Type S6E2D3 Series Power-on Reset or Low-Voltage Detection State Function Group INITX Input State K Resource other than above selected Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 Setting disabled ‐ ‐ ‐ Maintain previous state Hi-Z Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input input fixed fixed fixed at 0 / at 0 / at 0 / Analog Analog Analog input input input enabled enabled enabled Setting Setting disabled disabled GPIO selected Document Number: 002-03984 Rev. *D SPL=1 Maintain previous state Hi-Z / Hi-Z / input input enabled enabled Setting disabled SPL=0 Setting Setting disabled disabled Hi-Z L Resource other than above selected Return Deep Standby RTC from Deep Mode or Deep Standby Standby Stop Mode State Mode State Power Supply Stable GPIO selected Analog input selected Timer Mode RTC Mode or Stop Mode State Power Supply Unstable ‐ External interrupt enabled selected Device Run Mode Internal or Sleep Reset Mode State State Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 SPL=0 SPL=1 - GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Page 67 of 182 Pin status Type S6E2D3 Series Power-on Reset or Low-Voltage Detection State Function Group INITX Input State M Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 Hi-Z ‐ ‐ ‐ Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input input fixed fixed fixed at 0 / at 0 / at 0 / Analog Analog Analog input input input enabled enabled enabled SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Setting disabled Setting Setting disabled disabled Maintain previous state Maintain previous state GPIO selected Analog input selected N Hi-Z Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input input fixed fixed fixed at 0 / at 0 / at 0 / Analog Analog Analog input input input enabled enabled enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Resource other than above selected Return Deep Standby RTC from Deep Mode or Deep Standby Standby Stop Mode State Mode State Power Supply Stable External interrupt enabled selected Resource other than above selected Timer Mode RTC Mode or Stop Mode State Power Supply Unstable ‐ Analog input selected Device Run Mode Internal or Sleep Reset Mode State State Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Trace output Setting disabled Setting Setting disabled disabled GPIO selected Document Number: 002-03984 Rev. *D Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Page 68 of 182 Pin status Type S6E2D3 Series Power-on Reset or Low-Voltage Detection State Function Group INITX Input State O Timer Mode RTC Mode or Stop Mode State Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 Hi-Z ‐ ‐ ‐ Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input input fixed fixed fixed at 0 / at 0 / at 0 / Analog Analog Analog input input input enabled enabled enabled SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Trace selected Trace output External interrupt enabled selected Maintain previous state Resource other than above selected Setting disabled Setting Setting disabled disabled Maintain previous state Maintain previous state GPIO selected WKUP enabled P Resource other than above selected Return Deep Standby RTC from Deep Mode or Deep Standby Standby Stop Mode State Mode State Power Supply Unstable ‐ Analog input selected Device Run Mode Internal or Sleep Reset Mode State State Setting disabled Setting Setting disabled disabled GPIO selected Document Number: 002-03984 Rev. *D Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Page 69 of 182 Pin status Type S6E2D3 Series Power-on Reset or Low-Voltage Detection State Function Group INITX Input State Device Run Mode Internal or Sleep Reset Mode State State Timer Mode RTC Mode or Stop Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 WKUP enabled Q External interrupt enabled selected Resource other than above selected Setting disabled Hi-Z Hi-Z / Hi-Z / input input enabled enabled Hi-Z Hi-Z / Hi-Z / input input enabled enabled R USB I/O pin Setting disabled SPL=1 Maintain previous state Setting Setting disabled disabled Maintain previous state GPIO selected GPIO selected Return Deep Standby RTC from Deep Mode or Deep Standby Standby Stop Mode State Mode State Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z at transmission/ Setting Setting Internal disabled disabled input fixed at 0 at reception SPL=0 SPL=1 - WKUP input enabled Hi-Z / WKUP input enabled WKUP input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z at transmission/ Internal input fixed at 0 at reception Hi-Z / input enabled Hi-Z / input enabled Hi-Z / input enabled Hi-Z / input enabled *1: Oscillation is stopped at Sub timer mode, low-speed CR timer mode, RTC mode, Stop mode, Deep standby RTC mode, and Deep standby Stop mode. Document Number: 002-03984 Rev. *D Page 70 of 182 S6E2D3 Series VBAT Pin Status Type List of VBAT Domain Pin Status S T Power-on Reset*1 Function Group Power Supply Unstable ‐ ‐ INITX Input State Run Device Mode Internal or Sleep Reset Mode State State Power Supply Stable INITX=0 ‐ Internal input fixed at 0 INITX=1 ‐ Internal input fixed at 0 Timer Mode RTC Mode or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State VBAT RTC Mode State Return from VBAT RTC Mode State Power Supply Stable - Power Supply Sable - Power Supply Stable INITX=1 ‐ Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Power Supply Stable INITX=1 - Input enabled Input enabled Input enabled Input enabled Input enabled Input Setting enabled prohibition GPIO selected Setting disabled Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Internal input fixed at 0 Internal input fixed at 0 Input enabled Input enabled Input enabled Input enabled Input enabled Input Setting enabled prohibition External sub clock input selected Setting disabled Maintain Maintain Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous previous previous state state state state state state state state Maintain Hi-Z/ previous Internal Sub crystal Maintain Maintain Maintain state / input fixed oscillator previous previous previous When at 0 or output pin state state state oscillation input stops, enabled Hi-Z*2 Resource Maintain Maintain Maintain Maintain selected U Hi-Z previous previous previous previous GPIO state state state state selected Maintain previous state - Maintain previous state - Maintain previous state Maintain previous state Maintain Maintain Maintain previous previous previous state / state / state / Maintain When When When previous oscillation oscillation oscillation state stops, stops, stops, Hi-Z*2 Hi-Z*2 Hi-Z*2 Maintain previous state Maintain previous state Maintain Maintain Maintain Maintain previous previous previous previous state state state state Maintain previous state Maintain previous state *1: When VBAT and VCC power on. *2: When the SOSCNTL bit in the WTOSCCNT register is 0, Sub crystal oscillator output pin maintains the previous state. When the SOSCNTL bit in the WTOSCCNT register is 1, Oscillation is stopped at Stop mode and Deep standby Stop mode Document Number: 002-03984 Rev. *D Page 71 of 182 S6E2D3 Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Power supply voltage *1, *2 Power supply voltage (VBAT) *1 ,*3 Analog power supply voltage *1 ,*4 Analog reference voltage *1 ,*4 Input voltage *1 Symbol VCC Min VSS - 0.5 VBAT AVCC AVRH VSS - 0.5 VSS - 0.5 VSS - 0.5 VI VSS - 0.5 VSS - 0.5 Analog pin input voltage *1 Output voltage *1 L level maximum output current *5 L level average output current *6 L level total maximum output current L level total average output current *7 H level maximum output current *5 H level average output current *6 H level total maximum output current H level total average output current *7 Power consumption Storage temperature VIA VSS - 0.5 VO VSS - 0.5 IOL - IOLAV - ∑IOL ∑IOLAV - IOH - IOHAV - ∑IOH ∑IOHAV PD TSTG - 55 Rating Max VSS + 4.6 Unit Remarks V VSS + 4.6 VSS + 4.6 VSS + 4.6 VCC + 0.5 (≤ 4.6 V) VSS + 6.5 AVCC + 0.5 (≤ 4.6 V) VCC + 0.5 (≤ 4.6 V) 10 20 20 20 22.4 2 4 8 11 20 100 50 - 10 V V V mA mA mA mA mA mA mA mA mA mA mA mA mA 2 mA type 4 mA type 8 mA type 11 mA type I2C Fm+ 2 mA type 4 mA type 8 mA type 11 mA type I2C Fm+ -20 mA 4 mA type - 20 - 20 -2 -4 -8 - 11 - 100 - 50 200 + 150 mA mA mA mA mA mA mA mA mW °C 8 mA type 11 mA type 2 mA type 4 mA type 8 mA type 11 mA type V V 5 V tolerant V V 2 mA type *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: VBAT must not drop below VSS - 0.5 V. *4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-03984 Rev. *D Page 72 of 182 S6E2D3 Series 12.2 Recommended Operating Conditions Parameter Symbol Conditions VCC - VBAT AVCC AVRH AVRL CS TJ TA - Power supply voltage Power supply voltage (VBAT) Analog power supply voltage Analog reference voltage Smoothing capacitor Junction temperature Operating temperature Ambient temperature Value Min Max 3.0 3.6 2.7 *5 3.6 1.65 3.6 2.7 3.6 *4 AVCC AVss AVss 1 10 -40 + 125 -40 *3 Unit V V V V V μF °C °C Remarks *1 *2 AVCC = VCC for built-in regulator *6 *1: When using the GDC part . When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *3: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (TJ). The calculation formula of the ambient temperature (TA) is shown below. TA(Max) = TJ(Max) - Pd(Max) × θJA Pd: θJA: Power dissipation (W) Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: IOH: VOL: VOH: L level output current H level output current L level output voltage H level output voltage *4: The minimum value of Analog reference voltage depends on the value of compare clock cycle (tCCK). See 14.5 12-bit A/D Converter for the details. *5: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. *6: See "C pin" in "7. Handling Devices" for the connection of the smoothing capacitor. Document Number: 002-03984 Rev. *D Page 73 of 182 S6E2D3 Series Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table 12-1 Table for Package Thermal Resistance and Maximum Permissible Power Maximum Permissible Power (mW) TA= +85°C TA= +105°C Printed Circuit Board Thermal Resistance θJA (°C/W) LQFP: LQM120 (0.5 mm pitch) 4 layers 38 1053 526 LQFP: LQM120 *1 (0.5 mm pitch) 4 layers 39 1026 513 LQFP: LQP176 (0.5 mm pitch) 4 layers 35 1143 571 FBGA: FDJ161 (0.5 mm pitch) 4 layers 35 1143 571 Ex-LQFP: LEM120 (0.5 mm pitch) 4 layers 18*2 2222 1111 Package *1: When S6E2D35GJA product. *2: This is a case where the connection process was carried out back exposed die pad foundation. Please connect directly to GND back exposed die pad. Notes: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-03984 Rev. *D Page 74 of 182 S6E2D3 Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): Current consumed in internal logic and memory, etc. through regulator ΣICC(IO): Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include I CC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Pin internal load capacitance CINT Conditions 2 mA type 4 mA type 8 mA type Capacitance Value 1.93 pF 3.45 pF 3.42 pF Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself. (1) Measure current value ICC (Typ) at normal temperature (+25°C). (2) Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Symbol Maximum leak current at operating ICC(leak_max) Conditions TJ = +125 °C TJ = +105 °C TJ = +85 °C Current Value 66.8 mA 33.7 mA 22.8 mA Note: − VFLASH of current is not included Document Number: 002-03984 Rev. *D Page 75 of 182 S6E2D3 Series Current Explanation Diagram Pd = VCC×ICC + Σ(IOL×VOL)+Σ((VCC-VOH)×(-IOH)) ICC = ICC(INT)+ΣICC(IO) VCC A ICC Chip ICC(INT) ΣICC(IO) A Regulator VOL V A ・・・ V IOL Flash VOH ・・・ Logic IOH RAM ICC(IO) CEXT ・・・ Document Number: 002-03984 Rev. *D Page 76 of 182 S6E2D3 Series 12.3 DC Characteristics 12.3.1 Current Rating Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Parameter Power supply current Symbol ICC Pin Name Conditions Normal operation *6,*7 (PLL) *5 Normal operation , *6,*7 (PLL) *5 VCC Value Frequency*4 (MHz) Typ* Max*2 Unit 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 182 176 167 159 151 143 136 128 123 122 43 39 34 29 24 20 15 10 7 6 279 270 256 244 233 221 210 199 191 190 117 112 106 100 95 90 84 78 74 73 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=3.6 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to main flash memory and VFLASH memory *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: 002-03984 Rev. *D Page 77 of 182 S6E2D3 Series Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Parameter Power supply current Symbol ICC Pin Name Frequency*4 (MHz) Conditions Normal operation *6,*7,*8 (PLL) *5 Normal operation *6,*7,*8 (PLL) *5 VCC 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz Value Typ* Max*2 1 185 179 169 161 154 146 138 130 125 124 45 41 36 31 26 22 17 12 10 9 285 276 261 250 239 227 215 204 196 195 122 117 111 105 99 94 89 83 80 79 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=3.6 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *5: When not operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) *6: With data access to a main flash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *8: Data access is nothing to VFLASH memory Document Number: 002-03984 Rev. *D Page 78 of 182 S6E2D3 Series Table 12-4 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Frequency*4 (MHz) Conditions *5 Power supply current ICC VCC Normal operation , *6,*7,*8 (PLL) *5 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz Value Typ* Max*2 1 168 161 154 147 140 133 131 128 41 36 32 27 23 18 17 15 251 242 233 224 214 205 202 199 114 108 104 98 94 88 87 85 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=3.6 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: With data access to a main flash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *8: Data access is nothing to VFLASH memory Document Number: 002-03984 Rev. *D Page 79 of 182 S6E2D3 Series Table 12-5 Typical and Maximum Current Consumption in Normal Operation (other than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Normal operation, *6,*8 (built-in Highspeed CR) Power supply current ICC VCC Frequency*4 (MHz) Conditions Normal operation , *6,*7,*8 (Sub oscillation) Normal operation , *6,*8 (built-in Low-speed CR) *5 *5 *5 Value Typ* Max*2 1 Unit 110 181 mA 4.1 74 mA 0.7 76.65 mA 0.69 71.65 mA 0.74 88.65 mA 0.73 74.65 mA 4 MHz 32 kHz 100 kHz Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=3.6 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: With data access to a main flash memory. *7: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) *8: Data access is nothing to VFLASH memory Document Number: 002-03984 Rev. *D Page 80 of 182 S6E2D3 Series Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Sleep *5,*6 operation (PLL) Power supply current ICCS VCC Sleep *5,*6 operation (PLL) Frequency*4 (MHz) 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz Value Typ*1 Max*2 103 181 98 175 91 168 86 162 80 155 74 149 69 143 63 137 59 132 58 131 24 91 22 89 19 86 16 83 14 81 11 78 9 76 6 73 5 72 4 71 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=3.6 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: Data access is nothing to VFLASH memory Document Number: 002-03984 Rev. *D Page 81 of 182 S6E2D3 Series Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Power supply current Symbol ICCS Pin Name VCC Conditions Sleep *5,*6 operation (PLL) Frequency*4 (MHz) 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 8 MHz 4 MHz Value Typ*1 Max*2 84 160 80 155 75 150 71 145 67 141 63 137 61 134 60 133 15 82 13 80 12 79 10 77 8 75 7 74 6 73 5 72 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=3.6 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: Data access is nothing to VFLASH memory Document Number: 002-03984 Rev. *D Page 82 of 182 S6E2D3 Series Table 12-8 Typical and Maximum Current Consumption in Sleep Operation (other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Sleep *6 operation (built-in High-speed CR) Power supply current ICCS VCC Sleep *5,*6 operation (Sub oscillation) Sleep *6 operation (built-in Low-speed CR) Frequency*4 (MHz) Value Typ* Max*2 1 Unit 56 126 mA 2 72 mA 0.52 69.65 mA 0.51 69.65 mA 0.54 70.65 mA 0.52 69.65 mA 4 MHz 32 kHz 100 kHz Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=3.6 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) *6: Data access is nothing to VFLASH memory Document Number: 002-03984 Rev. *D Page 83 of 182 S6E2D3 Series Table 12-9 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode Parameter Symbol Pin Name ICCH Conditions Stop mode Timer mode (built-in High-speed CR) Power supply current ICCT VCC Timer mode *5 (Sub oscillation) Timer mode (built-in Low-speed CR) ICCR RTC mode (Sub oscillation) Frequency (MHz) - 4 MHz 32 kHz 100 kHz 32 kHz Value Typ*1 Max*2 Unit 0.41 2.07 mA *3, *4 TA=+25°C - 21.35 mA *3, *4 TA=+85°C - 30.57 mA *3, *4 TA=+105°C 1.14 2.8 mA *3, *4 TA=+25°C - 22.08 mA *3, *4 TA=+85°C - 31.3 mA *3, *4 TA=+105°C 0.43 2.09 mA *3, *4 TA=+25°C - 21.37 mA *3, *4 TA=+85°C - 30.59 mA *3, *4 TA=+105°C 0.43 2.09 mA *3, *4 TA=+25°C - 21.37 mA *3, *4 TA=+85°C - 30.59 mA *3, *4 TA=+105°C 0.41 2.07 mA *3, *4 TA=+25°C - 21.35 mA *3, *4 TA=+85°C - 30.57 mA *3, *4 TA=+105°C Remarks *1: VCC=3.3 V *2: VCC=3.6 V *3: When all ports are fixed. *4: When LVD is OFF *5: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) Document Number: 002-03984 Rev. *D Page 84 of 182 S6E2D3 Series Table 12-10 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT Parameter Symbol Pin Name Conditions Frequency (MHz) Deep Standby Stop mode (When RAM is OFF) - Value Typ*1 Max*2 Unit 108 173 μA - 1774 μA - 2208 μA 112 177 μA - 1778 μA - 2212 μA 109 174 μA - 1771 μA - 2205 μA 113 178 μA - 1775 μA - 2209 μA 0.009 0.032 μA - 0.994 μA - 1.491 μA 1.0 1.636 μA - 2.828 μA - 4.242 μA 0.7 1.153 μA - 2.277 μA - 3.416 μA ICCHD Deep Standby Stop mode (When RAM is ON) - VCC Deep Standby RTC mode (When RAM is OFF) ICCRD 32 kHz Deep Standby RTC mode (When RAM is ON) Power supply current RTC stop *8 ICCVBAT VBAT RTC *6, *8 operation RTC *7, *8 operation - Remarks *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4, *5 TA=+25°C *3, *4, *5 TA=+85°C *3, *4, *5 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *3, *4 TA=+25°C *3, *4 TA=+85°C *3, *4 TA=+105°C *1: VCC=3.3 V *2: VCC=3.6 V *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF *6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) When the Standard setting (CCS/CCB=11001110) *7: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) When the low power setting (CCS/CCB=00000100) *8: In the case of setting RTC after VCC power on Document Number: 002-03984 Rev. *D Page 85 of 182 S6E2D3 Series Table 12-11 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase, VFLASH Memory (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Low-voltage detection circuit (LVD) power supply current Main flash memory write/erase current VFLASH memory Standby current VFLASH memory Read current VFLASH memory write/erase current Symbol Pin name Conditions Min Value Typ Max Unit ICCLVD At operation - 4 7 μA ICCFLASH At Write/Erase - 13.4 15.8 mA At Standby - 15 35 μA At Read - 9 14 13 20 At Write/Erase - 20 25 Remarks For occurrence of interrupt VCC ICCVFLASH mA 40MHz 80MHz mA Peripheral Current Dissipation Clock system HCLK PCLK1 PCLK2 GECLK Peripheral Unit GPIO DMAC DSTC External bus I/F USB I2 S Programmable CRC Base timer Multi-functional timer/PPG Quadrature position/Revolution counter A/DC All ports 1ch. 1 unit 4ch. Multi-function serial GDC unit GDC High-Speed Quad SPI HyperBus I/F SDRAM-IF Document Number: 002-03984 Rev. *D 1unit/4ch. Frequency (MHz) 40 80 160 0.30 0.60 1.19 0.99 1.95 3.82 0.41 0.83 1.61 0.18 0.35 0.70 0.47 0.93 1.85 0.36 0.71 1.42 0.04 0.09 0.18 0.20 0.39 0.76 0.61 1.21 Unit Remarks mA TA=+25°C, VCC=3.3 V mA TA=+25°C, VCC=3.3 V 2.40 1ch. 0.04 0.09 0.18 1 unit 0.25 0.50 1.00 1ch. 0.44 0.88 - mA TA=+25°C, VCC=3.3 V 1 unit 1ch. 1 unit 1ch. 31 1.1 0.6 2.3 57 2.3 1.2 4.6 109 - mA TA=+25°C, VCC=3.3 V Page 86 of 182 S6E2D3 Series 12.3.2 Pin Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) H level output voltage L level output voltage Input leak current Pull-up resistor value Input capacitance Symbol VIHS VILS Pin Name CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin Input pin doubled as I2C Fm+ TTL Schmitt input pin CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin Input pin doubled as I2C Fm+ VOH VOL Min Value Typ Max Unit - VCC×0.8 - VCC + 0.3 V - VCC×0.8 - VSS + 5.5 V - VCC×0.7 - VSS + 5.5 V - 2.0 - VCC+0.3 V - VSS - 0.3 - VCC×0.2 V - VSS - 0.3 - VCC×0.2 V - VSS - VCC×0.3 V TTL Schmitt input pin - VSS - 0.3 - 0.8 V 2 mA type 4 mA type 8 mA type IOH = - 2 mA IOH = - 4 mA IOH = - 8 mA VCC - 0.5 VCC - 0.5 VCC - 0.5 - VCC VCC VCC V V V 11 mA type IOH = - 11 mA VCC - 0.5 - VCC V IOH = - 13.0 mA VCC - 0.4 - VCC V IOH = - 3 mA VCC - 0.5 - VCC V IOL = 2 mA IOL = 4 mA IOL = 8 mA IOL = 11 mA VSS VSS VSS VSS - 0.4 0.4 0.4 0.4 V V V V IOL = 10.5 mA VSS - 0.4 V IOL = 3 mA IOL = 20 mA VSS - 0.4 V - -5 - +5 μA - 30 80 200 - 15 33 70 - - 5 15 The pin doubled as USB I/O The pin doubled as I2C Fm+ 2 mA type 4 mA type 8 mA type 11 mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ IIL - RPU Pull-up pin CIN Other than VCC, VBAT, VSS, AVCC, AVSS, AVRH Document Number: 002-03984 Rev. *D Conditions kΩ Remarks Highspeed IO At GPIO At GPIO At I2C Fm+ Highspeed IO pF Page 87 of 182 S6E2D3 Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Input frequency Input clock cycle Symbol Pin Name Conditions Value Unit Max - 4 20 MHz When crystal oscillator is connected - 4 20 MHz When using external clock - 50 250 ns When using external clock PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock - - 5 ns When using external clock fCH tCYLH X0, X1 Remarks Min Input clock pulse width - Input clock rising time and falling time tCF, tCR fCM - - - 160 MHz Master clock fCC - - - 160 MHz Base clock (HCLK/FCLK) fCP0 fCP1 fCP2 - - 5 10 5 10 80 160 80 - MHz MHz MHz ns ns ns ns APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 Internal operating clock*1 frequency Internal operating clock*1 cycle time tCYCC tCYCP0 tCYCP1 tCYCP2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 Document Number: 002-03984 Rev. *D Page 88 of 182 S6E2D3 Series 12.4.2 Sub Clock Input Characteristics (VBAT = 1.65V to 3.6V, VSS = 0V) Parameter Symbol Input frequency Pin Name Value Conditions Unit Min Typ Max - - 32.768 - kHz - 32 - 100 kHz tCYLL - 10 - 31.25 μs - PWH/tCYLL, PWL/tCYLL 45 - 55 % 1/tCYLL X0A, X1A Input clock cycle Input clock pulse width Remarks When crystal oscillator is connected * When using external clock When using external clock When using external clock *: For more information about crystal oscillator, see Sub crystal oscillator in 9. Handling Devices. tCYLL 0.8 × VBAT 0.8 × VBAT 0.8 × VBAT 0.2 × VBAT 0.2 × VBAT X0A PWH PWL 12.4.3 Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Clock frequency Frequency stabilization time fCRH Value Conditions Min Typ Max TJ = - 20 °C to + 105 °C 3.92 4 4.08 TJ = - 40 °C to + 125 °C 3.88 4 4.12 TJ = - 40 °C to + 125 °C 2.9 4 5 - - - 30 tCRWT Unit Remarks When trimming *1 MHz When not trimming μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Clock frequency Symbol Condition fCRL - Document Number: 002-03984 Rev. *D Value Min Typ Max 50 100 150 Unit Remarks kHz Page 89 of 182 S6E2D3 Series 12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Min Value Typ Max tLOCK 100 - - μs fPLLI fPLLO 4 13 200 - - 16 100 400 200 MHz multiplier MHz MHz Symbol fCLKPLL Unit Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1 : Clock in FM4 Family Peripheral Manual Main part (002-04856). 12.4.5 Operating Conditions of USB/I2S/GDC PLL (In the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 3.6V, VSS = 0V) Min Value Typ Max tLOCK 100 - - μs fPLLI - 4 13 - fPLLO 200 - 16 100 400 384 MHz multiplier MHz MHz USB clock frequency *2 fCLKPLL - - 50 MHz I2S clock frequency *3 fCLKPLL - - 12.288 MHz GDC clock frequency *4 fCLKPLL - - 160 MHz Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Symbol Unit Remarks USB/GDC I2 S After the M frequency division After the M frequency division After divided by GDC part *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about USB clock, see Chapter 2-2: USB Clock Generation in FM4 Family Peripheral Manual Communication Macro part (002-04862). *3: For more information about I2S clock, see Chapter 7-1: I2S Clock Generation in FM4 Family Peripheral Manual Communication Macro part (002-04862). *4: For more information about GDC clock, see FM4 Family Peripheral Manual GDC part (002-04917). Document Number: 002-03984 Rev. *D Page 90 of 182 S6E2D3 Series 12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Min Value Typ Max tLOCK 100 - - fPLLI 3.8 4 4.2 MHz fPLLO 50 190 - 95 400 multiplier MHz fCLKPLL - - 160 MHz Symbol PLL oscillation stabilization wait (LOCK UP time) PLL input clock frequency time*1 PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Unit Remarks μs *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). Note:  The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main PLL. 12.4.7 Reset Input Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Reset input time Symbol Pin Name conditions tINITX INITX - Document Number: 002-03984 Rev. *D Value Min Max 500 - Unit Remarks ns Page 91 of 182 S6E2D3 Series 12.4.8 Power-on Reset Timing (VSS = 0V) Parameter Symbol Power supply shut down time Pin Name Min Typ Max - 1 - - VCC: 0.2V to 2.70V 0.6 - 1000 - 0.33 - 0.60 tOFF Power ramp rate dV/dt Time until releasing Power-on reset VCC Value Conditions tPRT Unit ms Remarks *1 mV/µs *2 ms *1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 7. 2.7V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST 0.2V tOFF release RST Active CPU Operation start Glossary  VDH: detection voltage of Low Voltage detection reset. See “Error! Reference source not found.. Error! Reference source no t found.”. 12.4.9 GPIO Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Output frequency Symbol Pin Name Conditions tPCYCLE Pxx* - Value Min Max - 32 Unit Remarks MHz *: GPIO is a target. Pxx tPCYCLE Document Number: 002-03984 Rev. *D Page 92 of 182 S6E2D3 Series 12.4.10 External Bus Timing External Bus Clock Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name tCYCLE MCLKOUT*1 Output frequency Value Conditions Min Max - 50*2 Unit Remarks MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual Main part (002-04856). *2: Generate MCLKOUT at setting more than 4 divisions when the AHB bus clock exceeds 100 MHz. 0.8 × Vcc 0.8 × Vcc MCLKOUT tCYCLE External Bus Signal Input/output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Signal input characteristics Signal output characteristics Symbol VIH VIL VOH VOL Conditions Value Unit - 0.8 × VCC 0.2 × VCC 0.8 × VCC 0.2 × VCC V V V V Input signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL Document Number: 002-03984 Rev. *D Remarks Page 93 of 182 S6E2D3 Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Value Symbol Pin name Condition s Min Max tOEW MOEX - MCLK×n-3 - ns MCSX↓→Address output delay time tCSL – AV MCSX, MAD[24:0] - -9 +9 ns MOEX↑→Address hold time tOEH - AX MOEX, MAD[24:0] - 0 MCLK×m+9 ns MCSX↓→ MOEX↓delay time tCSL - OEL - MCLK×m-9 MCLK×m+9 ns MOEX↑→ MCSX↑time tOEH - CSH - 0 MCLK×m+9 ns Parameter MOEX Minimum pulse width MCSX↓→ MDQM↓delay time MOEX, MCSX Unit tCSL - RDQML MCSX, MDQM[1:0] - MCLK×m-9 MCLK×m+9 ns Data setup→ MOEX↑time tDS - OE MOEX, MADATA[15:0] - 20 - ns MOEX↑→ Data hold time tDH - OE MOEX, MADATA[15:0] - 0 - ns tWEW MWEX - MCLK×n-3 - ns MWEX↑→Address output delay time tWEH - AX MWEX, MAD[24:0] - 0 MCLK×m+9 ns MCSX↓→ MWEX↓delay time tCSL - WEL - MCLK×n-9 MCLK×n+9 ns MWEX↑→ MCSX↑delay time tWEH - CSH - 0 MCLK×m+9 ns MCSX↓→ MDQM↓delay time tCSL-WDQML MCSX, MDQM[1:0] - MCLK×n-9 MCLK×n+9 ns tCSL-DX MCSX, MADATA[15:0] - MCLK-9 MCLK+9 ns tWEH - DX MWEX, MADATA[15:0] - 0 MCLK×m+9 ns MWEX Mininum pulse width MCSX↓→ Data output time MWEX↑→ Data hold time MWEX, MCSX Remarks Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) Document Number: 002-03984 Rev. *D Page 94 of 182 S6E2D3 Series tCYCLE MCLK tOEH-CSH tWEH-CSH MCSX tCSL-AV MAD[24:0] tOEH-AX Address tWEH-AX tCSL-AV Address tCSL-OEL MOEX tOEW tCSL-WDQML tCSL-RDQML MDQM[1:0] tCSL-WEL tWEW MWEX tDS-OE MADATA[15:0] tDH-OE RD tWEH-DX WD Invalid tCSL-DX Document Number: 002-03984 Rev. *D Page 95 of 182 S6E2D3 Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Address delay time tAV MCLK, MAD[24:0] MCSX delay time MOEX delay time Data set up →MCLK↑ time MCLK↑→ Data hold time MWEX delay time MDQM[1:0] delay time tCSL tCSH tREL tREH tDH tWEL tWEH tDQML tDQMH Unit Max - 1 9 ns MCLK, MCSX - 1 9 ns - 1 9 ns MCLK, MOEX - 1 9 ns - 1 9 ns - 19 - ns - 0 - ns MCLK, MWEX - 1 9 ns - 1 9 ns MCLK, MDQM[1:0] - 1 9 ns - 1 9 ns - MCLK+1 MCLK+18 ns - 1 18 ns MCLK, MADATA[15:0] MCLK, MADATA[15:0] tDS Value Min MCLK↑→ MCLK, tODS MADATA[15:0] Data output time MCLK↑→ MCLK, tOD MADATA[15:0] Data hold time Note: − When the external load capacitance CL = 30 pF Remarks tCYCLE MCLK tCSL tCSH MCSX tAV tAV Address MAD[24:0] Address tREL tREH tDQML tDQMH MOEX tDQML tDQMH tWEL tWEH MDQM[1:0] MWEX MADATA[15:0] tDS tDH RD tOD WD Invalid tODS Document Number: 002-03984 Rev. *D Page 96 of 182 S6E2D3 Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Multiplexed address delay time tALE-CHMADV Multiplexed address hold time tCHMADH Pin Name MALE, MAD[24:0] Conditions Value Unit Min Max - 0 10 ns - MCLK×n+0 MCLK×n+10 ns Remarks Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) MCLK MCSX MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-03984 Rev. *D Page 97 of 182 S6E2D3 Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter MALE delay time Symbol Pin Name tCHAL MCLK, MALE tCHAH MCLK↑→Multiplexed address delay time MCLK↑→Multiplexed data output time tCHMADV tCHMADX MCLK, MADATA[15:0] Value Condition s Min Max - 1 9 ns - 1 9 ns - 1 tOD ns - 1 tOD ns Unit Remarks Note: − When the external load capacitance CL = 30 pF MCLK MCSX MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-03984 Rev. *D Page 98 of 182 S6E2D3 Series NAND Flash Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter MNREX Min pulse width Data set up →MNREX↑time Symbol Pin Name Conditions tNREW MNREX tDS – NRE MNREX, MADATA[15:0] MNREX, MADATA[15:0] MNALE, MNWEX MNALE, MNWEX Value Unit Min Max - MCLK×n-3 - ns - 20 - ns - 0 - ns - MCLK×m-9 MCLK×m+9 ns - MCLK×m-9 MCLK×m+9 ns MNREX↑→ Data hold time MNALE↑→ MNWEX delay time MNALE↓→ MNWEX delay time MNCLE↑→ MNWEX delay time tCLEH - NWEL MNCLE, MNWEX - MCLK×m-9 MCLK×m+9 ns MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX - 0 MCLK×m+9 ns MCLK×n-3 - ns -9 9 ns 0 MCLK×m+9 ns tDH – NRE tALEH - NWEL tALEL - NWEL MNWEX tNWEW MNWEX Min pulse width MNWEX↓→ MNWEX, tNWEL – DV MADATA[15:0] Data output time MNWEX↑→ MNWEX, tNWEH – DX MADATA[15:0] Data hold time Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) Remarks NAND Flash Read MCLK MNREX MADATA[15:0] Document Number: 002-03984 Rev. *D Read Page 99 of 182 S6E2D3 Series NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Document Number: 002-03984 Rev. *D Write Page 100 of 182 S6E2D3 Series External Ready Input Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter MCLK↑ MRDY input setup time Symbol Pin Name Conditions tRDYI MCLK, MRDY - Value Min Max 19 - Unit Remarks ns ◼ When RDY is input ·· · MCLK Over 2cycles Original MOEX MWEX tRDYI MRDY ◼ When RDY is released MCLK ··· ··· 2 cycles Extended MOEX MWEX tRDYI 0.5×VCC MRDY Document Number: 002-03984 Rev. *D Page 101 of 182 S6E2D3 Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Output frequency tCYCSD MSDCLK Address delay time tAOSD MSDCLK↑→ Data output delay time MSDCLK↑→ Data output Hi-Z time tDOSD tDOZSD MDQM[1:0] delay time tWROSD MCSX delay time tMCSSD MRASX delay time tRASSD MCASX delay time tCASSD MSDWEX delay time tMWESD MSDCKE delay time tCKESD Data setup time tDSSD Data hold time tDHSD MSDCLK, MAD[15:0] MSDCLK, MADATA[15:0] MSDCLK, MADATA[15:0] MSDCLK, MDQM[1:0] MSDCLK, MCSX8 MSDCLK, MRASX MSDCLK, MCASX MSDCLK, MSDWEX MSDCLK, MSDCKE MSDCLK, MADATA[15:0] MSDCLK, MADATA[15:0] Unit Unit Min Max - - 50 MHz - 2 12 ns - 2 12 ns - 2 19.5 ns - 1 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 2 12 ns - 19 - ns - 0 - ns Remarks Note: − When the external load capacitance CL = 30 pF Document Number: 002-03984 Rev. *D Page 102 of 182 S6E2D3 Series tCYCSD SDRAM Access MSDCLK tAOSD MAD[24:0] MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE Address tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDSSD MADATA[15:0] tDOSD MADATA[15:0] Document Number: 002-03984 Rev. *D tDHSD RD tDOZSD WD Page 103 of 182 S6E2D3 Series 12.4.11 Base Timer Input Timing Timer Input Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Input pulse width Symbol Pin Name Cond itions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min 2tCYCP Max - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger Input Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Input pulse width Value Symbol Pin Name Cond itions Min tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP tTRGH TGIN VIHS Max - Unit Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet. Document Number: 002-03984 Rev. *D Page 104 of 182 S6E2D3 Series 12.4.12 CSIO Timing Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V) Baud rate Serial clock cycle time Symb ol tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE Parameter SCK falling time SCK rising time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions Internal shift clock operation Min 4tCYCP Value Mbps ns - 30 + 30 ns 50 - ns 0 - ns - ns - ns - 50 ns 10 - ns 20 - ns - 5 5 ns ns 2tCYCP 10 tCYCP + 10 External shift clock operation Unit Max 8 - Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 105 of 182 S6E2D3 Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-03984 Rev. *D Page 106 of 182 S6E2D3 Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx Baud rate Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation Min 4tCYCP Value Mbps ns - 30 + 30 ns 50 - ns 0 - ns - ns - ns - 50 ns 10 - ns 20 - ns - 5 5 ns ns 2tCYCP 10 tCYCP + 10 External shift clock operation Unit Max 8 - Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 107 of 182 S6E2D3 Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL VIH SCK VIL tR tSLSH tSHOVE SOT SIN VIH VIL VIL tF VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-03984 Rev. *D Page 108 of 182 S6E2D3 Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Baud rate Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation Min 4tCYCP Value Mbps ns - 30 + 30 ns 50 - ns 0 - ns - ns - ns - ns - 50 ns 10 - ns 20 - ns - 5 5 ns ns 2tCYCP 30 2tCYCP 10 tCYCP + 10 External shift clock operation Unit Max 8 - Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 109 of 182 S6E2D3 Series tSCYC VOH SCK SOT VOL VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK SOT VIH *V VIL tSHSL VIH VIL tF tR VIH tSHOVE VOH VOL OH VOL tIVSLE SIN tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-03984 Rev. *D Page 110 of 182 S6E2D3 Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Baud rate Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - Internal shift clock operation External shift clock operation Value Unit Min 4tCYCP Max 8 - Mbps ns - 30 + 30 ns 50 - ns 0 - ns 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - ns ns - 50 ns 10 - ns 20 - ns - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 111 of 182 S6E2D3 Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL SOT VIH tSLSH VIH VIL tF VIL VIH tSLOVE VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-03984 Rev. *D Page 112 of 182 S6E2D3 Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↓ setup time tCSSE SCK↑→SCS↑ hold time tCSHE SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation Value Min Max Unit (*1)-50 (*1)+0 ns (*2)+0 (*3)-50 +5tCYCP 3tCYCP+30 (*2)+50 (*3)+50 +5tCYCP - ns 0 - ns 3tCYCP+30 - ns - 40 ns 0 - ns ns ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 113 of 182 S6E2D3 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 114 of 182 S6E2D3 Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↓→SCK↑ setup time tCSSI SCK↓→SCS↑ hold time tCSHI SCS deselect time tCSDI Conditions Internal shift clock operation Value Min Max Unit (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 ns (*3)-50+5tCYCP (*3)+50+5tCYCP ns SCS↓→SCK↑ setup time tCSSE 3tCYCP+30 - ns SCK↓→SCS↑ hold time tCSHE 0 - ns SCS deselect time tCSDE 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 40 ns SCS↑→SOT delay time tDEE 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (00204856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 115 of 182 S6E2D3 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 116 of 182 S6E2D3 Series When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↑→SCK↓ setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↓ setup time tCSSE SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation Value Unit Min Max (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 ns (*3)-50+5tCYCP (*3)+50+5tCYCP ns 3tCYCP+30 - ns 0 - ns 3tCYCP+30 - ns - 40 ns 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (00204856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 117 of 182 S6E2D3 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 118 of 182 S6E2D3 Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↑→SCK↑ setup time tCSSI SCK↓→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↑ setup time tCSSE SCK↓→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation Value Unit Min Max (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 ns (*3)-50+5tCYCP (*3)+50+5tCYCP ns 3tCYCP+30 - ns 0 - ns 3tCYCP+30 - ns - 40 ns 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (00204856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 119 of 182 S6E2D3 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 120 of 182 S6E2D3 Series High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx Conditions Internal shift clock operation SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx External shift clock operation Value Unit Min 4tCYCP Max - - 10 + 10 ns - ns 5 - ns 2tCYCP - 5 tCYCP + 10 - ns ns - 15 ns 5 - ns 5 - ns - 5 5 ns ns 14 12.5* ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins.  SIN6_0, SOT6_0, SCK6_0, SCS60_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-03984 Rev. *D Page 121 of 182 S6E2D3 Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL VIH VIL SIN MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-03984 Rev. *D Page 122 of 182 S6E2D3 Series High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SCKx SCKx, SOTx SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time tF tR SCKx, SINx Conditions Internal shift clock operation SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx External shift clock operation Value Unit Min 4tCYCP Max - - 10 + 10 ns - ns 5 - ns 2tCYCP - 5 tCYCP + 10 - ns ns - 15 ns 5 - ns 5 - ns - 5 5 ns ns 14 12.5* ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins.  SIN6_0, SOT6_0, SCK6_0, SCS60_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-03984 Rev. *D Page 123 of 182 S6E2D3 Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK VIL tR tSLSH VIH VIH SIN VIL tF tSHOVE SOT VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-03984 Rev. *D Page 124 of 182 S6E2D3 Series High-Speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Serial clock cycle time tSCYC SCK↑→SOT delay time tSHOVI SCKx SCKx, SOTx SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time tF tR SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions Internal shift clock operation External shift clock operation Value Unit Min 4tCYCP Max - - 10 + 10 ns - ns 5 - ns 2tCYCP - 10 - ns 2tCYCP - 5 tCYCP + 10 - ns ns - 15 ns 5 - ns 5 - ns - 5 5 ns ns 14 12.5* ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins.  SIN6_0, SOT6_0, SCK6_0, SCS60_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-03984 Rev. *D Page 125 of 182 S6E2D3 Series tSCYC VOH SCK SOT VOL VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK SOT VIH VIL VIH VIL tF *V tR VIH tSHOVE VOH VOL OH VOL tIVSLE SIN tSHSL tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-03984 Rev. *D Page 126 of 182 S6E2D3 Series High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SCKx SCKx, SOTx SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time tF tR SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions Internal shift clock operation External shift clock operation Value Unit Min 4tCYCP Max - - 10 + 10 ns - ns 5 - ns 2tCYCP - 10 - ns 2tCYCP - 5 tCYCP + 10 - ns ns - 15 ns 5 - ns 5 - ns - 5 5 ns ns 14 12.5* ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins.  SIN6_0, SOT6_0, SCK6_0, SCS60_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-03984 Rev. *D Page 127 of 182 S6E2D3 Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-03984 Rev. *D Page 128 of 182 S6E2D3 Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↓→SCK↓ setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time tCSDI Conditions Internal shift clock operation Value Min Max Unit (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 ns (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS↓→SCK↓ setup time tCSSE 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - ns SCS deselect time tCSDE 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 ns SCS↑→SOT delay time tDEE 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (00204856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 129 of 182 S6E2D3 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 130 of 182 S6E2D3 Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↓→SCK↑ setup time tCSSI SCK↓→SCS↑ hold time tCSHI SCS deselect time tCSDI Conditions Internal shift clock operation Value Min Max Unit (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 ns (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS↓→SCK↑ setup time tCSSE 3tCYCP+15 - ns SCK↓→SCS↑ hold time tCSHE 0 - ns SCS deselect time tCSDE 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 ns SCS↑→SOT delay time tDEE 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (00204856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 131 of 182 S6E2D3 Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 132 of 182 S6E2D3 Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↑→SCK↓ setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↓ setup time tCSSE SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation Value Unit Min Max (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 ns (*3)-20+5tCYCP (*3)+20+5tCYCP ns 3tCYCP+15 - ns 0 - ns 3tCYCP+15 - ns - 25 ns 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (00204856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 133 of 182 S6E2D3 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 134 of 182 S6E2D3 Series When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCS↑→SCK↑ setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↑ setup time tCSSE SCK↓→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Conditions Internal shift clock operation External shift clock operation Value Unit Min Max (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 ns (*3)-20+5tCYCP (*3)+20+5tCYCP ns 3tCYCP+15 - ns 0 - ns 3tCYCP+15 - ns - 40 ns 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (00204856). − When the external load capacitance CL = 30 pF. Document Number: 002-03984 Rev. *D Page 135 of 182 S6E2D3 Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-03984 Rev. *D Page 136 of 182 S6E2D3 Series External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time Symbol tSLSH tSHSL tF tR Condition CL = 30 pF tR tSHSL SCK V IL Document Number: 002-03984 Rev. *D Min tCYCP + 10 tCYCP + 10 - VIH Value Max 5 5 VIL Remarks ns ns ns ns tF tSLSH VIH Unit VIL VIH Page 137 of 182 S6E2D3 Series 12.4.13 External Input Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Min Max Conditions Unit ADTG - 2tCYCP*1 - ns IC0x DTTI0X - - ns - ns INTxx, NMIX - 2tCYCP*1 2tCYCP + 100(*1) 500(*2) - ns 500(*3) - ns FRCK0 Input pulse width tINH, tINL WKUPx - Remarks A/D converter trigger input Free-run timer input clock Input capture Waveform generator External interrupt, NMI Deep standby wake up (*1): tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which the Multi-function Timer and External interrupt are connected to, see 8. Block Diagram in this data sheet. (*2): When in STOP mode, in timer mode. (*3): When in deep standby RTC mode, in deep standby Stop mode. Document Number: 002-03984 Rev. *D Page 138 of 182 S6E2D3 Series 12.4.14 Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Conditions AIN pin H width AIN pin L width BIN pin H width BIN pin L width BIN rising time from AIN pin H level AIN falling time from BIN pin H level BIN falling time from AIN pin L level AIN rising time from BIN pin L level AIN rising time from BIN pin H level BIN falling time from AIN pin H level AIN falling time from BIN pin L level BIN rising time from AIN pin L level ZIN pin H width ZIN pin L width AIN/BIN rising and falling time from determined ZIN level Determined ZIN level from AIN/BIN rising and falling time tAHL tALL tBHL tBLL tZHL tZLL PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 QCR:CGSC=0 QCR:CGSC=0 tZABE QCR:CGSC=1 tABEZ QCR:CGSC=1 tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU Min Value 2tCYCP* Max - Unit ns *: tCYCP indicates the APB bus clock cycle time except when in Stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8. Block Diagram in this data sheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 002-03984 Rev. *D tBLL Page 139 of 182 S6E2D3 Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN Document Number: 002-03984 Rev. *D Page 140 of 182 S6E2D3 Series ZIN AIN/BIN Document Number: 002-03984 Rev. *D Page 141 of 182 S6E2D3 Series 12.4.15 I2C Timing Standard Mode, Fast Mode (VCC = 2.7V to 3.6, VSS = 0V) Parameter SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width (Repeated) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between Stop condition and Start condition Noise filter Symbol Conditions fSCL Standard Mode Min Max 0 100 Fast Mode Min Max 0 400 Unit kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs tHDDAT 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP*4 - - ns 4 tCYCP*4 - - ns 6 tCYCP*4 - - ns 8 tCYCP*4 - - ns tSUSTA tSP CL = 30 pF, R = (Vp/IOL)*1 2 MHz ≤ tCYCP<40 MHz 40 MHz ≤ tCYCP<60 MHz 60 MHz ≤ tCYCP<80 MHz 80 MHz ≤ tCYCP ≤ 100 MHz 2 tCYCP*4 4 tCYCP*4 6 tCYCP*4 8 tCYCP*4 Remarks *5 *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast mode I2C bus device can be used on a Standard mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see 8. Block Diagram in this data sheet. When the standard mode is used, please set to 2 MHz or more peripheral bus clock. When fast mode is used, please set to 8MHz or more peripheral bus clock. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. Document Number: 002-03984 Rev. *D Page 142 of 182 S6E2D3 Series Fast Mode Plus (Fm+) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol SCL clock frequency (Repeated) Start condition hold time SDA ↓ → SCL ↓ SCL clock L width SCL clock H width (Repeated) Start condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ Stop condition setup time SCL ↑ → SDA ↑ Bus free time between Stop condition and Start condition fSCL Noise filter Conditions Fast Mode Plus (Fm+)*6 Min Max 0 1000 Unit kHz tHDSTA 0.26 - μs tLOW tHIGH 0.5 0.26 - μs μs 0.26 - μs tHDDAT 0 0.45*2, *3 μs tSUDAT 50 - ns tSUSTO 0.26 - μs tBUF 0.5 - μs 6 tCYCP*4 - ns 8 tCYCP*4 - ns tSUSTA tSP CL = 30 pF, R = (Vp/IOL)*1 60 MHz ≤ tCYCP<80 MHz 80 MHz ≤ tCYCP ≤100 MHz Remarks *5 *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (t LOW) of device's SCL signal. *3: A Fast mode I2C bus device can be used on a Standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see 8. Block Diagram in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. *6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See Chapter 12 : I/O Port in "FM4 Family Peripheral Manual Main part (002-04856)" for the details. SDA SCL 12.4.16 ETM Timing (VCC = 2.7V to 3.6V, VSS = 0V) Document Number: 002-03984 Rev. *D Page 143 of 182 S6E2D3 Series Parameter Data hold Symbol Pin Name Conditions tETMH TRACECLK, TRACED[3:0] - TRACECLK frequency 1/tTRACE TRACECLK clock cycle tTRACE Min 2 - Value Max Unit 15 ns 32 MHz - ns Remarks TRACECLK - 31.25 Note: − When the external load capacitance CL= 30 pF. HCLK TRACECLK TRACED[3:0] Document Number: 002-03984 Rev. *D Page 144 of 182 S6E2D3 Series 12.4.17 JTAG Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Value Symbol Pin Name Conditions TMS, TDI setup time tJTAGS TCK, TMS, TDI - 15 - ns TMS, TDI hold time tJTAGH TCK, TMS, TDI - 15 - ns TDO delay time tJTAGD TCK, TDO - - 45 ns Min Max Unit Remarks Note: − When the external load capacitance CL= 30 pF. TCK TMS/TDI TDO Document Number: 002-03984 Rev. *D Page 145 of 182 S6E2D3 Series 12.4.18 I2S Timing Master Mode Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions tMCYC tMHW I2SCK - I2SCK - Output frequency Output clock pulse width I2SCK→I2SWS delay time I2SCK→I2SDO delay time* I2SDI→I2SCK setup time I2SDI→I2SCK hold time Input signal rising time Input signal falling time tMLW tDFS tDDO tHSDI tHDI tRI tFI I2SCK, I2SWS I2SCK, I2SDO I2SCK, I2SDI I2SDI Min 45 Value Unit Max 12.288 55 MHz % 45 55 % - 0 24.0 ns - 0 24.0 ns - 25.0 - ns - 0 - ns - - 5 ns - - 5 ns Remarks *: Except for the first bit of transmission frame Notes: − When the external load capacitance CL = 20 pF − When I2SWS=48 kHz, I2MCLK=256 × I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the details. Document Number: 002-03984 Rev. *D Page 146 of 182 S6E2D3 Series t MCYC tMHW I2SCK (CPOL=0) tMLW I2SCK (CPOL=1) tDFS I2SWS (FSPH=0, FSLN=0) tDFS tDFS tDFS I2SWS (FSPH=1, FSLN=0) tDFS tDFS I2SWS (FSPH=0, FSLN=1) tDFS tDFS I2SWS (FSPH=1, FSLN=1) tDDO I2SDO tSDI tHDI tSDI tHDI I2SDI (SMPL=0) tSDI tHDI I2SDI (SMPL=1) Note: − See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the details of CPOL, FSPH, FSLIN, SMPL . I2SDI 0. 8×VCC 0. 8×VCC 0.2×V CC t FI Document Number: 002-03984 Rev. *D 0. 8×VCC 0.2×V CC tRI Page 147 of 182 S6E2D3 Series Slave Mode Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions tSCYC tSHW I2SCK - I2SCK - Input frequency Input clock pulse width I2SWS→I2SCK Setup time I2SWS→I2SCK Hold time I2SCK↑→I2SDO Delay time*1 I2SCK↑→I2SDO Delay Time*2 I2SDI→I2SCK↓ Setup time I2SDI→I2SCK↓ Hold time Input signal rising time Input signal falling time tSLW tSFI tHFI I2SCK, I2SWS I2SCK, I2SWS tDDO Min 45 Value Unit Max 12.288 55 MHz % 45 55 % - 8 - ns - 0 - ns - 0 32 ns - 0 32 ns - 8 - ns - 0 - ns - - 5 ns - - 5 ns Remarks I2SCK, I2SDO tDFB1 tSDI I2SCK, I2SDI tHDI tRI tFI I2SCK, I2SWS,I2SDI *1: Except for the first bit of transmission frame *2: When FSPH register 1. Notes: − When the external load capacitance CL = 20 pF − When I2SWS=48 kHz, I2MCLK=256 × I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the details. Document Number: 002-03984 Rev. *D Page 148 of 182 S6E2D3 Series tSCYC tSHW I2SCK (CPOL=0) tSLW I2SCK (CPOL=1) tSFI tHFI I2SWS (FSPH=0, FSLN=0) tSFI tHFI I2SWS (FSPH=1, FSLN=0) tSFI I2SWS (FSPH=0, FSLN=1) tSFI I2SWS (FSPH=1, FSLN=1) tDDO tDFB1 1 I2SDO tSDI tHDI tSDI tHDI I2SDI (SMPL=0) tSDI tHDI I2SDI (SMPL=1) Notes: − See Chapter 7-2: I2S(Inter-IC Sound bus)Interface in FM4 Family Peripheral Manual Communication part (002-04862) for the details of FSPH, FSLN, SMPL − I2SCK input is selectable polarity by CPOL bit of CNTREG register I2SCK I2SWS I2SDI 0. 8×VCC 0. 8×VCC 0.2×V CC t FI Document Number: 002-03984 Rev. *D 0. 8×VCC 0.2×V CC tRI Page 149 of 182 S6E2D3 Series ・I2SMCLK Input Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Value Symbol Pin Name Conditions Input frequency fCHS I2SCK - - 25 MHz Input clock cycle tCYLHS - 40 - ns - - PWHS/tCYLHS PWLS/tCYLHS 45 55 % tCFS tCRS - - - 5 ns Parameter Input clock pulse width Input clock rising time and falling time Min Max Unit Remarks When using external clock When using external clock tCYLHS I2SMCLK 0.8×VCC 0.8×VCC 0.8×VCC 0.2×VCC PWHS 0.2×VCC PWLS tCFS tCRS ・I2SMCLK Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions fCHS I2SCK - Input frequency Document Number: 002-03984 Rev. *D Min - Value Max 12.288 Unit Remarks MHz Page 150 of 182 S6E2D3 Series 12.4.19 GDC: Panel Output Timing (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Value Symbol Pin Name Conditions tCYCPNGE PNL_DCLK - - 40 MHz tPDOPDGE PNL_PD[23:0] - -4.5 4.5 ns tHDOPDGE PNL_LH_SYNC - -4.5 4.5 ns tVDOPDGE PNL_FV_SYNC - -4.5 4.5 ns tLDOPDGE PNL_LE - -4.5 4.5 ns PNL_DCLK↓→PNL_DEN Output delay time tDDOPDGE PNL_DEN - -4.5 4.5 ns PNL_DCLK↓→PNL_PWE Output delay time tPDOPDGE PNL_PWE -4.5 4.5 ns Output frequency PNL_DCLK↓→PNL_PD[23:0] Output delay time PNL_DCLK↓→PNL_LH_SYN C Output delay time PNL_DCLK↓→PNL_FV_SYN C Output delay time PNL_DCLK↓→PNL_LE Output delay time Min Max Unit − tCYCPNGE PNL_DCLK PNL_PD[23:0] tPDOPDGE PNL_LHSYNC tHDOPDGE PNL_FVSYNC tVDOPDGE PNL_LE tLDOPDGE PNL_DEN tDDOPDGE PNL_PWE tPDOPDGE Document Number: 002-03984 Rev. *D Page 151 of 182 S6E2D3 Series 12.4.20 GDC: SDRAM-IF Timing (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Output frequency tCYCSD Address delay time Value Unit Min Max GE_SDCLK - 80 MHz tAOSD GE_SDCLK GE_SDA[11:0] 1 5 ns Bank address delay time tBAOSD GE_SDCLK GE_SDBA[1:0] 1 5 ns GE_SDCLK↑→ Data output delay time tDOSD GE_SDCLK GE_SDDQ[31:0] 1 5 ns GE_SDCLK↑→ Data output Hi-Z time tDOZSD GE_SDCLK GE_SDDQ[31:0] 1 5 ns GE_SDDQM[3:0] delay time tWROSD GE_SDCLK GE_SDDQM[3:0] 1 5 ns GE_SDCSX delay time tSCSSD GE_SDCLK GE_SDCSX 1 5 ns GE_SDRASX delay time tRASSD GE_SDCLK GE_SDRASX 1 5 ns GE_SDCASX delay time tCASSD GE_SDCLK GE_SDCASX 1 5 ns GE_SDWEX delay time tSWESD GE_SDCLK GE_SDWEX 1 5 ns GE_SDCKE delay time tCKESD GE_SDCLK GE_SDCKE 1 5 ns Data setup time tDSSD GE_SDCLK GE_SDDQ[31:0] 4 - ns Data hold time tDHSD GE_SDCLK GE_SDDQ[31:0] 0 - ns Document Number: 002-03984 Rev. *D Page 152 of 182 S6E2D3 Series tCYCSD GE_SDCLK tAOSD Address GE_SDA[11:0] tBAOSD Address GE_SDBA[1:0] tWROSD GE_SDDQM[3:0] tSCSSD GE_SDCSX tRASSD GE_SDRASX tCASSD GE_SDCASX tSWESD GE_SDWEX tCKESD GE_SDCKE tDSSD GE_SDRASX RD tDOSD GE_SDRASX Document Number: 002-03984 Rev. *D tDHSD tDOZSD WD Page 153 of 182 S6E2D3 Series 12.4.21 GDC: High-Speed Quad SPI Timing (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Serial clock frequency tSCYCM GE_SPCK Enabled CS→ CLK Starting Time (mode0/mode2) Conditions Value Unit Min Max - 80 MHz tOSLSK02 1.5×tSCYCM – 4.25 - ns Enabled CS→ CLK Starting Time (mode1/mode3) tOSLSK13 tSCYCM – 4.25 - ns CLK Last→ Disabled CS Time (mode0/mode2) tOSKSL02 tSCYCM - ns CLK Last→ Disabled CS Time (mode1/mode3) tOSKSL13 1.5×tSCYCM - ns -1.25 4.25 ns 4 - ns 0.5×tSCYCM - ns GE_SPCK, GE_SPCSX0 SIO Data output time tOSDAT SIO Setup tDSSET SIO Hold tSDHOLD CL=20 pF GE_SPCK, GE_SPDQ0, GE_SPDQ1, GE_SPDQ2, GE_SPDQ3 Note: − See Chapter 8-3: High-Speed Quad SPI controller in FM4 Family Peripheral Manual Communication part (002-04862) for the detail of RTM mode. Document Number: 002-03984 Rev. *D Page 154 of 182 S6E2D3 Series GE_SPCSX0 t SCYCM mode0 mode2 t OSLSK02 GE_SPCK t OSKSL02 mode1 mode3 t OSKSL13 tOSLSK13 GE_SPDQ0, GE_SPDQ1, GE_SPDQ2, GE_SPDQ3 input tDSSET tSDHOLD output tOSDAT Document Number: 002-03984 Rev. *D Page 155 of 182 S6E2D3 Series 12.4.22 GDC: HyperBus I/F Timing HyperFlash Write (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Symbol Pin Name tCKCYC Hyper Bus clock cycle CS↑↓→CK↑ Chip Select setup time CS↓→RDS↓ Chip select active to RDS valid(Low) DQ → CK↑↓ Input setup time CK↑↓→ DQ Input hold time CK↓ → CS↑ Chip select hold time CS↑→ RDS(Hi-z) Chip select Inactive to RDS High-Z CS↑ → CS↓ Chip select HIGH between operation Conditions Value Unit Min Max GE_HBCK 10 - ns tCSS GE_HBCSX1 GE_HBCSX0 3 - ns tDSV GE_HBRWDS - 8 ns 0.8 - ns 0.8 - ns 0 - ns - 7 ns 8 - ns GE_HBDQ7GE_HBDQ0 GE_HBDQ7GE_HBDQ0 GE_HBCSX1 GE_HBCSX0 GE_HBCSX1 GE_HBCSX0 GE_HBCSX1 GE_HBCSX0 tIS tIH tCSH tDSZ tCSHI CL=30 pF tCSHI GE_HBCSX0,1 VOH VOL tCKCYC tCSS VOH GE_HBCK tCSH tCSS VOL tDSV tDSZ GE_HBRWDS tIS GE_HBDQ7-0 CA0 47-40 CA0 39-32 CA1 31-24 CA1 23-16 tIH VIH CA2 15-8 CA2 7-0 Dn 15-8 Dn 7-0 VIL Document Number: 002-03984 Rev. *D Page 156 of 182 S6E2D3 Series HyperFlash Read (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Hyper Bus clock cycle Symbol Pin Name tRDSCYC Read initial Access Time CS↑↓→CK↑ Chip Select setup time CS↓ → RDS↓ Chip select active to RDS valid (Low) DQ → CK↑↓ Input setup time CK↑↓→ DQ Input hold time CK↓ → CS↑ Chip select hold time CS↑ → RDS(Hi-Z) Chip select Inactive to RDS High-Z CK↑↓ → DQ (Low Z) Clock to DQs Low Z RDS↑↓→ DQ (valid) RDS transition to DQ valid RDS↑↓→ DQ (invalid) RDS transition to DQ invalid CS↑→ DQ (Hi-Z) Chip select Inactive to DQs High-Z CK↑↓→ RDS↑↓ CK transition to RDS transition CS↑→ CS↓ Chip select HIGH between Operation Value Conditions Unit Min Max GE_HBCK 10 - ns tACC GE_HBCK - 120 ns tCSS GE_HBCSX1 GE_HBCSX0 3 - ns tDSV GE_HBRWDS - 8 ns 0.8 - ns 0.8 - ns 0 - ns - 7 ns 0 - ns -0.8 +0.8 ns -0.8 +0.8 ns - 7 ns GE_HBDQ7GE_HBDQ0 GE_HBDQ7GE_HBDQ0 GE_HBCSX1 GE_HBCSX0 tIS tIH tCSH tDSZ CL=30pF GE_HBRWDS GE_HBDQ7GE_HBDQ0 GE_HBDQ7GE_HBDQ0 GE_HBDQ7GE_HBDQ0 GE_HBDQ7GE_HBDQ0 tDQLZ tDSS tDSH tOZ tCKDS GE_HBRWDS 1 7 ns tCSHI GE_HBCSX1 GE_HBCSX0 8 - ns tCSHI tACC GE_HBCSX0,1 VOH VOL tCSH tCSS GE_HBCK VOL tDSV tDQLZ tCKDS tRDSCYC tDSZ tOZ VOH GE_HBRWDS tIH tIS tDSH VIH GE_HBDQ7-0 tCSS VOH CA0 47-40 CA0 39-32 CA1 31-24 CA1 23-16 CA2 15-8 VIL Document Number: 002-03984 Rev. *D tDSS VOH CA2 7-0 Dn 15-8 Dn 7-0 Dn+1 15-8 Dn+1 7-0 VOL Page 157 of 182 S6E2D3 Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 3.6V, VSS = AVSS = AVRL = 0V) - - - Value Typ ±2 AVRH ± 2 ±3 ±8 LSB Conversion time - - 1.0*1 - - μs Sampling time *2 tS - 0.3 - 10 μs Compare clock cycle*3 tCCK - 50 - 1000 ns State transition time to operation permission tSTT - - - 1.0 μs Power supply current (analog + digital) - AVCC - 0.30 0.45 mA - 0.1 9.5 μA Reference power supply current(AVRH) - AVRH - 0.66 1.18 mA - 0.2 3.2 μA CAIN RAIN - - - - 12.05 1.8 4 pF kΩ LSB - ANxx - - 5 μA Analog input voltage - ANxx Reference voltage - AVRH AVRL AVSS AVSS 2.7 AVSS - AVRH AVCC AVCC AVSS V V V V VZT Pin Name ANxx Min - VFST ANxx - Parameter Symbol Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage Full-scale transition voltage Total error Analog input capacity Analog input resistance Interchannel disparity Analog port input leak current Max 12 ± 4.5 ± 2.5 ±7 Unit bit LSB LSB LSB AVRH ± 7 LSB Remarks AVRH=2.7 V to 3.6 V Offset calibration when used A/D 1unit operation When A/D stop A/D 1unit operation AVRH=3.3 V When A/D stop tCCK ≥ 50 ns *1: The conversion time is the value of sampling time (tS) + compare time (tC). Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part (002-04860). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus signal to which the A/D converter is connected, see 10. Block Diagram in this data sheet. The sampling clock and compare clock are set at base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2). Document Number: 002-03984 Rev. *D Page 158 of 182 S6E2D3 Series ANxx Analog input pin REXT Analog signal source Comparator RAIN CAIN Cin (Equation 1) tS ≥ (RAIN + REXT) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D = 1.8 kΩ CAIN: Input capacity of A/D = 12.05 pF REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-03984 Rev. *D Page 159 of 182 S6E2D3 Series Definition of 12-bit A/D Converter Terms ◼ Resolution: Analog variation that is recognized by an A/D converter. ◼ Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. ◼ Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actually-measured value) 0x003 0x002 0x001 (Actuallymeasured value) Digital output Digital output 0xFFD Differential Nonlinearity Actual conversion characteristics Ideal characteristics 0xN Ideal characteristics VNT Actual conversion characteristics AVRH AVss Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST : VNT: (Actually-measured value) (Actually-measured value) 0x(N-2) VZT (Actually-measured value) AVss V(N+1)T 0x(N-1) AVRH Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-03984 Rev. *D Page 160 of 182 S6E2D3 Series ◼ Total error: A difference between actual value and theoretical value. The overall error includes zero-transition voltage, full-scale transition voltage and linearity error. Total error 0xFFF VFST’=1.5LSB’ 0xFFE Actual conversion characteristics Digital output 0xFFD {1LSB’ x (N-1) + 0.5 LSB’} 0x004 VNT (Actually-measured value) 0x003 Actual conversion characteristics 0x002 Ideal characterisics 0x001 VZT’=0.5LSB’ AVRL AVRH Analog input Total error of digital output N = 1 LSB’ (ideal value) = VNT – {1 LSB’ X (N-1) + 0.5 LSB’} 1 LSB’ AVRH – AVRL 4096 VZT’ (ideal value) = AVRL + 0.5 LSB’ [V] VFST’ (ideal value) = AVRH - 1.5 LSB’ [V] [LSB] [V] VNT’: A voltage for causing transition of digital output from (N-1) to N Document Number: 002-03984 Rev. *D Page 161 of 182 S6E2D3 Series 12.6 USB Characteristics (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Input characteristi cs Output characteristi cs Input H level voltage Input L level voltage Differential input sensitivity Different common mode range Symbol Pin Name Conditions VIH VIL VDI - VCM - Output H level voltage VOH Output L level voltage VOL Crossover voltage Rising time Falling time Rising/falling time matching Output impedance VCRS tFR tFF tFRFM ZDRV Rising time Falling time Rising/falling time matching tLR tLF UDP0/ UDM0 External pullup resistance = 15kΩ External pullup resistance = 15kΩ Full-Speed Full-Speed Full-Speed Full-Speed tLRFM Low-Speed Low-Speed Low-Speed Value Min Max 2.0 VCC + 0.3 VSS - 0.3 0.8 0.2 - Unit Remarks V V V *1 *1 *2 0.8 2.5 V *2 2.8 3.6 V *3 0.0 0.3 V *3 1.3 4 4 90 28 2.0 20 20 111.11 44 V ns ns % Ω *4 *5 *5 *5 *6 75 75 80 300 300 125 ns ns % *7 *7 *7 *1: The switching threshold voltage of Single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. *2: Use differential-Receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Minimum differential input sensitivity [V] Above voltage range is the common mode input voltage range. Common mode input voltage [V] *3: The output drive capability of the driver is below 0.3 V at Low-state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 15 kΩ load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V. Document Number: 002-03984 Rev. *D Page 162 of 182 S6E2D3 Series D+ Max 2.0 V Min 1.3 V D- VCRS specified range *5: They indicate Rising time (tFR) and Falling time (tFF) of the Full-speed differential data signal. They are defined by the time between 10 % and 90 % of the output signal voltage. For Full-speed buffer, tFR/tFF ratio is regulated as within ± 10 % to minimize RFI emission. D+ 90% D- 90% 10% 10% tFR Rising time tFF Falling time Full-speed Buffer Rs=27Ω TxD+ CL=50pF Rs=27Ω TxDCL=50pF 3-State Enable Document Number: 002-03984 Rev. *D Page 163 of 182 S6E2D3 Series *6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15 % characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25 Ω to 30 Ω Series resistor of 27 Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7: They indicate rising time (tLR) and Falling time (tLF) of the Low-speed differential data signal. They are defined by the time between 10 % and 90 % of the output signal voltage. D+ 90% D- 90% 10% 10% tLR Rising time tLF Falling time Note: − See Low-speed load (Compliance load) for conditions of external load. Document Number: 002-03984 Rev. *D Page 164 of 182 S6E2D3 Series ◼ Low-speed load (Upstream port load) - Reference 1 CL = 50pF to 150pF CL = 50pF to 150pF ◼ Low-speed load (Downstream port load) - Reference 2 CL = 200pF to 600pF CL = 200pF to 600pF ◼ Low-speed load (Compliance load) CL = 200pF to 450pF CL = 200pF to 450pF Document Number: 002-03984 Rev. *D Page 165 of 182 S6E2D3 Series 12.7 Low-Voltage Detection Characteristics 12.7.1 Low-Voltage Detection Reset Parameter Min Value Typ Max - 2.46 2.55 2.64 V - 2.51 2.60 2.69 V Min Value Typ Max 2.80 2.90 3.00 V 2.90 3.00 3.11 V 2.99 3.10 3.21 V 3.09 3.20 3.31 V 3.18 3.30 3.42 V 3.28 3.40 3.52 V - - Symbol Conditions Detected voltage VDL Released voltage VDH Unit Remarks When voltage drops When voltage rises 12.7.2 Interrupt of Low-Voltage Detection Parameter Symbol Detected voltage VDL Released voltage VDH Detected voltage VDL Conditions Unit SVHI = 00111 SVHI = 00100 Released voltage VDH Detected voltage VDL SVHI = 01100 Released voltage VDH LVD stabilization wait time tLVDW - 4800×tCYCP * Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises μs *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-03984 Rev. *D Page 166 of 182 S6E2D3 Series 12.8 MainFlash Memory Write/Erase Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Sector erase time Unit Typ Max Large Sector - 0.7 3.7 s Small Sector - 0.3 1.1 s - 12 Write cycles ≤ 100 times Half word (16bit) write time Value Min Write cycles > 100 times Chip erase time 100 6.6 31 Includes write time prior to internal erase μs Not including system-level overhead time s Includes write time prior to internal erase 200 - Remarks Write Cycles and Data Hold Time Erase/Write Cycles (cycle) Data Hold Time (year) 1,000 20* 10,000 10* 100,000 5* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C) . 12.9 VFLASH Memory Write/Erase Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Min Value Typ Max Unit Sector erase time (4 KB) - 50 450 ms Block Erase Time (64 KB) - 500 2000 ms Page Program Time - 0.7 3 ms Chip erase time - 11.2 64 s Remarks Erase Endurance Parameter Erase per sector Value Min Typ Max 100k - - Unit Remarks cycle *: Data retention of 20 years is based on 1k erase cycle or less. Document Number: 002-03984 Rev. *D Page 167 of 182 S6E2D3 Series 12.10 Standby Recovery Time 12.10.1 Recovery Cause: Interrupt/WKUP The time from recovery cause reception of the internal circuit to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Value Symbol Sleep mode High-speed CR Timer mode Main Timer mode PLL Timer mode Unit Max* Typ HCLK×1 μs 40 80 μs Low-speed CR timer mode 450 900 μs Sub timer mode 896 1136 μs 316 581 μs 270 540 μs 365 667 μs 365 667 μs RTC mode Stop mode (High-speed CR /Main/PLL run mode return) RTC mode Stop mode (Low-speed CR/sub run mode return) tICNT Deep standby RTC mode Deep standby Stop mode Remarks without RAM retention with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of standby recovery operation (when in external interrupt recovery*) Ext.INT Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-03984 Rev. *D Page 168 of 182 S6E2D3 Series Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*) Internal Resource INT Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: The return factor from each low power consumption modes in “FM4 Family Peripheral Manual Main Part (002-04856). − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode" in "FM4 Family Peripheral Manual Main part (002-04856). Document Number: 002-03984 Rev. *D Page 169 of 182 S6E2D3 Series 12.10.2 Recovery Cause: Reset The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Typ 155 Sleep mode High-speed CR Timer mode Main Timer mode PLL Timer mode Low-speed CR timer mode Sub timer mode tRCNT RTC mode Stop mode Deep standby RTC mode Deep standby Stop mode Value Max* 266 Unit Remarks μs 155 266 μs 315 567 μs 315 567 μs 315 567 μs 336 667 μs 336 667 μs without RAM retention with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in INITX Recovery) INITX Internal RST RST Active Release tRCNT CPU Operation Document Number: 002-03984 Rev. *D Start Page 170 of 182 S6E2D3 Series Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*) Internal Resource RST Internal RST RST Active Release tRCNT CPU Operation Start *: Depending on the Low-Power consumption mode, the reset issue from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each low power consumption mode. See Chapter 6: The return factor from each low power consumption modes in “FM4 Family Peripheral Manual Main Part (002-04856). − The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family Peripheral Manual Main Part (002-04856) − When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-on Reset Timing. − In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock, they need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock. − Internal resource reset indicates Watchdog reset and CSV reset. Document Number: 002-03984 Rev. *D Page 171 of 182 S6E2D3 Series 13. Ordering Information Part Number Package S6E2D35G0AGV20000 Plastic・LQFP (0.5 mm pitch), 120 pin (LQM120) S6E2D35J0AGV2000A Plastic・LQFP (0.5 mm pitch), 176 pin (LQP176) S6E2D35G0AGB3000A Plastic・FBGA (0.5 mm pitch), 161 pin (FDJ161) Document Number: 002-03984 Rev. *D Page 172 of 182 S6E2D3 Series 14. Package Dimensions Package Type Package Code LQFP 120 LQM 120 4 D 5 7 D1 90 61 91 61 60 90 91 60 E1 E 4 5 7 3 6 31 120 1 31 30 e b 0.20 C A-B D 30 2 5 7 0.10 3 0.08 1 C A-B D C A-B D BOTTOM VIEW 8 TOP VIEW 2 A 9 c θ A A' 0.08 C SEATI N G PLA N E 0.25 A1 10 b SECTION A -A' L SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. 0.05 0.15 A A1 1. 70 b 0.17 c 0.115 0.22 D 18.00 BSC D1 16.00 BSC e 0.50 BSC E 18.00 BSC E1 L θ 0.27 0.195 16.00 BSC 0.45 0.60 0° 0.75 8° 002-16172 ** PACKAGE OUTLINE, 120 LEAD LQFP 18.0X18.0X1.7 M M LQM 120 REV** Document Number: 002-03984 Rev. *D Page 173 of 182 S6E2D3 Series Package Type Package Code LQFP 176 LQP 176 D D1 132 4 5 7 89 133 89 88 132 133 88 E1 E 5 7 4 3 6 176 45 1 176 45 44 44 1 2 5 7 e 3 BOTTOM VIEW 0.10 C A-B D 0.20 C A-B D b 0.08 C A-B D 8 TOP VIEW 2 A A A' 0.08 C SIDE VIEW SYM BOL NOM . M AX. 0.05 0.15 L1 0.25 A1 10 L c b SECTION A-A' 1.70 b 0.17 c 0.09 0.22 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 0.27 0.20 D 24.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ SEA TIN G PLAN E DIM ENSIONS M IN. A A1 9 θ 0° 8° 002-15150 ** PACKAGE OUTLINE, 176 LEAD LQFP 24.0X24.0X1.7 M M LQP176 REV** Document Number: 002-03984 Rev. *D Page 174 of 182 S6E2D3 Series Package Type Package Code FBGA 161 FDJ 161 D D1 A eD 0.08 C 13 2X 12 eE 7 11 10 SE 9 8 E E1 7 6 5 4 3 2 1 N INDEX M ARK 8 PIN A1 CORNER M L K J H G F E D B 161xφb 0.08 C 6 2X TOP VIEW C B A 7 SD 0.15 0.05 C A B C BOTTOM VIEW DETAIL A 0.20 C A1 A 0.08 C C SIDE VIEW DETAIL A NOTES DIM ENSIONS SYM BOL M IN. NOM . A A1 0.20 D 0.25 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 1.20 2. DIM ENSIONS AND TOLERANCES M ETHODS PER ASM E Y14.5-2009 . THIS OUTLINE CON FORM S TO JEP95, SECTION 4.5. 0.30 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010 . 4. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 8.00 BSC E 8.00 BSC D1 6.00 BSC E1 6.00 BSC MD 13 ME 13 n Φb M AX. 5. SYM BOL "M D" IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION. SYM BOL "M E" IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. n IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX SIZE M D X M E. 6. DIM ENSION "b " IS M EASURED AT THE M AXIM UM BALL DIAM ETER IN A PLANE PARALLEL TO DATUM C. 161 0.25 0.30 eD 0.50 BSC eE 0.50 BSC SD / SE 0.00 0.35 7. "SD" AND "SE" ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . W HEN THERE IS AN ODD NUM BER OF SOLDER BALLS IN THE OUTER ROW , "SD" OR "SE"= 0. W HEN THERE IS AN EVEN NUM BER OF SOLDER BALLS IN THE OUTER ROW , "SD" = eD/2 AND "SE" = eE/2. 8. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK. M ETALLIZED M ARK INDEN TATION OR OTHER M EANS. 9. "+ " INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10. JEDEC SPECIFICATION NO. REF: N/A. 002-16413 ** PACKAGE OUTLINE, 161 BALL FBGA 8.00X8.00X1.20 M M FDJ161 REV** Document Number: 002-03984 Rev. *D Page 175 of 182 S6E2D3 Series Package Type Package Code Ex-LQFP 120 LEM 120 002-12611 *A Document Number: 002-03984 Rev. *D Page 176 of 182 S6E2D3 Series 15. Errata This chapter describes the errata for S6E2D3 series. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. 15.1 Part Numbers Affected Part Number S6E2D35J0AGV20000, S6E2D35J0AGV2000A 15.2 Qualification Status Product Status: In Production 15.3 Errata Summary This table defines the errata applicability to available devices. Items Part Number Silicon Revision Fix Status SDRAM cannot be used as destination buffer of the GDC Refer to 15.1 Rev A No silicon fix planned. Workaround required. SDRAM cannot be used as destination buffer of the GDC 1. PROBLEM DEFINITION Unnecessary data is written on the before and after the correct addresses if the GDC writes data to the external SDRAM, the CPU’s internal SRAM0, SRAM2, or any memory devices connected to the External Bus Interface. 2. PARAMETERS AFFECTED N/A 3. TRIGGER CONDITION(S) The GDC generates either write data that is NOT size of multiples of 8 bytes multiplied by Burst Length or write address that is NOT aligned with 8 bytes multiplied by Burst Length to the external SDRAM, the CPU's internal SRAM0, SRAM2, or any memory devices connected to the External Bus Interface. The Burst Length means length of write burst transaction, and you can set it as 2 (16 bytes), or 4 (32 bytes). 4. SCOPE OF IMPACT The external SDRAM, the CPU’s internal SRAM0, SRAM2, or any memory devices connected to the External Bus Interface cannot be used as destination buffer of the GDC. Document Number: 002-03984 Rev. *D Page 177 of 182 S6E2D3 Series 5. WORKAROUND Keep Write data size and Base address according as following table when the GDC writes to the external SDRAM, the CPU’s internal SRAM0, SRAM2 or any memory devices connected to the External Bus Interface. Burst Length for write access Write data size 2 Multiples of 16 bytes 16 bytes aligned address. E.g. 0xB000_0010, 0xB000_0020. 4 Multiples of 32 bytes 32 bytes aligned address. E.g. 0xB000_0020, 0xB000_0040. Base address alignment for write data 6. FIX STATUS There is no fix planned. The workaround listed above should be used. Document Number: 002-03984 Rev. *D Page 178 of 182 S6E2D3 Series 16. Major Changes Spansion Publication Number: DS709-00023 Page Section Revision 0.1 Revision 1.0 1, 3 Title 13, 14 3. Product Lineup 15 4. Packages 176 15. Ordering Information Change Results Initial release Deleted the following products. S6E2D35JAA/ S6E2D35GAA Added the following description: 6 2. Features External Bus Interface ◼ Maximum area size : Up to 256 Mbytes ◼ Modified the following description: ◼ 0x6000_0000 to 0xDFFF_FFFF to 0x6000_0000 to 0x7FFF_FFFF 2. Features 4. Packages 5. Pin Assignment 6. Pin Descriptions 14.2. Recommended Operating 15. Ordering Information 7. I/O Circuit Type 7. I/O Circuit Type Modified the ch. Number of I2C ( ch.7→ch.4) 59 7. I/O Circuit Type ◼ Modified theType-Q Remarks 67 10. Block Diagram 68 80 163 12. Memory Map 14.2. Recommended Operating 14.5 12-bit A/D Converter 82 14.2. Recommended Operating 8 15 16 20 to 52 81 176 53 54,55,58 84 to 93 93 95 97 163 170 171 14.3.1 Current Rating 14.3.1 Current Rating Table 14-11 14.4 AC Characteristics 14.4.1 Main Clock Input 14.4 AC Characteristics 14.4.5 Operating Conditions 14.5 12-bit A/D Converter 14.7.2 Interrupt of Low-Voltage Detection 14.9 VFLASH Memory Added the Ex-LQFP(TEQFP)(LEM120) Modified the Type-A Circuit Added the comment in TypeD/E/F/G/N CMOS level output → CMOS level hysteresis input Deleted the following products. ◼ S6E2D35JAA/ S6E2D35GAA Modified the External Device Area / GDC Area Added the AVRL in Analog reference voltage. Modified the TBD in Current Value Added the Note Modified the TBD in Max spec Added the comment of VFLASH memory Added the VFLASH memory current Added the Master clock Modified the I2S PLL frequency (307.2→384) Modified the GDC clock frequency (400→160) Modified the Spec Modified the comment of Conversion time Modified the max value in LVD stabilization wait time. (6000→4800) Added the new Modified the Part Number (S6E2D35G0AGB10000→ 176 15. Ordering Information S6E2D35G0AGB30000) Added the Package (Ex_LQFP) 179, 180 16. Package Dimensions Added the FDJ161/LEM120 NOTE: Please see “Document History” about later revised information. Document Number: 002-03984 Rev. *D Page 179 of 182 S6E2D3 Series Document History Document Title: S6E2D3 Series 32-bit Arm® Cortex®-M4F, FM4 Microcontroller Document Number: 002-03984 Orig. of Submission Change Date Revision ECN Description of Change ** - AKIH 04/21/2015 New Spec. *A 5123103 SHOY 03/04/2016 Added CCS/CCB settings in 7. HandlingDevices (Page58) and Table 1210 Typical…*6,*7 (page 85). Changed PN: S6E2DH5G0AGZ20000 to S6E2DH5G0AGE20000 in 13. Ordering… (Page 172). Changed “GE_SPCSX_0” to “GE_SPCSX0” in 3. PinAssignment (Page 9, 11), 4. PinDescriptions (Page16, 42), 8. BlockDiagram (Page 61) and 12.4.21 GDC: … (Page 154,155) Changed “GE_HBCSX_0” to “GE_HBCSX0” in 3. PinAssignment (Page 9, 11), 4. PinDescriptions (Page 16, 42) , 8. BlockDiagram (Page 61) and 12.4.22 GDC: ... (Page 156,157) Changed “GE_HBCSX_1” to “GE_HBCSX1” in 3. PinAssignment (Page 9, 11), 4. PinDescriptions (Page 14, 42), 8. BlockDiagram (Page 61) and 12.4.22 GDC: … (Page 156,157) Updated VFLASH memory Standby current value to 35uA in Table 12-11 Typical… (Page 86). Changed “Ex_LQFP” to “Ex-LQFP” in 2. Packages (Page 8), 4. Pin Descriptions (Page 13 to 46), 12.2 Recommended… (Page 74) and 13. Ordering… (Page 172). Changed “VMAKEUP” to “VWAKEUP” in 8. BlockDiagram (Page 61). Changed “HW flow control (ch. 4, 5)” to “HW flow control (ch. 4)” in 8. BlockDiagram (Page 61). Added “(N.C.): Do not connect anything” in 3. Pin Assignment (Page 10). Added the Note in 4. Pin Descriptions (Page 46). Added Function of PNL_TSIG in 4. Pin Descriptions (Page 43). Changed “PFBGA” to “FBGA” in 12.2 Recommended… (Page 74) and 13. Ordering… (Page 172). New added errata in 15. Errata (Page 177 to 178). *B 5634638 YSKA 02/21/2016 Changed an explanation from “from 01 to 99” to “from 00 to 99” in RealTime Clock (RTC) (Page 3) of Features. Added an explanation in Notes on Power-on (Page 60) of 7. Handling Devices. Changed “VBAT Power-on Reset” to “Power-on Reset” in List of VBAT Domain Pin Status (Page 71) of 11. Pin Status in Each CPU State, and Added Remark *1. Added Remark *8 in Table 12-10 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT (Page 85). Document Number: 002-03984 Rev. *D Page 180 of 182 S6E2D3 Series Revision ECN Orig. of Submission Change Date Description of Change Changed Parameter “Power supply rising time (tVCCR)” to “Power ramp rate (dV/dt)” in 12.4.8 Power-on Reset Timing (Page 92), Changed the minimum to 0.6mV/μs, Changed the maximum to 1000mV/μs, and Added Remarks and Note. Deleted setting value “SPI=1” and “MS=0” at using chip select in 12.4.12 CSIO Timing, and Added “MS bit = 0” and “MS bit = 1” on the Figure (Page 113 to 120, Page 129 to 136). Deleted following Part Numbers from 13. Ordering Information (Page 172). S6E2D35J0AGV20000, S6E2D35G0AGB30000 Added following Part Numbers to 13. Ordering Information (Page 172). S6E2D35J0AGV2000A, S6E2D35G0AGB3000A Updated figures in 14.Package Dimensions (Page 173 to 176). Added following Part Numbers to 15. Errata (Page 177). S6E2D35J0AGV2000A Deleted Baud rate spec for High-Speed Synchronous Serial in “12.4.12 CSIO Timing”(Page 121-127) *C 6579172 HUAL 05/23/2019 Updated Package Dimensions: Spec 002-12611 – Changed revision from ** to *A. Updated to new template. *D 7156460 XITO 06/14/2021 Deleted following obsolete Part Numbers from 13. Ordering Information (Page 172): S6E2D35GJAMV20000 S6E2D35G0AGE20000 Completing Sunset Review. Document Number: 002-03984 Rev. *D Page 181 of 182 S6E2D3 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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