Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
S6E2G Series
32-bit Arm® Cortex®-M4F
FM4 Microcontroller
S6E2G Series are FM4 devices with up to 180 MHz CPU, 1 MB flash, 192 KB SRAM, 20x communication peripherals, 33x digital
peripherals and 3x analog peripherals. They are designed for industrial automation and metering applications.
Devices in the S6E2G Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is
based on the Arm® Cortex®-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as motor control
timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that are described in
this data sheet are placed into TYPE5-M4 product categories in the "FM4 Family Peripheral Manual Main Part (002-04856)”.
Features
32-bit Arm Cortex-M4F Core
Up
Watch Counter
to 180 MHz frequency operation
External Interrupt Controller Unit
On-chip Memories
Watchdog Timer (Two channels)
Flash
memory: Up to 1024 Kbytes
memory:
• SRAM0: up to 128 Kbytes
• SRAM1: 32 Kbytes
• SRAM2: 32 Kbytes
SRAM
Cyclic Redundancy Check (CRC) Accelerator
SD Card Interface Available on S6E2GM, S6E2GH, and
S6E2GK Devices Only
Direct Memory Access (DMA) Controller (Eight Channels)
Descriptor System Data Transfer Controller (DSTC);
256 channels
Ethernet-MAC Available on S6E2GM, S6E2GK, and
S6E2G2 Devices only
Smartcard Interface (Max 2 channels)
Five Clock Sources
External Bus Interface
USB Interface (Max two channels): Host and Device
Six Reset Sources
CAN Interface (Max one channel) Available on S6E2GM
Clock Supervisor (CSV)
Multi-function Serial Interface (Max 10 Channels)
Six Low-power Consumption Modes
and S6E2GH Devices Only
UART
(Universal Asynchronous Receiver/Transmitter)
Clock Synchronous Serial Interface (CSIO (SPI))
Local Interconnect Network (LIN)
Inter-Integrated Circuit (I2C)
Inter-IC Sound (I2S)
Low-Voltage Detector (LVD)
Sleep
Timer
RTC
Stop
Deep
Deep
Base Timer (Max 16 channels)
standby RTC
standby stop
Peripheral Clock Gating System
General Purpose I/O Port
Up
to 121 high-speed general-purpose I/O ports in 144-pin
package
Up to 153 high-speed general-purpose I/O ports in 176-pin
package
Crypto Assist Function
Debug
Serial
wire JTAG debug port (SWJ-DP)
trace macrocells (ETM) provide comprehensive
debug and trace facilities.
AHB trace macrocells (HTM)
Embedded
Multi-function Timer (Max two units)
Real-Time Clock (RTC)
Analog to Digital Converter (ADC) (Max 32 Channels)
41-bit Unique ID
Dual Timer (32-/16-bit Down Counter)
Wide range voltage: VCC = 2.7 to 5.5 V
Quadrature Position/Revolution Counter (QPRC; Max two
channels)
Cypress Semiconductor Corporation
Document Number: 001-98708 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 24, 2019
S6E2G Series
Ecosystem for Cypress FM4 MCUs
Cypress provides a wealth of data at www.cypress.com to help you to select the right MCU for your design, and to help you to
quickly and effectively integrate the device into your design. Following is an abbreviated list for FM4 MCUs:
Overview: Product Portfolio, Product Roadmap
Product Selectors: FM4 MCUs
Application notes: Cypress offers a large number of FM4
application notes covering a broad range of topics, from
basic to advanced level. Recommended application notes
for getting started with FM4 family of MCUs are:
AN204468 - FM4 I2S USB MP3 Player Application 32-Bit
Microcontroller FM4 Family: This application note
describes the general structure of the I²S USB MP3Player
software example, its single modules in detail and how it is
used.
AN204471 - FM4 S6E2CC Series External Memory
Programmer: This document describes use of the MCU
Universal Programmer as an off-line programmer for Quad
SPI flash memory programming on the S6E2CC Series
SK.
AN203277 - FM 32-Bit Microcontroller Family Hardware
Design Considerations: This application note reviews
several topics for designing a hardware system around
FM0+, FM3, and FM4 family MCUs. Subjects include
power system, reset, crystal, and other pin connections,
and programming and debugging interfaces.
AN202488 - FM4 MB9BF56x and S6E2HG Series MCU Servo Motor Speed Control: This document covers servo
motor speed control solution on FM4 MCU - MB9BF56x
and S6E2HG.
Document Number: 001-98708 Rev. *E
AN99235
- FM4 S6E2HG Series MCU - 16-Bit PWM Using
a Base Timer: Cypress FM4 Family of 32-bit Arm®
Cortex®-M4 Microcontrollers FM4 S6E2H Series Motor
Control Arm® Cortex®-M4 MCU
AN202487 - Differences Among FM0+, FM3, and FM4
32-Bit Microcontrollers: Highlights the peripheral
differences in Cypress’s FM family MCUs. It provides
dedicated sections for each peripheral and contains lists,
tables, and descriptions of peripheral feature and register
differences.
AN204438 - How to Setup Flash Security for FM0+, FM3
and FM4 Families: This application note describes how to
setup the Flash Security for FM0+, FM3, and FM4 devices
Development kits:
FM4-U120-9B560
- Arm® Cortex®-M4 MCU Starter Kit
with USB and CMSIS-DAP
FM4-216-ETHERNET Arm® Cortex®-M4 MCU
Development Kit with Ethernet, CAN and USB Host
FM4-176L-S6E2CC-ETH - Arm® Cortex®-M4 MCU Starter
Kit with Ethernet and USB Host
FM4-176L-S6E2GM - Arm® Cortex®-M4 MCU Pioneer Kit
with Ethernet and USB Host
Peripheral Manuals
Page 2 of 190
S6E2G Series
Table of Contents
1.
S6E2G Series Block Diagram ................................ 4
2.
Product Lineup ....................................................... 5
3.
Package-Dependent Features ............................... 7
4.
Product Features in Detail ..................................... 8
5.
Pin Assignments .................................................. 12
6.
Pin Descriptions ................................................... 14
7.
I/O Circuit Type ..................................................... 54
8.
Handling Precautions .......................................... 63
8.1
Precautions for Product Design ........................... 63
8.2
Precautions for Package Mounting ...................... 64
8.3
Precautions for Use Environment ........................ 66
9.
Handling Devices ................................................. 67
10. Memory Map ......................................................... 70
11. Pin Status in Each CPU State .............................. 74
12. Electrical Characteristics .................................... 84
12.1 Absolute Maximum Ratings ................................. 84
12.2 Recommended Operating Conditions ................. 86
12.3 DC Characteristics .............................................. 91
12.3.1 Current Rating .................................................. 91
12.3.2 Pin Characteristics .......................................... 101
12.4 AC Characteristics ............................................. 103
12.4.1 Main Clock Input Characteristics .................... 103
12.4.2 Sub Clock Input Characteristics ...................... 104
12.4.3 Built-In CR Oscillation Characteristics ............ 104
12.4.4 Operating Conditions of Main PLL (in the Case of
Using Main Clock for Input Clock of PLL) ....... 105
12.4.5 Operating Conditions of USB/Ethernet PLL (in the
Case of Using Main Clock for Input Clock of PLL)
....................................................................... 105
12.4.6 Operating Conditions of Main PLL (in the Case of
Using Built-in High-Speed CR Clock for Input Clock
of Main PLL) ................................................... 106
Document Number: 001-98708 Rev. *E
12.4.7
12.4.8
12.4.9
12.4.10
12.4.11
12.4.12
12.4.13
12.4.14
Reset Input Characteristics ............................. 106
Power-On Reset Timing .................................. 107
GPIO Output Characteristics........................... 107
External Bus Timing ........................................ 108
Base Timer Input Timing ................................. 119
CSIO (SPI) Timing .......................................... 120
External Input Timing ...................................... 153
Quadrature Position/Revolution Counter Timing
........................................................................ 154
12.4.15 I2C Timing ....................................................... 157
12.4.16 SD Card Interface Timing................................ 160
12.4.17 ETM/ HTM Timing ........................................... 162
12.4.18 JTAG Timing ................................................... 164
12.4.19 Ethernet-MAC Timing ..................................... 165
12.4.20 I2S Timing (Multi-function Serial Interface) ...... 170
12.5 12-bit A/D Converter .......................................... 171
12.6 USB Characteristics ........................................... 175
12.7 Low-Voltage Detection Characteristics .............. 179
12.7.1 Low-Voltage Detection Reset.......................... 179
12.7.2 Interrupt of Low-Voltage Detection .................. 179
12.8 MainFlash Memory Write/Erase Characteristics
........................................................................... 180
12.9 Standby Recovery Time .................................... 181
12.9.1 Recovery Cause: Interrupt/WKUP .................. 181
12.9.2 Recovery Cause: Reset .................................. 183
13. Ordering Information .......................................... 185
14. Package Dimensions .......................................... 186
Document History ....................................................... 188
Worldwide Sales and Design Support....................... 190
Page 3 of 190
S6E2G Series
1. S6E2G Series Block Diagram
Document Number: 001-98708 Rev. *E
Page 4 of 190
S6E2G Series
2. Product Lineup
Memory Size
Product Name
S6E2GM6
S6E2GK6
S6E2GH6
S6E2G36
S6E2G26
S6E2GM8
S6E2GK8
S6E2GH8
S6E2G38
S6E2G28
512 Kbytes
1024 Kbytes
SRAM
128 Kbytes
192 Kbytes
SRAM0
64 Kbytes
128 Kbytes
SRAM1
32 Kbytes
32 Kbytes
SRAM2
32 Kbytes
32 Kbytes
Memory Type
On-chip flash
memory
On-chip
Function Availability by Part
Product Name
Description
CPU
S6E2GM6
S6E2GM8
S6E2GK6
S6E2GK8
S6E2GH6
S6E2GH8
S6E2G36
S6E2G38
S6E2G26
S6E2G28
Cortex-M4F, MPU, NVIC 128 ch
Freq.
180 MHz
Power supply voltage
range
2.7 V to 5.5 V
USB2.0 (Device/Host)
2 ch
1 ch. (Max)
MII: 1 ch /
RMII: 1 ch (Max)
Ethernet-MAC
CAN
1 ch (Max)
SD card interface
1ch. (Max)
MII: 1 ch /
RMII: 1 ch (Max)
N/A
N/A
1 ch (Max)
1 unit
N/A
N/A
DMAC
8 ch
DSTC
256 ch
Addr: 25-bit (Max),
Data: 8-/16-bit
CS: 9 (Max),
External bus interface
SRAM,
NOR flash
NAND flash
SDRAM
Multi-function serial
interface
(UART/CSIO(SPI)/LIN/I2C
/I2S)
Document Number: 001-98708 Rev. *E
10ch (Max)
ch 1, ch 4 to ch 7: FIFO,
ch 0, ch 2, ch3, ch 8 to ch 15: No FIFO
ch 1: I2S
Page 5 of 190
S6E2G Series
Product Name
Description
S6E2GM6
S6E2GM8
S6E2GK6
S6E2GK8
MF timer
Base timer
(PWC/Reload
timer/PWM/PPG)
S6E2GH6
S6E2GH8
S6E2G26
S6E2G28
16 ch (Max)
A/D
activation
compare
6 ch
Input
capture
4 ch
Free-run
timer
3 ch
Output
compare
6 ch
Waveform
generator
3 ch
PPG
3 ch
2 units (Max)
Smartcard (ISO7816)
2 ch (Max)
QPRC
2 ch (Max)
Dual timer
1 unit
Real-time clock
1 unit
Watch counter
1 unit
CRC accelerator
Yes (fixed)
Watchdog timer
1 ch (SW) + 1 ch (HW)
External interrupts
32 pins (Max)+ NMI × 1
CSV (clock supervisor)
Yes
LVD (low-voltage
detector)
2 ch
Built-in CR
S6E2G36
S6E2G38
High-speed
4 MHz
Low-speed
100 kHz
Debug function
Unique ID
SWJ-DP/ETM/HTM
Yes
*1: Crypto Assist Function is built in following products.
S6E2GM6HHA, S6E2GM8HHA, S6E2GM6JHA, S6E2GM8JHA
Notes:
−
Because of package pin limitations, not all functions within the device can be brought out to external pins. You must carefully
work out the pin allocation needed for your design.
You must use the port relocate function of the I/O port according to your function use.
−
See 12.4.3 Built-In CR Oscillation Characteristics for the accuracy of the built-in CR.
Document Number: 001-98708 Rev. *E
Page 6 of 190
S6E2G Series
3. Package-Dependent Features
All S6E2G Series of parts are available in both 144-pin LQFP and 176-pin LQFP.
Base Part Number
S6E2G
Description
Package Suffix
H0A
LQFP: (0.5 mm pitch)
I/O Ports
J0A
JHA*
144 pins
176 pins
121 pins (Max)
153 pins (Max)
24 (3 units)
32 ch (3 units)
12-bit ADC converter
Crypto Assist Function
HHA*
—
Yes
—
Yes
*HHA and JHA parts have the Crypto Assist Function built in. HHA and JHA options are not available for the S6E2GH or S6E2G3
parts. The HHA and JHA options are available on the S6E2GM, S6E2GK, and S6E2G2 parts.
Notes:
−
For an explicit list of part numbers and the feature differences among them, see 13. Ordering Information
−
See 14. Package Dimensions for detailed information on each package.
Document Number: 001-98708 Rev. *E
Page 7 of 190
S6E2G Series
4. Product Features in Detail
32-bit Arm Cortex-M4F Core
Up to 180 MHz frequency operation
FPU built-in
Support DSP instructions
Memory protection unit (MPU): improves the reliability of an
embedded system
Integrated nested vectored interrupt controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit system timer (Sys Tick): system timer for OS task
management
On-chip Memories
Flash memory
This series is on-chip flash memories.
Up
to 1024 Kbytes
flash accelerator for zero wait state
Security function for code protection
Built-in
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
and D-code bus of Cortex-M4F core. SRAM1 and SRAM2
are connected to system bus of Cortex-M4F core.
SRAM0:
up to 128 Kbytes
32 Kbytes
SRAM2: 32 Kbytes
SRAM1:
• EndPoint 0 is control transfer
• EndPoint 1,2 can be selected bulk-transfer, interrupttransfer or isochronous-transfer
• EndPoint 3 to 5 can select bulk-transfer or interrupttransfer
EndPoint 1 to 5 comprise double buffer
The size of each endpoint is as follows.
• Endpoint 0, 2 to 5: 64 byte
• EndPoint 1: 256 byte
USB Host
USB2.0
Full-Speed/Low-Speed supported
interrupt-transfer, and isochronoustransfer support
USB Device connected/dis-connected automatically
detect
IN/OUT token handshake packet automatically
Max 256-byte packet length supported
Wake-up function supported
Bulk-transfer,
CAN Interface (Max one channel) Available on
S6E2GM and S6E2GH Devices Only
Compatible with CAN specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32-message buffer
Multi-function Serial Interface (Max 10 Channels)
Separate 64 byte receive and transmit FIFO buffers for
channels 1 and channels 4 to 7.
Operation mode is selectable for each channel from the
following:
UART
CSIO
External Bus Interface
Supports SRAM, NOR, NAND flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-/32-bit data width
Up to 25-bit address bus
Supports address/data multiplexing
Supports external RDY function
Supports scramble function
Possible
to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key
Note: It is necessary to use the Cypress provided software
library to use the scramble function.
USB Interface (Max two channels)
The USB interface is composed of a Device and a Host.
USB Device
USB
Max
2.0 Full-speed supported
6 EndPoint supported
Document Number: 001-98708 Rev. *E
(SPI)
LIN
I2 C
I2 S
UART
Full-duplex
double buffer
with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Selection
CSIO (SPI)
Full-duplex
double buffer
dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch 6 and ch 7 only)
Supports high-speed SPI (ch 4 and ch 6 only)
Data length 5 to 16-bit
Built-in
LIN
LIN
protocol Rev.2.1 supported
double buffer
Master/slave mode supported
LIN break field generation (can change to 13- to 16-bit
length)
Full-duplex
Page 8 of 190
S6E2G Series
LIN
break delimiter generation (can change to 1- to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
I2 C
Standard
mode (Max 100 kbps)/Fast mode (Max 400 kbps)
supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A
and ch 7 = ch B) supported
I2 S
CSIO (SPI) (ch 1 only) and I2S clock generator
Supports two transfer protocol: I2S and MSB-justified
Master mode only
Using
DMA Controller (Eight Channels)
DMA controller has an independent bus, so the CPU and
DMA controller can process simultaneously.
Eight independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Event counter mode (External clock mode)
General Purpose I/O Port
This series can use its pins as general purpose I/O ports
when they are not used for external bus or peripherals;
moreover, the port relocate function is built in. It can set the
I/O port to which the peripheral function can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in port-relocate function
Up to 121 high-speed general-purpose I/O ports in 144-pin
package
Some pins 5 V tolerant I/O.
See 6. Pin Descriptions and 7. I/O Circuit Type for the
corresponding pins.
Transfer address area: 32-bit (4 GB)
Multi-function Timer (Max two units)
Transfer mode: Block transfer/Burst transfer/Demand
The multi-function timer is composed of the following blocks:
Minimum resolution: 5.56 ns
Transfer data type: bytes/half-word/word
16-bit free-run timer × 3 ch/unit
Transfer block count: 1 to 16
Input capture × 4 ch/unit
Number of transfers: 1 to 65536
Output compare × 6 ch/unit
DSTC (Descriptor System Data Transfer Controller;
256 channels)
A/D activation compare × 6 ch/unit
transfer
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the descriptor system and,
following the specified contents of the descriptor that has
already been constructed on the memory, can access directly
the memory/peripheral device and perform the data-transfer
operation.
It supports the software activation, the hardware activation,
and the chain activation functions.
Waveform generator × 3 ch/unit
16-bit PPG timer × 3 ch/unit
The following functions can be used to achieve the motor
control:
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
A/D Converter (Max 32 Channels)
12-bit A/D Converter
DTIF (motor emergency stop) interrupt function
Successive
Real-Time Clock (RTC)
Built-in
The real-time clock can count year, month, day, hour, minute,
second, or day of the week from 00 to 99.
approximation type
three units
Conversion time: 0.5 μs at 5 V
Priority conversion available (priority at two levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for priority conversion: 4 steps)
Interrupt function with specifying date and time
(year/month/day/hour/minute) is available. This function is
also available by specifying only year, month, day, hour, or
minute.
Base Timer (Max 16 channels)
Timer interrupt function after set time or each set time.
Operation mode is selected from the following for each
channel:
Capable of rewriting the time with continuing the time count.
16-bit PWM timer
Document Number: 001-98708 Rev. *E
Leap year automatic count is available.
Page 9 of 190
S6E2G Series
Quadrature Position/Revolution Counter (QPRC;
Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. It is also
possible to use up/down counter.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 generator polynomial: 0x1021
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
The detection edge of the three external event input pins
SD Card Interface Available on S6E2GM, S6E2GH,
and S6E2GK Devices Only
16-bit position counter
It is possible to use the SD card that conforms to the
following standards.
16-bit revolution counter
Part 1 Physical Layer Specification version 3.01
Two 16-bit compare registers
Part E1 SDIO Specification version 3.00
AIN, BIN and ZIN is configurable.
Dual Timer (32-/16-bit Down Counter)
The dual timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the following for each
channel:
Free-running
Periodic (= Reload)
One shot
Watch Counter
The watch counter is used for wake up from low-power
consumption mode. It is possible to select the main clock,
sub clock, built-in High-speed CR clock, or built-in low-speed
CR clock as the clock source.
Interval timer: up to 64 s (max) with a sub clock of 32.768
kHz
Part A2 SD Host Controller Standard Specification version
3.00
1-bit or 4-bit data bus
Ethernet-MAC Available on S6E2GM, S6E2GK, and
S6E2G2 Devices only
Compliant with IEEE802.3 specification
10 Mbps/100 Mbps data transfer rates supported
MII/RMII for external PHY device supported.
MII: Max one channel
RMII: Max one channel
Full-duplex and half-duplex mode supported.
Wake-ON-LAN supported
Built-in dedicated descriptor-system DMAC
Built-in 2 Kbytes transmit FIFO and 2 Kbytes receive FIFO.
Compliant IEEE1558-2008 (PTP)
External Interrupt Controller Unit
Smartcard Interface (Max 2 channels)
External interrupt input pin: Max 32 pins
Compliant with ISO7816-3 specification
Both edges(Rise edge and Fall edge) detect
Include one non-maskable interrupt (NMI)
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs: a "hardware"
watchdog and a "software" watchdog.
The hardware watchdog timer is clocked by low-speed
internal CR oscillator. The hardware watchdog is thus active
in any power saving mode except RTC mode and Stop mode.
Cyclic Redundancy Check (CRC) Accelerator
The CRC accelerator helps to verify data transmission or
storage integrity.
Document Number: 001-98708 Rev. *E
Card Reader only/B class card only
Available protocols
Transmitter:
8E2, 8O2, 8N2
8E1, 8O1, 8N2, 8N1, 9N1
Inverse mode
Receiver:
TX/RX FIFO integrated (RX: 16-bytes, TX:16-bytes)
Clock and Reset
Clocks
Five clock sources (two external oscillators, two internal CR
oscillators, and Main PLL) that are dynamically selectable.
Main
clock: 4 MHz to 48 MHz
clock: 30 kHz to 100 kHz
High-speed internal CR clock: 4 MHz
Low-speed internal CR clock: 100 kHz
Main PLL Clock
Sub
Page 10 of 190
S6E2G Series
Resets
Reset
requests from INITX pin
Power on reset
Software reset
Watchdog timer reset
Low-voltage detector reset
Clock supervisor reset
Clock Supervisor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include two-stage monitoring of voltage on the
VCC pins. When the voltage falls below the voltage that has
been set, the low-voltage detector function generates an
interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-power Consumption Mode
Crypto Assist Function
These features are enabled for the crypto assist function.
The dedicated middleware is necessary for this calculator
operation.
PKA (Public Key Accelerator)
PKA（Public
Key Accelerator）is modular exponentiation
calculation accelerator used of RSA Public Key crypto and
so on.
Available bit length: Up to 2048-bit
AES calculator
AES
(Advanced Encryption Standard) calculator is a AES
common key crypto accelerator which is compliant with
FIPS (Federal Information Processing Standard
Publication)197.
Available key length: 128/192/256-bit
CBC mode and ECB mode support
External Bus Data Scramble
It
enables to scramble input/output data of External Bus
Interface.
Debug
Serial wire JTAG debug port (SWJ-DP)
Embedded trace macrocells (ETM) provide comprehensive
debug and trace facilities.
AHB trace macrocells (HTM)
Six low power consumption modes are supported.
Unique ID
Unique value of the device (41-bit) is set.
Sleep
Timer
RTC
Stop
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
Power Supply
Four power supplies
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral
functions not used.
Document Number: 001-98708 Rev. *E
Wide range voltage:
VCC = 2.7 V to 5.5 V
Power supply for USB ch 0 I/O: USBVCC0
= 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for USB ch 1 I/O: USBVCC1
= 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for Ethernet-MAC I/O: ETHVCC
= 3.0 V to 5.5 V (when Ethernet is used.)
Page 11 of 190
S6E2G Series
5. Pin Assignments
LQS144
Note:
−
Only the GPIO function is shown on GPIO pins. See the table in Pin Descriptions for the full, multiplexed signal name.
Document Number: 001-98708 Rev. *E
Page 12 of 190
S6E2G Series
LQP176
Note:
−
Only the GPIO function is shown on GPIO pins. See the table in Pin Descriptions for the full, multiplexed signal name.
Document Number: 001-98708 Rev. *E
Page 13 of 190
S6E2G Series
6. Pin Descriptions
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin Number
LQFP-176
LQFP-144
1
1
Pin Name
I/O
Circuit
Type
Pin State
Type
VCC
-
-
E
K
E
I
E
I
E
I
E
I
E
K
PA0
RTO00_1
(PPG00_1)
2
TIOA8_0
2
INT00_0
MADATA00_0
IC0_CIN_0
PA1
3
3
RTO01_1
(PPG01_1)
TIOA9_0
MADATA01_0
IC0_DATA_0
PA2
4
4
RTO02_1
(PPG02_1)
TIOA10_0
MADATA02_0
IC0_RST_0
PA3
5
5
RTO03_1
(PPG03_1)
TIOA11_0
MADATA03_0
IC0_VPEN_0
PA4
6
6
RTO04_1
(PPG04_1)
TIOA12_0
MADATA04_0
IC0_VCC_0
PA5
RTO05_1
(PPG05_1)
7
7
TIOA13_0
INT01_0
MADATA05_0
IC0_CLK_0
Document Number: 001-98708 Rev. *E
Page 14 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
E
K
E
K
E
I
E
I
E
I
I
Q
N
I
N
I
E
K
E
I
PA6
8
8
DTTI0X_1
INT00_2
MADATA06_0
PA7
IC00_1
9
9
INT02_2
MADATA07_0
RTCCO_1
SUBOUT_1
P50
10
-
SCS72_0
IC01_1
TIOA8_2
P51
11
-
SCS73_0
IC02_1
TIOB8_2
P52
12
IC03_1
-
TIOA9_2
PA8
SIN7_0
13
10
FRCK0_1
INT02_0
WKUP1
MADATA08_0
PA9
14
11
SOT7_0
(SDA7_0)
AIN1_1
MADATA09_0
PAA
15
12
SCK7_0
(SCL7_0)
BIN1_1
MADATA10_0
PAB
SCS70_0
16
13
ZIN1_1
INT03_0
MADATA11_0
PAC
17
14
SCS71_0
TIOB8_0
MADATA12_0
Document Number: 001-98708 Rev. *E
Page 15 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
N
I
N
I
I
K
E
K
E
K
L
I
E
K
E
I
L
K
L
I
PAD
18
15
SCK3_0
(SCL3_0)
TIOB9_0
MADATA13_0
PAE
ADTG_0
19
16
SOT3_0
(SDA3_0)
TIOB10_0
MADATA14_0
PAF
SIN3_0
20
17
TIOB11_0
INT16_0
MADATA15_0
P08
21
18
TIOB12_0
INT17_0
MDQM0_0
P09
22
19
TIOB13_0
INT18_0
MDQM1_0
P0A
23
20
ADTG_1
MCLKOUT_0
P30
MI2SWS1_1
24
RX0_1
-
TIOB11_2
INT01_2
P31
25
-
MI2SMCK1_1
TX0_1
TIOA12_2
P32
26
21
INT19_0
S_DATA1_0
P33
27
22
FRCK0_0
S_DATA0_0
Document Number: 001-98708 Rev. *E
Page 16 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
L
K
P34
28
IC03_0
23
INT00_1
S_CLK_0
29
24
VCC
-
-
30
25
VSS
-
-
L
K
L
K
L
K
E
I
G
K
G
K
G
K
P35
31
IC02_0
26
INT01_1
S_CMD_0
P36
32
IC01_0
27
INT02_1
S_DATA3_0
P37
33
IC00_0
28
INT03_1
S_DATA2_0
P38
34
ADTG_2
29
DTTI0X_0
S_WP_0
P39
RTO00_0
(PPG00_0)
35
TIOA0_1
30
AIN1_0
INT16_1
S_CD_0
MAD24_0
P3A
RTO01_0
(PPG01_0)
36
TIOA1_1
31
BIN1_0
INT17_1
MAD23_0
P3B
RTO02_0
(PPG02_0)
37
TIOA2_1
32
ZIN1_0
INT18_1
MAD22_0
Document Number: 001-98708 Rev. *E
Page 17 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
G
K
G
I
G
I
E
K
E
I
E
I
P3C
SIN2_1
38
33
RTO03_0
(PPG03_0)
TIOA3_1
INT19_1
MAD21_0
P3D
SOT2_1
(SDA2_1)
39
34
RTO04_0
(PPG04_0)
TIOA4_1
MAD20_0
P3E
SCK2_1
(SCL2_1)
40
35
RTO05_0
(PPG05_0)
TIOA5_1
MAD19_0
P5D
SIN1_1
41
-
MI2SDI1_1
TIOB12_2
INT03_2
P5E
42
-
SOT1_1
(SDA1_1)
MI2SDO1_1
TIOA13_2
P5F
43
-
SCK1_1
(SCL1_1)
MI2SCK1_1
TIOB13_2
44
36
VSS
-
-
45
37
VCC
-
-
G
K
P40
SIN7_1
46
38
RTO10_0
(PPG10_0)
TIOA0_0
AIN0_0
INT23_0
MCSX7_0
Document Number: 001-98708 Rev. *E
Page 18 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
G
I
G
I
G
K
G
I
G
I
P41
SOT7_1
(SDA7_1)
47
39
RTO11_0
(PPG11_0)
TIOA1_0
BIN0_0
MCSX6_0
P42
SCK7_1
(SCL7_1)
48
40
RTO12_0
(PPG12_0)
TIOA2_0
ZIN0_0
MCSX5_0
P43
SCS70_1
49
41
RTO13_0
(PPG13_0)
TIOA3_0
INT04_0
MCSX4_0
P44
SCS71_1
50
42
RTO14_0
(PPG14_0)
TIOA4_0
MCSX3_0
P45
SCS72_1
51
43
RTO15_0
(PPG15_0)
TIOA5_0
MCSX2_0
52
44
C
-
-
53
45
VSS
-
-
54
46
VCC
-
-
D
S
D
T
B
C
55
47
56
48
57
49
Document Number: 001-98708 Rev. *E
P46
X0A
P47
X1A
INITX
Page 19 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
E
K
E
K
L
K
L
I
L
I
L
K
L
K
L
K
PF0
SCS73_1
58
RX0_2
-
TIOA15_1
INT22_1
PF1
59
-
TX0_2
TIOB15_1
INT23_1
P48
SIN1_0
60
50
MI2SDI1_0
DTTI1X_0
INT06_0
MRASX_0
P49
61
51
SOT1_0
(SDA1_0)
MI2SDO1_0
IC10_0
MCASX_0
P4A
62
52
SCK1_0
(SCL1_0)
MI2SCK1_0
IC11_0
MSDWEX_0
P4B
MI2SWS1_0
63
53
IC12_0
INT04_2
MCSX8_0
P4C
MI2SMCK1_0
64
54
IC13_0
INT05_2
MSDCKE_0
P4D
65
55
FRCK1_0
INT07_0
MSDCLK_0
Document Number: 001-98708 Rev. *E
Page 20 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
L
Q
L
I
I
K
E
I
E
K
E
I
E
I
E
K
L
I
P4E
66
56
SCK9_0
(SCL9_0)
INT05_0
WKUP2
MCSX1_0
P70
ADTG_7
67
57
SOT9_0
(SDA9_0)
MCSX0_0
P71
ADTG_8
68
58
SIN9_0
INT04_1
MRDY_0
P72
69
TIOB0_0
59
INT06_2
MAD00_0
P73
SIN8_0
70
60
TIOB1_0
INT20_0
MAD01_0
P74
71
61
SOT8_0
(SDA8_0)
TIOB2_0
MAD02_0
P75
72
62
SCK8_0
(SCL8_0)
TIOB3_0
MAD03_0
P76
SIN6_0
73
63
TIOB4_0
INT21_0
MAD04_0
P77
74
64
SOT6_0
(SDA6_0)
TIOB5_0
MAD05_0
Document Number: 001-98708 Rev. *E
Page 21 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
L
I
E
K
E
K
E
I
E
K
E
K
E
K
E
K
P78
75
65
SCK6_0
(SCL6_0)
AIN0_1
MAD06_0
P79
SCS60_0
76
66
BIN0_1
INT22_0
MAD07_0
P7A
SCS61_0
77
67
ZIN0_1
INT07_2
MAD08_0
PF2
SCS62_0
78
-
DTTI1X_1
TIOA6_1
IC1_CLK_1
PF3
SCS63_0
79
-
FRCK1_1
TIOB6_1
INT05_1
IC1_VCC_1
PF4
IC10_1
80
TIOA7_1
-
INT06_1
IC1_VPEN_1
PF5
SIN3_1
81
IC11_1
-
TIOB7_1
INT07_1
IC1_RST_1
PF6
SOT3_1
(SDA3_1)
82
IC12_1
-
TIOA14_1
INT20_1
IC1_DATA_1
Document Number: 001-98708 Rev. *E
Page 22 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
I/O
Circuit
Type
Pin State
Type
E
K
C
E
J
D
A
A
A
B
VSS
-
-
Pin Name
PF7
SCK3_1
(SCL3_1)
83
IC13_1
-
TIOB14_1
INT21_1
IC1_CIN_1
84
68
85
69
PE0
MD1
MD0
PE2
86
70
87
71
88
72
89
73
VCC
-
-
90
74
AVCC
-
-
91
75
AVSS
-
-
92
76
AVRL
-
-
93
77
AVRH
-
-
F
M
F
L
F
L
F
M
X0
PE3
X1
P10
AN00
94
TIOA0_2
78
INT08_0
MNREX_0
IC1_CLK_0
P11
AN01
95
79
TIOB0_2
MNWEX_0
IC1_VCC_0
P12
AN02
96
80
TIOA1_2
MNCLE_0
IC1_VPEN_0
P13
AN03
SIN9_1
97
81
TIOB1_2
INT25_1
MNALE_0
IC1_RST_0
Document Number: 001-98708 Rev. *E
Page 23 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
F
N
F
N
F
O
F
N
F
N
F
O
F
O
P14
AN04
98
82
SOT9_1
(SDA9_1)
TIOA2_2
IC1_DATA_0
TRACED0
P15
AN05
99
83
SCK9_1
(SCL9_1)
TIOB2_2
IC1_CIN_0
TRACED1
P16
AN06
100
SIN6_1
84
RX0_0
INT09_0
TRACED2
P17
AN07
101
85
SOT6_1
(SDA6_1)
TX0_0
TRACED3
PB0
AN16
102
-
SCK6_1
(SCL6_1)
TIOA9_1
TRACED8
PB1
AN17
SCS60_1
103
TIOB9_1
-
AIN0_2
INT08_1
TRACED9
PB2
AN18
SCS61_1
104
-
TIOA10_1
BIN0_2
INT09_1
TRACED10
Document Number: 001-98708 Rev. *E
Page 24 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
F
N
F
O
F
O
F
N
F
O
F
O
F
O
PB3
AN19
105
-
SCS62_1
TIOB10_1
ZIN0_2
TRACED11
P18
AN08
106
SIN2_0
86
TIOA3_2
INT10_0
TRACED4
P19
AN09
107
87
SOT2_0
(SDA2_0)
TIOB3_2
INT24_1
TRACED5
P1A
AN10
108
88
SCK2_0
(SCL2_0)
TIOA4_2
TRACED6
P1B
AN11
109
89
TIOB4_2
INT11_0
TRACED7
PB4
AN20
110
-
SCS63_1
TIOA11_1
INT10_1
TRACED12
PB5
AN21
SIN8_1
111
-
TIOB11_1
AIN1_2
INT11_1
TRACED13
Document Number: 001-98708 Rev. *E
Page 25 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
F
N
F
N
F
N
F
L
F
M
F
M
F
M
PB6
AN22
112
-
SOT8_1
(SDA8_1)
TIOA12_1
BIN1_2
TRACED14
PB7
AN23
113
-
SCK8_1
(SCL8_1)
TIOB12_1
ZIN1_2
TRACED15
P1C
AN12
114
90
SCK0_1
(SCL0_1)
TIOA5_2
TRACECLK
P1D
AN13
115
91
SOT0_1
(SDA0_1)
TIOB5_2
MAD09_0
P1E
AN14
116
SIN0_1
92
TIOA8_1
INT26_1
MAD10_0
P1F
AN15
117
RTS5_0
93
TIOB8_1
INT27_1
MAD11_0
P2A
AN24
118
94
CTS5_0
INT08_2
MAD12_0
Document Number: 001-98708 Rev. *E
Page 26 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
F
M
F
M
F
M
E
M
F
M
F
L
F
L
E
M
P29
AN25
119
95
SCK5_0
(SCL5_0)
INT09_2
MAD13_0
P28
AN26
120
96
SOT5_0
(SDA5_0)
INT10_2
MAD14_0
P27
AN27
121
97
SIN5_0
INT24_0
MAD15_0
P26
ADTG_6
122
98
TIOA6_2
INT11_2
MAD16_0
P25
AN28
123
99
TIOB6_2
INT25_0
MAD17_0
P24
124
100
AN29
TIOA13_1
MAD18_0
P23
UHCONX1
125
101
AN30
SCK0_0
(SCL0_0)
TIOB13_1
P22
AN31
126
102
SOT0_0
(SDA0_0)
INT26_0
Document Number: 001-98708 Rev. *E
Page 27 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
I
K
I
F
-
-
H
R
H
R
P21
ADTG_4
127
103
SIN0_0
INT27_0
CROUT_0
P20
128
104
NMIX
129
105
USBVCC1
WKUP0
P82
130
106
131
107
132
108
VSS
-
-
133
109
VCC
-
-
134
110
E
G
135
111
E
G
E
G
E
G
E
G
E
K
E
K
UDM1
P83
UDP1
P00
TRSTX
P01
TCK
SWCLK
136
112
137
113
P02
TDI
P03
TMS
SWDIO
P04
138
114
TDO
SWO
P90
139
RTO10_1
(PPG10_1)
-
TIOB0_1
INT12_1
IC0_CLK_1
P91
SIN5_1
140
-
RTO11_1
(PPG11_1)
TIOB1_1
INT13_1
IC0_VCC_1
Document Number: 001-98708 Rev. *E
Page 28 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
E
K
E
K
E
I
E
I
K
V
K
V
K
V
K
V
K
V
K
V
P92
SOT5_1
(SDA5_1)
141
-
RTO12_1
(PPG12_1)
TIOB2_1
INT14_1
IC0_VPEN_1
P93
SCK5_1
(SCL5_1)
142
-
RTO13_1
(PPG13_1)
TIOB3_1
INT15_1
IC0_RST_1
P94
CTS5_1
143
-
RTO14_1
(PPG14_1)
TIOB4_1
IC0_DATA_1
P95
RTS5_1
144
-
RTO15_1
(PPG15_1)
TIOB5_1
IC0_CIN_1
145
PC0
115
E_RXER
PC1
146
116
TIOB6_0
E_RX03
PC2
147
117
TIOA6_0
E_RX02
PC3
148
118
TIOB7_0
E_RX01
PC4
149
119
TIOA7_0
E_RX00
PC5
150
120
TIOB14_0
E_RXDV
Document Number: 001-98708 Rev. *E
Page 29 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
I/O
Circuit
Type
Pin State
Type
K
V
E
W
K
V
K
V
K
V
ETHVCC
-
-
VSS
-
-
L
W
K
V
L
W
L
W
L
W
L
W
L
W
L
V
Pin Name
PC6
151
121
TIOA14_0
E_MDIO
PC7
152
INT13_0
122
E_MDC
CROUT_1
153
123
PC8
E_RXCK_REFCK
PC9
154
124
TIOB15_0
E_COL
PCA
155
125
TIOA15_0
E_CRS
156
126
157
127
PCB
158
128
INT28_0
E_COUT
159
PCC
129
E_TCK
PCD
160
130
SOT4_1
(SDA4_1)
INT14_0
E_TXER
PCE
161
131
SIN4_1
INT15_0
E_TX03
PCF
162
132
RTS4_1
INT12_0
E_TX02
PD0
163
133
INT30_1
E_TX01
PD1
164
134
INT31_1
E_TX00
PD2
165
135
CTS4_1
E_TXEN
Document Number: 001-98708 Rev. *E
Page 30 of 190
S6E2G Series
Pin Number
LQFP-176
LQFP-144
Pin Name
I/O
Circuit
Type
Pin State
Type
E
W
E
K
I
K
L
K
L
I
L
I
I
Q
-
-
H
R
H
R
-
-
P6E
ADTG_5
166
136
SCK4_1
(SCL4_1)
INT29_0
E_PPS
167
-
168
-
P65
INT28_1
P64
CTS4_0
INT29_1
P63
ADTG_3
169
137
RTS4_0
INT30_0
MOEX_0
P62
170
138
SCK4_0
(SCL4_0)
TIOB7_2
MWEX_0
P61
UHCONX0
171
139
SOT4_0
(SDA4_0)
TIOA7_2
MALE_0
RTCCO_0
SUBOUT_0
P60
172
SIN4_0
140
INT31_0
WKUP3
173
141
174
142
175
143
176
144
USBVCC0
Document Number: 001-98708 Rev. *E
P80
UDM0
P81
UDP0
VSS
Page 31 of 190
S6E2G Series
Signal Descriptions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin Number
Module
Pin Name
Function
LQFP 176
LQFP 144
ADTG_0
19
16
ADTG_1
23
ADTG_2
34
29
ADTG_3
169
137
ADTG_4
A/D
converter
A/D converter external trigger input pin
20
127
103
ADTG_5
166
136
ADTG_6
122
98
ADTG_7
67
57
ADTG_8
68
58
AN00
94
78
AN01
95
79
AN02
96
80
AN03
97
81
AN04
98
82
AN05
99
83
AN06
100
84
AN07
101
85
AN08
106
86
AN09
107
87
AN10
108
88
AN11
109
89
AN12
114
90
AN13
115
91
AN14
116
92
AN15
A/D converter analog input pin.
117
93
AN16
ANxx describes A/D converter ch xx.
102
-
AN17
103
-
AN18
104
-
AN19
105
-
AN20
110
-
AN21
111
-
AN22
112
-
AN23
113
-
AN24
118
94
AN25
119
95
AN26
120
96
AN27
121
97
AN28
123
99
AN29
124
100
AN30
125
101
AN31
126
102
Document Number: 001-98708 Rev. *E
Page 32 of 190
S6E2G Series
Module
Pin Name
Function
TIOA0_0
TIOA0_1
Base Timer
0
Base Timer ch 0 TIOA pin
35
30
TIOA0_2
94
78
TIOB0_0
69
59
TIOB0_1
Base Timer ch 0 TIOB pin
TIOB0_2
TIOA1_0
TIOA1_1
Base Timer
1
Base Timer ch 1 TIOA pin
TIOA1_2
TIOB1_0
39
36
31
96
80
TIOB1_2
97
81
TIOA2_0
48
40
Base Timer ch 2 TIOA pin
37
32
TIOA2_2
98
82
TIOB2_0
71
61
Base Timer ch 2 TIOB pin
TIOA3_0
TIOA3_1
Base Timer ch 3 TIOA pin
TIOA3_2
TIOB3_0
141
-
99
83
49
41
38
33
106
86
72
62
142
-
TIOB3_2
107
87
TIOA4_0
50
42
39
34
TIOA4_2
108
88
TIOB4_0
73
63
TIOB3_1
TIOA4_1
TIOB4_1
Base Timer ch 3 TIOB pin
Base Timer ch 4 TIOA pin
Base Timer ch 4 TIOB pin
TIOB4_2
TIOA5_0
TIOA5_1
Base Timer ch 5 TIOA pin
TIOA5_2
TIOB5_0
TIOB5_1
Base Timer ch 5 TIOB pin
143
-
109
89
51
43
40
35
114
90
74
64
144
-
TIOB5_2
115
91
TIOA6_0
147
117
78
-
TIOA6_1
Base Timer
6
47
-
Base Timer ch 1 TIOB pin
TIOB2_2
Base Timer
5
79
60
TIOB2_1
Base Timer
4
-
95
70
TIOA2_1
Base Timer
3
139
140
TIOB1_1
Base Timer
2
Pin Number
LQFP 176
LQFP 144
46
38
Base Timer ch 6 TIOA pin
TIOA6_2
122
98
TIOB6_0
146
116
TIOB6_1
Base Timer ch 6 TIOB pin
TIOB6_2
Document Number: 001-98708 Rev. *E
79
-
123
99
Page 33 of 190
S6E2G Series
Module
Pin Name
Function
TIOA7_0
TIOA7_1
Base Timer
7
Base Timer ch 7 TIOA pin
80
-
TIOA7_2
171
139
TIOB7_0
148
118
TIOB7_1
Base Timer ch 7 TIOB pin
TIOB7_2
TIOA8_0
TIOA8_1
Base Timer
8
TIOB8_0
10
-
17
14
117
93
3
102
-
TIOA9_1
Base Timer ch 9 TIOA pin
TIOA9_2
12
-
TIOB9_0
18
15
TIOA10_1
TIOB10_0
TIOA11_1
Base Timer ch 9 TIOB pin
Base Timer ch 10 TIOA pin
Base Timer ch 10 TIOB pin
Base Timer ch 11 TIOA pin
TIOB11_0
TIOB11_1
Base Timer ch 11 TIOB pin
TIOB11_2
TIOA12_0
TIOA12_1
Base Timer ch 12 TIOA pin
103
-
4
4
104
-
19
16
105
-
5
5
110
-
20
17
111
-
24
-
6
6
112
-
TIOA12_2
25
-
TIOB12_0
21
18
113
-
TIOB12_1
Base Timer ch 12 TIOB pin
TIOB12_2
41
-
TIOA13_0
7
7
124
100
42
-
TIOA13_1
Base Timer ch 13 TIOA pin
TIOA13_2
TIOB13_0
TIOB13_1
Base Timer ch 13 TIOB pin
TIOB13_2
TIOA14_0
Base Timer
14
2
92
3
TIOA11_0
Base Timer
13
2
116
11
TIOB10_1
Base Timer
12
138
TIOA9_0
TIOA10_0
Base Timer
11
Base Timer ch 8 TIOB pin
81
170
TIOB8_2
TIOB9_1
Base Timer
10
Base Timer ch 8 TIOA pin
TIOA8_2
TIOB8_1
Base Timer
9
Pin Number
LQFP 176
LQFP 144
149
119
TIOA14_1
TIOB14_0
TIOB14_1
Base Timer ch 14 TIOA pin
Base Timer ch 14 TIOB pin
Document Number: 001-98708 Rev. *E
22
19
125
101
43
-
151
121
82
-
150
120
83
-
Page 34 of 190
S6E2G Series
Module
Pin Name
TIOA15_0
Base Timer
15
TIOA15_1
TIOB15_0
TIOB15_1
Function
Base Timer ch 15 TIOA pin
Base timer ch 15 TIOB pin
TX0_0
TX0_1
CAN 0
CAN interface ch 0 TX output pin
58
-
154
124
59
-
101
85
25
-
TX0_2
59
-
RX0_0
100
84
24
-
58
-
135
111
137
113
RX0_1
CAN interface ch 0 RX input pin
RX0_2
SWO
Serial wire debug interface clock input
pin
Serial wire debug interface data input/
output pin
Serial wire viewer output pin
138
114
TCK
JTAG test clock input pin
135
111
SWCLK
SWDIO
TDI
JTAG test data input pin
136
112
TDO
JTAG debug data output pin
138
114
TMS
JTAG test mode state input/output pin
137
113
Trace CLK output pin of ETM/HTM
114
90
98
82
TRACECLK
TRACED0
TRACED1
99
83
100
84
TRACED3
101
85
TRACED4
106
86
TRACED5
107
87
TRACED6
108
88
TRACED7
109
89
TRACED8
102
-
TRACED9
103
-
TRACED2
Debugger
Pin Number
LQFP 176
LQFP 144
155
125
TRACED10
Trace data output pin of ETM/
Trace data output pin of HTM
Trace data output pin of HTM
104
-
TRACED11
105
-
TRACED12
110
-
TRACED13
111
-
TRACED14
112
-
TRACED15
TRSTX
JTAG test reset Input pin
Document Number: 001-98708 Rev. *E
113
-
134
110
Page 35 of 190
S6E2G Series
Module
Pin Name
Function
MAD00_0
MAD01_0
70
60
MAD02_0
71
61
MAD03_0
72
62
MAD04_0
73
63
MAD05_0
74
64
MAD06_0
75
65
MAD07_0
76
66
MAD08_0
77
67
MAD09_0
115
91
MAD10_0
116
92
117
93
118
94
MAD13_0
119
95
MAD14_0
120
96
MAD15_0
121
97
MAD16_0
122
98
MAD17_0
123
99
MAD18_0
124
100
MAD19_0
40
35
MAD20_0
39
34
MAD21_0
38
33
MAD22_0
37
32
MAD23_0
36
31
MAD24_0
35
30
MCSX0_0
67
57
MCSX1_0
66
56
MCSX2_0
51
43
50
42
49
41
MAD11_0
MAD12_0
External
bus
Pin Number
LQFP 176
LQFP 144
69
59
MCSX3_0
MCSX4_0
MCSX5_0
External bus interface address bus
External bus interface chip select
output pin
48
40
MCSX6_0
47
39
MCSX7_0
46
38
MCSX8_0
63
53
Document Number: 001-98708 Rev. *E
Page 36 of 190
S6E2G Series
Module
Pin Name
Function
MADATA00_0
MADATA01_0
3
3
MADATA02_0
4
4
MADATA03_0
5
5
MADATA04_0
6
6
MADATA05_0
7
7
MADATA06_0
8
8
MADATA07_0 External bus interface data bus
MADATA08_0 (address/data multiplex bus)
9
9
13
10
MADATA09_0
14
11
MADATA10_0
15
12
MADATA11_0
16
13
MADATA12_0
17
14
MADATA13_0
18
15
MADATA14_0
19
16
MADATA15_0
20
17
21
18
22
19
171
139
68
58
23
20
97
81
96
80
94
78
95
79
169
137
170
138
65
55
64
54
60
50
61
51
62
52
MDQM0_0
MDQM1_0
External bus interface byte mask signal
output pin
External bus interface address latch
enable output signal for multiplex
External bus interface external RDY
MRDY_0
input signal
External bus interface external clock
MCLKOUT_0
output pin
External bus interface ALE signal to
MNALE_0
control NAND flash output pin
External bus interface CLE signal to
MNCLE_0
control NAND flash output pin
External bus interface read enable signal
MNREX_0
to control NAND flash
External bus interface write enable signal
MNWEX_0
to control NAND flash
External bus interface read enable
MOEX_0
signal for SRAM
External bus interface write enable
MWEX_0
signal for SRAM
SDRAM interface
MSDCLK_0
SDRAM clock output pin
SDRAM interface
MSDCKE_0
SDRAM clock enable pin
SDRAM interface
MRASX_0
SDRAM row active strobe pin
SDRAM interface
MCASX_0
SDRAM column active strobe pin
SDRAM interface
MSDWEX_0
SDRAM write enable pin
MALE_0
External
bus
Pin Number
LQFP 176
LQFP 144
2
2
Document Number: 001-98708 Rev. *E
Page 37 of 190
S6E2G Series
Module
Pin Name
Function
INT00_0
INT00_1
External interrupt request 00 input pin
28
23
INT00_2
8
8
INT01_0
7
7
31
26
24
-
13
10
32
27
9
9
16
13
33
28
INT01_1
External interrupt request 01 input pin
INT01_2
INT02_0
INT02_1
External interrupt request 02 input pin
INT02_2
INT03_0
INT03_1
External interrupt request 03 input pin
INT03_2
41
-
INT04_0
49
41
INT04_1
External interrupt request 04 input pin
68
58
INT04_2
63
53
INT05_0
66
56
INT05_1
External interrupt request 05 input pin
INT05_2
INT06_0
External
interrupt
Pin Number
LQFP 176
LQFP 144
2
2
INT06_1
External interrupt request 06 input pin
79
-
64
54
60
50
80
-
69
59
65
55
81
-
INT07_2
77
67
INT08_0
94
78
103
-
INT08_2
118
94
INT09_0
100
84
INT06_2
INT07_0
INT07_1
INT08_1
INT09_1
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
INT09_2
INT10_0
INT10_1
External interrupt request 10 input pin
INT10_2
INT11_0
INT11_1
External interrupt request 11 input pin
104
-
119
95
106
86
110
-
120
96
109
89
111
-
INT11_2
122
98
INT12_0
162
132
139
-
152
122
140
-
INT12_1
INT13_0
INT13_1
External interrupt request 12 input pin
External interrupt request 13 input pin
Document Number: 001-98708 Rev. *E
Page 38 of 190
S6E2G Series
Module
Pin Name
INT14_0
INT14_1
INT15_0
INT15_1
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
External
interrupt
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
Function
External interrupt request 14 input pin
External interrupt request 15 input pin
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
External interrupt request 23 input pin
External interrupt request 24 input pin
External interrupt request 25 input pin
External interrupt request 26 input pin
External interrupt request 27 input pin
External interrupt request 28 input pin
External interrupt request 29 input pin
External interrupt request 30 input pin
External interrupt request 31 input pin
Non-maskable interrupt input pin
Document Number: 001-98708 Rev. *E
Pin Number
LQFP 176
LQFP 144
160
130
141
-
161
131
142
-
20
17
35
30
21
18
36
31
22
19
37
32
26
21
38
33
70
60
82
-
73
63
83
-
76
66
58
-
46
38
59
-
121
97
107
87
123
99
97
81
126
102
116
92
127
103
117
93
158
128
167
-
166
136
168
-
169
137
163
133
172
140
164
134
128
104
Page 39 of 190
S6E2G Series
Module
Pin Name
Function
P00
P01
135
111
P02
136
112
137
113
P03
P04
General-purpose I/O port 0
138
114
P08
21
18
P09
22
19
P0A
23
20
P10
94
78
P11
95
79
P12
96
80
P13
97
81
P14
98
82
P15
99
83
P16
100
84
P17
101
85
P18
GPIO
Pin Number
LQFP 176
LQFP 144
134
110
General-purpose I/O port 1
106
86
P19
107
87
P1A
108
88
P1B
109
89
P1C
114
90
P1D
115
91
P1E
116
92
P1F
117
93
P20
128
104
P21
127
103
P22
126
102
P23
125
101
124
100
123
99
P26
122
98
P27
121
97
P28
120
96
P29
119
95
P2A
118
94
P24
P25
General-purpose I/O port 2
Document Number: 001-98708 Rev. *E
Page 40 of 190
S6E2G Series
Module
Pin Name
Function
P30
P31
25
-
P32
26
21
P33
27
22
P34
28
23
P35
31
26
32
27
33
28
P38
34
29
P36
P37
GPIO
Pin Number
LQFP 176
LQFP 144
24
-
General-purpose I/O port 3
P39
35
30
P3A
36
31
P3B
37
32
P3C
38
33
P3D
39
34
P3E
40
35
P40
46
38
P41
47
39
P42
48
40
P43
49
41
P44
50
42
P45
51
43
55
47
56
48
P48
60
50
P49
61
51
P4A
62
52
P46
P47
General-purpose I/O port 4
P4B
63
53
P4C
64
54
P4D
65
55
P4E
66
56
P50
10
-
P51
11
-
P52
12
-
41
-
42
-
P5D
General-purpose I/O port 5
P5E
P5F
43
-
P60
172
140
P61
171
139
170
138
169
137
P64
168
-
P65
167
-
P6E
166
136
P62
P63
General-purpose I/O port 6
Document Number: 001-98708 Rev. *E
Page 41 of 190
S6E2G Series
Module
Pin Name
Function
P70
P71
68
58
P72
69
59
P73
70
60
71
61
72
62
P76
73
63
P77
74
64
P78
75
65
P74
P75
General-purpose I/O port 7
P79
76
66
P7A
77
67
P80
174
142
P81
175
143
P82
GPIO
Pin Number
LQFP 176
LQFP 144
67
57
General-purpose I/O port 8
130
106
P83
131
107
P90
139
-
P91
140
-
P92
141
-
P93
General-purpose I/O port 9
142
-
P94
143
-
P95
144
-
PA0
2
2
PA1
3
3
PA2
4
4
PA3
5
5
PA4
6
6
PA5
7
7
PA6
8
8
PA7
PA8
General-purpose I/O port A
9
9
13
10
PA9
14
11
PAA
15
12
PAB
16
13
PAC
17
14
PAD
18
15
PAE
19
16
PAF
20
17
Document Number: 001-98708 Rev. *E
Page 42 of 190
S6E2G Series
Module
Pin Name
Function
PB0
GPIO
PB1
103
-
PB2
104
-
PB3
105
-
PB4
General-purpose I/O port B
110
-
PB5
111
-
PB6
112
-
PB7
113
-
PC0
145
115
PC1
146
116
PC2
147
117
PC3
148
118
PC4
149
119
PC5
150
120
PC6
151
121
PC7
152
122
PC8
GPIO
Pin Number
LQFP 176
LQFP 144
102
-
General-purpose I/O port C
153
123
PC9
154
124
PCA
155
125
PCB
158
128
PCC
159
129
PCD
160
130
PCE
161
131
PCF
162
132
PD0
163
133
164
134
PD2
165
135
PE0
84
68
PD1
PE2
General-purpose I/O port D
General-purpose I/O port E
86
70
PE3
87
71
PF0
58
-
PF1
59
-
PF2
78
-
79
-
80
-
PF5
81
-
PF6
82
-
PF7
83
-
PF3
PF4
General-purpose I/O port F
Document Number: 001-98708 Rev. *E
Page 43 of 190
S6E2G Series
Module
Pin Name
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
MultiFunction
Serial
0
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Function
Multi-function serial interface ch 0 input
pin
Multi-function serial interface ch 0 output
pin
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 0 clock
I/O pin
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2) and
as SCL0 when it is used in an I2C
(operation mode 4)
SIN1_0
Multi-function serial interface ch 1 input
(MI2SDI1_0) pin.
SIN1 pin operates as MI2SDI1 when used
SIN1_1
2
(MI2SDI1_1) as an I S pin (operation mode 2).
Multi-function serial interface ch 1 output
SOT1_0
pin
(SDA1_0)
(MI2SDO1_0) This pin operates as SOT1 when it is used in a
Pin Number
LQFP 176
LQFP 144
127
103
116
92
126
102
115
91
125
101
114
90
60
50
41
-
61
51
42
-
62
52
43
-
63
53
24
-
64
54
25
-
UART/CSIO/LIN (operation modes 0 to 3) and
MultiFunction
Serial
1
as SDA1 when it is used in an I2C (operation
SOT1_1
mode 4).
(SDA1_1)
(MI2SDO1_1) SOT1 pin operates as MI2SDO1 when used as
an I2S pin (operation mode 2).
Multi-function serial interface ch 1 clock
SCK1_0
I/O pin
(SCL1_0)
(MI2SCK1_0) This pin operates as SCK1 when it is
used in a CSIO (operation mode 2) and
as SCL1 when it is used in an I2C
SCK1_1
(operation mode 4).
(SCL1_1)
as MI2SCK1 when
(MI2SCK1_1) SCK1 pin operates
used as an I2S pin (operation mode 2).
MI2SWS1_0
MI2SWS1_1
MI2SMCK1_0
MI2SMCK1_1
I2S word select (WS) output pin
I2S master clock I/O pin
Document Number: 001-98708 Rev. *E
Page 44 of 190
S6E2G Series
Module
Pin Name
SIN2_0
SIN2_1
SOT2_0
(SDA2_0)
MultiFunction
Serial
2
SOT2_1
(SDA2_1)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SIN3_0
SIN3_1
SOT3_0
(SDA3_0)
MultiFunction
Serial
3
SOT3_1
(SDA3_1)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SIN4_0
SIN4_1
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
MultiFunction
Serial
4
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
CTS4_0
CTS4_1
RTS4_0
RTS4_1
Function
Multi-function serial interface ch 2 input
pin
Multi-function serial interface ch 2 output
pin
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 2 clock
I/O pin
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2) and
as SCL2 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 3 input
pin
Multi-function serial interface ch 3 output
pin
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 3 clock
I/O pin
This pin operates as SCK3 when it is
used in a CSIO (operation modes 2) and
as SCL3 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 4 input
pin
Multi-function serial interface ch 4 output
pin
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 4 clock
I/O pin
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2) and
as SCL4 when it is used in an I2C
(operation mode 4).
Pin Number
LQFP 176
LQFP 144
106
86
38
33
107
87
39
34
108
88
40
35
20
17
81
-
19
16
82
-
18
15
83
-
172
140
161
131
171
139
160
130
170
138
166
136
Multi-function serial interface ch 4 CTS
input pin
168
-
165
135
Multi-function serial interface ch 4 RTS
output pin
169
137
162
132
Document Number: 001-98708 Rev. *E
Page 45 of 190
S6E2G Series
Module
Pin Name
SIN5_0
SIN5_1
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
MultiFunction
Serial
5
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
CTS5_0
CTS5_1
RTS5_0
RTS5_1
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
MultiFunction
Serial
6
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SCS60_0
SCS60_1
SCS61_0
SCS61_1
SCS62_0
SCS62_1
SCS63_0
SCS63_1
Function
Multi-function serial interface ch 5 input
pin
Multi-function serial interface ch 5 output
pin
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 5 clock
I/O pin
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 5 CTS
input pin
Multi-function serial interface ch 5 RTS
output pin
Multi-function serial interface ch 6 input
pin
Multi-function serial interface ch 6 output
pin
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 6 clock
I/O pin
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2) and
as SCL6 when it is used in an I2C
(operation mode 4).
Pin Number
LQFP 176
LQFP 144
121
97
140
-
120
96
141
-
119
95
142
-
118
94
143
-
117
93
144
-
73
63
100
84
74
64
101
85
75
65
102
-
Multi-function serial interface ch 6 chip
select 0 input/output pin
76
66
103
-
Multi-function serial interface ch 6 chip
select1 input/output pin
77
67
104
-
78
-
105
-
79
-
110
-
Multi-function serial interface ch 6 chip
select2 input/output pin
Multi-function serial interface ch 6 chip
select3 input/output pin
Document Number: 001-98708 Rev. *E
Page 46 of 190
S6E2G Series
Module
Pin Name
SIN7_0
SIN7_1
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
MultiFunction
Serial
7
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
SCS70_0
SCS70_1
SCS71_0
SCS71_1
SCS72_0
SCS72_1
SCS73_0
SCS73_1
SIN8_0
SIN8_1
SOT8_0
(SDA8_0)
MultiFunction
Serial
8
SOT8_1
(SDA8_1)
SCK8_0
(SCL8_0)
SCK8_1
(SCL8_1)
SIN9_0
SIN9_1
SOT9_0
(SDA9_0)
MultiFunction
Serial
9
SOT9_1
(SDA9_1)
SCK9_0
(SCL9_0)
SCK9_1
(SCL9_1)
Function
Multi-function serial interface ch 7 input
pin
Pin Number
LQFP 176
LQFP 144
13
10
46
38
14
11
47
39
15
12
48
40
Multi-function serial interface ch 7 chip
select 0 input/output pin
16
13
49
41
Multi-function serial interface ch 7 chip
select 1 input/output pin
17
14
50
42
Multi-function serial interface ch 7 chip
select 2 input/output pin
10
-
51
43
Multi-function serial interface ch 7 chip
select 3 input/output pin
11
-
Multi-function serial interface ch 7 output
pin
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 7
clock I/O pin
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2) and
as SCL7 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 8 input
pin
Multi-function serial interface ch 8 output
pin
This pin operates as SOT8 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA8 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 8 clock
I/O pin
This pin operates as SCK8 when it is
used in a CSIO (operation mode 2) and
as SCL8 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch 9 input
pin
Multi-function serial interface ch 9 output
pin
This pin operates as SOT9 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA9 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch 9 clock
I/O pin
This pin operates as SCK9 when it is
used in a CSIO (operation mode 2) and
as SCL9 when it is used in an I2C
(operation mode 4).
Document Number: 001-98708 Rev. *E
58
-
70
60
111
-
71
61
112
-
72
62
113
-
68
58
97
81
67
57
98
82
66
56
99
83
Page 47 of 190
S6E2G Series
Module
Pin Name
DTTI0X_0
DTTI0X_1
FRCK0_0
FRCK0_1
Function
Input signal controlling waveform
generator outputs RTO00 to RTO05 of
Multi-Function Timer 0.
16-bit free-run timer ch 0 external
clock input pin
IC00_0
8
8
27
22
13
10
33
28
IC00_1
9
9
IC01_0
32
27
IC01_1
16-bit input capture input pin of
Multi-Function Timer 0.
ICxx describes channel number.
10
-
31
26
IC02_1
11
-
IC03_0
28
23
IC03_1
12
-
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG00 when it is
used in PPG0 output modes.
35
30
2
2
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG00 when it is
used in PPG0 output modes.
36
31
3
3
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
37
32
4
4
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG02 when it is
used in PPG0 output modes.
38
33
5
5
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG04 when it is
used in PPG0 output modes.
39
34
6
6
Waveform generator output pin of
Multi-Function Timer 0.
This pin operates as PPG04 when it is
used in PPG0 output modes.
40
35
7
7
IC02_0
RTO00_0
(PPG00_0)
MultiFunction
Timer 0
Pin Number
LQFP 176
LQFP 144
34
29
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
Document Number: 001-98708 Rev. *E
Page 48 of 190
S6E2G Series
Module
Pin Name
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
Input signal controlling waveform
generator outputs RTO10 to RTO15 of
Multi-Function Timer 1.
16-bit free-run timer ch 1 external
clock input pin
Pin Number
LQFP 176
LQFP 144
60
50
78
-
65
55
79
-
IC10_0
61
51
IC10_1
80
-
IC11_0
62
52
IC11_1
16-bit input capture input pin of
Multi-Function Timer 1.
ICxx describes channel number.
81
-
63
53
IC12_1
82
-
IC13_0
64
54
IC13_1
83
-
46
38
139
-
47
39
140
-
48
40
141
-
49
41
142
-
50
42
143
-
51
43
144
-
IC12_0
RTO10_0
(PPG10_0)
MultiFunction
Timer 1
Function
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG10 when it is
used in PPG1 output modes.
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG10 when it is
used in PPG1 output modes.
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG12 when it is
used in PPG1 output modes.
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG12 when it is
used in PPG1 output modes.
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG14 when it is
used in PPG1 output modes.
Waveform generator output pin of
Multi-Function Timer 1.
This pin operates as PPG14 when it is
used in PPG1 output modes.
Document Number: 001-98708 Rev. *E
Page 49 of 190
S6E2G Series
Module
Pin Name
Function
AIN0_0
AIN0_1
Quadrature
Position/
Revolution
Counter
0
QPRC ch 0 AIN input pin
-
BIN0_0
47
39
BIN0_1
QPRC ch 0 BIN input pin
BIN0_2
ZIN0_0
QPRC ch 0 ZIN input pin
AIN1_0
AIN1_1
QPRC ch 1 AIN input pin
-
48
40
77
67
105
-
35
30
14
11
111
-
36
31
15
12
BIN1_1
QPRC ch 1 BIN input pin
BIN1_2
112
-
ZIN1_0
37
32
RTCCO_0
RTCCO_1
SUBOUT_0
SUBOUT_1
QPRC ch 1 ZIN input pin
0.5 seconds pulse output pin of
real-time clock
Sub-clock output pin
16
13
113
-
171
139
9
9
171
139
9
9
UDM0
USB ch 0 device/host D – pin
174
142
UDP0
USB ch 0 device/host D + pin
175
143
USB ch 0 external pull-up control pin
171
139
UDM1
USB ch 1 device/host D – pin
130
106
UDP1
USB ch 1 device/host D + pin
131
107
USB ch 1 external pull-up control pin
Deep standby mode return signal input
pin 0
Deep standby mode return signal input
pin 1
Deep standby mode return signal input
pin 2
Deep standby mode return signal input
pin 3
125
101
128
104
13
10
66
56
172
140
UHCONX0
UHCONX1
WKUP0
Low power
consumption
mode
66
BIN1_0
ZIN1_2
USB1
76
104
AIN1_2
ZIN1_1
USB0
65
103
ZIN0_2
Real-time
clock
75
AIN0_2
ZIN0_1
Quadrature
Position/
Revolution
Counter
1
Pin Number
LQFP 176
LQFP 144
46
38
WKUP1
WKUP2
WKUP3
Document Number: 001-98708 Rev. *E
Page 50 of 190
S6E2G Series
Module
Pin Name
S_CLK_0
SD memory card interface
SD memory card clock output pin
SD memory card interface
SD memory card command output
23
31
26
S_DATA1_0
26
21
S_DATA0_0
27
22
32
27
33
28
35
30
S_DATA3_0
SD memory card interface
SD memory card data bus
S_DATA2_0
SD memory card interface
SD memory card detection pin
SD memory card interface
SD memory card write protection
Collision detection
34
29
154
124
Clock output for Ethernet PHY
158
128
E_CRS
Carrier detection
155
125
E_MDC
Management clock
152
122
E_MDIO
Management data I/O
151
121
E_PPS
PTP counter monitor
166
136
E_RX00
Received data0
149
119
E_RX01
Received data1
148
118
E_RX02
Received data2
147
117
E_RX03
Received data3
146
116
153
123
150
120
S_CD_0
S_WP_0
E_COL
E_COUT
Ethernet
Pin Number
LQFP 176
LQFP 144
28
S_CMD_0
SD I/F
Function
E_RXCK_RE Received clock input/
Reference clock
FCK
Received data enable
E_RXDV
Received data error detection
145
115
E_TCK
Transition clock input
159
129
E_TX00
Transition data0
164
134
E_TX01
Transition data1
163
133
E_TX02
Transition data2
162
132
E_RXER
E_TX03
Transition data3
161
131
E_TXEN
Transition data enable
165
135
E_TXER
Transition data error detection
160
130
Document Number: 001-98708 Rev. *E
Page 51 of 190
S6E2G Series
Module
Pin Name
IC0_VCC_0
IC0_VCC_1
IC0_VPEN_0
IC0_VPEN_1
IC0_RST_0
Smartcard0
IC0_RST_1
IC0_CIN_0
IC0_CIN_1
IC0_CLK_0
IC0_CLK_1
Smartcard ch 0 power enable output pin
Smartcard ch 0 programming output pin
Smartcard ch 0 reset output pin
Smartcard ch 0 insert detection input pin
Smartcard ch 0 serial interface clock
output pin
Pin Number
LQFP 176
LQFP 144
6
6
140
-
5
5
141
-
4
4
142
-
2
2
144
-
7
7
139
-
3
3
IC0_DATA_0 Smartcard ch 0 serial interface data I/O
IC0_DATA_1 pin
143
-
IC1_VCC_0
95
79
IC1_VCC_1
IC1_VPEN_0
IC1_VPEN_1
IC1_RST_0
Smartcard1
Function
IC1_RST_1
IC1_CIN_0
IC1_CIN_1
IC1_CLK_0
IC1_CLK_1
Smartcard ch 1 power enable output pin
Smartcard ch 1 programming output pin
Smartcard ch 1 reset output pin
Smartcard ch 1 insert detection input pin
Smartcard ch 1 serial interface clock
output pin
IC1_DATA_0 Smartcard ch 1 serial interface data I/O
IC1_DATA_1 pin
Document Number: 001-98708 Rev. *E
79
-
96
80
80
-
97
81
81
-
99
83
83
-
94
78
78
-
98
82
82
-
Page 52 of 190
S6E2G Series
Module
Pin Name
Reset
INITX
MD1
Mode
MD0
VCC
Function
External reset Input pin
A reset is valid when INITX = L.
Mode 1 pin
During serial programming to flash
memory, MD1 = L must be input.
Mode 0 pin
During normal operation, MD0 = L must
be input. During serial programming to
flash memory, MD0 = H must be input.
Power supply pin
Power
USBVCC0
USBVCC1
ETHVCC
GND
Clock
VSS
Power supply pin for Ethernet I/O
GND pin
57
49
84
68
85
69
1
1
29
24
45
37
54
46
89
73
133
109
173
141
129
105
156
126
30
25
44
36
53
45
88
72
132
108
157
127
176
144
X0
Main clock (oscillation) input pin
86
70
X1
Main clock (oscillation) I/O pin
87
71
X0A
Sub clock (oscillation) input pin
55
47
X1A
Sub clock (oscillation) I/O pin
56
48
Built-in high-speed CR-oscillation clock
output port
127
103
152
122
90
74
92
76
93
77
A/D converter and D/A converter
GND pin
91
75
Power supply stabilization capacity pin
52
44
CROUT_0
CROUT_1
AVCC
Analog
power
3.3V power supply port for USB I/O
Pin Number
LQFP 176
LQFP 144
AVRL
AVRH
Analog
GND
AVSS
C pin
C
A/D converter and D/A converter
analog power-supply pin
A/D converter analog reference voltage
input pin
A/D converter analog reference voltage
input pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 001-98708 Rev. *E
Page 53 of 190
S6E2G Series
7. I/O Circuit Type
Type
Circuit
P-ch
P-ch
Remarks
Digital output
X1
N-ch
Digital output
R
It is possible to select the main
Oscillation/GPIO function.
Pull-up resistor control
Digital input
Standby mode control
Clock input
A
When the main oscillation
is selected:
・ Oscillation feedback resistor:
approximately 1 MΩ
・ Standby mode control
When the GPIO is selected:
・ CMOS level output.
・ CMOS level hysteresis input
Standby mode control
・ Pull-up resistor control
・ Standby mode control
Digital input
・ Pull-up resistor:
Standby mode control
・ IOH = -4 mA, IOL = 4 mA
approximately 50 kΩ
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
B
・ CMOS level hysteresis input
Pull-up resistor
・ Pull-up resistor:
Digital input
Document Number: 001-98708 Rev. *E
approximately 50 kΩ
Page 54 of 190
S6E2G Series
Type
Circuit
Remarks
Digital input
・ Open drain output
C
N-ch
Document Number: 001-98708 Rev. *E
Digital output
・ CMOS level hysteresis input
Page 55 of 190
S6E2G Series
Type
Circuit
P-ch
X1A
X1
P-ch
N-ch
Remarks
Digital output
Digital output
R
It is possible to select the sub
oscillation/GPIO function.
Pull-up resistor control
Digital input
When the main oscillation
is selected:
Standby mode control
・ Oscillation feedback resistor:
Clock input
・ Standby mode control
D
approximately 5 MΩ
When the GPIO is selected:
・ CMOS level output.
Standby mode control
Digital input
Standby mode control
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
R
X0A
X0
P-ch
P-ch
Digital output
N-ch
Digital output
Pull-up resistor control
Document Number: 001-98708 Rev. *E
Page 56 of 190
S6E2G Series
Type
Circuit
P-ch
P-ch
Remarks
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
E
N-ch
Digital output
R
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an I2C pin,
Pull-up resistor control
the digital output P-ch transistor is
always off.
Digital input
Standby mode control
P-ch
P-ch
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Input control
N-ch
Digital output
・ Analog input
・ Pull-up resistor control
・ Standby mode control
F
・ Pull-up resistor:
Pull-up resistor control
R
Digital input
Standby mode control
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off.
Analog input
Input control
Document Number: 001-98708 Rev. *E
Page 57 of 190
S6E2G Series
Type
Circuit
P-ch
Remarks
Digital output
P-ch
・ CMOS level output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
G
N-ch
Digital output
R
approximately 50 kΩ
・ IOH = -12 mA, IOL = 12 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
Pull-up resistor
control
Digital input
transistor is always off.
Standby mode
control
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
UDP/Pxx
It is possible to select either USB I/O
or GPIO function.
USB Full-speed/Low-speed control
UDP input
When the USB I/O is selected:
・ Full-speed, low-speed control
H
Differential
UDM/Pxx
Differential input
USB/GPIO select
UDM input
UDM output
When the GPIO is selected:
・ CMOS level output
・ CMOS level hysteresis input
・ Standby mode control
・ IOH = -20.5 mA, IOL = 18.5 mA
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
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Page 58 of 190
S6E2G Series
Type
Circuit
Remarks
・ CMOS level output
・ CMOS level hysteresis input
P-ch
P-ch
Digital output
・ 5 V tolerant
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
I
N-ch
Digital output
R
・ IOH = -4 mA, IOL = 4 mA
・ Available to control of PZR registers
(pseudo-open drain control)
・ For PZR registers, refer to GPIO in
Pull-up resistor
control
Digital input
the FM4 Family Peripheral Manual
Main Part (002-04856).
Standby mode control
J
Mode input
P-ch
P-ch
CMOS level hysteresis input
Digital output
・ CMOS level output
・ TTL level hysteresis input
K
N-ch
Digital output
R
・ Pull-up resistor control
・Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
Document Number: 001-98708 Rev. *E
Page 59 of 190
S6E2G Series
Type
Circuit
P-ch
Remarks
P-ch
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Pull-up resistor control
・ Standby mode control
・ Pull-up resistor:
L
N-ch
Digital output
approximately 50 kΩ
・ IOH = -8 mA, IOL = 8 mA
・ When this pin is used as an I2C
pin, the digital output P-ch
Pull-up resistor
control
R
transistor is always off.
Digital input
Standby mode
control
・ CMOS level output
・ CMOS level hysteresis input
P-ch
P-ch
Pull-up resistor
control
・ 5V tolerant
Digital output
・ Standby mode control
・ Pull-up resistor control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA (GPIO)
N
N-ch
・ IOL = 20mA (Fast mode Plus)
N-ch
Digital output
・ Available to control of PZR register
(pseudo-open drain control)
・ For PZR registers, refer to GPIO in
R
Fast mode
control
Main Part (002-04856).
・ When this pin is used as an I2C pin,
Digital input
Standby mode
control
Document Number: 001-98708 Rev. *E
the FM4 Family Peripheral Manual
the digital output P-ch transistor is
always off.
Page 60 of 190
S6E2G Series
Type
Circuit
Remarks
・ CMOS level output
P-ch
P-ch
Pull-up resistor
control
・ CMOS level hysteresis input
Digital output
・ Pull-up resistor control
・ 5 V tolerant
・ Pull-up resistor:
approximately 50 kΩ
O
・ IOH = -4 mA, IOL = 4 mA
N-ch
Digital output
・ Available to control of PZR register
(pseudo-open drain control)
・ For PZR registers, refer to GPIO in
the FM4 Family Peripheral Manual
Main Part (002-04856).
R
Digital input
P-ch
P-ch
X0A
Pull-up resistor
control
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Pull-up resistor control
P
N-ch
Digital output
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
R
Digital input
Standby mode
control
OSC
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Page 61 of 190
S6E2G Series
Type
Circuit
Pull-up resistor
control
Digital output
P-ch
X1A
Remarks
P-ch
It is possible to select the sub
oscillation/GPIO function.
When the sub oscillation
Digital output
N-ch
is selected:
・ Oscillation feedback resistor:
approximately 10 MΩ
Q
When the GPIO is selected:
・ CMOS level output.
R
Digital input
・ CMOS level hysteresis input
Standby mode
control
OSC
・ Pull-up resistor:
・ Pull-up resistor control
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
RX
Standby mode
control
Clock input
P-ch
P-ch
Pull-up resistor
control
Digital output
・ CMOS level output
・ CMOS level hysteresis input
・ Analog output
・ Pull-up resistor control
N-ch
R
Digital output
・ Standby mode control
・ Pull-up resistor:
approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
(4.5V to 5.5V)
・ IOH = -2 mA, IOL = 2 mA
R
Digital input
(2.7V to 4.5V)
Standby mode
control
Analog output
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Page 62 of 190
S6E2G Series
8. Handling Precautions
Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must
be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
8.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins that connect semiconductor devices to power supply and I/O
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions, if present for extended periods of time, can damage the device; therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power-supply pin or ground pin.
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S6E2G Series
Latch-Up
Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When subjected to
abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels
in excess of several hundred milliamps to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
As previously mentioned, all semiconductor devices have inherent rates of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection,
and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support,
etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages
arising from such use without prior approval.
8.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering,
you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your
sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
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S6E2G Series
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of
recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent this, do the following:
1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%.
4. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in these aluminum laminate bags for storage.
5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ). Wearing of conductive clothing and shoes, and the use of conductive floor mats and other measures to minimize shock
loads is recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.
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S6E2G Series
8.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of static electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive gases, dust, or oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, including cosmic radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, flame
CAUTION: Plastic molded devices are flammable and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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S6E2G Series
9. Handling Devices
Power-Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. All of these pins should be connected externally to the power supply or ground lines,
however, in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total output current rating.
Be sure to connect the current-supply source with the power pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this
device.
A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1V/μs at a momentary fluctuation such as switching the power
supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device
as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane, as this is expected to produce stable operation.
Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board.
Sub Crystal Oscillator
The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize the oscillation, Cypress
recommends a crystal oscillator that meets the following conditions:
Surface mount type
Size: More than 3.2 mm × 1.5 mm
Load capacitance: approximately 6 pF to 7 pF
Lead type
Load capacitance: approximately 6 pF to 7 pF
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S6E2G Series
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0.
X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set
X0A/X1A to the external clock input and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as external clock
input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
Handling When Using Multi-Function Serial Pin as I2C Pin
If the application uses the multi-function serial pin as an I2C pin, the P-channel transistor of the digital output must be disabled. I2C
pins need to conform to electrical limitations like other pins, however, and avoid connecting to live external systems with the MCU
power off.
C Pin
Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and
the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
Some laminated ceramic capacitors have a large capacitance variation due to thermal fluctuation. Please select a capacitor that
meets the specifications in the operating conditions to use by evaluating the temperature characteristics of the device. A
smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, the distance between the mode pins and VCC pins or VSS pins is as short as possible, and the connection impedance
is low when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. This is important
to prevent the device from erroneously switching to test mode as a result of noise.
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Page 68 of 190
S6E2G Series
Notes on Power-On
Turn power on/off in the sequence shown below or at the same time. If not using the A/D converter and D/A converter, connect
AVCC = VCC and AVSS = VSS.
Turning on:
Turning off:
VCC → USBVCC0
VCC → USBVCC1
VCC →ETHVCC
VCC → AVCC → AVRH
AVRH → AVCC → VCC
ETHVCC → VCC
USBVCC1 → VCC
USBVCC0 → VCC
Serial Communication
There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial communication. Take
care to design the printed circuit board to minimize noise.
Consider the case of introducing error as a result of noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
Differences in Characteristics within the Product Line
The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among members of the
product line because chip layout and memory structures are not the same; for example, different sizes, flash versus ROM, etc. If
you are switching to a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Pin Doubled as Debug Function
The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do not use as input.
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S6E2G Series
10. Memory Map
Memory Map (1)
See "Memory Map (2) for
memory size details.
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Page 70 of 190
S6E2G Series
Memory Map (2)
*: See S6E2GM/GK/GH/G3/G2 Series Flash Programming Manual to confirm the detail of flash Memory.
Document Number: 001-98708 Rev. *E
Page 71 of 190
S6E2G Series
Peripheral Address Map
Start Address
End Address
Bus
Peripherals
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/reset control
0x4001_1000
0x4001_1FFF
Hardware watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-Function Timer unit 0
0x4002_1000
0x4002_1FFF
Multi-Function Timer unit 1
0x4002_2000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External interrupt controller
0x4003_1000
0x4003_1FFF
Interrupt request batch-read function
0x4003_2000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low voltage detector
0x4003_5800
0x4003_5FFF
Deep standby mode Controller
0x4003_6000
0x4003_6FFF
USB clock generator
0x4003_7000
0x4003_7FFF
CAN prescaler
0x4003_8000
0x4003_8FFF
Multi-function serial interface
0x4003_9000
0x4003_9FFF
0x4003_A000
0x4003_AFFF
Watch counter
0x4003_B000
0x4003_BFFF
RTC/port control
0x4003_C000
0x4003_C0FF
Low-speed CR prescaler
0x4003_C100
0x4003_C7FF
Peripheral clock gating
0x4003_C800
0x4003_C8FF
Reserved
0x4003_C900
0x4003_CA00
0x4003_CB00
0x4003_F000
0x4003_C9FF
0x4003_CAFF
0x4003_EFFF
0x4003_FFFF
I2S clock generator
Smartcard Interface
Reserved
External memory interface
Document Number: 001-98708 Rev. *E
AHB
APB0
APB1
APB2
MainFlash I/F register
Reserved
Software watchdog timer
Reserved
Base timer
Quadrature position/revolution counter
CRC
Page 72 of 190
S6E2G Series
Start Address
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4006_6000
0x4006_7000
0x4006_E000
0x4006_F000
0x4007_0000
End Address
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x4006_5FFF
0x4006_6FFF
0x4006_DFFF
0x4006_EFFF
0x4006_FFFF
0x41FF_FFFF
Document Number: 001-98708 Rev. *E
Bus
AHB
Peripherals
USB ch 0
USB ch 1
DMAC register
DSTC register
CAN ch 0
Reserved
Ethernet-MAC ch 0
Ethernet-MAC setting register
Reserved
SD card I/F
GPIO
Reserved
Page 73 of 190
S6E2G Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings:
INITX = 0
This is the period when the INITX pin is at the L level.
INITX = 1
This is the period when the INITX pin is at the H level.
SPL = 0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL = 1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Setting prohibition
Prohibition of a setting by specification limitation
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S6E2G Series
Pin Status Type
List of Pin Behavior by Mode State
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
A
B
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
Device
Internal
Reset
State
‐
‐
SPL=0
Maintain
previous
state
SPL=1
SPL=0
SPL=1
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
-
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Main crystal
oscillator
input pin/
external main
clock input
selected
Input
enabled
Input
Input
enabled enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
State
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
External main
clock input
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Main crystal
oscillator
output pin
Hi-Z/
Hi-Z/
internal
internal
input fixed
input
at 0/
fixed
or input
at 0
enabled
Hi-Z/
internal
input
fixed
at 0
Input
enabled
Input
enabled
Maintain
previous
state
Input
enabled
Hi-Z/internal
input fixed
at 0
GPIO
selected
Input
Enabled
Maintain previous state while oscillator active/
When oscillation stops*1, it will be Hi-Z/
Internal input fixed at 0
C
INITX
input pin
Pull-up/
input
enabled
Pull-up/ Pull-up/
Pull-up/
Input
Input
Input enabled
enabled enabled
Pull-up/
Input
enabled
Pull-up/
Input enabled
Pull-up/
Input
enabled
Pull-up/
Input enabled
Pull-up/
Input
enabled
D
Mode
input pin
Input
enabled
Input
Input
enabled enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Mode
input pin
Input
enabled
Input
Input
enabled enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
input
enabled
GPIO
selected
Hi-Z/
input
enabled
GPIO
selected
E
Document Number: 001-98708 Rev. *E
Page 75 of 190
Pin Status Type
S6E2G Series
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
NMIX
selected
F
Resource
other than
above
selected
Setting
disabled
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
‐
Hi-Z
Hi-Z
Pull-up/ Pull-up/
input
input
enabled enabled
G
H
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
JTAG
selected
Hi-Z
Pull-up/ Pull-up/
input
input
enabled enabled
Resource
other than
above
selected
‐
INITX=1
SPL=0
Setting
disabled
Setting Setting
disabled disabled
Hi-Z
Hi-Z/
Hi-Z/
input
input
enabled enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
I
GPIO
selected
Document Number: 001-98708 Rev. *E
Hi-Z/
internal
input fixed
at 0
Maintain
previous
state
Hi-Z/
internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Resource
selected
SPL=1
SPL=0
SPL=1
Maintain
previous
state
Setting Setting
disabled disabled
Hi-Z/
Hi-Z/
input
input
enabled enabled
GPIO
selected
JTAG
selected
Run mode
or Sleep
mode State
‐
Device
Internal
Reset
State
Maintain
previous
state
WKUP
input
enabled
Hi-Z/
WKUP
input enabled
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z/
selected,
internal input
internal input
fixed
fixed
at 0
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Maintain
previous
state
GPIO
selected
Maintain
previous
state
GPIO
Hi-Z/Internal
selected,
Hi-Z/Internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
GPIO
Hi-Z/Internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Page 76 of 190
Pin Status Type
S6E2G Series
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
‐
Device
Internal
Reset
State
‐
‐
Analog output
selected
J
External
interrupt
enable
selected
Hi-Z
Resource
other than
above
selected
Hi-Z/
Hi-Z/
input
input
enabled enabled
Maintain
previous
state
INITX=1
SPL=0
SPL=1
*2
*3
Maintain
previous
state
Maintain
previous
state
GPIO
selected
External
interrupt
enable
selected
K
Resource
other than
above
selected
Setting
disabled
GPIO
selected,
Hi-Z/internal
internal input input fixed
fixed
at 0
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected,
Hi-Z/internal
internal input input fixed
fixed
at 0
Hi-Z/internal
at 0
input fixed
at 0
Hi-Z
Setting Setting
disabled disabled
GPIO
selected
Document Number: 001-98708 Rev. *E
GPIO
selected
Maintain
previous
state
Setting Setting
disabled disabled
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal internal
Hi-Z/
Hi-Z/
Hi-Z/
internal input
internal input
input
input
internal input
internal input
internal input
fixed
fixed
fixed at fixed at
fixed
fixed
fixed
at 0/
at 0/
0/
0/
at 0/
at 0/
at 0/
analog
analog
analog
analog
analog
analog
analog
input
input
input
input
input enabled
input enabled
input enabled
enabled
enabled
enabled enabled
Setting
disabled
-
Hi-Z/internal
input fixed
at 0
Hi-Z/
Hi-Z/
input
input
enabled enabled
L
Resource
other than
above
selected
SPL=1
Hi-Z
GPIO
selected
Analog input
selected
SPL=0
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Hi-Z/
internal input
fixed
at 0/
analog
input
enabled
GPIO
selected
Page 77 of 190
Pin Status Type
S6E2G Series
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
Analog input
selected
M
Hi-Z
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
‐
Device
Internal
Reset
State
‐
‐
INITX=1
SPL=0
N
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z
GPIO
selected,
Hi-Z/internal
internal input input fixed
fixed
at 0
Hi-Z/internal
at 0
input fixed
at 0
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal internal
Hi-Z/
Hi-Z/
Hi-Z/
internal input
internal input
input
input
internal input
internal input
internal input
fixed
fixed
fixed
fixed
fixed
fixed
fixed
at 0/
at 0/
at0/
at 0/
at 0/
at 0/
at 0/
analog
analog
analog
analog
analog
analog
analog
input
input
input
input
input enabled
input enabled
input enabled
enabled
enabled
enabled enabled
Trace
selected
Resource
other than
above
selected
SPL=1
Hi-Z/
internal input
fixed
at 0/
analog
input
enabled
Maintain
previous state
GPIO
selected
Analog input
selected
SPL=0
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal internal
Hi-Z/
Hi-Z/
Hi-Z/
internal input
internal input
input
input
internal input
internal input
internal input
fixed
fixed
fixed
fixed
fixed
fixed
fixed
at 0/
at 0/
at 0/
at 0/
at 0/
at 0/
at 0/
analog
analog
analog
analog
analog
analog
analog
input
input
input
input
input enabled
input enabled
input enabled
enabled
enabled
enabled enabled
External
interrupt
enable
selected
Resource
other than
above
selected
SPL=1
GPIO
selected
Hi-Z/
internal input
fixed
at 0/
analog
input
enabled
Trace
output
Setting
disabled
Setting Setting
disabled disabled
GPIO
selected
Document Number: 001-98708 Rev. *E
Maintain
previous
state
Maintain
previous
state
GPIO
selected,
Hi-Z/internal
Hi-Z/internal internal input input fixed
fixed
at 0
input fixed
at 0
at 0
GPIO
selected
Page 78 of 190
Pin Status Type
S6E2G Series
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
Analog input
selected
O
Hi-Z
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
‐
Device
Internal
Reset
State
‐
‐
INITX=1
SPL=0
SPL=1
Trace
output
External
interrupt
enable
selected
Maintain
previous state
Resource
other than
above
selected
SPL=1
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal internal
Hi-Z/
Hi-Z/
Hi-Z/
internal input
internal input
input
input
internal input
internal input
internal input
fixed
fixed
fixed
fixed
fixed
fixed
fixed
at 0/
at 0/
at 0/
at 0/
at 0/
at 0/
at 0/
analog
analog
analog
analog
analog
analog
analog
input
input
input
input
input enabled
input enabled
input enabled
enabled
enabled
enabled enabled
Trace
selected
Setting
disabled
SPL=0
Setting Setting
disabled disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
GPIO
selected,
Hi-Z/internal
internal input input fixed
fixed
at 0
at 0
Hi-Z/
internal input
fixed
at 0/
analog
input
enabled
GPIO
selected
GPIO
selected
Analog input
selected
P
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
internal internal
Hi-Z/
Hi-Z/
Hi-Z/
internal input
internal input
input
input
internal input
internal input
internal input
fixed
fixed
fixed at fixed at
fixed
fixed
fixed
at 0/
at 0/
0/
0/
at 0/
at 0/
at 0/
analog
analog
analog
analog
analog
analog
analog
input
input
input
input
input enabled
input enabled
input enabled
enabled
enabled
enabled enabled
WKUP
enabled
Resource
other than
above
selected
Maintain
previous state
Setting
disabled
Setting Setting
disabled disabled
GPIO
selected
Document Number: 001-98708 Rev. *E
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z/
internal input
fixed
at 0/
analog
input
enabled
Hi-Z/
WKUP input
enabled
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Page 79 of 190
Pin Status Type
S6E2G Series
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
‐
Device
Internal
Reset
State
‐
‐
INITX=1
SPL=0
WKUP
enabled
External
interrupt
enable
selected
Setting
disabled
Resource
other than
above
selected
Maintain
previous
state
Setting Setting
disabled disabled
Maintain
previous
state
Q
SPL=1
Hi-Z
Hi-Z/
Hi-Z/
input
input
enabled enabled
Hi-Z
Hi-Z/
Hi-Z/
Maintain
input
input
previous state
enabled enabled
Maintain
previous
state
SPL=0
SPL=1
-
WKUP input
enabled
Hi-Z/
WKUP
input enabled
WKUP input
enabled
GPIO
selected,
Hi-Z/internal
internal input input fixed
fixed
at 0
Hi-Z/internal
at 0
input fixed
at 0
GPIO
selected
GPIO
selected
GPIO
selected
R
USB I/O pin
S
Setting
disabled
Maintain
previous
state
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
Hi-Z at
Hi-Z at
Hi-Z at
transtranstransmission/
mission/
mission/
input
input
input
Setting Setting
enabled/
enabled/
enabled/
disabled disabled
internal input internal input internal input
fixed
fixed
fixed
at 0 at
at 0 at
at 0 at
reception
reception
reception
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Sub crystal
oscillator
input pin/
external main
clock input
selected
Input
enabled
Input
Input
enabled enabled
Input
enabled
Document Number: 001-98708 Rev. *E
Maintain
previous
state
Input
enabled
Hi-Z/
input
enabled
Hi-Z/
input enabled
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Hi-Z/
input enabled
GPIO
selected
Input
Enabled
Page 80 of 190
Pin Status Type
S6E2G Series
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
T
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
‐
SPL=0
Maintain
previous
state
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
State
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
External main
clock input
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Ethernet I/O
selected
*4
Resource
other than
above
selected
Hi-Z/
Hi-Z/
internal
internal
input fixed
input
at 0/
fixed
or input
at 0
enabled
Setting
disabled
Hi-Z
INITX=1
‐
Maintain
previous
state
Sub crystal
oscillator
output pin
V
Run mode
or Sleep
mode State
‐
Device
Internal
Reset
State
Hi-Z/
internal
input
fixed
at 0
SPL=0
Maintain
previous
state
SPL=1
Hi-Z/internal
input fixed
at 0
-
Maintain previous state while oscillator active/
When oscillation stops*5, it will be Hi-Z/
Internal input fixed at 0
Maintain
previous
state
Setting Setting
disabled disabled
Hi-Z/
Hi-Z/
input
input
enabled enabled
SPL=1
Maintain
previous
state
Maintain
previous
state
GPIO
selected,
Hi-Z/internal
internal input input fixed
fixed
at "0
Hi-Z/internal
at 0
input fixed
at 0
GPIO
selected
GPIO
selected
Document Number: 001-98708 Rev. *E
Page 81 of 190
Pin Status Type
S6E2G Series
Function
Group
Power-On
Reset or
LowVoltage
Detection
State
INITX
Input
State
Power
Supply
Unstable
‐
‐
Run mode
or Sleep
mode State
Timer mode,
RTC mode, or
Stop mode State
Deep Standby RTC
mode or Deep Standby
Stop mode State
Return from
Deep
Standby
mode State
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power
Supply
Stable
INITX=0 INITX=1
INITX=1
INITX=1
INITX=1
‐
Device
Internal
Reset
State
‐
‐
INITX=1
SPL=0
Ethernet
input/output
selected*4
W
External
interrupt
enable
selected
Resource
other than
above
selected
Setting
disabled
GPIO
selected
S
T
Maintain
previous
state
Setting Setting
disabled disabled
Maintain
previous
state
Hi-Z
SPL=1
SPL=1
-
GPIO
selected,
Hi-Z/internal
internal input input fixed
fixed
at 0
at 0
GPIO
selected
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Maintain
previous
state
Hi-Z/
Hi-Z/
input
input
enabled enabled
SPL=0
Hi-Z/internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Sub crystal
oscillator
input pin/
external main
clock input
selected
Input
enabled
Input
Input
enabled enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z/internal
selected,
Hi-Z/internal
input fixed internal input input fixed
at 0
fixed
at 0
at 0
GPIO
selected
Maintain
previous
state
Hi-Z/internal
input fixed
at 0
Maintain
previous
State
GPIO
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
External main
clock input
selected
Setting
disabled
Setting Setting
disabled disabled
Maintain
previous
state
Sub crystal
oscillator
output pin
Hi-Z/
Hi-Z/
internal
internal
input fixed
input
at 0/
fixed
or input
at 0
enabled
Document Number: 001-98708 Rev. *E
Hi-Z/
internal
input
fixed
at 0
Maintain
previous
state
Input
enabled
Input
enabled
Maintain
previous
state
Input
enabled
Hi-Z/internal
input fixed
at 0
Input
Enabled
Maintain previous state while oscillator active/
When oscillation stops*5, it will be Hi-Z/
Internal input fixed at 0
Page 82 of 190
S6E2G Series
1: Oscillation is stopped at Sub Timer mode, sub CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode,
and Deep Standby Stop mode.
2: Maintain previous state at Timer mode. GPIO selected internal input fixed at 0 at RTC mode, Stop mode.
3: Maintain previous state at Timer mode. Hi-Z/internal input fixed at 0 at RTC mode, Stop mode.
4: It shows the case selected by EPFR14.E_SPLC register.
Document Number: 001-98708 Rev. *E
Page 83 of 190
S6E2G Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS - 0.5
VSS + 6.5
V
Power supply voltage (for USB) *1,*3
USBVCC0
VSS - 0.5
VSS + 6.5
V
USB) *1,*3
USBVCC1
VSS - 0.5
VSS + 6.5
V
ETHVCC
VSS - 0.5
VSS + 6.5
V
AVCC
VSS - 0.5
VSS + 6.5
V
AVRH
VSS - 0.5
VSS + 6.5
V
VSS - 0.5
VCC + 0.5 (≤ 6.5 V)
V
Except for USB and
Ethernet-MAC pin
VSS - 0.5
USBVCC0 + 0.5 (≤ 6.5 V)
V
USB ch 0 pin
VSS - 0.5
USBVCC1 + 0.5 (≤ 6.5 V)
V
USB ch 1 pin
VSS - 0.5
ETHVCC + 0.5 (≤ 6.5 V)
V
Ethernet-MAC Pin
VSS - 0.5
VSS + 6.5
V
5 V tolerant
VIA
VSS - 0.5
AVCC + 0.5 (≤ 6.5 V)
V
VO
VSS - 0.5
VCC + 0.5 (≤ 6.5 V)
V
10
mA
4 mA type
20
mA
8 mA type
20
mA
12 mA type
22.4
mA
I2C Fm+
4
mA
4 mA type
8
mA
8 mA type
12
mA
12 mA type
20
mA
I2C Fm+
Power supply voltage*1,*2
Power supply voltage (for
Power supply voltage (for Ethernet-MAC) *1, *4
Analog power supply voltage
*1 ,*5
Analog reference voltage
Input voltage
*1
VI
Analog pin input voltage
Output voltage
*1 ,*5
*1
*1
L level maximum output current *6
IOL
L level average output current *7
IOLAV
L level total maximum output current
L level total average output
current*8
H level maximum output current *6
H level average output current
H level total average output current
Storage temperature
-
100
mA
∑IOLAV
-
50
mA
- 10
mA
4 mA type
-20
mA
8 mA type
- 20
mA
12 mA type
-4
mA
4 mA type
-8
mA
8 mA type
- 12
mA
12 mA type
IOHAV
H level total maximum output current
*8
-
∑IOL
IOH
*7
-
-
-
∑IOH
-
- 100
mA
∑IOHAV
-
- 50
mA
TSTG
- 55
+ 150
°C
1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
Document Number: 001-98708 Rev. *E
Page 84 of 190
S6E2G Series
2: VCC must not drop below VSS - 0.5 V.
3: USBVCC0, USBVCC1 must not drop below VSS - 0.5 V.
4: ETHVCC must not drop below VSS - 0.5 V.
5: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on.
6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100-ms period.
8: The total average output current is defined as the average current value flowing through all of corresponding pins for a
100-ms period.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 001-98708 Rev. *E
Page 85 of 190
S6E2G Series
12.2 Recommended Operating Conditions
Parameter
Power supply voltage
Power supply voltage (for USB ch 0)
Power supply voltage (for USB ch 1)
Power supply voltage (for
Ethernet-MAC)
Conditions
VCC
-
USBVCC0
-
USBVCC1
ETHVCC
Analog power supply voltage
Value
Min
Max
2.7*10
5.5
3.0
3.6 (≤VCC)
V
*1
2.7
5.5 (≤VCC)
3.0
3.6 (≤VCC)
*2
*3
V
2.7
5.5 (≤VCC)
*4
3.0
3.6 (≤VCC)
*5
4.5
5.5 (≤VCC)
2.7
5.5 (≤VCC)
V
*5
*6
-
2.7
5.5
V
AVRH
-
*9
AVCC
V
AVRL
-
AVSS
AVSS
V
CS
-
1
10
μF
Junction temperature
TJ
-
- 40
+ 125
°C
Ambient temperature
TA
-
-40
*8
°C
Smoothing capacitor
Remarks
V
-
-
Unit
AVCC
Analog reference voltage
Operating
temperature
Symbol
AVCC = VCC
for built-in regulator *7
1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0)
2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80)
3: When P83/UDP1 and P82/UDM1 pins are used as USB (UDP1, UDM1)
4: When P83/UDP1 and P82/UDM1 pins are used as GPIO (P83, P82)
5: When the pins in Ethernet-MAC Timing, except P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS pin, are used as
Ethernet-MAC pin
6: When the pins in Ethernet-MAC Timing, except P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS pin, are used as function
pins
7: See "C pin" in 9 Handling Devices for the connection of the smoothing capacitor.
8: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction
temperature (TJ).
The calculation formula of the ambient temperature (TA) is:
TA (Max) = TJ(Max) - Pd(Max) × θJA
Pd:
θJA:
Power dissipation (W)
Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL:
IOH:
VOL:
VOH:
L level output current
H level output current
L level output voltage
H level output voltage
9: The minimum value of analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5.
12-bit A/D Converter for the details.
10: For the voltage range between VCC(min) and the low voltage detection reset (VDH), the MCU must be clocked from either
the High-speed CR or the low-speed CR.
Document Number: 001-98708 Rev. *E
Page 86 of 190
S6E2G Series
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for Package Thermal Resistance and Maximum Permissible Power
Package
LQS144
(0.5-mm pitch)
LQP176
(0.5-mm pitch)
Thermal
Printed
Resistance
Circuit Board
θja
(°C/W)
Maximum Permissible Power
(mW)
TA = +85 °C
TA = +105 °C
Single-layered
both sides
48
833
417
4 layers
33
1212
606
Single-layered
both sides
45
889
444
4 layers
31
1290
645
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure.
−
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 001-98708 Rev. *E
Page 87 of 190
S6E2G Series
Ethernet-MAC Pins
Pin Name
Except For
Ethernet-MAC
Function
Ethernet-MAC
Function
P6E/ADTG_5/SCK4_1/INT29_0/E_PPS
E_PPS *
P6E/ADTG_5/SCK4_1/INT29_0
PC0/E_RXER
E_RXER
PC0
PC1/TIOB6_0/E_RX03
E_RX03
PC1/TIOB6_0
PC2/TIOA6_0/E_RX02
E_RX02
PC2/TIOA6_0
PC3/TIOB7_0/E_RX01
E_RX01
PC3/TIOB7_0
PC4/TIOA7_0/E_RX00
E_RX00
PC4/TIOA7_0
PC5/TIOB14_0/E_RXDV
E_RXDV
PC5/TIOB14_0
PC6/TIOA14_0/E_MDIO
E_MDIO
PC6/TIOA14_0
PC7/INT13_0/E_MDC/CROUT_1
E_MDC
PC7/INT13_0/CROUT_1
PC8/E_RXCK_REFCK
E_RXCK_REFCK PC8
PC9/TIOB15_0/E_COL
E_COL
PC9/TIOB15_0
PCA/TIOA15_0/E_CRS
E_CRS
PCA/TIOA15_0
PCB/INT28_0/E_COUT
E_COUT
PCB/INT28_0
PCC/E_TCK
E_TCK
PCC
PCD/SOT4_1/INT14_0/E_TXER
E_TXER
PCD/SOT4_1/INT14_0
PCE/SIN4_1/INT15_0/E_TX03
E_TX03
PCE/SIN4_1/INT15_0
PCF/RTS4_1/INT12_0/E_TX02
E_TX02
PCF/RTS4_1/INT12_0
PD0/INT30_1/E_TX01
E_TX01
PD0/INT30_1
PD1/INT31_1/E_TX00
E_TX00
PD1/INT31_1
PD2/CTS4_1/E_TXEN
E_TXEN
PD2/CTS4_1
Power
Supply
Type
VCC
ETHVCC
*: It is used to confirm the PTP counter cycle in Ethernet-MAC by waveforms.
Document Number: 001-98708 Rev. *E
Page 88 of 190
S6E2G Series
Calculation Method of Power Dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL:
L level output current
IOH:
H level output current
VOL:
L level output voltage
VOH:
H level output voltage
ICC is the current drawn by the device.
It can be analyzed as follows.
ICC = ICC (INT) + ΣICC (IO)
ICC (INT): Current drawn by internal logic and memory, etc. through the regulator
ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin
For ICC (INT), it can be anticipated by "(1) Current Rating" in "12.3. DC Characteristics" (This rating value does not include ICC (IO)
for a value at pin fixed).
For ICC (IO), it depends on system used by customers.
The calculation formula is shown below.
ICC (IO) =
(CINT + CEXT) × VCC × fSW
CINT:
Pin internal load capacitance
CEXT:
External load capacitance of output pin
fSW:
Pin switching frequency
Parameter
Pin internal load
capacitance
Symbol
CINT
Conditions
Capacitance Value
4 mA type
1.93 pF
8 mA type
3.45 pF
12 mA type
3.42 pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself:
Measure current value ICC (Typ) at normal temperature (+25°C).
Add maximum leakage current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC (Typ) + ICC (leak_max)
Parameter
Maximum leakage current
at operating
Symbol
ICC (leak_max)
Document Number: 001-98708 Rev. *E
Conditions
Current Value
TJ = +125 °C
53.6 mA
TJ = +105 °C
26.6 mA
TJ = +85 °C
17.5 mA
Page 89 of 190
S6E2G Series
Current Explanation Diagram
Pd=VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC=ICC (INT)＋ΣICC (IO)
VCC
A
ICC
Chip
ICC (INT)
ΣICC (IO)
A
Regulator
VOL
V
A
・・・
V
IOL
Flash
VOH
・・・
Logic
IOH
RAM
ICC (IO)
CEXT
・・・
Document Number: 001-98708 Rev. *E
Page 90 of 190
S6E2G Series
12.3 DC Characteristics
12.3.1
Current Rating
Table 12-1 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory
(Flash Accelerator Mode and Trace Buffer Function Enabled)
Parameter
Symbol
Pin
Name
Frequency*4
Conditions
*5
*6
Power
supply
current
ICC
VCC
Normal
operation
*7,*8
(PLL)
*5
*6
Value
Unit
Typ*1
Max*2
180 MHz
73
131
mA
160 MHz
65
123
mA
144 MHz
59
117
mA
120 MHz
50
108
mA
100 MHz
43
101
mA
80 MHz
35
93
mA
60 MHz
27
85
mA
40 MHz
19
77
mA
20 MHz
11
69
mA
8 MHz
6.9
64
mA
4 MHz
5.3
63
mA
180 MHz
44
102
mA
160 MHz
40
98
mA
144 MHz
36
94
mA
120 MHz
31
89
mA
100 MHz
27
85
mA
80 MHz
22
80
mA
60 MHz
17
75
mA
40 MHz
13
71
mA
20 MHz
7.9
65
mA
8 MHz
5.2
63
mA
4 MHz
4.3
62
mA
Remarks
*3
When all peripheral
clocks are on
*3
When all peripheral
clocks are off
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1)
6: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
7: Firmware being executed during data collection for this table is not being accessed from the MainFlash memory.”
8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 91 of 190
S6E2G Series
Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled)
Parameter
Symbol
Pin
Name
Frequency*4
Conditions
*5
*6
Power
supply
current
ICC
VCC
Normal
operation
*7,*8
(PLL)
*5
*6
Value
Unit
Remarks
Typ*1
Max*2
180 MHz
82
140
mA
160 MHz
74
132
mA
144 MHz
68
126
mA
120 MHz
58
116
mA
100 MHz
49
107
mA
*3
80 MHz
40
98
mA
60 MHz
31
89
mA
When all peripheral
clocks are on
40 MHz
22
80
mA
20 MHz
13
71
mA
8 MHz
7.5
65
mA
4 MHz
5.6
63
mA
180 MHz
48
106
mA
160 MHz
44
102
mA
144 MHz
41
99
mA
120 MHz
35
93
mA
100 MHz
30
88
mA
*3
80 MHz
25
83
mA
60 MHz
20
78
mA
When all peripheral
clocks are off
40 MHz
14
72
mA
20 MHz
8.7
66
mA
8 MHz
5.6
63
mA
4 MHz
4.5
62
mA
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 0)
6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
7: With data access to a MainFlash memory.
8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 92 of 190
S6E2G Series
Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running
from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait)
Parameter
Symbol
Pin
Name
Frequency*4
Conditions
*5
Power
supply
current
ICC
VCC
Normal
operation
*6,*7
(PLL)
*5
Value
Unit
Typ*1
Max*2
72 MHz
54
112
mA
60 MHz
47
105
mA
48 MHz
39
97
mA
36 MHz
31
89
mA
24 MHz
23
81
mA
12 MHz
14
72
mA
8 MHz
11
69
mA
4 MHz
7.2
65
mA
72 MHz
37
95
mA
60 MHz
33
91
mA
48 MHz
28
86
mA
36 MHz
23
81
mA
24 MHz
17
75
mA
12 MHz
11
69
mA
8 MHz
8.3
66
mA
4 MHz
5.9
63
mA
Remarks
*3
When all peripheral
clocks are on
*3
When all peripheral
clocks are off
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)
6: With data access to a MainFlash memory.
7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 93 of 190
S6E2G Series
Table 12-4 Typical and Maximum Current Consumption in Normal Operation (Other than PLL), Code with Data Accessing
Running from Flash Memory (Flash 0 Wait-Cycle Mode and Read Access 0 Wait)
Parameter
Symbol
Pin
Name
Normal
operation
*6, *7
(main
oscillation)
Power
supply
current
ICC
VCC
Frequency*4
Conditions
Normal
operation
*6
(built-in
High-speed
CR)
*5
Value
Unit
Remarks
Typ*1
Max*2
4.3
62
mA
*3
When all peripheral
clocks are on
3.7
61
mA
*3
When all peripheral
clocks are off
4 MHz
*3
*5
3.5
61
mA
2.9
60
mA
0.47
58
mA
4 MHz
When all peripheral
clocks are on
*3
When all peripheral
clocks are off
*3
Normal
operation
*6, *8
(sub
oscillation)
Normal
operation
*6
(built-in
low-speed
CR)
*5
32 kHz
When all peripheral
clocks are on
*3
0.46
58
mA
0.51
58
mA
0.50
58
mA
When all peripheral
clocks are off
*3
*5
100 kHz
When all peripheral
clocks are on
*3
When all peripheral
clocks are off
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)
6: With data access to a MainFlash memory.
7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
8: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 94 of 190
S6E2G Series
Table 12-5 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2
Parameter
Power
supply
current
Symbol
ICCS
Pin
Name
VCC
Conditions
Sleep
operation*5
(PLL)
Frequency*4
Value
Typ*
1
Max*2
Unit
180 MHz
58
116
mA
160 MHz
52
110
mA
144 MHz
48
106
mA
120 MHz
40
98
mA
100 MHz
35
93
mA
80 MHz
28
86
mA
60 MHz
22
80
mA
40 MHz
16
74
mA
20 MHz
9.7
67
mA
8 MHz
6.2
64
mA
4 MHz
5.0
63
mA
180 MHz
30
88
mA
160 MHz
27
85
mA
144 MHz
25
83
mA
120 MHz
21
79
mA
100 MHz
18
76
mA
80 MHz
15
73
mA
60 MHz
12
70
mA
40 MHz
9.3
67
mA
20 MHz
6.2
64
mA
8 MHz
4.5
62
mA
4 MHz
4.0
62
mA
Remarks
*3
When all peripheral clocks
are on
*3
When all peripheral clocks
are off
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 95 of 190
S6E2G Series
Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK
Parameter
Power
supply
current
Symbol
ICCS
Pin
Name
VCC
Conditions
Sleep
operation*5
(PLL)
Frequency*4
Value
Typ*
1
Max*2
Unit
72 MHz
32
90
mA
60 MHz
27
85
mA
48 MHz
23
81
mA
36 MHz
18
76
mA
24 MHz
13
71
mA
12 MHz
8.5
66
mA
8 MHz
6.9
64
mA
4 MHz
5.3
63
mA
72 MHz
15
73
mA
60 MHz
13
71
mA
48 MHz
11
69
mA
36 MHz
9.3
67
mA
24 MHz
7.3
65
mA
12 MHz
5.4
63
mA
8 MHz
4.7
62
mA
4 MHz
4.1
62
mA
Remarks
*3
When all peripheral clocks
are on
*3
When all peripheral clocks
are off
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 96 of 190
S6E2G Series
Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (Other than PLL), when PCLK0 = PCLK1 =
PCLK2 = HCLK/2
Parameter
Symbol
Pin
Name
Conditions
Sleep
operation*5
(main oscillation)
Sleep
operation
(built-in
High-speed CR)
Power
supply
current
ICCS
Frequency*4
Value
Unit
Remarks
60
mA
*3
When all peripheral clocks
are on
2.0
60
mA
*3
When all peripheral clocks
are off
2.0
60
mA
*3
When all peripheral clocks
are on
1.3
59
mA
*3
When all peripheral clocks
are off
0.46
58
mA
*3
When all peripheral clocks
are on
0.45
58
mA
*3
When all peripheral clocks
are off
0.47
58
mA
*3
When all peripheral clocks
are on
0.46
58
mA
*3
When all peripheral clocks
are off
Typ*1
Max*2
2.6
4 MHz
4 MHz
VCC
Sleep
operation*6
(sub oscillation)
Sleep
operation
(built-in
low-speed CR)
32 kHz
100 kHz
1: TA = +25 °C, VCC = 3.3 V
2: TJ = +125 °C, VCC = 5.5 V
3: When all ports are input and are fixed at 0.
4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 97 of 190
S6E2G Series
Table 12-8 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode
Parameter
Symbol
Pin
Name
Conditions
Stop mode
ICCH
Timer mode*5
(main oscillation)
Timer mode
(built-in
High-speed CR)
Power
supply
current
ICCT
Frequency
-
4 MHz
4 MHz
Value
Typ*
1
Max*2
Unit
0.41
1.9
mA
*3, *4
TA = +25°C
-
18
mA
*3, *4
TA = +85°C
-
26
mA
*3, *4
TA = +105°C
1.4
2.9
mA
*3, *4
TA = +25°C
-
19
mA
*3, *4
TA = +85°C
-
27
mA
*3, *4
TA = +105°C
0.71
2.2
mA
*3, *4
TA = +25°C
-
19
mA
*3, *4
TA = +85°C
-
27
mA
*3, *4
TA = +105°C
0.41
1.9
mA
*3, *4
TA = +25°C
-
18
mA
*3, *4
TA = +85°C
-
27
mA
*3, *4
TA = +105°C
0.42
1.9
mA
*3, *4
TA = +25°C
-
18
mA
*3, *4
TA = +85°C
-
27
mA
*3, *4
TA = +105°C
0.42
1.9
mA
*3, *4
TA = +25°C
-
18
mA
*3, *4
TA = +85°C
-
27
mA
*3, *4
TA = +105°C
VCC
Timer mode*6
(sub oscillation)
Timer mode
(built-in
low-speed CR)
ICCR
RTC mode*6
(sub oscillation)
32 kHz
100 kHz
32 kHz
Remarks
1: VCC = 3.3 V
2: VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: When LVD is off
5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)
6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 98 of 190
S6E2G Series
Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode
Parameter
Symbol
Pin
Name
Conditions
Deep standby
Stop mode
(When RAM
is off)
Frequency
-
Value
Typ*
1
Max*2
Unit
89
162
μA
*3, *4
TA = +25°C
-
1689
μA
*3, *4
TA = +85°C
-
2189
μA
*3, *4
TA = +105°C
101
245
μA
*3, *4
TA = +25°C
-
2401
μA
*3, *4
TA = +85°C
-
3223
μA
*3, *4
TA = +105°C
93
166
μA
*3, *4
TA = +25°C
-
1693
μA
*3, *4
TA = +85°C
-
2193
μA
*3, *4
TA = +105°C
105
249
μA
*3, *4
TA = +25°C
-
2405
μA
*3, *4
TA = +85°C
-
3227
μA
*3, *4
TA = +105°C
ICCHD
Deep standby
Stop mode
(When RAM
is on)
Power
supply
current
-
VCC
Deep standby
RTC mode*6
(When RAM
is off)
32 kHz
ICCRD
Deep standby
RTC mode*6
(When RAM
is on)
Remarks
1: VCC = 3.3 V
2: VCC = 5.5 V
3: When all ports are input and are fixed at 0
4: When LVD is off
5: When sub oscillation is off
6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)
Document Number: 001-98708 Rev. *E
Page 99 of 190
S6E2G Series
Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/Erase
Parameter
Low-voltage
detection
circuit (LVD)
power supply
current
MainFlash
memory
write/erase
current
Symbol
Pin
Name
ICCLVD
Conditions
Value
Unit
Remarks
Min
Typ
Max
At operation
-
4
7
μA
For occurrence of
interrupt
At
write/erase
-
13.4
15.9
mA
*1
VCC
ICCFLASH
1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power
supply current (ICC).
Table 12-11 Peripheral Current Dissipation
Clock
System
HCLK
PCLK1
PCLK2
Peripheral
Unit
GPIO
Frequency (MHz)
45
90
180
All ports
0.69
1.39
2.76
DMAC
-
0.74
1.46
2.83
DSTC
-
0.58
1.13
2.12
External bus I/F
-
0.23
0.44
0.87
SD card I/F
-
0.56
1.10
2.18
CAN
1 ch
0.09
0.10
0.12
USB
1 ch
0.41
0.83
1.64
Ethernet-MAC
-
1.52
2.97
5.84
Base timer
4 ch
0.38
0.76
1.50
Multi-functional
timer/PPG
1 unit/4 ch
0.72
1.43
2.83
Quadrature
position/revolution
counter
1 unit
0.06
0.12
0.22
A/D converter
1 unit
0.31
0.61
1.22
Multi-function serial
1 ch
0.36
0.72
-
IC Card Interface
1 ch
0.27
0.54
-
I2S clock generator
1 ch
0.26
0.53
-
Document Number: 001-98708 Rev. *E
Unit
Remarks
mA
TA=+25°C,
VCC=3.3 V
mA
TA=+25°C,
VCC=3.3 V
mA
TA=+25°C,
VCC=3.3 V
Page 100 of 190
S6E2G Series
12.3.2
Pin Characteristics
(VCC = USBVCC0 = USBVCC1 = ETHVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter
H level input
voltage
(hysteresis
input)
L level input
voltage
(hysteresis
input)
Symbol
Pin Name
Conditions
CMOS hysteresis input pin,
MD0, MD1
-
MADATAxx
Remarks
Typ
Max
VCC×0.8
-
VCC + 0.3
V
ETHVCC×0.8
-
ETHVCC + 0.3
V
VCC > 3.0 V,
VCC ≤ 3.6 V,
2.4
-
VCC + 0.3
V
5V tolerant input pin
-
VCC×0.8
-
VSS + 5.5
V
Input pin doubled as I2C Fm+
-
VCC×0.7
-
VSS + 5.5
V
TTL Schmitt input pin
-
2.0
-
ETHVCC+0.3
V
CMOS hysteresis input pin,
MD0, MD1
VSS - 0.3
-
VCC×0.2
V
-
VSS - 0.3
-
ETHVCC×0.2
V
5V tolerant input pin
-
VSS - 0.3
-
VCC×0.2
V
Input pin doubled as I2C Fm+
-
VSS
-
VCC×0.3
V
TTL Schmitt input pin
-
VSS - 0.3
-
0.8
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
ETHVCC
V
VCC - 0.5
-
VCC
V
ETHVCC - 0.5
-
ETHVCC
V
VCC - 0.5
-
VCC
V
USBVCC - 0.4
-
USBVCC
V
*1
VCC - 0.5
-
VCC
V
At GPIO
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 2 mA
4 mA type
ETHVCC ≥ 4.5 V,
IOH = - 4 mA
ETHVCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 8 mA
VCC < 4.5 V,
IOH = - 4 mA
8 mA type
H level output
voltage
Unit
Min
VIHS
VILS
Value
VOH
ETHVCC ≥ 4.5 V,
IOH = - 8 mA
ETHVCC < 4.5 V,
IOH = - 4 mA
12 mA type
The pin
doubled as USB I/O
The pin doubled as I2C Fm+
Document Number: 001-98708 Rev. *E
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
IOH = - 20.5 mA
USBVCC < 4.5 V,
IOH = - 13.0 mA
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5V,
IOH = - 3 mA
At External
Bus
Page 101 of 190
S6E2G Series
Parameter
Symbol
Pin Name
VCC ≥ 4.5 V,
IOL = 4 mA
4 mA type
VCC < 4.5 V,
IOL = 2 mA
ETHVCC ≥ 4.5 V,
IOL = 4 mA
RTHVCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 8 mA
8 mA type
L level output
voltage
VCC < 4.5 V,
IOL = 4 mA
ETHVCC ≥ 4.5 V,
IOL = 8 mA
RTHVCC < 4.5 V,
IOL = 4 mA
VOL
12 mA type
The pin doubled
as USB I/O
Value
Conditions
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
USBVCC ≥ 4.5 V,
IOL = 18.5 mA
USBVCC < 4.5 V,
IOL = 10.5 mA
Unit
Min
Typ
Max
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
VCC ≥ 4.5 V,
IOL = 4 mA
The pin doubled
as I2C Fm+
VCC < 4.5 V,
IOL = 3 mA
Pull-up
resistor value
Input
capacitance
IIL
-
RPU
Pull-up pin
CIN
Other than
VCC,
USBVCC0,
USBVCC1,
ETHVCC,
VSS,
AVCC, AVSS,
AVRH
*1
At GPIO
VSS
-
0.4
V
At I2C
Fm+
VCC ≤ 4.5 V,
IOL = 20 mA
Input leak
current
Remarks
-
-5
-
+5
VCC ≥ 4.5 V
25
50
100
VCC < 4.5 V
30
80
200
-
-
5
15
μA
kΩ
pF
1: USBVCC0 and USBVCC1 are described as USBVCC.
Document Number: 001-98708 Rev. *E
Page 102 of 190
S6E2G Series
12.4 AC Characteristics
12.4.1
Main Clock Input Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40C to +105C)
Parameter
Input frequency
Input clock cycle
Input clock pulse width
Input clock rise time and
fall time
Internal operating clock *1
frequency
Internal operating clock *1
cycle time
Symbol
Pin
Name
Value
Conditions
Unit
Min
Max
VCC ≥4.5 V
4
48
VCC < 4.5 V
4
20
VCC ≥4.5 V
4
48
VCC < 4.5 V
4
20
VCC ≥4.5 V
20.83
250
VCC < 4.5 V
50
250
-
PWH/tCYLH,
PWL/tCYLH
45
tCF,
tCR
-
fCH
tCYLH
X0,
X1
Remarks
MHz
When crystal oscillator is
connected
MHz
When using external clock
ns
When using external clock
55
%
When using external clock
-
5
ns
When using external clock
fCC
-
-
-
180
MHz
Base clock (HCLK/FCLK)
fCP0
-
-
-
90
MHz
APB0bus clock *2
fCP1
-
-
-
180
MHz
APB1bus clock *2
fCP2
-
-
-
90
MHz
APB2bus clock *2
tCYCC
-
-
5.56
-
ns
Base clock (HCLK/FCLK)
tCYCP0
-
-
11.1
-
ns
APB0bus clock *2
tCYCP1
-
-
5.56
-
ns
APB1bus clock *2
tCYCP2
-
-
11.1
-
ns
APB2bus clock *2
1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main
Part (002-04856).
2: For more about each APB bus to which each peripheral is connected, see 1. S6E2G Series Block Diagram in this data
sheet.
X0
Document Number: 001-98708 Rev. *E
Page 103 of 190
S6E2G Series
12.4.2
Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Input frequency
Pin
Name
Value
Conditions
Unit
Remarks
-
kHz
When crystal
oscillator is connected
-
100
kHz
When using external
clock
10
-
31.25
μs
When using external
clock
45
-
55
%
When using external
clock
Min
Typ
Max
-
-
32.768
-
32
tCYLL
-
-
PWH/tCYLL,
PWL/tCYLL
1/tCYLL
X0A,
X1A
Input clock cycle
Input clock pulse width
*
*: For more information about crystal oscillator, see Sub crystal oscillator in 9. Handling Devices.
tCYLL
0.8 × VCC
0.8 × VCC
0.2 × VCC
X0A
PWH
12.4.3
0.8 × VCC
0.2 × VCC
PWL
Built-In CR Oscillation Characteristics
Built-In High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Clock frequency
Frequency
stabilization
time
Symbol
fCRH
Value
Conditions
Min
Typ
Max
TJ = - 20°C to + 105°C
3.92
4
4.08
TJ = - 40°C to + 125°C
3.88
4
4.12
TJ = - 40°C to + 125°C
2.9
4
5
-
-
-
30
tCRWT
Unit
MHz
Remarks
When trimmed
*1
When not trimmed
μs
*2
1: In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming
2: This is the time to stabilize the frequency of the High-speed CR clock after setting trimming value. During this period, it is
able to use the High-speed CR clock as a source clock.
Built-In Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Condition
Clock frequency
fCRL
-
Document Number: 001-98708 Rev. *E
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
Page 104 of 190
S6E2G Series
12.4.4
Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Min
Typ
Max
Unit
PLL oscillation stabilization wait time*1
(lock up time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
4
-
16
MHz
-
13
-
100
multiplier
fPLLO
200
-
400
MHz
fCLKPLL
-
-
180
MHz
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
Remarks
1: Time from when the PLL starts operating until the oscillation stabilizes
2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual
Main Part (002-04856).
12.4.5
Operating Conditions of USB/Ethernet PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
PLL oscillation stabilization wait time*1
(lock up time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
4
-
16
MHz
-
13
-
100
multiplier
fPLLO
200
-
400
MHz
USB/Ethernet
fCLKPLL
-
-
50
MHz
After the M
frequency division
PLL multiplication rate
PLL macro oscillation clock frequency
USB/Ethernet clock frequency
*2
1: Time from when the PLL starts operating until the oscillation stabilizes
2: For more information about USB/Ethernet clock, see Chapter 2-2: USB/Ethernet Clock Generation in FM4 Family
Peripheral Manual Communication Macro Part (002-04862).
Document Number: 001-98708 Rev. *E
Page 105 of 190
S6E2G Series
12.4.6
Operating Conditions of Main PLL (in the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Min
Typ
Max
Unit
PLL oscillation stabilization wait time*1
(lock up time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
-
50
-
95
multiplier
fPLLO
190
-
400
MHz
fCLKPLL
-
-
180
MHz
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency *2
Remarks
1: Time from when the PLL starts operating until the oscillation stabilizes
2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part
(002-04856).
Note:
−
The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main
PLL.
12.4.7
Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Reset input time
Symbol
Pin Name
Conditions
tINITX
INITX
-
Document Number: 001-98708 Rev. *E
Value
Min
Max
500
-
Unit
Remarks
ns
Page 106 of 190
S6E2G Series
12.4.8
Power-On Reset Timing
(VSS = 0V)
Pin
Symbol Name
Parameter
Power supply shut down time
Power ramp rate
Time until releasing Power-on reset
VCC
Unit
Min
Typ
Max
-
1
-
-
VCC: 0.2V to 2.70V
0.6
-
1000
-
0.33
-
0.60
tOFF
dV/dt
Value
Conditions
tPRT
ms
Remarks
*1
mV/µs *2
ms
1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 7.
2.7V
VCC
VDH
0.2V
0.2V
dV/dt
0.2V
tPRT
Internal RST
tOFF
release
RST Active
CPU Operation
start
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics”.
12.4.9
GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Output frequency
Symbol
Pin Name
tPCYCLE
Pxx*
Conditions
Value
Unit
Min
Max
VCC ≥ 4.5V
-
50
MHz
VCC < 4.5V
-
32
MHz
Remarks
*: GPIO is a target.
Pxx
tPCYCLE
Document Number: 001-98708 Rev. *E
Page 107 of 190
S6E2G Series
12.4.10 External Bus Timing
External Bus Clock Output Characteristics
Parameter
Symbol
Pin Name
tCYCLE
MCLKOUT *1
Output frequency
Value
Conditions
Min
Max
-
50 *2
Unit
Remarks
MHz
1: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral
Manual Main Part (002-04856).
2: Generate MCLKOUT at setting more than four divisions when the AHB bus clock exceeds 100 MHz.
0.8 × VCC
0.8 × Vcc
0.8
×Vcc
VCC
0.8 ×
MCLK
tCYCLE
External Bus Signal I/O Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Signal input characteristics
Signal output characteristics
Input signal
Document Number: 001-98708 Rev. *E
Conditions
VIH
VIL
-
VOH
VOL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
Page 108 of 190
S6E2G Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
tOEW
MOEX
MCSX↓→Address
output delay time
tCSL – AV
MOEX↑→Address
hold time
tOEH - AX
MCSX↓→
MOEX↓delay time
tCSL - OEL
MOEX↑→
MCSX↑time
tOEH - CSH
MOEX
Minimum pulse width
MCSX↓→
MDQM↓delay time
Value
Unit
Min
Max
-
MCLK×n-3
-
ns
MCSX[7: 0],
MAD[24: 0]
-
-9
+9
ns
MOEX,
MAD[24: 0]
-
0
MCLK×m+9
ns
-
MCLK×m-9
MCLK×m+9
ns
-
0
MCLK×m+9
ns
MOEX,
MCSX[7: 0]
tCSL - RDQML
MCSX,
MDQM[3: 0]
-
MCLK×m-9
MCLK×m+9
ns
Data set up→MOEX↑
time
tDS - OE
MOEX,
MADATA[31: 0]
-
20
-
ns
MOEX↑→
Data hold time
tDH - OE
MOEX,
MADATA[31: 0]
-
0
-
ns
MWEX
Minimum pulse width
tWEW
MWEX
-
MCLK×n-3
-
ns
MWEX↑→Address
output delay time
tWEH - AX
MWEX,
MAD[24: 0]
-
0
MCLK×m+9
ns
MCSX↓→
MWEX↓delay time
tCSL - WEL
-
MCLK×n-9
MCLK×n+9
ns
MWEX↑→
MCSX↑delay time
tWEH - CSH
-
0
MCLK×m+9
ns
MCSX↓→
MDQM↓delay time
tCSL-WDQML
MCSX,
MDQM[3: 0]
-
MCLK×n-9
MCLK×n+9
ns
tCSL-DX
MCSX,
MADATA[31: 0]
-
MCLK-9
MCLK+9
ns
tWEH - DX
MWEX,
MADATA[31: 0]
-
0
MCLK×m+9
ns
MCSX↓→
Data output time
MWEX↑→
Data hold time
MWEX,
MCSX[7: 0]
Remarks
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
Document Number: 001-98708 Rev. *E
Page 109 of 190
S6E2G Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7: 0]
tCSL-AV
MAD[24: 0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1: 0]
tCSL-WEL
tWEW
MWEX
tDS-OE
MADATA[15: 0]
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DX
Document Number: 001-98708 Rev. *E
Page 110 of 190
S6E2G Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
tAV
MCLK,
MAD[24: 0]
Address delay time
tCSL
MCSX delay time
tCSH
Unit
Min
Max
-
1
9
ns
MCLK,
MCSX[7: 0]
-
1
9
ns
-
1
9
ns
MCLK,
MOEX
-
1
9
ns
-
1
9
ns
tREL
MOEX delay time
Value
tREH
Data set up
→MCLK↑ time
tDS
MCLK,
MADATA[31: 0]
-
19
-
ns
MCLK↑→
Data hold time
tDH
MCLK,
MADATA[31: 0]
-
0
-
ns
MCLK,
MWEX
-
1
9
ns
-
1
9
ns
MCLK,
MDQM[3: 0]
-
1
9
ns
-
1
9
ns
MWEX delay time
MDQM[1: 0]
delay time
tWEL
tWEH
tDQML
tDQMH
MCLK↑→
Data output time
tODS
MCLK,
MADATA[31: 0]
-
MCLK+1
MCLK+18
ns
MCLK↑→
Data hold time
tOD
MCLK,
MADATA[31: 0]
-
1
18
ns
Remarks
Note:
−
When the external load capacitance CL = 30 pF
tCYCLE
MCLK
tCSL
tCSH
MCSX[7: 0]
tAV
tAV
Address
MAD[24: 0]
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[3: 0]
MWEX
MADATA[31: 0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
Document Number: 001-98708 Rev. *E
Page 111 of 190
S6E2G Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Multiplexed
address delay time
Multiplexed address hold
time
Symbol
tALE-CHMADV
tCHMADH
Pin Name
MALE,
MAD[24: 0]
Value
Conditions
Unit
Min
Max
-
0
10
ns
-
MCLK×n+0
MCLK×n+10
ns
Remarks
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7: 0]
MALE
MAD [24: 0]
MOEX
MDQM [3: 0]
MWEX
MADATA[31: 0]
Document Number: 001-98708 Rev. *E
Page 112 of 190
S6E2G Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK↑→Multiplexed
address delay time
tCHMADV
MCLK↑→Multiplexed
data output time
tCHMADX
Pin Name
Conditions
MCLK,
MALE
MCLK,
MADATA[31: 0]
Value
Unit
Min
Max
-
1
9
-
1
9
-
1
tOD
ns
-
1
tOD
ns
Remarks
Note:
−
When the external load capacitance CL = 30 pF
MCLK
MCSX[7: 0]
MALE
MAD [24: 0]
MOEX
MDQM [3: 0]
MWEX
MADATA[31: 0]
Document Number: 001-98708 Rev. *E
Page 113 of 190
S6E2G Series
NAND Flash Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
tNREW
MNREX
Data set up
→MNREX↑time
tDS – NRE
MNREX↑→
Data hold time
Value
Unit
Min
Max
-
MCLK×n-3
-
ns
MNREX,
MADATA[31: 0]
-
20
-
ns
tDH – NRE
MNREX,
MADATA[31: 0]
-
0
-
ns
MNALE↑→
MNWEX delay time
tALEH - NWEL
MNALE,
MNWEX
-
MCLK×m-9
MCLK×m+9
ns
MNALE↓→
MNWEX delay time
tALEL - NWEL
MNALE,
MNWEX
-
MCLK×m-9
MCLK×m+9
ns
MNCLE↑→
MNWEX delay time
tCLEH - NWEL
MNCLE,
MNWEX
-
MCLK×m-9
MCLK×m+9
ns
MNWEX↑→
MNCLE delay time
tNWEH - CLEL
MNCLE,
MNWEX
-
0
MCLK×m+9
ns
MNWEX
Min pulse width
tNWEW
MNWEX
-
MCLK×n-3
-
ns
MNWEX↓→
Data output time
tNWEL – DV
MNWEX,
MADATA[31: 0]
-
-9
9
ns
MNWEX↑→
Data hold time
tNWEH – DX
MNWEX,
MADATA[31: 0]
-
0
MCLK×m+9
ns
MNREX
Min pulse width
Remarks
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[31: 0]
Document Number: 001-98708 Rev. *E
Read
Page 114 of 190
S6E2G Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[31: 0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[31: 0]
Document Number: 001-98708 Rev. *E
Write
Page 115 of 190
S6E2G Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
MCLK↑
MRDY input
setup time
Symbol
Pin Name
Conditions
tRDYI
MCLK,
MRDY
-
Value
Min
Max
19
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 001-98708 Rev. *E
Page 116 of 190
S6E2G Series
SDRAM Mode
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Value
Output frequency
tCYCSD
MSDCLK
Address delay time
tAOSD
MSDCLK↑→
Data output delay time
Unit
Unit
Min
Max
-
-
50
MHz
MSDCLK,
MAD[15: 0]
-
2
12
ns
tDOSD
MSDCLK,
MADATA[31: 0]
-
2
12
ns
MSDCLK↑→
Data output Hi-Z time
tDOZSD
MSDCLK,
MADATA[31: 0]
-
2
19.5
ns
MDQM[3: 0] delay time
tWROSD
MSDCLK,
MDQM[1: 0]
-
1
12
ns
MCSX delay time
tMCSSD
MSDCLK,
MCSX8
-
2
12
ns
MRASX delay time
tRASSD
MSDCLK,
MRASX
-
2
12
ns
MCASX delay time
tCASSD
MSDCLK,
MCASX
-
2
12
ns
MSDWEX delay time
tMWESD
MSDCLK,
MSDWEX
-
2
12
ns
MSDCKE delay time
tCKESD
MSDCLK,
MSDCKE
-
2
12
ns
Data set up time
tDSSD
MSDCLK,
MADATA[31: 0]
-
19
-
ns
Data hold time
tDHSD
MSDCLK,
MADATA[31: 0]
-
0
-
ns
Remarks
Note:
−
When the external load capacitance CL = 30 pF
Document Number: 001-98708 Rev. *E
Page 117 of 190
S6E2G Series
tCYCSD
SDRAM Access
MSDCLK
tAOSD
MAD[24:0]
MDQM[1:0]
MCSX
MRASX
MCASX
MSDWEX
MSDCKE
Address
tWROSD
tMCSSD
tRASSD
tCASSD
tMWESD
tCKESD
tDSSD
MADATA[15:0]
tDOSD
MADATA[15:0]
Document Number: 001-98708 Rev. *E
tDHSD
RD
tDOZSD
WD
Page 118 of 190
S6E2G Series
12.4.11 Base Timer Input Timing
Timer Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Input pulse width
Value
Symbol
Pin Name
Conditi
ons
Min
Max
tTIWH, tTIWL
TIOAn/TIOBn
(when using as ECK, TIN)
-
2tCYCP
-
tTIWH
Unit
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Input pulse width
Pin Name
Conditi
ons
Min
Max
tTRGH, tTRGL
TIOAn/TIOBn
(when using as TGIN)
-
2tCYCP
-
tTRGH
TGIN
Value
Symbol
VIHS
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the base timer is
connected, see 1. S6E2G Series Block Diagram in this data sheet.
Document Number: 001-98708 Rev. *E
Page 119 of 190
S6E2G Series
12.4.12 CSIO (SPI) Timing
Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Conditions
-
-
-
Serial clock cycle time
tSCYC
SCKx
SCK↓→SOT delay time
tSLOVI
SCKx,
SOTx
Parameter
Baud rate
Internal shift
clock operation
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
0
-
0
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
10
-
10
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
20
-
20
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
External shift
clock
operation
Notes:
The above characteristics apply to CLK synchronous mode.
−
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 120 of 190
S6E2G Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tF
VIL
tSHSL
VIL
SIN
VIH
tR
tSLOVE
SOT
VIH
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 121 of 190
S6E2G Series
Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Conditions
-
-
-
Serial clock cycle time
tSCYC
SCKx
SCK↑→SOT delay time
tSHOVI
SCKx,
SOTx
Parameter
Baud rate
Internal shift
clock operation
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
SIN→SCK↓ setup time
tIVSLI
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
0
-
0
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↓ setup time
tIVSLE
SCKx,
SINx
10
-
10
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
20
-
20
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
External shift
clock operation
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 122 of 190
S6E2G Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
VIL
tR
tSLSH
VIH
VIH
SIN
VIL
tF
tSHOVE
SOT
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 123 of 190
S6E2G Series
Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Conditions
-
-
-
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
Parameter
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
-
8
-
8
Mbps
SCKx
4tCYCP
-
4tCYCP
-
ns
tSHOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
50
-
30
-
ns
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
0
-
0
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
10
-
10
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
20
-
20
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
Baud rate
Internal shift
clock operation
External shift
clock operation
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 124 of 190
S6E2G Series
tSCYC
VOH
SCK
SOT
VOL
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
MS bit = 0
tSLSH
SCK
SOT
VIH
VIL
tSHSL
V
VIL IH
tF
*V
VIH
tSHOVE
tR
VOH
VOL
OH
VOL
tIVSLE
SIN
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 001-98708 Rev. *E
Page 125 of 190
S6E2G Series
Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Conditions
-
-
-
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
Parameter
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
-
8
-
8
Mbps
SCKx
4tCYCP
-
4tCYCP
-
ns
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↑ setup time
tIVSHI
SCKx,
SINx
50
-
30
-
ns
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
0
-
0
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↑ setup time
tIVSHE
SCKx,
SINx
10
-
10
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
20
-
20
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
Baud rate
Internal shift
clock operation
External shift
clock operation
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 126 of 190
S6E2G Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIL
VIH
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 127 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
Symbol
VCC ≥ 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS↓→SCK↓ setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↓→SCK↓ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
Internal shift
clock
operation
External shift
clock
operation
SCS deselect time
tCSDE
SCS↓→SOT delay time
tDSE
-
40
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 128 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 129 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
Symbol
VCC ≥ 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS↓→SCK↓ setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↓→SCK↓ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
Internal shift
clock
operation
External shift
clock
operation
SCS deselect time
tCSDE
SCS↓→SOT delay time
tDSE
-
40
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 130 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 131 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
SCS↑→SCK↓ setup time
Symbol
VCC ≥ 4.5 V
Conditions
tCSSI
Internal shift
clock
operation
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCK↑→SCS↓ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↑→SCK↓ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↓ hold time
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
External shift
clock
operation
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 132 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 133 of 190
S6E2G Series
When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
Symbol
SCS↑→SCK↑setup time
VCC ≥ 4.5 V
Conditions
tCSSI
Internal shift
clock
operation
Units
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCK↓→SCS↓hold time
tCSHI
SCS deselect time
tCSDI
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
(*3)-50
+5tCYCP
(*3)+50
+5tCYCP
ns
SCS↑→SCK↑setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↓→SCS↓hold time
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
External
shift clock
operation
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 134 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 135 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
SIN→SCK↑ setup time
Parameter
Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
SCKx
4tCYCP
-
4tCYCP
-
ns
tSLOVI
SCKx,
SOTx
- 10
+ 10
- 10
+ 10
ns
tIVSHI
SCKx,
SINx
-
12.5
-
ns
Internal shift
clock operation
14
12.5*
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
5
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 5
-
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↑ setup time
tIVSHE
SCKx,
SINx
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
5
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
External shift
clock operation
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
−
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 136 of 190
S6E2G Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
SCK
VIH
tF
SOT
VIL
VIL
VIH
tR
tSLOVE
SIN
VIH
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 137 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
Parameter
SIN→SCK↓ setup time
Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
SCKx
4tCYCP
-
4tCYCP
-
ns
tSHOVI
SCKx,
SOTx
- 10
+ 10
- 10
+ 10
ns
tIVSLI
SCKx,
SINx
-
12.5
-
ns
Internal shift
clock operation
14
12.5*
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
5
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 5
-
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↓ setup time
tIVSLE
SCKx,
SINx
5
-
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
External shift
clock operation
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
−
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 138 of 190
S6E2G Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
VIL
tR
tSLSH
VIH
VIH
SIN
VIL
tF
tSHOVE
SOT
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 139 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Serial clock cycle time
tSCYC
SCK↑→SOT delay time
SIN→SCK↓ setup time
Parameter
Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
SCKx
4tCYCP
-
4tCYCP
-
ns
tSHOVI
SCKx,
SOTx
- 10
+ 10
- 10
+ 10
ns
tIVSLI
SCKx,
SINx
-
12.5
-
ns
Internal shift
clock operation
14
12.5*
SCK↓→SIN hold time
tSLIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↓ delay time
tSOVLI
SCKx,
SOTx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 5
-
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↑→SOT delay time
tSHOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↓ setup time
tIVSLE
SCKx,
SINx
5
-
5
-
ns
SCK↓→SIN hold time
tSLIXE
SCKx,
SINx
5
-
5
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
External shift
clock operation
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
−
When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 140 of 190
S6E2G Series
tSCYC
VOH
SCK
SOT
VOL
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
MS bit = 0
tSLSH
SCK
SOT
VIH
VIL
V
VIL IH
tF
*V
VIH
tSHOVE
tR
VOH
VOL
OH
VOL
tIVSLE
SIN
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 001-98708 Rev. *E
Page 141 of 190
S6E2G Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Symbol
Pin
Name
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
SIN→SCK↑ setup time
Parameter
Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
SCKx
4tCYCP
-
4tCYCP
-
ns
tSLOVI
SCKx,
SOTx
- 10
+ 10
- 10
+ 10
ns
tIVSHI
SCKx,
SINx
-
12.5
-
ns
14
Internal shift
clock operation
12.5*
SCK↑→SIN hold time
tSHIXI
SCKx,
SINx
5
-
5
-
ns
SOT→SCK↑ delay time
tSOVHI
SCKx,
SOTx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock L pulse width
tSLSH
SCKx
2tCYCP - 5
-
2tCYCP - 5
-
ns
Serial clock H pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time
tSLOVE
SCKx,
SOTx
-
15
-
15
ns
SIN→SCK↑ setup time
tIVSHE
SCKx,
SINx
5
-
5
-
ns
SCK↑→SIN hold time
tSHIXE
SCKx,
SINx
5
-
5
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
External shift
clock operation
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
−
When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)
Document Number: 001-98708 Rev. *E
Page 142 of 190
S6E2G Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIL
VIH
tSLSH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 143 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
Symbol
VCC ≥ 4.5 V
Conditions
Unit
Min
Max
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCS↓→SCK↓ setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↓→SCK↓ setup time
tCSSE
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
3tCYCP+15
-
3tCYCP+15
-
ns
Internal shift
clock
operation
External shift
clock
operation
SCS deselect time
tCSDE
SCS↓→SOT delay time
tDSE
-
25
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 144 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 145 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
Symbol
VCC≥ 4.5 V
Conditions
Unit
Min
Min
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCS↓→SCK↓ setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↓→SCK↑ setup time
tCSSE
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
3tCYCP+15
-
3tCYCP+15
-
ns
Internal shift
clock
operation
External shift
clock
operation
SCS deselect time
tCSDE
SCS↓→SOT delay time
tDSE
-
25
-
25
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 146 of 190
S6E2G Series
SCS
output
tCSDI
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 147 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
SCS↑→SCK↓ setup time
Symbol
VCC ≥ 4.5 V
Conditions
tCSSI
Internal shift
clock
operation
Unit
Min
Max
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCK↑→SCS↓ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↑→SCK↓ setup time
tCSSE
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↑→SCS↓ hold time
tCSHE
0
-
0
-
ns
3tCYCP+15
-
3tCYCP+15
-
ns
External shift
clock
operation
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
-
25
-
25
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 148 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 149 of 190
S6E2G Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Parameter
Symbol
SCS↓→SCK↓ setup time
VCC ≥ 4.5 V
Conditions
tCSSI
Internal shift
clock
operation
Unit
Min
Max
Min
Max
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
(*2)+0
(*2)+20
(*2)+0
(*2)+20
ns
SCK↑→SCS↓ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
(*3)-20
+5tCYCP
(*3)+20
+5tCYCP
ns
SCS↑→SCK↑ setup time
tCSSE
3tCYCP+15
-
3tCYCP+15
-
ns
SCK↓→SCS↓ hold time
tCSHE
0
-
0
-
ns
3tCYCP+15
-
3tCYCP+15
-
ns
External shift
clock
operation
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 1. S6E2G Series Block Diagram in this data sheet.
−
For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 150 of 190
S6E2G Series
tCSDI
SCS
output
tCSHI
tCSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS
input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 001-98708 Rev. *E
Page 151 of 190
S6E2G Series
External Clock (EXT = 1): When in Asynchronous Mode Only
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Serial clock L pulse width
tSLSH
Serial clock H pulse width
tSHSL
SCK fall time
tF
SCK rise time
tR
CL = 30 pF
tR
VIL
VIH
Unit
Min
Max
tCYCP + 10
-
ns
tCYCP + 10
-
ns
-
5
ns
-
5
ns
tSHSL
SCK
Document Number: 001-98708 Rev. *E
Value
Condition
tF
tSLSH
VIH
VIL
Remarks
VIL
VIH
Page 152 of 190
S6E2G Series
12.4.13 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
Value
Min
Max
Unit
A/D converter trigger input
ADTGx
FRCKx
-
2tCYCP*1
-
ns
tINH, tINL
DTTIxX
INT00 to INT31,
NMIX
WKUPx
Free-run timer input clock
Input capture
Icxx
Input pulse
width
Remarks
-
2tCYCP*1
-
ns
2tCYCP + 100*1
-
ns
500*2
-
ns
500*3
-
ns
-
-
Waveform generator
External interrupt,
NMI
Deep standby wake up
1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in Timer mode. For more information about
the APB bus number to which the A/D converter, multi-function timer, and external interrupt are connected, see 1. S6E2G
Series Block Diagram in this data sheet.
2: When in Stop mode, in Timer mode
3: When in Deep Standby RTC mode, in Deep Standby Stop mode
Document Number: 001-98708 Rev. *E
Page 153 of 190
S6E2G Series
12.4.14 Quadrature Position/Revolution Counter Timing
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Conditions
AIN pin H width
tAHL
-
AIN pin L width
tALL
-
BIN pin H width
tBHL
-
BIN pin L width
tBLL
-
BIN rise time from
AIN pin H level
tAUBU
PC_Mode2 or PC_Mode3
AIN fall time from
BIN pin H level
tBUAD
PC_Mode2 or PC_Mode3
BIN fall time from
AIN pin L level
tADBD
PC_Mode2 or PC_Mode3
AIN rise time from
BIN pin L level
tBDAU
PC_Mode2 or PC_Mode3
AIN rise time from
BIN pin H level
tBUAU
PC_Mode2 or PC_Mode3
BIN fall time from
AIN pin H level
tAUBD
PC_Mode2 or PC_Mode3
AIN fall time from
BIN pin L level
tBDAD
PC_Mode2 or PC_Mode3
BIN rise time from
AIN pin L level
tADBU
PC_Mode2 or PC_Mode3
ZIN pin H width
tZHL
QCR: CGSC = 0
ZIN pin L width
tZLL
QCR: CGSC = 0
AIN/BIN rise and fall time
from determined ZIN level
tZABE
QCR: CGSC = 1
Determined ZIN level from
AIN/BIN rise and fall time
tABEZ
QCR: CGSC = 1
Value
Min
Max
2tCYCP*
-
Unit
ns
*: tCYCP indicates the APB bus clock cycle time except when in Stop mode, in Timer mode. For more information about the
APB bus number to which the quadrature position/revolution counter is connected, see 1. S6E2G Series Block Diagram in
this data sheet.
Document Number: 001-98708 Rev. *E
Page 154 of 190
S6E2G Series
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
tBLL
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
Document Number: 001-98708 Rev. *E
tALL
Page 155 of 190
S6E2G Series
ZIN
ZIN
AIN/BIN
Document Number: 001-98708 Rev. *E
Page 156 of 190
S6E2G Series
12.4.15 I2C Timing
Standard-Mode, Fast-Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Standard-Mode
Fast-Mode
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SCL clock L width
tLOW
4.7
-
1.3
-
μs
SCL clock H width
tHIGH
4.0
-
0.6
-
μs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
0
0.9*3
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
250
-
100
-
ns
Stop condition setup time
SCL ↑ → SDA ↑
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 MHz ≤
tCYCP＜40 MHz
2 tCYCP*4
-
2 tCYCP*4
-
ns
40 MHz ≤
tCYCP ＜60 MHz
4 tCYCP*4
-
4 tCYCP*4
-
ns
60 MHz ≤
tCYCP ＜80 MHz
6 tCYCP
*4
-
6 tCYCP
*4
-
ns
80 MHz ≤
tCYCP ≤100 MHz
8 tCYCP*4
-
8 tCYCP*4
-
ns
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
Bus free time between
Stop condition and
START condition
Noise filter
tSP
CL = 30 pF,
R = (Vp/IOL)*1
Remarks
*5
1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal.
3: Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns.
4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see
1.S6E2G Series Block Diagram in this data sheet.
When using Standard-mode, the peripheral bus clock must be set more than 2 MHz.
When using Fast-mode, the peripheral bus clock must be set more than 8 MHz.
5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB
bus clock frequency.
Document Number: 001-98708 Rev. *E
Page 157 of 190
S6E2G Series
Fast mode Plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Fast mode Plus (Fm+)*6
Unit
Min
Max
fSCL
0
1000
kHz
tHDSTA
0.26
-
μs
SCL clock L width
tLOW
0.5
-
μs
SCL clock H width
tHIGH
0.26
-
μs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA
0.26
-
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
0.45*2, *3
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
50
-
ns
Stop condition setup time
SCL ↑ → SDA ↑
tSUSTO
0.26
-
μs
tBUF
0.5
-
μs
60 MHz ≤
tCYCP＜80 MHz
6 tCYCP*4
-
ns
80 MHz ≤
tCYCP ≤100 MHz
*4
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
Bus free time between
Stop condition and
START condition
Noise filter
tSP
CL = 30 pF,
R = (Vp/IOL)*1
Remarks
*5
8 tCYCP
-
ns
1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal.
3: The Fast mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns.”
4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see
1.S6E2G Series Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB
bus clock frequency.
6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register.
See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details.
Document Number: 001-98708 Rev. *E
Page 158 of 190
S6E2G Series
Document Number: 001-98708 Rev. *E
Page 159 of 190
S6E2G Series
12.4.16 SD Card Interface Timing
Default-Speed Mode
Clock CLK (All values are referenced to VIH and VIL transition points)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Clock frequency Data
Transfer mode
fPP
Clock frequency
Identification mode
Value
Conditions
Remarks
Min
Max
S_CLK
0
25
MHz
fOD
S_CLK
0/100
400
kHz
Clock low time
tWL
S_CLK
10
-
ns
Clock high time
tWH
S_CLK
10
-
ns
Clock rise time
tTLH
S_CLK
-
10
ns
Clock fall time
tTHL
S_CLK
-
10
ns
CCARD ≤ 10 pF
(1card)
*: 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Input set-up time
tISU
S_CMD,
S_DATA3: 0
Input hold time
tIH
S_CMD,
S_DATA3: 0
Value
Conditions
CCARD ≤ 10 pF
(1card)
Remarks
Min
Max
5
-
ns
5
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Output Delay time during
Data Transfer mode
tODLY
S_CMD,
S_DATA3: 0
Output Delay time during
Identification mode
tODLY
S_CMD,
S_DATA3: 0
Value
Conditions
CCARD ≤ 40 pF
(1card)
Max
0
14
ns
0
50
ns
tWH
tWL
S_CLK
(SD Clock)
VIH
VIH
VIH
VIL
VIL
tTLH
tTHL
tIH
tISU
S_CMD,
S_DATA3: 0
(Card Input)
VIH
VIH
VIL
VIL
tODLY(Min)
tODLY(Max)
S_CMD,
S_DATA3: 0
(Card Output)
Remarks
Min
VOH
VOH
VOL
VOL
Default-Speed mode
Document Number: 001-98708 Rev. *E
Page 160 of 190
S6E2G Series
Notes:
−
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the
Host.
−
For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main
Part (002-04856).
High-speed Mode
Clock CLK (All values are referred to VIH and VIL)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Symbol
Pin Name
Clock frequency Data Transfer
mode
fPP
S_CLK
Clock low time
tWL
S_CLK
Clock high time
tWH
S_CLK
Clock rise time
tTLH
Clock fall time
tTHL
Conditions
Value
Remarks
Min
Max
0
45
MHz
7
-
ns
7
-
ns
S_CLK
-
3
ns
S_CLK
-
3
ns
CCARD ≤ 10 pF
(1 card)
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Input set-up time
tISU
S_CMD,
S_DATA3: 0
Input hold time
tIH
S_CMD,
S_DATA3: 0
Conditions
CCARD ≤ 10 pF
(1 card)
Value
Remarks
Min
Max
6
-
ns
2
-
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol
Pin Name
Conditions
tODLY
S_CMD,
S_DATA3: 0
Output hold time
tOH
Total system capacitance for
each line*
CL
Output delay time during data
transfer mode
Value
Remarks
Min
Max
CL ≤ 40 pF
(1 card)
0
14
ns
S_CMD,
S_DATA3: 0
CL ≥ 15 pF
(1 card)
2.5
-
ns
-
1 card
-
40
pF
*: In order to satisfy severe timing, host shall drive only one card.
Document Number: 001-98708 Rev. *E
Page 161 of 190
S6E2G Series
tWH
tWL
S_CLK
(SD Clock)
50%VCC
VIH
VIH
VIL
VIL
tTLH
tTHL
tIH
tISU
S_CMD,
S_DATA3: 0
(Card Input)
VIH
VIH
VIL
VIL
tOH(Min)
tODLY(Max)
S_CMD,
S_DATA3: 0
(Card Output)
VIH
50%VCC
VOH
VOH
VOL
VOL
High-speed mode
Notes:
−
The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is
the Host.
−
For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual
Main Part (002-04856).
12.4.17 ETM/ HTM Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Data hold
TRACECLK
frequency
Symbol
Pin Name
tETMH
TRACECLK,
TRACED[15: 0]
1/tTRACE
TRACECLK
TRACECLK
clock cycle
tTRACE
Conditions
Value
Min
Max
VCC ≥ 4.5 V
2
9
VCC ＜4.5 V
2
15
Unit
Remarks
ns
VCC ≥ 4.5 V
50
MHz
VCC ＜4.5 V
32
MHz
VCC ≥ 4.5 V
20
-
ns
VCC ＜4.5 V
31.25
-
ns
Note:
−
When the external load capacitance CL = 30 pF.
Document Number: 001-98708 Rev. *E
Page 162 of 190
S6E2G Series
HCLK
TRACECLK
TRACED[15: 0]
Document Number: 001-98708 Rev. *E
Page 163 of 190
S6E2G Series
12.4.18 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
tJTAGD
TCK,
TDO
TDO delay time
Conditions
Value
Unit
Min
Max
15
-
ns
15
-
ns
VCC ≥ 4.5 V
-
25
VCC ＜4.5 V
-
45
Remarks
VCC ≥ 4.5 V
VCC ＜4.5 V
VCC ≥ 4.5 V
VCC ＜4.5 V
ns
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 001-98708 Rev. *E
Page 164 of 190
S6E2G Series
12.4.19 Ethernet-MAC Timing
RMII Transmission (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V*1, VSS = 0V, CL = 25 pF)
Parameter
Symbol
Pin Name
Conditions
Reference clock cycle time*2
tREFCYC
E_RXCK_REFCK
Reference clock
High-pulse-width duty cycle
tREFCYCH
Reference clock
Low-pulse-width duty cycle
REFCK ↑ → Transmitted data
delay time
Value
Unit
Min
Max
20 ns (typical)
-
-
ns
E_RXCK_REFCK
tREFCYCH/tREFCYC
35
65
%
tREFCYCL
E_RXCK_REFCK
tREFCYCL/tREFCYC
35
65
%
tRMIITX
E_TX03, E_RX02,
E_TX01, E_TX00,
E_TXEN
-
-
12
ns
*1: When ETHV = 4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the output
current.
*2: The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device
specifications.
tREFCYC
E_RXCK_REFCK
VIHS
VIHS
VILS
tREFCYCH
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
tREFCYCL
VOH
VOL
tRMIITX
Document Number: 001-98708 Rev. *E
Page 165 of 190
S6E2G Series
RMII Receiving (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Parameter
Symbol
Pin Name
Conditions
Reference clock
cycle time*
tREFCYC
E_RXCK_REFCK
Reference clock
High-pulse-width duty cycle
tREFCYCH
Reference clock
Low-pulse-width duty cycle
Value
Unit
Min
Max
20 ns (typical)
-
-
ns
E_RXCK_REFCK
tREFCYCH/tREFCYC
35
65
%
tREFCYCL
E_RXCK_REFCK
tREFCYCL/tREFCYC
35
65
%
Received data → REFCK↑
Setup time
tRMIIRXS
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
-
4
-
ns
REFCK ↑ → Received data
Hold time
tRMIIRXH
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
-
2
-
ns
*: The reference clock is fixed to 50 MHz in the RMII specifications.
The clock accuracy should meet the PHY-device specifications.
tREFCYC
E_RXCK_REFCK
VIHS
tREFCYCH
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
VIHS
VIHS
VILS
VILS
tRMIIRXS
Document Number: 001-98708 Rev. *E
VIHS
VILS
tREFCYCL
tRMIIRXH
Page 166 of 190
S6E2G Series
Management Interface
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Parameter
Symbol
Pin Name
Conditions
Management clock
cycle time*
tMDCYC
E_MDC
Management clock
High pulse width duty cycle
tMDCYCH
Management clock
Low pulse width duty cycle
Value
Unit
Min
Max
-
400
-
ns
E_MDC
tMDCYCH/tMDCYC
35
65
%
tMDCYCL
E_MDC
tMDCYCL/tMDCYC
35
65
%
MDC ↓ → MDIO
Delay time
tMDO
E_MDIO
-
-
60
ns
MDIO → MDC ↑
Setup time
tMDIS
E_MDIO
-
20
-
ns
MDC ↑ → MDIO
Hold time
tMDIH
E_MDIO
-
0
-
ns
*: The clock time should be set to a value greater than the minimum value by setting the Ethernet-MAC setting register.
tMDCYC
E_MDC (output)
VOL
VOH
tMDCYCH
E_MDIO (input)
VIHS
VIHS
VIHS
VILS
VILS
VILS
VILS
tMDIS
tMDIH
tMDIH
tMDO
tMDO
Document Number: 001-98708 Rev. *E
tMDCYCL
VIHS
tMDIS
E_MDIO (output)
VOH
VOL
VOH
VOH
VOL
VOL
Page 167 of 190
S6E2G Series
MII Transmission (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V*1, VSS = 0V, CL = 25 pF)
Parameter
Transmission clock
Cycle time*2
Symbol
tTXCYC
Pin Name
Conditions
E_TCK
Value
Unit
Min
Max
100 Mbps
40 ns (typical)
-
-
ns
100 Mbps
400 ns (typical)
-
-
ns
Transmission clock
High-pulse-width duty cycle
tTXCYCH
E_TCK
tTXCYCH/tTXCYC
35
65
%
Transmission clock
Low-pulse-width duty cycle
tTXCYCL
E_TCK
tTXCYCL/tTXCYC
35
65
%
tMIITX
E_TX03, E_TX02,
E_TX01, E_TX00,
E_TXEN
-
-
24
ns
TXCK ↑ → Transmitted data delay
time
1: When ETHV = 4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the output current.
2: The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications. The clock accuracy should meet the
PHY-device specifications.
tTXCYC
E_TCK
VIHS
VIHS
VILS
tTXCYCH
E_TX03
E_TX02
E_TX01
E_TX00
E_TXEN
tTXCYCL
VOH
VOL
tMIITX
Document Number: 001-98708 Rev. *E
Page 168 of 190
S6E2G Series
MII Receiving (100 Mbps/10 Mbps)
(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)
Parameter
Receiving clock
cycle time*
Symbol
Pin Name
tRXCYC
Conditions
E_RXCK_REFCK
Value
Unit
Min
Max
100 Mbps
40 ns (typical)
-
-
ns
100 Mbps
400 ns (typical)
-
-
ns
Receiving clock
High pulse width duty cycle
tRXCYCH
E_RXCK_REFCK
tRXCYCH/tRXCYC
35
65
%
Receiving clock
Low pulse width duty cycle
tRXCYCL
E_RXCK_REFCK
tRXCYCL/tRXCYC
35
65
%
Received data →
REFCK ↑Setup time
tMIIRXS
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
-
5
-
ns
REFCK ↑ →
Received data Hold time
tMIIRXH
E_RX03, E_RX02,
E_RX01, E_RX00,
E_RXDV
-
2
-
ns
*: The receiving clock 100Mbps is fixed to 25MHz or 2.5MHz in the MII specifications.
The clock accuracy should meet the PHY-device specifications.
tRXCYC
E_RXCK_REFCK
VIHS
tRXCYCH
E_RX03
E_RX02
E_RX01
E_RX00
E_RXDV
VIHS
VIHS
VILS
VILS
tMIIRXS
Document Number: 001-98708 Rev. *E
VIHS
VILS
tRXCYCL
tMIIRXH
Page 169 of 190
S6E2G Series
12.4.20 I2S Timing (Multi-function Serial Interface)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin Name
Conditions
fI2SCK
MI2SCKx
tICYC
MI2SCKx
∆
MI2SCKx
I2SCK↓ → I2SWS delay time
tSWDT
MI2SCKx,
MI2SWSx
I2SCK↓ → I2SDO delay time
tSDDT
MI2SCKx,
MI2SDOx
I2SDI → I2SCK ↑ setup time
tDSST
I2SCK ↑ → I2SDI hold time
tSDHT
I2SCK max frequency *1
I2S clock cycle time
*1
I2S clock Duty cycle
I2SCK falling time
tF
I2SCK rising time
tR
MI2SCKx, MI2SDIx
MI2SCKx
Value
Unit
Min
Max
-
-
6.144
MHz
-
4 tCYCP2
-
%
45
55
%
-
-20
+20
ns
-
-20
+20
ns
-
36
-
ns
-
0
-
ns
-
-
5
ns
-
-
5
ns
Remarks
*1: I2S clock should meet the multiple of PCLK(tICYC) and the frequency less than fI2SCK meantime.
Note:
−
See Chapter 1-6: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04856)
for the details.
VIH
VIH
MI2SCK
VIL
VIL
tF
tR
tSWDT,
tSDDT
MI2SWS
and
MI2SDO
VOH
VOL
tDSST
tSDHT
VIH
VIH
VIL
VIL
MI2SDI
Document Number: 001-98708 Rev. *E
Page 170 of 190
S6E2G Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Parameter
Symbol
Pin Name
Resolution
-
Integral nonlinearity
Value
Unit
Min
Typ
Max
-
-
-
12
bit
-
-
-
-
± 4.5
LSB
Differential nonlinearity
-
-
-
-
± 2.5
LSB
Zero transition voltage
VZT
Anxx
-
±2
±7
Full-scale transition voltage
VFST
Anxx
-
AVRH ± 2
AVRH ± 7
-
-
-
Total error
Conversion time
-
-
Sampling time *2
tS
-
Compare clock cycle*3
State transition time to
operation permission
Power supply current (analog +
digital)
Reference power supply
current (AVRH)
tCCK
-
tSTT
-
-
AVCC
-
AVRH
AVRH
LSB = 2.7 V to 5.5 V
Offset calibration
LSB when used
±3
±8
LSB
*1
-
-
μs
0.15
-
0.3
10
μs
-
25
-
1000
50
-
1000
-
-
1.0
μs
-
0.69
0.92
mA
A/D 1 unit operation
-
1.3
22
μA
When A/D stop
-
1.1
1.97
mA
A/D 1 unit operation
AVRH = 5.5 V
-
0.3
6.3
μA
When A/D stop
12.05
pF
0.5
ns
Analog input capacity
CAIN
-
-
-
Analog input resistance
RAIN
-
-
-
Interchannel disparity
-
-
-
-
4
LSB
Analog port input leak current
-
Anxx
-
-
5
μA
Analog input voltage
Anxx
AVSS
-
AVRH
V
-
AVSS
-
AVCC
V
4.5
-
AVCC
2.7
-
AVCC
AVSS
-
AVSS
Reference voltage
-
1.2
AVRH
AVRL
Remarks
1.8
kΩ
V
AVCC ≥ 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
Tcck ＜50 ns
Tcck ≥ 50 ns
V
1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is when the value of Ts = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure that it
satisfies the value of sampling time (tS) and compare clock cycle (tCCK).
For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog
Macro Part (002-04860). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information
about the APB bus number to which the A/D converter is connected, see 1. S6E2G Series Block Diagram in this data sheet.
The sampling clock and compare clock are set at base clock (HCLK).
2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1).
3: The compare time (tC) is the value of (Equation 2).
Document Number: 001-98708 Rev. *E
Page 171 of 190
S6E2G Series
ANxx
Analog input pin
Rext
Comparator
R
AIN
Rin
Analog signal
source
Cin
CAIN
(Equation 1) tS ≥ (RAIN + Rext) × CAIN × 9
tS:
Sampling time
RAIN: Input resistance of A/D = 1.2 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistance of A/D = 1.8 kΩ at 2.7 V ≤ AVCC < 4.5 V
CAIN: Input capacity of A/D = 12.05 pF at 2.7 V ≤ AVCC ≤ 5.5 V
Rext: Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK: Compare clock cycle
Document Number: 001-98708 Rev. *E
Page 172 of 190
S6E2G Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
Differential nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
Differential nonlinearity
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
0xN
Ideal characteristics
VNT
Actual conversion characteristics
AVRH
AVss
AVRH
Analog input
Integral nonlinearity of digital output N =
Differential nonlinearity of digital output N =
1LSB =
N:
VZT:
VFST:
VNT:
(Actually-measured
value)
(Actually-measured
value)
0x(N-2)
VZT (Actually-measured value)
AVss
V(N+1)T
0x(N-1)
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 001-98708 Rev. *E
Page 173 of 190
S6E2G Series
Total error: A difference between actual value and theoretical value.
The overall error includes zero-transition voltage, full-scale transition voltage and linearity error.
Total error
0xFFF
VFST’=1.5LSB’
0xFFE
Actual conversion
characteristics
Digital output
0xFFD
{1LSB’ x (N-1) + 0.5 LSB’}
0x004
VNT
(Actually-measured
value)
0x003
Actual conversion
characteristics
0x002
Ideal characterisics
0x001
VZT’=0.5LSB’
AVRL
AVRH
Analog input
Total error of digital output N =
1 LSB’ (ideal value) =
VNT – {1 LSB’ X (N-1) + 0.5 LSB’}
1 LSB’
AVRH – AVRL
4096
VZT’ (ideal value) =
AVRL + 0.5 LSB’
[V]
VFST’ (ideal value) =
AVRH - 1.5 LSB’
[V]
[LSB]
[V]
VNT’: A voltage for causing transition of digital output from (N-1) to N
Document Number: 001-98708 Rev. *E
Page 174 of 190
S6E2G Series
12.6 USB Characteristics
(VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V)
Parameter
Symbol
Input H level voltage
Conditions
Value
Min
Max
Unit Remarks
VIH
-
2.0
USBVCC + 0.3
V
*1
VIL
-
VSS - 0.3
0.8
V
*1
VDI
-
0.2
-
V
*2
Different common mode
range
VCM
-
0.8
2.5
V
*2
Output H level voltage
VOH
External pull-down
resistance = 15 kΩ
2.8
3.6
V
*3
Output L level voltage
VOL
External pull-up
resistance = 1.5 kΩ
0.0
0.3
V
*3
Crossover voltage
VCRS
-
1.3
2.0
V
*4
Rise time
tFR
Full-Speed
4
20
ns
*5
Fall time
tFF
Full-Speed
4
20
ns
*5
Rise/fall time matching
tFRFM
Full-Speed
90
111.11
%
*5
Output impedance
ZDRV
Full-Speed
28
44
Ω
*6
Rise time
tLR
Low-Speed
75
300
ns
*7
Fall time
tLF
Low-Speed
75
300
ns
*7
Rise/fall time matching
tLRFM
Low-Speed
80
125
%
*7
Input L level voltage
Input
characteristics Differential input sensitivity
Output
characteristics
Pin
Name
UDP0/
UDM0,
UDP1/
UDM1
1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V,
VIH (Min) = 2.0 V (TTL input standard).
There is some hysteresis applied to lower noise sensitivity.
2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input
sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level.
Minimum differential input
sensitivity [V]
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
Document Number: 001-98708 Rev. *E
Page 175 of 190
S6E2G Series
3: The output drive capability of the driver is below 0.3 V at low state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or
above (to the VSS and 1.5 kΩ load) at high state (VOH).
4: The cross voltage of the external differential output signal (D +/D −) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
5: They indicate rise time (tRISE) and fall time (tFALL) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, tR/tF ratio is regulated as within ± 10% to minimize RFI emission.
D+
90%
D-
90%
10%
10%
TRISE
Rise time
TFALL
Falling time
Full-speed Buffer
Rs=27
TxD+
CL=50pF
Rs=27
TxDCL=50pF
3-State Enable
Document Number: 001-98708 Rev. *E
Page 176 of 190
S6E2G Series
6: USB Full-speed connection is performed via twisted-pair cable shield with 90Ω ± 15% characteristic impedance
(differential mode).
USB standard defines that the output impedance of the USB driver must be in the range from 28 Ω to 44 Ω. So, a discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommended value 27 Ω) series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence.”
7: They indicate rise time (tRISE) and fall time (tFALL) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
D+
90%
D-
90%
10%
10%
TRISE
Rise time
TFALL
Falling time
Note:
−
See Low-Speed Load (Compliance Load) for conditions of external load.
Document Number: 001-98708 Rev. *E
Page 177 of 190
S6E2G Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL=50pF to 150pF
CL=50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL=
200pF to 600pF
CL=
200pF to 600pF
Low-Speed Load (Compliance Load)
CL=200pF to 450pF
CL=200pF to 450pF
Document Number: 001-98708 Rev. *E
Page 178 of 190
S6E2G Series
12.7 Low-Voltage Detection Characteristics
12.7.1
Low-Voltage Detection Reset
Parameter
Symbol
Conditions
Detected voltage
VDL
Released voltage
VDH
12.7.2
Value
Unit
Remarks
2.64
V
When voltage drops
2.69
V
When voltage rises
Unit
Remarks
Min
Typ
Max
-
2.46
2.55
-
2.51
2.60
Interrupt of Low-Voltage Detection
Parameter
Symbol
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait
time
tLVDW
Conditions
SVHI = 00111
SVHI = 00100
SVHI = 01100
SVHI = 01111
SVHI = 01110
SVHI = 01001
SVHI = 01000
SVHI = 11000
-
Value
Min
Typ
Max
2.80
2.90
3.00
V
When voltage drops
2.90
3.00
3.11
V
When voltage rises
2.99
3.10
3.21
V
When voltage drops
3.09
3.20
3.31
V
When voltage rises
3.18
3.30
3.42
V
When voltage drops
3.28
3.40
3.52
V
When voltage rises
3.67
3.80
3.93
V
When voltage drops
3.76
3.90
4.04
V
When voltage rises
3.76
3.90
4.04
V
When voltage drops
3.86
4.00
4.14
V
When voltage rises
4.05
4.20
4.35
V
When voltage drops
4.15
4.30
4.45
V
When voltage rises
4.15
4.30
4.45
V
When voltage drops
4.25
4.40
4.55
V
When voltage rises
4.25
4.40
4.55
V
When voltage drops
4.34
4.50
4.66
V
When voltage rises
-
-
6000×tCYCP*
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 001-98708 Rev. *E
Page 179 of 190
S6E2G Series
12.8 MainFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Parameter
Value
Unit
Min
Typ
Max
Large Sector
-
0.7
3.7
s
Small Sector
-
0.3
1.1
s
Half word (16-bit) Write cycles < 100 times
write time
Write cycles > 100 times
-
12
Chip erase time*
-
13.6
Sector erase time
100
200
68
Remarks
Includes write time prior to internal
erase
μs
Not including system-level overhead
time
s
Includes write time prior to internal
erase
*: It indicates the chip erase time of 1MB MainFlash memory
For devices with 1.5 MB or 2 MB of MainFlash memory, two erase cycles are required.
See 3.2.2 Command Operating Explanations and 3.3.3 Flash Erase Operation in this product's Flash Programming Manual for
the detail.
Write Cycles and Data Retention Time
Erase/Write Cycles (Cycle)
Data Retention Time (Year)
1,000
20*
10,000
10*
100,000
5*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
acceleration test result into average temperature value at + 85°C).
Document Number: 001-98708 Rev. *E
Page 180 of 190
S6E2G Series
12.9 Standby Recovery Time
12.9.1 Recovery Cause: Interrupt/WKUP
The time from the interrupt occurring to the time of program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Value
Symbol
Sleep mode
Unit
Max*
Typ
HCLK×1
Remarks
μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
40
80
μs
Low-speed CR Timer mode
450
900
μs
Sub Timer mode
896
1136
μs
316
581
μs
270
540
μs
365
667
μs
without RAM
retention
365
667
μs
with RAM retention
RTC mode
Stop mode
(High-speed CR/Main/PLL Run mode return)
tICNT
RTC mode
Stop mode
(Low-speed CR/sub Run mode return)
Deep Standby RTC mode with RAM retention
Deep Standby Stop mode with RAM retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in External Interrupt Recovery*)
Ext.INT
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 001-98708 Rev. *E
Page 181 of 190
S6E2G Series
Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*)
Internal
Resource INT
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
−
The return factor is different in each low-power consumption mode. See Chapter 6: Low Power Consumption mode and
Operations of Standby modes in FM4 Family Peripheral Manual Main Part (002-04856).
−
The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family
Peripheral Manual Main Part (002-04856).
Document Number: 001-98708 Rev. *E
Page 182 of 190
S6E2G Series
12.9.2 Recovery Cause: Reset
The time from reset release to the program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Typ
Max*
Sleep mode
155
266
μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
155
266
μs
Low-speed CR Timer mode
315
567
μs
315
567
μs
315
567
μs
336
667
μs
without RAM
retention
336
667
μs
with RAM retention
Sub Timer mode
tRCNT
RTC mode
Stop mode
Deep Standby RTC mode with RAM retention
Deep Standby Stop mode with RAM retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in INITX Recovery)
INITX
Internal RST
RST Active
Release
tRCNT
CPU
Operation
Document Number: 001-98708 Rev. *E
Start
Page 183 of 190
S6E2G Series
Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*)
Internal
Resource RST
Internal RST
RST Active
Release
tRCNT
CPU
Operation
Start
*: Depending on the low-power consumption mode, the reset issue from the internal resource is not included in the
recovery cause.
Notes:
−
The return factor is different in each low power consumption mode.
See Chapter 6: Low Power Consumption mode and Operations of Standby modes in “FM4 Family Peripheral Manual
Main Part (002-04856).
−
The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption mode in FM4 Family
Peripheral Manual Main Part (002-04856).
−
When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-On
Reset Timing.
−
In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock,
they need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock.
−
Internal resource reset indicates Watchdog reset and CSV reset.
Document Number: 001-98708 Rev. *E
Page 184 of 190
S6E2G Series
13. Ordering Information
Part Number
Flash
RAM
Crypto
Package
S6E2GM6H0AGV2000A
512 KB
128 KB
✓
✓
✓
S6E2GM8H0AGV2000A
1 MB
192 KB
✓
✓
✓
✓
✓
Plastic LQFP (0.5 mm pitch),
144 pin
(LQS144)
S6E2GM6HHAGV2000A
512 KB
128 KB
✓
✓
S6E2GM8HHAGV2000A
1 MB
192 KB
✓
✓
✓
✓
S6E2GM6J0AGV2000A
512 KB
128 KB
✓
✓
✓
S6E2GM8J0AGV2000A
1 MB
192 KB
✓
✓
✓
S6E2GM6JHAGV2000A
512 KB
128 KB
✓
✓
✓
✓
S6E2GM8JHAGV2000A
1 MB
192 KB
✓
✓
✓
✓
S6E2GK6H0AGV2000A
512 KB
128 KB
✓
✓
S6E2GK8H0AGV2000A
1 MB
192 KB
✓
✓
S6E2GK6HHAGV2000A
512 KB
128 KB
✓
✓
✓
S6E2GK8HHAGV2000A
1 MB
192 KB
✓
✓
✓
S6E2GK6J0AGV2000A
512 KB
128 KB
✓
✓
S6E2GK8J0AGV2000A
1 MB
192 KB
✓
✓
S6E2GK6JHAGV2000A
512 KB
128 KB
✓
✓
✓
S6E2GK8JHAGV2000A
1 MB
192 KB
✓
✓
✓
S6E2GH6H0AGV2000A
512 KB
128 KB
✓
✓
S6E2GH8H0AGV2000A
1 MB
192 KB
✓
✓
S6E2GH6J0AGV2000A
512 KB
128 KB
✓
✓
S6E2GH8J0AGV2000A
1 MB
192 KB
✓
✓
S6E2G36H0AGV2000A
512 KB
128 KB
S6E2G38H0AGV2000A
1 MB
192 KB
S6E2G36J0AGV2000A
512 KB
128 KB
S6E2G38J0AGV2000A
1 MB
192 KB
S6E2G26H0AGV2000A
512 KB
128 KB
✓
S6E2G28H0AGV2000A
1 MB
192 KB
✓
S6E2G26HHAGV2000A
512 KB
128 KB
✓
✓
S6E2G28HHAGV2000A
1 MB
192 KB
✓
✓
S6E2G26J0AGV2000A
512 KB
128 KB
✓
S6E2G28J0AGV2000A
1 MB
192 KB
✓
S6E2G26JHAGV2000A
512 KB
128 KB
✓
✓
S6E2G28JHAGV2000A
1 MB
192 KB
✓
✓
Document Number: 001-98708 Rev. *E
CAN
Ethernet
SD Card
Plastic LQFP (0.5 mm pitch),
176 pin
(LQP176)
Plastic LQFP (0.5 mm pitch),
144 pin
(LQS144)
Plastic LQFP (0.5 mm pitch),
176 pin
(LQP176)
Plastic LQFP (0.5 mm pitch),
144 pin
(LQS144)
Plastic LQFP (0.5 mm pitch),
176 pin
(LQP176)
Plastic LQFP (0.5 mm pitch),
144 pin
(LQS144)
Plastic LQFP (0.5 mm pitch),
176 pin
(LQP176)
Plastic LQFP (0.5 mm pitch),
144 pin
(LQS144)
Plastic LQFP (0.5 mm pitch),
176 pin
(LQP176)
Page 185 of 190
S6E2G Series
14. Package Dimensions
Package Type
Package Code
LQFP 144
LQS144
4
D
D1
10 8
4
5 7
7 5
73
10 9
73
72
D
D1
108
10 9
72
E1
E
5
7
E
4
4
E1
5
7
3
3
6
14 4
37
1
14 4
37
36
1
36
BOTTOM VIEW
2 5 7
e
3
0.1 0 C A-B D
0.2 0 C A-B D
b
0.0 8
TOP VIEW
C A-B
D
8
2
A
9 c
A
A'
0.0 8 C
SEATING
PLAN E
L1
0.25
L
A1
10
b
SECTION A-A'
SIDE VIEW
SYMBOL
DIM ENSIONS
M IN. NOM. M AX.
1.70
A
A1
0.05
b
0.17
c
0.09
0.15
0.22
0.27
0.20
D
22.00 BSC
D1
20.00 BSC
e
0.50 BSC
E
22.00 BSC
20.00 BSC
E1
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 M M LQS144 REV*A
Document Number: 001-98708 Rev. *E
002-13015 *A
Page 186 of 190
S6E2G Series
Package Type
Package Code
LQFP 176
LQP176
D
D1
132
4
5 7
89
133
89
88
132
133
88
E1
E
5
7
4
3
6
176
45
1
176
45
44
44
1
2 5 7
e
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.08
C A-B
D
8
TOP VIEW
2
A
A
A'
0.08 C
SIDE VIEW
SYM BOL
NOM . M AX.
0.05
0.15
L1
0.25
A1
10
L
c
b
SECTION A-A'
1.70
b
0.17
c
0.09
0.22
26.00 BSC
D1
24.00 BSC
e
0.50 BSC
E
26.00 BSC
E1
0.27
0.20
D
24.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
θ
SEA TIN G
PLAN E
DIM ENSIONS
M IN.
A
A1
9
θ
0°
8°
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 M M LQP176 REV**
002-15150 **
Document Number: 001-98708 Rev. *E
Page 187 of 190
S6E2G Series
Document History
Document Title: S6E2G Series 32-bit Arm® Cortex®-M4F, FM4 Microcontroller
Document Number: 001-98708
Revision
ECN
Orig. of
Change
**
4861788
YOHO
*A
4945035
HITK
*B
5122844
BOO
03/29/2016 Removed full multiplexed signal names from the Pin Assignments drawing.
Consolidated the G Series of Cypress MCUs into one data sheet.
Added tables to differentiate parts in 2 Product Lineup and 3
Package-Dependent Features.
Added hyperlinks to 6 Pin Descriptions.
Added circuit type D to 7 I/O Circuit Type and pin state types S and T to 11
Pin Status in Each CPU State.
Consolidated 10 Memory Map to two pages.
Expanded 13 Ordering Information.
*C
5448447
YSKA
04/12/2017 Modified typo about the number (from 5 to 4) of power supplies. (Page 11)
Updated “12.4.8 Power-On Reset Timing”. Changed parameter from
“Power Supply rise time(tVCCR) [ms]” to “Power ramp rate(dV/dt) [mV/us]”
and add some comments. (Page 107)
Modified “12.4.12 CSIO(SPI) Timing”. Deleted “SPI=1, MS=0” in the titles
and added MS=0,1 in the schematic (Page 128-135, 144-151)
Deleted Baud rate spec for High-Speed Synchronous Serial in “12.4.12
CSIO(SPI) Timing”(Page 136-142)
“Modified RTC description in “4. Product Features in Detail, Real-Time
Clock(RTC)”
Changed starting count value from 01 to 00. Deleted “second, or day of
the week” in the Interrupt function (Page 9)
Updated “14. Package dimensions” (Page 186-187)
Change the name from “USB Function” to “USB Device” (Page 50)
Deleted MPNs below from “13. Ordering Information” (Page 185)
S6E2G26H0AGV20000, S6E2G26HHAGV20000,
S6E2G26J0AGV20000,
S6E2G26JHAGV20000, S6E2G28H0AGV20000,
S6E2G28HHAGV20000,
S6E2G28J0AGV20000, S6E2G28JHAGV20000, S6E2G36H0AGV20000,
S6E2G36J0AGV20000, S6E2G38H0AGV20000, S6E2G38J0AGV20000,
Document Number: 001-98708 Rev. *E
Submission
Date
Description of Change
07/27/2015 New spec.
11/20/2015 Changed status from Preliminary to Final.
Updated 4 Pin Description:
Added “Note” about TAP pins.
Updated 12.2 Recommended Operating Conditions:
Added the "Smoothing capacitor (CS)”.
Added the “Current Value” in “Maximum leak current at operating”.
Updated 12.3.1 Current Rating:
Updated Table 12-1 to Table 12-9:
Added the “MAX” value.
Updated Table 12-11:
Updated 12.5 12-bit A/D Converter:
Updated “Zero transition” and “Full-scale transition” value.
Added “Total error”.
Page 188 of 190
S6E2G Series
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
S6E2GH6H0AGV20000, S6E2GH6J0AGV20000,
S6E2GH8H0AGV20000,
S6E2GH8J0AGV20000, S6E2GK6H0AGV20000,
S6E2GK6HHAGV20000,
S6E2GK6J0AGV20000, S6E2GK6JHAGV20000,
S6E2GK8H0AGV20000,
S6E2GK8HHAGV20000, S6E2GK8J0AGV20000,
S6E2GK8JHAGV20000,
S6E2GM6H0AGV20000, S6E2GM6HHAGV20000,
S6E2GM6J0AGV20000,
S6E2GM6JHAGV20000, S6E2GM8H0AGV20000,
S6E2GM8HHAGV20000,
S6E2GM8J0AGV20000, S6E2GM8JHAGV20000
Added MPNs below to “13. Ordering Information” (Page 185)
S6E2G26H0AGV2000A, S6E2G26HHAGV2000A,
S6E2G26J0AGV2000A,
S6E2G26JHAGV2000A, S6E2G28H0AGV2000A,
S6E2G28HHAGV2000A,
S6E2G28J0AGV2000A, S6E2G28JHAGV2000A,
S6E2G36H0AGV2000A,
S6E2G36J0AGV2000A, S6E2G38H0AGV2000A,
S6E2G38J0AGV2000A,
S6E2GH6H0AGV2000A, S6E2GH6J0AGV2000A,
S6E2GH8H0AGV2000A,
S6E2GH8J0AGV2000A, S6E2GK6H0AGV2000A,
S6E2GK6HHAGV2000A,
S6E2GK6J0AGV2000A, S6E2GK6JHAGV2000A,
S6E2GK8H0AGV2000A,
S6E2GK8HHAGV2000A, S6E2GK8J0AGV2000A,
S6E2GK8JHAGV2000A,
S6E2GM6H0AGV2000A, S6E2GM6HHAGV2000A,
S6E2GM6J0AGV2000A,
S6E2GM6JHAGV2000A, S6E2GM8H0AGV2000A,
S6E2GM8HHAGV2000A,
S6E2GM8J0AGV2000A, S6E2GM8JHAGV2000A
Modified typo about the munber of QPRC channels(from 4ch to 2ch) (Page
1,6,10)
Modified the expression of the “Built-in CR” in “2. Product Lineup” (Page 6).
Updated Cypress Logo and Copyright.
*D
6298066
XITO
09/03/2018 Updated to new template.
Completing Sunset Review.
*E
6602132
XITO
06/24/2019 Updated to new template.
Completing Sunset Review.
Document Number: 001-98708 Rev. *E
Page 189 of 190
S6E2G Series
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Document Number: 001-98708 Rev. *E
June 24, 2019
Page 190 of 190
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