S6J323CLSPSC20000

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com S6J3200 Series 32-bit Microcontroller TRAVEO T1G Family The TRAVEO™ T1G MCU S6J3200 family features 32-bit RISC microcontrollers with an Arm® Cortex®- R5 core and operates up to 240 MHz. This microcontroller comes with highly-efficient 2D/3D graphic engines with advanced feature-sets for memory saving, safety, and high image quality to help manufacturers take advantage of the lower overall system costs. It also meets the increasingly high levels of performance and quality that industrial, consumer, and automotive applications demand. In addition, this microcontroller offers support for the Cypress HyperBus™ memory interface, a breakthrough that dramatically improves read performance while reducing the number of pins. This microcontroller comes with Ethernet AVB, CAN-FD, a high-speed communication protocol compatible with the conventional CAN, and Secure Hardware Extension (SHE) as a security function. Features ◼ System ◼ Memory  32-bit Arm Cortex-R5F CPU core at up to 240 MHz  GPIO port: Up to 120  12-bit A/D converter: Up to 50 channels  External interrupt: Up to 16 channels  Base timer: Up to 24 channels  32-bit free-run timer: Up to 12 channels  Built-in CR oscillators  Real-time clock  Input capture unit: Up to 24 channels  Output compare unit: Up to 24 channels  DMA controller: 16 channels  Stepper motor controller (SMC): Six units  JTAG debug interface  Cypress  Dual HyperBus Memory interface quad double data rate SPI Flash Interface ◼ Multimedia  I2S input/output: Up to two units to PWM output unit  Sound mixer (optional): 1 unit x 10 inputs (optional)  Stereo audio DAC (optional)  PCM ◼ Security and Safety ◼ Graphics and Display  2D graphic engine graphic engine (optional)  Timing generator - TCON  TTL/RSDS  FPD-Link – LVDS (optional)  Video capture (optional)  Communication: Ethernet AVB MAC (optional)  CAN-FD: up to four channels  Multi-function serial interface：up to 12 channels, selec table protocol: UART, CSIO, LIN, and I2C  MediaLB: up to one channel (optional)  Secure Hardware Extension features, such as MPU, TPU, ECC, and others  CRC generator: One channel  Watchdog timer with window function  Low-voltage detector  Clock supervisor for all source clocks  Safety  3D Cypress Semiconductor Corporation Document Number: 002-05682 Rev. *Q • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 27, 2021 S6J3200 Series Table of Contents 1. Overview ............................................................................................................................................................................ 3 1.1 Document Definition ...................................................................................................................................................... 3 2. Function List ..................................................................................................................................................................... 4 2.1 Function List .................................................................................................................................................................. 4 2.2 Optional Function .......................................................................................................................................................... 7 3. Product Description ........................................................................................................................................................ 15 3.1 Overview ..................................................................................................................................................................... 15 3.2 Product Description ..................................................................................................................................................... 15 4. Package and Pin Assignment ........................................................................................................................................ 22 4.1 Pin Assignment ........................................................................................................................................................... 22 4.2 Package Dimensions ................................................................................................................................................... 39 5. I/O Circuit Type................................................................................................................................................................ 44 5.1 I/O Circuit Type ........................................................................................................................................................... 44 5.2 Note ............................................................................................................................................................................. 51 6. Port Description .............................................................................................................................................................. 52 6.1 Port Description List .................................................................................................................................................... 52 6.2 Remark ........................................................................................................................................................................ 70 7. Precautions and Handling Devices ............................................................................................................................... 70 7.1 Handling Precautions .................................................................................................................................................. 70 7.2 Handling Devices ........................................................................................................................................................ 73 8. Electric Characteristics .................................................................................................................................................. 75 8.1 Absolute Maximum Rating........................................................................................................................................... 75 8.2 Operation Assurance Condition ................................................................................................................................... 79 8.3 DC Characteristics....................................................................................................................................................... 84 8.4 AC Characteristics ....................................................................................................................................................... 98 8.5 A/D Converter ............................................................................................................................................................ 173 8.6 Audio DAC................................................................................................................................................................. 177 8.7 Flash Memory ............................................................................................................................................................ 180 9. Abbreviation .................................................................................................................................................................. 181 10. Ordering Information .................................................................................................................................................... 183 11. Errata.............................................................................................................................................................................. 185 12. Appendix ........................................................................................................................................................................ 190 12.1Application 1: JTAG tool Connection ........................................................................................................................ 190 13. Major Changes .............................................................................................................................................................. 191 13.1Supplementary Information ...................................................................................................................................... 191 Document History ............................................................................................................................................................... 214 Sales, Solutions, and Legal Information ........................................................................................................................... 225 Document Number: 002-05682 Rev. *Q Page 2 of 225 S6J3200 Series 1. Overview 1.1 Document Definition Following are the related documents of S6J3200. Table 1-1 Document Type Datasheet S6J3200 hardware manual TRAVEO™ T1G Platform hardware manual Application note Definition The function and its characteristics are specified quantitatively. The function and operation of the S6J3200 series are described. The function and operation of the CPU core platform are described. The reference software, sample application, the reference board design, and so on are explained. Primary User Investigator and hardware engineer Document Code 002-05682 Revision (Previous: DS708-00003-Revision) Software engineer 002-04852 Revision Software engineer 002-04854 Revision Software and hardware engineer 002-09861 Revision 002-09715 Revision 002-04455 Revision 002-04096 Revision 002-12061 Revision 002-04452 Revision 002-09716 Revision 002-11319 Revision 002-02495 Revision Notes: − Refer to all documents for the system development. − − "Primary user" is most likely the engineer for whom the document is the most useful. − − − The TRAVEO™ T1G platform hardware manual is expected to be used as a dictionary of platform specification. The description of the datasheet and the S6J3200 hardware manual should precede the duplicated description of TRAVEO™ T1G platform hardware manual. Document code usually includes its revision. Revised information from the previous revision can be seen the supplementary information. Document Number: 002-05682 Rev. *Q Page 3 of 225 S6J3200 Series 2. Function List 2.1 Function List The table shows the functions which are implemented in S6J3200 series. Table 2-1 Function CPU core PPU MPU TPU Endian Description Arm Cortex R5F Available (Double precision and Single precision) Available Available Available Little endian Core clock frequency Option HPM bus frequency Option Resource clock frequency Option Embedded CR oscillation Slow clock:100 kHz, Fast clock: 4 MHz (Center frequency) PLL SSCG PLL Clock supervisor DMA Boot-ROM JTAG Data cache Instruction cache Program FLASH Work FLASH TC-RAM System-RAM Backup-RAM Security (SHE) Low latency interrupt Power domain Power supply Embedded LDO power supply for 5.0 V Low-voltage detection of external power supply Low-voltage detection of internal LDO output Hardware watchdog timer Software watchdog timer Package AUTOSAR General Purpose I/O Quad Position & Revolution Counter (Up/Down Counter) I/O timer 32 bit Reload timer Real time clock Sound generator PLL0, 1, 2, 3 SSCG0, 1, 2, 3 Available 16 ch 16 Kbytes Available 16 Kbytes 16 Kbytes Option 112 Kbytes Option Option 16 Kbytes Option Available 5 domains 5 V +/- 0.5 V, 3.3 V +/- 0.3 V, 1.2 V +/- 0.1 V FPU Sound waveform generator Document Number: 002-05682 Rev. *Q Remark See 2.2.1 and AC specification on the datasheet. See AC specification on the datasheet See AC specification on the datasheet See AC specification on the datasheet See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 Available Available Available Available Available Option AUTOSAR 4.0.3 Option See 2.2.1 See 2.2.3 2 ch 3 unit x 8 ch 14 ch Available 4 ch Option 1 unit x 5 outputs Automatic calibration See 2.2.1 Page 4 of 225 S6J3200 Series Function CRC Programmable CRC Source clock timer NMI External interrupt Internal interrupt Description Option 1 unit x 10 inputs Option 1 unit (L and R) Option 1 unit (L and R) 12 units (24 ch) 12 ch 12 unit (24channels of capture) 12unit (24 channels of compare match) For 6 gauges Option 1 unit x 50 input ports (Max) 4 unit 1 unit 4 ch Available 16 ch 512 vectors I2S 2 ch DDR HSSPI 2 ch HyperBus (RPC2) Option Multi-function serial interface CAN-FD 12 ch 4 ch 16KB/ch It equivalents to 128 message buffer per channel of CCAN module Option Option Option 4 COM x 32 SEG (Max) 1 ch 1 unit 1 unit Option Option Option Option 64 MHz (ch.0), 50 MHz(ch.1) Graphic display controller clock or external clock 60 fps Option Maximum 2 outputs simultaneously Option 1 output Option 1 output, 350 Mbps (Max) Option ITU656, YCbCr4:4:4, YCbCr4:2:2, RGB888, RGB666 1 unit Available Available Available Available CYPRESS proprietary Sound mixer Stereo audio DAC PCM-PWM Base timer Free-run timer Input Capture Unit Output Compare Unit Stepping motor controller (SMC) 12 bit-A/D converter CAN-FD RAM (ECC supported) Ethernet AVB Media-LB (MOST25) LCD controller Indicator PWM MPU for AHB MPU for AXI Internal VRAM Graphic engine clock Graphic AXI clock Display clock Display clock source Target frame rate Number of display outputs TTL output (RGB888) RSDS/TCON support FPD-Link (LVDS) Video capture unit Video capture format 2D Graphic engine 2.5D support Vector drawing on 2D engine Warping Scale/Rotate/Blend 2D Driver API Document Number: 002-05682 Rev. *Q Remark See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.3 One only supports an output as a function of the sound system. A type of Quad SPI See 2.2.1 See AC specification on the datasheet. See 2.2.1 See 2.2.1 See 2.2.3 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 Page 5 of 225 S6J3200 Series Function 3D Graphic engine Vector drawing on 3D engine 3D Driver API Description Option Option Option Remark See 2.2.1 See 2.2.1 See 2.2.1 Notes: − The options are described in 2.2. − The described specifications in the table which are related the electric characteristics only show the typical values. They don’t necessarily include the width of characteristics, errors, and so on. They should be seen in the datasheet in detailed. − − Target resolution of graphics is WVGA 800 x 480, WQVGA 480 x 272. Target capture resolution of graphics is WVGA 800 x 480. Document Number: 002-05682 Rev. *Q Page 6 of 225 S6J3200 Series 2.2 Optional Function 2.2.1 Basic Option The following figure shows the optional function and the part number relations of the series. 2.2.1.1 S6J320C Figure 2-1: Option and Part Number for S6J320C *1 TCRAM: 128 KB + System-RAM: 128 KB 1) Please contact your Cypress sales representative to receive the customer information CI708-0001 2) Please contact your Cypress sales representative to receive the product errata notification PEN182201 Document Number: 002-05682 Rev. *Q Page 7 of 225 S6J3200 Series Table 2-2: Function Digit Table S6J32X (X = Function Digit) Part Number Function Digit CPU Clock Maximum Graphics Clock Maximum Display Output Support Video Capture Support Graphic Engine Type HyperBus Interface Sound System FPD-Link Media System Chip Select Output of MFS I2 C 3 240 MHz 4 240 MHz 5 240 MHz 6 240 MHz 7 240 MHz 8 240 MHz 9 240 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 1 unit 2D ch.0, 1 N/A N/A YES 1 unit 2D ch.0, 1 YES N/A YES 1 unit 2D, 3D ch.0, 1 N/A N/A YES 1 unit 2D, 3D ch.0, 1 YES YES YES 1 unit 2D ch.0, 1, 2 YES N/A YES 1 unit 2D, 3D ch.0, 1, 2 YES YES YES 1 unit 2D ch.0, 1, 2 YES YES YES YES YES YES YES YES YES YES MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 Notes: − This table only shows the relation between the optional function and the part numbers. That is, all products are not necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products. − − − The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0. − Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn’t support FPD-LINK is used for RSDS and DRGB. − Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support FPD-LINK is used for DRGB only. − HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. The media system means both Ethernet AVB and Media LB. The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of Clock Configuration. Document Number: 002-05682 Rev. *Q Page 8 of 225 S6J3200 Series 2.2.1.2 S6J320A Figure 2-2: Option and Part Number for S6J320A S 6 J 3 2 0 0 H A A x x x x x x x x Ordering options 7 digit Revision: Revision version Digit E Support MCAN 3.0.1 Option Digit S SHE ON Pin count Digit K Pin count 208 pin Memory size Digit A Description Program FLASH Work FLASH 1088KB 112KB RAM 192KB* VRAM 1024KB Function See the function digit table. Product series Digit 2 Product type Graphic SoC Identifier: Automotive MCU * TCRAM: 64 KB + System-RAM: 128 KB Document Number: 002-05682 Rev. *Q Page 9 of 225 S6J3200 Series Table 2-3: Function Digit Table Part Number S6J32X (X = Function Digit) Function Digit CPU Clock Maximum Graphics Clock Maximum Display Output Support Video Capture Support Graphic Engine Type HyperBus Interface Sound System FPD-Link Media System Chip Select Output of MFS I2 C B 160 MHz 160 MHz ch.0 N/A 2D ch.0, 1 YES N/A N/A N/A MFS ch.16, 17 Notes: − This table only shows the relation between the optional function and the part numbers. That is, all products are not necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products. − − − The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0. − Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn’t support FPD-LINK is used for RSDS and DRGB. − HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. The media system means both Ethernet AVB and Media LB. The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of Clock Configuration. Document Number: 002-05682 Rev. *Q Page 10 of 225 S6J3200 Series 2.2.1.3 S6J320E Figure 2-3: Option and Part Number for S6J320E *1 TCRAM: 128 KB + System-RAM: 384 KB Document Number: 002-05682 Rev. *Q Page 11 of 225 S6J3200 Series Table 2-4: Function Digit Table S6J32X Part Number Function Digit CPU Clock Maximum Graphics Clock Maximum Display Output Support Video Capture Support Graphic Engine Type HyperBus Interface Sound System FPD-Link Media System Chip Select Output of MFS I2C (X = Function Digit) K 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1 N/A YES YES L 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1 YES YES YES M 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1, 2 YES YES YES N 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1 N/A N/A YES YES YES YES YES MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 Notes: − This table only shows the relation between the optional function and the part numbers. That is, all products are not necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products. − − − The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0. − Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn’t support FPD-LINK is used for RSDS and DRGB. − Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support FPD-LINK is used for DRGB only. − HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. The media system means both Ethernet AVB and Media LB. The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of Clock Configuration. Document Number: 002-05682 Rev. *Q Page 12 of 225 S6J3200 Series 2.2.2 ID ID is specified for each function digit and revision, which is defined in Figure 2-1 through Figure 2-3. The Chip ID can be read from SYSC0_SYSIDR and the Platform ID can be read from SYSC0_SYSPFIDR. For SYSC0_SYSIDR and SYSC0_SYSPFIDR, see the TRAVEO™ T1G Platform hardware manual. The Graphic subsystem ID can be read from the IPIdentifier register on the graphic subsystem. See the chapter Graphic Subsystem in S6J3200 hardware manual. Function Digit Option 3, 4, 5, 6, 7, 8, 9 S and U B S K L M N S S S S Revision Chip ID JTAG ID Platform ID A B C and D E and F H J M P A B C and D E 0x10100000 0x10100100 0x10100101 0x10100102 0x10100103 0x10100104 0x10100104 0x10110000 0x10110002 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 M 0x10170000 0x100085CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x100095CF 0x100095CF 0x002705CF 0x002715CF 0x002725CF 0x002735CF Graphic Subsystem N/A N/A 0x23443420 0x23443470 0x23443480 0x23443490 0x23443490 N/A 0x23442450 0x00110200 0x23443490 2.2.3 Restriction Some functions have restrictions which depend on package pin counts. Table 2-5 Function TEQFP256 TEQFP216 Analog input port (12 bitADC) AN0 to AN49 (50 ports) AN0 to AN49 (50 ports) SEG port of LCD controller SEG0 to SEG31 (32 ports) SEG0 to SEG31 (32 ports) Document Number: 002-05682 Rev. *Q TEQFP208 AN1 to AN3, AN5 to AN17, AN20 to AN49 (46 ports) SEG0 to SEG29 (30 ports) Page 13 of 225 S6J3200 Series Function General Purpose I/O PPG triggered input TEQFP256 P0_00, P0_01, P0_02, P0_03, P0_04, P0_05, P0_06, P0_07, P0_08, P0_09, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_26, P0_27, P0_28, P0_30, P0_31, P1_00, P1_01, P1_02, P1_03, P1_04, P1_05, P1_06, P1_07, P1_08, P1_09, P2_16, P2_17, P2_19, P2_22, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, P3_00, P3_01, P3_02, P3_03, P3_04, P3_05, P3_06, P3_07, P3_08, P3_09, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, P4_00, P4_01, P4_02, P4_03, P4_04, P4_05, P4_06, P4_07, P4_08, P4_09, P4_10, P4_11, P4_12, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, P5_00, P5_01, P5_02, P5_03, P5_04, P5_05, P5_06, P5_07, P5_08, P5_09, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, P5_16, P5_17, P5_18, P5_19, P5_20, P5_21, P5_22, P5_27, P5_28, P5_29, P5_30, P5_31, P6_00, P6_01, P6_02, P6_03, P6_04, P6_05, P6_06, P6_07, P6_08, P6_09, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, P6_16, P6_17, P6_18, P6_19, P6_20, P6_21, P6_22, P6_23, P6_24, P6_25, P6_26 (154 ports) PPG0/1/2/3/4/5_TIN1, PPG6/7/8/9/10/11_TIN TEQFP216 P0_00, P0_01, P0_02, P0_03, P0_04, P0_05, P0_06, P0_07, P0_08, P0_09, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_26, P0_27, P0_28, P0_30, P0_31, P1_00, P1_01, P1_02, P1_03, P1_04, P1_05, P1_06, P1_07, P1_08, P1_09, P2_16, P2_17, P2_19, P2_22, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, P3_00, P3_01, P3_02, P3_03, P3_04, P3_05, P3_06, P3_07, P3_08, P3_09, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, P4_00, P4_01, P4_02, P4_03, P4_04, P4_05, P4_06, P4_07, P4_08, P4_09, P4_10, P4_11, P4_12, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, P5_00, P5_01, P5_02, P5_03, P5_04, P5_05, P5_06, P5_07, P5_08, P5_09, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, P5_16, P5_17, P5_18, P5_19, P5_20, P5_21, P5_22, P5_27, P5_28, P5_29, P5_30, P5_31, P6_00 (128 ports) PPG0/1/2/3/4/5_TIN1, PPG6/7/8/9/10/11_TIN TEQFP208 P0_00, P0_01, P0_04, P0_05, P0_06, P0_07, P0_08, P0_09, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_26, P0_27, P0_28, P0_30, P0_31, P1_00, P1_01, P1_02, P1_03, P1_04, P1_05, P1_06, P1_07, P1_08, P1_09, P2_16, P2_17, P2_19, P2_22, P2_25, P2_26, P2_27, P2_29, P2_30, P2_31, P3_00, P3_01, P3_02, P3_03, P3_04, P3_05, P3_06, P3_07, P3_08, P3_09, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, P4_00, P4_01, P4_02, P4_03, P4_04, P4_05, P4_06, P4_07, P4_08, P4_09, P4_10, P4_11, P4_12, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, P5_00, P5_01, P5_02, P5_03, P5_04, P5_05, P5_06, P5_07, P5_08, P5_09, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, P5_16, P5_17, P5_18, P5_19, P5_20, P5_21, P5_22, P5_27, P5_28, P5_29, P5_30, P5_31, P6_00 (120 ports) PPG6/7/8/9/10/11_TIN Notes: − See multiplexed functions on pin assignment sheet. − The optional restriction will be added without notification. Document Number: 002-05682 Rev. *Q Page 14 of 225 S6J3200 Series 3. Product Description 3.1 Overview This section explains the product features of the S6J3200 series. The description of this section should precede the duplicated description on platform manual. 3.2 Product Description Table 3-1: Product Features Feature Technology Functional Safety Peripherals Power Domain (PD) Debug and Trace Description 55-nm CMOS technology with embedded flash Fully automotive qualified according to ISO/TS 16949 and AEC-Q100 The product series has some functional safety features suited for ASIL-B application. See function list. See the platform manual and the STATE TRANSITION chapter in detail. The product series supports the power-off control of PD2 (including PD3 and 5), PD4_0, PD4_1, and PD6. The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series, and "0" is always read from the reset factor flags of them. This series does not support partial wakeup for PD6. See the platform manual in detail. − Standard 5-pin JTAG interface − 4k Word Embedded Trace Buffer 4-bit trace support for TEQFP package. Full trace (dedicated 16-bit port) with special bond-out package is planned. See the platform manual in detail. Main and sub oscillator is available. System Control Clock Embedded CR oscillation Clock Supervisor Reset Hardware Watchdog − A wide range of 3.6 - 16 MHz is available for main oscillator − 32 KHz is available for sub oscillator Sub clock is enable/disable by register settings See the platform manual in detail. CLK_CLKO (Clock Output Function) is not supported. Main Oscillation Stabilization Wait Time (at 4 MHz):8.19 ms (Initial value) See the platform manual in detail. Stabilization time is as followings. − 0.35 ms to 0.8 ms for 4 MHz (Fast clock) − 0.43 ms to 1.28 ms for 100 kHz (Slow clock) See the platform manual in detail. This product series does not support the clock supervisor output port. (Related register and internal circuit is implemented.) See the platform manual in detail. Following resets are not mounted on this device or not supported. − INITX: INITX is issued by simultaneous assert of RSTX and MODE, but this product series does not support INITX. − SRSTX (and nSRST pin) The product series does not support EX5VRST and writing EX5VRSTCNT bits in SYSC0_SPECFGR has no effect. See the platform manual in detail. Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the bit ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1). The product series does not support Watchdog Counter Monitor Output port. (Related register and internal circuit is implemented.) Document Number: 002-05682 Rev. *Q Page 15 of 225 S6J3200 Series Feature Software Watchdog Standby Mode Description See the platform manual in detail. The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and internal circuit is implemented.) See the platform manual in detail. Standby mode with 5 V single power supply is available. Turning off the 3.3-V supply and the external 1.2-V supply in standby mode is available. The long term pulse of the indicator PWM can be outputted during RTC Standby mode. See the platform manual in detail. Use case assumption is following. − PLL ➢ Sound system clock ➢ Sound frequency master clock ➢ Peripherals ➢ Display clock ➢ Trace clock PLL / SSCG PLL − SSCG ➢ CPU core ➢ GDC core ➢ HyperBus ➢ DDR-HSSPI External Interrupts NMI Memory Protection Product supports down spread and center spread modes with the conditions defined in chapter "Internal Clock Timing" on the datasheet. See the platform manual in detail. See the platform manual in detail. 1 NMI pin. MPU16 AHB: See the platform manual in detail. MPU for AXI: ch.0 (Supervise Ethernet) MPU for AHB: ch.1 (Supervise Media LB) Additional MPU for Graphic sub system, MediaLB and Ethernet AVB. They are described on the chapter of MPU for AHB and MPU for AXI. To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK, Peripheral Protection Internal Memories System RAM Internal Memories TCRAM Internal Memories Backup RAM Internal Memories VRAM − Lock: 0x112ABB56 − Unlock: 0xACCABB56 See the platform manual in detail. Protected peripherals are described in the base address map. See the platform manual in detail. 1 wait cycle is necessary for RAM read at over 160 MHz. No need to insert wait cycles for RAM write. See the platform manual in detail. 16 KB Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM is not supported and cannot be used. ECC region is shared with user region. Memory size available for user program become less when ECC is enabled. User can define ECC enabled area and ECC disabled area. Single error correction, double error detection (SECDED) ECC support per 32-bit word. Document Number: 002-05682 Rev. *Q Page 16 of 225 S6J3200 Series Feature Embedded Program/Work Flash Memory Security Internal Power Domain Power Supply Low-voltage Detection Low-voltage Detection for RAM Retention (RVD) Resource inter-connect I/O Ports A/D Converter CRC Programmable CRC Sound Generator Description Embedded Program flash can be accessed with 0-wait-cycle if CPU frequency is 80 MHz or less. 0-wait-cycle: 80 MHz or less. 1-wait-cycle: 160 MHz or less. 2-wait-cycle: more than 160 MHz. The maximum frequency should be referred in datasheet. Erase suspend is supported. Reading and writing to the other sector are possible when Flash Erase is suspended. Serial Flash programing and Parallel Flash programing are supported. Margin mode is not supported. Chip erase function is available for flash memory. The function of "MK_CEER" is not supported. (MK_CEER = not selectable) For details, see the platform manual and chapter "Security" PD1: Always ON PD2: Cortex R5F platform/ GDC/ additional peripherals PD4: Backup RAM in Always On domain PD6: Peripherals in Always On domain * The chapter of the block diagram explains in detail. External 5 V, 3 V, 1.2 V is required. Built in LDO provides internal 1.2 V for Always On region (PD1). External 1.2-V power supply control pin is supported. External 3.3-V power supply should be controlled by GPIO. There are constraints of power on/off sequence. LVD for external voltage is supported. LVD for internal voltage is supported. See the specification of the detected level on the datasheet. RVD for RAM retention is effective during the standby mode only. That is, it is only for the Backup RAM of 16 KB that the function is available. The output signal of some resources can be inputted to the other resource. 5-V GPIO 3-V GPIO Multi input level and multi output drivability Pull-up, pull-down function is available. Resource input and output is multiplexed. +B input is allowed many pins of 3.3 V, 5 V, and 3.3 V/5 V I/O domain. 12-bit resolution, 1 unit 50 channels of analog input for TEQFP256 and TEQPF216 46 channels of analog input for TEQFP208 24 channels of them are shared with the SMC for TEQFP256/216/208 External trigger and timer trigger are available. The description of the A/D converter function should be referred in the S6J3200 hardware manual. Though the chapter of I/O port in TRAVEO™ T1G PF V3 hardware manual describes another A/D converter function, do not refer it. See the platform manual in detail. DMA support Produces sound/melody with varying frequency and amplitude for convenient duration Square wave sound output Automatic linear amplitude increment or decrement Interrupt request generated when specified sound length has ended Document Number: 002-05682 Rev. *Q Page 17 of 225 S6J3200 Series Feature Sound Waveform Generator Sound Mixer PCM-PWM Audio DAC I2S Description Sine waveform, saw-tooth waveform and Square waveform are generated with easy configuration of the parameters which specified sound sources. Fade-in and Fade-out control for reverberation. The input channels of 0-4 are reserved for waveform generator. Mixing different sampling frequency sounds. Mixing Internal sounds and External I2S input sounds. Saturating addition function for keeping sound quality. Cut a specific frequency data by digital filter. LPF is support by FIR filter. Fade-in and Fade-out control. Conversion of PCM audio streaming to Pulse Width Modulated signals. Supports 2 output channels for stereo and mono data Up to 16-bit output sample resolution Support for half and full H-bridges The sound source of the fixed 48 kHz sampling frequency can be outputted. 1unit, L/R channels support. BTL connection is available. 2 ch. − I2S0 can output sound sources which are processed by Sound System. − I2S1 can input sound sources which are processed by Sound System. See the "Sound System Configuration" of S6J3200 hardware manual in detail. See the platform manual in detail. Base Timer Reload Timer I/O Timer Quad Position & Revolution Counter (Up/Down Counter) A unit consists of a pair of 16-bit base timers. 12 units, that is, 24 channels of base timers are available. See the platform manual in detail. See the platform manual in detail. See the platform manual in detail. See the platform manual in detail. 5 ports of MFS only support I2C. Note − Multi-functional Serial (MFS) Not all pins support I2C. Only pins which have the I2C I/O characteristics support it. See the datasheet in detail. The I2C is not designed to be hot swappable. The availability of chip select function can be seen at Function Digit Table. Chip Select Input is not supported. CTS/RTS is not mounted (hardware flow control is not supported for this series.) CAN-FD Real Time Clock (RTC) with Auto-calibration WUCR function is not supported for this product. Flexible data rate is supported. 16 KB/ch of message RAM is available. The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function of the message RAM is not supported for this device. Therefore, CAN FD ECC Error Insertion Control Register (FDFECR) is not writeable. See the platform manual in detail See the platform manual in detail. Document Number: 002-05682 Rev. *Q Page 18 of 225 S6J3200 Series Feature DDR High Speed SPI HyperBus I/F Description ch.0: HSSPI as a MCU peripheral ch.1: HSSPI on graphic subsystem See the platform manual in detail ch.0: HyperBus as a MCU peripheral ch.1: HyperBus on graphic subsystem ch.2: HyperBus on graphic subsystem The following register is not supported and cannot be used. − Controller Status Register (HYPERBUSIn_CSR) − Interrupt Enable Register (HYPERBUSIn_IEN) − Interrupt Status Register (HYPERBUSIn_ISR) − Write Protection Register (HYPERBUSIn_WPR) − Test Register (HYPERBUSIn_TEST) GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can select using HyperBus of PF or using HyperBus of Graphic Sub System. See the "HyperBus Interface Port Configuration" of S6J3200 hardware manual in detail. Stepper Motor Control (SMC) External Interrupt Capture Unit (EICU) Ethernet AVB Each channel has four motor drivers with high output capability See the platform manual in detail. 10/100 Mbps MII-Interface Supports Audio-Video Bridging (AVB) ETHERNETn_revision_reg : 0x30070106 (Initial value) for after revision B ETHERNETn_designcfg_debug6: 0x0302000E (Initial value) MediaLB LCD Controller SHE Source Clock Timer Graphics Subsystem FPD-Link Converter See 0 in details. MOST25 (512FS) 3 wires Maximum 15 ch is available. TEQFP256: 4 com x 32 seg TEQFP216: 4 com x 32 seg TEQFP208: 4 com x 30 seg LCDC pins are initialized with Reset. (Stop LCDC alternating current output). Duty and Static of segment output is supported. (SEG23/ST0, SEG24/ST1, SEG25/ST2, SEG26/ST3, SEG27/ST4, SEG28/ST5, SEG29/ST6, SEG30/ST7, SEG31/ST8) See the platform manual in detail. See the platform manual in detail. Variable setting about GDC clock. (Asynchronous with CPU clock) Two drawing engines for “2D drawing” and “3D drawing”. Parallel processing support. CPU can direct access to VRAM. Programmable panel timing controller with RGB888 and RSDS support. LFCTRL and FRANGE bit of CTRL1. See chapter FPD-Link Converter about function. -These register bit are supported for revision M, P. -These register bit are not supported for revision F and J. These bit are reserved bit(Access type is R0,W0. Initial value is 0). Document Number: 002-05682 Rev. *Q Page 19 of 225 S6J3200 Series Feature Power Supply Control (PSC) Description PSC (PSC_1) output is used for external 1.2-V power supply module control and automatically switched with the following condition. "High": Request to supply VCC12 - "Power ON Reset" is released - CPU wakes up from PSS shutdown mode "Low": Request to stop supplying VCC12 - CPU transfers from RUN mode to PSS shutdown mode. For timing chart of output signals include PSC in detail, see the "S6J3200 hardware manual" and chapter "State Transition" Document Number: 002-05682 Rev. *Q Page 20 of 225 S6J3200 Series 3.2.1 Ethernet The following functions are not supported. Functions Remark External FIFO Interface Additional Low Latency TX FIFO Interface for DMA configurations MAC Transmit Block - half-duplex - collision - back_pressure MAC Filtering Block - external address match - Wakeup On Lan Energy Efficient Ethernet support LPI Operation in Cadence IP PHY Interface - GMII - SGMII - TBI 10/100/1000 Operation - 1000 M SGMII Operation Jumbo Frames Physical Control Sub-Layer Document Number: 002-05682 Rev. *Q Page 21 of 225 S6J3200 Series 4. Package and Pin Assignment 4.1 Pin Assignment The characters next to the pin number in the pin assignment drawing specify the I/O circuit type. Figure 4-1: Pin Number and I/O Circuit Type 0 DAC_R A 3 0 0 C_R A 4 0 0 AVSS - 5 0 0 AVCC3_DAC - 6 0 0 DAC_L A 7 0 0 C_L A 8 0 0 AVSS - 9 0 0 VSS - 10 0 0 VCC12 - 11 0 0 AVSS_LVDS_PLL - 12 0 0 AVCC3_LVDS_PLL - 13 0 0 VCC3_LVDS_Tx - 14 0 0 VSS_LVDS_Tx - 15 0 0 TxDOUT3+ B 16 0 0 TxDOUT3- B 17 0 0 TxDOUT2+ B 18 TEQFP-216 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 - TEQFP-208 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 4-14 Figure 4-15 Figure 4-16 215 2 0 216 1 - - - AVSS Y VSS 0 VCC53 Document Number: 002-05682 Rev. *Q 0 0 DSP1_CTRL0 Function Digit S6J328, S6J329, S6J32M S6J327 S6J326, S6J32L S6J325, S6J32N S6J324 S6J323 S6J32K B 0 0 I/O Circuit Type 0 Pin Number ○ TEQFP-256 Figure 4-17 - Page 22 of 225 S6J3200 Series TEQFP-216 Pin Assignment 4.1.1 Figure 4-2: TEQFP-216 (S6J328CLxx, S6J329CLxx, S6J32MELxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 EINT7 EINT3 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 PPG0_TOUT0 PPG11_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6/7/8/9/10/11_TIN TIN48 0 0 ICU0_IN1 ICU4_IN1 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 0 0 ICU0_IN0 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 TIN18 OCU0_OTD0 WOT TOT18 0 0 TOT19 0 0 0 0 0 0 OCU2_OTD0 SGO0 TOT32 SOT10 0 TIN19 0 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 0 0 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU1_OTD1 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 - X X W W W W W W W W V V V U - - 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 0 0 0 0 0 0 0 0 0 0 OCU3_OTD0 SGA3 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_10 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 DSP1_DATA0_6 0 DSP1_DATA0_10 0 DSP1_DATA1_5 VCC53 VSS Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 0 TOT17 0 0 0 0 SEG13 0 199 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 0 0 SEG12 AIN8 Y 0 P5_07 OCU8_OTD1 DSP1_DATA0_5 0 P5_08 ICU8_IN1 0 0 0 0 0 200 0 0 PPG8_TOUT2 0 SOT10 Y 0 EINT9 OCU9_OTD0 BIN8 DSP1_DATA1_4 0 SEG11 ICU9_IN0 0 P5_09 0 0 0 0 PPG9_TOUT0 0 SCK10 0 EINT10 ZIN8 201 SEG10 OCU9_OTD1 202 P5_10 ICU9_IN1 - Y MFS8_CS0 0 0 VCC53 DSP1_DATA0_4 MFS10_SDA PPG9_TOUT2 0 EINT11 0 SEG9 0 P5_11 0 MFS9_CS0 0 0 0 SIN10 0 MFS10_SCL 0 AIN9 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - - G H I J J I I I I I J J I I I I I L - VCC12 VSS VCC5 PSC_1 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 0 0 0 0 0 0 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 0 0 0 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 SGO0 SGA0 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 OCU8_OTD0 ICU8_IN0 OCU8_OTD1 ICU8_IN1 OCU9_OTD0 ICU9_IN0 OCU9_OTD1 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU10_OTD1 ICU10_IN1 0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD0 ICU10_IN0 0 0 0 0 0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 OCU6_OTD0 ICU6_IN0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 0 0 OCU3_OTD0 ICU3_IN0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 ZIN9 OCU7_OTD1 ICU7_IN1 FRT8/9/10/11_TEXT PPG7_TOUT2 0 0 BIN9 OCU7_OTD0 ICU7_IN0 0 0 AIN9 OCU6_OTD1 ICU6_IN1 0 0 0 ZIN8 OCU5_OTD0 ICU5_IN0 0 0 0 BIN8 OCU4_OTD1 ICU4_IN1 0 0 0 AIN8 OCU4_OTD0 ICU4_IN0 0 0 0 SIN1 OCU4_OTD1 ICU4_IN1 0 0 SCK1 0 0 0 SOT1 0 0 OCU7_OTD1 ICU7_IN1 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT8 EINT9 0 0 0 0 0 0 0 P2_24 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 EINT15 P2_31 0 PPG11_TOUT0 EINT6 P0_28 0 EINT14 P2_30 0 EINT3 P0_27 0 0 0 P0_26 0 EINT13 P2_29 0 EINT2 0 0 EINT12 P2_28 0 EINT1 0 0 0 G_DQ4_1 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT11 P2_27 INDICATOR0_0 0 EINT0 P1_02 M_DQ7_0 EINT10 P2_26 0 PPG10_TOUT2 EINT5 0 0 PPG10_TOUT0 EINT4 0 EINT10 P1_03 M_DQ6_0 EINT9 P1_00 M_DQ5_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 89 - 0 0 0 P1_01 M_DQ4_0 88 DSP0_CTRL4 0 0 0 EINT7 87 MLBCLK 0 0 PPG8_TOUT0 EINT8 F CAP0_DATA25 0 0 0 PPG6_TOUT2 86 DSP0_CTRL3 0 0 PPG7_TOUT0 MLBSIG 0 CAP0_DATA24 0 0 0 F 0 0 OCU8_OTD0 ICU8_IN0 0 85 0 DSP0_CTRL2 0 OCU6_OTD1 ICU6_IN1 MLBDAT 0 0 OCU7_OTD0 ICU7_IN0 VCC3 0 0 F 0 0 0 0 G_CS#2_1 0 - G_SDATA0_3 0 0 P0_31 M_CS#2_0 84 VSS 0 0 0 83 M_SDATA1_3 0 EINT6 - 0 0 0 E 0 0 0 PPG6_TOUT0 82 0 0 0 81 G_SSEL0 0 0 M_SSEL1 0 0 E 0 0 OCU6_OTD0 ICU6_IN0 80 0 0 G_SDATA0_1 0 G_SDATA0_2 0 M_SDATA1_1 0 M_SDATA1_2 0 E 0 E 0 79 0 78 0 0 0 0 0 0 G_RWDS_1 0 0 0 G_SDATA0_0 0 VCC3 P0_30 M_RWDS_0 M_SDATA1_0 0 E EINT5 - 0 77 PPG5_TOUT2 76 0 0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 0 P1_09 M_CK_0 0 0 0 0 G_SCLK0 PPG9_TOUT0 0 0 VSS 0 0 0 0 0 - 0 PPG11_TOUT0 EINT0 0 E 0 0 75 0 0 74 0 0 OCU9_OTD0 ICU9_IN0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 0 VSS 0 0 0 - 0 0 0 0 73 0 0 0 0 0 0 0 G_CS#1_1 0 0 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 G_SDATA1_3 0 0 OCU10_OTD1 ICU10_IN1 0 M_SDATA0_3 0 0 0 E 0 0 0 72 0 0 0 0 0 G_DQ0_1 0 0 EINT11 P1_04 M_DQ0_0 0 0 0 PPG8_TOUT2 G_SSEL1 0 0 0 M_SSEL0 0 0 OCU8_OTD1 ICU8_IN1 E 0 0 0 71 0 0 0 0 0 0 0 0 G_DQ1_1 G_SDATA1_1 0 0 G_DQ2_1 G_SDATA1_2 0 EINT13 P1_06 M_DQ1_0 M_SDATA0_1 0 PPG9_TOUT2 M_SDATA0_2 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 E 0 0 E 0 0 OCU9_OTD1 ICU9_IN1 70 0 OCU10_OTD0 ICU10_IN0 0 69 G_SDATA1_0 0 0 M_SDATA0_0 0 G_DQ3_1 E 0 EINT12 P1_05 M_DQ3_0 68 0 0 0 0 0 0 0 G_CK_1 0 0 0 0 VCC3 0 VSS 0 VSS 0 VCC12 M_SCLK0 0 - 0 - 0 E 0 - 0 - DSP0_CTRL1 67 0 DSP0_CTRL0 66 0 DSP0_CLK 65 0 64 P5_22 0 0 63 PPG10_TOUT0 EINT4 P0_17 0 OCU10_OTD0 ICU10_IN0 0 P0_16 0 0 0 EINT2 DSP0_CTRL2 0 EINT1 G_DQ7_2 0 PPG9_TOUT0 G_DQ6_2 TXER PPG8_TOUT2 G_DQ5_2 CAP0_DATA34 0 0 G_DQ4_2 DSP0_CTRL2 0 P0_15 0 0 0 DSP0_CTRL0 OCU9_OTD0 ICU9_IN0 EINT0 C OCU8_OTD1 ICU8_IN1 EINT15 P0_14 0 62 0 TIN35 I2S1_SCK 0 EINT14 P0_13 0 TOT35 I2S1_WS EINT13 P0_12 0 0 0 COL PPG8_TOUT0 DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK PPG7_TOUT2 DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 PPG7_TOUT0 D 0 PPG6_TOUT2 D 0 61 0 60 0 0 0 0 0 0 DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD 0 TXCLK TOT33 I2S0_WS DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 OCU8_OTD0 ICU8_IN0 DSP0_DATA1_9 DSP0_DATA_D9- CAP0_DATA22 0 OCU7_OTD1 ICU7_IN1 VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 OCU7_OTD0 ICU7_IN0 D OCU6_OTD1 ICU6_IN1 D 0 D 0 D 0 - 0 59 RXCLK TIN33 I2S0_SCK 0 58 0 57 0 56 0 55 Page 23 of 225 Document Number: 002-05682 Rev. *Q 0 PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 136 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 0 AP1(AH1) 0 0 ICU10_IN0 OCU10_OTD0 0 0 0 AN30 0 0 S 0 PPG10_TOUT0 137 TOP VIEW TEQFP-216 0 0 26 0 EINT12 - DSP0_DATA1_11 0 VSS_LVDS_Tx DSP0_DATA0_11 SEG8 0 0 0 0 0 P5_12 0 DSP0_DATA1_10 0 0 0 0 MFS9_CS1 0 0 0 0 0 0 0 0 0 203 0 0 - 0 0 0 VSS P3_26 0 0 PPG9_TOUT0 EINT10 0 0 OCU9_OTD0 ICU9_IN0 0 0 PWM1M1 0 0 AN1(AL1) 0 0 0 0 0 AN31 0 0 S 0 0 138 0 0 25 0 0 B 0 0 TxDOUT0- 0 0 0 0 0 0 0 0 0 0 0 204 0 0 205 0 0 206 0 0 207 0 0 208 0 0 0 Y 0 P3_27 0 Y P3_28 PPG9_TOUT2 EINT11 0 Y PPG10_TOUT0 EINT12 OCU9_OTD1 ICU9_IN1 0 Y OCU10_OTD0ICU10_IN0 PWM2P1 0 Y PWM2M1 BP1(BH1) 0 DSP1_DATA1_3 BN1(BL1) 0 0 DSP1_DATA0_3 0 AN32 0 DSP1_DATA1_2 AN33 S 0 DSP1_DATA1_1 S 139 0 0 140 24 0 0 23 B 0 DSP1_CLK DSP1_DATA0_2 B TxDOUT0+ 0 0 DSP0_CTRL0 TxDOUT1- 0 0 0 DSP0_CTRL1 0 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 0 DSP0_CTRL3 0 0 0 0 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT11 0 0 0 SCK11 0 0 0 SIN11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZIN9 0 0 OCU0_OTD0 DVSS 0 OCU0_OTD1 0 ICU0_IN0 141 0 ICU0_IN1 22 0 0 ICU10_IN1 OCU10_OTD1 BIN9 B 0 0 ICU11_IN0 OCU11_OTD0 TxDOUT1+ 0 0 ICU11_IN1 OCU11_OTD1 0 0 0 0 0 0 0 0 PPG0_TOUT0 0 0 PPG0_TOUT2 0 0 PPG10_TOUT2 0 0 0 PPG11_TOUT0 0 0 PPG11_TOUT2 0 0 EINT0 0 0 0 EINT1 0 0 0 EINT13 0 0 0 EINT14 0 0 0 EINT15 0 0 0 SEG7 0 0 0 SEG6 DVCC 0 0 SEG5 - 0 0 SEG4 142 0 0 SEG3 21 0 0 P5_13 B 0 0 P5_14 TxCLK0 P5_15 0 0 P5_16 0 0 0 P5_17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS8_CS3 0 0 P3_29 0 0 0 0 0 MFS8_CS1 0 P3_30 PPG10_TOUT2 EINT13 0 0 0 0 0 MFS8_CS2 0 PPG11_TOUT0 EINT14 OCU10_OTD1ICU10_IN1 0 0 0 0 0 0 OCU11_OTD0ICU11_IN0 PWM1P2 0 0 0 0 0 0 PWM1M2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AN34 0 0 0 0 0 0 AN35 S 0 0 0 0 0 209 S 143 0 0 0 0 Y 144 20 0 0 0 DSP1_DATA0_1 19 B 0 0 DSP0_CTRL5 DSP1_CTRL1 B TxCLK+ 0 0 SOT12 TxDOUT2- 0 0 0 0 0 0 OCU1_OTD0 0 0 0 ICU1_IN0 0 0 0 0 0 0 0 PPG1_TOUT0 0 P3_31 0 EINT2 0 P4_00 PPG11_TOUT2 EINT15 0 SEG2 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 P5_18 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 MFS12_SDA 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 0 210 OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 0 211 PWM2P3 0 0 AN37 S 0 Y 0 SOT2 AN38 S 145 0 Y SCK2 AN39 S 146 18 0 DSP1_DATA1_0 AN40 S 147 17 B 0 0 DSP1_DATA0_0 S 148 16 B TxDOUT2+ 0 0 0 149 15 B TxDOUT3- 0 0 0 0 14 - TxDOUT3+ 0 0 0 0 DSP0_CTRL6 - VSS_LVDS_Tx 0 0 0 0 0 DSP0_CTRL7 VCC3_LVDS_Tx 0 0 0 0 0 0 SCK12 0 0 0 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 0 0 0 OCU1_OTD1 P4_04 0 0 OCU2_OTD0 PPG2_TOUT0 EINT4 0 0 ICU1_IN1 OCU2_OTD0 ICU2_IN0 0 0 ICU2_IN0 PWM2M3 0 0 0 0 0 0 SIN2 0 PPG1_TOUT2 AN41 0 PPG2_TOUT0 S 0 EINT3 150 0 EINT4 13 0 SEG1 0 SEG0 AVCC3_LVDS_PLL 0 P5_19 0 0 P5_20 0 0 0 0 0 0 MFS12_SCL 0 0 0 0 0 0 0 0 0 0 0 0 212 0 0 0 213 0 0 0 214 0 0 0 215 0 0 0 216 0 0 0 - 0 DVSS 0 Y DVCC - 0 Y 151 0 Y 152 12 0 Y 11 0 VCC53 - AVSS_LVDS_PLL 0 DSP1_CLK VCC12 0 0 DSP1_CTRL2 0 0 DSP1_CTRL1 0 0 DSP1_CTRL0 P4_05 0 0 PPG2_TOUT2 EINT5 0 0 OCU2_OTD1 ICU2_IN1 0 0 PWM1P4 0 0 0 0 0 0 C_L 0 AN42 DAC_L 0 DSP0_CTRL8 S 0 0 DSP0_CTRL9 153 0 0 0 0 10 0 0 0 0 0 0 SOT11 0 VSS 0 0 0 SCK11 DSP0_CTRL10 MFS0_CS0 0 0 0 SIN11 DSP0_CTRL11 P4_06 0 0 0 PPG3_TOUT0 EINT6 0 0 0 OCU3_OTD0 ICU3_IN0 0 0 0 PWM1M4 0 0 0 0 0 0 0 SOT3 0 0 OCU0_OTD1 AN43 0 0 OCU1_OTD0 SGA1 S 0 0 OCU1_OTD1 SGO1 154 0 0 OCU2_OTD0 9 0 0 - ICU0_IN1 0 AVSS AVCC3_DAC ICU1_IN0 0 MFS2_CS0 0 ICU1_IN1 MFS2_CS1 P4_07 0 ICU2_IN0 P4_08 PPG3_TOUT2 EINT7 0 0 PPG4_TOUT0 EINT8 OCU3_OTD1 ICU3_IN1 0 0 OCU4_OTD0 ICU4_IN0 PWM2P4 0 0 PWM2M4 0 0 0 0 SCK3 0 0 SIN3 AN44 0 0 AN45 S 0 PPG0_TOUT2 S 155 0 PPG1_TOUT0 156 8 0 PPG1_TOUT2 0 7 A 0 PPG2_TOUT0 0 A 0 0 P4_09 0 EINT9 PPG4_TOUT2 EINT9 0 EINT10 OCU4_OTD1 ICU4_IN1 0 EINT11 PWM1P5 5 EINT12 0 4 VSS 0 0 3 A AVSS COM3 AN46 2 A C_R 0 COM2 S - DAC_R 0 0 COM1 MFS4_SDA 157 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 162 0 0 ○ 0 Note: − The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-3: TEQFP-216 (S6J327CLxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 EINT7 EINT3 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 PPG0_TOUT0 PPG11_TOUT2 0 0 0 0 0 0 0 0 FRT4/5/6/7_TEXT 0 0 0 0 0 0 PPG6/7/8/9/10/11_TIN FRT0/1/2/3_TEXT TIN48 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU11_IN1 ICU1_IN1 0 0 0 OCU0_OTD0 OCU0_OTD1 OCU4_OTD1 OCU4_OTD0 OCU3_OTD1 OCU3_OTD0 OCU2_OTD1 OCU2_OTD0 OCU1_OTD1 OCU1_OTD0 OCU0_OTD1 OCU0_OTD0 OCU11_OTD1 0 0 0 0 0 0 SGO2 0 TOT19 0 TOT17 0 TIN18 WOT TOT18 0 TIN19 0 0 0 0 0 SIN11 SIN10 SGO0 TOT32 SOT10 0 TIN34 0 SGA0 TIN32 SCK10 0 0 SGA1 TOT33 0 0 SGA2 TOT34 SCK11 SGO1 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 - X X W W W W W W W W V V V U - - 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 MFS10_SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_11 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 EINT11 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 PPG9_TOUT2 PPG9_TOUT0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU9_IN1 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 OCU9_OTD1 OCU9_OTD0 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 OCU3_OTD1 OCU3_OTD0 OCU2_OTD1 0 0 ZIN8 BIN8 AIN8 0 0 0 0 0 0 0 0 0 0 0 0 0 SGO3 SGA3 0 0 0 0 SCK10 0 SOT10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 DSP1_DATA1_4 0 DSP1_DATA0_5 0 DSP1_DATA1_5 0 DSP1_DATA0_6 0 DSP1_DATA1_6 0 DSP1_DATA0_7 0 DSP1_DATA1_7 0 0 0 0 VSS VCC12 VCC12 0 DSP1_DATA1_8 0 DSP1_DATA0_9 0 DSP1_DATA1_9 0 DSP1_DATA0_10 0 DSP1_DATA1_10 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 VCC53 0 DSP1_DATA0_8 0 VCC53 0 DSP1_DATA0_4 VCC53 VSS - Y Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 TIN33 SOT11 0 0 0 0 INDICATOR0_1 0 MFS10_SCL 0 203 0 204 0 205 0 206 SIN10 207 0 - 208 0 Y 0 Y AIN9 Y 0 VSS Y OCU10_OTD0 0 Y 0 0 DSP1_DATA1_3 ICU10_IN0 0 0 DSP1_DATA0_3 0 DSP0_CTRL0 0 DSP0_CTRL1 DSP1_CLK DSP1_DATA0_2 DSP0_CTRL2 DSP1_CTRL2 DSP1_DATA1_2 0 0 DSP0_CTRL3 PPG10_TOUT0 0 DSP0_CTRL4 DSP1_CTRL0 DSP1_DATA1_1 0 0 0 EINT12 0 0 0 SOT11 0 SIN11 0 SCK11 0 0 0 SEG8 0 0 0 0 0 P5_12 0 0 0 0 0 0 ZIN9 BIN9 MFS9_CS1 0 0 OCU10_OTD1 0 0 0 OCU11_OTD0 0 0 OCU0_OTD0 OCU11_OTD1 OCU0_OTD1 ICU0_IN0 ICU10_IN1 ICU0_IN1 ICU11_IN0 32 ICU11_IN1 D 0 DSP0_CLK 0 DSP0_CLK+ 0 CAP0_DATA1 0 MDIO 0 0 PPG0_TOUT0 0 PPG0_TOUT2 OCU3_OTD1 PPG10_TOUT2 ICU3_IN1 PPG11_TOUT0 PPG3_TOUT2 PPG11_TOUT2 EINT15 EINT0 P0_18 EINT1 0 EINT13 0 EINT14 0 EINT15 0 SEG7 0 SEG6 DSP0_DATA0_11 SEG5 31 SEG4 C SEG3 DSP0_CTRL1 P5_13 0 P5_14 CAP0_DATA0 P5_15 MDC P5_16 0 DSP0_DATA0_4 P5_17 0 0 0 0 0 OCU9_OTD1 0 0 0 ICU9_IN1 MFS8_CS3 0 0 PPG9_TOUT2 MFS8_CS1 0 0 EINT3 MFS8_CS2 0 0 P5_21 0 0 0 0 0 0 0 DVSS 0 0 - 0 0 0 131 0 209 0 DSP0_DATA1_10 210 0 29 30 Y 0 - - Y 0 VSS VCC3 0 DSP1_DATA1_0 0 0 0 DSP0_CTRL5 DSP1_CTRL1 DSP1_DATA0_1 0 0 0 DSP0_CTRL6 0 0 0 0 SOT12 0 0 0 0 SCK12 DVCC 0 0 0 - 0 0 0 0 0 132 0 0 OCU1_OTD0 P3_22 P3_21 0 0 OCU1_OTD1 PPG7_TOUT0 EINT6 PPG6_TOUT2 EINT5 0 0 ICU1_IN0 OCU7_OTD0 ICU7_IN0 OCU6_OTD1 ICU6_IN1 0 0 ICU1_IN1 PWM1M0 PWM1P0 0 0 0 AN0(AL0) AP0(AH0) 0 0 0 0 0 0 0 PPG1_TOUT0 AN27 AN26 0 0 PPG1_TOUT2 S S 0 0 EINT2 134 133 0 0 EINT3 28 SEG2 - SEG1 VCC12 P5_18 0 P5_19 0 MFS12_SDA 0 0 MFS12_SCL 0 0 0 0 0 0 211 0 Y 0 0 DSP1_DATA0_0 0 DSP0_CTRL7 0 SIN12 0 0 0 0 0 OCU2_OTD0 0 ICU2_IN0 0 0 0 P3_23 0 PPG2_TOUT0 PPG7_TOUT2 EINT7 26 27 EINT4 OCU7_OTD1 ICU7_IN1 - - SEG0 PWM2P0 VSS_LVDS_Tx VCC3_LVDS_Tx P5_20 BP0(BH0) 0 0 0 0 0 0 0 0 AN28 0 0 212 S 0 0 213 0 0 135 0 0 214 P3_25 P3_24 0 0 215 PPG8_TOUT2 EINT9 PPG8_TOUT0 EINT8 0 0 216 OCU8_OTD1 ICU8_IN1 OCU8_OTD0 ICU8_IN0 0 0 - 159 S AN48 SCK4 RX1 PWM2P5 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT11 P4_11 MFS0_CS1 MFS4_SCL 5 158 S AN47 SOT4 0 PWM1M5 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT10 P4_10 MFS0_CS3 MFS4_SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVCC3_DAC - 6 157 S AN46 0 0 PWM1P5 OCU4_OTD1 ICU4_IN1 PPG4_TOUT2 EINT9 P4_09 0 0 162 - DVCC 0 0 0 0 0 0 0 0 0 161 - DVSS 0 0 0 0 0 0 0 0 0 160 S AN49 SIN4 TX1 PWM2M5 OCU6_OTD0 ICU6_IN0 P4_12 MFS0_CS2 PPG6_TOUT0 EINT12 S AN41 SIN2 0 PWM2M3 OCU2_OTD0 ICU2_IN0 PPG2_TOUT0 EINT4 P4_04 0 0 - 15 148 S AN39 SOT2 0 PWM1M3 OCU1_OTD0 ICU1_IN0 PPG1_TOUT0 EINT2 P4_02 0 TxDOUT3+ B 16 147 S AN38 0 0 PWM1P3 OCU0_OTD1 ICU0_IN1 PPG0_TOUT2 EINT1 P4_01 0 0 TxDOUT3- B 17 146 S AN37 0 0 PWM2M2 OCU0_OTD0 ICU0_IN0 PPG0_TOUT0 EINT0 P4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2+ B 18 145 S AN36 0 0 PWM2P2 OCU11_OTD1ICU11_IN1 PPG11_TOUT2 EINT15 P3_31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2- B - 14 19 149 144 S S AN40 AN35 SCK2 0 0 0 PWM2P3 PWM1M2 OCU1_OTD1 ICU1_IN1 OCU11_OTD0ICU11_IN0 PPG1_TOUT2 EINT3 PPG11_TOUT0 EINT14 P4_03 P3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK+ B 20 143 S AN34 0 0 PWM1P2 OCU10_OTD1ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 142 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 141 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B 23 140 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0ICU10_IN0 0 0 PPG10_TOUT0 EINT12 0 0 P3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B 24 139 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 138 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 P3_20 0 PPG6_TOUT0 EINT4 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - E - - E E E E E - - F F F - - - G H I J J I I I I I J J I I I I I L - M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 0 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA24 CAP0_DATA25 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGO0 SGA0 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU6_OTD0 ZIN9 OCU7_OTD1 0 0 OCU5_OTD1 BIN9 OCU7_OTD0 0 OCU10_OTD1 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU9_OTD1 BIN8 OCU4_OTD1 0 OCU10_OTD0 AIN8 OCU4_OTD0 0 OCU9_OTD0 SIN1 OCU4_OTD1 0 0 SCK1 0 0 0 SOT1 0 0 0 OCU11_OTD0 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 OCU10_OTD0 OCU10_OTD1 OCU11_OTD0 0 0 0 0 ICU11_IN0 0 0 ICU9_IN0 ICU10_IN0 ICU9_IN1 ICU8_IN1 ICU10_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 ICU10_IN0 ICU10_IN1 ICU11_IN0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG0/1/2/3/4/5_TIN1 0 0 FRT8/9/10/11_TEXT 0 0 0 0 0 0 0 0 0 0 0 PPG11_TOUT0 0 0 PPG9_TOUT0 PPG10_TOUT0 PPG9_TOUT2 PPG8_TOUT2 PPG10_TOUT2 0 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 PPG10_TOUT0 PPG10_TOUT2 PPG11_TOUT0 0 0 0 0 EINT0 0 0 EINT15 P1_08 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT8 EINT9 EINT6 0 0 P1_00 P1_02 0 0 P0_26 P0_27 P0_28 0 0 0 0 P2_22 P2_24 P2_25 EINT15 P2_31 EINT5 P1_01 EINT14 P2_30 EINT4 P0_31 EINT13 P2_29 EINT3 0 EINT12 P2_28 EINT2 0 EINT11 P2_27 EINT1 P0_30 EINT10 P2_26 EINT0 0 EINT10 P1_03 EINT9 0 EINT11 P1_04 0 0 EINT13 P1_06 0 P1_09 EINT14 P1_07 EINT5 0 EINT12 P1_05 0 0 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 0 0 0 0 M_CK_0 0 0 M_DQ3_0 M_DQ2_0 M_DQ1_0 M_DQ0_0 M_CS#1_0 0 M_RWDS_0 0 0 M_CS#2_0 M_DQ4_0 M_DQ5_0 M_DQ6_0 M_DQ7_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 G_CS#1_1 0 0 0 G_CS#2_1 G_DQ4_1 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G_RWDS_1 0 INDICATOR0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 73 E G_SSEL1 0 0 0 72 M_SSEL0 0 0 E G_SDATA1_1 0 71 G_SDATA1_2 0 M_SDATA0_1 0 M_SDATA0_2 0 0 E 0 E 0 70 0 0 69 0 0 G_SDATA1_0 0 M_SDATA0_0 0 E 0 68 0 0 0 0 0 0 0 DSP0_CTRL1 0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 0 P5_22 0 P0_17 0 EINT4 VCC3 EINT2 VSS PPG10_TOUT0 VSS PPG9_TOUT0 VCC12 0 M_SCLK0 0 - ICU10_IN0 - ICU9_IN0 E OCU10_OTD0 - OCU9_OTD0 - 0 67 0 66 0 65 TIN35 I2S1_SCK 0 64 TXER 63 0 DSP0_CLK 0 0 DSP0_CTRL2 0 G_DQ7_2 CAP0_DATA34 G_DQ6_2 CAP0_CLK G_DQ5_2 DSP0_CTRL2 0 0 G_DQ4_2 DSP0_DATA_D11- P0_16 0 DSP0_CTRL0 EINT1 0 DSP0_DATA1_11 PPG8_TOUT2 0 C 0 0 D ICU8_IN1 0 62 OCU8_OTD1 P0_15 61 0 EINT0 TOT35 I2S1_WS EINT15 P0_14 COL EINT14 P0_13 0 EINT13 P0_12 CAP0_DATA33 0 DSP0_DATA_D11+ PPG8_TOUT0 DSP0_DATA0_11 PPG7_TOUT2 D PPG7_TOUT0 60 0 PPG6_TOUT2 0 0 0 0 0 CAP0_DATA35 RXDV TIN34 I2S1_SD 0 CAP0_DATA32 0 CAP0_DATA23 0 CAP0_DATA22 0 0 CAP0_DATA21 ICU8_IN0 DSP0_DATA_D10- ICU7_IN1 DSP0_DATA_D10+ ICU7_IN0 DSP0_DATA_D9- ICU6_IN1 0 DSP0_DATA_D9+ 0 DSP0_DATA1_10 OCU8_OTD0 DSP0_DATA0_10 OCU7_OTD1 DSP0_DATA1_9 OCU7_OTD0 VCC3 DSP0_DATA0_9 OCU6_OTD1 D 0 D 0 D RXCLK TIN33 I2S0_SCK 0 D TXCLK TOT33 I2S0_WS - 0 59 0 58 0 57 0 56 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 55 Page 24 of 225 Document Number: 002-05682 Rev. *Q PWM1P1 PWM2M0 0 0 Condition on PCB Set to ground Package Pin Number 12 to 27 AP1(AH1) BN0(BL0) 0 0 Y 0 0 0 0 0 0 0 Y 0 0 0 AN30 AN29 0 0 Y G_CS#1_2 G_RWDS_2 0 S S 0 0 Y 0 0 0 137 0 0 VCC53 4 - ○ 136 0 0 DSP1_CLK 0 0 TOP VIEW TEQFP-216 0 0 DSP1_CTRL2 150 VSS_LVDS_Tx DSP1_CTRL1 13 VCC3_LVDS_Tx DSP1_CTRL0 - 0 0 AVCC3_LVDS_PLL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL8 0 0 DSP0_CTRL9 0 0 0 0 0 0 SIN11 DSP0_CTRL11 0 0 0 0 0 0 SOT11 0 0 0 SCK11 DSP0_CTRL10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA1 0 0 0 SGO1 0 0 0 0 0 0 0 OCU0_OTD1 0 0 0 OCU1_OTD0 0 0 0 OCU1_OTD1 0 0 0 OCU2_OTD0 0 0 0 0 0 0 0 ICU0_IN1 DVCC DVSS 0 ICU1_IN0 - - 0 ICU1_IN1 152 151 0 ICU2_IN0 11 12 0 0 - - 0 0 VCC12 AVSS_LVDS_PLL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG0_TOUT2 0 0 0 PPG1_TOUT0 0 0 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 0 0 0 0 0 0 0 EINT9 0 0 0 EINT10 0 0 0 EINT11 0 0 0 EINT12 0 0 0 0 0 0 0 COM3 0 0 0 COM2 A VSS 0 COM1 C_R AVSS 0 0 COM0 0 0 0 0 0 0 0 0 0 0 0 P4_25 0 0 0 0 0 P4_26 0 0 0 0 0 P4_27 0 0 0 0 0 P4_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 2 0 0 0 0 0 0 1 - A 0 0 0 0 0 Any function at the following pins is not supported. − 0 0 0 - AVSS DAC_R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC_L A 7 156 S AN45 SIN3 0 PWM2M4 OCU4_OTD0 ICU4_IN0 PPG4_TOUT0 EINT8 P4_08 MFS2_CS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_L A 8 155 S AN44 SCK3 0 PWM2P4 OCU3_OTD1 ICU3_IN1 PPG3_TOUT2 EINT7 P4_07 MFS2_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 9 154 S AN43 SOT3 0 PWM1M4 OCU3_OTD0 ICU3_IN0 PPG3_TOUT0 EINT6 P4_06 MFS0_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 10 153 S AN42 0 0 PWM1P4 OCU2_OTD1 ICU2_IN1 PPG2_TOUT2 EINT5 P4_05 0 Notes: − The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-4: TEQFP-216 (S6J326CLxx, S6J32LELxx) TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 - - - X X W W W W W W W W V V 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 163 RX6 0 VCC53 Y 185 - TX6 0 Y 186 VCC5 0 0 DSP1_DATA1_11 Y 187 0 0 0 0 DSP1_DATA0_11 Y 188 0 0 0 ICU0_IN0 OCU0_OTD0 WOT TOT18 SCK9 0 0 DSP1_DATA1_10 Y 189 0 0 0 SIN9 0 0 DSP1_DATA0_10 Y 190 0 0 0 0 0 0 0 DSP1_DATA1_9 Y 191 0 0 EINT3 0 TIN18 0 AP0(AH0) 0 DSP1_DATA0_9 - Y 192 0 0 0 EINT7 PPG11_TOUT2 0 ICU2_IN0 OCU2_OTD0 SGO0 TOT32 SOT10 0 TOT19 0 0 ICU2_IN1 OCU2_OTD1 SGA0 TIN32 SCK10 0 TIN19 0 0 ICU3_IN0 OCU3_OTD0 SGA1 TOT33 SIN10 EINT8 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN 0 0 0 ICU4_IN0 OCU4_OTD0 SGA2 TOT34 SCK11 0 ICU0_IN1 OCU0_OTD1 0 0 AN0(AL0) 0 DSP1_DATA1_8 - 193 0 0 EINT9 PPG0_TOUT2 0 0 FRT4/5/6/7_TEXT ICU3_IN1 OCU3_OTD1 SGO1 TIN33 SOT11 0 ICU1_IN0 OCU1_OTD0 0 0 BP0(BH0) VCC12 0 DSP1_DATA0_8 - 164 EINT10 PPG1_TOUT0 0 0 0 0 ICU4_IN1 OCU4_OTD1 SGO2 TIN34 SIN11 0 ICU1_IN1 OCU1_OTD1 0 0 0 BN0(BL0) VCC12 - - 0 EINT11 PPG1_TOUT2 0 ICU0_IN1 OCU0_OTD1 0 0 AP1(AH1) 0 VSS VSS V3 EINT12 PPG2_TOUT0 0 ICU0_IN0 OCU0_OTD0 0 0 0 AN1(AL1) 0 VCC53 0 0 V2 EINT13 PPG2_TOUT2 0 0 0 0 BN1(BL1) BP1(BH1) 0 0 0 0 V1 EINT14 PPG3_TOUT0 0 0 0 SOT8 0 0 0 0 0 P2_19 V0 EINT0 PPG4_TOUT0 EINT15 PPG3_TOUT2 0 0 0 0 SIN8 0 SCK8 0 194 0 0 0 P3_07 SEG31 EINT1 PPG4_TOUT2 0 0 0 0 0 195 0 0 0 P3_08 SEG30 EINT1 PPG0_TOUT2 0 0 0 0 Y 0 0 0 P3_09 SEG29 EINT0 PPG0_TOUT0 0 0 0 0 ICU3_IN0 OCU3_OTD0 SGA3 0 0 0 ICU3_IN1 OCU3_OTD1 SGO3 0 ICU2_IN1 OCU2_OTD1 0 0 0 Y 0 0 0 0 P3_10 SEG28 0 0 ICU4_IN0 OCU4_OTD0 0 0 0 DSP1_DATA1_7 165 0 0 P3_11 SEG27 0 0 ICU4_IN1 OCU4_OTD1 0 0 0 DSP1_DATA0_7 166 0 MFS8_CS0 0 P3_12 SEG26 0 0 ICU5_IN0 OCU5_OTD0 0 0 0 ICU6_IN0 OCU6_OTD0 0 0 V 0 MFS9_CS0 0 P3_13 SEG25 0 0 0 0 0 U 0 MFS9_CS1 0 P3_14 SEG24 EINT13 PPG2_TOUT2 0 0 0 0 0 MFS8_CS3 0 P3_15 0 EINT14 PPG3_TOUT0 0 0 SOT9 AN15 0 MFS8_CS1 0 P3_16 0 EINT15 PPG3_TOUT2 0 0 0 196 0 0 MFS8_CS2 0 P3_17 0 EINT0 PPG4_TOUT0 0 0 0 197 0 0 0 0 P2_17 0 EINT1 PPG4_TOUT2 0 0 0 0 Y 198 0 0 0 0 0 0 0 Y 0 0 0 SEG23 0 0 0 ICU6_IN1 OCU6_OTD1 0 DSP1_DATA1_6 Y 0 0 0 0 SEG22 0 0 0 ICU7_IN0 OCU7_OTD0 0 DSP1_DATA0_6 SOT9 0 0 0 0 SEG21 EINT5 PPG6_TOUT2 0 0 DSP1_DATA1_5 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG20 EINT6 PPG7_TOUT0 0 SCK9 0 0 0 0 0 P4_30 SEG15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_04 0 0 P5_03 0 0 P5_02 0 0 P5_01 0 0 P5_00 0 0 0 0 SEG16 SEG17 SEG18 SEG19 0 0 EINT4 PPG6_TOUT0 EINT3 PPG5_TOUT2 EINT2 PPG5_TOUT0 0 ICU5_IN1 OCU5_OTD1 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 TOT17 0 0 0 P4_31 SEG14 0 ICU7_IN1 OCU7_OTD1 0 SIN9 0 0 0 0 P5_05 EINT7 PPG7_TOUT2 0 TIN48 ICU1_IN1 0 0 0 P5_06 SEG13 0 P3_26 0 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 136 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-216 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 - - E E E E E - - F F F - - - G H I J J I I I I I J J I I I I I L - VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 0 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGO0 SGA0 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 TOT1 SGA0 TOT2 SGA1 TOT3 SGO1 TIN16 SGA2 TOT16 SGO2 TIN17 0 0 0 TOT0 SGO0 0 0 TIN49 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU6_OTD1 ICU6_IN1 0 OCU8_OTD0 ICU8_IN0 0 OCU7_OTD1 ICU7_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU8_OTD0 ICU8_IN0 0 OCU8_OTD1 ICU8_IN1 0 OCU9_OTD0 ICU9_IN0 0 OCU9_OTD1 ICU9_IN1 0 OCU10_OTD0 ICU10_IN0 0 OCU10_OTD1 ICU10_IN1 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 EINT13 P2_29 0 PPG7_TOUT0 EINT14 P2_30 0 PPG8_TOUT0 EINT0 P3_00 0 PPG8_TOUT2 EINT1 P3_01 0 PPG9_TOUT0 EINT2 P3_02 0 PPG9_TOUT2 EINT3 P3_03 0 PPG10_TOUT0 EINT4 P3_04 0 PPG10_TOUT2 EINT5 P3_05 0 PPG11_TOUT0 EINT6 P3_06 0 0 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 PPG5_TOUT2 EINT11 P2_27 INDICATOR0_0 0 0 0 PPG5_TOUT0 EINT10 P2_26 0 0 0 0 PPG4_TOUT2 EINT9 P2_25 0 0 0 0 PPG4_TOUT0 EINT8 P2_24 0 0 0 0 0 PPG3_TOUT0 EINT6 P2_22 0 0 0 0 0 EINT2 P0_27 0 0 0 EINT1 P0_26 0 0 0 PPG4_TOUT2 EINT3 P0_28 0 0 0 0 PPG7_TOUT2 EINT9 P1_02 M_DQ7_0 0 0 PPG8_TOUT0 EINT10 P1_03 M_DQ6_0 0 0 0 PPG6_TOUT2 EINT7 P1_00 M_DQ5_0 0 0 0 PPG7_TOUT0 EINT8 P1_01 M_DQ4_0 0 0 PPG6_TOUT0 EINT6 P0_31 M_CS#2_0 0 0 PPG5_TOUT2 EINT5 P0_30 M_RWDS_0 0 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 0 PPG8_TOUT2 EINT11 P1_04 M_DQ0_0 0 0 PPG9_TOUT2 EINT13 P1_06 M_DQ1_0 0 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 0 0 PPG9_TOUT0 EINT12 P1_05 M_DQ3_0 0 0 OCU6_OTD0 ICU6_IN0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 EINT12 P2_28 0 0 0 OCU5_OTD1 ICU5_IN1 0 0 0 OCU3_OTD0 ICU3_IN0 0 0 0 0 ZIN9 OCU7_OTD1 ICU7_IN1 FRT8/9/10/11_TEXT PPG7_TOUT2 EINT15 P2_31 0 0 OCU7_OTD0 ICU7_IN0 0 0 0 OCU6_OTD0 ICU6_IN0 0 0 0 0 BIN9 OCU7_OTD0 ICU7_IN0 0 0 0 0 AIN9 OCU6_OTD1 ICU6_IN1 0 0 0 ZIN8 OCU5_OTD0 ICU5_IN0 0 0 0 OCU5_OTD1 ICU5_IN1 0 BIN8 OCU4_OTD1 ICU4_IN1 0 0 OCU10_OTD1 ICU10_IN1 0 AIN8 OCU4_OTD0 ICU4_IN0 0 0 OCU8_OTD1 ICU8_IN1 0 SIN1 OCU4_OTD1 ICU4_IN1 0 0 OCU9_OTD1 ICU9_IN1 0 SCK1 0 0 OCU10_OTD0 ICU10_IN0 0 SOT1 0 0 OCU9_OTD0 ICU9_IN0 0 0 PPG11_TOUT0 EINT0 P1_09 M_CK_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 75 0 0 0 0 0 0 0 G_SCLK0 0 0 0 0 0 0 0 0 0 0 0 VSS 0 0 0 0 0 E 0 0 0 0 0 0 - G_SDATA1_3 0 0 0 0 74 M_SDATA0_3 0 0 0 0 0 73 E G_SSEL1 0 0 72 M_SSEL0 0 0 E G_SDATA1_1 0 71 G_SDATA1_2 0 M_SDATA0_1 0 0 OCU11_OTD0 ICU11_IN0 0 M_SDATA0_2 0 0 E 0 0 E 0 0 70 0 0 69 0 0 G_SDATA1_0 0 M_SDATA0_0 0 E 0 68 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 0 VSS 0 VSS 0 VCC12 M_SCLK0 0 - 0 - 0 E 0 DSP0_CTRL1 - 0 - PPG10_TOUT0 EINT4 P5_22 0 67 OCU10_OTD0 ICU10_IN0 0 66 0 65 0 64 0 63 TXER CAP0_DATA34 0 DSP0_CTRL0 0 0 DSP0_CTRL2 0 DSP0_CLK DSP0_CTRL0 PPG9_TOUT0 EINT2 P0_17 0 DSP0_CTRL2 C OCU9_OTD0 ICU9_IN0 0 0 62 TIN35 I2S1_SCK 0 G_DQ7_2 0 G_DQ6_2 DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK G_DQ5_2 D G_DQ4_2 61 PPG8_TOUT2 EINT1 P0_16 0 0 PPG8_TOUT0 EINT0 P0_15 0 0 PPG7_TOUT2 EINT15 P0_14 0 TOT35 I2S1_WS PPG7_TOUT0 EINT14 P0_13 0 COL PPG6_TOUT2 EINT13 P0_12 0 DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 DSP0_DATA1_9 DSP0_DATA_D9- CAP0_DATA22 0 OCU8_OTD1 ICU8_IN1 0 VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 OCU8_OTD0 ICU8_IN0 0 D OCU7_OTD1 ICU7_IN1 0 D OCU7_OTD0 ICU7_IN0 0 D OCU6_OTD1 ICU6_IN1 0 D 0 D 0 - 0 60 0 59 RXCLK TIN33 I2S0_SCK 0 58 0 57 0 56 0 55 Page 25 of 225 Document Number: 002-05682 Rev. *Q 0 0 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 AIN8 0 CAP0_DATA11 0 0 ICU8_IN0 OCU8_OTD0 PPG9_TOUT0 EINT10 OCU8_OTD1 ICU8_IN1 0 0 ICU8_IN1 OCU8_OTD1 OCU9_OTD0 ICU9_IN0 PWM1P1 0 EINT8 PPG8_TOUT0 PWM1M1 AP1(AH1) 0 EINT9 PPG8_TOUT2 AN1(AL1) 0 0 SEG12 0 AN30 DSP0_DATA1_11 SEG11 AN31 S 0 0 0 P5_08 S 137 0 0 0 P5_09 138 26 DSP0_DATA0_11 0 25 - 0 0 B VSS_LVDS_Tx 0 199 TxDOUT0- 0 0 Y 0 0 DSP0_DATA1_10 0 DSP1_DATA0_5 0 0 0 0 0 0 0 0 SOT10 0 0 0 0 ICU9_IN0 OCU9_OTD0 BIN8 0 0 0 EINT10 PPG9_TOUT0 0 0 0 SEG10 0 0 0 MFS8_CS0 0 P5_10 0 0 0 MFS10_SDA P3_27 0 200 PPG9_TOUT2 EINT11 0 Y OCU9_OTD1 ICU9_IN1 0 0 DSP1_DATA1_4 PWM2P1 0 0 BP1(BH1) 0 0 SCK10 0 0 ZIN8 AN32 0 0 ICU9_IN1 OCU9_OTD1 S 0 EINT11 PPG9_TOUT2 139 0 SEG9 24 0 MFS9_CS0 0 P5_11 B 0 MFS10_SCL TxDOUT0+ 0 201 0 0 202 0 0 - 0 0 Y 0 0 VCC53 0 0 0 DSP1_DATA0_4 0 0 0 0 0 0 0 P3_28 0 0 PPG10_TOUT0 EINT12 0 0 OCU10_OTD0ICU10_IN0 0 0 SIN10 PWM2M1 0 0 BN1(BL1) 0 0 0 0 AIN9 AN33 0 0 S 0 0 140 0 0 ICU10_IN0 OCU10_OTD0 23 0 0 B 0 0 TxDOUT1- 0 0 0 0 EINT12 PPG10_TOUT0 0 0 0 0 0 SEG8 0 0 0 0 0 0 0 0 0 0 MFS9_CS1 0 P5_12 0 0 0 0 0 0 0 0 0 0 0 203 0 0 0 - 0 0 0 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 DVSS 0 0 DVCC 0 0 141 0 0 142 22 0 0 21 B 0 0 B TxDOUT1+ 0 0 TxCLK- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 204 P3_29 0 205 PPG10_TOUT2 EINT13 0 206 OCU10_OTD1ICU10_IN1 0 207 PWM1P2 0 208 0 0 Y 0 0 Y AN34 0 Y S 0 Y 143 0 Y 20 0 0 DSP1_DATA1_3 B 0 0 DSP1_DATA0_3 TxCLK+ 0 DSP1_CLK DSP1_DATA0_2 0 0 0 DSP0_CTRL0 0 0 0 0 DSP0_CTRL4 DSP1_CTRL0 DSP1_DATA1_1 0 0 0 0 0 0 0 0 0 0 SOT11 DSP0_CTRL1 0 P3_30 0 0 0 0 SCK11 DSP0_CTRL2 DSP1_CTRL2 DSP1_DATA1_2 0 P3_31 PPG11_TOUT0 EINT14 0 0 0 0 0 SIN11 DSP0_CTRL3 0 P4_00 PPG11_TOUT2 EINT15 OCU11_OTD0ICU11_IN0 0 0 0 0 0 0 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 PWM1M2 0 0 0 0 0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 0 0 0 0 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 0 0 0 0 0 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 AN35 0 0 0 0 0 ZIN9 PWM1M3 0 0 AN36 S 0 0 0 0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 0 0 AN37 S 144 0 0 0 0 0 ICU11_IN0 OCU11_OTD0 SOT2 AN38 S 145 19 0 0 0 0 ICU11_IN1 OCU11_OTD1 AN39 S 146 18 B 0 0 0 ICU0_IN0 OCU0_OTD0 S 147 17 B TxDOUT20 0 ICU0_IN1 OCU0_OTD1 148 16 B TxDOUT2+ 0 0 0 EINT0 PPG0_TOUT0 15 B TxDOUT3- 0 0 0 0 0 0 EINT1 PPG0_TOUT2 - TxDOUT3+ 0 0 0 0 0 0 0 0 EINT13 PPG10_TOUT2 VSS_LVDS_Tx 0 0 0 0 0 0 0 0 EINT14 PPG11_TOUT0 0 0 0 0 0 0 0 0 EINT15 PPG11_TOUT2 0 0 0 0 0 0 SEG7 0 0 0 0 SEG6 0 0 0 SEG5 0 P4_03 0 0 SEG4 P4_04 PPG1_TOUT2 EINT3 0 0 SEG3 PPG2_TOUT0 EINT4 OCU1_OTD1 ICU1_IN1 0 0 0 0 P5_13 OCU2_OTD0 ICU2_IN0 PWM2P3 0 0 0 P5_17 PWM2M3 0 0 MFS8_CS3 0 P5_14 0 SCK2 0 MFS8_CS1 0 P5_15 SIN2 AN40 0 MFS8_CS2 0 P5_16 AN41 S 0 0 S 149 0 0 150 14 0 0 13 0 0 - VCC3_LVDS_Tx 0 0 0 AVCC3_LVDS_PLL 0 0 0 0 209 0 0 0 0 0 Y 0 0 0 0 SOT12 DSP0_CTRL5 DSP1_CTRL1 DSP1_DATA0_1 0 0 0 0 0 0 ICU1_IN0 OCU1_OTD0 0 0 EINT2 PPG1_TOUT0 0 0 SEG2 0 0 MFS12_SDA 0 P5_18 0 0 0 0 0 210 0 0 Y 0 0 0 DSP1_DATA1_0 DVSS 0 0 SCK12 DSP0_CTRL6 - 0 0 151 0 0 ICU1_IN1 OCU1_OTD1 12 0 EINT3 PPG1_TOUT2 0 0 SEG1 AVSS_LVDS_PLL 0 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 211 0 0 0 212 0 0 0 213 0 0 0 214 0 0 0 215 0 0 0 216 0 0 0 - 0 0 0 Y 0 0 0 Y DVCC 0 0 Y - 0 0 Y 152 0 0 Y 11 0 0 VCC53 0 0 DSP1_CLK VCC12 0 0 DSP1_CTRL2 0 0 0 DSP1_CTRL1 MFS0_CS0 P4_05 0 DSP1_CTRL0 P4_06 PPG2_TOUT2 EINT5 0 0 DSP1_DATA0_0 PPG3_TOUT0 EINT6 OCU2_OTD1 ICU2_IN1 0 0 OCU3_OTD0 ICU3_IN0 PWM1P4 0 0 PWM1M4 0 0 0 0 0 0 0 SOT3 AN42 0 0 AN43 S 0 0 S 153 VSS 0 0 DSP0_CTRL8 0 154 10 AVSS 0 0 0 SIN12 DSP0_CTRL7 9 0 0 0 0 0 0 0 0 SOT11 DSP0_CTRL9 MFS2_CS0 0 0 SCK11 DSP0_CTRL10 P4_07 0 0 SIN11 DSP0_CTRL11 PPG3_TOUT2 EINT7 0 0 OCU3_OTD1 ICU3_IN1 0 0 PWM2P4 0 0 0 0 0 SCK3 0 0 AN44 0 0 0 S A 0 0 ICU2_IN0 OCU2_OTD0 155 C_L 0 0 ICU0_IN1 OCU0_OTD1 0 8 0 0 0 ICU1_IN0 OCU1_OTD0 SGA1 0 MFS2_CS1 0 0 ICU1_IN1 OCU1_OTD1 SGO1 0 P4_08 0 0 ICU2_IN0 OCU2_OTD0 0 PPG4_TOUT0 EINT8 0 EINT4 PPG2_TOUT0 OCU4_OTD0 ICU4_IN0 0 EINT9 PPG0_TOUT2 PWM2M4 0 EINT10 PPG1_TOUT0 0 AVCC3_DAC EINT11 PPG1_TOUT2 SIN3 0 EINT12 PPG2_TOUT0 AN45 0 0 0 S 0 0 0 SEG0 0 156 A 0 0 0 0 COM3 MFS4_SDA 0 7 DAC_L 0 0 0 0 0 COM2 MFS4_SCL MFS0_CS3 P4_09 0 0 0 0 0 0 COM1 0 MFS0_CS1 P4_10 0 0 0 0 0 0 COM0 MFS0_CS2 P4_11 PPG4_TOUT2 EINT9 0 0 0 0 0 0 0 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 0 0 0 P5_20 0 0 PPG5_TOUT2 EINT11 OCU4_OTD1 ICU4_IN1 0 0 0 0 0 0 0 0 P4_25 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 PWM1P5 0 0 0 0 0 0 0 0 P4_26 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 P4_27 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 P4_28 0 0 PWM2M5 RX1 SOT4 AN46 0 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 S 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 157 6 0 0 0 0 0 0 0 0 0 AN49 S 158 5 0 0 0 0 0 0 0 DVSS S 159 4 0 0 0 0 0 DVCC 160 3 0