Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
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Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
S70FL01GS
1 Gbit (128 Mbyte) 3.0V SPI Flash
Features
CMOS 3.0V Core
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
– AutoBoot – power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock
systems
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles, minimum
Data Retention
– 20 Year Data Retention, minimum
Security Features
One Time Program (OTP) array of 2048 bytes
Block Protection
– Status Register bits to control protection against program
or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress® 65 nm MirrorBit® Technology with Eclipse
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
Temperature Range / Grade:
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
– 16-lead SOIC (300 mils)
– BGA-24, 8 6 mm
– 5 5 ball (ZSA024) footprint
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, refer to the discrete die datasheet provided in the Affected Documents/Related Documents table.
Affected Documents/Related Documents
Document Title
Publication Number
S25FL512S 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Datasheet
001-98284
Cypress Semiconductor Corporation
Document Number: 001-98295 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 03, 2018
S70FL01GS
Contents
1.
Block Diagram.............................................................. 3
2.
Connection Diagrams.................................................. 4
3.
Input/Output Summary ................................................ 5
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Device Operations .......................................................
Programming .................................................................
Simultaneous Die Operation ..........................................
Sequential Reads...........................................................
Sector/Bulk Erase ..........................................................
Status Registers.............................................................
Configuration Register ...................................................
Bank Address Register ..................................................
Security and DDR Registers ..........................................
Block Protection .............................................................
5.
Read Identification (RDID)........................................... 7
6.
RESET# ......................................................................... 7
7.
Versatile I/O Power Supply (VIO)................................. 7
8.
DC Characteristics....................................................... 8
9.
AC Test Conditions...................................................... 9
Document Number: 001-98295 Rev. *N
6
6
6
6
6
6
6
6
6
6
10. SDR AC Characteristics ............................................. 10
10.1 DDR AC Characteristics ............................................... 11
10.2 Capacitance Characteristics ......................................... 11
11. Ordering Information .................................................. 12
11.1 Valid Combinations — Standard................................... 13
11.2 Valid Combinations — Automotive Grade /
AEC-Q100 .................................................................... 13
12.
12.1
12.2
12.3
Other Resources ......................................................... 14
Cypress Flash Memory Roadmap ................................ 14
Links to Software .......................................................... 14
Links to Application Notes............................................. 14
13. Physical Diagram ........................................................ 15
13.1 SOIC 16 Lead, 300-mil Body Width .............................. 15
13.2 24-Ball BGA 8 x 6 mm (ZSA024) .................................. 16
14. Revision History.......................................................... 17
Sales, Solutions, and Legal Information .......................... 19
Worldwide Sales and Design Support ........................... 19
Products ........................................................................ 19
PSoC® Solutions .......................................................... 19
Cypress Developer Community ..................................... 19
Technical Support ......................................................... 19
Page 2 of 19
S70FL01GS
1. Block Diagram
SI/IO0
WP#/IO2
S I/IO 0
WP#/IO2
S O /IO 1
HOLD#/IO3
H O LD #/IO 3
SCK
SCK
CS#1
CS#
FL512S
Flash
Memory
SO/IO1
VSS
VSS
VCC
VCC
S I/IO 0
WP#/IO2
S O /IO 1
H O LD #/IO 3
SCK
CS#2
FL512S
Flash
Memory
VSS
CS#
VCC
Document Number: 001-98295 Rev. *N
Page 3 of 19
S70FL01GS
2.
Connection Diagrams
Figure 1. 16-Pin Plastic Small Outline Package (SO)
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
RESET#
3
14
VIO/RFU
DNU
4
13
NC
DNU
5
12
DNU
CS2#
6
11
DNU
CS1#
7
10
VSS
SO/IO1
8
9
WP#/IO2
Figure 2. 24-Ball BGA, 5 x 5 Ball Footprint (ZSA024), Top View
1
2
3
4
5
DNU
CS2#
RESET#
RFU
DNU
SCK
VSS
VCC
RFU
DNU
CS1#
RFU
WP#/IO2
RFU
DNU
SO/IO1
DNU
DNU
A
B
C
D
SI/IO0 HOLD#/IO3 DNU
E
DNU
VIO/RFU
DNU
Note:
1. VIO is not supported in the S70FL01GS device and is RFU. Refer to Section 7. for more details.
Document Number: 001-98295 Rev. *N
Page 4 of 19
S70FL01GS
3.
Input/Output Summary
Table 2. Signal List
Signal Name
Type
Description
RESET#
Input
Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used.
SCK
Input
Serial Clock.
CS1#
Input
Chip Select. FL512S #1.
CS2#
Input
Chip Select. FL512S #2.
SI / IO0
I/O
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1
I/O
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
WP# / IO2
I/O
Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up
resistor and may be left unconnected in the host system if not used for Quad commands.
HOLD# / IO3
I/O
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The
signal has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad commands.
VCC
Supply
Core Power Supply.
VIO
Supply
Versatile I/O Power Supply. Note: VIO is not supported in the S70FL01GS device. Refer to
Section 7. for more details.
VSS
Supply
Ground.
Unused
Not Connected. No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for routing
space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC
must not have voltage levels higher than VCC.
Reserved
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use of the connector for a signal. It is recommended to not
use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for connection
to any host system signal. Any DNU signal related function will be inactive when the signal is at
VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system
or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not
connect any host system signal to this connection.
NC
RFU
DNU
Document Number: 001-98295 Rev. *N
Page 5 of 19
S70FL01GS
4. Device Operations
4.1
Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
4.2
Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
4.3
Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the user desires to
sequentially read across the two die, data must be read out of the first die via CS1# and then read out of the second die via CS2#.
4.4
Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via a single command is
not supported due to the nature of the dual die stack. A Bulk Erase command must be issued for each die.
4.5
Status Registers
Each Flash die of the dual die stack is managed by its own Status Registers. Reads and updates to the Status Registers must be
managed separately. It is recommended that Status Register control bit settings of each die are kept identical to maintain
consistency when switching between die.
4.6
Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the Configuration Register control bits
must be managed separately. It is recommended that Configuration Register control bit settings of each die are kept identical to
maintain consistency when switching between die.
4.7
Bank Address Register
It is recommended that the Bank Address Register bit settings of each die are kept identical to maintain consistency when switching
between die.
4.8
Security and DDR Registers
It is recommended that the bit settings for ASP Register, Password Register, PPB Lock Register, PPB Access Register, DYB
Access Register, and DDR Data Learning Register in each die are kept identical to maintain consistency when switching between
die.
4.9
Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and BPNV bits of each die must
be managed separately. By default, each die is configured to be protected starting at the top (highest address) of each array, but no
address range is protected. It is recommended that the Block Protection settings of each die are kept identical to maintain
consistency when switching between die. In addition, any update to the FREEZE bit must be managed separately for each die. If the
FREEZE bit is set to a logic 1, it cannot be cleared to a logic 0 until a power-on-reset is executed on each die that has the FREEZE
bit set to 1.
Document Number: 001-98295 Rev. *N
Page 6 of 19
S70FL01GS
5. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device
identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the FL01GS dual die stack will have identical
identification data as the FL512S die, with the exception of the CFI data at byte 27h, as shown in Table 3.
Table 3. Product Group CFI Device Geometry Definition
Byte
Data
Description
27h
1Bh
Device Size = 2N byte
6. RESET#
Note that the hardware RESET# input (pin 3 on the 16-pin SO package and ball A4 on the 5x5 BGA package) is bonded out and
active for the S70FL01GS device. For applications that do NOT require use of the RESET# pin, it is recommended to not use
RESET# for PCB routing channels that would cause the RESET# signal to be asserted Low (VIL). Doing so will cause the device to
reset to standby state. The RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not
used.
7. Versatile I/O Power Supply (VIO)
Note that the Versatile I/O (VIO) power supply (pin 14 on the 16-pin SO package and ball E4 on the 5x5 BGA package) is not
supported, and pin 14 and ball E4 are RFU (Reserved for Future Use) in the standard configuration of the S70FL01GS device.
Contact your local sales office to confirm availability with the VIO feature enabled.
Document Number: 001-98295 Rev. *N
Page 7 of 19
S70FL01GS
8.
DC Characteristics
This section summarizes the DC Characteristics of the device.
Table 4. DC Characteristics
Symbol
Parameter
Test Conditions
Min
Typ (1)
Max
Unit
VIL
Input Low Voltage
–
-0.5
–
0.2 x VCC
V
VIH
Input High Voltage
–
0.7 x VCC
–
VCC + 0.4
V
VOL
Output Low Voltage
IOL = 1.6 mA, VCC = VCC min
–
–
0.15 x VCC
V
VOH
Output High Voltage
IOH = –0.1 mA
0.85 x VCC
–
ILI
Input Leakage Current
VCC = VCC Max, VIN = VIH or VIL
–
–
±4
µA
ILO
Output Leakage Current VCC = VCC Max, VIN = VIH or VIL
–
–
±4
µA
–
–
18
36
50
61
75
90
mA
Serial SDR @ 50 MHz
Serial SDR @ 133 MHz
Quad SDR @ 80 MHz
Quad SDR @ 104 MHz
Quad DDR @ 66 MHz
Quad DDR @ 80 MHz
Outputs unconnected during read data
return (2)
V
ICC1
Active Power Supply
Current (READ)
ICC2
Active Power Supply
CS# = VCC
Current (Page Program)
–
–
100
mA
ICC3
Active Power Supply
Current (WRR)
CS# = VCC
–
–
100
mA
ICC4
Active Power Supply
Current (SE)
CS# = VCC
–
–
100
mA
ICC5
Active Power Supply
Current (BE) (3)
CS# = VCC
–
–
200
mA
Standby Current
RESET#, CS# = VCC; SI, SCK = VCC or
VSS, Industrial Temp
–
140
200
µA
ISB (Industrial Plus) Standby Current
RESET#, CS# = VCC; SI, SCK = VCC or
VSS, Industrial Plus Temp
–
140
600
µA
ISB (Industrial)
Notes:
1. Typical values are at TAI = 25°C and VCC = 3V.
2. Output switching current is not included.
3. Bulk Erase current is for both die erasing simultaneously.
Document Number: 001-98295 Rev. *N
Page 8 of 19
S70FL01GS
9. AC Test Conditions
Figure 3. Input, Output, and Timing Reference Levels
Input Levels
Output Levels
VCC + 0.4V
0.7 x VCC
0.85 x VCC
Timing Reference Level
0.5 x VCC
0.2 x VCC
0.15 x VCC
- 0.5V
Figure 4. Test Setup
Device
Under
Test
CL
Table 5. AC Measurement Conditions
Symbol
CL
Parameter
Min
Load Capacitance
Input Rise and Fall Times
Max
30
15 (4)
–
Unit
pF
2.4
ns
Input Pulse Voltage
0.2 x VCC to 0.8 VCC
V
Input Timing Ref Voltage
0.5 VCC
V
Output Timing Ref Voltage
0.5 VCC
V
Notes:
1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).
4. DDR Operation.
Document Number: 001-98295 Rev. *N
Page 9 of 19
S70FL01GS
10. SDR AC Characteristics
Table 6. SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V)
Symbol
Min
Typ
Max
Unit
FSCK, R
SCK Clock Frequency for READ and 4READ instructions
DC
–
50
MHz
FSCK, C
SCK Clock Frequency for single commands (4)
DC
–
133
MHz
FSCK, C
SCK Clock Frequency for the following dual and quad commands:
DOR, 4DOR, QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR
DC
–
104
MHz
SCK Clock Frequency for the QPP, 4QPP commands
DC
–
80
MHz
1/ FSCK
–
FSCK, QPP
PSCK
Parameter
SCK Clock Period
tWH, tCH
Clock High Time (5)
45% PSCK
–
–
ns
tWL, tCL
Clock Low Time (5)
45% PSCK
–
–
ns
tCRT, tCLCH
Clock Rise Time (slew rate)
0.1
–
–
V/ns
tCFT, tCHCL
Clock Fall Time (slew rate)
0.1
–
–
V/ns
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50
–
–
ns
CS# Active Setup Time (relative to SCK)
3
–
–
ns
tCS (7)
tCSS
tCSH
CS# Active Hold Time (relative to SCK)
3
–
–
ns
tSU
Data in Setup Time
1.5
–
3000 (6)
ns
tHD
Data in Hold Time
2
–
–
ns
Clock Low to Output Valid
–
–
8.0 (2)
7.65 (3)
6.5 (4)
ns
tV
tHO
Output Hold Time
2
–
–
ns
tDIS
Output Disable Time
0
–
8
ns
tWPS
WP# Setup Time
20 (1)
–
–
ns
tWPH
WP# Hold Time
100 (1)
–
–
ns
tHLCH
HOLD# Active Setup Time (relative to SCK)
3
–
–
ns
tCHHH
HOLD# Active Hold Time (relative to SCK)
3
–
–
ns
tHHCH
HOLD# Non-Active Setup Time (relative to SCK)
3
–
–
ns
tCHHL
HOLD# Non-Active Hold Time (relative to SCK)
3
–
–
ns
tHZ
HOLD# Enable to Output Invalid
–
–
8
ns
tLZ
HOLD# Disable to Output Valid
–
–
8
ns
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Full VCC range (2.7 - 3.6V) and CL = 30 pF.
3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF.
4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF.
5. ±10% duty cycle is supported for frequencies
50 MHz.
6. Maximum value only applies during Program/Erase Suspend/Resume commands.
7. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the other for operations and data
to be valid.
Document Number: 001-98295 Rev. *N
Page 10 of 19
S70FL01GS
10.1
DDR AC Characteristics
Table 7. DDR AC Characteristics 66 MHz and 80 MHz Operation
Symbol
Parameter
FSCK, R
66 MHz
80 MHz
Unit
Min
Typ
Max
Min
Typ
Max
SCK Clock Frequency for DDR
READ instruction
DC
–
66
DC
–
80
MHz
PSCK, R
SCK Clock Period for DDR
READ instruction
15
–
12.5
–
ns
tWH, tCH
Clock High Time
45% PSCK
–
–
45% PSCK
–
–
ns
Clock Low Time
tWL, tCL
45% PSCK
–
–
45% PSCK
–
–
ns
tCS
CS# High Time (Read
Instructions)
10
–
–
10
–
–
ns
tCSS
CS# Active Setup Time (relative
to SCK)
3
–
–
3
–
–
ns
tCSH
CS# Active Hold Time (relative
to SCK)
3
–
–
3
–
–
ns
tSU
IO in Setup Time
2
–
3000 (2)
1.5
–
3000 (2)
ns
tHD
IO in Hold Time
2
–
1.5
–
–
ns
tV
0
–
6.5 (1)
–
6.5 (1)
ns
1.5
–
–
1.5
–
–
ns
Output Disable Time
–
–
8
–
8
ns
Clock to Output Low
Impedance
0
–
8
0
–
8
ns
First IO to last IO data valid
time
–
–
600
–
–
600
ps
Clock Low to Output Valid
tHO
Output Hold Time
tDIS
tLZ
tIO_skew
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
10.2
Capacitance Characteristics
Table 8. Capacitance
CIN
COUT
Parameter
Test Conditions
Min
Max
Unit
Input Capacitance (applies to SCK, CS#1, CS#2, RESET#)
1 MHz
–
16
pF
Output Capacitance (applies to All I/O)
1 MHz
–
16
pF
Note:
1. For more information on capacitance, please consult the IBIS models.
Document Number: 001-98295 Rev. *N
Page 11 of 19
S70FL01GS
11. Ordering Information
The ordering part number is formed by a valid combination of the following:
S70FL
01G
S
AG
M
F
I
0
1
1
Packing Type (Note 1)
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Sector Type)
1 = Uniform 256-kB sectors
Model Number
(Latency Type, Package Details, RESET# support)
0 = EHPLC, SO footprint
C = EHPLC, 5 x 5 ball BGA footprint with RESET#
Temperature Range / Grade
I = Industrial (-40°C to + 85°C)
V = Industrial Plus (-40°C to +105°C)
A = Automotive, AEC-Q100 Grade 3 (-40°C to +85°C)
B = Automotive, AEC-Q100 Grade 2 (-40°C to +105°C)
M = Automotive, AEC-Q100 Grade 1(-40°C to +125°C)
Package Materials
F = Lead (Pb)-free
H = Low-Halogen, Lead (Pb)-free
Package Type
B = 24-ball BGA 8 x 6 mm package, 1.00 mm pitch
M = 16-pin SO package
Speed
AG = 133 MHz
DP = 66 MHz DDR
DS = 80 MHz DDR
Device Technology
S = 65 nm MirrorBit Process Technology
Density
01G = 1 Gbit
Device Family
S70FL
Cypress Stacked Memory 3.0V-Only, Serial Peripheral Interface (SPI) Flash Memory
Notes:
1. EHPLC = Enhanced High Performance Latency Code table.
2. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer.
Document Number: 001-98295 Rev. *N
Page 12 of 19
S70FL01GS
11.1
Valid Combinations — Standard
Table 9 lists the valid combinations configurations planned to be supported in volume for this device.
Table 9. S70FL01GS Valid Combinations — Standard
S70FL01GS Valid Combinations
Base Ordering
Part Number
Speed
Option
Package and
Temperature
Model
Number
Packing Type
Package Marking (1)
MFI, MFV
01
0, 1, 3
FL01GS + D + (temp) + F + (Model Number)
AG
DP
S70FL01GS
FL01GS + A + (temp) + F + (Model Number)
DS
FL01GS + S + (temp) + F + (Model Number)
AG
FL01GS + A + (temp) + H + (Model Number)
DP
BHI, BHV
C1
0, 3
DS
FL01GS + D + (temp) + H + (Model Number)
FL01GS + S + (temp) + H + (Model Number)
Note:
1. Package Marking omits the leading “S70” and package type.
11.2
Valid Combinations — Automotive Grade / AEC-Q100
Table 10 lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table
will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific
combinations and to check on newly released combinations.
Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in
combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with
ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949
compliance.
Table 10. S70FL01GS Valid Combinations — Automotive Grade / AEC-Q100
S70FL01GS Valid Combinations
Base Ordering
Part Number
S70FL01GS
Speed
Option
Package and
Temperature
Model
Number
Packing Type
AG
MFA, MFB,
MFM
01
0, 1, 3
DS
AG
DS
BHA, BHB,
BHM
C1
0, 3
Package Marking (1)
FL01GS + A + (temp) + F + (Model Number)
FL01GS + S + (temp) + F + (Model Number)
FL01GS + A + (temp) + H + (Model Number)
FL01GS + S + (temp) + H + (Model Number)
Note:
1. Package Marking omits the leading “S70” and package type.
Document Number: 001-98295 Rev. *N
Page 13 of 19
S70FL01GS
12. Other Resources
12.1
Cypress Flash Memory Roadmap
www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap
12.2
Links to Software
www.cypress.com/software-and-drivers-cypress-flash-memory
12.3
Links to Application Notes
www.cypress.com/appnotes
Document Number: 001-98295 Rev. *N
Page 14 of 19
S70FL01GS
13. Physical Diagram
13.1
SOIC 16 Lead, 300-mil Body Width
0.20 C A-B
0.10 C D
2X
0.33 C
0.25 M
C A-B D
0.10 C
0.10 C
DIMENSIONS
SYMBOL
MIN.
NOM.
NOTES:
MAX.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
A
2.35
-
2.65
A1
0.10
-
0.30
A2
2.05
-
2.55
b
0.31
-
b1
c
0.27
-
0.48
0.20
-
0.33
c1
0.20
-
0.30
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
-
L1
1.40 REF
L2
0.25 BSC
0.51
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
1.27
16
N
h
0.25
-
0
0°
-
8°
01
5°
-
15°
02
0°
-
-
Document Number: 001-98295 Rev. *N
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
0.75
Page 15 of 19
S70FL01GS
13.2
24-Ball BGA 8 x 6 mm (ZSA024)
NOTES:
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
A
-
-
1.20
A1
0.20
-
-
D
8.00 BSC
E
6.00 BSC
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
D1
4.00 BSC
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
E1
4.00 BSC
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
MD
5
ME
5
n
24
b
0.35
0.40
eD
1.00 BSC
eE
1.00 BSC
SD
0.00
SE
0.00
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE
MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
0.45
PARALLEL TO DATUM C.
7
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE
THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
Document Number: 001-98295 Rev. *N
Page 16 of 19
S70FL01GS
14. Revision History
Document Title: S70FL01GS, 1 Gbit (128 Mbyte) 3.0V SPI Flash
Document Number: 001-98295
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
BWHA
11/06/2012 Initial release
*A
BWHA
Global: Datasheet designation updated from Advance Information to Preliminary
04/25/2013 DC Characteristics: DC Characteristics table: changed Max value of ILI, ILO,
ICC1, and ISB
*B
BWHA
05/16/2013
SOIC 16 Physical Diagram: Updated package nomenclature from S03016 to
SL3016
*C
BWHA
08/22/2013
Valid Combinations: Valid Combinations table: added MFV
DC Characteristics: DC Characteristics table: added ISB (Automotive)
*D
BWHA
11/08/2013 Global: Datasheet designation updated from Preliminary to Full Production
Description of Change
*E
BWHA
Features: Packages (all Pb-free): added BGA-24, 8 x 6 mm
Connections Diagrams: Added figure: 24-Ball BGA, 5 x 5 Ball Footprint (FAB024),
Top View
Ordering Information: Added options to: Model Number, Package Materials,
Package Type, and Speed
Valid Combinations: Added option to S70FL01GS Valid Combinations Table
03/19/2014
SDR AC Characteristics: SDR AC Characteristics (Single Die Package, VCC =
2.7V to 3.6V) table: updated tv Min
DDR AC Characteristics:Updated DDR AC Characteristics 66 MHz Operation
table
Capacitance Characteristics: Capacitance table: updated Max values and
removed note
*F
BWHA
11/07/2014 Valid Combinations: Added DP Speed Option for BGA 5x5 package
*G
BWHA
04/21/2015 Valid Combinations: Added BHV option
*H
4871631
BWHA
Updated to Cypress template.
08/24/2015 Changed Automotive Temperature Range to Industrial Plus Temperature Range
in Features and Section 4.
*I
5123878
BWHA
02/03/2016 Updated General Description.
BWHA
Updated Features on page 1: Added Extended and Automotive Grade
temperatures.
Updated DDR AC Characteristics 66 MHz and 80 MHz Operation on page 11
12/02/2016
table: Corrected tHO Min value, tCSH and tSU Max value.
Ordering Information on page 12: Added Extended and Automotive Grade.
Added Other Resources on page 14.
ECAO
Added ICC1 value for Quad DDR @ 80 MHz in Table 4, DC Characteristics
on page 8
Updated ICC5 value in Table 4, DC Characteristics on page 8
Updated DDR AC Characteristics 66 MHz and 80 MHz Operation on page 11
01/17/2017 Removed Extended (-40°C to +125°C) temperature option in Ordering Information
Updated Physical Diagram:
Updated package name and drawing from SL3016 to SS3016.
Updated package name and drawing from FAB024 to ZSA024.
*J
*K
5536564
5612027
Document Number: 001-98295 Rev. *N
Page 17 of 19
S70FL01GS
Document Title: S70FL01GS, 1 Gbit (128 Mbyte) 3.0V SPI Flash
Document Number: 001-98295
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*L
5669602
ECAO
Updated Figure 2, 24-Ball BGA, 5 x 5 Ball Footprint (ZSA024), Top View
on page 4.
Removed SS3016 from Section 13.1, SOIC 16 Lead, 300-mil Body Width
on page 15.
04/05/2017 Removed CS# from Table 2, Signal List on page 5.
Updated tSU in Table 6, SDR AC Characteristics (Single Die Package, VCC =
2.7V to 3.6V) on page 10.
Updated Cypress logo.
Updated Sales page.
*M
5783913
ECAO
06/23/2017
*N
6104454
BWHA
03/21/2018 Table 6: Removed Typ value for tche and updated tsu value as “3000”.
Document Number: 001-98295 Rev. *N
Changed OTP total space in Security Features.
Updated ISB values in Table 4.
Page 18 of 19
S70FL01GS
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
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liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-98295 Rev. *N
Revised April 03, 2018
Page 19 of 19