S70GL-P MirrorBit® Flash
S70GL02GP
2 Gigabit, 3.0 Volt-only Page Mode Flash Memory
featuring 90 nm MirrorBit Process Technology
S70GL-P MirrorBit® Flash Cover Sheet
Data Sheet
The S70GL02GP is not recommended for new designs. At this time, there is no direct replacement. Customers are
advised to use the S29GL01GP or contact your local sales representative for more information. Please refer to the
S29GL01GP data sheet for specifications and ordering information.
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S70GL-P_00
Revision 02
Issue Date May 19, 2008
D at a
S hee t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S70GL-P MirrorBit® Flash
S70GL-P_00_02 May 19, 2008
S70GL-P MirrorBit® Flash
S70GL02GP
2 Gigabit, 3.0 Volt-only Page Mode Flash Memory
featuring 90 nm MirrorBit Process Technology
Data Sheet
The S70GL02GP is not recommended for new designs. At this time, there is no direct replacement. Customers are advised to
use the S29GL01GP or contact your local sales representative for more information. Please refer to the S29GL01GP data
sheet for specifications and ordering information.
General Description
The Spansion S70GL02GP 2-Gigabit Mirrorbit Flash memory device is fabricated on 90 nm process technology. This device
offers a fast page access time of 25 ns with a corresponding random access time of 110 ns. It features a Write Buffer that
allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than
standard single byte/word programming algorithms. This makes the device an ideal product for today’s embedded applications
that require higher density, better performance and lower power consumption.
Distinctive Characteristics
Two 1024 Megabit (S29GL01GP) in a single 64-ball FortifiedBGA package (see publication S29GL-P_00 for full
specifications)
Single 3V read/program/erase (2.7-3.6 V)
Enhanced VersatileI/O™ control
– All input levels (address, control, and DQ input levels) and outputs
are determined by voltage on VIO input. VIO range is 1.65 to VCC
Offered Packages
– 64-ball Fortified BGA
Suspend and Resume commands for Program and Erase
operations
Write operation status bits indicate program and erase
operation completion
90 nm MirrorBit process technology
Unlock Bypass Program command to reduce programming
time
8-word/16-byte page read buffer
Support for CFI (Common Flash Interface)
32-word/64-byte write buffer reduces overall programming
time for multiple-word writes
Persistent and Password methods of Advanced Sector
Protection
Secured Silicon Sector region
WP#/ACC input
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
– Can be programmed and locked at the factory or by the customer
Uniform 64Kword/128KByte Sector Architecture
– S70GL02GP: two thousand forty-eight sectors
100,000 erase cycles per sector typical
20-year data retention typical
Publication Number S70GL-P_00
– Accelerates programming time (when VACC is applied) for greater
throughput during system production
– Protects first or last sector of each die, regardless of sector
protection settings
Hardware reset input (RESET#) resets device
Ready/Busy# output (RY/BY#) detects program or erase
cycle completion
Revision 02
Issue Date May 19, 2008
D at a
S hee t
Performance Characteristics
Max. Read Access Times (ns) (Note 1)
2 Gb
Parameter
V1
V2
V3
Random Access Time (tACC)
110
120
130
Page Access Time (tPACC)
25
25
25
CE# Access Time (tCE)
110
120
130
OE# Access Time (tOE)
25
25
30
Notes
1. Access times are dependent on VCC and VIO operating ranges. See Ordering Information on page 7 for further details.
2. V1: VCC = 3.0–3.6 V.
V2: VCC = VIO = 2.7–3.6 V.
V3: VIO = 1.65–VCC, VCC = 3 V.
3. Contact a sales representative for availability.
Current Consumption (typical values)
Random Access Read
30 mA
8-Word Page Read
1 mA
Program/Erase
50 mA
Standby
2 µA
Program & Erase Times (typical values)
Single Word Programming
4
60 µs
Effective Write Buffer Programming (VCC) Per Word
15 µs
Effective Write Buffer Programming (VACC) Per Word
15 µs
Sector Erase Time (64 Kword Sector)
0.5 s
S70GL-P MirrorBit® Flash
S70GL-P_00_02 May 19, 2008
Data
May 19, 2008 S70GL-P_00_02
She et
S70GL-P MirrorBit® Flash
5
D at a
S hee t
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
1.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Recommended Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Special Handling Instructions for BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
LSE064—64 ball Fortified Ball Grid Array, 13 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.
Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.
Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.
BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
S70GL-P MirrorBit® Flash
S70GL-P_00_02 May 19, 2008
Data
1.
She et
Ordering Information
The ordering part number is formed by a valid combination of the following:
S70GL02GP
11
F
F
C
R1
0
PACKING TYPE
0 = Tray (standard; see (Note 3)
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER (VIO range, protection when WP# =VIL)
01 = VIO = VCC = 2.7 to 3.6 V, highest address sector protected
02 = VIO = VCC = 2.7 to 3.6 V, lowest address sector protected
V1 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, highest address sector protected
V2 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, lowest address sector protected
R1 = VIO = VCC = 3.0 to 3.6 V, highest address sector protected
R2 = VIO = VCC = 3.0 to 3.6 V, lowest address sector protected
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
C = Commercial (0°C to +85°C)
PACKAGE MATERIALS SET
A = Pb (Note 1)
F = Pb-free
PACKAGE TYPE
F = Fortified Ball Grid Array, 1.0 mm pitch package
SPEED OPTION
11 = 110 ns
12 = 120 ns
13 = 130 ns
DEVICE NUMBER/DESCRIPTION
S70GL02GP
3.0 Volt-only, 2048 Megabit (128 M x 16-Bit/256 M x 8-Bit) Page-Mode Flash Memory
Manufactured on 90 nm MirrorBit process technology
1.1
Recommended Combinations
Recommended Combinations table below list various configurations planned to be available in volume. The
table below will be updated as new combinations are released. Check with your local sales representative to
confirm availability of specific configuration not listed or to check on newly released combinations.
S29GL-P Recommended Combinations (Note 1)
Base OPN
Speed (ns)
Package &
Temperature
Model Number
Packing Type
Ordering Part Number
(x = Packing Type)
S70GL02GP11FFCR1x
S70GL02GP
110
FFC, FAC
(Note 2)
R1, R2
0, 2, 3
S70GL02GP11FFCR2x
(Note 3)
S70GL02GP11FACR1x
S70GL02GP11FACR2x
Notes
1. Contact a local sales representative for availability.
2. BGA package marking omits leading “S29” and packing type designator from ordering part number.
3. Packing Type “0” is standard option.
May 19, 2008 S70GL-P_00_02
S70GL-P MirrorBit® Flash
7
D at a
2.
S hee t
Input/Output Descriptions & Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
8
Symbol
Type
Description
A26–A0
Input
DQ14–DQ0
I/O
Address lines for GL02GP
DQ15/A-1
I/O
CE#
Input
Chip Enable.
Data input/output.
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
OE#
Input
Output Enable.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply.
VIO
Supply
Versatile IO Input.
VSS
Supply
Ground.
RY/BY#
Output
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
VIL, the device is actively erasing or programming. At High Z, the device is in ready.
BYTE#
Input
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0DQ7 are active. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15
are active.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#/ACC
Input
Write Protect/Acceleration Input. At VIL, disables program and erase functions in the
outermost sectors. At VHH, accelerates programming; automatically places device in
unlock bypass mode. Should be at VIH for all other conditions.
RFU
Reserved
Reserved for future use. Not connected internally.
S70GL-P MirrorBit® Flash
S70GL-P_00_02 May 19, 2008
Data
2.1
She et
Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages.
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Figure 2.1 64-ball Fortified Ball Grid Array
64-ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
H8
RFU
A22
A23
VIO
VSS
A24
A25
RFU
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
BYTE#
DQ15/A-1
VSS
A6
B6
C6
D6
E6
F6
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
DQ4
WE#
RESET#
A21
A19
DQ5
DQ12
VCC
A4
B4
C4
D4
E4
F4
G4
H4
A18
A20
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
May 19, 2008 S70GL-P_00_02
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
RFU
A26
RFU
RFU
RFU
VIO
RFU
RFU
S70GL-P MirrorBit® Flash
9
D at a
2.2
S hee t
LSE064—64 ball Fortified Ball Grid Array, 13 x 11 mm
Figure 2.2 LSE064—64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm
NOTES:
PACKAGE
LSE 064
JEDEC
N/A
DxE
13.00 mm x 11.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.40
A1
0.40
---
---
A2
0.79
---
0.91
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BODY THICKNESS
E
11.00 BSC.
BODY SIZE
7.00 BSC.
MATRIX FOOTPRINT
E1
7.00 BSC.
MD
8
MATRIX SIZE D DIRECTION
MATRIX FOOTPRINT
ME
8
MATRIX SIZE E DIRECTION
64
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL COUNT
0.70
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
1.00 BSC.
BALL PITCH
eD
1.00 BSC
BALL PITCH
SD / SE
0.50 BSC.
---
BALL POSITION DESIGNATION PER JEP95,
SECTION 4.3, SPP-010.
4.
D1
0.60
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
PROFILE
BODY SIZE
0.50
2.
BALL HEIGHT
13.00 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
NOTE
D
Øb
1.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SOLDER BALL PLACEMENT
8.
"+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
DEPOPULATED SOLDER BALLS
3611 \ 16-038.15 \ 11.13.6
10
S70GL-P MirrorBit® Flash
S70GL-P_00_02 May 19, 2008
Data
She et
3. Memory Map
The S70GL02GP consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 3.1.
Table 3.1 S70GL02GP Sector & Memory Address Map
Uniform Sector
Size
Sector
Count
64 Kword/128 Kb
Sector
Range
Address Range (16-bit)
Notes
SA00
0000000h–000FFFFh
Sector Starting Address
2048
:
:
SA2047
7FF0000H–7FFFFFFh
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA2046) have sector starting and ending addresses that form the same pattern as all other
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
4. Autoselect
Table 4.1 provides the device identification codes for the S70GL02GP. For more information on the
autoselect function, refer to the S29GL-P data sheet (publication number S29GL-P_00).
Table 4.1 Autoselect Addresses in System
Description
Address
Read Data (word/byte mode)
Manufacturer ID
(Base) + 00h
xx01h/1h
Device ID, Word 1
(Base) + 01h
227Eh/7Eh
Device ID, Word 2
(Base) + 0Eh
2248h/48h
Device ID, Word 3
(Base) + 0Fh
2201h/01h
Secure Device Verify
(Base) + 03h
Sector Protect Verify
(SA) + 02h
For S70GL02GPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked.
For S70GL02GPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked.
xx01h/01h = Locked, xx00h/00h = Unlocked
5. Erase And Programming Performance
Table 5.1 Erase And Programming Performance
Typ
(Note 1)
Parameter
Sector Erase Time
Chip Erase Time
S70GL02GP
Max
(Note 2)
Unit
0.5
3.5
sec
1024
4096
sec
Total Write Buffer Time, for 64 bytes
480
µs
Total Accelerated Write Buffer Programming Time, for 64
bytes
432
µs
1928
sec
Chip Program Time
S70GL02GP
Comments
Excludes 00h programming
prior to erasure (Note 3)
Excludes system level
overhead (Note 4)
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V VCC, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, VCC = 3.0 V, 100,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
May 19, 2008 S70GL-P_00_02
S70GL-P MirrorBit® Flash
11
D at a
S hee t
6. BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
12
20
pF
COUT
Output Capacitance
VOUT = 0
20
24
pF
CIN2
Control Pin Capacitance
VIN = 0
16
20
pF
RESET#, WP#/ACC
Separated Control Pin
VIN = 0
84
90
pF
CE#
Separated Control Pin
VIN = 0
44
50
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
12
S70GL-P MirrorBit® Flash
S70GL-P_00_02 May 19, 2008
Data
She et
7. Revision History
Section
Description
Revision 01 (December 4, 2006)
Initial Release.
Revision 02 (May 19, 2008)
Changed data sheet designation
Global
Added Product Life-cycle notice
Removed Table of Figures and Table of Tables
- Changed sample OPN
Ordering Information
- Added Commercial temperature range
- Changed configuration in “Device Number/description”
- Modified “Recommended Combination” table & removed TSOP package option
Erase And Program Performance
Chip Program Time: removed comment
Common Flash Memory Interface
Removed section (see publication S29GL-P_00 for details)
May 19, 2008 S70GL-P_00_02
S70GL-P MirrorBit® Flash
13
D at a
S hee t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2006-2008 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-SIM™
and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes
only and may be trademarks of their respective owners.
14
S70GL-P MirrorBit® Flash
S70GL-P_00_02 May 19, 2008
工商网监
湘ICP备2023018690号
