STK11C68-SF45

STK11C68 64-Kbit (8 K × 8) SoftStore nvSRAM Functional Description ■ 25 ns, 35 ns, and 45 ns access times ■ Pin compatible with industry standard SRAMs ■ Software initiated nonvolatile STORE ■ Unlimited Read and Write endurance ■ Automatic RECALL to SRAM on power up ■ Unlimited RECALL cycles ■ 1,000,000 STORE cycles The Cypress STK11C68 is a 64Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers under software control from SRAM to the nonvolatile elements (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation) from the nonvolatile memory. RECALL operations are also available under software control. ■ 100 year data retention For a complete list of related documentation, click here. ■ Single 5 V+10% operation ■ Commercial and industrial temperature ■ 28-pin (330 mil) SOIC package ■ 28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages ■ RoHS compliance Logic Block Diagram A5 A7 A8 A9 A 11 STATIC RAM ARRAY 128 X 512 RECALL STORE/ RECALL CONTROL DQ 0 DQ 4 DQ 5 DQ 6 A0 - A 12 COLUMN I/O INPUT BUFFERS DQ 2 DQ 3 HSB SOFTWARE DETECT A 12 DQ 1 VCAP POWER CONTROL STORE ROW DECODER A6 VCC Quantum Trap 128 X 512 COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 DQ 7 OE CE WE Cypress Semiconductor Corporation Document Number: 001-50638 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 24, 2015 Not recommended for new designs. In production to support ongoing production programs only. Features STK11C68 Pin Configurations ........................................................... Pin Definitions .................................................................. Device Operation .............................................................. SRAM Read ....................................................................... SRAM Write ....................................................................... Software STORE ............................................................... Software RECALL............................................................. Hardware RECALL (Power Up)........................................ Hardware Protect.............................................................. Noise Considerations....................................................... Low Average Active Power.............................................. Best Practices................................................................... Maximum Ratings............................................................. Operating Range............................................................... DC Electrical Characteristics .......................................... Data Retention and Endurance ....................................... Capacitance ...................................................................... Thermal Resistance.......................................................... Document Number: 001-50638 Rev. *F 3 3 4 4 4 4 4 4 4 4 4 5 6 6 6 6 7 7 AC Test Conditions .......................................................... 7 AC Switching Characteristics ......................................... 8 SRAM Read Cycle ...................................................... 8 SRAM Write Cycle....................................................... 9 AutoStore INHIBIT or Power Up RECALL .................... 10 Software Controlled STORE/RECALL Cycle................ 11 Part Numbering Nomenclature...................................... 12 Ordering Information...................................................... 12 Package Diagrams.......................................................... 13 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Page 2 of 18 Not recommended for new designs. In production to support ongoing production programs only. Contents STK11C68 Pin Configurations NC 1 28 VCC A12 2 27 A7 3 26 WE NC A6 4 25 A8 A5 5 24 A9 A4 6 23 A 11 A3 7 A2 8 A1 22 OE 21 A 10 9 20 A0 10 19 CE DQ 7 DQ0 11 18 DQ 6 DQ1 12 17 DQ 5 DQ2 13 16 DQ4 VSS 14 15 DQ3 (TOP) Pin Definitions Pin Name Alt I/O Type A0–A12 Input DQ0-DQ7 Input or Output Description Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Bidirectional Data I/O Lines. Used as input or output lines depending on operation. WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. VSS VCC Ground Ground for the Device. The device is connected to ground of the system. Power Supply Power Supply Inputs to the Device. Document Number: 001-50638 Rev. *F Page 3 of 18 Not recommended for new designs. In production to support ongoing production programs only. Figure 1. Pin Diagram – 28-Pin SOIC/DIP and 28-Pin LLC STK11C68 The STK11C68 is a versatile memory chip that provides several modes of operation. The STK16C88 can operate as a standard 8K x 8 SRAM. A 8K x 8 array of nonvolatile storage elements shadow the SRAM. SRAM data can be copied nonvolatile memory or nonvolatile data can be recalled to the SRAM. SRAM Read The STK11C68 performs a Read cycle whenever CE and OE are LOW while WE is HIGH. The address specified on pins A0–12 determines the 8,192 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA (Read cycle 1). If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (Read cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE brought LOW. SRAM Write A Write cycle is performed whenever CE and WE are LOW. The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK11C68 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of Reads from specific addresses is used for STORE initiation, it is important that no other Read or Write accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following Read sequence is performed: 1. Read address 0x0000, Valid READ 2. Read address 0x1555, Valid READ 3. Read address 0x0AAA, Valid READ 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0F, Initiate STORE cycle The software sequence is clocked with CE controlled Reads. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that Read cycles and not Write cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the Document Number: 001-50638 Rev. *F tSTORE cycle time is fulfilled, the SRAM is again activated for Read and Write operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of Read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled Read operations is performed: 1. Read address 0x0000, Valid READ 2. Read address 0x1555, Valid READ 3. Read address 0x0AAA, Valid READ 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0E, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for Read and Write operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. Hardware RECALL (Power Up) During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. If the STK11C68 is in a Write state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC. Hardware Protect The STK11C68 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage conditions. When VCAP (VCC – 0.2 V). All other inputs cycling. tRC= 200 ns, 5 V, 25 °C Dependent on output loading and cycle rate. Values obtained Typical without output loads. 10 mA ISB1[2] VCC Standby Current (Standby, Cycling TTL Input Levels) Commercial 27 23 20 mA mA mA Industrial 28 24 21 mA mA mA 750 A 1500 A ISB2 [2] VCC Standby Current tRC = 25 ns, CE > VIH tRC = 35 ns, CE > VIH tRC = 45 ns, CE > VIH CE > (VCC – 0.2 V). All others VIN < 0.2 V or > Commercial (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Industrial Inputs are static. f = 0 MHz. IIX Input Leakage Current VCC = Max, VSS < VIN < VCC -1 +1 A IOZ Off State Output Leakage Current -5 +5 A VIH Input HIGH Voltage 2.2 VCC + 0.5 V VSS – 0.5 0.8 VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL VIL Input LOW Voltage VOH Output HIGH Voltage IOUT = –4 mA VOL Output LOW Voltage IOUT = 8 mA V 2.4 V 0.4 V Data Retention and Endurance Parameter Description DATAR Data Retention NVC Nonvolatile STORE Operations Min Unit 100 Years 1,000 K Note 2. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out. Document Number: 001-50638 Rev. *F Page 6 of 18 Not recommended for new designs. In production to support ongoing production programs only. Operating Range Storage Temperature ............................... –65 C to +150 C STK11C68 Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 0 to 3.0 V Max Unit 8 pF 7 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.[3] Parameter Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 28-SOIC 28-CDIP 28-LCC Unit TBD TBD TBD C/W TBD TBD TBD C/W Figure 4. AC Test Loads R1 480  5.0 V Output 30 pF R2 255  AC Test Conditions Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% to 90%) ...................... VIH; device is continuously selected. 6. Measured ±200 mV from steady state output voltage. Document Number: 001-50638 Rev. *F Page 8 of 18 Not recommended for new designs. In production to support ongoing production programs only. Parameter Cypress Alt Parameter tELQV tACE tAVAV, tELEH tRC [4] tAVQV tAA [5] tGLQV tDOE tAXQX tOHA [5] tELQX tLZCE [6] tEHQZ tHZCE [6] [6] tGLQX tLZOE tGHQZ tHZOE [6] tELICCH tPU [3] [3] tEHICCL tPD STK11C68 SRAM Write Cycle Cypress Parameter 25 ns Description Alt tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [6,7] tLZWE [6] Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 35 ns Max Min 25 20 20 10 0 20 0 0 45 ns Max 35 25 25 12 0 25 0 0 10 Min 45 30 30 15 0 30 0 0 13 5 Max 5 15 5 Unit ns ns ns ns ns ns ns ns ns ns Switching Waveforms Figure 7. SRAM Write Cycle 1: WE Controlled [7, 8] tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 8. SRAM Write Cycle 2: CE and OE Controlled [7, 8] tWC ADDRESS CE WE tHA tSCE tSA tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 7. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 8. CE or WE must be greater than VIH during address transitions. Document Number: 001-50638 Rev. *F Page 9 of 18 Not recommended for new designs. In production to support ongoing production programs only. Parameter STK11C68 AutoStore INHIBIT or Power Up RECALL tHRECALL [9] tSTORE VSWITCH VRESET Alt tRESTORE tHLHZ Description Power up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level Low Voltage Reset Level STK11C68 Max 550 10 4.0 4.5 3.6 Min Unit s ms V V Switching Waveform Figure 9. AutoStore INHIBIT/Power Up RECALL VCC 5V VSWITCH VRESET STORE INHIBIT POWER-UP RECALL tHRECALL DQ (DATA OUT) POWER-UP RECALL BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH Note 9. tHRECALL starts from the time VCC rises above VSWITCH. Document Number: 001-50638 Rev. *F Page 10 of 18 Not recommended for new designs. In production to support ongoing production programs only. Parameter STK11C68 Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [10, 11] Alt Description 25 ns Min 35 ns Max Min 45 ns Max Min Max Unit tRC tAVAV STORE/RECALL Initiation Cycle Time 25 35 45 ns tSA[10] tCW[10] tHACE[10] tRECALL[10] tAVEL Address Setup Time 0 0 0 ns tELEH Clock Pulse Width 20 25 30 ns tELAX Address Hold Time 20 20 20 ns RECALL Duration 20 20 20 s Switching Waveform Figure 10. CE Controlled Software STORE/RECALL Cycle [11] tRC ADDRESS # 1 ADDRESS tSA tRC ADDRESS # 6 tSCE CE tHACE OE t STORE / t RECALL DQ (DATA) DATA VALID DATA VALID HIGH IMPEDANCE Notes 10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence). 11. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. Document Number: 001-50638 Rev. *F Page 11 of 18 Not recommended for new designs. In production to support ongoing production programs only. Parameter STK11C68 Part Numbering Nomenclature Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70 °C) I - Industrial (–40 to 85 °C) Lead Finish Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns F = 100% Sn (Matte Tin) Package: S = Plastic 28-pin 330 mil SOIC C = Ceramic 28-pin 300 mil DIP L = Ceramic 28-pin 350 mil LLC Ordering Information These parts are not recommended for new designs. They are in production to support ongoing production programs only. Speed (ns) 35 45 Ordering Code STK11C68-C35I Package Diagram 001-51695 Package Type 28-Pin CDIP (300 mil) STK11C68-SF45TR 51-85058 28-Pin SOIC (330 mil) STK11C68-SF45 51-85058 28-Pin SOIC (330 mil) Operating Range Industrial All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts Document Number: 001-50638 Rev. *F Page 12 of 18 Not recommended for new designs. In production to support ongoing production programs only. STK11C68 – S F 45 I TR STK11C68 Package Diagrams 51-85058 *D Document Number: 001-50638 Rev. *F Page 13 of 18 Not recommended for new designs. In production to support ongoing production programs only. Figure 11. 28-Pin (330 Mil) SOIC (51-85058) STK11C68 Package Diagrams (continued) 001-51695 *C Document Number: 001-50638 Rev. *F Page 14 of 18 Not recommended for new designs. In production to support ongoing production programs only. Figure 12. 28-Pin (300 Mil) Side Braze DIL (001-51695) STK11C68 Package Diagrams (continued) Not recommended for new designs. In production to support ongoing production programs only. Figure 13. 28-Pad (350 Mil) LCC (001-51696) 001-51696 *C Document Number: 001-50638 Rev. *F Page 15 of 18 STK11C68 Acronym Document Conventions Description Units of Measure CE CMOS chip enable complementary metal oxide semiconductor °C degree Celsius EIA electronic industries alliance Hz hertz I/O input/output kHz kilohertz nvSRAM non-volatile static random access memory k kilo-ohm OE RoHS output enable MHz megahertz restriction of hazardous substances A microampere SRAM static random access memory F microfarad WE write enable s microsecond mA milliampere ms millisecond ns nanosecond  ohm % percent pF picofarad V volt W watt Document Number: 001-50638 Rev. *F Symbol Unit of Measure Not recommended for new designs. In production to support ongoing production programs only. Acronyms Page 16 of 18 STK11C68 Document History Page Document Title: STK11C68 64-Kbit (8 K × 8) SoftStore nvSRAM Document Number: 001-50638 ECN Orig. of Change Submission Date Description of Change ** 2625084 GVCH/PYRS 01/30/2009 New data sheet *A 2826441 GVCH 12/11/2009 Added following text in the Ordering Information section: “These parts are not recommended for new designs. In production to support ongoing production programs only.” Added watermark in PDF stating “Not recommended for new designs. In production to support ongoing production programs only.” Added Contents on page 2. *B 2902591 GVCH 04/05/2010 Removed inactive parts from Ordering Information. Updated Package Diagrams. *C 3052511 GVCH 10/08/2010 Removed the following inactive parts from the Ordering Information table: STK11C68-L35, STK11C68-L35I, STK11C68-L45, STK11C68-L45I, STK11C68-SF25, STK11C68-SF25I, STK11C68-SF25ITR, STK11C68-SF25TR Removed the 28-pin LCC package diagram *D 3527653 GVCH 02/20/2012 Package Diagrams: Updated 28-Pin (330 Mil) SOIC package diagram *E 4571551 GVCH 11/17/2014 Added documentation related hyperlink in page 1 Removed pruned parts - STK11C68-SF45ITR, STK11C68-SF45I Updated package diagram from 001-51695 *A to 001-51695 *B *F 4693449 GVCH 03/24/2015 Figure 13: Added 28-Pad (350 Mil) LCC package diagram Updated package diagram spec 51-85058 *C to 51-85058 *D Updated package diagram spec 001-51695 *B to 001-51695 *C Document Number: 001-50638 Rev. *F Page 17 of 18 Not recommended for new designs. In production to support ongoing production programs only. Revision STK11C68 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-50638 Rev. *F Revised March 24, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18 Not recommended for new designs. In production to support ongoing production programs only. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.