STK12C68-5 (SMD5962-94599)
64 Kbit (8K x 8) AutoStore nvSRAM
Features
Functional Description
■
35 ns and 55 ns access times
■
Hands off automatic STORE on power down with external
68 µF capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated
by software, hardware, or AutoStore™ on power down
■
RECALL to SRAM initiated by software or power up
■
Unlimited Read, Write, and Recall cycles
■
1,000,000 STORE cycles to QuantumTrap
■
100 year data retention to QuantumTrap
The Cypress STK12C68-5 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE is initiated with the HSB pin.
■
Single 5V+10% operation
■
Military temperature
■
28-pin (300mil) CDIP and 28-pad LCC packages
Logic Block Diagram
Quantum Trap
128 X 512
A5
STORE
ROW DECODER
A6
A7
A8
A9
A 11
STATIC RAM
ARRAY
128 X 512
RECALL
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
A 12
DQ 0
A0
- A12
COLUMN I/O
INPUT BUFFERS
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-51026 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 02, 2009
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STK12C68-5 (SMD5962-94599)
Pinouts
Figure 1. Pin Diagram - 28-Pin DIP
Figure 2. Pin Diagram - 28-Pin LLC
Pin Definitions
Pin Name
Alt
A0–A12
IO Type
Input
DQ0-DQ7
Description
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-51026 Rev. **
Page 2 of 18
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STK12C68-5 (SMD5962-94599)
Device Operation
The STK12C68-5 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK12C68-5 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE
operations.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage capacitor
between 68 µF and 220 µF (+20%) rated at 6V must be provided.
The voltage on the VCAP pin is driven to 5V by a charge pump
internal to the chip. A pull up is placed on WE to hold it inactive
during power up.
Figure 3. AutoStore Mode
9FF
:(
N2KP
9&$3
5)
%\SDVV
+6%
5)
Y
The STK12C68-5 performs a Read cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0–12 determines the 8,192 data bytes accessed. When
the Read is initiated by an address transition, the outputs are
valid after a delay of tAA (Read cycle 1). If the Read is initiated
by CE or OE, the outputs are valid at tACE or at tDOE, whichever
is later (Read cycle 2). The data outputs repeatedly respond to
address changes within the tAA access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
N2KP
SRAM Read
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ0–7 are written into the memory if it has valid tSD, before
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
AutoStore Operation
The STK12C68-5 stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK12C68-5.
Document Number: 001-51026 Rev. **
9VV
In system power mode, both VCC and VCAP are connected to the
+5V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the STK12C68-5 operates on the stored
system charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6V during the 10 ms
STORE cycle.
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations are ignored, unless at least one Write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a Write operation has taken place. An
optional pull up resistor is shown connected to HSB. The HSB
signal is monitored by the system to detect if an AutoStore cycle
is in progress.
Page 3 of 18
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STK12C68-5 (SMD5962-94599)
9FF
:(
N2KP
9&$3
N2KP
5)
%\SDVV
Figure 4. AutoStore Inhibit Mode
+6%
During any STORE operation, regardless of how it is initiated,
the STK12C68-5 continues to drive the HSB pin LOW,
releasing it only when the STORE is complete. After
completing the STORE operation, the STK12C68-5 remains
disabled until the HSB pin returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
If the STK12C68-5 is in a Write state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.
Software STORE
9VV
If the power supply drops faster than 20 us/volt before Vcc
reaches VSWITCH, then a 2.2 ohm resistor must be connected
between VCC and the system supply to avoid momentary
excess of current between VCC and VCAP.
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then VCC
is tied to ground and +5V is applied to VCAP (Figure 4). This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the STK12C68-5 is operated in this configuration,
references to VCC are changed to VCAP throughout this data
sheet. In this mode, STORE operations are triggered through
software control or the HSB pin. To enable or disable Autostore
using an IO port pin see Preventing Store on page 5. It is not
permissible to change between these three options “on the
fly”.
Hardware STORE (HSB) Operation
The STK12C68-5 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is
driven LOW, the STK12C68-5 conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
Write to the SRAM takes place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress.
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the STK12C68-5 continues SRAM operations for tDELAY.
During tDELAY, multiple SRAM Read operations take place. If
a Write is in progress when HSB is pulled LOW, it allows a
time, tDELAY to complete. However, any SRAM Write cycles
requested after HSB goes LOW are inhibited until HSB returns
HIGH.
Document Number: 001-51026 Rev. **
Data is transferred from the SRAM to the nonvolatile memory
by a software address sequence. The STK12C68-5 software
STORE cycle is initiated by executing sequential CE controlled
Read cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output
are disabled until the cycle is completed.
Because a sequence of Reads from specific addresses is
used for STORE initiation, it is important that no other Read or
Write accesses intervene in the sequence. If they intervene,
the sequence is aborted and no STORE or RECALL takes
place.
To initiate the software STORE cycle, the following Read
sequence is performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
The software sequence is clocked with CE controlled Reads
or OE controlled Reads. When the sixth address in the
sequence is entered, the STORE cycle commences and the
chip is disabled. It is important that Read cycles and not Write
cycles are used in the sequence. It is not necessary that OE
is LOW for a valid sequence. After the tSTORE cycle time is
fulfilled, the SRAM is again activated for Read and Write
operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner
similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE controlled Read
operations is performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
Page 4 of 18
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STK12C68-5 (SMD5962-94599)
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
Figure 5. Current Versus Cycle Time (Read)
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
Data Protection
The STK12C68-5 protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and Write operations. The low voltage condition is detected
when VCC is less than VSWITCH. If the STK12C68-5 is in a Write
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the Write is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Figure 6. Current Versus Cycle Time (Write)
Noise Considerations
The STK12C68-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK12C68-5 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage conditions. When VCAP (VCC – 0.2V). All other inputs cycling.
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values
obtained without output loads.
Typical
10
mA
ICC4
Average VCAP Current All Inputs Do Not Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
2
mA
ISB1[5]
VCC Standby Current tRC = 35 ns, CE > VIH
(Standby, Cycling TTL tRC = 55 ns, CE > VIH
Input Levels)
24
19
mA
mA
ISB2 [5]
VCC Standby Current
2.5
mA
IIX
-1
+1
μA
IOZ
Input Leakage Current VCC = Max, VSS < VIN < VCC
Off State Output
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
Leakage Current
-5
+5
μA
VIH
Input HIGH Voltage
2.2
VCC + 0.5
V
VIL
Input LOW Voltage
VSS – 0.5
0.8
V
VOH
Output HIGH Voltage
IOUT = –4 mA
VOL
Output LOW Voltage
IOUT = 8 mA
0.4
V
VBL
Logic ‘0’ Voltage on
HSB Output
IOUT = 3 mA
0.4
V
VCAP
Storage Capacitor
Between Vcap pin and Vss, 6V rated. 68 µF +20% nom.
260
µF
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
2.4
54
V
Notes
4. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
5. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
Document Number: 001-51026 Rev. **
Page 7 of 18
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STK12C68-5 (SMD5962-94599)
Data Retention and Endurance
Parameter
Description
DATAR
Data Retention
NVC
Nonvolatile STORE Operations
Min
Unit
100
Years
1,000
K
Capacitance
In the following table, the capacitance parameters are listed.[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0 V
Unit
8
pF
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[6]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
28-CDIP 28-LCC
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
Unit
TBD
TBD
°C/W
TBD
TBD
°C/W
Figure 7. AC Test Loads
R1 963Ω
R1 963Ω For Tri-state Specs
5.0V
5.0V
Output
Output
30 pF
R2
512Ω
5 pF
R2
512Ω
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times (10% to 90%) ......................