STK14C88
32 K x 8 AutoStore nvSRAM
Features
Description
■
25 ns, 35 ns, and 45 ns read access and R/W cycle time
The Cypress STK14C88 is a 256 Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
■
Unlimited read/write endurance
■
Automatic nonvolatile STORE on power loss
■
Nonvolatile STORE under hardware or software control
■
Automatic RECALL to SRAM on power up
■
Unlimited RECALL cycles
■
1-Million STORE cycles
■
100-year nonvolatile data retention
■
Single 5 V + 10% power supply
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
■
Commercial, industrial, military temperatures
For a complete list of related documentation, click here.
■
32-Pin 300 mil SOIC (RoHS-compliant)
■
32-Pin CDIP and LCC packages
The SRAM provides the fast access and cycle times, ease of
use, and unlimited read and write endurance of a normal SRAM.
Data automatically transfers to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
Logic Block Diagram
VCCX
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
POWER
CONTROL
STORE
STATIC RAM
ARRAY
512 x 512
STORE/
RECALL
CONTROL
RECALL
SOFTWARE
DETECT
COLUMN I/O
INPUT BUFFERS
A5
A6
A7
A8
A9
A11
A12
A13
A14
ROW DECODER
Quantum Trap
512 x 512
VCAP
HSB
A0 - A13
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52038 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 31, 2015
STK14C88
Contents
Pin Configurations ........................................................... 3
Pin Descriptions ............................................................... 3
Absolute Maximum Ratings ............................................ 4
DC Characteristics ........................................................... 4
AC Test Conditions .......................................................... 5
Capacitance ...................................................................... 5
SRAM Read Cycles #1 and #2 ......................................... 6
SRAM Write Cycle #1 and #2 ........................................... 7
Hardware Mode Selection................................................ 8
Hardware STORE Cycle ................................................... 8
AutoStore/Power up RECALL ......................................... 9
Software STORE/RECALL Mode Selection .................. 10
Software-Controlled STORE/RECALL Cycle................ 10
nvSRAM Operation......................................................... 11
Noise Considerations..................................................... 11
SRAM Read ..................................................................... 11
SRAM Write ..................................................................... 11
Power Up RECALL ......................................................... 11
Software Nonvolatile STORE......................................... 11
Software Nonvolatile RECALL ...................................... 11
Document Number: 001-52038 Rev. *F
AutoStore Mode..............................................................
AutoStore INHIBIT Mode................................................
HSB Operation ................................................................
Best Practices.................................................................
Preventing STORES .......................................................
Hardware Protect............................................................
Low Average Active Power............................................
Ordering Information......................................................
Commercial and Industrial Ordering Information.......
Military Ordering Information .....................................
Package Diagrams..........................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page ................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
11
12
12
13
13
13
13
14
14
15
16
19
19
19
20
21
21
21
21
Page 2 of 21
STK14C88
Pin Configurations
27
A9
7
26
A11
8
25
NC
A2
9
24
G
NC
10
23
A10
A1
A0
11
22
12
21
E
DQ7
DQ0
13
20
DQ1
DQ2
14
19
DQ6
DQ5
15
18
DQ4
VSS
16
17
DQ3
(TOP)
W
6
HSB
A5
A4
A3
A6
A13
A5
A8
A4
A3
A11
A9
NC
G
(TOP)
A2
NC
A1
A10
A0
E
DQ0
DQ7
DQ6
5
W
A13
A8
DQ5
A6
29
28
VCap
4
VCCx
HSB
30
DQ4
31
3
DQ3
2
A12
A7
A14
A14
VSS
VCC
A7
32
DQ2
1
DQ1
VCAP
Figure 2. Pin Diagram - 32-Pin 450 Mil LCC
A12
Figure 1. Pin Diagram - 32-Pin 300 Mil SOIC/CDIP
Pin Descriptions
Pin Name
I/O
A14-A0
Input
DQ7-DQ0
I/O
E
Input
Chip Enable: The active low E input selects the device.
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E.
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles. Deasserting
G high caused the DQ pins to tristate.
VCC
HSB
Description
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array.
Data: Bidirectional 8-bit data bus for accessing the nvSRAM.
Power Supply Power: 5.0 V +10%.
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external
to the chip, it initiates a nonvolatile STORE operation. A weak pull-up resistor keeps this pin high if not
connected (optional connection).
VCAP
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS
Power Supply Ground.
NC
No Connect
Unlabeled pins have no internal connections.
Document Number: 001-52038 Rev. *F
Page 3 of 21
STK14C88
Absolute Maximum Ratings
Note Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Voltage on Input Relative to Ground...............–0.5 V to 7.0 V
Voltage on Input Relative to VSS .........–0.6 V to (VCC + 0.5 V)
Voltage on DQ0-7 or HSB ....................–0.5 V to (VCC + 0.5 V)
Temperature under Bias ............................. –55 C to 125 C
Storage Temperature .................................. –65 C to 150 C
Power Dissipation............................................................ 1 W
DC Output Current (1 output at a time, 1s duration).... 15 mA
DC Characteristics
Over the operating range (VCC = 5.0 V ± 10%)[4]
Symbol
Parameter
Commercial
Industrial/
Military
Unit
Notes
Min
Max
Min
Max
Average VCC current
–
97
80
70
–
100
85
70
mA
mA
mA
tAVAV = 25 ns
tAVAV = 35 ns
tAVAV = 45 ns
ICC2[2]
Average VCC current during
STORE
–
3
–
3
mA
All Inputs Don’t Care,
VCC = max
ICC3[1]
Average VCC Current at tAVAV =
200 ns
5V, 25°C, Typical
–
10
–
10
mA
W (V CC – 0.2 V)
All others cycling, CMOS
levels
ICC4[2]
Average VCAP current during
AutoStore Cycle
–
2
–
2
mA
All Inputs Don’t Care
ISB1[3]
Average VCC current
(Standby, Cycling TTL Input
Levels)
–
30
25
22
–
31
26
23
mA
mA
mA
tAVAV = 25 ns, E VIH
tAVAV = 35 ns, E VIH
tAVAV = 45 ns, E VIH
ISB2[3]
VCC Standby current
(Standby, Stable CMOS Input
Levels)
–
1.5
–
1.5
mA
E (V CC – 0.2 V)
All Others VIN 0.2 V or
(VCC – 0.2 V)
IILK
Input Leakage current
–
1
–
1
A
VCC = max
VIN = VSS to VCC
IOLK
Off-State output leakage current
–
5
–
5
A
VCC = max
VIN = VSS to VCC, E or G VIH
VIH
Input Logic “1” voltage
2.2
VCC + 0.5
2.2
VCC +0.5
V
All inputs
VIL
Input Logic “0” voltage
VSS – .5
0.8
VSS – .5
0.8
V
All inputs
VOH
Output Logic “1” voltage
2.4
–
2.4
–
V
IOUT = – 4 mA except HSB
VOL
Output Logic “0” voltage
–
0.4
–
0.4
V
IOUT = 8 mA except HSB
VBL
Logic “0” voltage on HSB output
–
0.4
–
0.4
V
IOUT = 3 mA
TA
Operating temperature
0
70
–40/–55
85/125
C
ICC1
[1]
Notes
1. ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
2. ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE).
3. E VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
4. VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
Document Number: 001-52038 Rev. *F
Page 4 of 21
STK14C88
AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V
Input rise and fall times ...............................................
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