STK14C88
32Kx8 AutoStore nvSRAM
Features
Description
■
25, 35, 45 ns Read Access and R/W Cycle Time
■
Unlimited Read/Write Endurance
The Cypress STK14C88 is a 256 Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
1 Million STORE Cycles
■
100-Year Nonvolatile Data Retention
■
Single 5V+10% Power Supply
■
Commercial, Industrial, Military Temperatures
■
32-Pin 300 mil SOIC (RoHS-Compliant)
■
32-Pin CDIP and LCC Packages
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The SRAM provides the fast access and cycle times, ease of
use, and unlimited read and write endurance of a normal SRAM.
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Data automatically transfers to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
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The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
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Logic Block Diagram
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STATIC RAM
ARRAY
512 x 512
VCAP
POWER
CONTROL
STORE
STORE/
RECALL
CONTROL
RECALL
SOFTWARE
DETECT
COLUMN I/O
INPUT BUFFERS
N
ot
R
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
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A5
A6
A7
A8
A9
A11
A12
A13
A14
ROW DECODER
Quantum Trap
512 x 512
VCCX
HSB
A0 - A13
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52038 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 01, 2009
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STK14C88
Contents
Features................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions .................................................................. 3
Absolute Maximum Ratings ............................................... 4
DC Characteristics .............................................................. 4
AC Test Conditions ............................................................. 5
Capacitance ......................................................................... 5
SRAM Read Cycles #1 and #2 ............................................ 6
SRAM Write Cycle #1 and #2 .............................................. 7
Hardware Mode Selection................................................... 8
Hardware STORE Cycle ...................................................... 8
AutoStore/Power up RECALL ............................................ 9
nvSRAM Operation............................................................ 10
Noise Considerations........................................................ 10
SRAM Read ........................................................................ 10
10
10
10
10
10
11
11
12
12
12
12
14
14
15
19
19
19
19
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SRAM Write ........................................................................
Power Up RECALL ............................................................
Software Nonvolatile STORE............................................
Software Nonvolatile RECALL .........................................
AutoStore Mode.................................................................
AutoStore INHIBIT Mode...................................................
HSB Operation ...................................................................
Best Practices....................................................................
Preventing STORES ..........................................................
Hardware Protect...............................................................
Low Average Active Power...............................................
Software STORE/RECALL Mode Selection .....................
Software-Controlled STORE/RECALL Cycle...................
Ordering Information.........................................................
Document History Page ....................................................
Sales, Solutions, and Legal Information .........................
Worldwide Sales and Design Support..........................
Products .......................................................................
Document Number: 001-52038 Rev. *B
Page 2 of 19
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STK14C88
Pin Configurations
27
A9
7
26
A11
8
25
24
G
NC
(TOP)
9
10
23
A10
A1
A0
11
22
12
21
E
DQ7
DQ0
13
20
DQ1
DQ2
14
19
DQ6
DQ5
15
18
DQ4
VSS
16
17
DQ3
W
HSB
VCap
VCCx
A11
NC
A1
A0
DQ0
G
(TOP)
A2
NC
A10
E
DQ7
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NC
A2
A9
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6
DQ6
A5
A4
A3
A8
A4
A3
DQ5
5
A13
A5
es
A6
A6
DQ4
W
A13
A8
29
28
DQ3
4
A14
HSB
30
D
31
3
VSS
2
A12
A7
A7
A14
DQ2
VCC
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32
DQ1
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VCAP
Figure 2. Pin Diagram - 32-Pin 450 Mil LCC
A12
Figure 1. Pin Diagram - 32-Pin 300 Mil SOIC/CDIP
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Pin Descriptions
I/O
A14-A0
Input
DQ7-DQ0
I/O
E
Input
Chip Enable: The active low E input selects the device.
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E.
G
Input
HSB
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array.
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Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
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Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tristate.
Power Supply Power: 5.0V, +10%.
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VCC
Description
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Pin Name
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (optional connection).
VCAP
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile storage elements.
VSS
Power Supply Ground.
NC
No Connect
Unlabeled pins have no internal connections.
Document Number: 001-52038 Rev. *B
Page 3 of 19
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STK14C88
Absolute Maximum Ratings
Note Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Voltage on Input Relative to Ground.................–0.5V to 7.0V
Voltage on Input Relative to VSS ...........–0.6V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB ......................–0.5V to (VCC + 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Storage Temperature .................................... –65°C to 150°C
Power Dissipation............................................................. 1W
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DC Output Current (1 output at a time, 1s duration).... 15 mA
DC Characteristics
Min
Max
Average VCC Current during
STORE
3
ICC3[1]
Average VCC Current at tAVAV =
200 ns
5V, 25°C, Typical
10
ICC4[2]
Average VCAP Current during
AutoStore Cycle
ISB1[3]
Average VCC Current
(Standby, Cycling TTL Input
Levels)
ISB2[3]
Notes
100
85
70
mA
mA
mA
tAVAV = 25 ns
tAVAV = 35 ns
tAVAV = 45 ns
3
mA
All Inputs Don’t Care, VCC =
max
10
mA
W ≥ (V CC – 0.2V)
All Others Cycling, CMOS
Levels
2
2
mA
All Inputs Don’t Care
30
25
22
31
26
23
mA
mA
mA
tAVAV = 25 ns, E ≥ VIH
tAVAV = 35 ns, E ≥ VIH
tAVAV = 45 ns, E ≥ VIH
VCC Standby Current
(Standby, Stable CMOS Input
Levels)
1.5
1.5
mA
E ≥ (V CC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC
– 0.2V)
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off-State Output Leakage Current
±5
±5
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.2
VCC + 0.5
2.2
VCC +0.5
V
All Inputs
VIL
Input Logic “0” Voltage
VSS – .5
0.8
VSS – .5
0.8
V
All Inputs
V
IOUT = – 4 mA except HSB
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ICC2[2]
Unit
Max
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80
70
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Average VCC Current
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ICC1
[1]
Industrial/
Military
Commercial
Parameter
D
Symbol
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Over the operating range (VCC = 5.0V ± 10%)[4]
Output Logic “1” Voltage
2.4
2.4
VOL
Output Logic “0” Voltage
0.4
0.4
V
IOUT = 8 mA except HSB
VBL
Logic “0” Voltage on HSB Output
0.4
0.4
V
IOUT = 3 mA
TA
Operating Temperature
85/125
°C
0
70
-40/-55
Notes
1. ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
2. ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE).
3. E ≥ VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
4. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
Document Number: 001-52038 Rev. *B
Page 4 of 19
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STK14C88
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times ............................................
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