STK22C48-NF45ITR

STK22C48 16-Kbit (2 K × 8) AutoStore™ nvSRAM 16-Kbit (2 K × 8) AutoStore nvSRAM Features Functional Description 25 ns and 45 ns access times ■ Hands off automatic STORE on power-down with external 68 µF capacitor ■ STORE to QuantumTrap™ nonvolatile elements is initiated by software, hardware, or AutoStore™ on power-down ■ RECALL to SRAM initiated by software or power-up ■ Unlimited read, write, and RECALL cycles ■ 1,000,000 STORE cycles to QuantumTrap ■ 100 year data retention to QuantumTrap ■ Single 5 V +10% operation ■ Commercial and industrial temperatures ■ 28-pin 300 mil and (330 mil) Small outline integrated circuit (SOIC) package ■ Restriction of hazardous substances (RoHS) compliant The Cypress STK22C48 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. A hardware STORE is initiated with the HSB pin. In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n pr og r am s on ly . ■ Logic Block Diagram Quantum Trap 32 X 512 A5 A8 STATIC RAM ARRAY 32 X 512 RECALL VCAP POWER CONTROL STORE/ RECALL CONTROL HSB N A9 ROW DECODER A6 A7 STORE VCC DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 COLUMN I/O INPUT BUFFERS DQ 1 COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 DQ 7 OE CE WE Cypress Semiconductor Corporation Document Number: 001-51000 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 7, 2011 [+] Feedback STK22C48 Contents n pr og r am s on ly . AC Test Conditions .......................................................... 8 AC Switching Characteristics ......................................... 9 SRAM Read Cycle ...................................................... 9 Switching Waveforms ...................................................... 9 SRAM Write Cycle ..................................................... 10 AutoStore or Power Up RECALL .................................. 11 Switching Waveform ...................................................... 11 Hardware STORE Cycle ................................................. 12 Switching Waveform ...................................................... 12 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Document Conventions ................................................. 15 Acronyms ................................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io Pin Configurations ........................................................... 3 Device Operation .............................................................. 4 SRAM Read ....................................................................... 4 SRAM Write ....................................................................... 4 AutoStore Operation ........................................................ 4 AutoStore Inhibit mode .................................................... 4 Hardware STORE (HSB) Operation ................................. 5 Hardware RECALL (Power Up) ........................................ 5 Data Protection ................................................................. 5 Noise Considerations....................................................... 5 Hardware Protect.............................................................. 5 Low Average Active Power.............................................. 5 Preventing Store............................................................... 6 Best Practices................................................................... 6 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 DC Electrical Characteristics .......................................... 7 Data Retention and Endurance ....................................... 7 Capacitance ...................................................................... 8 Thermal Resistance .......................................................... 8 Document Number: 001-51000 Rev. *D Page 2 of 17 [+] Feedback STK22C48 Pin Configurations Figure 1. Pin Diagram - 28-pin SOIC NC 2 27 WE A7 3 26 HSB 25 A8 A6 4 A5 5 A4 6 A3 7 A2 8 24 A9 23 NC Top View 22 OE (Not To Scale) 21 A 10 28-SOIC A1 9 20 CE A0 10 19 DQ7 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 V SS 14 15 am DQ0 on ly 28 s 1 . V CC V CAP pr og r DQ4 Table 1. Pin Definitions Pin Name Alt A0–A10 N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n DQ3 IO Type Input DQ0–DQ7 Description Address inputs. Used to select one of the 2,048 bytes of the nvSRAM. Input or output Bidirectional data IO lines. Used as input or output lines depending on operation. WE W Input Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. CE E Input Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. VSS Ground Ground for the device. The device is connected to ground of the system. VCC Power supply Power supply inputs to the device. HSB Input or output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull-up resistor keeps this pin high if not connected (connection optional). VCAP Power supply AutoStore capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. NC No connect No connect. This pin is not connected to the die. Document Number: 001-51000 Rev. *D Page 3 of 17 [+] Feedback STK22C48 Device Operation SRAM Write N2KP :( +6% . on ly s am pr og r n io 9VV N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t The STK22C48 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0–10 determines the 2,048 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA (Read cycle 1). If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (Read cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. 9FF 5) %\SDVV SRAM Read 9&$3 5) Y The STK22C48 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK22C48 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. N2KP Figure 2. AutoStore Mode A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. In system power mode, both VCC and VCAP are connected to the +5 V power supply without the 68 μF capacitor. In this mode, the AutoStore function of the STK22C48 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6 V during the 10 ms STORE cycle. To prevent unneeded STORE operations, automatic STOREs and those initiated by externally driving HSB LOW are ignored, unless at least one WRITE operation takes place since the most recent STORE or RECALL cycle. An optional pull-up resistor is shown connected to HSB. This is used to signal the system that the AutoStore cycle is in progress. AutoStore Inhibit mode If an automatic STORE on power loss is not required, then VCC is tied to ground and +5 V is applied to VCAP (Figure 3 on page 5). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK22C48 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered with the HSB pin. It is not permissible to change between these three options “on the fly”. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor between 68 µF and 220 µF (+20%) rated at 6 V should be Document Number: 001-51000 Rev. *D Page 4 of 17 [+] Feedback STK22C48 Data Protection 9FF :( N2KP 9&$3 N2KP 5) %\SDVV Figure 3. AutoStore Inhibit Mode +6% The STK22C48 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the STK22C48 is in a Write mode (both CE and WE are low) at power-up after a RECALL or after a STORE, the Write is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power-up or brown out conditions. Noise Considerations am s Hardware Protect on ly . The STK22C48 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise. The STK22C48 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage conditions. When VCAP (VCC – 0.2 V). All other inputs cycling. tRC = 200 ns, 5 V, 25 °C typical Dependent on output loading and cycle rate. Values obtained without output loads. Average VCAP current during All inputs Do Not Care, VCC = Max AutoStore cycle Average current for duration tSTORE Average Vcc current tRC = 25 ns, CE > VIH Commercial tRC = 45 ns, CE > VIH (Standby, cycling TTL input levels) Industrial Max 85 65 90 65 Unit mA mA mA mA – 3 mA – 10 mA – 2 mA – – 25 18 26 19 1.5 mA mA mA mA mA –1 –5 +1 +5 μA μA ICC4 ISB1[4] n io ICC3 N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t ICC2 pr og r am s – ISB2[4] VCC standby current IILK IOLK Input leakage current Off state output leakage current Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Logic ‘0’ voltage on HSB output Storage capacitor VIH VIL VOH VOL VBL VCAP – CE > (VCC – 0.2 V). All others VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL IOUT = –4 mA except HSB IOUT = 8 mA except HSB IOUT = 3 mA Between VCAP pin and Vss, 6 V rated. 68 µF –10%, +20% nom. 2.2 VCC + 0.5 V VSS – 0.5 0.8 V 2.4 – V – 0.4 V – 0.4 V 61 220 µF Data Retention and Endurance Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 100 Years 1,000 K Notes 3. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 4. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out. Document Number: 001-51000 Rev. *D Page 7 of 17 [+] Feedback STK22C48 Capacitance In the following table, the capacitance parameters are listed.[5] Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 8 pF 7 pF 28-SOIC (300 mil) 28-SOIC (330 mil) Unit TBD TBD °C/W TBD TBD °C/W TA = 25 °C, f = 1 MHz, VCC = 0 to 3.0 V Thermal Resistance In the following table, the thermal resistance parameters are listed.[5] Description Thermal resistance (junction to ambient) ΘJC Thermal resistance (junction to case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. . ΘJA Test Conditions on ly Parameter am s Figure 6. AC Test Loads pr og r R1 963 Ω Output N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t Output 30 pF R2 512 Ω R1 963 Ω For Tri-state Specs n 5.0 V io 5.0 V 5 pF R2 512 Ω AC Test Conditions Input pulse levels.................................................... 0 V to 3 V Input rise and fall times (10% to 90%)......................... < 5 ns Input and output timing reference levels ....................... 1.5 V Note 5. These parameters are guaranteed by design and are not tested. Document Number: 001-51000 Rev. *D Page 8 of 17 [+] Feedback STK22C48 AC Switching Characteristics SRAM Read Cycle 25 ns Max Min Max – 25 – – 5 5 – 0 – 0 – 25 – 25 10 – – 10 – 10 – 25 – 45 – – 5 5 – 0 – 0 – 45 – 45 20 – – 15 – 15 – 45 . Min on ly Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Output disable to output inactive Chip enable to power active Chip disable to power standby Unit ns ns ns ns ns ns ns ns ns ns ns pr og r Switching Waveforms 45 ns s Description am Parameter Cypress Alt Parameter tELQV tACE [6] tAVAV, tELEH tRC tAVQV tAA [7] tGLQV tDOE [7] tAXQX tOHA tELQX tLZCE [8] tEHQZ tHZCE [8] tGLQX tLZOE [8] [8] tGHQZ tHZOE tPU [9] tELICCH tEHICCL tPD [9] $''5(66 N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t W5& io n Figure 7. SRAM Read Cycle 1: Address Controlled [6, 7] W $$ W2+$ '4'$7$287 '$7$9$/,' Figure 8. SRAM Read Cycle 2: CE and OE Controlled [6] W5& $''5(66 W$&( &( W3' W/=&( W+=&( 2( W+=2( W'2( W/=2( '4'$7$287 '$7$9$/,' W 38 ,&& $&7,9( 67$1'%< Notes 6. WE and HSB must be High during SRAM Read cycles. 7. Device is continuously selected with CE and OE both Low. 8. Measured ±200 mV from steady state output voltage. 9. These parameters are guaranteed by design and are not tested. Document Number: 001-51000 Rev. *D Page 9 of 17 [+] Feedback STK22C48 SRAM Write Cycle Parameter 25 ns Alt tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [10, 11] tLZWE [10] Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write 45 ns Min Max Min Max 25 20 20 10 0 20 0 0 – 5 – – – – – – – – 10 – 45 30 30 15 0 30 0 0 – 5 – – – – – – – – 14 – . Description Switching Waveforms ns ns ns ns ns ns ns ns ns ns am s Figure 9. SRAM Write Cycle 1: WE Controlled [12, 13] Unit on ly Cypress Parameter pr og r tWC N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io tSCE CE tHA n ADDRESS tAW tSA WE tPWE tSD DATA IN tHD DATA VALID tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 10. SRAM Write Cycle 2: CE Controlled [12, 13] tWC ADDRESS CE WE tHA tSCE tSA tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 10. Measured ±200 mV from steady state output voltage. 11. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 12. HSB must be high during SRAM Write cycles. 13. CE or WE must be greater than VIH during address transitions. Document Number: 001-51000 Rev. *D Page 10 of 17 [+] Feedback STK22C48 AutoStore or Power Up RECALL Parameter Alt tHRECALL [14] tSTORE [15, 16] tDELAY [17] VSWITCH VRESET tVSBL[18] tRESTORE tHLHZ tHLQZ , tBLQZ Description Power Up RECALL duration STORE cycle duration Time allowed to complete SRAM cycle Low voltage trigger level Low voltage reset level Low voltage trigger (VSWITCH) to HSB Low STK22C48 Min Max – 550 – 10 1 – 4.0 4.5 – 3.6 – 300 Unit μs ms μs V V ns Switching Waveform WE N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n pr og r am s on ly . Figure 11. AutoStore/Power Up RECALL Notes 14. tHRECALL starts from the time VCC rises above VSWITCH. 15. CE and OE low and WE high for output behavior. 16. HSB is asserted low for 1us when VCAP drops through VSWITCH. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store takes place. 17. CE and OE low for output behavior. 18. HSB must be high during SRAM Write cycles. Document Number: 001-51000 Rev. *D Page 11 of 17 [+] Feedback STK22C48 Hardware STORE Cycle Parameter Alt STK22C48 Description Unit Min Max 700 ns tDHSB [19, 20] tRECOVER, tHHQX Hardware STORE HIGH to inhibit off – tPHSB tHLHX Hardware STORE pulse width 15 – ns Hardware STORE LOW to STORE busy – 300 ns tHLBL Switching Waveform N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n pr og r am s on ly . Figure 12. Hardware STORE Cycle Notes 19. CE and OE low and WE high for output behavior. 20. tDHSB is only applicable after tSTORE is complete. Document Number: 001-51000 Rev. *D Page 12 of 17 [+] Feedback STK22C48 Ordering Code Definitions STK22C48 - N F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 °C to 70 °C) I - Industrial (-40 °C to 85 °C) Speed: 25 - 25 ns 45 - 45 ns Lead Finish on ly . F = 100% Sn (Matte Tin) N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n pr og r am s Package: N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 330 mil SOIC Ordering Information These parts are not recommended for new designs. They are in production to support ongoing production programs only. Speed (ns) 25 45 Ordering Code Package Diagram Package Type STK22C48-NF25ITR 51-85026 28-pin SOIC (300 mil) STK22C48-NF25I 51-85026 28-pin SOIC (300 mil) STK22C48-SF25ITR 51-85058 28-pin SOIC (330 mil) STK22C48-SF25I 51-85058 28-pin SOIC (330 mil) STK22C48-NF45TR 51-85026 28-pin SOIC (300 mil) STK22C48-NF45 51-85026 28-pin SOIC (300 mil) Operating Range Industrial Commercial All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts Document Number: 001-51000 Rev. *D Page 13 of 17 [+] Feedback STK22C48 Package Diagrams N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n pr og r am s on ly . Figure 13. 28-Pin (300 mil) SOIC (51-85026) 51-85026-*E 51-85026 *F Figure 14. 28-Pin (330 mil) SOIC (51-85058) 51-85058 *B 51-85058-*A Document Number: 001-51000 Rev. *D Page 14 of 17 [+] Feedback STK22C48 Document Conventions Acronyms Acronym CMOS Description Complementary metal oxide semiconductor EIA Electronic Industries Alliance I/O Input/output nvSRAM nonvolatile static random access memory RoHS Restriction of hazardous substances SOIC Small outline integrated circuit 1024 bits KΩ kilo ohms micro Amperes milli Amperes μF micro Farads MHz N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t μA mA s kbit am Hertz pr og r degree Celsius n °C Hz on ly Unit of Measure io Symbol . Units of Measure mega Hertz μs micro seconds ms milli seconds ns nano seconds pF pico Farads V Volts Ω ohms W Watts Document Number: 001-51000 Rev. *D Page 15 of 17 [+] Feedback STK22C48 Document History Page Document Title: STK22C48 16-Kbit (2 K × 8) AutoStore™ nvSRAM Document Number: 001-51000 Rev. ECN No. Orig. of Change Submission Date Description of Change 2625139 GVCH/PYRS 01/30/2009 New data sheet 2826441 GVCH 12/11/2009 Added following text in the Ordering Information section: “These parts are not recommended for new designs. In production to support ongoing production programs only.” Added watermark in PDF stating “Not recommended for new designs. In production to support ongoing production programs only.” Added Contents on page 2. *B 3037216 GVCH 09/23/2010 Added Pin Configurations and Pin Definitions table. Updated Package Diagrams. Added Acronyms and units Units of Measure table. Minor edits. *C 3054310 GVCH/KEER 10/11/2010 Removed inactive parts - STK22C48-NF25, STK22C48-NF25TR, STK22C48-SF25, STK22C48-SF25TR, STK22C48-SF45, STK22C48-SF45TR, STK22C48-NF45I, STK22C48-NF45ITR from Ordering information table. Updated Package diagrams. *D 3189527 GVCH 03/07/2011 Added watermark in PDF stating “Not recommended for new designs. In production to support ongoing production programs only.” N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n pr og r am s on ly . ** *A Document Number: 001-51000 Rev. *D Page 16 of 17 [+] Feedback STK22C48 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Touch Sensing USB Controllers . on ly cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless N In ot R pr e od co uc mm tio e n nd to e su d f pp or or Ne to w ng D oi es ng ig pr ns. od uc t io n Wireless/RF cypress.com/go/image s PSoC am Optical & Image Sensing cypress.com/go/memory pr og r Memory © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-51000 Rev. *D Revised March 7, 2011 Page 17 of 17 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback